From 416b6dcffa17f0df96620b1d4939f0ffc7d56ce4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 13 Nov 2020 16:11:20 +0000 Subject: [PATCH] update full core ls180 (actually with litex peripherals but not core) --- experiments9/non_generated/full_core_ls180.il | 528249 ++++----------- 1 file changed, 138606 insertions(+), 389643 deletions(-) diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index b2e8f45..35e0b91 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,313721 +1,4225 @@ # Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 14657 -attribute \src "libresoc.v:5.1-330.10" +autoidx 3721 +attribute \src "libresoc.v:5.1-277.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" +attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" attribute \generator "nMigen" -module \ALU_dec19 - attribute \src "libresoc.v:279.3-288.6" - wire width 3 $0\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:289.3-298.6" - wire width 3 $0\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:319.3-328.6" - wire width 2 $0\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:219.3-228.6" - wire $0\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:189.3-198.6" - wire width 12 $0\ALU_dec19_function_unit[11:0] - attribute \src "libresoc.v:259.3-268.6" - wire width 3 $0\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:269.3-278.6" - wire width 4 $0\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:249.3-258.6" - wire width 7 $0\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:199.3-208.6" - wire $0\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:209.3-218.6" - wire $0\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:229.3-238.6" - wire $0\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:299.3-308.6" - wire width 4 $0\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:309.3-318.6" - wire width 2 $0\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:239.3-248.6" - wire $0\ALU_dec19_sgn[0:0] +module \_fsm + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $0\fsm_state$next[3:0]$25 + attribute \src "libresoc.v:91.3-92.35" + wire width 4 $0\fsm_state[3:0] attribute \src "libresoc.v:6.7-6.20" wire $0\initial[0:0] - attribute \src "libresoc.v:279.3-288.6" - wire width 3 $1\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:289.3-298.6" - wire width 3 $1\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:319.3-328.6" - wire width 2 $1\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:219.3-228.6" - wire $1\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:189.3-198.6" - wire width 12 $1\ALU_dec19_function_unit[11:0] - attribute \src "libresoc.v:259.3-268.6" - wire width 3 $1\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:269.3-278.6" - wire width 4 $1\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:249.3-258.6" - wire width 7 $1\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:199.3-208.6" - wire $1\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:209.3-218.6" - wire $1\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:229.3-238.6" - wire $1\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:299.3-308.6" - wire width 4 $1\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:309.3-318.6" - wire width 2 $1\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:239.3-248.6" - wire $1\ALU_dec19_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \ALU_dec19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \ALU_dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_dec19_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \ALU_dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \ALU_dec19_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \ALU_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \ALU_dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \ALU_dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \ALU_dec19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \ALU_dec19_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \ALU_dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \ALU_dec19_sgn + attribute \src "libresoc.v:97.3-124.6" + wire $0\isdr$next[0:0]$21 + attribute \src "libresoc.v:93.3-94.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $0\isir$next[0:0]$38 + attribute \src "libresoc.v:95.3-96.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $10\fsm_state$next[3:0]$35 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $11\fsm_state$next[3:0]$36 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:46.13-46.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:97.3-124.6" + wire $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:51.7-51.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:240.3-267.6" + wire $1\isir$next[0:0]$39 + attribute \src "libresoc.v:56.7-56.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $2\fsm_state$next[3:0]$27 + attribute \src "libresoc.v:97.3-124.6" + wire $2\isdr$next[0:0]$23 + attribute \src "libresoc.v:240.3-267.6" + wire $2\isir$next[0:0]$40 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $3\fsm_state$next[3:0]$28 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $4\fsm_state$next[3:0]$29 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $5\fsm_state$next[3:0]$30 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $6\fsm_state$next[3:0]$31 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $7\fsm_state$next[3:0]$32 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $8\fsm_state$next[3:0]$33 + attribute \src "libresoc.v:125.3-239.6" + wire width 4 $9\fsm_state$next[3:0]$34 + attribute \src "libresoc.v:75.17-75.110" + wire $eq$libresoc.v:75$1_Y + attribute \src "libresoc.v:76.18-76.111" + wire $eq$libresoc.v:76$2_Y + attribute \src "libresoc.v:77.18-77.111" + wire $eq$libresoc.v:77$3_Y + attribute \src "libresoc.v:78.18-78.111" + wire $eq$libresoc.v:78$4_Y + attribute \src "libresoc.v:79.18-79.111" + wire $eq$libresoc.v:79$5_Y + attribute \src "libresoc.v:80.17-80.108" + wire $eq$libresoc.v:80$6_Y + attribute \src "libresoc.v:81.18-81.111" + wire $eq$libresoc.v:81$7_Y + attribute \src "libresoc.v:82.18-82.111" + wire $eq$libresoc.v:82$8_Y + attribute \src "libresoc.v:83.18-83.111" + wire $eq$libresoc.v:83$9_Y + attribute \src "libresoc.v:84.18-84.111" + wire $eq$libresoc.v:84$10_Y + attribute \src "libresoc.v:85.18-85.111" + wire $eq$libresoc.v:85$11_Y + attribute \src "libresoc.v:86.18-86.111" + wire $eq$libresoc.v:86$12_Y + attribute \src "libresoc.v:87.18-87.112" + wire $eq$libresoc.v:87$13_Y + attribute \src "libresoc.v:88.17-88.108" + wire $eq$libresoc.v:88$14_Y + attribute \src "libresoc.v:89.17-89.108" + wire $eq$libresoc.v:89$15_Y + attribute \src "libresoc.v:90.17-90.108" + wire $eq$libresoc.v:90$16_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state$next attribute \src "libresoc.v:6.7-6.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \src "libresoc.v:189.3-198.6" - process $proc$libresoc.v:189$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 11 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:75$1 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:75$1_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:76$2 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:76$2_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + cell $eq $eq$libresoc.v:77$3 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:77$3_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + cell $eq $eq$libresoc.v:78$4 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:78$4_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:79$5 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:79$5_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + cell $eq $eq$libresoc.v:80$6 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:80$6_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:81$7 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:81$7_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + cell $eq $eq$libresoc.v:82$8 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:82$8_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + cell $eq $eq$libresoc.v:83$9 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:83$9_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + cell $eq $eq$libresoc.v:84$10 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:84$10_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + cell $eq $eq$libresoc.v:85$11 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:85$11_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + cell $eq $eq$libresoc.v:86$12 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:86$12_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + cell $eq $eq$libresoc.v:87$13 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:87$13_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:88$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:88$14_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:89$15 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:89$15_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:90$16 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:90$16_Y + end + attribute \src "libresoc.v:125.3-239.6" + process $proc$libresoc.v:125$24 assign { } { } assign { } { } - assign $0\ALU_dec19_function_unit[11:0] $1\ALU_dec19_function_unit[11:0] - attribute \src "libresoc.v:190.5-190.29" + assign $0\fsm_state$next[3:0]$25 $1\fsm_state$next[3:0]$26 + attribute \src "libresoc.v:126.5-126.29" switch \initial - attribute \src "libresoc.v:190.9-190.17" + attribute \src "libresoc.v:126.9-126.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $2\fsm_state$next[3:0]$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$27 4'0001 + case + assign $2\fsm_state$next[3:0]$27 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $3\fsm_state$next[3:0]$28 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$28 4'0010 + case + assign $3\fsm_state$next[3:0]$28 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $4\fsm_state$next[3:0]$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$29 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $5\fsm_state$next[3:0]$30 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$30 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $6\fsm_state$next[3:0]$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$31 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $7\fsm_state$next[3:0]$32 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$32 4'0110 + case + assign $7\fsm_state$next[3:0]$32 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $8\fsm_state$next[3:0]$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$33 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $9\fsm_state$next[3:0]$34 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$34 4'1001 + case + assign $9\fsm_state$next[3:0]$34 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$26 $10\fsm_state$next[3:0]$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$35 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\ALU_dec19_function_unit[11:0] 12'000000000010 + assign $1\fsm_state$next[3:0]$26 $11\fsm_state$next[3:0]$36 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$36 4'0010 + end case - assign $1\ALU_dec19_function_unit[11:0] 12'000000000000 + assign $1\fsm_state$next[3:0]$26 \fsm_state end sync always - update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[11:0] + update \fsm_state$next $0\fsm_state$next[3:0]$25 end - attribute \src "libresoc.v:199.3-208.6" - process $proc$libresoc.v:199$2 + attribute \src "libresoc.v:240.3-267.6" + process $proc$libresoc.v:240$37 assign { } { } assign { } { } - assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] - attribute \src "libresoc.v:200.5-200.29" + assign $0\isir$next[0:0]$38 $1\isir$next[0:0]$39 + attribute \src "libresoc.v:241.5-241.29" switch \initial - attribute \src "libresoc.v:200.9-200.17" + attribute \src "libresoc.v:241.9-241.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$39 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$39 $2\isir$next[0:0]$40 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$40 1'1 + case + assign $2\isir$next[0:0]$40 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } - assign $1\ALU_dec19_inv_a[0:0] 1'0 + assign $1\isir$next[0:0]$39 1'0 case - assign $1\ALU_dec19_inv_a[0:0] 1'0 + assign $1\isir$next[0:0]$39 \isir end sync always - update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] + update \isir$next $0\isir$next[0:0]$38 end - attribute \src "libresoc.v:209.3-218.6" - process $proc$libresoc.v:209$3 + attribute \src "libresoc.v:46.13-46.29" + process $proc$libresoc.v:46$42 assign { } { } + assign $1\fsm_state[3:0] 4'0000 + sync always + sync init + update \fsm_state $1\fsm_state[3:0] + end + attribute \src "libresoc.v:51.7-51.18" + process $proc$libresoc.v:51$43 assign { } { } - assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] - attribute \src "libresoc.v:210.5-210.29" - switch \initial - attribute \src "libresoc.v:210.9-210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_inv_out[0:0] 1'0 - case - assign $1\ALU_dec19_inv_out[0:0] 1'0 - end + assign $1\isdr[0:0] 1'0 sync always - update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] + sync init + update \isdr $1\isdr[0:0] end - attribute \src "libresoc.v:219.3-228.6" - process $proc$libresoc.v:219$4 + attribute \src "libresoc.v:56.7-56.18" + process $proc$libresoc.v:56$44 assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$41 assign { } { } - assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] - attribute \src "libresoc.v:220.5-220.29" - switch \initial - attribute \src "libresoc.v:220.9-220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_cry_out[0:0] 1'0 - case - assign $1\ALU_dec19_cry_out[0:0] 1'0 - end + assign $0\initial[0:0] 1'0 sync always - update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:229.3-238.6" - process $proc$libresoc.v:229$5 + attribute \src "libresoc.v:91.3-92.35" + process $proc$libresoc.v:91$17 assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:93.3-94.25" + process $proc$libresoc.v:93$18 assign { } { } - assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] - attribute \src "libresoc.v:230.5-230.29" - switch \initial - attribute \src "libresoc.v:230.9-230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_is_32b[0:0] 1'0 - case - assign $1\ALU_dec19_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:95.3-96.25" + process $proc$libresoc.v:95$19 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] end - attribute \src "libresoc.v:239.3-248.6" - process $proc$libresoc.v:239$6 + attribute \src "libresoc.v:97.3-124.6" + process $proc$libresoc.v:97$20 assign { } { } assign { } { } - assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] - attribute \src "libresoc.v:240.5-240.29" + assign $0\isdr$next[0:0]$21 $1\isdr$next[0:0]$22 + attribute \src "libresoc.v:98.5-98.29" switch \initial - attribute \src "libresoc.v:240.9-240.17" + attribute \src "libresoc.v:98.9-98.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 4'0000 assign { } { } - assign $1\ALU_dec19_sgn[0:0] 1'0 - case - assign $1\ALU_dec19_sgn[0:0] 1'0 - end - sync always - update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$22 $2\isdr$next[0:0]$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$23 1'1 + case + assign $2\isdr$next[0:0]$23 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$22 1'0 + case + assign $1\isdr$next[0:0]$22 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$21 + end + connect \$9 $eq$libresoc.v:75$1_Y + connect \$11 $eq$libresoc.v:76$2_Y + connect \$13 $eq$libresoc.v:77$3_Y + connect \$15 $eq$libresoc.v:78$4_Y + connect \$17 $eq$libresoc.v:79$5_Y + connect \$1 $eq$libresoc.v:80$6_Y + connect \$19 $eq$libresoc.v:81$7_Y + connect \$21 $eq$libresoc.v:82$8_Y + connect \$23 $eq$libresoc.v:83$9_Y + connect \$25 $eq$libresoc.v:84$10_Y + connect \$27 $eq$libresoc.v:85$11_Y + connect \$29 $eq$libresoc.v:86$12_Y + connect \$31 $eq$libresoc.v:87$13_Y + connect \$3 $eq$libresoc.v:88$14_Y + connect \$5 $eq$libresoc.v:89$15_Y + connect \$7 $eq$libresoc.v:90$16_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:281.1-353.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:326.3-346.6" + wire width 32 $0\TAP_id_sr$next[31:0]$50 + attribute \src "libresoc.v:324.3-325.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:282.7-282.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:326.3-346.6" + wire width 32 $1\TAP_id_sr$next[31:0]$51 + attribute \src "libresoc.v:292.14-292.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:326.3-346.6" + wire width 32 $2\TAP_id_sr$next[31:0]$52 + attribute \src "libresoc.v:321.17-321.110" + wire $and$libresoc.v:321$45_Y + attribute \src "libresoc.v:322.17-322.108" + wire $and$libresoc.v:322$46_Y + attribute \src "libresoc.v:323.17-323.109" + wire $and$libresoc.v:323$47_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire input 1 \id_bypass + attribute \src "libresoc.v:282.7-282.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire input 9 \select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:321$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \capture + connect \Y $and$libresoc.v:321$45_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:322$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \shift + connect \Y $and$libresoc.v:322$46_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $and $and$libresoc.v:323$47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \update + connect \Y $and$libresoc.v:323$47_Y end - attribute \src "libresoc.v:249.3-258.6" - process $proc$libresoc.v:249$7 + attribute \src "libresoc.v:282.7-282.20" + process $proc$libresoc.v:282$53 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:292.14-292.31" + process $proc$libresoc.v:292$54 assign { } { } - assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] - attribute \src "libresoc.v:250.5-250.29" - switch \initial - attribute \src "libresoc.v:250.9-250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_internal_op[6:0] 7'0100100 - case - assign $1\ALU_dec19_internal_op[6:0] 7'0000000 - end + assign $1\TAP_id_sr[31:0] 0 sync always - update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:324.3-325.35" + process $proc$libresoc.v:324$48 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] end - attribute \src "libresoc.v:259.3-268.6" - process $proc$libresoc.v:259$8 + attribute \src "libresoc.v:326.3-346.6" + process $proc$libresoc.v:326$49 assign { } { } assign { } { } - assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] - attribute \src "libresoc.v:260.5-260.29" + assign $0\TAP_id_sr$next[31:0]$50 $1\TAP_id_sr$next[31:0]$51 + attribute \src "libresoc.v:327.5-327.29" switch \initial - attribute \src "libresoc.v:260.9-260.17" + attribute \src "libresoc.v:327.9-327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" + switch { \_shift \_capture } attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 2'-1 assign { } { } - assign $1\ALU_dec19_in1_sel[2:0] 3'000 + assign $1\TAP_id_sr$next[31:0]$51 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$51 $2\TAP_id_sr$next[31:0]$52 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$52 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$52 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$52 { \_tdi \TAP_id_sr [31:1] } + end case - assign $1\ALU_dec19_in1_sel[2:0] 3'000 + assign $1\TAP_id_sr$next[31:0]$51 \TAP_id_sr end sync always - update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$50 + end + connect \$1 $and$libresoc.v:321$45_Y + connect \$3 $and$libresoc.v:322$46_Y + connect \$5 $and$libresoc.v:323$47_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \id_bypass + connect \_update \$5 + connect \_shift \$3 + connect \_capture \$1 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:357.1-441.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:358.7-358.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:419.3-439.6" + wire width 4 $0\ir$next[3:0]$67 + attribute \src "libresoc.v:402.3-403.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:406.3-418.6" + wire width 4 $0\shift_ir$next[3:0]$64 + attribute \src "libresoc.v:404.3-405.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:419.3-439.6" + wire width 4 $1\ir$next[3:0]$68 + attribute \src "libresoc.v:377.13-377.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:406.3-418.6" + wire width 4 $1\shift_ir$next[3:0]$65 + attribute \src "libresoc.v:389.13-389.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:419.3-439.6" + wire width 4 $2\ir$next[3:0]$69 + attribute \src "libresoc.v:396.17-396.103" + wire $and$libresoc.v:396$55_Y + attribute \src "libresoc.v:397.18-397.105" + wire $and$libresoc.v:397$56_Y + attribute \src "libresoc.v:398.17-398.105" + wire $and$libresoc.v:398$57_Y + attribute \src "libresoc.v:399.17-399.103" + wire $and$libresoc.v:399$58_Y + attribute \src "libresoc.v:400.17-400.104" + wire $and$libresoc.v:400$59_Y + attribute \src "libresoc.v:401.17-401.105" + wire $and$libresoc.v:401$60_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 1 \capture + attribute \src "libresoc.v:358.7-358.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:396$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:396$55_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:397$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:397$56_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:398$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:398$57_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:399$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:399$58_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:400$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:400$59_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:401$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:401$60_Y + end + attribute \src "libresoc.v:358.7-358.20" + process $proc$libresoc.v:358$70 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:269.3-278.6" - process $proc$libresoc.v:269$9 + attribute \src "libresoc.v:377.13-377.22" + process $proc$libresoc.v:377$71 assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:389.13-389.28" + process $proc$libresoc.v:389$72 assign { } { } - assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] - attribute \src "libresoc.v:270.5-270.29" - switch \initial - attribute \src "libresoc.v:270.9-270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec19_in2_sel[3:0] 4'0000 - end + assign $1\shift_ir[3:0] 4'0000 sync always - update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] + sync init + update \shift_ir $1\shift_ir[3:0] + end + attribute \src "libresoc.v:402.3-403.21" + process $proc$libresoc.v:402$61 + assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] end - attribute \src "libresoc.v:279.3-288.6" - process $proc$libresoc.v:279$10 + attribute \src "libresoc.v:404.3-405.33" + process $proc$libresoc.v:404$62 assign { } { } + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] + end + attribute \src "libresoc.v:406.3-418.6" + process $proc$libresoc.v:406$63 assign { } { } - assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] - attribute \src "libresoc.v:280.5-280.29" + assign { } { } + assign $0\shift_ir$next[3:0]$64 $1\shift_ir$next[3:0]$65 + attribute \src "libresoc.v:407.5-407.29" switch \initial - attribute \src "libresoc.v:280.9-280.17" + attribute \src "libresoc.v:407.9-407.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$5 \$3 \$1 } attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$65 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- assign { } { } - assign $1\ALU_dec19_cr_in[2:0] 3'000 + assign $1\shift_ir$next[3:0]$65 { \TAP_bus__tdi \shift_ir [3:1] } case - assign $1\ALU_dec19_cr_in[2:0] 3'000 + assign $1\shift_ir$next[3:0]$65 \shift_ir end sync always - update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] + update \shift_ir$next $0\shift_ir$next[3:0]$64 end - attribute \src "libresoc.v:289.3-298.6" - process $proc$libresoc.v:289$11 + attribute \src "libresoc.v:419.3-439.6" + process $proc$libresoc.v:419$66 assign { } { } assign { } { } - assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] - attribute \src "libresoc.v:290.5-290.29" + assign { } { } + assign $0\ir$next[3:0]$67 $2\ir$next[3:0]$69 + attribute \src "libresoc.v:420.5-420.29" switch \initial - attribute \src "libresoc.v:290.9-290.17" + attribute \src "libresoc.v:420.9-420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$11 \$9 \$7 } attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 3'--1 + assign $1\ir$next[3:0]$68 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$68 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- assign { } { } - assign $1\ALU_dec19_cr_out[2:0] 3'000 - case - assign $1\ALU_dec19_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] - end - attribute \src "libresoc.v:299.3-308.6" - process $proc$libresoc.v:299$12 - assign { } { } - assign { } { } - assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] - attribute \src "libresoc.v:300.5-300.29" - switch \initial - attribute \src "libresoc.v:300.9-300.17" - case 1'1 + assign $1\ir$next[3:0]$68 \shift_ir case + assign $1\ir$next[3:0]$68 \ir end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 1'1 assign { } { } - assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + assign $2\ir$next[3:0]$69 4'0001 case - assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + assign $2\ir$next[3:0]$69 $1\ir$next[3:0]$68 end sync always - update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] + update \ir$next $0\ir$next[3:0]$67 + end + connect \$9 $and$libresoc.v:396$55_Y + connect \$11 $and$libresoc.v:397$56_Y + connect \$1 $and$libresoc.v:398$57_Y + connect \$3 $and$libresoc.v:399$58_Y + connect \$5 $and$libresoc.v:400$59_Y + connect \$7 $and$libresoc.v:401$60_Y + connect \tdo \ir [0] +end +attribute \src "libresoc.v:445.1-469.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core" +attribute \generator "nMigen" +module \core + attribute \src "libresoc.v:446.7-446.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:460.3-468.6" + wire $0\x$next[0:0]$76 + attribute \src "libresoc.v:458.3-459.19" + wire $0\x[0:0] + attribute \src "libresoc.v:460.3-468.6" + wire $1\x$next[0:0]$77 + attribute \src "libresoc.v:454.7-454.15" + wire $1\x[0:0] + attribute \src "libresoc.v:457.17-457.89" + wire $not$libresoc.v:457$73_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 2 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire input 1 \coresync_rst + attribute \src "libresoc.v:446.7-446.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125" + wire \x + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:125" + wire \x$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:126" + cell $not $not$libresoc.v:457$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x + connect \Y $not$libresoc.v:457$73_Y end - attribute \src "libresoc.v:309.3-318.6" - process $proc$libresoc.v:309$13 + attribute \src "libresoc.v:446.7-446.20" + process $proc$libresoc.v:446$78 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:454.7-454.15" + process $proc$libresoc.v:454$79 assign { } { } - assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] - attribute \src "libresoc.v:310.5-310.29" - switch \initial - attribute \src "libresoc.v:310.9-310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\ALU_dec19_rc_sel[1:0] 2'00 - case - assign $1\ALU_dec19_rc_sel[1:0] 2'00 - end + assign $1\x[0:0] 1'0 sync always - update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] + sync init + update \x $1\x[0:0] + end + attribute \src "libresoc.v:458.3-459.19" + process $proc$libresoc.v:458$74 + assign { } { } + assign $0\x[0:0] \x$next + sync posedge \coresync_clk + update \x $0\x[0:0] end - attribute \src "libresoc.v:319.3-328.6" - process $proc$libresoc.v:319$14 + attribute \src "libresoc.v:460.3-468.6" + process $proc$libresoc.v:460$75 assign { } { } assign { } { } - assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] - attribute \src "libresoc.v:320.5-320.29" + assign $0\x$next[0:0]$76 $1\x$next[0:0]$77 + attribute \src "libresoc.v:461.5-461.29" switch \initial - attribute \src "libresoc.v:320.9-320.17" + attribute \src "libresoc.v:461.9-461.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 + case 1'1 assign { } { } - assign $1\ALU_dec19_cry_in[1:0] 2'00 + assign $1\x$next[0:0]$77 1'0 case - assign $1\ALU_dec19_cry_in[1:0] 2'00 + assign $1\x$next[0:0]$77 \$1 end sync always - update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] - end - attribute \src "libresoc.v:6.7-6.20" - process $proc$libresoc.v:6$15 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \x$next $0\x$next[0:0]$76 end - connect \opcode_switch \opcode_in [10:1] + connect \$1 $not$libresoc.v:457$73_Y end -attribute \src "libresoc.v:334.1-1750.10" +attribute \src "libresoc.v:473.1-1187.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" +attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" -module \ALU_dec31 - attribute \src "libresoc.v:1457.3-1478.6" - wire width 3 $0\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1479.3-1500.6" - wire width 3 $0\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1545.3-1566.6" - wire width 2 $0\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1611.3-1632.6" - wire $0\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1677.3-1698.6" - wire width 12 $0\ALU_dec31_function_unit[11:0] - attribute \src "libresoc.v:1721.3-1742.6" - wire width 3 $0\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1435.3-1456.6" - wire width 4 $0\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1699.3-1720.6" - wire width 7 $0\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1567.3-1588.6" - wire $0\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1589.3-1610.6" - wire $0\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1633.3-1654.6" - wire $0\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1501.3-1522.6" - wire width 4 $0\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1523.3-1544.6" - wire width 2 $0\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1655.3-1676.6" - wire $0\ALU_dec31_sgn[0:0] - attribute \src "libresoc.v:335.7-335.20" +module \dbg + attribute \src "libresoc.v:1003.3-1012.6" + wire $0\d_cr_req[0:0] + attribute \src "libresoc.v:810.3-819.6" + wire $0\d_gpr_req[0:0] + attribute \src "libresoc.v:1013.3-1022.6" + wire $0\d_xer_req[0:0] + attribute \src "libresoc.v:792.3-809.6" + wire $0\dmi_ack_o[0:0] + attribute \src "libresoc.v:1023.3-1053.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "libresoc.v:994.3-1002.6" + wire $0\dmi_read_log_data$next[0:0]$193 + attribute \src "libresoc.v:770.3-771.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "libresoc.v:985.3-993.6" + wire $0\dmi_read_log_data_1$next[0:0]$190 + attribute \src "libresoc.v:772.3-773.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:820.3-828.6" + wire $0\dmi_req_i_1$next[0:0]$156 + attribute \src "libresoc.v:782.3-783.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "libresoc.v:1144.3-1177.6" + wire $0\do_dmi_log_rd$next[0:0]$220 + attribute \src "libresoc.v:784.3-785.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:1114.3-1143.6" + wire $0\do_icreset$next[0:0]$213 + attribute \src "libresoc.v:786.3-787.37" + wire $0\do_icreset[0:0] + attribute \src "libresoc.v:1084.3-1113.6" + wire $0\do_reset$next[0:0]$206 + attribute \src "libresoc.v:788.3-789.33" + wire $0\do_reset[0:0] + attribute \src "libresoc.v:1054.3-1083.6" + wire $0\do_step$next[0:0]$199 + attribute \src "libresoc.v:790.3-791.31" + wire $0\do_step[0:0] + attribute \src "libresoc.v:923.3-950.6" + wire width 7 $0\gspr_index$next[6:0]$178 + attribute \src "libresoc.v:776.3-777.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "libresoc.v:474.7-474.20" wire $0\initial[0:0] - attribute \src "libresoc.v:1457.3-1478.6" - wire width 3 $1\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1479.3-1500.6" - wire width 3 $1\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1545.3-1566.6" - wire width 2 $1\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1611.3-1632.6" - wire $1\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1677.3-1698.6" - wire width 12 $1\ALU_dec31_function_unit[11:0] - attribute \src "libresoc.v:1721.3-1742.6" - wire width 3 $1\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1435.3-1456.6" - wire width 4 $1\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1699.3-1720.6" - wire width 7 $1\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1567.3-1588.6" - wire $1\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1589.3-1610.6" - wire $1\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1633.3-1654.6" - wire $1\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1501.3-1522.6" - wire width 4 $1\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1523.3-1544.6" - wire width 2 $1\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1655.3-1676.6" - wire $1\ALU_dec31_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \ALU_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \ALU_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_dec31_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \ALU_dec31_sgn - attribute \src "libresoc.v:335.7-335.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:1350.22-1366.4" - cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 - connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in - connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out - connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out - connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit - connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel - connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel - connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b - connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len - connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - connect \opcode_in \ALU_dec31_dec_sub0_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:1367.23-1383.4" - cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 - connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in - connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out - connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out - connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit - connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel - connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel - connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b - connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len - connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - connect \opcode_in \ALU_dec31_dec_sub10_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:1384.23-1400.4" - cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 - connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in - connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out - connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out - connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit - connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel - connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel - connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b - connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len - connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - connect \opcode_in \ALU_dec31_dec_sub22_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:1401.23-1417.4" - cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 - connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in - connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out - connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out - connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit - connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel - connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel - connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b - connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len - connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - connect \opcode_in \ALU_dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:1418.22-1434.4" - cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 - connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in - connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out - connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out - connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit - connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel - connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel - connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op - connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b - connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len - connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn - connect \opcode_in \ALU_dec31_dec_sub8_opcode_in - end - attribute \src "libresoc.v:1435.3-1456.6" - process $proc$libresoc.v:1435$16 - assign { } { } - assign { } { } - assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] - attribute \src "libresoc.v:1436.5-1436.29" - switch \initial - attribute \src "libresoc.v:1436.9-1436.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel - case - assign $1\ALU_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:1457.3-1478.6" - process $proc$libresoc.v:1457$17 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] - attribute \src "libresoc.v:1458.5-1458.29" - switch \initial - attribute \src "libresoc.v:1458.9-1458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in - case - assign $1\ALU_dec31_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:1479.3-1500.6" - process $proc$libresoc.v:1479$18 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] - attribute \src "libresoc.v:1480.5-1480.29" - switch \initial - attribute \src "libresoc.v:1480.9-1480.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out - case - assign $1\ALU_dec31_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] - end - attribute \src "libresoc.v:1501.3-1522.6" - process $proc$libresoc.v:1501$19 - assign { } { } - assign { } { } - assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] - attribute \src "libresoc.v:1502.5-1502.29" - switch \initial - attribute \src "libresoc.v:1502.9-1502.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len - case - assign $1\ALU_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] - end - attribute \src "libresoc.v:1523.3-1544.6" - process $proc$libresoc.v:1523$20 - assign { } { } - assign { } { } - assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] - attribute \src "libresoc.v:1524.5-1524.29" - switch \initial - attribute \src "libresoc.v:1524.9-1524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel - case - assign $1\ALU_dec31_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:1545.3-1566.6" - process $proc$libresoc.v:1545$21 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] - attribute \src "libresoc.v:1546.5-1546.29" - switch \initial - attribute \src "libresoc.v:1546.9-1546.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in - case - assign $1\ALU_dec31_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] - end - attribute \src "libresoc.v:1567.3-1588.6" - process $proc$libresoc.v:1567$22 - assign { } { } - assign { } { } - assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] - attribute \src "libresoc.v:1568.5-1568.29" - switch \initial - attribute \src "libresoc.v:1568.9-1568.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a - case - assign $1\ALU_dec31_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] - end - attribute \src "libresoc.v:1589.3-1610.6" - process $proc$libresoc.v:1589$23 - assign { } { } - assign { } { } - assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] - attribute \src "libresoc.v:1590.5-1590.29" - switch \initial - attribute \src "libresoc.v:1590.9-1590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out - case - assign $1\ALU_dec31_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] - end - attribute \src "libresoc.v:1611.3-1632.6" - process $proc$libresoc.v:1611$24 - assign { } { } - assign { } { } - assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] - attribute \src "libresoc.v:1612.5-1612.29" - switch \initial - attribute \src "libresoc.v:1612.9-1612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out - case - assign $1\ALU_dec31_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] - end - attribute \src "libresoc.v:1633.3-1654.6" - process $proc$libresoc.v:1633$25 - assign { } { } - assign { } { } - assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] - attribute \src "libresoc.v:1634.5-1634.29" - switch \initial - attribute \src "libresoc.v:1634.9-1634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b - case - assign $1\ALU_dec31_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] - end - attribute \src "libresoc.v:1655.3-1676.6" - process $proc$libresoc.v:1655$26 - assign { } { } - assign { } { } - assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] - attribute \src "libresoc.v:1656.5-1656.29" - switch \initial - attribute \src "libresoc.v:1656.9-1656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn - case - assign $1\ALU_dec31_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] - end - attribute \src "libresoc.v:1677.3-1698.6" - process $proc$libresoc.v:1677$27 - assign { } { } - assign { } { } - assign $0\ALU_dec31_function_unit[11:0] $1\ALU_dec31_function_unit[11:0] - attribute \src "libresoc.v:1678.5-1678.29" - switch \initial - attribute \src "libresoc.v:1678.9-1678.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit - case - assign $1\ALU_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[11:0] - end - attribute \src "libresoc.v:1699.3-1720.6" - process $proc$libresoc.v:1699$28 - assign { } { } - assign { } { } - assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] - attribute \src "libresoc.v:1700.5-1700.29" - switch \initial - attribute \src "libresoc.v:1700.9-1700.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op - case - assign $1\ALU_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:1721.3-1742.6" - process $proc$libresoc.v:1721$29 - assign { } { } - assign { } { } - assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] - attribute \src "libresoc.v:1722.5-1722.29" - switch \initial - attribute \src "libresoc.v:1722.9-1722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel - case - assign $1\ALU_dec31_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] - end - attribute \src "libresoc.v:335.7-335.20" - process $proc$libresoc.v:335$30 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - connect \ALU_dec31_dec_sub8_opcode_in \opcode_in - connect \ALU_dec31_dec_sub22_opcode_in \opcode_in - connect \ALU_dec31_dec_sub26_opcode_in \opcode_in - connect \ALU_dec31_dec_sub0_opcode_in \opcode_in - connect \ALU_dec31_dec_sub10_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:1754.1-2163.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub0 - attribute \src "libresoc.v:2082.3-2097.6" - wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:2098.3-2113.6" - wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2146.3-2161.6" - wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:1986.3-2001.6" - wire $0\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1938.3-1953.6" - wire width 12 $0\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:2050.3-2065.6" - wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:2066.3-2081.6" - wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2034.3-2049.6" - wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:1954.3-1969.6" - wire $0\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:1970.3-1985.6" - wire $0\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:2002.3-2017.6" - wire $0\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2114.3-2129.6" - wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:2130.3-2145.6" - wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2018.3-2033.6" - wire $0\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:1755.7-1755.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:2082.3-2097.6" - wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:2098.3-2113.6" - wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2146.3-2161.6" - wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:1986.3-2001.6" - wire $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1938.3-1953.6" - wire width 12 $1\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:2050.3-2065.6" - wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:2066.3-2081.6" - wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2034.3-2049.6" - wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:1954.3-1969.6" - wire $1\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:1970.3-1985.6" - wire $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:2002.3-2017.6" - wire $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2114.3-2129.6" - wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:2130.3-2145.6" - wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2018.3-2033.6" - wire $1\ALU_dec31_dec_sub0_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_dec31_dec_sub0_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \ALU_dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \ALU_dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \ALU_dec31_dec_sub0_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \ALU_dec31_dec_sub0_sgn - attribute \src "libresoc.v:1755.7-1755.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:1755.7-1755.20" - process $proc$libresoc.v:1755$45 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:1938.3-1953.6" - process $proc$libresoc.v:1938$31 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_function_unit[11:0] $1\ALU_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:1939.5-1939.29" - switch \initial - attribute \src "libresoc.v:1939.9-1939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[11:0] - end - attribute \src "libresoc.v:1954.3-1969.6" - process $proc$libresoc.v:1954$32 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:1955.5-1955.29" - switch \initial - attribute \src "libresoc.v:1955.9-1955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 - case - assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] - end - attribute \src "libresoc.v:1970.3-1985.6" - process $proc$libresoc.v:1970$33 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:1971.5-1971.29" - switch \initial - attribute \src "libresoc.v:1971.9-1971.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] - end - attribute \src "libresoc.v:1986.3-2001.6" - process $proc$libresoc.v:1986$34 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:1987.5-1987.29" - switch \initial - attribute \src "libresoc.v:1987.9-1987.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] - end - attribute \src "libresoc.v:2002.3-2017.6" - process $proc$libresoc.v:2002$35 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:2003.5-2003.29" - switch \initial - attribute \src "libresoc.v:2003.9-2003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] - end - attribute \src "libresoc.v:2018.3-2033.6" - process $proc$libresoc.v:2018$36 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:2019.5-2019.29" - switch \initial - attribute \src "libresoc.v:2019.9-2019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] - end - attribute \src "libresoc.v:2034.3-2049.6" - process $proc$libresoc.v:2034$37 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:2035.5-2035.29" - switch \initial - attribute \src "libresoc.v:2035.9-2035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 - case - assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] - end - attribute \src "libresoc.v:2050.3-2065.6" - process $proc$libresoc.v:2050$38 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:2051.5-2051.29" - switch \initial - attribute \src "libresoc.v:2051.9-2051.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] - end - attribute \src "libresoc.v:2066.3-2081.6" - process $proc$libresoc.v:2066$39 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:2067.5-2067.29" - switch \initial - attribute \src "libresoc.v:2067.9-2067.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 - case - assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] - end - attribute \src "libresoc.v:2082.3-2097.6" - process $proc$libresoc.v:2082$40 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:2083.5-2083.29" - switch \initial - attribute \src "libresoc.v:2083.9-2083.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] - end - attribute \src "libresoc.v:2098.3-2113.6" - process $proc$libresoc.v:2098$41 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:2099.5-2099.29" - switch \initial - attribute \src "libresoc.v:2099.9-2099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 - case - assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] - end - attribute \src "libresoc.v:2114.3-2129.6" - process $proc$libresoc.v:2114$42 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:2115.5-2115.29" - switch \initial - attribute \src "libresoc.v:2115.9-2115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] - end - attribute \src "libresoc.v:2130.3-2145.6" - process $proc$libresoc.v:2130$43 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:2131.5-2131.29" - switch \initial - attribute \src "libresoc.v:2131.9-2131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 - case - assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] - end - attribute \src "libresoc.v:2146.3-2161.6" - process $proc$libresoc.v:2146$44 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:2147.5-2147.29" - switch \initial - attribute \src "libresoc.v:2147.9-2147.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 - case - assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:2167.1-2870.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub10 - attribute \src "libresoc.v:2684.3-2720.6" - wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2721.3-2757.6" - wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2832.3-2868.6" - wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2462.3-2498.6" - wire $0\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2351.3-2387.6" - wire width 12 $0\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:2610.3-2646.6" - wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2647.3-2683.6" - wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2573.3-2609.6" - wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2388.3-2424.6" - wire $0\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2425.3-2461.6" - wire $0\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2499.3-2535.6" - wire $0\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2758.3-2794.6" - wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2795.3-2831.6" - wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2536.3-2572.6" - wire $0\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:2168.7-2168.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:2684.3-2720.6" - wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2721.3-2757.6" - wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2832.3-2868.6" - wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2462.3-2498.6" - wire $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2351.3-2387.6" - wire width 12 $1\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:2610.3-2646.6" - wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2647.3-2683.6" - wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2573.3-2609.6" - wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2388.3-2424.6" - wire $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2425.3-2461.6" - wire $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2499.3-2535.6" - wire $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2758.3-2794.6" - wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2795.3-2831.6" - wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2536.3-2572.6" - wire $1\ALU_dec31_dec_sub10_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_dec31_dec_sub10_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub10_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \ALU_dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \ALU_dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \ALU_dec31_dec_sub10_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \ALU_dec31_dec_sub10_sgn - attribute \src "libresoc.v:2168.7-2168.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:2168.7-2168.20" - process $proc$libresoc.v:2168$60 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:2351.3-2387.6" - process $proc$libresoc.v:2351$46 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_function_unit[11:0] $1\ALU_dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:2352.5-2352.29" - switch \initial - attribute \src "libresoc.v:2352.9-2352.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[11:0] - end - attribute \src "libresoc.v:2388.3-2424.6" - process $proc$libresoc.v:2388$47 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:2389.5-2389.29" - switch \initial - attribute \src "libresoc.v:2389.9-2389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] - end - attribute \src "libresoc.v:2425.3-2461.6" - process $proc$libresoc.v:2425$48 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:2426.5-2426.29" - switch \initial - attribute \src "libresoc.v:2426.9-2426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] - end - attribute \src "libresoc.v:2462.3-2498.6" - process $proc$libresoc.v:2462$49 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:2463.5-2463.29" - switch \initial - attribute \src "libresoc.v:2463.9-2463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 - case - assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] - end - attribute \src "libresoc.v:2499.3-2535.6" - process $proc$libresoc.v:2499$50 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:2500.5-2500.29" - switch \initial - attribute \src "libresoc.v:2500.9-2500.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] - end - attribute \src "libresoc.v:2536.3-2572.6" - process $proc$libresoc.v:2536$51 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:2537.5-2537.29" - switch \initial - attribute \src "libresoc.v:2537.9-2537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] - end - attribute \src "libresoc.v:2573.3-2609.6" - process $proc$libresoc.v:2573$52 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:2574.5-2574.29" - switch \initial - attribute \src "libresoc.v:2574.9-2574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 - case - assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] - end - attribute \src "libresoc.v:2610.3-2646.6" - process $proc$libresoc.v:2610$53 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:2611.5-2611.29" - switch \initial - attribute \src "libresoc.v:2611.9-2611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] - end - attribute \src "libresoc.v:2647.3-2683.6" - process $proc$libresoc.v:2647$54 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:2648.5-2648.29" - switch \initial - attribute \src "libresoc.v:2648.9-2648.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] - end - attribute \src "libresoc.v:2684.3-2720.6" - process $proc$libresoc.v:2684$55 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:2685.5-2685.29" - switch \initial - attribute \src "libresoc.v:2685.9-2685.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] - end - attribute \src "libresoc.v:2721.3-2757.6" - process $proc$libresoc.v:2721$56 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:2722.5-2722.29" - switch \initial - attribute \src "libresoc.v:2722.9-2722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] - end - attribute \src "libresoc.v:2758.3-2794.6" - process $proc$libresoc.v:2758$57 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:2759.5-2759.29" - switch \initial - attribute \src "libresoc.v:2759.9-2759.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] - end - attribute \src "libresoc.v:2795.3-2831.6" - process $proc$libresoc.v:2795$58 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:2796.5-2796.29" - switch \initial - attribute \src "libresoc.v:2796.9-2796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] - end - attribute \src "libresoc.v:2832.3-2868.6" - process $proc$libresoc.v:2832$59 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:2833.5-2833.29" - switch \initial - attribute \src "libresoc.v:2833.9-2833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:2874.1-3451.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub22 - attribute \src "libresoc.v:3310.3-3337.6" - wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3338.3-3365.6" - wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3422.3-3449.6" - wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3142.3-3169.6" - wire $0\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3058.3-3085.6" - wire width 12 $0\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:3254.3-3281.6" - wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3282.3-3309.6" - wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3226.3-3253.6" - wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3086.3-3113.6" - wire $0\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3114.3-3141.6" - wire $0\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3170.3-3197.6" - wire $0\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3366.3-3393.6" - wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3394.3-3421.6" - wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3198.3-3225.6" - wire $0\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:2875.7-2875.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:3310.3-3337.6" - wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3338.3-3365.6" - wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3422.3-3449.6" - wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3142.3-3169.6" - wire $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3058.3-3085.6" - wire width 12 $1\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:3254.3-3281.6" - wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3282.3-3309.6" - wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3226.3-3253.6" - wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3086.3-3113.6" - wire $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3114.3-3141.6" - wire $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3170.3-3197.6" - wire $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3366.3-3393.6" - wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3394.3-3421.6" - wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3198.3-3225.6" - wire $1\ALU_dec31_dec_sub22_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_dec31_dec_sub22_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \ALU_dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \ALU_dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \ALU_dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \ALU_dec31_dec_sub22_sgn - attribute \src "libresoc.v:2875.7-2875.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:2875.7-2875.20" - process $proc$libresoc.v:2875$75 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:3058.3-3085.6" - process $proc$libresoc.v:3058$61 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_function_unit[11:0] $1\ALU_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:3059.5-3059.29" - switch \initial - attribute \src "libresoc.v:3059.9-3059.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[11:0] - end - attribute \src "libresoc.v:3086.3-3113.6" - process $proc$libresoc.v:3086$62 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:3087.5-3087.29" - switch \initial - attribute \src "libresoc.v:3087.9-3087.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] - end - attribute \src "libresoc.v:3114.3-3141.6" - process $proc$libresoc.v:3114$63 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:3115.5-3115.29" - switch \initial - attribute \src "libresoc.v:3115.9-3115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] - end - attribute \src "libresoc.v:3142.3-3169.6" - process $proc$libresoc.v:3142$64 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:3143.5-3143.29" - switch \initial - attribute \src "libresoc.v:3143.9-3143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] - end - attribute \src "libresoc.v:3170.3-3197.6" - process $proc$libresoc.v:3170$65 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:3171.5-3171.29" - switch \initial - attribute \src "libresoc.v:3171.9-3171.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] - end - attribute \src "libresoc.v:3198.3-3225.6" - process $proc$libresoc.v:3198$66 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:3199.5-3199.29" - switch \initial - attribute \src "libresoc.v:3199.9-3199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] - end - attribute \src "libresoc.v:3226.3-3253.6" - process $proc$libresoc.v:3226$67 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:3227.5-3227.29" - switch \initial - attribute \src "libresoc.v:3227.9-3227.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 - case - assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] - end - attribute \src "libresoc.v:3254.3-3281.6" - process $proc$libresoc.v:3254$68 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:3255.5-3255.29" - switch \initial - attribute \src "libresoc.v:3255.9-3255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] - end - attribute \src "libresoc.v:3282.3-3309.6" - process $proc$libresoc.v:3282$69 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:3283.5-3283.29" - switch \initial - attribute \src "libresoc.v:3283.9-3283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] - end - attribute \src "libresoc.v:3310.3-3337.6" - process $proc$libresoc.v:3310$70 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:3311.5-3311.29" - switch \initial - attribute \src "libresoc.v:3311.9-3311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] - end - attribute \src "libresoc.v:3338.3-3365.6" - process $proc$libresoc.v:3338$71 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:3339.5-3339.29" - switch \initial - attribute \src "libresoc.v:3339.9-3339.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] - end - attribute \src "libresoc.v:3366.3-3393.6" - process $proc$libresoc.v:3366$72 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:3367.5-3367.29" - switch \initial - attribute \src "libresoc.v:3367.9-3367.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] - end - attribute \src "libresoc.v:3394.3-3421.6" - process $proc$libresoc.v:3394$73 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:3395.5-3395.29" - switch \initial - attribute \src "libresoc.v:3395.9-3395.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] - end - attribute \src "libresoc.v:3422.3-3449.6" - process $proc$libresoc.v:3422$74 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:3423.5-3423.29" - switch \initial - attribute \src "libresoc.v:3423.9-3423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - case - assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:3455.1-3864.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub26 - attribute \src "libresoc.v:3783.3-3798.6" - wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3799.3-3814.6" - wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3847.3-3862.6" - wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3687.3-3702.6" - wire $0\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3639.3-3654.6" - wire width 12 $0\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:3751.3-3766.6" - wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3767.3-3782.6" - wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3735.3-3750.6" - wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3655.3-3670.6" - wire $0\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3671.3-3686.6" - wire $0\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3703.3-3718.6" - wire $0\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3815.3-3830.6" - wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3831.3-3846.6" - wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3719.3-3734.6" - wire $0\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:3456.7-3456.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:3783.3-3798.6" - wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3799.3-3814.6" - wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3847.3-3862.6" - wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3687.3-3702.6" - wire $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3639.3-3654.6" - wire width 12 $1\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:3751.3-3766.6" - wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3767.3-3782.6" - wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3735.3-3750.6" - wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3655.3-3670.6" - wire $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3671.3-3686.6" - wire $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3703.3-3718.6" - wire $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3815.3-3830.6" - wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3831.3-3846.6" - wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3719.3-3734.6" - wire $1\ALU_dec31_dec_sub26_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_dec31_dec_sub26_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \ALU_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \ALU_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \ALU_dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \ALU_dec31_dec_sub26_sgn - attribute \src "libresoc.v:3456.7-3456.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:3456.7-3456.20" - process $proc$libresoc.v:3456$90 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:3639.3-3654.6" - process $proc$libresoc.v:3639$76 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_function_unit[11:0] $1\ALU_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:3640.5-3640.29" - switch \initial - attribute \src "libresoc.v:3640.9-3640.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[11:0] - end - attribute \src "libresoc.v:3655.3-3670.6" - process $proc$libresoc.v:3655$77 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:3656.5-3656.29" - switch \initial - attribute \src "libresoc.v:3656.9-3656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] - end - attribute \src "libresoc.v:3671.3-3686.6" - process $proc$libresoc.v:3671$78 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:3672.5-3672.29" - switch \initial - attribute \src "libresoc.v:3672.9-3672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] - end - attribute \src "libresoc.v:3687.3-3702.6" - process $proc$libresoc.v:3687$79 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:3688.5-3688.29" - switch \initial - attribute \src "libresoc.v:3688.9-3688.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] - end - attribute \src "libresoc.v:3703.3-3718.6" - process $proc$libresoc.v:3703$80 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:3704.5-3704.29" - switch \initial - attribute \src "libresoc.v:3704.9-3704.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] - end - attribute \src "libresoc.v:3719.3-3734.6" - process $proc$libresoc.v:3719$81 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:3720.5-3720.29" - switch \initial - attribute \src "libresoc.v:3720.9-3720.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] - end - attribute \src "libresoc.v:3735.3-3750.6" - process $proc$libresoc.v:3735$82 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:3736.5-3736.29" - switch \initial - attribute \src "libresoc.v:3736.9-3736.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 - case - assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] - end - attribute \src "libresoc.v:3751.3-3766.6" - process $proc$libresoc.v:3751$83 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:3752.5-3752.29" - switch \initial - attribute \src "libresoc.v:3752.9-3752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 - case - assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] - end - attribute \src "libresoc.v:3767.3-3782.6" - process $proc$libresoc.v:3767$84 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:3768.5-3768.29" - switch \initial - attribute \src "libresoc.v:3768.9-3768.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "libresoc.v:3783.3-3798.6" - process $proc$libresoc.v:3783$85 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:3784.5-3784.29" - switch \initial - attribute \src "libresoc.v:3784.9-3784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] - end - attribute \src "libresoc.v:3799.3-3814.6" - process $proc$libresoc.v:3799$86 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:3800.5-3800.29" - switch \initial - attribute \src "libresoc.v:3800.9-3800.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] - end - attribute \src "libresoc.v:3815.3-3830.6" - process $proc$libresoc.v:3815$87 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:3816.5-3816.29" - switch \initial - attribute \src "libresoc.v:3816.9-3816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 - case - assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] - end - attribute \src "libresoc.v:3831.3-3846.6" - process $proc$libresoc.v:3831$88 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:3832.5-3832.29" - switch \initial - attribute \src "libresoc.v:3832.9-3832.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "libresoc.v:3847.3-3862.6" - process $proc$libresoc.v:3847$89 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:3848.5-3848.29" - switch \initial - attribute \src "libresoc.v:3848.9-3848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:3868.1-4655.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" -attribute \generator "nMigen" -module \ALU_dec31_dec_sub8 - attribute \src "libresoc.v:4439.3-4481.6" - wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4482.3-4524.6" - wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4611.3-4653.6" - wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4181.3-4223.6" - wire $0\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4052.3-4094.6" - wire width 12 $0\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:4353.3-4395.6" - wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4396.3-4438.6" - wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4310.3-4352.6" - wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4095.3-4137.6" - wire $0\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4138.3-4180.6" - wire $0\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4224.3-4266.6" - wire $0\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4525.3-4567.6" - wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4568.3-4610.6" - wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4267.3-4309.6" - wire $0\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:3869.7-3869.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:4439.3-4481.6" - wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4482.3-4524.6" - wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4611.3-4653.6" - wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4181.3-4223.6" - wire $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4052.3-4094.6" - wire width 12 $1\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:4353.3-4395.6" - wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4396.3-4438.6" - wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4310.3-4352.6" - wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4095.3-4137.6" - wire $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4138.3-4180.6" - wire $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4224.3-4266.6" - wire $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4525.3-4567.6" - wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4568.3-4610.6" - wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4267.3-4309.6" - wire $1\ALU_dec31_dec_sub8_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_dec31_dec_sub8_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \ALU_dec31_dec_sub8_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \ALU_dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \ALU_dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \ALU_dec31_dec_sub8_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \ALU_dec31_dec_sub8_sgn - attribute \src "libresoc.v:3869.7-3869.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:3869.7-3869.20" - process $proc$libresoc.v:3869$105 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:4052.3-4094.6" - process $proc$libresoc.v:4052$91 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_function_unit[11:0] $1\ALU_dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:4053.5-4053.29" - switch \initial - attribute \src "libresoc.v:4053.9-4053.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[11:0] - end - attribute \src "libresoc.v:4095.3-4137.6" - process $proc$libresoc.v:4095$92 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:4096.5-4096.29" - switch \initial - attribute \src "libresoc.v:4096.9-4096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 - case - assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] - end - attribute \src "libresoc.v:4138.3-4180.6" - process $proc$libresoc.v:4138$93 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:4139.5-4139.29" - switch \initial - attribute \src "libresoc.v:4139.9-4139.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] - end - attribute \src "libresoc.v:4181.3-4223.6" - process $proc$libresoc.v:4181$94 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:4182.5-4182.29" - switch \initial - attribute \src "libresoc.v:4182.9-4182.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 - case - assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] - end - attribute \src "libresoc.v:4224.3-4266.6" - process $proc$libresoc.v:4224$95 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:4225.5-4225.29" - switch \initial - attribute \src "libresoc.v:4225.9-4225.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] - end - attribute \src "libresoc.v:4267.3-4309.6" - process $proc$libresoc.v:4267$96 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:4268.5-4268.29" - switch \initial - attribute \src "libresoc.v:4268.9-4268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - case - assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 - end - sync always - update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] - end - attribute \src "libresoc.v:4310.3-4352.6" - process $proc$libresoc.v:4310$97 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:4311.5-4311.29" - switch \initial - attribute \src "libresoc.v:4311.9-4311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 - case - assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] - end - attribute \src "libresoc.v:4353.3-4395.6" - process $proc$libresoc.v:4353$98 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:4354.5-4354.29" - switch \initial - attribute \src "libresoc.v:4354.9-4354.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] - end - attribute \src "libresoc.v:4396.3-4438.6" - process $proc$libresoc.v:4396$99 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:4397.5-4397.29" - switch \initial - attribute \src "libresoc.v:4397.9-4397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] - end - attribute \src "libresoc.v:4439.3-4481.6" - process $proc$libresoc.v:4439$100 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:4440.5-4440.29" - switch \initial - attribute \src "libresoc.v:4440.9-4440.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - case - assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] - end - attribute \src "libresoc.v:4482.3-4524.6" - process $proc$libresoc.v:4482$101 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:4483.5-4483.29" - switch \initial - attribute \src "libresoc.v:4483.9-4483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 - case - assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 - end - sync always - update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] - end - attribute \src "libresoc.v:4525.3-4567.6" - process $proc$libresoc.v:4525$102 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:4526.5-4526.29" - switch \initial - attribute \src "libresoc.v:4526.9-4526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - case - assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] - end - attribute \src "libresoc.v:4568.3-4610.6" - process $proc$libresoc.v:4568$103 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:4569.5-4569.29" - switch \initial - attribute \src "libresoc.v:4569.9-4569.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] - end - attribute \src "libresoc.v:4611.3-4653.6" - process $proc$libresoc.v:4611$104 - assign { } { } - assign { } { } - assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:4612.5-4612.29" - switch \initial - attribute \src "libresoc.v:4612.9-4612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 - case - assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 - end - sync always - update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:4659.1-4938.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" -attribute \generator "nMigen" -module \BRANCH_dec19 - attribute \src "libresoc.v:4857.3-4872.6" - wire width 3 $0\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4873.3-4888.6" - wire width 3 $0\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4809.3-4824.6" - wire width 12 $0\BRANCH_dec19_function_unit[11:0] - attribute \src "libresoc.v:4841.3-4856.6" - wire width 4 $0\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4825.3-4840.6" - wire width 7 $0\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4905.3-4920.6" - wire $0\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4921.3-4936.6" - wire $0\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4889.3-4904.6" - wire width 2 $0\BRANCH_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4660.7-4660.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:4857.3-4872.6" - wire width 3 $1\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4873.3-4888.6" - wire width 3 $1\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4809.3-4824.6" - wire width 12 $1\BRANCH_dec19_function_unit[11:0] - attribute \src "libresoc.v:4841.3-4856.6" - wire width 4 $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4825.3-4840.6" - wire width 7 $1\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4905.3-4920.6" - wire $1\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4921.3-4936.6" - wire $1\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4889.3-4904.6" - wire width 2 $1\BRANCH_dec19_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \BRANCH_dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \BRANCH_dec19_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \BRANCH_dec19_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \BRANCH_dec19_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \BRANCH_dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 7 \BRANCH_dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \BRANCH_dec19_lk - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \BRANCH_dec19_rc_sel - attribute \src "libresoc.v:4660.7-4660.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \src "libresoc.v:4660.7-4660.20" - process $proc$libresoc.v:4660$114 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:4809.3-4824.6" - process $proc$libresoc.v:4809$106 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_function_unit[11:0] $1\BRANCH_dec19_function_unit[11:0] - attribute \src "libresoc.v:4810.5-4810.29" - switch \initial - attribute \src "libresoc.v:4810.9-4810.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 - case - assign $1\BRANCH_dec19_function_unit[11:0] 12'000000000000 - end - sync always - update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[11:0] - end - attribute \src "libresoc.v:4825.3-4840.6" - process $proc$libresoc.v:4825$107 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] - attribute \src "libresoc.v:4826.5-4826.29" - switch \initial - attribute \src "libresoc.v:4826.9-4826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 - case - assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 - end - sync always - update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] - end - attribute \src "libresoc.v:4841.3-4856.6" - process $proc$libresoc.v:4841$108 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] - attribute \src "libresoc.v:4842.5-4842.29" - switch \initial - attribute \src "libresoc.v:4842.9-4842.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 - case - assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 - end - sync always - update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] - end - attribute \src "libresoc.v:4857.3-4872.6" - process $proc$libresoc.v:4857$109 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] - attribute \src "libresoc.v:4858.5-4858.29" - switch \initial - attribute \src "libresoc.v:4858.9-4858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_cr_in[2:0] 3'010 - case - assign $1\BRANCH_dec19_cr_in[2:0] 3'000 - end - sync always - update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] - end - attribute \src "libresoc.v:4873.3-4888.6" - process $proc$libresoc.v:4873$110 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] - attribute \src "libresoc.v:4874.5-4874.29" - switch \initial - attribute \src "libresoc.v:4874.9-4874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - case - assign $1\BRANCH_dec19_cr_out[2:0] 3'000 - end - sync always - update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] - end - attribute \src "libresoc.v:4889.3-4904.6" - process $proc$libresoc.v:4889$111 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4890.5-4890.29" - switch \initial - attribute \src "libresoc.v:4890.9-4890.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - case - assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 - end - sync always - update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] - end - attribute \src "libresoc.v:4905.3-4920.6" - process $proc$libresoc.v:4905$112 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] - attribute \src "libresoc.v:4906.5-4906.29" - switch \initial - attribute \src "libresoc.v:4906.9-4906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - case - assign $1\BRANCH_dec19_is_32b[0:0] 1'0 - end - sync always - update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] - end - attribute \src "libresoc.v:4921.3-4936.6" - process $proc$libresoc.v:4921$113 - assign { } { } - assign { } { } - assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] - attribute \src "libresoc.v:4922.5-4922.29" - switch \initial - attribute \src "libresoc.v:4922.9-4922.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\BRANCH_dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\BRANCH_dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\BRANCH_dec19_lk[0:0] 1'1 - case - assign $1\BRANCH_dec19_lk[0:0] 1'0 - end - sync always - update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] - end - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:4942.1-5239.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" -attribute \generator "nMigen" -module \CR_dec19 - attribute \src "libresoc.v:5136.3-5169.6" - wire width 3 $0\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5170.3-5203.6" - wire width 3 $0\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5068.3-5101.6" - wire width 12 $0\CR_dec19_function_unit[11:0] - attribute \src "libresoc.v:5102.3-5135.6" - wire width 7 $0\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5204.3-5237.6" - wire width 2 $0\CR_dec19_rc_sel[1:0] - attribute \src "libresoc.v:4943.7-4943.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:5136.3-5169.6" - wire width 3 $1\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5170.3-5203.6" - wire width 3 $1\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5068.3-5101.6" - wire width 12 $1\CR_dec19_function_unit[11:0] - attribute \src "libresoc.v:5102.3-5135.6" - wire width 7 $1\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5204.3-5237.6" - wire width 2 $1\CR_dec19_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \CR_dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \CR_dec19_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec19_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \CR_dec19_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 5 \CR_dec19_rc_sel - attribute \src "libresoc.v:4943.7-4943.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \src "libresoc.v:4943.7-4943.20" - process $proc$libresoc.v:4943$120 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:5068.3-5101.6" - process $proc$libresoc.v:5068$115 - assign { } { } - assign { } { } - assign $0\CR_dec19_function_unit[11:0] $1\CR_dec19_function_unit[11:0] - attribute \src "libresoc.v:5069.5-5069.29" - switch \initial - attribute \src "libresoc.v:5069.9-5069.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\CR_dec19_function_unit[11:0] 12'000001000000 - case - assign $1\CR_dec19_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec19_function_unit $0\CR_dec19_function_unit[11:0] - end - attribute \src "libresoc.v:5102.3-5135.6" - process $proc$libresoc.v:5102$116 - assign { } { } - assign { } { } - assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] - attribute \src "libresoc.v:5103.5-5103.29" - switch \initial - attribute \src "libresoc.v:5103.9-5103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'0101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\CR_dec19_internal_op[6:0] 7'1000101 - case - assign $1\CR_dec19_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] - end - attribute \src "libresoc.v:5136.3-5169.6" - process $proc$libresoc.v:5136$117 - assign { } { } - assign { } { } - assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] - attribute \src "libresoc.v:5137.5-5137.29" - switch \initial - attribute \src "libresoc.v:5137.9-5137.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\CR_dec19_cr_in[2:0] 3'100 - case - assign $1\CR_dec19_cr_in[2:0] 3'000 - end - sync always - update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] - end - attribute \src "libresoc.v:5170.3-5203.6" - process $proc$libresoc.v:5170$118 - assign { } { } - assign { } { } - assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] - attribute \src "libresoc.v:5171.5-5171.29" - switch \initial - attribute \src "libresoc.v:5171.9-5171.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\CR_dec19_cr_out[2:0] 3'011 - case - assign $1\CR_dec19_cr_out[2:0] 3'000 - end - sync always - update \CR_dec19_cr_out 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$1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\CR_dec19_rc_sel[1:0] 2'00 - case - assign $1\CR_dec19_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:5243.1-5972.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" -attribute \generator "nMigen" -module \CR_dec31 - attribute \src "libresoc.v:5928.3-5946.6" - wire width 3 $0\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:5947.3-5965.6" - wire width 3 $0\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5890.3-5908.6" - wire width 12 $0\CR_dec31_function_unit[11:0] - attribute \src "libresoc.v:5909.3-5927.6" - wire width 7 $0\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5871.3-5889.6" - wire width 2 $0\CR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:5244.7-5244.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:5928.3-5946.6" - wire width 3 $1\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:5947.3-5965.6" - wire width 3 $1\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5890.3-5908.6" - wire width 12 $1\CR_dec31_function_unit[11:0] - attribute \src "libresoc.v:5909.3-5927.6" - wire width 7 $1\CR_dec31_internal_op[6:0] - attribute \src "libresoc.v:5871.3-5889.6" - wire width 2 $1\CR_dec31_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - 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\CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op - case - assign $1\CR_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:5928.3-5946.6" - process $proc$libresoc.v:5928$124 - assign { } { } - assign { } { } - assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] - attribute \src "libresoc.v:5929.5-5929.29" - switch \initial - attribute \src "libresoc.v:5929.9-5929.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in - case - assign $1\CR_dec31_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:5947.3-5965.6" - process $proc$libresoc.v:5947$125 - assign { } { } - assign { } { } - assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] - attribute \src "libresoc.v:5948.5-5948.29" - switch \initial - attribute \src "libresoc.v:5948.9-5948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out - case - assign $1\CR_dec31_cr_out[2:0] 3'000 - end - sync always - update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] - end - connect \CR_dec31_dec_sub16_opcode_in \opcode_in - connect \CR_dec31_dec_sub15_opcode_in \opcode_in - connect \CR_dec31_dec_sub19_opcode_in \opcode_in - connect \CR_dec31_dec_sub0_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:5976.1-6153.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" -attribute \generator "nMigen" -module \CR_dec31_dec_sub0 - attribute \src "libresoc.v:6122.3-6131.6" - wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6132.3-6141.6" - wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6102.3-6111.6" - wire width 12 $0\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:6112.3-6121.6" - wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:6142.3-6151.6" - wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:5977.7-5977.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:6122.3-6131.6" - wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6132.3-6141.6" - wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6102.3-6111.6" - wire width 12 $1\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:6112.3-6121.6" - wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:6142.3-6151.6" - wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \CR_dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \CR_dec31_dec_sub0_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub0_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \CR_dec31_dec_sub0_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel - attribute \src "libresoc.v:5977.7-5977.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:5977.7-5977.20" - process $proc$libresoc.v:5977$132 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:6102.3-6111.6" - process $proc$libresoc.v:6102$127 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_function_unit[11:0] $1\CR_dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:6103.5-6103.29" - switch \initial - attribute \src "libresoc.v:6103.9-6103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000001000000 - case - assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[11:0] - end - attribute \src "libresoc.v:6112.3-6121.6" - process $proc$libresoc.v:6112$128 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:6113.5-6113.29" - switch \initial - attribute \src "libresoc.v:6113.9-6113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 - case - assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] - end - attribute \src "libresoc.v:6122.3-6131.6" - process $proc$libresoc.v:6122$129 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:6123.5-6123.29" - switch \initial - attribute \src "libresoc.v:6123.9-6123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 - case - assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] - end - attribute \src "libresoc.v:6132.3-6141.6" - process $proc$libresoc.v:6132$130 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:6133.5-6133.29" - switch \initial - attribute \src "libresoc.v:6133.9-6133.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 - case - assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] - end - attribute \src "libresoc.v:6142.3-6151.6" - process $proc$libresoc.v:6142$131 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:6143.5-6143.29" - switch \initial - attribute \src "libresoc.v:6143.9-6143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 - case - assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:6157.1-6799.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" -attribute \generator "nMigen" -module \CR_dec31_dec_sub15 - attribute \src "libresoc.v:6489.3-6591.6" - wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6592.3-6694.6" - wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6283.3-6385.6" - wire width 12 $0\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:6386.3-6488.6" - wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6695.3-6797.6" - wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:6158.7-6158.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:6489.3-6591.6" - wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6592.3-6694.6" - wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6283.3-6385.6" - wire width 12 $1\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:6386.3-6488.6" - wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6695.3-6797.6" - wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \CR_dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \CR_dec31_dec_sub15_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub15_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \CR_dec31_dec_sub15_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel - attribute \src "libresoc.v:6158.7-6158.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:6158.7-6158.20" - process $proc$libresoc.v:6158$138 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:6283.3-6385.6" - process $proc$libresoc.v:6283$133 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub15_function_unit[11:0] $1\CR_dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:6284.5-6284.29" - switch \initial - attribute \src "libresoc.v:6284.9-6284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 - case - assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[11:0] - end - attribute \src "libresoc.v:6386.3-6488.6" - process $proc$libresoc.v:6386$134 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:6387.5-6387.29" - switch \initial - attribute \src "libresoc.v:6387.9-6387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 - case - assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] - end - attribute \src "libresoc.v:6489.3-6591.6" - process $proc$libresoc.v:6489$135 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:6490.5-6490.29" - switch \initial - attribute \src "libresoc.v:6490.9-6490.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 - case - assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] - end - attribute \src "libresoc.v:6592.3-6694.6" - process $proc$libresoc.v:6592$136 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:6593.5-6593.29" - switch \initial - attribute \src "libresoc.v:6593.9-6593.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - case - assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] - end - attribute \src "libresoc.v:6695.3-6797.6" - process $proc$libresoc.v:6695$137 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:6696.5-6696.29" - switch \initial - attribute \src "libresoc.v:6696.9-6696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - case - assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:6803.1-6980.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" -attribute \generator "nMigen" -module \CR_dec31_dec_sub16 - attribute \src "libresoc.v:6949.3-6958.6" - wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:6959.3-6968.6" - wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6929.3-6938.6" - wire width 12 $0\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:6939.3-6948.6" - wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:6969.3-6978.6" - wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:6804.7-6804.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:6949.3-6958.6" - wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:6959.3-6968.6" - wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6929.3-6938.6" - wire width 12 $1\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:6939.3-6948.6" - wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:6969.3-6978.6" - wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \CR_dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \CR_dec31_dec_sub16_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub16_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \CR_dec31_dec_sub16_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel - attribute \src "libresoc.v:6804.7-6804.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:6804.7-6804.20" - process $proc$libresoc.v:6804$144 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:6929.3-6938.6" - process $proc$libresoc.v:6929$139 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_function_unit[11:0] $1\CR_dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:6930.5-6930.29" - switch \initial - attribute \src "libresoc.v:6930.9-6930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000001000000 - case - assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[11:0] - end - attribute \src "libresoc.v:6939.3-6948.6" - process $proc$libresoc.v:6939$140 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:6940.5-6940.29" - switch \initial - attribute \src "libresoc.v:6940.9-6940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 - case - assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] - end - attribute \src "libresoc.v:6949.3-6958.6" - process $proc$libresoc.v:6949$141 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:6950.5-6950.29" - switch \initial - attribute \src "libresoc.v:6950.9-6950.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 - case - assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] - end - attribute \src "libresoc.v:6959.3-6968.6" - process $proc$libresoc.v:6959$142 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:6960.5-6960.29" - switch \initial - attribute \src "libresoc.v:6960.9-6960.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 - case - assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] - end - attribute \src "libresoc.v:6969.3-6978.6" - process $proc$libresoc.v:6969$143 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:6970.5-6970.29" - switch \initial - attribute \src "libresoc.v:6970.9-6970.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 - case - assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:6984.1-7161.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" -attribute \generator "nMigen" -module \CR_dec31_dec_sub19 - attribute \src "libresoc.v:7130.3-7139.6" - wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7140.3-7149.6" - wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7110.3-7119.6" - wire width 12 $0\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:7120.3-7129.6" - wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7150.3-7159.6" - wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:6985.7-6985.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:7130.3-7139.6" - wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7140.3-7149.6" - wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7110.3-7119.6" - wire width 12 $1\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:7120.3-7129.6" - wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7150.3-7159.6" - wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \CR_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \CR_dec31_dec_sub19_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \CR_dec31_dec_sub19_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \CR_dec31_dec_sub19_internal_op - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:6985.7-6985.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 6 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:6985.7-6985.20" - process $proc$libresoc.v:6985$150 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:7110.3-7119.6" - process $proc$libresoc.v:7110$145 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub19_function_unit[11:0] $1\CR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:7111.5-7111.29" - switch \initial - attribute \src "libresoc.v:7111.9-7111.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000001000000 - case - assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[11:0] - end - attribute \src "libresoc.v:7120.3-7129.6" - process $proc$libresoc.v:7120$146 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:7121.5-7121.29" - switch \initial - attribute \src "libresoc.v:7121.9-7121.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 - case - assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 - end - sync always - update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] - end - attribute \src "libresoc.v:7130.3-7139.6" - process $proc$libresoc.v:7130$147 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:7131.5-7131.29" - switch \initial - attribute \src "libresoc.v:7131.9-7131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 - case - assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] - end - attribute \src "libresoc.v:7140.3-7149.6" - process $proc$libresoc.v:7140$148 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:7141.5-7141.29" - switch \initial - attribute \src "libresoc.v:7141.9-7141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 - case - assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 - end - sync always - update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] - end - attribute \src "libresoc.v:7150.3-7159.6" - process $proc$libresoc.v:7150$149 - assign { } { } - assign { } { } - assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:7151.5-7151.29" - switch \initial - attribute \src "libresoc.v:7151.9-7151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 - case - assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 - end - sync always - update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:7165.1-7903.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" -attribute \generator "nMigen" -module \DIV_dec31 - attribute \src "libresoc.v:7873.3-7885.6" - wire width 3 $0\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7886.3-7898.6" - wire width 3 $0\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7743.3-7755.6" - wire width 2 $0\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7782.3-7794.6" - wire $0\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7821.3-7833.6" - wire width 12 $0\DIV_dec31_function_unit[11:0] - attribute \src "libresoc.v:7847.3-7859.6" - wire width 3 $0\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7860.3-7872.6" - wire width 4 $0\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7834.3-7846.6" - wire width 7 $0\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7756.3-7768.6" - wire $0\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7769.3-7781.6" - wire $0\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7795.3-7807.6" - wire $0\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7717.3-7729.6" - wire width 4 $0\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7730.3-7742.6" - wire width 2 $0\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7808.3-7820.6" - wire $0\DIV_dec31_sgn[0:0] - attribute \src "libresoc.v:7166.7-7166.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:7873.3-7885.6" - wire width 3 $1\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7886.3-7898.6" - wire width 3 $1\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7743.3-7755.6" - wire width 2 $1\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7782.3-7794.6" - wire $1\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7821.3-7833.6" - wire width 12 $1\DIV_dec31_function_unit[11:0] - attribute \src "libresoc.v:7847.3-7859.6" - wire width 3 $1\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7860.3-7872.6" - wire width 4 $1\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7834.3-7846.6" - wire width 7 $1\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7756.3-7768.6" - wire $1\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7769.3-7781.6" - wire $1\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7795.3-7807.6" - wire $1\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7717.3-7729.6" - wire width 4 $1\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7730.3-7742.6" - wire width 2 $1\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7808.3-7820.6" - wire $1\DIV_dec31_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \DIV_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \DIV_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \DIV_dec31_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - 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\enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \DIV_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \DIV_dec31_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \DIV_dec31_sgn - attribute \src "libresoc.v:7166.7-7166.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:7683.23-7699.4" - cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 - connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in - connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out - connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out - connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit - connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel - connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel - connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b - connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len - connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - connect \opcode_in \DIV_dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:7700.22-7716.4" - cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 - connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in - connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out - connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out - connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit - connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel - connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel - connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b - connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len - connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - connect \opcode_in \DIV_dec31_dec_sub9_opcode_in - end - attribute \src "libresoc.v:7166.7-7166.20" - process $proc$libresoc.v:7166$165 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:7717.3-7729.6" - process $proc$libresoc.v:7717$151 - assign { } { } - assign { } { } - assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] - attribute \src "libresoc.v:7718.5-7718.29" - switch \initial - attribute \src "libresoc.v:7718.9-7718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len - case - assign $1\DIV_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] - end - attribute \src "libresoc.v:7730.3-7742.6" - process $proc$libresoc.v:7730$152 - assign { } { } - assign { } { } - assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] - attribute \src "libresoc.v:7731.5-7731.29" - switch \initial - attribute \src "libresoc.v:7731.9-7731.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel - case - assign $1\DIV_dec31_rc_sel[1:0] 2'00 - end - sync always - update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:7743.3-7755.6" - process $proc$libresoc.v:7743$153 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] - attribute \src "libresoc.v:7744.5-7744.29" - switch \initial - attribute \src "libresoc.v:7744.9-7744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in - case - assign $1\DIV_dec31_cry_in[1:0] 2'00 - end - sync always - update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] - end - attribute \src "libresoc.v:7756.3-7768.6" - process $proc$libresoc.v:7756$154 - assign { } { } - assign { } { } - assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] - attribute \src "libresoc.v:7757.5-7757.29" - switch \initial - attribute \src "libresoc.v:7757.9-7757.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a - case - assign $1\DIV_dec31_inv_a[0:0] 1'0 - end - sync always - update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] - end - attribute \src "libresoc.v:7769.3-7781.6" - process $proc$libresoc.v:7769$155 - assign { } { } - assign { } { } - assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] - attribute \src "libresoc.v:7770.5-7770.29" - switch \initial - attribute \src "libresoc.v:7770.9-7770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out - case - assign $1\DIV_dec31_inv_out[0:0] 1'0 - end - sync always - update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] - end - attribute \src "libresoc.v:7782.3-7794.6" - process $proc$libresoc.v:7782$156 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] - attribute \src "libresoc.v:7783.5-7783.29" - switch \initial - attribute \src "libresoc.v:7783.9-7783.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out - case - assign $1\DIV_dec31_cry_out[0:0] 1'0 - end - sync always - update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] - end - attribute \src "libresoc.v:7795.3-7807.6" - process $proc$libresoc.v:7795$157 - assign { } { } - assign { } { } - assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] - attribute \src "libresoc.v:7796.5-7796.29" - switch \initial - attribute \src "libresoc.v:7796.9-7796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b - case - assign $1\DIV_dec31_is_32b[0:0] 1'0 - end - sync always - update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] - end - attribute \src "libresoc.v:7808.3-7820.6" - process $proc$libresoc.v:7808$158 - assign { } { } - assign { } { } - assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] - attribute \src "libresoc.v:7809.5-7809.29" - switch \initial - attribute \src "libresoc.v:7809.9-7809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn - case - assign $1\DIV_dec31_sgn[0:0] 1'0 - end - sync always - update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] - end - attribute \src "libresoc.v:7821.3-7833.6" - process $proc$libresoc.v:7821$159 - assign { } { } - assign { } { } - assign $0\DIV_dec31_function_unit[11:0] $1\DIV_dec31_function_unit[11:0] - attribute \src "libresoc.v:7822.5-7822.29" - switch \initial - attribute \src "libresoc.v:7822.9-7822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit - case - assign $1\DIV_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[11:0] - end - attribute \src "libresoc.v:7834.3-7846.6" - process $proc$libresoc.v:7834$160 - assign { } { } - assign { } { } - assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] - attribute \src "libresoc.v:7835.5-7835.29" - switch \initial - attribute \src "libresoc.v:7835.9-7835.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op - case - assign $1\DIV_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:7847.3-7859.6" - process $proc$libresoc.v:7847$161 - assign { } { } - assign { } { } - assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] - attribute \src "libresoc.v:7848.5-7848.29" - switch \initial - attribute \src "libresoc.v:7848.9-7848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel - case - assign $1\DIV_dec31_in1_sel[2:0] 3'000 - end - sync always - update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] - end - attribute \src "libresoc.v:7860.3-7872.6" - process $proc$libresoc.v:7860$162 - assign { } { } - assign { } { } - assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] - attribute \src "libresoc.v:7861.5-7861.29" - switch \initial - attribute \src "libresoc.v:7861.9-7861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel - case - assign $1\DIV_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:7873.3-7885.6" - process $proc$libresoc.v:7873$163 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] - attribute \src "libresoc.v:7874.5-7874.29" - switch \initial - attribute \src "libresoc.v:7874.9-7874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in - case - assign $1\DIV_dec31_cr_in[2:0] 3'000 - end - sync always - update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:7886.3-7898.6" - process $proc$libresoc.v:7886$164 - assign { } { } - assign { } { } - assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] - attribute \src "libresoc.v:7887.5-7887.29" - switch \initial - attribute \src "libresoc.v:7887.9-7887.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out - case - assign $1\DIV_dec31_cr_out[2:0] 3'000 - end - sync always - update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] - end - connect \DIV_dec31_dec_sub11_opcode_in \opcode_in - connect \DIV_dec31_dec_sub9_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:7907.1-8610.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" -attribute \generator "nMigen" -module \DIV_dec31_dec_sub11 - attribute \src "libresoc.v:8424.3-8460.6" - wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8461.3-8497.6" - wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8572.3-8608.6" - wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8202.3-8238.6" - wire $0\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8091.3-8127.6" - wire width 12 $0\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:8350.3-8386.6" - wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8387.3-8423.6" - wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8313.3-8349.6" - wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8128.3-8164.6" - wire $0\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8165.3-8201.6" - wire $0\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8239.3-8275.6" - wire $0\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8498.3-8534.6" - wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8535.3-8571.6" - wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8276.3-8312.6" - wire $0\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:7908.7-7908.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:8424.3-8460.6" - wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8461.3-8497.6" - wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8572.3-8608.6" - wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8202.3-8238.6" - wire $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8091.3-8127.6" - wire width 12 $1\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:8350.3-8386.6" - wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8387.3-8423.6" - wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8313.3-8349.6" - wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8128.3-8164.6" - wire $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8165.3-8201.6" - wire $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8239.3-8275.6" - wire $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8498.3-8534.6" - wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8535.3-8571.6" - wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8276.3-8312.6" - wire $1\DIV_dec31_dec_sub11_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \DIV_dec31_dec_sub11_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \DIV_dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \DIV_dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \DIV_dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \DIV_dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \DIV_dec31_dec_sub11_sgn - attribute \src "libresoc.v:7908.7-7908.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:7908.7-7908.20" - process $proc$libresoc.v:7908$180 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:8091.3-8127.6" - process $proc$libresoc.v:8091$166 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_function_unit[11:0] $1\DIV_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:8092.5-8092.29" - switch \initial - attribute \src "libresoc.v:8092.9-8092.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 - case - assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[11:0] - end - attribute \src "libresoc.v:8128.3-8164.6" - process $proc$libresoc.v:8128$167 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:8129.5-8129.29" - switch \initial - attribute \src "libresoc.v:8129.9-8129.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] - end - attribute \src "libresoc.v:8165.3-8201.6" - process $proc$libresoc.v:8165$168 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:8166.5-8166.29" - switch \initial - attribute \src "libresoc.v:8166.9-8166.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] - end - attribute \src "libresoc.v:8202.3-8238.6" - process $proc$libresoc.v:8202$169 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:8203.5-8203.29" - switch \initial - attribute \src "libresoc.v:8203.9-8203.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] - end - attribute \src "libresoc.v:8239.3-8275.6" - process $proc$libresoc.v:8239$170 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:8240.5-8240.29" - switch \initial - attribute \src "libresoc.v:8240.9-8240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 - case - assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] - end - attribute \src "libresoc.v:8276.3-8312.6" - process $proc$libresoc.v:8276$171 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:8277.5-8277.29" - switch \initial - attribute \src "libresoc.v:8277.9-8277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 - case - assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] - end - attribute \src "libresoc.v:8313.3-8349.6" - process $proc$libresoc.v:8313$172 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:8314.5-8314.29" - switch \initial - attribute \src "libresoc.v:8314.9-8314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 - case - assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] - end - attribute \src "libresoc.v:8350.3-8386.6" - process $proc$libresoc.v:8350$173 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:8351.5-8351.29" - switch \initial - attribute \src "libresoc.v:8351.9-8351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 - case - assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] - end - attribute \src "libresoc.v:8387.3-8423.6" - process $proc$libresoc.v:8387$174 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:8388.5-8388.29" - switch \initial - attribute \src "libresoc.v:8388.9-8388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 - case - assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 - end - sync always - update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] - end - attribute \src "libresoc.v:8424.3-8460.6" - process $proc$libresoc.v:8424$175 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:8425.5-8425.29" - switch \initial - attribute \src "libresoc.v:8425.9-8425.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] - end - attribute \src "libresoc.v:8461.3-8497.6" - process $proc$libresoc.v:8461$176 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:8462.5-8462.29" - switch \initial - attribute \src "libresoc.v:8462.9-8462.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] - end - attribute \src "libresoc.v:8498.3-8534.6" - process $proc$libresoc.v:8498$177 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:8499.5-8499.29" - switch \initial - attribute \src "libresoc.v:8499.9-8499.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - case - assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] - end - attribute \src "libresoc.v:8535.3-8571.6" - process $proc$libresoc.v:8535$178 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:8536.5-8536.29" - switch \initial - attribute \src "libresoc.v:8536.9-8536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 - case - assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 - end - sync always - update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] - end - attribute \src "libresoc.v:8572.3-8608.6" - process $proc$libresoc.v:8572$179 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:8573.5-8573.29" - switch \initial - attribute \src "libresoc.v:8573.9-8573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - case - assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 - end - sync always - update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:8614.1-9317.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" -attribute \generator "nMigen" -module \DIV_dec31_dec_sub9 - attribute \src "libresoc.v:9131.3-9167.6" - wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9168.3-9204.6" - wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9279.3-9315.6" - wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:8909.3-8945.6" - wire $0\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8798.3-8834.6" - wire width 12 $0\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:9057.3-9093.6" - wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9094.3-9130.6" - wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9020.3-9056.6" - wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:8835.3-8871.6" - wire $0\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8872.3-8908.6" - wire $0\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:8946.3-8982.6" - wire $0\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:9205.3-9241.6" - wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9242.3-9278.6" - wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:8983.3-9019.6" - wire $0\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:8615.7-8615.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:9131.3-9167.6" - wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9168.3-9204.6" - wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9279.3-9315.6" - wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:8909.3-8945.6" - wire $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8798.3-8834.6" - wire width 12 $1\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:9057.3-9093.6" - wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9094.3-9130.6" - wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9020.3-9056.6" - wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:8835.3-8871.6" - wire $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8872.3-8908.6" - wire $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:8946.3-8982.6" - wire $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:9205.3-9241.6" - wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9242.3-9278.6" - wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:8983.3-9019.6" - wire $1\DIV_dec31_dec_sub9_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \DIV_dec31_dec_sub9_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \DIV_dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \DIV_dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \DIV_dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \DIV_dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \DIV_dec31_dec_sub9_sgn - attribute \src "libresoc.v:8615.7-8615.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:8615.7-8615.20" - process $proc$libresoc.v:8615$195 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:8798.3-8834.6" - process $proc$libresoc.v:8798$181 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_function_unit[11:0] $1\DIV_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:8799.5-8799.29" - switch \initial - attribute \src "libresoc.v:8799.9-8799.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 - case - assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[11:0] - end - attribute \src "libresoc.v:8835.3-8871.6" - process $proc$libresoc.v:8835$182 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:8836.5-8836.29" - switch \initial - attribute \src "libresoc.v:8836.9-8836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] - end - attribute \src "libresoc.v:8872.3-8908.6" - process $proc$libresoc.v:8872$183 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:8873.5-8873.29" - switch \initial - attribute \src "libresoc.v:8873.9-8873.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] - end - attribute \src "libresoc.v:8909.3-8945.6" - process $proc$libresoc.v:8909$184 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:8910.5-8910.29" - switch \initial - attribute \src "libresoc.v:8910.9-8910.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] - end - attribute \src "libresoc.v:8946.3-8982.6" - process $proc$libresoc.v:8946$185 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:8947.5-8947.29" - switch \initial - attribute \src "libresoc.v:8947.9-8947.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] - end - attribute \src "libresoc.v:8983.3-9019.6" - process $proc$libresoc.v:8983$186 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:8984.5-8984.29" - switch \initial - attribute \src "libresoc.v:8984.9-8984.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 - case - assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 - end - sync always - update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] - end - attribute \src "libresoc.v:9020.3-9056.6" - process $proc$libresoc.v:9020$187 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:9021.5-9021.29" - switch \initial - attribute \src "libresoc.v:9021.9-9021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 - case - assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] - end - attribute \src "libresoc.v:9057.3-9093.6" - process $proc$libresoc.v:9057$188 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:9058.5-9058.29" - switch \initial - attribute \src "libresoc.v:9058.9-9058.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 - case - assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] - end - attribute \src "libresoc.v:9094.3-9130.6" - process $proc$libresoc.v:9094$189 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:9095.5-9095.29" - switch \initial - attribute \src "libresoc.v:9095.9-9095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] - end - attribute \src "libresoc.v:9131.3-9167.6" - process $proc$libresoc.v:9131$190 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:9132.5-9132.29" - switch \initial - attribute \src "libresoc.v:9132.9-9132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] - end - attribute \src "libresoc.v:9168.3-9204.6" - process $proc$libresoc.v:9168$191 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:9169.5-9169.29" - switch \initial - attribute \src "libresoc.v:9169.9-9169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 - case - assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] - end - attribute \src "libresoc.v:9205.3-9241.6" - process $proc$libresoc.v:9205$192 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:9206.5-9206.29" - switch \initial - attribute \src "libresoc.v:9206.9-9206.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - case - assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] - end - attribute \src "libresoc.v:9242.3-9278.6" - process $proc$libresoc.v:9242$193 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:9243.5-9243.29" - switch \initial - attribute \src "libresoc.v:9243.9-9243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 - case - assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 - end - sync always - update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] - end - attribute \src "libresoc.v:9279.3-9315.6" - process $proc$libresoc.v:9279$194 - assign { } { } - assign { } { } - assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:9280.5-9280.29" - switch \initial - attribute \src "libresoc.v:9280.9-9280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - case - assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 - end - sync always - update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:9321.1-10482.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" -attribute \generator "nMigen" -module \LDST_dec31 - attribute \src "libresoc.v:10324.3-10342.6" - wire $0\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10229.3-10247.6" - wire width 3 $0\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10248.3-10266.6" - wire width 3 $0\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10400.3-10418.6" - wire width 12 $0\LDST_dec31_function_unit[11:0] - attribute \src "libresoc.v:10438.3-10456.6" - wire width 3 $0\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10457.3-10475.6" - wire width 4 $0\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10419.3-10437.6" - wire width 7 $0\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10362.3-10380.6" - wire $0\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10267.3-10285.6" - wire width 4 $0\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10305.3-10323.6" - wire width 2 $0\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10381.3-10399.6" - wire $0\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10343.3-10361.6" - wire $0\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10286.3-10304.6" - wire width 2 $0\LDST_dec31_upd[1:0] - attribute \src "libresoc.v:9322.7-9322.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:10324.3-10342.6" - wire $1\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10229.3-10247.6" - wire width 3 $1\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10248.3-10266.6" - wire width 3 $1\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10400.3-10418.6" - wire width 12 $1\LDST_dec31_function_unit[11:0] - attribute \src "libresoc.v:10438.3-10456.6" - wire width 3 $1\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10457.3-10475.6" - wire width 4 $1\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10419.3-10437.6" - wire width 7 $1\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10362.3-10380.6" - wire $1\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10267.3-10285.6" - wire width 4 $1\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10305.3-10323.6" - wire width 2 $1\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10381.3-10399.6" - wire $1\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10343.3-10361.6" - wire $1\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10286.3-10304.6" - wire width 2 $1\LDST_dec31_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LDST_dec31_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LDST_dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute 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\LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out - connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit - connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel - connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel - connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b - connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len - connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext - connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - connect \opcode_in \LDST_dec31_dec_sub22_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:10213.24-10228.4" - cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 - connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br - connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in - connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out - connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit - connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel - connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel - connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b - connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len - connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext - connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd - connect \opcode_in \LDST_dec31_dec_sub23_opcode_in - end - attribute \src "libresoc.v:10229.3-10247.6" - process $proc$libresoc.v:10229$196 - assign { } { } - assign { } { } - assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] - attribute \src "libresoc.v:10230.5-10230.29" - switch \initial - attribute \src "libresoc.v:10230.9-10230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in - case - assign $1\LDST_dec31_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:10248.3-10266.6" - process $proc$libresoc.v:10248$197 - assign { } { } - assign { } { } - assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] - attribute \src "libresoc.v:10249.5-10249.29" - switch \initial - attribute \src "libresoc.v:10249.9-10249.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out - case - assign $1\LDST_dec31_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] - end - attribute \src "libresoc.v:10267.3-10285.6" - process $proc$libresoc.v:10267$198 - assign { } { } - assign { } { } - assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] - attribute \src "libresoc.v:10268.5-10268.29" - switch \initial - attribute \src "libresoc.v:10268.9-10268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len - case - assign $1\LDST_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] - end - attribute \src "libresoc.v:10286.3-10304.6" - process $proc$libresoc.v:10286$199 - assign { } { } - assign { } { } - assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] - attribute \src "libresoc.v:10287.5-10287.29" - switch \initial - attribute \src "libresoc.v:10287.9-10287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd - case - assign $1\LDST_dec31_upd[1:0] 2'00 - end - sync always - update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] - end - attribute \src "libresoc.v:10305.3-10323.6" - process $proc$libresoc.v:10305$200 - assign { } { } - assign { } { } - assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] - attribute \src "libresoc.v:10306.5-10306.29" - switch \initial - attribute \src "libresoc.v:10306.9-10306.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel - case - assign $1\LDST_dec31_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:10324.3-10342.6" - process $proc$libresoc.v:10324$201 - assign { } { } - assign { } { } - assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] - attribute \src "libresoc.v:10325.5-10325.29" - switch \initial - attribute \src "libresoc.v:10325.9-10325.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br - case - assign $1\LDST_dec31_br[0:0] 1'0 - end - sync always - update \LDST_dec31_br $0\LDST_dec31_br[0:0] - end - attribute \src "libresoc.v:10343.3-10361.6" - process $proc$libresoc.v:10343$202 - assign { } { } - assign { } { } - assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] - attribute \src "libresoc.v:10344.5-10344.29" - switch \initial - attribute \src "libresoc.v:10344.9-10344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext - case - assign $1\LDST_dec31_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] - end - attribute \src "libresoc.v:10362.3-10380.6" - process $proc$libresoc.v:10362$203 - assign { } { } - assign { } { } - assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] - attribute \src "libresoc.v:10363.5-10363.29" - switch \initial - attribute \src "libresoc.v:10363.9-10363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b - case - assign $1\LDST_dec31_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] - end - attribute \src "libresoc.v:10381.3-10399.6" - process $proc$libresoc.v:10381$204 - assign { } { } - assign { } { } - assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] - attribute \src "libresoc.v:10382.5-10382.29" - switch \initial - attribute \src "libresoc.v:10382.9-10382.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn - case - assign $1\LDST_dec31_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] - end - attribute \src "libresoc.v:10400.3-10418.6" - process $proc$libresoc.v:10400$205 - assign { } { } - assign { } { } - assign $0\LDST_dec31_function_unit[11:0] $1\LDST_dec31_function_unit[11:0] - attribute \src "libresoc.v:10401.5-10401.29" - switch \initial - attribute \src "libresoc.v:10401.9-10401.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit - case - assign $1\LDST_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[11:0] - end - attribute \src "libresoc.v:10419.3-10437.6" - process $proc$libresoc.v:10419$206 - assign { } { } - assign { } { } - assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] - attribute \src "libresoc.v:10420.5-10420.29" - switch \initial - attribute \src "libresoc.v:10420.9-10420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op - case - assign $1\LDST_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:10438.3-10456.6" - process $proc$libresoc.v:10438$207 - assign { } { } - assign { } { } - assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] - attribute \src "libresoc.v:10439.5-10439.29" - switch \initial - attribute \src "libresoc.v:10439.9-10439.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel - case - assign $1\LDST_dec31_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] - end - attribute \src "libresoc.v:10457.3-10475.6" - process $proc$libresoc.v:10457$208 - assign { } { } - assign { } { } - assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] - attribute \src "libresoc.v:10458.5-10458.29" - switch \initial - attribute \src "libresoc.v:10458.9-10458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel - case - assign $1\LDST_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:9322.7-9322.20" - process $proc$libresoc.v:9322$209 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - connect \LDST_dec31_dec_sub23_opcode_in \opcode_in - connect \LDST_dec31_dec_sub21_opcode_in \opcode_in - connect \LDST_dec31_dec_sub20_opcode_in \opcode_in - connect \LDST_dec31_dec_sub22_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:10486.1-10994.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" -attribute \generator "nMigen" -module \LDST_dec31_dec_sub20 - attribute \src "libresoc.v:10693.3-10717.6" - wire $0\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10868.3-10892.6" - wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10893.3-10917.6" - wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10668.3-10692.6" - wire width 12 $0\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:10818.3-10842.6" - wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10843.3-10867.6" - wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10793.3-10817.6" - wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10743.3-10767.6" - wire $0\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:10918.3-10942.6" - wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:10968.3-10992.6" - wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10768.3-10792.6" - wire $0\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10718.3-10742.6" - wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:10943.3-10967.6" - wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:10487.7-10487.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:10693.3-10717.6" - wire $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10868.3-10892.6" - wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10893.3-10917.6" - wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10668.3-10692.6" - wire width 12 $1\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:10818.3-10842.6" - wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10843.3-10867.6" - wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10793.3-10817.6" - wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10743.3-10767.6" - wire $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:10918.3-10942.6" - wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:10968.3-10992.6" - wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10768.3-10792.6" - wire $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10718.3-10742.6" - wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:10943.3-10967.6" - wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LDST_dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LDST_dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LDST_dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LDST_dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LDST_dec31_dec_sub20_upd - attribute \src "libresoc.v:10487.7-10487.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:10487.7-10487.20" - process $proc$libresoc.v:10487$223 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:10668.3-10692.6" - process $proc$libresoc.v:10668$210 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_function_unit[11:0] $1\LDST_dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:10669.5-10669.29" - switch \initial - attribute \src "libresoc.v:10669.9-10669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[11:0] - end - attribute \src "libresoc.v:10693.3-10717.6" - process $proc$libresoc.v:10693$211 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:10694.5-10694.29" - switch \initial - attribute \src "libresoc.v:10694.9-10694.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 - case - assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] - end - attribute \src "libresoc.v:10718.3-10742.6" - process $proc$libresoc.v:10718$212 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:10719.5-10719.29" - switch \initial - attribute \src "libresoc.v:10719.9-10719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] - end - attribute \src "libresoc.v:10743.3-10767.6" - process $proc$libresoc.v:10743$213 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:10744.5-10744.29" - switch \initial - attribute \src "libresoc.v:10744.9-10744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] - end - attribute \src "libresoc.v:10768.3-10792.6" - process $proc$libresoc.v:10768$214 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:10769.5-10769.29" - switch \initial - attribute \src "libresoc.v:10769.9-10769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] - end - attribute \src "libresoc.v:10793.3-10817.6" - process $proc$libresoc.v:10793$215 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:10794.5-10794.29" - switch \initial - attribute \src "libresoc.v:10794.9-10794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 - case - assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] - end - attribute \src "libresoc.v:10818.3-10842.6" - process $proc$libresoc.v:10818$216 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:10819.5-10819.29" - switch \initial - attribute \src "libresoc.v:10819.9-10819.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] - end - attribute \src "libresoc.v:10843.3-10867.6" - process $proc$libresoc.v:10843$217 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:10844.5-10844.29" - switch \initial - attribute \src "libresoc.v:10844.9-10844.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 - case - assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] - end - attribute \src "libresoc.v:10868.3-10892.6" - process $proc$libresoc.v:10868$218 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:10869.5-10869.29" - switch \initial - attribute \src "libresoc.v:10869.9-10869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] - end - attribute \src "libresoc.v:10893.3-10917.6" - process $proc$libresoc.v:10893$219 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:10894.5-10894.29" - switch \initial - attribute \src "libresoc.v:10894.9-10894.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] - end - attribute \src "libresoc.v:10918.3-10942.6" - process $proc$libresoc.v:10918$220 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:10919.5-10919.29" - switch \initial - attribute \src "libresoc.v:10919.9-10919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 - case - assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] - end - attribute \src "libresoc.v:10943.3-10967.6" - process $proc$libresoc.v:10943$221 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:10944.5-10944.29" - switch \initial - attribute \src "libresoc.v:10944.9-10944.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] - end - attribute \src "libresoc.v:10968.3-10992.6" - process $proc$libresoc.v:10968$222 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:10969.5-10969.29" - switch \initial - attribute \src "libresoc.v:10969.9-10969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:10998.1-11818.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" -attribute \generator "nMigen" -module \LDST_dec31_dec_sub21 - attribute \src "libresoc.v:11229.3-11277.6" - wire $0\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11572.3-11620.6" - wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11621.3-11669.6" - wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11180.3-11228.6" - wire width 12 $0\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:11474.3-11522.6" - wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11523.3-11571.6" - wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11425.3-11473.6" - wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11327.3-11375.6" - wire $0\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11670.3-11718.6" - wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11768.3-11816.6" - wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11376.3-11424.6" - wire $0\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11278.3-11326.6" - wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11719.3-11767.6" - wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:10999.7-10999.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:11229.3-11277.6" - wire $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11572.3-11620.6" - wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11621.3-11669.6" - wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11180.3-11228.6" - wire width 12 $1\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:11474.3-11522.6" - wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11523.3-11571.6" - wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11425.3-11473.6" - wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11327.3-11375.6" - wire $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11670.3-11718.6" - wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11768.3-11816.6" - wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11376.3-11424.6" - wire $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11278.3-11326.6" - wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11719.3-11767.6" - wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LDST_dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LDST_dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LDST_dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LDST_dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LDST_dec31_dec_sub21_upd - attribute \src "libresoc.v:10999.7-10999.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:10999.7-10999.20" - process $proc$libresoc.v:10999$237 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:11180.3-11228.6" - process $proc$libresoc.v:11180$224 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_function_unit[11:0] $1\LDST_dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:11181.5-11181.29" - switch \initial - attribute \src "libresoc.v:11181.9-11181.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[11:0] - end - attribute \src "libresoc.v:11229.3-11277.6" - process $proc$libresoc.v:11229$225 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:11230.5-11230.29" - switch \initial - attribute \src "libresoc.v:11230.9-11230.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] - end - attribute \src "libresoc.v:11278.3-11326.6" - process $proc$libresoc.v:11278$226 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:11279.5-11279.29" - switch \initial - attribute \src "libresoc.v:11279.9-11279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] - end - attribute \src "libresoc.v:11327.3-11375.6" - process $proc$libresoc.v:11327$227 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:11328.5-11328.29" - switch \initial - attribute \src "libresoc.v:11328.9-11328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] - end - attribute \src "libresoc.v:11376.3-11424.6" - process $proc$libresoc.v:11376$228 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:11377.5-11377.29" - switch \initial - attribute \src "libresoc.v:11377.9-11377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] - end - attribute \src "libresoc.v:11425.3-11473.6" - process $proc$libresoc.v:11425$229 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:11426.5-11426.29" - switch \initial - attribute \src "libresoc.v:11426.9-11426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 - case - assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] - end - attribute \src "libresoc.v:11474.3-11522.6" - process $proc$libresoc.v:11474$230 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:11475.5-11475.29" - switch \initial - attribute \src "libresoc.v:11475.9-11475.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] - end - attribute \src "libresoc.v:11523.3-11571.6" - process $proc$libresoc.v:11523$231 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:11524.5-11524.29" - switch \initial - attribute \src "libresoc.v:11524.9-11524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 - case - assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] - end - attribute \src "libresoc.v:11572.3-11620.6" - process $proc$libresoc.v:11572$232 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:11573.5-11573.29" - switch \initial - attribute \src "libresoc.v:11573.9-11573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] - end - attribute \src "libresoc.v:11621.3-11669.6" - process $proc$libresoc.v:11621$233 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:11622.5-11622.29" - switch \initial - attribute \src "libresoc.v:11622.9-11622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] - end - attribute \src "libresoc.v:11670.3-11718.6" - process $proc$libresoc.v:11670$234 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:11671.5-11671.29" - switch \initial - attribute \src "libresoc.v:11671.9-11671.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 - case - assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] - end - attribute \src "libresoc.v:11719.3-11767.6" - process $proc$libresoc.v:11719$235 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:11720.5-11720.29" - switch \initial - attribute \src "libresoc.v:11720.9-11720.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 - case - assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] - end - attribute \src "libresoc.v:11768.3-11816.6" - process $proc$libresoc.v:11768$236 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:11769.5-11769.29" - switch \initial - attribute \src "libresoc.v:11769.9-11769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:11822.1-12408.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" -attribute \generator "nMigen" -module \LDST_dec31_dec_sub22 - attribute \src "libresoc.v:12035.3-12065.6" - wire $0\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12252.3-12282.6" - wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12283.3-12313.6" - wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12004.3-12034.6" - wire width 12 $0\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:12190.3-12220.6" - wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12221.3-12251.6" - wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12159.3-12189.6" - wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12097.3-12127.6" - wire $0\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12314.3-12344.6" - wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12376.3-12406.6" - wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12128.3-12158.6" - wire $0\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12066.3-12096.6" - wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12345.3-12375.6" - wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:11823.7-11823.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:12035.3-12065.6" - wire $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12252.3-12282.6" - wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12283.3-12313.6" - wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12004.3-12034.6" - wire width 12 $1\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:12190.3-12220.6" - wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12221.3-12251.6" - wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12159.3-12189.6" - wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12097.3-12127.6" - wire $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12314.3-12344.6" - wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12376.3-12406.6" - wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12128.3-12158.6" - wire $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12066.3-12096.6" - wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12345.3-12375.6" - wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LDST_dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LDST_dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LDST_dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LDST_dec31_dec_sub22_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LDST_dec31_dec_sub22_upd - attribute \src "libresoc.v:11823.7-11823.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:11823.7-11823.20" - process $proc$libresoc.v:11823$251 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:12004.3-12034.6" - process $proc$libresoc.v:12004$238 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_function_unit[11:0] $1\LDST_dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:12005.5-12005.29" - switch \initial - attribute \src "libresoc.v:12005.9-12005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[11:0] - end - attribute \src "libresoc.v:12035.3-12065.6" - process $proc$libresoc.v:12035$239 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:12036.5-12036.29" - switch \initial - attribute \src "libresoc.v:12036.9-12036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] - end - attribute \src "libresoc.v:12066.3-12096.6" - process $proc$libresoc.v:12066$240 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:12067.5-12067.29" - switch \initial - attribute \src "libresoc.v:12067.9-12067.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] - end - attribute \src "libresoc.v:12097.3-12127.6" - process $proc$libresoc.v:12097$241 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:12098.5-12098.29" - switch \initial - attribute \src "libresoc.v:12098.9-12098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] - end - attribute \src "libresoc.v:12128.3-12158.6" - process $proc$libresoc.v:12128$242 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:12129.5-12129.29" - switch \initial - attribute \src "libresoc.v:12129.9-12129.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] - end - attribute \src "libresoc.v:12159.3-12189.6" - process $proc$libresoc.v:12159$243 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:12160.5-12160.29" - switch \initial - attribute \src "libresoc.v:12160.9-12160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 - case - assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] - end - attribute \src "libresoc.v:12190.3-12220.6" - process $proc$libresoc.v:12190$244 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:12191.5-12191.29" - switch \initial - attribute \src "libresoc.v:12191.9-12191.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] - end - attribute \src "libresoc.v:12221.3-12251.6" - process $proc$libresoc.v:12221$245 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:12222.5-12222.29" - switch \initial - attribute \src "libresoc.v:12222.9-12222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 - case - assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] - end - attribute \src "libresoc.v:12252.3-12282.6" - process $proc$libresoc.v:12252$246 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:12253.5-12253.29" - switch \initial - attribute \src "libresoc.v:12253.9-12253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] - end - attribute \src "libresoc.v:12283.3-12313.6" - process $proc$libresoc.v:12283$247 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:12284.5-12284.29" - switch \initial - attribute \src "libresoc.v:12284.9-12284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] - end - attribute \src "libresoc.v:12314.3-12344.6" - process $proc$libresoc.v:12314$248 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:12315.5-12315.29" - switch \initial - attribute \src "libresoc.v:12315.9-12315.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 - case - assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] - end - attribute \src "libresoc.v:12345.3-12375.6" - process $proc$libresoc.v:12345$249 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:12346.5-12346.29" - switch \initial - attribute \src "libresoc.v:12346.9-12346.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] - end - attribute \src "libresoc.v:12376.3-12406.6" - process $proc$libresoc.v:12376$250 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:12377.5-12377.29" - switch \initial - attribute \src "libresoc.v:12377.9-12377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:12412.1-13232.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" -attribute \generator "nMigen" -module \LDST_dec31_dec_sub23 - attribute \src "libresoc.v:12643.3-12691.6" - wire $0\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:12986.3-13034.6" - wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:13035.3-13083.6" - wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:12594.3-12642.6" - wire width 12 $0\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:12888.3-12936.6" - wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:12937.3-12985.6" - wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12839.3-12887.6" - wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12741.3-12789.6" - wire $0\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:13084.3-13132.6" - wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13182.3-13230.6" - wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:12790.3-12838.6" - wire $0\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12692.3-12740.6" - wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:13133.3-13181.6" - wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:12413.7-12413.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:12643.3-12691.6" - wire $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:12986.3-13034.6" - wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:13035.3-13083.6" - wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:12594.3-12642.6" - wire width 12 $1\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:12888.3-12936.6" - wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:12937.3-12985.6" - wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12839.3-12887.6" - wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12741.3-12789.6" - wire $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:13084.3-13132.6" - wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13182.3-13230.6" - wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:12790.3-12838.6" - wire $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12692.3-12740.6" - wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:13133.3-13181.6" - wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LDST_dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LDST_dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LDST_dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LDST_dec31_dec_sub23_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LDST_dec31_dec_sub23_upd - attribute \src "libresoc.v:12413.7-12413.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:12413.7-12413.20" - process $proc$libresoc.v:12413$265 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:12594.3-12642.6" - process $proc$libresoc.v:12594$252 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_function_unit[11:0] $1\LDST_dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:12595.5-12595.29" - switch \initial - attribute \src "libresoc.v:12595.9-12595.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[11:0] - end - attribute \src "libresoc.v:12643.3-12691.6" - process $proc$libresoc.v:12643$253 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:12644.5-12644.29" - switch \initial - attribute \src "libresoc.v:12644.9-12644.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] - end - attribute \src "libresoc.v:12692.3-12740.6" - process $proc$libresoc.v:12692$254 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:12693.5-12693.29" - switch \initial - attribute \src "libresoc.v:12693.9-12693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] - end - attribute \src "libresoc.v:12741.3-12789.6" - process $proc$libresoc.v:12741$255 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:12742.5-12742.29" - switch \initial - attribute \src "libresoc.v:12742.9-12742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] - end - attribute \src "libresoc.v:12790.3-12838.6" - process $proc$libresoc.v:12790$256 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:12791.5-12791.29" - switch \initial - attribute \src "libresoc.v:12791.9-12791.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - case - assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 - end - sync always - update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] - end - attribute \src "libresoc.v:12839.3-12887.6" - process $proc$libresoc.v:12839$257 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:12840.5-12840.29" - switch \initial - attribute \src "libresoc.v:12840.9-12840.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 - case - assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] - end - attribute \src "libresoc.v:12888.3-12936.6" - process $proc$libresoc.v:12888$258 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:12889.5-12889.29" - switch \initial - attribute \src "libresoc.v:12889.9-12889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] - end - attribute \src "libresoc.v:12937.3-12985.6" - process $proc$libresoc.v:12937$259 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:12938.5-12938.29" - switch \initial - attribute \src "libresoc.v:12938.9-12938.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 - case - assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] - end - attribute \src "libresoc.v:12986.3-13034.6" - process $proc$libresoc.v:12986$260 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:12987.5-12987.29" - switch \initial - attribute \src "libresoc.v:12987.9-12987.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] - end - attribute \src "libresoc.v:13035.3-13083.6" - process $proc$libresoc.v:13035$261 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:13036.5-13036.29" - switch \initial - attribute \src "libresoc.v:13036.9-13036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - case - assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] - end - attribute \src "libresoc.v:13084.3-13132.6" - process $proc$libresoc.v:13084$262 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:13085.5-13085.29" - switch \initial - attribute \src "libresoc.v:13085.9-13085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 - case - assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] - end - attribute \src "libresoc.v:13133.3-13181.6" - process $proc$libresoc.v:13133$263 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:13134.5-13134.29" - switch \initial - attribute \src "libresoc.v:13134.9-13134.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] - end - attribute \src "libresoc.v:13182.3-13230.6" - process $proc$libresoc.v:13182$264 - assign { } { } - assign { } { } - assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:13183.5-13183.29" - switch \initial - attribute \src "libresoc.v:13183.9-13183.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:13236.1-13627.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" -attribute \generator "nMigen" -module \LDST_dec58 - attribute \src "libresoc.v:13434.3-13449.6" - wire $0\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13546.3-13561.6" - wire width 3 $0\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13562.3-13577.6" - wire width 3 $0\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13418.3-13433.6" - wire width 12 $0\LDST_dec58_function_unit[11:0] - attribute \src "libresoc.v:13514.3-13529.6" - wire width 3 $0\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13530.3-13545.6" - wire width 4 $0\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13498.3-13513.6" - wire width 7 $0\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13466.3-13481.6" - wire $0\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13578.3-13593.6" - wire width 4 $0\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13610.3-13625.6" - wire width 2 $0\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13482.3-13497.6" - wire $0\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13450.3-13465.6" - wire $0\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13594.3-13609.6" - wire width 2 $0\LDST_dec58_upd[1:0] - attribute \src "libresoc.v:13237.7-13237.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:13434.3-13449.6" - wire $1\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13546.3-13561.6" - wire width 3 $1\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13562.3-13577.6" - wire width 3 $1\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13418.3-13433.6" - wire width 12 $1\LDST_dec58_function_unit[11:0] - attribute \src "libresoc.v:13514.3-13529.6" - wire width 3 $1\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13530.3-13545.6" - wire width 4 $1\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13498.3-13513.6" - wire width 7 $1\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13466.3-13481.6" - wire $1\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13578.3-13593.6" - wire width 4 $1\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13610.3-13625.6" - wire width 2 $1\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13482.3-13497.6" - wire $1\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13450.3-13465.6" - wire $1\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13594.3-13609.6" - wire width 2 $1\LDST_dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LDST_dec58_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LDST_dec58_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec58_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LDST_dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LDST_dec58_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LDST_dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LDST_dec58_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LDST_dec58_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LDST_dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LDST_dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LDST_dec58_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LDST_dec58_upd - attribute \src "libresoc.v:13237.7-13237.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:13237.7-13237.20" - process $proc$libresoc.v:13237$279 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:13418.3-13433.6" - process $proc$libresoc.v:13418$266 - assign { } { } - assign { } { } - assign $0\LDST_dec58_function_unit[11:0] $1\LDST_dec58_function_unit[11:0] - attribute \src "libresoc.v:13419.5-13419.29" - switch \initial - attribute \src "libresoc.v:13419.9-13419.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec58_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[11:0] - end - attribute \src "libresoc.v:13434.3-13449.6" - process $proc$libresoc.v:13434$267 - assign { } { } - assign { } { } - assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] - attribute \src "libresoc.v:13435.5-13435.29" - switch \initial - attribute \src "libresoc.v:13435.9-13435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_br[0:0] 1'0 - case - assign $1\LDST_dec58_br[0:0] 1'0 - end - sync always - update \LDST_dec58_br $0\LDST_dec58_br[0:0] - end - attribute \src "libresoc.v:13450.3-13465.6" - process $proc$libresoc.v:13450$268 - assign { } { } - assign { } { } - assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] - attribute \src "libresoc.v:13451.5-13451.29" - switch \initial - attribute \src "libresoc.v:13451.9-13451.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_sgn_ext[0:0] 1'1 - case - assign $1\LDST_dec58_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] - end - attribute \src "libresoc.v:13466.3-13481.6" - process $proc$libresoc.v:13466$269 - assign { } { } - assign { } { } - assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] - attribute \src "libresoc.v:13467.5-13467.29" - switch \initial - attribute \src "libresoc.v:13467.9-13467.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_is_32b[0:0] 1'0 - case - assign $1\LDST_dec58_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] - end - attribute \src "libresoc.v:13482.3-13497.6" - process $proc$libresoc.v:13482$270 - assign { } { } - assign { } { } - assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] - attribute \src "libresoc.v:13483.5-13483.29" - switch \initial - attribute \src "libresoc.v:13483.9-13483.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_sgn[0:0] 1'0 - case - assign $1\LDST_dec58_sgn[0:0] 1'0 - end - sync always - update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] - end - attribute \src "libresoc.v:13498.3-13513.6" - process $proc$libresoc.v:13498$271 - assign { } { } - assign { } { } - assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] - attribute \src "libresoc.v:13499.5-13499.29" - switch \initial - attribute \src "libresoc.v:13499.9-13499.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_internal_op[6:0] 7'0100101 - case - assign $1\LDST_dec58_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] - end - attribute \src "libresoc.v:13514.3-13529.6" - process $proc$libresoc.v:13514$272 - assign { } { } - assign { } { } - assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] - attribute \src "libresoc.v:13515.5-13515.29" - switch \initial - attribute \src "libresoc.v:13515.9-13515.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec58_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] - end - attribute \src "libresoc.v:13530.3-13545.6" - process $proc$libresoc.v:13530$273 - assign { } { } - assign { } { } - assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] - attribute \src "libresoc.v:13531.5-13531.29" - switch \initial - attribute \src "libresoc.v:13531.9-13531.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_in2_sel[3:0] 4'1000 - case - assign $1\LDST_dec58_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] - end - attribute \src "libresoc.v:13546.3-13561.6" - process $proc$libresoc.v:13546$274 - assign { } { } - assign { } { } - assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] - attribute \src "libresoc.v:13547.5-13547.29" - switch \initial - attribute \src "libresoc.v:13547.9-13547.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_cr_in[2:0] 3'000 - case - assign $1\LDST_dec58_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] - end - attribute \src "libresoc.v:13562.3-13577.6" - process $proc$libresoc.v:13562$275 - assign { } { } - assign { } { } - assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] - attribute \src "libresoc.v:13563.5-13563.29" - switch \initial - attribute \src "libresoc.v:13563.9-13563.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_cr_out[2:0] 3'000 - case - assign $1\LDST_dec58_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] - end - attribute \src "libresoc.v:13578.3-13593.6" - process $proc$libresoc.v:13578$276 - assign { } { } - assign { } { } - assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] - attribute \src "libresoc.v:13579.5-13579.29" - switch \initial - attribute \src "libresoc.v:13579.9-13579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_ldst_len[3:0] 4'0100 - case - assign $1\LDST_dec58_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] - end - attribute \src "libresoc.v:13594.3-13609.6" - process $proc$libresoc.v:13594$277 - assign { } { } - assign { } { } - assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] - attribute \src "libresoc.v:13595.5-13595.29" - switch \initial - attribute \src "libresoc.v:13595.9-13595.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_upd[1:0] 2'00 - case - assign $1\LDST_dec58_upd[1:0] 2'00 - end - sync always - update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] - end - attribute \src "libresoc.v:13610.3-13625.6" - process $proc$libresoc.v:13610$278 - assign { } { } - assign { } { } - assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] - attribute \src "libresoc.v:13611.5-13611.29" - switch \initial - attribute \src "libresoc.v:13611.9-13611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\LDST_dec58_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec58_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:13631.1-13983.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" -attribute \generator "nMigen" -module \LDST_dec62 - attribute \src "libresoc.v:13826.3-13838.6" - wire $0\LDST_dec62_br[0:0] - attribute \src "libresoc.v:13917.3-13929.6" - wire width 3 $0\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:13930.3-13942.6" - wire width 3 $0\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13813.3-13825.6" - wire width 12 $0\LDST_dec62_function_unit[11:0] - attribute \src "libresoc.v:13891.3-13903.6" - wire width 3 $0\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:13904.3-13916.6" - wire width 4 $0\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13878.3-13890.6" - wire width 7 $0\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13852.3-13864.6" - wire $0\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:13943.3-13955.6" - wire width 4 $0\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:13969.3-13981.6" - wire width 2 $0\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13865.3-13877.6" - wire $0\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13839.3-13851.6" - wire $0\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:13956.3-13968.6" - wire width 2 $0\LDST_dec62_upd[1:0] - attribute \src "libresoc.v:13632.7-13632.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:13826.3-13838.6" - wire $1\LDST_dec62_br[0:0] - attribute \src "libresoc.v:13917.3-13929.6" - wire width 3 $1\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:13930.3-13942.6" - wire width 3 $1\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13813.3-13825.6" - wire width 12 $1\LDST_dec62_function_unit[11:0] - attribute \src "libresoc.v:13891.3-13903.6" - wire width 3 $1\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:13904.3-13916.6" - wire width 4 $1\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13878.3-13890.6" - wire width 7 $1\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13852.3-13864.6" - wire $1\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:13943.3-13955.6" - wire width 4 $1\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:13969.3-13981.6" - wire width 2 $1\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13865.3-13877.6" - wire $1\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13839.3-13851.6" - wire $1\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:13956.3-13968.6" - wire width 2 $1\LDST_dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LDST_dec62_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LDST_dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LDST_dec62_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LDST_dec62_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LDST_dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LDST_dec62_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LDST_dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LDST_dec62_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LDST_dec62_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LDST_dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LDST_dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LDST_dec62_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LDST_dec62_upd - attribute \src "libresoc.v:13632.7-13632.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 14 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:13632.7-13632.20" - process $proc$libresoc.v:13632$293 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:13813.3-13825.6" - process $proc$libresoc.v:13813$280 - assign { } { } - assign { } { } - assign $0\LDST_dec62_function_unit[11:0] $1\LDST_dec62_function_unit[11:0] - attribute \src "libresoc.v:13814.5-13814.29" - switch \initial - attribute \src "libresoc.v:13814.9-13814.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_dec62_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[11:0] - end - attribute \src "libresoc.v:13826.3-13838.6" - process $proc$libresoc.v:13826$281 - assign { } { } - assign { } { } - assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] - attribute \src "libresoc.v:13827.5-13827.29" - switch \initial - attribute \src "libresoc.v:13827.9-13827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_br[0:0] 1'0 - case - assign $1\LDST_dec62_br[0:0] 1'0 - end - sync always - update \LDST_dec62_br $0\LDST_dec62_br[0:0] - end - attribute \src "libresoc.v:13839.3-13851.6" - process $proc$libresoc.v:13839$282 - assign { } { } - assign { } { } - assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] - attribute \src "libresoc.v:13840.5-13840.29" - switch \initial - attribute \src "libresoc.v:13840.9-13840.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_sgn_ext[0:0] 1'0 - case - assign $1\LDST_dec62_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] - end - attribute \src "libresoc.v:13852.3-13864.6" - process $proc$libresoc.v:13852$283 - assign { } { } - assign { } { } - assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] - attribute \src "libresoc.v:13853.5-13853.29" - switch \initial - attribute \src "libresoc.v:13853.9-13853.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_is_32b[0:0] 1'0 - case - assign $1\LDST_dec62_is_32b[0:0] 1'0 - end - sync always - update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] - end - attribute \src "libresoc.v:13865.3-13877.6" - process $proc$libresoc.v:13865$284 - assign { } { } - assign { } { } - assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] - attribute \src "libresoc.v:13866.5-13866.29" - switch \initial - attribute \src "libresoc.v:13866.9-13866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_sgn[0:0] 1'0 - case - assign $1\LDST_dec62_sgn[0:0] 1'0 - end - sync always - update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] - end - attribute \src "libresoc.v:13878.3-13890.6" - process $proc$libresoc.v:13878$285 - assign { } { } - assign { } { } - assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] - attribute \src "libresoc.v:13879.5-13879.29" - switch \initial - attribute \src "libresoc.v:13879.9-13879.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_internal_op[6:0] 7'0100110 - case - assign $1\LDST_dec62_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] - end - attribute \src "libresoc.v:13891.3-13903.6" - process $proc$libresoc.v:13891$286 - assign { } { } - assign { } { } - assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] - attribute \src "libresoc.v:13892.5-13892.29" - switch \initial - attribute \src "libresoc.v:13892.9-13892.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_in1_sel[2:0] 3'010 - case - assign $1\LDST_dec62_in1_sel[2:0] 3'000 - end - sync always - update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] - end - attribute \src "libresoc.v:13904.3-13916.6" - process $proc$libresoc.v:13904$287 - assign { } { } - assign { } { } - assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] - attribute \src "libresoc.v:13905.5-13905.29" - switch \initial - attribute \src "libresoc.v:13905.9-13905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_in2_sel[3:0] 4'1000 - case - assign $1\LDST_dec62_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] - end - attribute \src "libresoc.v:13917.3-13929.6" - process $proc$libresoc.v:13917$288 - assign { } { } - assign { } { } - assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] - attribute \src "libresoc.v:13918.5-13918.29" - switch \initial - attribute \src "libresoc.v:13918.9-13918.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_cr_in[2:0] 3'000 - case - assign $1\LDST_dec62_cr_in[2:0] 3'000 - end - sync always - update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] - end - attribute \src "libresoc.v:13930.3-13942.6" - process $proc$libresoc.v:13930$289 - assign { } { } - assign { } { } - assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] - attribute \src "libresoc.v:13931.5-13931.29" - switch \initial - attribute \src "libresoc.v:13931.9-13931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_cr_out[2:0] 3'000 - case - assign $1\LDST_dec62_cr_out[2:0] 3'000 - end - sync always - update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] - end - attribute \src "libresoc.v:13943.3-13955.6" - process $proc$libresoc.v:13943$290 - assign { } { } - assign { } { } - assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] - attribute \src "libresoc.v:13944.5-13944.29" - switch \initial - attribute \src "libresoc.v:13944.9-13944.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_ldst_len[3:0] 4'1000 - case - assign $1\LDST_dec62_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] - end - attribute \src "libresoc.v:13956.3-13968.6" - process $proc$libresoc.v:13956$291 - assign { } { } - assign { } { } - assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] - attribute \src "libresoc.v:13957.5-13957.29" - switch \initial - attribute \src "libresoc.v:13957.9-13957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_upd[1:0] 2'01 - case - assign $1\LDST_dec62_upd[1:0] 2'00 - end - sync always - update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] - end - attribute \src "libresoc.v:13969.3-13981.6" - process $proc$libresoc.v:13969$292 - assign { } { } - assign { } { } - assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] - attribute \src "libresoc.v:13970.5-13970.29" - switch \initial - attribute \src "libresoc.v:13970.9-13970.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\LDST_dec62_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\LDST_dec62_rc_sel[1:0] 2'00 - case - assign $1\LDST_dec62_rc_sel[1:0] 2'00 - end - sync always - update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:13987.1-14725.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" -attribute \generator "nMigen" -module \LOGICAL_dec31 - attribute \src "libresoc.v:14695.3-14707.6" - wire width 3 $0\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14708.3-14720.6" - wire width 3 $0\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14565.3-14577.6" - wire width 2 $0\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14604.3-14616.6" - wire $0\LOGICAL_dec31_cry_out[0:0] - attribute \src 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\LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out - connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out - connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit - connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel - connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel - connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b - connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len - connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:14522.27-14538.4" - cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 - connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in - connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out - connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out - connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit - connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel - connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel - connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b - connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len - connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in - end - attribute \src "libresoc.v:13988.7-13988.20" - process $proc$libresoc.v:13988$308 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:14539.3-14551.6" - process $proc$libresoc.v:14539$294 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] - attribute \src "libresoc.v:14540.5-14540.29" - switch \initial - attribute \src "libresoc.v:14540.9-14540.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len - case - assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] - end - attribute \src "libresoc.v:14552.3-14564.6" - process $proc$libresoc.v:14552$295 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:14553.5-14553.29" - switch \initial - attribute \src "libresoc.v:14553.9-14553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel - case - assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:14565.3-14577.6" - process $proc$libresoc.v:14565$296 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] - attribute \src "libresoc.v:14566.5-14566.29" - switch \initial - attribute \src "libresoc.v:14566.9-14566.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in - case - assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] - end - attribute \src "libresoc.v:14578.3-14590.6" - process $proc$libresoc.v:14578$297 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] - attribute \src "libresoc.v:14579.5-14579.29" - switch \initial - attribute \src "libresoc.v:14579.9-14579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a - case - assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] - end - attribute \src "libresoc.v:14591.3-14603.6" - process $proc$libresoc.v:14591$298 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] - attribute \src "libresoc.v:14592.5-14592.29" - switch \initial - attribute \src "libresoc.v:14592.9-14592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out - case - assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] - end - attribute \src "libresoc.v:14604.3-14616.6" - process $proc$libresoc.v:14604$299 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] - attribute \src "libresoc.v:14605.5-14605.29" - switch \initial - attribute \src "libresoc.v:14605.9-14605.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out - case - assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] - end - attribute \src "libresoc.v:14617.3-14629.6" - process $proc$libresoc.v:14617$300 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] - attribute \src "libresoc.v:14618.5-14618.29" - switch \initial - attribute \src "libresoc.v:14618.9-14618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b - case - assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] - end - attribute \src "libresoc.v:14630.3-14642.6" - process $proc$libresoc.v:14630$301 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] - attribute \src "libresoc.v:14631.5-14631.29" - switch \initial - attribute \src "libresoc.v:14631.9-14631.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn - case - assign $1\LOGICAL_dec31_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] - end - attribute \src "libresoc.v:14643.3-14655.6" - process $proc$libresoc.v:14643$302 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_function_unit[11:0] $1\LOGICAL_dec31_function_unit[11:0] - attribute \src "libresoc.v:14644.5-14644.29" - switch \initial - attribute \src "libresoc.v:14644.9-14644.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit - case - assign $1\LOGICAL_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[11:0] - end - attribute \src "libresoc.v:14656.3-14668.6" - process $proc$libresoc.v:14656$303 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] - attribute \src "libresoc.v:14657.5-14657.29" - switch \initial - attribute \src "libresoc.v:14657.9-14657.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op - case - assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:14669.3-14681.6" - process $proc$libresoc.v:14669$304 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] - attribute \src "libresoc.v:14670.5-14670.29" - switch \initial - attribute \src "libresoc.v:14670.9-14670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel - case - assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] - end - attribute \src "libresoc.v:14682.3-14694.6" - process $proc$libresoc.v:14682$305 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:14683.5-14683.29" - switch \initial - attribute \src "libresoc.v:14683.9-14683.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel - case - assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:14695.3-14707.6" - process $proc$libresoc.v:14695$306 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] - attribute \src "libresoc.v:14696.5-14696.29" - switch \initial - attribute \src "libresoc.v:14696.9-14696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in - case - assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:14708.3-14720.6" - process $proc$libresoc.v:14708$307 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] - attribute \src "libresoc.v:14709.5-14709.29" - switch \initial - attribute \src "libresoc.v:14709.9-14709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out - case - assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] - end - connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in - connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:14729.1-15390.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" -attribute \generator "nMigen" -module \LOGICAL_dec31_dec_sub26 - attribute \src "libresoc.v:15219.3-15252.6" - wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15253.3-15286.6" - wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15355.3-15388.6" - wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15015.3-15048.6" - wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:14913.3-14946.6" - wire width 12 $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:15151.3-15184.6" - wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15185.3-15218.6" - wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15117.3-15150.6" - wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:14947.3-14980.6" - wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:14981.3-15014.6" - wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:15049.3-15082.6" - wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15287.3-15320.6" - wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15321.3-15354.6" - wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15083.3-15116.6" - wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:14730.7-14730.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:15219.3-15252.6" - wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15253.3-15286.6" - wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15355.3-15388.6" - wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15015.3-15048.6" - wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:14913.3-14946.6" - wire width 12 $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:15151.3-15184.6" - wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15185.3-15218.6" - wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15117.3-15150.6" - wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:14947.3-14980.6" - wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:14981.3-15014.6" - wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:15049.3-15082.6" - wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15287.3-15320.6" - wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15321.3-15354.6" - wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15083.3-15116.6" - wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LOGICAL_dec31_dec_sub26_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LOGICAL_dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LOGICAL_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LOGICAL_dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LOGICAL_dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \LOGICAL_dec31_dec_sub26_sgn - attribute \src "libresoc.v:14730.7-14730.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:14730.7-14730.20" - process $proc$libresoc.v:14730$323 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:14913.3-14946.6" - process $proc$libresoc.v:14913$309 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:14914.5-14914.29" - switch \initial - attribute \src "libresoc.v:14914.9-14914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 - case - assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] - end - attribute \src "libresoc.v:14947.3-14980.6" - process $proc$libresoc.v:14947$310 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:14948.5-14948.29" - switch \initial - attribute \src "libresoc.v:14948.9-14948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] - end - attribute \src "libresoc.v:14981.3-15014.6" - process $proc$libresoc.v:14981$311 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:14982.5-14982.29" - switch \initial - attribute \src "libresoc.v:14982.9-14982.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] - end - attribute \src "libresoc.v:15015.3-15048.6" - process $proc$libresoc.v:15015$312 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:15016.5-15016.29" - switch \initial - attribute \src "libresoc.v:15016.9-15016.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] - end - attribute \src "libresoc.v:15049.3-15082.6" - process $proc$libresoc.v:15049$313 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:15050.5-15050.29" - switch \initial - attribute \src "libresoc.v:15050.9-15050.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] - end - attribute \src "libresoc.v:15083.3-15116.6" - process $proc$libresoc.v:15083$314 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:15084.5-15084.29" - switch \initial - attribute \src "libresoc.v:15084.9-15084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] - end - attribute \src "libresoc.v:15117.3-15150.6" - process $proc$libresoc.v:15117$315 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:15118.5-15118.29" - switch \initial - attribute \src "libresoc.v:15118.9-15118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 - case - assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] - end - attribute \src "libresoc.v:15151.3-15184.6" - process $proc$libresoc.v:15151$316 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:15152.5-15152.29" - switch \initial - attribute \src "libresoc.v:15152.9-15152.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 - case - assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] - end - attribute \src "libresoc.v:15185.3-15218.6" - process $proc$libresoc.v:15185$317 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:15186.5-15186.29" - switch \initial - attribute \src "libresoc.v:15186.9-15186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - case - assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "libresoc.v:15219.3-15252.6" - process $proc$libresoc.v:15219$318 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:15220.5-15220.29" - switch \initial - attribute \src "libresoc.v:15220.9-15220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] - end - attribute \src "libresoc.v:15253.3-15286.6" - process $proc$libresoc.v:15253$319 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:15254.5-15254.29" - switch \initial - attribute \src "libresoc.v:15254.9-15254.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - case - assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] - end - attribute \src "libresoc.v:15287.3-15320.6" - process $proc$libresoc.v:15287$320 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:15288.5-15288.29" - switch \initial - attribute \src "libresoc.v:15288.9-15288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 - case - assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] - end - attribute \src "libresoc.v:15321.3-15354.6" - process $proc$libresoc.v:15321$321 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:15322.5-15322.29" - switch \initial - attribute \src "libresoc.v:15322.9-15322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - case - assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "libresoc.v:15355.3-15388.6" - process $proc$libresoc.v:15355$322 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:15356.5-15356.29" - switch \initial - attribute \src "libresoc.v:15356.9-15356.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:15394.1-16097.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" -attribute \generator "nMigen" -module \LOGICAL_dec31_dec_sub28 - attribute \src "libresoc.v:15911.3-15947.6" - wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:15948.3-15984.6" - wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:16059.3-16095.6" - wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:15689.3-15725.6" - wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15578.3-15614.6" - wire width 12 $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:15837.3-15873.6" - wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:15874.3-15910.6" - wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15800.3-15836.6" - wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15615.3-15651.6" - wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15652.3-15688.6" - wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15726.3-15762.6" - wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:15985.3-16021.6" - wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:16022.3-16058.6" - wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:15763.3-15799.6" - wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:15395.7-15395.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:15911.3-15947.6" - wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:15948.3-15984.6" - wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:16059.3-16095.6" - wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:15689.3-15725.6" - wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15578.3-15614.6" - wire width 12 $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:15837.3-15873.6" - wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:15874.3-15910.6" - wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15800.3-15836.6" - wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15615.3-15651.6" - wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15652.3-15688.6" - wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15726.3-15762.6" - wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:15985.3-16021.6" - wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:16022.3-16058.6" - wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:15763.3-15799.6" - wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \LOGICAL_dec31_dec_sub28_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \LOGICAL_dec31_dec_sub28_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \LOGICAL_dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \LOGICAL_dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \LOGICAL_dec31_dec_sub28_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \LOGICAL_dec31_dec_sub28_sgn - attribute \src "libresoc.v:15395.7-15395.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 15 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:15395.7-15395.20" - process $proc$libresoc.v:15395$338 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:15578.3-15614.6" - process $proc$libresoc.v:15578$324 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:15579.5-15579.29" - switch \initial - attribute \src "libresoc.v:15579.9-15579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 - case - assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] - end - attribute \src "libresoc.v:15615.3-15651.6" - process $proc$libresoc.v:15615$325 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:15616.5-15616.29" - switch \initial - attribute \src "libresoc.v:15616.9-15616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] - end - attribute \src "libresoc.v:15652.3-15688.6" - process $proc$libresoc.v:15652$326 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:15653.5-15653.29" - switch \initial - attribute \src "libresoc.v:15653.9-15653.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] - end - attribute \src "libresoc.v:15689.3-15725.6" - process $proc$libresoc.v:15689$327 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:15690.5-15690.29" - switch \initial - attribute \src "libresoc.v:15690.9-15690.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] - end - attribute \src "libresoc.v:15726.3-15762.6" - process $proc$libresoc.v:15726$328 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:15727.5-15727.29" - switch \initial - attribute \src "libresoc.v:15727.9-15727.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] - end - attribute \src "libresoc.v:15763.3-15799.6" - process $proc$libresoc.v:15763$329 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:15764.5-15764.29" - switch \initial - attribute \src "libresoc.v:15764.9-15764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - case - assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] - end - attribute \src "libresoc.v:15800.3-15836.6" - process $proc$libresoc.v:15800$330 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:15801.5-15801.29" - switch \initial - attribute \src "libresoc.v:15801.9-15801.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 - case - assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] - end - attribute \src "libresoc.v:15837.3-15873.6" - process $proc$libresoc.v:15837$331 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:15838.5-15838.29" - switch \initial - attribute \src "libresoc.v:15838.9-15838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 - case - assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] - end - attribute \src "libresoc.v:15874.3-15910.6" - process $proc$libresoc.v:15874$332 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:15875.5-15875.29" - switch \initial - attribute \src "libresoc.v:15875.9-15875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 - case - assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] - end - attribute \src "libresoc.v:15911.3-15947.6" - process $proc$libresoc.v:15911$333 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:15912.5-15912.29" - switch \initial - attribute \src "libresoc.v:15912.9-15912.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - case - assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] - end - attribute \src "libresoc.v:15948.3-15984.6" - process $proc$libresoc.v:15948$334 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:15949.5-15949.29" - switch \initial - attribute \src "libresoc.v:15949.9-15949.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 - case - assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] - end - attribute \src "libresoc.v:15985.3-16021.6" - process $proc$libresoc.v:15985$335 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:15986.5-15986.29" - switch \initial - attribute \src "libresoc.v:15986.9-15986.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - case - assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] - end - attribute \src "libresoc.v:16022.3-16058.6" - process $proc$libresoc.v:16022$336 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:16023.5-16023.29" - switch \initial - attribute \src "libresoc.v:16023.9-16023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 - case - assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] - end - attribute \src "libresoc.v:16059.3-16095.6" - process $proc$libresoc.v:16059$337 - assign { } { } - assign { } { } - assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:16060.5-16060.29" - switch \initial - attribute \src "libresoc.v:16060.9-16060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - case - assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:16101.1-16659.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" -attribute \generator "nMigen" -module \MUL_dec31 - attribute \src "libresoc.v:16616.3-16628.6" - wire width 3 $0\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16629.3-16641.6" - wire width 3 $0\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16577.3-16589.6" - wire width 12 $0\MUL_dec31_function_unit[11:0] - attribute \src "libresoc.v:16603.3-16615.6" - wire width 4 $0\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16590.3-16602.6" - wire width 7 $0\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16551.3-16563.6" - wire $0\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16642.3-16654.6" - wire width 2 $0\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16564.3-16576.6" - wire $0\MUL_dec31_sgn[0:0] - attribute \src "libresoc.v:16102.7-16102.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:16616.3-16628.6" - wire width 3 $1\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16629.3-16641.6" - wire width 3 $1\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16577.3-16589.6" - wire width 12 $1\MUL_dec31_function_unit[11:0] - attribute \src "libresoc.v:16603.3-16615.6" - wire width 4 $1\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16590.3-16602.6" - wire width 7 $1\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16551.3-16563.6" - wire $1\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16642.3-16654.6" - wire width 2 $1\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16564.3-16576.6" - wire $1\MUL_dec31_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \MUL_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \MUL_dec31_cr_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \MUL_dec31_dec_sub11_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \MUL_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 7 \MUL_dec31_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \MUL_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \MUL_dec31_sgn - attribute \src "libresoc.v:16102.7-16102.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:16529.23-16539.4" - cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 - connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in - connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out - connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit - connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel - connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b - connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - connect \opcode_in \MUL_dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:16540.22-16550.4" - cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 - connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in - connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out - connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit - connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel - connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b - connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - connect \opcode_in \MUL_dec31_dec_sub9_opcode_in - end - attribute \src "libresoc.v:16102.7-16102.20" - process $proc$libresoc.v:16102$347 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:16551.3-16563.6" - process $proc$libresoc.v:16551$339 - assign { } { } - assign { } { } - assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] - attribute \src "libresoc.v:16552.5-16552.29" - switch \initial - attribute \src "libresoc.v:16552.9-16552.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b - case - assign $1\MUL_dec31_is_32b[0:0] 1'0 - end - sync always - update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] - end - attribute \src "libresoc.v:16564.3-16576.6" - process $proc$libresoc.v:16564$340 - assign { } { } - assign { } { } - assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] - attribute \src "libresoc.v:16565.5-16565.29" - switch \initial - attribute \src "libresoc.v:16565.9-16565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn - case - assign $1\MUL_dec31_sgn[0:0] 1'0 - end - sync always - update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] - end - attribute \src "libresoc.v:16577.3-16589.6" - process $proc$libresoc.v:16577$341 - assign { } { } - assign { } { } - assign $0\MUL_dec31_function_unit[11:0] $1\MUL_dec31_function_unit[11:0] - attribute \src "libresoc.v:16578.5-16578.29" - switch \initial - attribute \src "libresoc.v:16578.9-16578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit - case - assign $1\MUL_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[11:0] - end - attribute \src "libresoc.v:16590.3-16602.6" - process $proc$libresoc.v:16590$342 - assign { } { } - assign { } { } - assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] - attribute \src "libresoc.v:16591.5-16591.29" - switch \initial - attribute \src "libresoc.v:16591.9-16591.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op - case - assign $1\MUL_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:16603.3-16615.6" - process $proc$libresoc.v:16603$343 - assign { } { } - assign { } { } - assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] - attribute \src "libresoc.v:16604.5-16604.29" - switch \initial - attribute \src "libresoc.v:16604.9-16604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel - case - assign $1\MUL_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:16616.3-16628.6" - process $proc$libresoc.v:16616$344 - assign { } { } - assign { } { } - assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] - attribute \src "libresoc.v:16617.5-16617.29" - switch \initial - attribute \src "libresoc.v:16617.9-16617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in - case - assign $1\MUL_dec31_cr_in[2:0] 3'000 - end - sync always - update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:16629.3-16641.6" - process $proc$libresoc.v:16629$345 - assign { } { } - assign { } { } - assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] - attribute \src "libresoc.v:16630.5-16630.29" - switch \initial - attribute \src "libresoc.v:16630.9-16630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out - case - assign $1\MUL_dec31_cr_out[2:0] 3'000 - end - sync always - update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] - end - attribute \src "libresoc.v:16642.3-16654.6" - process $proc$libresoc.v:16642$346 - assign { } { } - assign { } { } - assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] - attribute \src "libresoc.v:16643.5-16643.29" - switch \initial - attribute \src "libresoc.v:16643.9-16643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel - case - assign $1\MUL_dec31_rc_sel[1:0] 2'00 - end - sync always - update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] - end - connect \MUL_dec31_dec_sub11_opcode_in \opcode_in - connect \MUL_dec31_dec_sub9_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:16663.1-17014.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" -attribute \generator "nMigen" -module \MUL_dec31_dec_sub11 - attribute \src "libresoc.v:16888.3-16912.6" - wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:16913.3-16937.6" - wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16813.3-16837.6" - wire width 12 $0\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:16863.3-16887.6" - wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16838.3-16862.6" - wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:16963.3-16987.6" - wire $0\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:16938.3-16962.6" - wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:16988.3-17012.6" - wire $0\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:16664.7-16664.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:16888.3-16912.6" - wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:16913.3-16937.6" - wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16813.3-16837.6" - wire width 12 $1\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:16863.3-16887.6" - wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16838.3-16862.6" - wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:16963.3-16987.6" - wire $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:16938.3-16962.6" - wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:16988.3-17012.6" - wire $1\MUL_dec31_dec_sub11_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \MUL_dec31_dec_sub11_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 7 \MUL_dec31_dec_sub11_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \MUL_dec31_dec_sub11_sgn - attribute \src "libresoc.v:16664.7-16664.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:16664.7-16664.20" - process $proc$libresoc.v:16664$356 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:16813.3-16837.6" - process $proc$libresoc.v:16813$348 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_function_unit[11:0] $1\MUL_dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:16814.5-16814.29" - switch \initial - attribute \src "libresoc.v:16814.9-16814.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 - case - assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[11:0] - end - attribute \src "libresoc.v:16838.3-16862.6" - process $proc$libresoc.v:16838$349 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:16839.5-16839.29" - switch \initial - attribute \src "libresoc.v:16839.9-16839.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 - case - assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] - end - attribute \src "libresoc.v:16863.3-16887.6" - process $proc$libresoc.v:16863$350 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:16864.5-16864.29" - switch \initial - attribute \src "libresoc.v:16864.9-16864.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 - case - assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] - end - attribute \src "libresoc.v:16888.3-16912.6" - process $proc$libresoc.v:16888$351 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:16889.5-16889.29" - switch \initial - attribute \src "libresoc.v:16889.9-16889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - case - assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] - end - attribute \src "libresoc.v:16913.3-16937.6" - process $proc$libresoc.v:16913$352 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:16914.5-16914.29" - switch \initial - attribute \src "libresoc.v:16914.9-16914.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 - case - assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] - end - attribute \src "libresoc.v:16938.3-16962.6" - process $proc$libresoc.v:16938$353 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:16939.5-16939.29" - switch \initial - attribute \src "libresoc.v:16939.9-16939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 - case - assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 - end - sync always - update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] - end - attribute \src "libresoc.v:16963.3-16987.6" - process $proc$libresoc.v:16963$354 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:16964.5-16964.29" - switch \initial - attribute \src "libresoc.v:16964.9-16964.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 - case - assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] - end - attribute \src "libresoc.v:16988.3-17012.6" - process $proc$libresoc.v:16988$355 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:16989.5-16989.29" - switch \initial - attribute \src "libresoc.v:16989.9-16989.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 - case - assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:17018.1-17369.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" -attribute \generator "nMigen" -module \MUL_dec31_dec_sub9 - attribute \src "libresoc.v:17243.3-17267.6" - wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17268.3-17292.6" - wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17168.3-17192.6" - wire width 12 $0\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:17218.3-17242.6" - wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17193.3-17217.6" - wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17318.3-17342.6" - wire $0\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17293.3-17317.6" - wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17343.3-17367.6" - wire $0\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:17019.7-17019.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:17243.3-17267.6" - wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17268.3-17292.6" - wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17168.3-17192.6" - wire width 12 $1\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:17218.3-17242.6" - wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17193.3-17217.6" - wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17318.3-17342.6" - wire $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17293.3-17317.6" - wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17343.3-17367.6" - wire $1\MUL_dec31_dec_sub9_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \MUL_dec31_dec_sub9_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 7 \MUL_dec31_dec_sub9_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \MUL_dec31_dec_sub9_sgn - attribute \src "libresoc.v:17019.7-17019.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 9 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:17019.7-17019.20" - process $proc$libresoc.v:17019$365 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:17168.3-17192.6" - process $proc$libresoc.v:17168$357 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_function_unit[11:0] $1\MUL_dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:17169.5-17169.29" - switch \initial - attribute \src "libresoc.v:17169.9-17169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 - case - assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[11:0] - end - attribute \src "libresoc.v:17193.3-17217.6" - process $proc$libresoc.v:17193$358 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:17194.5-17194.29" - switch \initial - attribute \src "libresoc.v:17194.9-17194.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 - case - assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] - end - attribute \src "libresoc.v:17218.3-17242.6" - process $proc$libresoc.v:17218$359 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:17219.5-17219.29" - switch \initial - attribute \src "libresoc.v:17219.9-17219.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] - end - attribute \src "libresoc.v:17243.3-17267.6" - process $proc$libresoc.v:17243$360 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:17244.5-17244.29" - switch \initial - attribute \src "libresoc.v:17244.9-17244.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] - end - attribute \src "libresoc.v:17268.3-17292.6" - process $proc$libresoc.v:17268$361 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:17269.5-17269.29" - switch \initial - attribute \src "libresoc.v:17269.9-17269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 - case - assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] - end - attribute \src "libresoc.v:17293.3-17317.6" - process $proc$libresoc.v:17293$362 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:17294.5-17294.29" - switch \initial - attribute \src "libresoc.v:17294.9-17294.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 - case - assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 - end - sync always - update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] - end - attribute \src "libresoc.v:17318.3-17342.6" - process $proc$libresoc.v:17318$363 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:17319.5-17319.29" - switch \initial - attribute \src "libresoc.v:17319.9-17319.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] - end - attribute \src "libresoc.v:17343.3-17367.6" - process $proc$libresoc.v:17343$364 - assign { } { } - assign { } { } - assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:17344.5-17344.29" - switch \initial - attribute \src "libresoc.v:17344.9-17344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 - case - assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 - end - sync always - update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:17373.1-17944.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" -attribute \generator "nMigen" -module \SHIFT_ROT_dec30 - attribute \src "libresoc.v:17721.3-17757.6" - wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17758.3-17794.6" - wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17832.3-17868.6" - wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17906.3-17942.6" - wire $0\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17536.3-17572.6" - wire width 12 $0\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17684.3-17720.6" - wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17647.3-17683.6" - wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17869.3-17905.6" - wire $0\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17573.3-17609.6" - wire $0\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17795.3-17831.6" - wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17610.3-17646.6" - wire $0\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "libresoc.v:17374.7-17374.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:17721.3-17757.6" - wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17758.3-17794.6" - wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17832.3-17868.6" - wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17906.3-17942.6" - wire $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17536.3-17572.6" - wire width 12 $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17684.3-17720.6" - wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17647.3-17683.6" - wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17869.3-17905.6" - wire $1\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17573.3-17609.6" - wire $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17795.3-17831.6" - wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17610.3-17646.6" - wire $1\SHIFT_ROT_dec30_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SHIFT_ROT_dec30_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SHIFT_ROT_dec30_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \SHIFT_ROT_dec30_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec30_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \SHIFT_ROT_dec30_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \SHIFT_ROT_dec30_sgn - attribute \src "libresoc.v:17374.7-17374.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 4 \opcode_switch - attribute \src "libresoc.v:17374.7-17374.20" - process $proc$libresoc.v:17374$377 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:17536.3-17572.6" - process $proc$libresoc.v:17536$366 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_function_unit[11:0] $1\SHIFT_ROT_dec30_function_unit[11:0] - attribute \src "libresoc.v:17537.5-17537.29" - switch \initial - attribute \src "libresoc.v:17537.9-17537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[11:0] - end - attribute \src "libresoc.v:17573.3-17609.6" - process $proc$libresoc.v:17573$367 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] - attribute \src "libresoc.v:17574.5-17574.29" - switch \initial - attribute \src "libresoc.v:17574.9-17574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] - end - attribute \src "libresoc.v:17610.3-17646.6" - process $proc$libresoc.v:17610$368 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] - attribute \src "libresoc.v:17611.5-17611.29" - switch \initial - attribute \src "libresoc.v:17611.9-17611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] - end - attribute \src "libresoc.v:17647.3-17683.6" - process $proc$libresoc.v:17647$369 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] - attribute \src "libresoc.v:17648.5-17648.29" - switch \initial - attribute \src "libresoc.v:17648.9-17648.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 - case - assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] - end - attribute \src "libresoc.v:17684.3-17720.6" - process $proc$libresoc.v:17684$370 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] - attribute \src "libresoc.v:17685.5-17685.29" - switch \initial - attribute \src "libresoc.v:17685.9-17685.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] - end - attribute \src "libresoc.v:17721.3-17757.6" - process $proc$libresoc.v:17721$371 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] - attribute \src "libresoc.v:17722.5-17722.29" - switch \initial - attribute \src "libresoc.v:17722.9-17722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] - end - attribute \src "libresoc.v:17758.3-17794.6" - process $proc$libresoc.v:17758$372 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] - attribute \src "libresoc.v:17759.5-17759.29" - switch \initial - attribute \src "libresoc.v:17759.9-17759.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] - end - attribute \src "libresoc.v:17795.3-17831.6" - process $proc$libresoc.v:17795$373 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] - attribute \src "libresoc.v:17796.5-17796.29" - switch \initial - attribute \src "libresoc.v:17796.9-17796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] - end - attribute \src "libresoc.v:17832.3-17868.6" - process $proc$libresoc.v:17832$374 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] - attribute \src "libresoc.v:17833.5-17833.29" - switch \initial - attribute \src "libresoc.v:17833.9-17833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] - end - attribute \src "libresoc.v:17869.3-17905.6" - process $proc$libresoc.v:17869$375 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] - attribute \src "libresoc.v:17870.5-17870.29" - switch \initial - attribute \src "libresoc.v:17870.9-17870.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] - end - attribute \src "libresoc.v:17906.3-17942.6" - process $proc$libresoc.v:17906$376 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] - attribute \src "libresoc.v:17907.5-17907.29" - switch \initial - attribute \src "libresoc.v:17907.9-17907.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] - end - connect \opcode_switch \opcode_in [4:1] -end -attribute \src "libresoc.v:17948.1-18780.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31 - attribute \src "libresoc.v:18743.3-18758.6" - wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18759.3-18774.6" - wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18615.3-18630.6" - wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18647.3-18662.6" - wire $0\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18695.3-18710.6" - wire width 12 $0\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18727.3-18742.6" - wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18711.3-18726.6" - wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18631.3-18646.6" - wire $0\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18663.3-18678.6" - wire $0\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18599.3-18614.6" - wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18679.3-18694.6" - wire $0\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:17949.7-17949.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:18743.3-18758.6" - wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18759.3-18774.6" - wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18615.3-18630.6" - wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18647.3-18662.6" - wire $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18695.3-18710.6" - wire width 12 $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18727.3-18742.6" - wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18711.3-18726.6" - wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18631.3-18646.6" - wire $1\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18663.3-18678.6" - wire $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18599.3-18614.6" - wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18679.3-18694.6" - wire $1\SHIFT_ROT_dec31_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SHIFT_ROT_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SHIFT_ROT_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \SHIFT_ROT_dec31_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \SHIFT_ROT_dec31_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \SHIFT_ROT_dec31_sgn - attribute \src "libresoc.v:17949.7-17949.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:18557.29-18570.4" - cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 - connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in - connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out - connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out - connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit - connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel - connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - connect \SHIFT_ROT_dec31_dec_sub24_inv_a \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a - connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b - connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:18571.29-18584.4" - cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 - connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in - connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out - connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out - connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit - connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel - connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - connect \SHIFT_ROT_dec31_dec_sub26_inv_a \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a - connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b - connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:18585.29-18598.4" - cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 - connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in - connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out - connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out - connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit - connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel - connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - connect \SHIFT_ROT_dec31_dec_sub27_inv_a \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a - connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b - connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in - end - attribute \src "libresoc.v:17949.7-17949.20" - process $proc$libresoc.v:17949$389 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:18599.3-18614.6" - process $proc$libresoc.v:18599$378 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] - attribute \src "libresoc.v:18600.5-18600.29" - switch \initial - attribute \src "libresoc.v:18600.9-18600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel - case - assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:18615.3-18630.6" - process $proc$libresoc.v:18615$379 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] - attribute \src "libresoc.v:18616.5-18616.29" - switch \initial - attribute \src "libresoc.v:18616.9-18616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in - case - assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] - end - attribute \src "libresoc.v:18631.3-18646.6" - process $proc$libresoc.v:18631$380 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] - attribute \src "libresoc.v:18632.5-18632.29" - switch \initial - attribute \src "libresoc.v:18632.9-18632.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a - case - assign $1\SHIFT_ROT_dec31_inv_a[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] - end - attribute \src "libresoc.v:18647.3-18662.6" - process $proc$libresoc.v:18647$381 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] - attribute \src "libresoc.v:18648.5-18648.29" - switch \initial - attribute \src "libresoc.v:18648.9-18648.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out - case - assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] - end - attribute \src "libresoc.v:18663.3-18678.6" - process $proc$libresoc.v:18663$382 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] - attribute \src "libresoc.v:18664.5-18664.29" - switch \initial - attribute \src "libresoc.v:18664.9-18664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b - case - assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] - end - attribute \src "libresoc.v:18679.3-18694.6" - process $proc$libresoc.v:18679$383 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] - attribute \src "libresoc.v:18680.5-18680.29" - switch \initial - attribute \src "libresoc.v:18680.9-18680.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn - case - assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] - end - attribute \src "libresoc.v:18695.3-18710.6" - process $proc$libresoc.v:18695$384 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_function_unit[11:0] $1\SHIFT_ROT_dec31_function_unit[11:0] - attribute \src "libresoc.v:18696.5-18696.29" - switch \initial - attribute \src "libresoc.v:18696.9-18696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit - case - assign $1\SHIFT_ROT_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[11:0] - end - attribute \src "libresoc.v:18711.3-18726.6" - process $proc$libresoc.v:18711$385 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] - attribute \src "libresoc.v:18712.5-18712.29" - switch \initial - attribute \src "libresoc.v:18712.9-18712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op - case - assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:18727.3-18742.6" - process $proc$libresoc.v:18727$386 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] - attribute \src "libresoc.v:18728.5-18728.29" - switch \initial - attribute \src "libresoc.v:18728.9-18728.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel - case - assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:18743.3-18758.6" - process $proc$libresoc.v:18743$387 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] - attribute \src "libresoc.v:18744.5-18744.29" - switch \initial - attribute \src "libresoc.v:18744.9-18744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in - case - assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:18759.3-18774.6" - process $proc$libresoc.v:18759$388 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] - attribute \src "libresoc.v:18760.5-18760.29" - switch \initial - attribute \src "libresoc.v:18760.9-18760.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out - case - assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] - end - connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in - connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in - connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:18784.1-19157.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31_dec_sub24 - attribute \src "libresoc.v:19042.3-19060.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19061.3-19079.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19099.3-19117.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19137.3-19155.6" - wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:18947.3-18965.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:19023.3-19041.6" - wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19004.3-19022.6" - wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19118.3-19136.6" - wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:18966.3-18984.6" - wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19080.3-19098.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:18985.3-19003.6" - wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:18785.7-18785.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:19042.3-19060.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19061.3-19079.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19099.3-19117.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19137.3-19155.6" - wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:18947.3-18965.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:19023.3-19041.6" - wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19004.3-19022.6" - wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19118.3-19136.6" - wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:18966.3-18984.6" - wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:19080.3-19098.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:18985.3-19003.6" - wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn - attribute \src "libresoc.v:18785.7-18785.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:18785.7-18785.20" - process $proc$libresoc.v:18785$401 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:18947.3-18965.6" - process $proc$libresoc.v:18947$390 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:18948.5-18948.29" - switch \initial - attribute \src "libresoc.v:18948.9-18948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] - end - attribute \src "libresoc.v:18966.3-18984.6" - process $proc$libresoc.v:18966$391 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:18967.5-18967.29" - switch \initial - attribute \src "libresoc.v:18967.9-18967.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] - end - attribute \src "libresoc.v:18985.3-19003.6" - process $proc$libresoc.v:18985$392 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:18986.5-18986.29" - switch \initial - attribute \src "libresoc.v:18986.9-18986.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] - end - attribute \src "libresoc.v:19004.3-19022.6" - process $proc$libresoc.v:19004$393 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:19005.5-19005.29" - switch \initial - attribute \src "libresoc.v:19005.9-19005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] - end - attribute \src "libresoc.v:19023.3-19041.6" - process $proc$libresoc.v:19023$394 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:19024.5-19024.29" - switch \initial - attribute \src "libresoc.v:19024.9-19024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] - end - attribute \src "libresoc.v:19042.3-19060.6" - process $proc$libresoc.v:19042$395 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:19043.5-19043.29" - switch \initial - attribute \src "libresoc.v:19043.9-19043.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] - end - attribute \src "libresoc.v:19061.3-19079.6" - process $proc$libresoc.v:19061$396 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:19062.5-19062.29" - switch \initial - attribute \src "libresoc.v:19062.9-19062.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] - end - attribute \src "libresoc.v:19080.3-19098.6" - process $proc$libresoc.v:19080$397 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:19081.5-19081.29" - switch \initial - attribute \src "libresoc.v:19081.9-19081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] - end - attribute \src "libresoc.v:19099.3-19117.6" - process $proc$libresoc.v:19099$398 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:19100.5-19100.29" - switch \initial - attribute \src "libresoc.v:19100.9-19100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] - end - attribute \src "libresoc.v:19118.3-19136.6" - process $proc$libresoc.v:19118$399 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:19119.5-19119.29" - switch \initial - attribute \src "libresoc.v:19119.9-19119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] - end - attribute \src "libresoc.v:19137.3-19155.6" - process $proc$libresoc.v:19137$400 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:19138.5-19138.29" - switch \initial - attribute \src "libresoc.v:19138.9-19138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:19161.1-19501.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31_dec_sub26 - attribute \src "libresoc.v:19404.3-19419.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19420.3-19435.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19452.3-19467.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19484.3-19499.6" - wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19324.3-19339.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19388.3-19403.6" - wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19372.3-19387.6" - wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19468.3-19483.6" - wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19340.3-19355.6" - wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19436.3-19451.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19356.3-19371.6" - wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19162.7-19162.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:19404.3-19419.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19420.3-19435.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19452.3-19467.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19484.3-19499.6" - wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19324.3-19339.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19388.3-19403.6" - wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19372.3-19387.6" - wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19468.3-19483.6" - wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19340.3-19355.6" - wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19436.3-19451.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19356.3-19371.6" - wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn - attribute \src "libresoc.v:19162.7-19162.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:19162.7-19162.20" - process $proc$libresoc.v:19162$413 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:19324.3-19339.6" - process $proc$libresoc.v:19324$402 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:19325.5-19325.29" - switch \initial - attribute \src "libresoc.v:19325.9-19325.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] - end - attribute \src "libresoc.v:19340.3-19355.6" - process $proc$libresoc.v:19340$403 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:19341.5-19341.29" - switch \initial - attribute \src "libresoc.v:19341.9-19341.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] - end - attribute \src "libresoc.v:19356.3-19371.6" - process $proc$libresoc.v:19356$404 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:19357.5-19357.29" - switch \initial - attribute \src "libresoc.v:19357.9-19357.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] - end - attribute \src "libresoc.v:19372.3-19387.6" - process $proc$libresoc.v:19372$405 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:19373.5-19373.29" - switch \initial - attribute \src "libresoc.v:19373.9-19373.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] - end - attribute \src "libresoc.v:19388.3-19403.6" - process $proc$libresoc.v:19388$406 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:19389.5-19389.29" - switch \initial - attribute \src "libresoc.v:19389.9-19389.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "libresoc.v:19404.3-19419.6" - process $proc$libresoc.v:19404$407 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:19405.5-19405.29" - switch \initial - attribute \src "libresoc.v:19405.9-19405.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] - end - attribute \src "libresoc.v:19420.3-19435.6" - process $proc$libresoc.v:19420$408 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:19421.5-19421.29" - switch \initial - attribute \src "libresoc.v:19421.9-19421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] - end - attribute \src "libresoc.v:19436.3-19451.6" - process $proc$libresoc.v:19436$409 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:19437.5-19437.29" - switch \initial - attribute \src "libresoc.v:19437.9-19437.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "libresoc.v:19452.3-19467.6" - process $proc$libresoc.v:19452$410 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:19453.5-19453.29" - switch \initial - attribute \src "libresoc.v:19453.9-19453.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] - end - attribute \src "libresoc.v:19468.3-19483.6" - process $proc$libresoc.v:19468$411 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:19469.5-19469.29" - switch \initial - attribute \src "libresoc.v:19469.9-19469.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] - end - attribute \src "libresoc.v:19484.3-19499.6" - process $proc$libresoc.v:19484$412 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:19485.5-19485.29" - switch \initial - attribute \src "libresoc.v:19485.9-19485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 - case - assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:19505.1-19878.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" -attribute \generator "nMigen" -module \SHIFT_ROT_dec31_dec_sub27 - attribute \src "libresoc.v:19763.3-19781.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19782.3-19800.6" - wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19820.3-19838.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19858.3-19876.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19668.3-19686.6" - wire width 12 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19744.3-19762.6" - wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19725.3-19743.6" - wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19839.3-19857.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19687.3-19705.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19801.3-19819.6" - wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19706.3-19724.6" - wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19506.7-19506.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:19763.3-19781.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19782.3-19800.6" - wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19820.3-19838.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19858.3-19876.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19668.3-19686.6" - wire width 12 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19744.3-19762.6" - wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19725.3-19743.6" - wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19839.3-19857.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19687.3-19705.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19801.3-19819.6" - wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19706.3-19724.6" - wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn - attribute \src "libresoc.v:19506.7-19506.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 12 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:19506.7-19506.20" - process $proc$libresoc.v:19506$425 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:19668.3-19686.6" - process $proc$libresoc.v:19668$414 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:19669.5-19669.29" - switch \initial - attribute \src "libresoc.v:19669.9-19669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] - end - attribute \src "libresoc.v:19687.3-19705.6" - process $proc$libresoc.v:19687$415 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:19688.5-19688.29" - switch \initial - attribute \src "libresoc.v:19688.9-19688.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] - end - attribute \src "libresoc.v:19706.3-19724.6" - process $proc$libresoc.v:19706$416 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:19707.5-19707.29" - switch \initial - attribute \src "libresoc.v:19707.9-19707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] - end - attribute \src "libresoc.v:19725.3-19743.6" - process $proc$libresoc.v:19725$417 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:19726.5-19726.29" - switch \initial - attribute \src "libresoc.v:19726.9-19726.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] - end - attribute \src "libresoc.v:19744.3-19762.6" - process $proc$libresoc.v:19744$418 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:19745.5-19745.29" - switch \initial - attribute \src "libresoc.v:19745.9-19745.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] - end - attribute \src "libresoc.v:19763.3-19781.6" - process $proc$libresoc.v:19763$419 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:19764.5-19764.29" - switch \initial - attribute \src "libresoc.v:19764.9-19764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] - end - attribute \src "libresoc.v:19782.3-19800.6" - process $proc$libresoc.v:19782$420 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:19783.5-19783.29" - switch \initial - attribute \src "libresoc.v:19783.9-19783.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] - end - attribute \src "libresoc.v:19801.3-19819.6" - process $proc$libresoc.v:19801$421 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:19802.5-19802.29" - switch \initial - attribute \src "libresoc.v:19802.9-19802.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] - end - attribute \src "libresoc.v:19820.3-19838.6" - process $proc$libresoc.v:19820$422 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:19821.5-19821.29" - switch \initial - attribute \src "libresoc.v:19821.9-19821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] - end - attribute \src "libresoc.v:19839.3-19857.6" - process $proc$libresoc.v:19839$423 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:19840.5-19840.29" - switch \initial - attribute \src "libresoc.v:19840.9-19840.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] - end - attribute \src "libresoc.v:19858.3-19876.6" - process $proc$libresoc.v:19858$424 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:19859.5-19859.29" - switch \initial - attribute \src "libresoc.v:19859.9-19859.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:19882.1-20204.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" -attribute \generator "nMigen" -module \SPR_dec31 - attribute \src "libresoc.v:20161.3-20170.6" - wire width 3 $0\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20171.3-20180.6" - wire width 3 $0\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20141.3-20150.6" - wire width 12 $0\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20151.3-20160.6" - wire width 7 $0\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20191.3-20200.6" - wire $0\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20181.3-20190.6" - wire width 2 $0\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:19883.7-19883.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20161.3-20170.6" - wire width 3 $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20171.3-20180.6" - wire width 3 $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20141.3-20150.6" - wire width 12 $1\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20151.3-20160.6" - wire width 7 $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20191.3-20200.6" - wire $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20181.3-20190.6" - wire width 2 $1\SPR_dec31_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \SPR_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SPR_dec31_cr_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \SPR_dec31_dec_sub19_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \SPR_dec31_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \SPR_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 6 \SPR_dec31_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 5 \SPR_dec31_rc_sel - attribute \src "libresoc.v:19883.7-19883.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:20132.23-20140.4" - cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 - connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in - connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out - connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit - connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b - connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - connect \opcode_in \SPR_dec31_dec_sub19_opcode_in - end - attribute \src "libresoc.v:19883.7-19883.20" - process $proc$libresoc.v:19883$432 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20141.3-20150.6" - process $proc$libresoc.v:20141$426 - assign { } { } - assign { } { } - assign $0\SPR_dec31_function_unit[11:0] $1\SPR_dec31_function_unit[11:0] - attribute \src "libresoc.v:20142.5-20142.29" - switch \initial - attribute \src "libresoc.v:20142.9-20142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_function_unit[11:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit - case - assign $1\SPR_dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[11:0] - end - attribute \src "libresoc.v:20151.3-20160.6" - process $proc$libresoc.v:20151$427 - assign { } { } - assign { } { } - assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] - attribute \src "libresoc.v:20152.5-20152.29" - switch \initial - attribute \src "libresoc.v:20152.9-20152.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op - case - assign $1\SPR_dec31_internal_op[6:0] 7'0000000 - end - sync always - update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] - end - attribute \src "libresoc.v:20161.3-20170.6" - process $proc$libresoc.v:20161$428 - assign { } { } - assign { } { } - assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] - attribute \src "libresoc.v:20162.5-20162.29" - switch \initial - attribute \src "libresoc.v:20162.9-20162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in - case - assign $1\SPR_dec31_cr_in[2:0] 3'000 - end - sync always - update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] - end - attribute \src "libresoc.v:20171.3-20180.6" - process $proc$libresoc.v:20171$429 - assign { } { } - assign { } { } - assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] - attribute \src "libresoc.v:20172.5-20172.29" - switch \initial - attribute \src "libresoc.v:20172.9-20172.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out - case - assign $1\SPR_dec31_cr_out[2:0] 3'000 - end - sync always - update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] - end - attribute \src "libresoc.v:20181.3-20190.6" - process $proc$libresoc.v:20181$430 - assign { } { } - assign { } { } - assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] - attribute \src "libresoc.v:20182.5-20182.29" - switch \initial - attribute \src "libresoc.v:20182.9-20182.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel - case - assign $1\SPR_dec31_rc_sel[1:0] 2'00 - end - sync always - update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:20191.3-20200.6" - process $proc$libresoc.v:20191$431 - assign { } { } - assign { } { } - assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] - attribute \src "libresoc.v:20192.5-20192.29" - switch \initial - attribute \src "libresoc.v:20192.9-20192.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b - case - assign $1\SPR_dec31_is_32b[0:0] 1'0 - end - sync always - update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] - end - connect \SPR_dec31_dec_sub19_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:20208.1-20416.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" -attribute \generator "nMigen" -module \SPR_dec31_dec_sub19 - attribute \src "libresoc.v:20363.3-20375.6" - wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20376.3-20388.6" - wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20337.3-20349.6" - wire width 12 $0\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20350.3-20362.6" - wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20402.3-20414.6" - wire $0\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20389.3-20401.6" - wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20209.7-20209.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20363.3-20375.6" - wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20376.3-20388.6" - wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20337.3-20349.6" - wire width 12 $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20350.3-20362.6" - wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20402.3-20414.6" - wire $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20389.3-20401.6" - wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 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\enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 6 \SPR_dec31_dec_sub19_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:20209.7-20209.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 7 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:20209.7-20209.20" - process $proc$libresoc.v:20209$439 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20337.3-20349.6" - process $proc$libresoc.v:20337$433 - assign { } { } - assign { } { } - assign $0\SPR_dec31_dec_sub19_function_unit[11:0] $1\SPR_dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:20338.5-20338.29" - switch \initial - attribute \src "libresoc.v:20338.9-20338.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 - case - assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 - end - sync always - update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[11:0] - end - attribute \src "libresoc.v:20350.3-20362.6" - process $proc$libresoc.v:20350$434 - assign { } { } - assign { } { } - assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:20351.5-20351.29" - switch \initial - attribute \src "libresoc.v:20351.9-20351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 - case - assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 - end - sync always - update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] - end - attribute \src "libresoc.v:20363.3-20375.6" - process $proc$libresoc.v:20363$435 - assign { } { } - assign { } { } - assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:20364.5-20364.29" - switch \initial - attribute \src "libresoc.v:20364.9-20364.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 - case - assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 - end - sync always - update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] - end - attribute \src "libresoc.v:20376.3-20388.6" - process $proc$libresoc.v:20376$436 - assign { } { } - assign { } { } - assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:20377.5-20377.29" - switch \initial - attribute \src "libresoc.v:20377.9-20377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 - case - assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 - end - sync always - update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] - end - attribute \src "libresoc.v:20389.3-20401.6" - process $proc$libresoc.v:20389$437 - assign { } { } - assign { } { } - assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:20390.5-20390.29" - switch \initial - attribute \src "libresoc.v:20390.9-20390.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 - case - assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 - end - sync always - update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] - end - attribute \src "libresoc.v:20402.3-20414.6" - process $proc$libresoc.v:20402$438 - assign { } { } - assign { } { } - assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:20403.5-20403.29" - switch \initial - attribute \src "libresoc.v:20403.9-20403.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 - case - assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 - end - sync always - update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:20420.1-20692.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" -attribute \generator "nMigen" -module \_fsm - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $0\fsm_state$next[3:0]$464 - attribute \src "libresoc.v:20506.3-20507.35" - wire width 4 $0\fsm_state[3:0] - attribute \src "libresoc.v:20421.7-20421.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20512.3-20539.6" - wire $0\isdr$next[0:0]$460 - attribute \src "libresoc.v:20508.3-20509.25" - wire $0\isdr[0:0] - attribute \src "libresoc.v:20655.3-20682.6" - wire $0\isir$next[0:0]$477 - attribute \src "libresoc.v:20510.3-20511.25" - wire $0\isir[0:0] - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $10\fsm_state$next[3:0]$474 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $11\fsm_state$next[3:0]$475 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20461.13-20461.29" - wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:20512.3-20539.6" - wire $1\isdr$next[0:0]$461 - attribute \src "libresoc.v:20466.7-20466.18" - wire $1\isdr[0:0] - attribute \src "libresoc.v:20655.3-20682.6" - wire $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20471.7-20471.18" - wire $1\isir[0:0] - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $2\fsm_state$next[3:0]$466 - attribute \src "libresoc.v:20512.3-20539.6" - wire $2\isdr$next[0:0]$462 - attribute \src "libresoc.v:20655.3-20682.6" - wire $2\isir$next[0:0]$479 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $3\fsm_state$next[3:0]$467 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $4\fsm_state$next[3:0]$468 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $5\fsm_state$next[3:0]$469 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $6\fsm_state$next[3:0]$470 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $7\fsm_state$next[3:0]$471 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $8\fsm_state$next[3:0]$472 - attribute \src "libresoc.v:20540.3-20654.6" - wire width 4 $9\fsm_state$next[3:0]$473 - attribute \src "libresoc.v:20490.17-20490.110" - wire $eq$libresoc.v:20490$440_Y - attribute \src "libresoc.v:20491.18-20491.111" - wire $eq$libresoc.v:20491$441_Y - attribute \src "libresoc.v:20492.18-20492.111" - wire $eq$libresoc.v:20492$442_Y - attribute \src "libresoc.v:20493.18-20493.111" - wire $eq$libresoc.v:20493$443_Y - attribute \src "libresoc.v:20494.18-20494.111" - wire $eq$libresoc.v:20494$444_Y - attribute \src "libresoc.v:20495.17-20495.108" - wire $eq$libresoc.v:20495$445_Y - attribute \src "libresoc.v:20496.18-20496.111" - wire $eq$libresoc.v:20496$446_Y - attribute \src "libresoc.v:20497.18-20497.111" - wire $eq$libresoc.v:20497$447_Y - attribute \src "libresoc.v:20498.18-20498.111" - wire $eq$libresoc.v:20498$448_Y - attribute \src "libresoc.v:20499.18-20499.111" - wire $eq$libresoc.v:20499$449_Y - attribute \src "libresoc.v:20500.18-20500.111" - wire $eq$libresoc.v:20500$450_Y - attribute \src "libresoc.v:20501.18-20501.111" - wire $eq$libresoc.v:20501$451_Y - attribute \src "libresoc.v:20502.18-20502.112" - wire $eq$libresoc.v:20502$452_Y - attribute \src "libresoc.v:20503.17-20503.108" - wire $eq$libresoc.v:20503$453_Y - attribute \src "libresoc.v:20504.17-20504.108" - wire $eq$libresoc.v:20504$454_Y - attribute \src "libresoc.v:20505.17-20505.108" - wire $eq$libresoc.v:20505$455_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 9 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 10 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire output 1 \capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - wire width 4 \fsm_state - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - wire width 4 \fsm_state$next - attribute \src "libresoc.v:20421.7-20421.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire output 11 \isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire \isdr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire output 4 \isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire \isir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" - wire \local_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire output 8 \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire output 6 \negjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire output 7 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire output 5 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" - wire \rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire output 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire output 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:20490$440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20490$440_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:20491$441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20491$441_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - cell $eq $eq$libresoc.v:20492$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20492$442_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - cell $eq $eq$libresoc.v:20493$443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:20493$443_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - cell $eq $eq$libresoc.v:20494$444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20494$444_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" - cell $eq $eq$libresoc.v:20495$445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'0 - connect \Y $eq$libresoc.v:20495$445_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - cell $eq $eq$libresoc.v:20496$446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20496$446_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - cell $eq $eq$libresoc.v:20497$447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20497$447_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - cell $eq $eq$libresoc.v:20498$448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:20498$448_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - cell $eq $eq$libresoc.v:20499$449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20499$449_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - cell $eq $eq$libresoc.v:20500$450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'1 - connect \Y $eq$libresoc.v:20500$450_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - cell $eq $eq$libresoc.v:20501$451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20501$451_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - cell $eq $eq$libresoc.v:20502$452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \TAP_bus__tms - connect \B 1'0 - connect \Y $eq$libresoc.v:20502$452_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" - cell $eq $eq$libresoc.v:20503$453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'11 - connect \Y $eq$libresoc.v:20503$453_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" - cell $eq $eq$libresoc.v:20504$454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 3'101 - connect \Y $eq$libresoc.v:20504$454_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" - cell $eq $eq$libresoc.v:20505$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 4'1000 - connect \Y $eq$libresoc.v:20505$455_Y - end - attribute \src "libresoc.v:20421.7-20421.20" - process $proc$libresoc.v:20421$480 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20461.13-20461.29" - process $proc$libresoc.v:20461$481 - assign { } { } - assign $1\fsm_state[3:0] 4'0000 - sync always - sync init - update \fsm_state $1\fsm_state[3:0] - end - attribute \src "libresoc.v:20466.7-20466.18" - process $proc$libresoc.v:20466$482 - assign { } { } - assign $1\isdr[0:0] 1'0 - sync always - sync init - update \isdr $1\isdr[0:0] - end - attribute \src "libresoc.v:20471.7-20471.18" - process $proc$libresoc.v:20471$483 - assign { } { } - assign $1\isir[0:0] 1'0 - sync always - sync init - update \isir $1\isir[0:0] - end - attribute \src "libresoc.v:20506.3-20507.35" - process $proc$libresoc.v:20506$456 - assign { } { } - assign $0\fsm_state[3:0] \fsm_state$next - sync posedge \local_clk - update \fsm_state $0\fsm_state[3:0] - end - attribute \src "libresoc.v:20508.3-20509.25" - process $proc$libresoc.v:20508$457 - assign { } { } - assign $0\isdr[0:0] \isdr$next - sync posedge \local_clk - update \isdr $0\isdr[0:0] - end - attribute \src "libresoc.v:20510.3-20511.25" - process $proc$libresoc.v:20510$458 - assign { } { } - assign $0\isir[0:0] \isir$next - sync posedge \local_clk - update \isir $0\isir[0:0] - end - attribute \src "libresoc.v:20512.3-20539.6" - process $proc$libresoc.v:20512$459 - assign { } { } - assign { } { } - assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 - attribute \src "libresoc.v:20513.5-20513.29" - switch \initial - attribute \src "libresoc.v:20513.9-20513.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\isdr$next[0:0]$461 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\isdr$next[0:0]$461 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\isdr$next[0:0]$461 $2\isdr$next[0:0]$462 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\isdr$next[0:0]$462 1'1 - case - assign $2\isdr$next[0:0]$462 \isdr - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\isdr$next[0:0]$461 1'0 - case - assign $1\isdr$next[0:0]$461 \isdr - end - sync always - update \isdr$next $0\isdr$next[0:0]$460 - end - attribute \src "libresoc.v:20540.3-20654.6" - process $proc$libresoc.v:20540$463 - assign { } { } - assign { } { } - assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20541.5-20541.29" - switch \initial - attribute \src "libresoc.v:20541.9-20541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $2\fsm_state$next[3:0]$466 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[3:0]$466 4'0001 - case - assign $2\fsm_state$next[3:0]$466 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $3\fsm_state$next[3:0]$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[3:0]$467 4'0010 - case - assign $3\fsm_state$next[3:0]$467 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $4\fsm_state$next[3:0]$468 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[3:0]$468 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\fsm_state$next[3:0]$468 4'0100 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $5\fsm_state$next[3:0]$469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[3:0]$469 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $5\fsm_state$next[3:0]$469 4'0000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $6\fsm_state$next[3:0]$470 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\fsm_state$next[3:0]$470 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $6\fsm_state$next[3:0]$470 4'0110 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $7\fsm_state$next[3:0]$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\fsm_state$next[3:0]$471 4'0110 - case - assign $7\fsm_state$next[3:0]$471 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $8\fsm_state$next[3:0]$472 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\fsm_state$next[3:0]$472 4'0111 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $8\fsm_state$next[3:0]$472 4'1000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $9\fsm_state$next[3:0]$473 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\fsm_state$next[3:0]$473 4'1001 - case - assign $9\fsm_state$next[3:0]$473 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $10\fsm_state$next[3:0]$474 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\fsm_state$next[3:0]$474 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $10\fsm_state$next[3:0]$474 4'1000 - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\fsm_state$next[3:0]$465 $11\fsm_state$next[3:0]$475 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\fsm_state$next[3:0]$475 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $11\fsm_state$next[3:0]$475 4'0010 - end - case - assign $1\fsm_state$next[3:0]$465 \fsm_state - end - sync always - update \fsm_state$next $0\fsm_state$next[3:0]$464 - end - attribute \src "libresoc.v:20655.3-20682.6" - process $proc$libresoc.v:20655$476 - assign { } { } - assign { } { } - assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20656.5-20656.29" - switch \initial - attribute \src "libresoc.v:20656.9-20656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\isir$next[0:0]$478 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\isir$next[0:0]$478 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\isir$next[0:0]$479 1'1 - case - assign $2\isir$next[0:0]$479 \isir - end - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\isir$next[0:0]$478 1'0 - case - assign $1\isir$next[0:0]$478 \isir - end - sync always - update \isir$next $0\isir$next[0:0]$477 - end - connect \$9 $eq$libresoc.v:20490$440_Y - connect \$11 $eq$libresoc.v:20491$441_Y - connect \$13 $eq$libresoc.v:20492$442_Y - connect \$15 $eq$libresoc.v:20493$443_Y - connect \$17 $eq$libresoc.v:20494$444_Y - connect \$1 $eq$libresoc.v:20495$445_Y - connect \$19 $eq$libresoc.v:20496$446_Y - connect \$21 $eq$libresoc.v:20497$447_Y - connect \$23 $eq$libresoc.v:20498$448_Y - connect \$25 $eq$libresoc.v:20499$449_Y - connect \$27 $eq$libresoc.v:20500$450_Y - connect \$29 $eq$libresoc.v:20501$451_Y - connect \$31 $eq$libresoc.v:20502$452_Y - connect \$3 $eq$libresoc.v:20503$453_Y - connect \$5 $eq$libresoc.v:20504$454_Y - connect \$7 $eq$libresoc.v:20505$455_Y - connect \update \$7 - connect \shift \$5 - connect \capture \$3 - connect \rst \$1 - connect \local_clk \TAP_bus__tck - connect \negjtag_rst \rst - connect \negjtag_clk \TAP_bus__tck - connect \posjtag_rst \rst - connect \posjtag_clk \TAP_bus__tck -end -attribute \src "libresoc.v:20696.1-20768.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" -attribute \generator "nMigen" -module \_idblock - attribute \src "libresoc.v:20741.3-20761.6" - wire width 32 $0\TAP_id_sr$next[31:0]$489 - attribute \src "libresoc.v:20739.3-20740.35" - wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:20697.7-20697.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20741.3-20761.6" - wire width 32 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:20707.14-20707.31" - wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:20741.3-20761.6" - wire width 32 $2\TAP_id_sr$next[31:0]$491 - attribute \src "libresoc.v:20736.17-20736.110" - wire $and$libresoc.v:20736$484_Y - attribute \src "libresoc.v:20737.17-20737.108" - wire $and$libresoc.v:20737$485_Y - attribute \src "libresoc.v:20738.17-20738.109" - wire $and$libresoc.v:20738$486_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 5 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" - wire width 32 \TAP_id_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" - wire width 32 \TAP_id_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" - wire output 6 \TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" - wire \_bypass - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" - wire \_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" - wire \_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" - wire \_tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" - wire \_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire input 2 \capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" - wire input 1 \id_bypass - attribute \src "libresoc.v:20697.7-20697.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire input 9 \select_id - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire input 3 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire input 4 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:20736$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \select_id - connect \B \capture - connect \Y $and$libresoc.v:20736$484_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:20737$485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \select_id - connect \B \shift - connect \Y $and$libresoc.v:20737$485_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $and $and$libresoc.v:20738$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \select_id - connect \B \update - connect \Y $and$libresoc.v:20738$486_Y - end - attribute \src "libresoc.v:20697.7-20697.20" - process $proc$libresoc.v:20697$492 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20707.14-20707.31" - process $proc$libresoc.v:20707$493 - assign { } { } - assign $1\TAP_id_sr[31:0] 0 - sync always - sync init - update \TAP_id_sr $1\TAP_id_sr[31:0] - end - attribute \src "libresoc.v:20739.3-20740.35" - process $proc$libresoc.v:20739$487 - assign { } { } - assign $0\TAP_id_sr[31:0] \TAP_id_sr$next - sync posedge \posjtag_clk - update \TAP_id_sr $0\TAP_id_sr[31:0] - end - attribute \src "libresoc.v:20741.3-20761.6" - process $proc$libresoc.v:20741$488 - assign { } { } - assign { } { } - assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:20742.5-20742.29" - switch \initial - attribute \src "libresoc.v:20742.9-20742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" - switch { \_shift \_capture } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\TAP_id_sr$next[31:0]$490 6399 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\TAP_id_sr$next[31:0]$490 $2\TAP_id_sr$next[31:0]$491 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" - switch \_bypass - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\TAP_id_sr$next[31:0]$491 [31:1] \TAP_id_sr [31:1] - assign $2\TAP_id_sr$next[31:0]$491 [0] \_tdi - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\TAP_id_sr$next[31:0]$491 { \_tdi \TAP_id_sr [31:1] } - end - case - assign $1\TAP_id_sr$next[31:0]$490 \TAP_id_sr - end - sync always - update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 - end - connect \$1 $and$libresoc.v:20736$484_Y - connect \$3 $and$libresoc.v:20737$485_Y - connect \$5 $and$libresoc.v:20738$486_Y - connect \TAP_id_tdo \TAP_id_sr [0] - connect \_bypass \id_bypass - connect \_update \$5 - connect \_shift \$3 - connect \_capture \$1 - connect \_tdi \TAP_bus__tdi -end -attribute \src "libresoc.v:20772.1-20856.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" -attribute \generator "nMigen" -module \_irblock - attribute \src "libresoc.v:20773.7-20773.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20834.3-20854.6" - wire width 4 $0\ir$next[3:0]$506 - attribute \src "libresoc.v:20817.3-20818.21" - wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:20821.3-20833.6" - wire width 4 $0\shift_ir$next[3:0]$503 - attribute \src "libresoc.v:20819.3-20820.33" - wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:20834.3-20854.6" - wire width 4 $1\ir$next[3:0]$507 - attribute \src "libresoc.v:20792.13-20792.22" - wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:20821.3-20833.6" - wire width 4 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:20804.13-20804.28" - wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:20834.3-20854.6" - wire width 4 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:20811.17-20811.103" - wire $and$libresoc.v:20811$494_Y - attribute \src "libresoc.v:20812.18-20812.105" - wire $and$libresoc.v:20812$495_Y - attribute \src "libresoc.v:20813.17-20813.105" - wire $and$libresoc.v:20813$496_Y - attribute \src "libresoc.v:20814.17-20814.103" - wire $and$libresoc.v:20814$497_Y - attribute \src "libresoc.v:20815.17-20815.104" - wire $and$libresoc.v:20815$498_Y - attribute \src "libresoc.v:20816.17-20816.105" - wire $and$libresoc.v:20816$499_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 4 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire input 1 \capture - attribute \src "libresoc.v:20773.7-20773.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 output 9 \ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 \ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire input 5 \isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 8 \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire input 7 \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire input 2 \shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" - wire width 4 \shift_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" - wire width 4 \shift_ir$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire output 6 \tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire input 3 \update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:20811$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \shift - connect \Y $and$libresoc.v:20811$494_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:20812$495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \update - connect \Y $and$libresoc.v:20812$495_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:20813$496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \capture - connect \Y $and$libresoc.v:20813$496_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:20814$497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \shift - connect \Y $and$libresoc.v:20814$497_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:20815$498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \update - connect \Y $and$libresoc.v:20815$498_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:20816$499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \isir - connect \B \capture - connect \Y $and$libresoc.v:20816$499_Y - end - attribute \src "libresoc.v:20773.7-20773.20" - process $proc$libresoc.v:20773$509 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20792.13-20792.22" - process $proc$libresoc.v:20792$510 - assign { } { } - assign $1\ir[3:0] 4'0001 - sync always - sync init - update \ir $1\ir[3:0] - end - attribute \src "libresoc.v:20804.13-20804.28" - process $proc$libresoc.v:20804$511 - assign { } { } - assign $1\shift_ir[3:0] 4'0000 - sync always - sync init - update \shift_ir $1\shift_ir[3:0] - end - attribute \src "libresoc.v:20817.3-20818.21" - process $proc$libresoc.v:20817$500 - assign { } { } - assign $0\ir[3:0] \ir$next - sync posedge \posjtag_clk - update \ir $0\ir[3:0] - end - attribute \src "libresoc.v:20819.3-20820.33" - process $proc$libresoc.v:20819$501 - assign { } { } - assign $0\shift_ir[3:0] \shift_ir$next - sync posedge \posjtag_clk - update \shift_ir $0\shift_ir[3:0] - end - attribute \src "libresoc.v:20821.3-20833.6" - process $proc$libresoc.v:20821$502 - assign { } { } - assign { } { } - assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:20822.5-20822.29" - switch \initial - attribute \src "libresoc.v:20822.9-20822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" - switch { \$5 \$3 \$1 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\shift_ir$next[3:0]$504 \ir - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\shift_ir$next[3:0]$504 { \TAP_bus__tdi \shift_ir [3:1] } - case - assign $1\shift_ir$next[3:0]$504 \shift_ir - end - sync always - update \shift_ir$next $0\shift_ir$next[3:0]$503 - end - attribute \src "libresoc.v:20834.3-20854.6" - process $proc$libresoc.v:20834$505 - assign { } { } - assign { } { } - assign { } { } - assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:20835.5-20835.29" - switch \initial - attribute \src "libresoc.v:20835.9-20835.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" - switch { \$11 \$9 \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\ir$next[3:0]$507 \ir - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\ir$next[3:0]$507 \ir - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\ir$next[3:0]$507 \shift_ir - case - assign $1\ir$next[3:0]$507 \ir - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ir$next[3:0]$508 4'0001 - case - assign $2\ir$next[3:0]$508 $1\ir$next[3:0]$507 - end - sync always - update \ir$next $0\ir$next[3:0]$506 - end - connect \$9 $and$libresoc.v:20811$494_Y - connect \$11 $and$libresoc.v:20812$495_Y - connect \$1 $and$libresoc.v:20813$496_Y - connect \$3 $and$libresoc.v:20814$497_Y - connect \$5 $and$libresoc.v:20815$498_Y - connect \$7 $and$libresoc.v:20816$499_Y - connect \tdo \ir [0] -end -attribute \src "libresoc.v:20860.1-20918.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" -attribute \generator "nMigen" -module \adr_l - attribute \src "libresoc.v:20861.7-20861.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20906.3-20914.6" - wire $0\q_int$next[0:0]$522 - attribute \src "libresoc.v:20904.3-20905.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:20906.3-20914.6" - wire $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:20885.7-20885.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:20896.17-20896.96" - wire $and$libresoc.v:20896$512_Y - attribute \src "libresoc.v:20901.17-20901.96" - wire $and$libresoc.v:20901$517_Y - attribute \src "libresoc.v:20898.18-20898.93" - wire $not$libresoc.v:20898$514_Y - attribute \src "libresoc.v:20900.17-20900.92" - wire $not$libresoc.v:20900$516_Y - attribute \src "libresoc.v:20903.17-20903.92" - wire $not$libresoc.v:20903$519_Y - attribute \src "libresoc.v:20897.18-20897.98" - wire $or$libresoc.v:20897$513_Y - attribute \src "libresoc.v:20899.18-20899.99" - wire $or$libresoc.v:20899$515_Y - attribute \src "libresoc.v:20902.17-20902.97" - wire $or$libresoc.v:20902$518_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:20861.7-20861.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:20896$512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:20896$512_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:20901$517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:20901$517_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:20898$514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \Y $not$libresoc.v:20898$514_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:20900$516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $not$libresoc.v:20900$516_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:20903$519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $not$libresoc.v:20903$519_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:20897$513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_adr - connect \Y $or$libresoc.v:20897$513_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:20899$515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \B \q_int - connect \Y $or$libresoc.v:20899$515_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:20902$518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_adr - connect \Y $or$libresoc.v:20902$518_Y - end - attribute \src "libresoc.v:20861.7-20861.20" - process $proc$libresoc.v:20861$524 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20885.7-20885.19" - process $proc$libresoc.v:20885$525 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:20904.3-20905.27" - process $proc$libresoc.v:20904$520 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:20906.3-20914.6" - process $proc$libresoc.v:20906$521 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:20907.5-20907.29" - switch \initial - attribute \src "libresoc.v:20907.9-20907.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$523 1'0 - case - assign $1\q_int$next[0:0]$523 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$522 - end - connect \$9 $and$libresoc.v:20896$512_Y - connect \$11 $or$libresoc.v:20897$513_Y - connect \$13 $not$libresoc.v:20898$514_Y - connect \$15 $or$libresoc.v:20899$515_Y - connect \$1 $not$libresoc.v:20900$516_Y - connect \$3 $and$libresoc.v:20901$517_Y - connect \$5 $or$libresoc.v:20902$518_Y - connect \$7 $not$libresoc.v:20903$519_Y - connect \qlq_adr \$15 - connect \qn_adr \$13 - connect \q_adr \$11 -end -attribute \src "libresoc.v:20922.1-20980.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" -attribute \generator "nMigen" -module \adrok_l - attribute \src "libresoc.v:20923.7-20923.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:20968.3-20976.6" - wire $0\q_int$next[0:0]$536 - attribute \src "libresoc.v:20966.3-20967.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:20968.3-20976.6" - wire $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:20947.7-20947.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:20958.17-20958.96" - wire $and$libresoc.v:20958$526_Y - attribute \src "libresoc.v:20963.17-20963.96" - wire $and$libresoc.v:20963$531_Y - attribute \src "libresoc.v:20960.18-20960.100" - wire $not$libresoc.v:20960$528_Y - attribute \src "libresoc.v:20962.17-20962.99" - wire $not$libresoc.v:20962$530_Y - attribute \src "libresoc.v:20965.17-20965.99" - wire $not$libresoc.v:20965$533_Y - attribute \src "libresoc.v:20959.18-20959.105" - wire $or$libresoc.v:20959$527_Y - attribute \src "libresoc.v:20961.18-20961.106" - wire $or$libresoc.v:20961$529_Y - attribute \src "libresoc.v:20964.17-20964.104" - wire $or$libresoc.v:20964$532_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:20923.7-20923.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 5 \q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire output 4 \qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:20958$526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:20958$526_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:20963$531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:20963$531_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:20960$528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \Y $not$libresoc.v:20960$528_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:20962$530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $not$libresoc.v:20962$530_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:20965$533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $not$libresoc.v:20965$533_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:20959$527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_addr_acked - connect \Y $or$libresoc.v:20959$527_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:20961$529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \B \q_int - connect \Y $or$libresoc.v:20961$529_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:20964$532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_addr_acked - connect \Y $or$libresoc.v:20964$532_Y - end - attribute \src "libresoc.v:20923.7-20923.20" - process $proc$libresoc.v:20923$538 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:20947.7-20947.19" - process $proc$libresoc.v:20947$539 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:20966.3-20967.27" - process $proc$libresoc.v:20966$534 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:20968.3-20976.6" - process $proc$libresoc.v:20968$535 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:20969.5-20969.29" - switch \initial - attribute \src "libresoc.v:20969.9-20969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$537 1'0 - case - assign $1\q_int$next[0:0]$537 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$536 - end - connect \$9 $and$libresoc.v:20958$526_Y - connect \$11 $or$libresoc.v:20959$527_Y - connect \$13 $not$libresoc.v:20960$528_Y - connect \$15 $or$libresoc.v:20961$529_Y - connect \$1 $not$libresoc.v:20962$530_Y - connect \$3 $and$libresoc.v:20963$531_Y - connect \$5 $or$libresoc.v:20964$532_Y - connect \$7 $not$libresoc.v:20965$533_Y - connect \qlq_addr_acked \$15 - connect \qn_addr_acked \$13 - connect \q_addr_acked \$11 -end -attribute \src "libresoc.v:20984.1-22309.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" -attribute \generator "nMigen" -module \alu0 - attribute \src "libresoc.v:21820.3-21821.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 - attribute \src "libresoc.v:21792.3-21793.67" - wire width 4 $0\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 - attribute \src "libresoc.v:21762.3-21763.65" - wire width 12 $0\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 - attribute \src "libresoc.v:21764.3-21765.79" - wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 - attribute \src "libresoc.v:21766.3-21767.75" - wire $0\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 - attribute \src "libresoc.v:21784.3-21785.73" - wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 - attribute \src "libresoc.v:21794.3-21795.59" - wire width 32 $0\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 - attribute \src "libresoc.v:21760.3-21761.69" - wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 - attribute \src "libresoc.v:21776.3-21777.69" - wire $0\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 - attribute \src "libresoc.v:21780.3-21781.71" - wire $0\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 - attribute \src "libresoc.v:21788.3-21789.67" - wire $0\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 - attribute \src "libresoc.v:21790.3-21791.69" - wire $0\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 - attribute \src "libresoc.v:21772.3-21773.63" - wire $0\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 - attribute \src "libresoc.v:21774.3-21775.63" - wire $0\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 - attribute \src "libresoc.v:21786.3-21787.75" - wire $0\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 - attribute \src "libresoc.v:21770.3-21771.63" - wire $0\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 - attribute \src "libresoc.v:21768.3-21769.63" - wire $0\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 - attribute \src "libresoc.v:21782.3-21783.69" - wire $0\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 - attribute \src "libresoc.v:21778.3-21779.63" - wire $0\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21818.3-21819.40" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:22208.3-22216.6" - wire $0\alu_l_r_alu$next[0:0]$784 - attribute \src "libresoc.v:21728.3-21729.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22199.3-22207.6" - wire $0\alui_l_r_alui$next[0:0]$781 - attribute \src "libresoc.v:21730.3-21731.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22049.3-22070.6" - wire width 64 $0\data_r0__o$next[63:0]$729 - attribute \src "libresoc.v:21756.3-21757.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:22049.3-22070.6" - wire $0\data_r0__o_ok$next[0:0]$730 - attribute \src "libresoc.v:21758.3-21759.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22071.3-22092.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$737 - attribute \src "libresoc.v:21752.3-21753.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22071.3-22092.6" - wire $0\data_r1__cr_a_ok$next[0:0]$738 - attribute \src "libresoc.v:21754.3-21755.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22093.3-22114.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$745 - attribute \src "libresoc.v:21748.3-21749.47" - wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22093.3-22114.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$746 - attribute \src "libresoc.v:21750.3-21751.53" - wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22115.3-22136.6" - wire width 2 $0\data_r3__xer_ov$next[1:0]$753 - attribute \src "libresoc.v:21744.3-21745.47" - wire width 2 $0\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22115.3-22136.6" - wire $0\data_r3__xer_ov_ok$next[0:0]$754 - attribute \src "libresoc.v:21746.3-21747.53" - wire $0\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22137.3-22158.6" - wire $0\data_r4__xer_so$next[0:0]$761 - attribute \src "libresoc.v:21740.3-21741.47" - wire $0\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22137.3-22158.6" - wire $0\data_r4__xer_so_ok$next[0:0]$762 - attribute \src "libresoc.v:21742.3-21743.53" - wire $0\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22217.3-22226.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:22227.3-22236.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:22237.3-22246.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:22247.3-22256.6" - wire width 2 $0\dest4_o[1:0] - attribute \src "libresoc.v:22257.3-22266.6" - wire $0\dest5_o[0:0] - attribute \src "libresoc.v:20985.7-20985.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:21965.3-21973.6" - wire $0\opc_l_r_opc$next[0:0]$671 - attribute \src "libresoc.v:21804.3-21805.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:21956.3-21964.6" - wire $0\opc_l_s_opc$next[0:0]$668 - attribute \src "libresoc.v:21806.3-21807.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22267.3-22275.6" - wire width 5 $0\prev_wr_go$next[4:0]$792 - attribute \src "libresoc.v:21816.3-21817.37" - wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:21910.3-21919.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:22001.3-22009.6" - wire width 5 $0\req_l_r_req$next[4:0]$683 - attribute \src "libresoc.v:21796.3-21797.39" - wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:21992.3-22000.6" - wire width 5 $0\req_l_s_req$next[4:0]$680 - attribute \src "libresoc.v:21798.3-21799.39" - wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:21929.3-21937.6" - wire $0\rok_l_r_rdok$next[0:0]$659 - attribute \src "libresoc.v:21812.3-21813.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:21920.3-21928.6" - wire $0\rok_l_s_rdok$next[0:0]$656 - attribute \src "libresoc.v:21814.3-21815.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:21947.3-21955.6" - wire $0\rst_l_r_rst$next[0:0]$665 - attribute \src "libresoc.v:21808.3-21809.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:21938.3-21946.6" - wire $0\rst_l_s_rst$next[0:0]$662 - attribute \src "libresoc.v:21810.3-21811.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:21983.3-21991.6" - wire width 4 $0\src_l_r_src$next[3:0]$677 - attribute \src "libresoc.v:21800.3-21801.39" - wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:21974.3-21982.6" - wire width 4 $0\src_l_s_src$next[3:0]$674 - attribute \src "libresoc.v:21802.3-21803.39" - wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:22159.3-22168.6" - wire width 64 $0\src_r0$next[63:0]$769 - attribute \src "libresoc.v:21738.3-21739.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:22169.3-22178.6" - wire width 64 $0\src_r1$next[63:0]$772 - attribute \src "libresoc.v:21736.3-21737.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:22179.3-22188.6" - wire $0\src_r2$next[0:0]$775 - attribute \src "libresoc.v:21734.3-21735.29" - wire $0\src_r2[0:0] - attribute \src "libresoc.v:22189.3-22198.6" - wire width 2 $0\src_r3$next[1:0]$778 - attribute \src "libresoc.v:21732.3-21733.29" - wire width 2 $0\src_r3[1:0] - attribute \src "libresoc.v:21123.7-21123.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - attribute \src "libresoc.v:21131.13-21131.45" - wire width 4 $1\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 - attribute \src "libresoc.v:21148.14-21148.48" - wire width 12 $1\alu_alu0_alu_op__fn_unit[11:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 - attribute \src "libresoc.v:21152.14-21152.68" - wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 - attribute \src "libresoc.v:21156.7-21156.43" - wire $1\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 - attribute \src "libresoc.v:21164.13-21164.48" - wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 - attribute \src "libresoc.v:21168.14-21168.43" - wire width 32 $1\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 - attribute \src "libresoc.v:21246.13-21246.47" - wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 - attribute \src "libresoc.v:21250.7-21250.40" - wire $1\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 - attribute \src "libresoc.v:21254.7-21254.41" - wire $1\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 - attribute \src "libresoc.v:21258.7-21258.39" - wire $1\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 - attribute \src "libresoc.v:21262.7-21262.40" - wire $1\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 - attribute \src "libresoc.v:21266.7-21266.37" - wire $1\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 - attribute \src "libresoc.v:21270.7-21270.37" - wire $1\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 - attribute \src "libresoc.v:21274.7-21274.43" - wire $1\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 - attribute \src "libresoc.v:21278.7-21278.37" - wire $1\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 - attribute \src "libresoc.v:21282.7-21282.37" - wire $1\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 - attribute \src "libresoc.v:21286.7-21286.40" - wire $1\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 - attribute \src "libresoc.v:21290.7-21290.37" - wire $1\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21322.7-21322.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:22208.3-22216.6" - wire $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:21330.7-21330.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22199.3-22207.6" - wire $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:21342.7-21342.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22049.3-22070.6" - wire width 64 $1\data_r0__o$next[63:0]$731 - attribute \src "libresoc.v:21376.14-21376.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:22049.3-22070.6" - wire $1\data_r0__o_ok$next[0:0]$732 - attribute \src "libresoc.v:21380.7-21380.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22071.3-22092.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$739 - attribute \src "libresoc.v:21384.13-21384.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22071.3-22092.6" - wire $1\data_r1__cr_a_ok$next[0:0]$740 - attribute \src "libresoc.v:21388.7-21388.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22093.3-22114.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$747 - attribute \src "libresoc.v:21392.13-21392.35" - wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22093.3-22114.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$748 - attribute \src "libresoc.v:21396.7-21396.32" - wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22115.3-22136.6" - wire width 2 $1\data_r3__xer_ov$next[1:0]$755 - attribute \src "libresoc.v:21400.13-21400.35" - wire width 2 $1\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22115.3-22136.6" - wire $1\data_r3__xer_ov_ok$next[0:0]$756 - attribute \src "libresoc.v:21404.7-21404.32" - wire $1\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22137.3-22158.6" - wire $1\data_r4__xer_so$next[0:0]$763 - attribute \src "libresoc.v:21408.7-21408.29" - wire $1\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22137.3-22158.6" - wire $1\data_r4__xer_so_ok$next[0:0]$764 - attribute \src "libresoc.v:21412.7-21412.32" - wire $1\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22217.3-22226.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:22227.3-22236.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:22237.3-22246.6" - wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:22247.3-22256.6" - wire width 2 $1\dest4_o[1:0] - attribute \src "libresoc.v:22257.3-22266.6" - wire $1\dest5_o[0:0] - attribute \src "libresoc.v:21965.3-21973.6" - wire $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:21435.7-21435.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:21956.3-21964.6" - wire $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:21439.7-21439.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22267.3-22275.6" - wire width 5 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:21570.13-21570.31" - wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:21910.3-21919.6" - wire $1\req_done[0:0] - attribute \src "libresoc.v:22001.3-22009.6" - wire width 5 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:21578.13-21578.32" - wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:21992.3-22000.6" - wire width 5 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:21582.13-21582.32" - wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:21929.3-21937.6" - wire $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:21594.7-21594.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:21920.3-21928.6" - wire $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:21598.7-21598.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:21947.3-21955.6" - wire $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:21602.7-21602.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:21938.3-21946.6" - wire $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:21606.7-21606.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:21983.3-21991.6" - wire width 4 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:21622.13-21622.31" - wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:21974.3-21982.6" - wire width 4 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:21626.13-21626.31" - wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:22159.3-22168.6" - wire width 64 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:21634.14-21634.43" - wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:22169.3-22178.6" - wire width 64 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:21638.14-21638.43" - wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:22179.3-22188.6" - wire $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:21642.7-21642.20" - wire $1\src_r2[0:0] - attribute \src "libresoc.v:22189.3-22198.6" - wire width 2 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:21646.13-21646.26" - wire width 2 $1\src_r3[1:0] - attribute \src "libresoc.v:22010.3-22048.6" - wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 - attribute \src "libresoc.v:22010.3-22048.6" - wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 - attribute \src "libresoc.v:22010.3-22048.6" - wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 - attribute \src "libresoc.v:22010.3-22048.6" - wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 - attribute \src "libresoc.v:22010.3-22048.6" - wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 - attribute \src "libresoc.v:22010.3-22048.6" - wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22049.3-22070.6" - wire width 64 $2\data_r0__o$next[63:0]$733 - attribute \src "libresoc.v:22049.3-22070.6" - wire $2\data_r0__o_ok$next[0:0]$734 - attribute \src "libresoc.v:22071.3-22092.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$741 - attribute \src "libresoc.v:22071.3-22092.6" - wire $2\data_r1__cr_a_ok$next[0:0]$742 - attribute \src "libresoc.v:22093.3-22114.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$749 - attribute \src "libresoc.v:22093.3-22114.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$750 - attribute \src "libresoc.v:22115.3-22136.6" - wire width 2 $2\data_r3__xer_ov$next[1:0]$757 - attribute \src "libresoc.v:22115.3-22136.6" - wire $2\data_r3__xer_ov_ok$next[0:0]$758 - attribute \src "libresoc.v:22137.3-22158.6" - wire $2\data_r4__xer_so$next[0:0]$765 - attribute \src "libresoc.v:22137.3-22158.6" - wire $2\data_r4__xer_so_ok$next[0:0]$766 - attribute \src "libresoc.v:22049.3-22070.6" - wire $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22071.3-22092.6" - wire $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22093.3-22114.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22115.3-22136.6" - wire $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22137.3-22158.6" - wire $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:21662.18-21662.134" - wire $and$libresoc.v:21662$541_Y - attribute \src "libresoc.v:21663.19-21663.133" - wire $and$libresoc.v:21663$542_Y - attribute \src "libresoc.v:21664.19-21664.161" - wire width 4 $and$libresoc.v:21664$543_Y - attribute \src "libresoc.v:21667.19-21667.134" - wire width 4 $and$libresoc.v:21667$546_Y - attribute \src "libresoc.v:21669.19-21669.115" - wire width 4 $and$libresoc.v:21669$548_Y - attribute \src "libresoc.v:21670.19-21670.125" - wire $and$libresoc.v:21670$549_Y - attribute \src "libresoc.v:21671.19-21671.125" - wire $and$libresoc.v:21671$550_Y - attribute \src "libresoc.v:21672.18-21672.110" - wire $and$libresoc.v:21672$551_Y - attribute \src "libresoc.v:21673.19-21673.125" - wire $and$libresoc.v:21673$552_Y - attribute \src "libresoc.v:21674.19-21674.125" - wire $and$libresoc.v:21674$553_Y - attribute \src "libresoc.v:21675.19-21675.125" - wire $and$libresoc.v:21675$554_Y - attribute \src "libresoc.v:21676.19-21676.157" - wire width 5 $and$libresoc.v:21676$555_Y - attribute \src "libresoc.v:21677.19-21677.121" - wire width 5 $and$libresoc.v:21677$556_Y - attribute \src "libresoc.v:21678.19-21678.127" - wire $and$libresoc.v:21678$557_Y - attribute \src "libresoc.v:21679.19-21679.127" - wire $and$libresoc.v:21679$558_Y - attribute \src "libresoc.v:21680.19-21680.127" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_alu0_alu_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_alu0_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_alu0_alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \alu_alu0_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_alu0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_alu0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_alu0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_alu0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_alu0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_alu0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_alu0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \alu_alu0_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_alu0_xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \alu_alu0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \alu_alu0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_alu0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 5 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 21 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 20 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 24 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 23 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 22 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 31 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 30 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 5 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r3__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r3__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r4__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r4__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r4__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r4__xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 32 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 34 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 36 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 38 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 40 \dest5_o - attribute \src "libresoc.v:20985.7-20985.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 18 \oper_i_alu_alu0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_alu0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_alu0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_alu0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 14 \oper_i_alu_alu0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \oper_i_alu_alu0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_alu0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_alu0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_alu_alu0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_alu0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \oper_i_alu_alu0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_alu0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_alu0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_alu0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_alu0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_alu0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_alu0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_alu0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire 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parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:21707$586_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:21708$587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21708$587_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:21709$588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:21709$588_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:21713$592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:21713$592_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:21722$601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:21722$601_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:21661$540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$libresoc.v:21661$540_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:21690$569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$libresoc.v:21690$569_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21693$572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:21693$572_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21694$573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:21694$573_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21719$598 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21719$598_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21720$599 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:21720$599_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:21721$600 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21721$600_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:21723$602 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_alu0_alu_op__imm_data__data - connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:21723$602_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21724$603 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:21724$603_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21725$604 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$88 - connect \S \src_sel$85 - connect \Y $ternary$libresoc.v:21725$604_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21726$605 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:21726$605_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:21727$606 - parameter \WIDTH 2 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:21727$606_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21822.12-21861.4" - cell \alu_alu0 \alu_alu0 - connect \alu_op__data_len \alu_alu0_alu_op__data_len - connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit - connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data - connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok - connect \alu_op__input_carry \alu_alu0_alu_op__input_carry - connect \alu_op__insn \alu_alu0_alu_op__insn - connect \alu_op__insn_type \alu_alu0_alu_op__insn_type - connect \alu_op__invert_in \alu_alu0_alu_op__invert_in - connect \alu_op__invert_out \alu_alu0_alu_op__invert_out - connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit - connect \alu_op__is_signed \alu_alu0_alu_op__is_signed - connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe - connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok - connect \alu_op__output_carry \alu_alu0_alu_op__output_carry - connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok - connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc - connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 - connect \alu_op__zero_a \alu_alu0_alu_op__zero_a - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_alu0_cr_a - connect \cr_a_ok \cr_a_ok - connect \n_ready_i \alu_alu0_n_ready_i - connect \n_valid_o \alu_alu0_n_valid_o - connect \o \alu_alu0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_alu0_p_ready_o - connect \p_valid_i \alu_alu0_p_valid_i - connect \ra \alu_alu0_ra - connect \rb \alu_alu0_rb - connect \xer_ca \alu_alu0_xer_ca - connect \xer_ca$2 \alu_alu0_xer_ca$2 - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov \alu_alu0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_alu0_xer_so - connect \xer_so$1 \alu_alu0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21862.9-21868.4" - cell \alu_l \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21869.10-21875.4" - cell \alui_l \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21876.9-21882.4" - cell \opc_l \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21883.9-21889.4" - cell \req_l \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21890.9-21896.4" - cell \rok_l \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21897.9-21902.4" - cell \rst_l \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:21903.9-21909.4" - cell \src_l \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:20985.7-20985.20" - process $proc$libresoc.v:20985$794 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:21123.7-21123.24" - process $proc$libresoc.v:21123$795 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:21131.13-21131.45" - process $proc$libresoc.v:21131$796 - assign { } { } - assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] - end - attribute \src "libresoc.v:21148.14-21148.48" - process $proc$libresoc.v:21148$797 - assign { } { } - assign $1\alu_alu0_alu_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:21152.14-21152.68" - process $proc$libresoc.v:21152$798 - assign { } { } - assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:21156.7-21156.43" - process $proc$libresoc.v:21156$799 - assign { } { } - assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:21164.13-21164.48" - process $proc$libresoc.v:21164$800 - assign { } { } - assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] - end - attribute \src "libresoc.v:21168.14-21168.43" - process $proc$libresoc.v:21168$801 - assign { } { } - assign $1\alu_alu0_alu_op__insn[31:0] 0 - sync always - sync init - update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] - end - attribute \src "libresoc.v:21246.13-21246.47" - process $proc$libresoc.v:21246$802 - assign { } { } - assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:21250.7-21250.40" - process $proc$libresoc.v:21250$803 - assign { } { } - assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] - end - attribute \src "libresoc.v:21254.7-21254.41" - process $proc$libresoc.v:21254$804 - assign { } { } - assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] - end - attribute \src "libresoc.v:21258.7-21258.39" - process $proc$libresoc.v:21258$805 - assign { } { } - assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] - end - attribute \src "libresoc.v:21262.7-21262.40" - process $proc$libresoc.v:21262$806 - assign { } { } - assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] - end - attribute \src "libresoc.v:21266.7-21266.37" - process $proc$libresoc.v:21266$807 - assign { } { } - assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] - end - attribute \src "libresoc.v:21270.7-21270.37" - process $proc$libresoc.v:21270$808 - assign { } { } - assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] - end - attribute \src "libresoc.v:21274.7-21274.43" - process $proc$libresoc.v:21274$809 - assign { } { } - assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] - end - attribute \src "libresoc.v:21278.7-21278.37" - process $proc$libresoc.v:21278$810 - assign { } { } - assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] - end - attribute \src "libresoc.v:21282.7-21282.37" - process $proc$libresoc.v:21282$811 - assign { } { } - assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] - end - attribute \src "libresoc.v:21286.7-21286.40" - process $proc$libresoc.v:21286$812 - assign { } { } - assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] - end - attribute \src "libresoc.v:21290.7-21290.37" - process $proc$libresoc.v:21290$813 - assign { } { } - assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] - end - attribute \src "libresoc.v:21322.7-21322.26" - process $proc$libresoc.v:21322$814 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:21330.7-21330.25" - process $proc$libresoc.v:21330$815 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:21342.7-21342.27" - process $proc$libresoc.v:21342$816 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:21376.14-21376.47" - process $proc$libresoc.v:21376$817 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:21380.7-21380.27" - process $proc$libresoc.v:21380$818 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:21384.13-21384.33" - process $proc$libresoc.v:21384$819 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:21388.7-21388.30" - process $proc$libresoc.v:21388$820 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:21392.13-21392.35" - process $proc$libresoc.v:21392$821 - assign { } { } - assign $1\data_r2__xer_ca[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] - end - attribute \src "libresoc.v:21396.7-21396.32" - process $proc$libresoc.v:21396$822 - assign { } { } - assign $1\data_r2__xer_ca_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] - end - attribute \src "libresoc.v:21400.13-21400.35" - process $proc$libresoc.v:21400$823 - assign { } { } - assign $1\data_r3__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] - end - attribute \src "libresoc.v:21404.7-21404.32" - process $proc$libresoc.v:21404$824 - assign { } { } - assign $1\data_r3__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:21408.7-21408.29" - process $proc$libresoc.v:21408$825 - assign { } { } - assign $1\data_r4__xer_so[0:0] 1'0 - sync always - sync init - update \data_r4__xer_so $1\data_r4__xer_so[0:0] - end - attribute \src "libresoc.v:21412.7-21412.32" - process $proc$libresoc.v:21412$826 - assign { } { } - assign $1\data_r4__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] - end - attribute \src "libresoc.v:21435.7-21435.25" - process $proc$libresoc.v:21435$827 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:21439.7-21439.25" - process $proc$libresoc.v:21439$828 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:21570.13-21570.31" - process $proc$libresoc.v:21570$829 - assign { } { } - assign $1\prev_wr_go[4:0] 5'00000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[4:0] - end - attribute \src "libresoc.v:21578.13-21578.32" - process $proc$libresoc.v:21578$830 - assign { } { } - assign $1\req_l_r_req[4:0] 5'11111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[4:0] - end - attribute \src "libresoc.v:21582.13-21582.32" - process $proc$libresoc.v:21582$831 - assign { } { } - assign $1\req_l_s_req[4:0] 5'00000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[4:0] - end - attribute \src "libresoc.v:21594.7-21594.26" - process $proc$libresoc.v:21594$832 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:21598.7-21598.26" - process $proc$libresoc.v:21598$833 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:21602.7-21602.25" - process $proc$libresoc.v:21602$834 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:21606.7-21606.25" - process $proc$libresoc.v:21606$835 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:21622.13-21622.31" - process $proc$libresoc.v:21622$836 - assign { } { } - assign $1\src_l_r_src[3:0] 4'1111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[3:0] - end - attribute \src "libresoc.v:21626.13-21626.31" - process $proc$libresoc.v:21626$837 - assign { } { } - assign $1\src_l_s_src[3:0] 4'0000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[3:0] - end - attribute \src "libresoc.v:21634.14-21634.43" - process $proc$libresoc.v:21634$838 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:21638.14-21638.43" - process $proc$libresoc.v:21638$839 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:21642.7-21642.20" - process $proc$libresoc.v:21642$840 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "libresoc.v:21646.13-21646.26" - process $proc$libresoc.v:21646$841 - assign { } { } - assign $1\src_r3[1:0] 2'00 - sync always - sync init - update \src_r3 $1\src_r3[1:0] - end - attribute \src "libresoc.v:21728.3-21729.39" - process $proc$libresoc.v:21728$607 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:21730.3-21731.43" - process $proc$libresoc.v:21730$608 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:21732.3-21733.29" - process $proc$libresoc.v:21732$609 - assign { } { } - assign $0\src_r3[1:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[1:0] - end - attribute \src "libresoc.v:21734.3-21735.29" - process $proc$libresoc.v:21734$610 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "libresoc.v:21736.3-21737.29" - process $proc$libresoc.v:21736$611 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:21738.3-21739.29" - process $proc$libresoc.v:21738$612 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:21740.3-21741.47" - process $proc$libresoc.v:21740$613 - assign { } { } - assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next - sync posedge \coresync_clk - update \data_r4__xer_so $0\data_r4__xer_so[0:0] - end - attribute \src "libresoc.v:21742.3-21743.53" - process $proc$libresoc.v:21742$614 - assign { } { } - assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next - sync posedge \coresync_clk - update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] - end - attribute \src "libresoc.v:21744.3-21745.47" - process $proc$libresoc.v:21744$615 - assign { } { } - assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next - sync posedge \coresync_clk - update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] - end - attribute \src "libresoc.v:21746.3-21747.53" - process $proc$libresoc.v:21746$616 - assign { } { } - assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:21748.3-21749.47" - process $proc$libresoc.v:21748$617 - assign { } { } - assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next - sync posedge \coresync_clk - update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] - end - attribute \src "libresoc.v:21750.3-21751.53" - process $proc$libresoc.v:21750$618 - assign { } { } - assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] - end - attribute \src "libresoc.v:21752.3-21753.43" - process $proc$libresoc.v:21752$619 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:21754.3-21755.49" - process $proc$libresoc.v:21754$620 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:21756.3-21757.37" - process $proc$libresoc.v:21756$621 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:21758.3-21759.43" - process $proc$libresoc.v:21758$622 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:21760.3-21761.69" - process $proc$libresoc.v:21760$623 - assign { } { } - assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:21762.3-21763.65" - process $proc$libresoc.v:21762$624 - assign { } { } - assign $0\alu_alu0_alu_op__fn_unit[11:0] \alu_alu0_alu_op__fn_unit$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:21764.3-21765.79" - process $proc$libresoc.v:21764$625 - assign { } { } - assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:21766.3-21767.75" - process $proc$libresoc.v:21766$626 - assign { } { } - assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:21768.3-21769.63" - process $proc$libresoc.v:21768$627 - assign { } { } - assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] - end - attribute \src "libresoc.v:21770.3-21771.63" - process $proc$libresoc.v:21770$628 - assign { } { } - assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] - end - attribute \src "libresoc.v:21772.3-21773.63" - process $proc$libresoc.v:21772$629 - assign { } { } - assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] - end - attribute \src "libresoc.v:21774.3-21775.63" - process $proc$libresoc.v:21774$630 - assign { } { } - assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] - end - attribute \src "libresoc.v:21776.3-21777.69" - process $proc$libresoc.v:21776$631 - assign { } { } - assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] - end - attribute \src "libresoc.v:21778.3-21779.63" - process $proc$libresoc.v:21778$632 - assign { } { } - assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] - end - attribute \src "libresoc.v:21780.3-21781.71" - process $proc$libresoc.v:21780$633 - assign { } { } - assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] - end - attribute \src "libresoc.v:21782.3-21783.69" - process $proc$libresoc.v:21782$634 - assign { } { } - assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] - end - attribute \src "libresoc.v:21784.3-21785.73" - process $proc$libresoc.v:21784$635 - assign { } { } - assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] - end - attribute \src "libresoc.v:21786.3-21787.75" - process $proc$libresoc.v:21786$636 - assign { } { } - assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] - end - attribute \src "libresoc.v:21788.3-21789.67" - process $proc$libresoc.v:21788$637 - assign { } { } - assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] - end - attribute \src "libresoc.v:21790.3-21791.69" - process $proc$libresoc.v:21790$638 - assign { } { } - assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] - end - attribute \src "libresoc.v:21792.3-21793.67" - process $proc$libresoc.v:21792$639 - assign { } { } - assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] - end - attribute \src "libresoc.v:21794.3-21795.59" - process $proc$libresoc.v:21794$640 - assign { } { } - assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next - sync posedge \coresync_clk - update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] - end - attribute \src "libresoc.v:21796.3-21797.39" - process $proc$libresoc.v:21796$641 - assign { } { } - assign $0\req_l_r_req[4:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[4:0] - end - attribute \src "libresoc.v:21798.3-21799.39" - process $proc$libresoc.v:21798$642 - assign { } { } - assign $0\req_l_s_req[4:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[4:0] - end - attribute \src "libresoc.v:21800.3-21801.39" - process $proc$libresoc.v:21800$643 - assign { } { } - assign $0\src_l_r_src[3:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[3:0] - end - attribute \src "libresoc.v:21802.3-21803.39" - process $proc$libresoc.v:21802$644 - assign { } { } - assign $0\src_l_s_src[3:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[3:0] - end - attribute \src "libresoc.v:21804.3-21805.39" - process $proc$libresoc.v:21804$645 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:21806.3-21807.39" - process $proc$libresoc.v:21806$646 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:21808.3-21809.39" - process $proc$libresoc.v:21808$647 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:21810.3-21811.39" - process $proc$libresoc.v:21810$648 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:21812.3-21813.41" - process $proc$libresoc.v:21812$649 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:21814.3-21815.41" - process $proc$libresoc.v:21814$650 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:21816.3-21817.37" - process $proc$libresoc.v:21816$651 - assign { } { } - assign $0\prev_wr_go[4:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[4:0] - end - attribute \src "libresoc.v:21818.3-21819.40" - process $proc$libresoc.v:21818$652 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:21820.3-21821.25" - process $proc$libresoc.v:21820$653 - assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:21910.3-21919.6" - process $proc$libresoc.v:21910$654 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:21911.5-21911.29" - switch \initial - attribute \src "libresoc.v:21911.9-21911.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:21920.3-21928.6" - process $proc$libresoc.v:21920$655 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:21921.5-21921.29" - switch \initial - attribute \src "libresoc.v:21921.9-21921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$657 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$657 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 - end - attribute \src "libresoc.v:21929.3-21937.6" - process $proc$libresoc.v:21929$658 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:21930.5-21930.29" - switch \initial - attribute \src "libresoc.v:21930.9-21930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$660 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$660 \$65 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 - end - attribute \src "libresoc.v:21938.3-21946.6" - process $proc$libresoc.v:21938$661 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:21939.5-21939.29" - switch \initial - attribute \src "libresoc.v:21939.9-21939.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$663 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$663 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 - end - attribute \src "libresoc.v:21947.3-21955.6" - process $proc$libresoc.v:21947$664 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:21948.5-21948.29" - switch \initial - attribute \src "libresoc.v:21948.9-21948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$666 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$666 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 - end - attribute \src "libresoc.v:21956.3-21964.6" - process $proc$libresoc.v:21956$667 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:21957.5-21957.29" - switch \initial - attribute \src "libresoc.v:21957.9-21957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$669 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$669 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 - end - attribute \src "libresoc.v:21965.3-21973.6" - process $proc$libresoc.v:21965$670 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:21966.5-21966.29" - switch \initial - attribute \src "libresoc.v:21966.9-21966.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$672 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$672 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 - end - attribute \src "libresoc.v:21974.3-21982.6" - process $proc$libresoc.v:21974$673 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:21975.5-21975.29" - switch \initial - attribute \src "libresoc.v:21975.9-21975.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[3:0]$675 4'0000 - case - assign $1\src_l_s_src$next[3:0]$675 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 - end - attribute \src "libresoc.v:21983.3-21991.6" - process $proc$libresoc.v:21983$676 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:21984.5-21984.29" - switch \initial - attribute \src "libresoc.v:21984.9-21984.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[3:0]$678 4'1111 - case - assign $1\src_l_r_src$next[3:0]$678 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 - end - attribute \src "libresoc.v:21992.3-22000.6" - process $proc$libresoc.v:21992$679 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:21993.5-21993.29" - switch \initial - attribute \src "libresoc.v:21993.9-21993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[4:0]$681 5'00000 - case - assign $1\req_l_s_req$next[4:0]$681 \$67 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 - end - attribute \src "libresoc.v:22001.3-22009.6" - process $proc$libresoc.v:22001$682 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:22002.5-22002.29" - switch \initial - attribute \src "libresoc.v:22002.9-22002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[4:0]$684 5'11111 - case - assign $1\req_l_r_req$next[4:0]$684 \$69 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 - end - attribute \src "libresoc.v:22010.3-22048.6" - process $proc$libresoc.v:22010$685 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 - assign $0\alu_alu0_alu_op__insn$next[31:0]$691 $1\alu_alu0_alu_op__insn$next[31:0]$709 - assign $0\alu_alu0_alu_op__insn_type$next[6:0]$692 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 - assign $0\alu_alu0_alu_op__invert_in$next[0:0]$693 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 - assign $0\alu_alu0_alu_op__invert_out$next[0:0]$694 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 - assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 - assign $0\alu_alu0_alu_op__is_signed$next[0:0]$696 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__output_carry$next[0:0]$699 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 - assign { } { } - assign { } { } - assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 - assign $0\alu_alu0_alu_op__zero_a$next[0:0]$703 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 - assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 - assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 - assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 - assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 - assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 - assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22011.5-22011.29" - switch \initial - attribute \src "libresoc.v:22011.9-22011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } - case - assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len - assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$705 \alu_alu0_alu_op__fn_unit - assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data - assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok - assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry - assign $1\alu_alu0_alu_op__insn$next[31:0]$709 \alu_alu0_alu_op__insn - assign $1\alu_alu0_alu_op__insn_type$next[6:0]$710 \alu_alu0_alu_op__insn_type - assign $1\alu_alu0_alu_op__invert_in$next[0:0]$711 \alu_alu0_alu_op__invert_in - assign $1\alu_alu0_alu_op__invert_out$next[0:0]$712 \alu_alu0_alu_op__invert_out - assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 \alu_alu0_alu_op__is_32bit - assign $1\alu_alu0_alu_op__is_signed$next[0:0]$714 \alu_alu0_alu_op__is_signed - assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 \alu_alu0_alu_op__oe__oe - assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 \alu_alu0_alu_op__oe__ok - assign $1\alu_alu0_alu_op__output_carry$next[0:0]$717 \alu_alu0_alu_op__output_carry - assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 \alu_alu0_alu_op__rc__ok - assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 \alu_alu0_alu_op__rc__rc - assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 \alu_alu0_alu_op__write_cr0 - assign $1\alu_alu0_alu_op__zero_a$next[0:0]$721 \alu_alu0_alu_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 1'0 - assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 1'0 - assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 1'0 - assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 1'0 - assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 1'0 - case - assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 - assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 - assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 - assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 - assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 - assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 - end - sync always - update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 - update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$687 - update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 - update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 - update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 - update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$691 - update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$692 - update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$693 - update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$694 - update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 - update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$696 - update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 - update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 - update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$699 - update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 - update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 - update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 - update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 - end - attribute \src "libresoc.v:22049.3-22070.6" - process $proc$libresoc.v:22049$728 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22050.5-22050.29" - switch \initial - attribute \src "libresoc.v:22050.9-22050.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$732 $1\data_r0__o$next[63:0]$731 } { \o_ok \alu_alu0_o } - case - assign $1\data_r0__o$next[63:0]$731 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$732 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$734 $2\data_r0__o$next[63:0]$733 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$733 $1\data_r0__o$next[63:0]$731 - assign $2\data_r0__o_ok$next[0:0]$734 $1\data_r0__o_ok$next[0:0]$732 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$735 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$735 $2\data_r0__o_ok$next[0:0]$734 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$729 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 - end - attribute \src "libresoc.v:22071.3-22092.6" - process $proc$libresoc.v:22071$736 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22072.5-22072.29" - switch \initial - attribute \src "libresoc.v:22072.9-22072.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$740 $1\data_r1__cr_a$next[3:0]$739 } { \cr_a_ok \alu_alu0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$739 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$740 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$742 $2\data_r1__cr_a$next[3:0]$741 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$741 $1\data_r1__cr_a$next[3:0]$739 - assign $2\data_r1__cr_a_ok$next[0:0]$742 $1\data_r1__cr_a_ok$next[0:0]$740 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$743 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$743 $2\data_r1__cr_a_ok$next[0:0]$742 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 - end - attribute \src "libresoc.v:22093.3-22114.6" - process $proc$libresoc.v:22093$744 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 - assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22094.5-22094.29" - switch \initial - attribute \src "libresoc.v:22094.9-22094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$748 $1\data_r2__xer_ca$next[1:0]$747 } { \xer_ca_ok \alu_alu0_xer_ca } - case - assign $1\data_r2__xer_ca$next[1:0]$747 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$748 \data_r2__xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$750 $2\data_r2__xer_ca$next[1:0]$749 } 3'000 - case - assign $2\data_r2__xer_ca$next[1:0]$749 $1\data_r2__xer_ca$next[1:0]$747 - assign $2\data_r2__xer_ca_ok$next[0:0]$750 $1\data_r2__xer_ca_ok$next[0:0]$748 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$751 1'0 - case - assign $3\data_r2__xer_ca_ok$next[0:0]$751 $2\data_r2__xer_ca_ok$next[0:0]$750 - end - sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 - end - attribute \src "libresoc.v:22115.3-22136.6" - process $proc$libresoc.v:22115$752 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 - assign { } { } - assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22116.5-22116.29" - switch \initial - attribute \src "libresoc.v:22116.9-22116.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_ov_ok$next[0:0]$756 $1\data_r3__xer_ov$next[1:0]$755 } { \xer_ov_ok \alu_alu0_xer_ov } - case - assign $1\data_r3__xer_ov$next[1:0]$755 \data_r3__xer_ov - assign $1\data_r3__xer_ov_ok$next[0:0]$756 \data_r3__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__xer_ov_ok$next[0:0]$758 $2\data_r3__xer_ov$next[1:0]$757 } 3'000 - case - assign $2\data_r3__xer_ov$next[1:0]$757 $1\data_r3__xer_ov$next[1:0]$755 - assign $2\data_r3__xer_ov_ok$next[0:0]$758 $1\data_r3__xer_ov_ok$next[0:0]$756 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r3__xer_ov_ok$next[0:0]$759 1'0 - case - assign $3\data_r3__xer_ov_ok$next[0:0]$759 $2\data_r3__xer_ov_ok$next[0:0]$758 - end - sync always - update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 - update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 - end - attribute \src "libresoc.v:22137.3-22158.6" - process $proc$libresoc.v:22137$760 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 - assign { } { } - assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:22138.5-22138.29" - switch \initial - attribute \src "libresoc.v:22138.9-22138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r4__xer_so_ok$next[0:0]$764 $1\data_r4__xer_so$next[0:0]$763 } { \xer_so_ok \alu_alu0_xer_so } - case - assign $1\data_r4__xer_so$next[0:0]$763 \data_r4__xer_so - assign $1\data_r4__xer_so_ok$next[0:0]$764 \data_r4__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r4__xer_so_ok$next[0:0]$766 $2\data_r4__xer_so$next[0:0]$765 } 2'00 - case - assign $2\data_r4__xer_so$next[0:0]$765 $1\data_r4__xer_so$next[0:0]$763 - assign $2\data_r4__xer_so_ok$next[0:0]$766 $1\data_r4__xer_so_ok$next[0:0]$764 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r4__xer_so_ok$next[0:0]$767 1'0 - case - assign $3\data_r4__xer_so_ok$next[0:0]$767 $2\data_r4__xer_so_ok$next[0:0]$766 - end - sync always - update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 - update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 - end - attribute \src "libresoc.v:22159.3-22168.6" - process $proc$libresoc.v:22159$768 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:22160.5-22160.29" - switch \initial - attribute \src "libresoc.v:22160.9-22160.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$770 \src_or_imm - case - assign $1\src_r0$next[63:0]$770 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$769 - end - attribute \src "libresoc.v:22169.3-22178.6" - process $proc$libresoc.v:22169$771 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:22170.5-22170.29" - switch \initial - attribute \src "libresoc.v:22170.9-22170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$773 \src_or_imm$88 - case - assign $1\src_r1$next[63:0]$773 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$772 - end - attribute \src "libresoc.v:22179.3-22188.6" - process $proc$libresoc.v:22179$774 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:22180.5-22180.29" - switch \initial - attribute \src "libresoc.v:22180.9-22180.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$776 \src3_i - case - assign $1\src_r2$next[0:0]$776 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$775 - end - attribute \src "libresoc.v:22189.3-22198.6" - process $proc$libresoc.v:22189$777 - assign { } { } - assign { } { } - assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:22190.5-22190.29" - switch \initial - attribute \src "libresoc.v:22190.9-22190.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r3$next[1:0]$779 \src4_i - case - assign $1\src_r3$next[1:0]$779 \src_r3 - end - sync always - update \src_r3$next $0\src_r3$next[1:0]$778 - end - attribute \src "libresoc.v:22199.3-22207.6" - process $proc$libresoc.v:22199$780 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:22200.5-22200.29" - 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\enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 23 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 24 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 22 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 28 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 8 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 27 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 37 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 36 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe1_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe1_alu_op__data_len$20 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_alu_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__imm_data__ok$7 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_alu_op__input_carry$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_alu_op__insn$21 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute 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attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_alu_op__insn_type$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_in$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__invert_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_32bit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__is_signed$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__oe$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__oe__ok$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__output_carry$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__rc__rc$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__write_cr0$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_alu_op__zero_a$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe1_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe1_xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe1_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe1_xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe2_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe2_alu_op__data_len$41 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe2_alu_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__imm_data__ok$28 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_alu_op__input_carry$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_alu_op__insn$42 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_alu_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__invert_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__write_cr0$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_alu_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \pipe2_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe2_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe2_xer_ca$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_ca_ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe2_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe2_xer_ov$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_ov_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_so$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_so_ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 32 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 33 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 29 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 35 \xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 30 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 34 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 6 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "libresoc.v:23212.5-23215.4" - cell \n \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:23216.5-23219.4" - cell \p \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:23220.9-23279.4" - cell \pipe1 \pipe1 - connect \alu_op__data_len \pipe1_alu_op__data_len - connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 - connect \alu_op__fn_unit \pipe1_alu_op__fn_unit - connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 - connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 - connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 - connect \alu_op__input_carry \pipe1_alu_op__input_carry - connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 - connect \alu_op__insn \pipe1_alu_op__insn - connect \alu_op__insn$19 \pipe1_alu_op__insn$21 - connect \alu_op__insn_type \pipe1_alu_op__insn_type - connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 - connect \alu_op__invert_in \pipe1_alu_op__invert_in - connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 - connect \alu_op__invert_out \pipe1_alu_op__invert_out - connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 - connect \alu_op__is_32bit \pipe1_alu_op__is_32bit - connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 - connect \alu_op__is_signed \pipe1_alu_op__is_signed - connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 - connect \alu_op__oe__oe \pipe1_alu_op__oe__oe - connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 - connect \alu_op__oe__ok \pipe1_alu_op__oe__ok - connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 - connect \alu_op__output_carry \pipe1_alu_op__output_carry - connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 - connect \alu_op__rc__ok \pipe1_alu_op__rc__ok - connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 - connect \alu_op__rc__rc \pipe1_alu_op__rc__rc - connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 - connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 - connect \alu_op__zero_a \pipe1_alu_op__zero_a - connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe1_cr_a - connect \cr_a_ok \pipe1_cr_a_ok - connect \muxid \pipe1_muxid - connect \muxid$1 \pipe1_muxid$3 - connect \n_ready_i \pipe1_n_ready_i - connect \n_valid_o \pipe1_n_valid_o - connect \o \pipe1_o - connect \o_ok \pipe1_o_ok - connect \p_ready_o \pipe1_p_ready_o - connect \p_valid_i \pipe1_p_valid_i - connect \ra \pipe1_ra - connect \rb \pipe1_rb - connect \xer_ca \pipe1_xer_ca - connect \xer_ca$21 \pipe1_xer_ca$23 - connect \xer_ca_ok \pipe1_xer_ca_ok - connect \xer_ov \pipe1_xer_ov - connect \xer_ov_ok \pipe1_xer_ov_ok - connect \xer_so \pipe1_xer_so - connect \xer_so$20 \pipe1_xer_so$22 - connect \xer_so_ok \pipe1_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:23280.9-23345.4" - cell \pipe2 \pipe2 - connect \alu_op__data_len \pipe2_alu_op__data_len - connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 - connect \alu_op__fn_unit \pipe2_alu_op__fn_unit - connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 - connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 - connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 - connect \alu_op__input_carry \pipe2_alu_op__input_carry - connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 - connect \alu_op__insn \pipe2_alu_op__insn - connect \alu_op__insn$19 \pipe2_alu_op__insn$42 - connect \alu_op__insn_type \pipe2_alu_op__insn_type - connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 - connect \alu_op__invert_in \pipe2_alu_op__invert_in - connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 - connect \alu_op__invert_out \pipe2_alu_op__invert_out - connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 - connect \alu_op__is_32bit \pipe2_alu_op__is_32bit - connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 - connect \alu_op__is_signed \pipe2_alu_op__is_signed - connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 - connect \alu_op__oe__oe \pipe2_alu_op__oe__oe - connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 - connect \alu_op__oe__ok \pipe2_alu_op__oe__ok - connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 - connect \alu_op__output_carry \pipe2_alu_op__output_carry - connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 - connect \alu_op__rc__ok \pipe2_alu_op__rc__ok - connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 - connect \alu_op__rc__rc \pipe2_alu_op__rc__rc - connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 - connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 - connect \alu_op__zero_a \pipe2_alu_op__zero_a - connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe2_cr_a - connect \cr_a$22 \pipe2_cr_a$45 - connect \cr_a_ok \pipe2_cr_a_ok - connect \cr_a_ok$23 \pipe2_cr_a_ok$46 - connect \muxid \pipe2_muxid - connect \muxid$1 \pipe2_muxid$24 - connect \n_ready_i \pipe2_n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \o \pipe2_o - connect \o$20 \pipe2_o$43 - connect \o_ok \pipe2_o_ok - connect \o_ok$21 \pipe2_o_ok$44 - connect \p_ready_o \pipe2_p_ready_o - connect \p_valid_i \pipe2_p_valid_i - connect \xer_ca \pipe2_xer_ca - connect \xer_ca$24 \pipe2_xer_ca$47 - connect \xer_ca_ok \pipe2_xer_ca_ok - connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 - connect \xer_ov \pipe2_xer_ov - connect \xer_ov$26 \pipe2_xer_ov$49 - connect \xer_ov_ok \pipe2_xer_ov_ok - connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 - connect \xer_so \pipe2_xer_so - connect \xer_so$28 \pipe2_xer_so$51 - connect \xer_so_ok \pipe2_xer_so_ok - connect \xer_so_ok$29 \pipe2_xer_so_ok$52 - end - connect \muxid 2'00 - connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } - connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } - connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } - connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } - connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } - connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } - connect \muxid$53 \pipe2_muxid$24 - connect \pipe2_n_ready_i \n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \pipe1_xer_ca$23 \xer_ca$2 - connect \pipe1_xer_so$22 \xer_so$1 - connect \pipe1_rb \rb - connect \pipe1_ra \ra - connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \pipe1_muxid$3 2'00 - connect \p_ready_o \pipe1_p_ready_o - connect \pipe1_p_valid_i \p_valid_i - connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } - connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } - connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } - connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } - connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } - connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } - connect \pipe2_muxid \pipe1_muxid - connect \pipe1_n_ready_i \pipe2_p_ready_o - connect \pipe2_p_valid_i \pipe1_n_valid_o -end -attribute \src "libresoc.v:23377.1-23912.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" -attribute \generator "nMigen" -module \alu_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$15 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \br_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \br_op__fn_unit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 11 \br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__data$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__imm_data__ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 10 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$18 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \br_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \br_op__insn_type$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__is_32bit$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 20 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 15 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 16 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 17 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 22 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 21 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__cia$4 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_br_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_br_op__fn_unit$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__data$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_br_op__imm_data__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_br_op__insn$7 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_br_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_br_op__insn_type$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_br_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_br_op__lk$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i - attribute \module_not_derived 1 - attribute \src "libresoc.v:23854.10-23857.4" - cell \n$18 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:23858.10-23861.4" - cell \p$17 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:23862.13-23896.4" - cell \pipe$19 \pipe - connect \br_op__cia \pipe_br_op__cia - connect \br_op__cia$2 \pipe_br_op__cia$4 - connect \br_op__fn_unit \pipe_br_op__fn_unit - connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 - connect \br_op__imm_data__data \pipe_br_op__imm_data__data - connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 - connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok - connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 - connect \br_op__insn \pipe_br_op__insn - connect \br_op__insn$5 \pipe_br_op__insn$7 - connect \br_op__insn_type \pipe_br_op__insn_type - connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 - connect \br_op__is_32bit \pipe_br_op__is_32bit - connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 - connect \br_op__lk \pipe_br_op__lk - connect \br_op__lk$8 \pipe_br_op__lk$10 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe_cr_a - connect \fast1 \pipe_fast1 - connect \fast1$10 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \fast2 \pipe_fast2 - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$3 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - end - connect \muxid 2'00 - connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } - connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } - connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } - connect \muxid$14 \pipe_muxid$3 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_cr_a \cr_a - connect \pipe_fast2 \fast2$2 - connect \pipe_fast1 \fast1$1 - connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i -end -attribute \src "libresoc.v:23916.1-24419.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" -attribute \generator "nMigen" -module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 12 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 16 \cr_a$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 17 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 18 \cr_c - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 8 \cr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \cr_op__fn_unit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 9 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$12 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute 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\enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 10 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 20 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 19 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \pipe_cr_a$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_c - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_cr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_cr_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn$6 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \pipe_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 \pipe_full_cr$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \module_not_derived 1 - attribute \src "libresoc.v:24365.9-24368.4" - cell \n$6 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:24369.9-24372.4" - cell \p$5 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:24373.8-24400.4" - cell \pipe \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe_cr_a - connect \cr_a$6 \pipe_cr_a$8 - connect \cr_a_ok \pipe_cr_a_ok - connect \cr_b \pipe_cr_b - connect \cr_c \pipe_cr_c - connect \cr_op__fn_unit \pipe_cr_op__fn_unit - connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 - connect \cr_op__insn \pipe_cr_op__insn - connect \cr_op__insn$4 \pipe_cr_op__insn$6 - connect \cr_op__insn_type \pipe_cr_op__insn_type - connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 - connect \full_cr \pipe_full_cr - connect \full_cr$5 \pipe_full_cr$7 - connect \full_cr_ok \pipe_full_cr_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$3 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - connect \ra \pipe_ra - connect \rb \pipe_rb - end - connect \muxid 2'00 - connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } - connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } - connect { \o_ok \o } { \pipe_o_ok \pipe_o } - connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } - connect \muxid$9 \pipe_muxid$3 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_cr_c \cr_c - connect \pipe_cr_b \cr_b - connect \pipe_cr_a \cr_a$2 - connect \pipe_full_cr \full_cr$1 - connect \pipe_rb \rb - connect \pipe_ra \ra - connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i -end -attribute \src "libresoc.v:24423.1-25864.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" -attribute \generator "nMigen" -module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 27 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 24 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$88 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$75 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 18 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 25 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$89 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 22 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 23 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 26 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 34 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \pipe_end_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_end_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \pipe_end_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \pipe_end_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \pipe_end_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \pipe_end_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \pipe_end_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len$68 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_end_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_end_logical_op__fn_unit$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__data - attribute \src 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width 32 \pipe_end_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_end_logical_op__insn$69 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_start_logical_op__insn_type$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__invert_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_32bit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__is_signed$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__oe$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__oe__ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__output_carry$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__rc__rc$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__write_cr0$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_start_logical_op__zero_a$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_start_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_start_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_start_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \pipe_start_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_start_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_start_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_start_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_start_xer_so$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 30 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 31 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 28 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 32 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "libresoc.v:25620.10-25623.4" - cell \n$75 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:25624.10-25627.4" - cell \p$74 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:25628.12-25691.4" - cell \pipe_end \pipe_end - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe_end_cr_a - connect \cr_a_ok \pipe_end_cr_a_ok - connect \div_by_zero \pipe_end_div_by_zero - connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 - connect \dividend_neg \pipe_end_dividend_neg - connect \divisor_neg \pipe_end_divisor_neg - connect \logical_op__data_len \pipe_end_logical_op__data_len - connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 - connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit - connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 - connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 - connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 - connect \logical_op__input_carry \pipe_end_logical_op__input_carry - connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 - connect \logical_op__insn \pipe_end_logical_op__insn - connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 - connect \logical_op__insn_type \pipe_end_logical_op__insn_type - connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 - connect \logical_op__invert_in \pipe_end_logical_op__invert_in - connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 - connect \logical_op__invert_out \pipe_end_logical_op__invert_out - connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 - connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit - connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 - connect \logical_op__is_signed \pipe_end_logical_op__is_signed - connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 - connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe - connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 - connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok - connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 - connect \logical_op__output_carry \pipe_end_logical_op__output_carry - connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 - connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok - connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 - connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc - connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 - connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 - connect \logical_op__zero_a \pipe_end_logical_op__zero_a - connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 - connect \muxid \pipe_end_muxid - connect \muxid$1 \pipe_end_muxid$51 - connect \n_ready_i \pipe_end_n_ready_i - connect \n_valid_o \pipe_end_n_valid_o - connect \o \pipe_end_o - connect \o_ok \pipe_end_o_ok - connect \p_ready_o \pipe_end_p_ready_o - connect \p_valid_i \pipe_end_p_valid_i - connect \quotient_root \pipe_end_quotient_root - connect \ra \pipe_end_ra - connect \rb \pipe_end_rb - connect \remainder \pipe_end_remainder - connect \xer_ov \pipe_end_xer_ov - connect \xer_ov_ok \pipe_end_xer_ov_ok - connect \xer_so \pipe_end_xer_so - connect \xer_so$20 \pipe_end_xer_so$70 - connect \xer_so_ok \pipe_end_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:25692.17-25758.4" - cell \pipe_middle_0 \pipe_middle_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \div_by_zero \pipe_middle_0_div_by_zero - connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 - connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 - connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 - connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 - connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 - connect \dividend \pipe_middle_0_dividend - connect \dividend_neg \pipe_middle_0_dividend_neg - connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 - connect \divisor_neg \pipe_middle_0_divisor_neg - connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 - connect \divisor_radicand \pipe_middle_0_divisor_radicand - connect \logical_op__data_len \pipe_middle_0_logical_op__data_len - connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 - connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit - connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 - connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 - connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 - connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry - connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 - connect \logical_op__insn \pipe_middle_0_logical_op__insn - connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 - connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type - connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 - connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in - connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 - connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out - connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 - connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit - connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 - connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed - connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 - connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe - connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 - connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok - connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 - connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry - connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 - connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok - connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 - connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc - connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 - connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 - connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a - connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 - connect \muxid \pipe_middle_0_muxid - connect \muxid$1 \pipe_middle_0_muxid$24 - connect \n_ready_i \pipe_middle_0_n_ready_i - connect \n_valid_o \pipe_middle_0_n_valid_o - connect \operation \pipe_middle_0_operation - connect \p_ready_o \pipe_middle_0_p_ready_o - connect \p_valid_i \pipe_middle_0_p_valid_i - connect \quotient_root \pipe_middle_0_quotient_root - connect \ra \pipe_middle_0_ra - connect \ra$20 \pipe_middle_0_ra$43 - connect \rb \pipe_middle_0_rb - connect \rb$21 \pipe_middle_0_rb$44 - connect \remainder \pipe_middle_0_remainder - connect \xer_so \pipe_middle_0_xer_so - connect \xer_so$22 \pipe_middle_0_xer_so$45 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:25759.14-25818.4" - cell \pipe_start \pipe_start - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \div_by_zero \pipe_start_div_by_zero - connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 - connect \dividend \pipe_start_dividend - connect \dividend_neg \pipe_start_dividend_neg - connect \divisor_neg \pipe_start_divisor_neg - connect \divisor_radicand \pipe_start_divisor_radicand - connect \logical_op__data_len \pipe_start_logical_op__data_len - connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 - connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit - connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 - connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 - connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 - connect \logical_op__input_carry \pipe_start_logical_op__input_carry - connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 - connect \logical_op__insn \pipe_start_logical_op__insn - connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 - connect \logical_op__insn_type \pipe_start_logical_op__insn_type - connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 - connect \logical_op__invert_in \pipe_start_logical_op__invert_in - connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 - connect \logical_op__invert_out \pipe_start_logical_op__invert_out - connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 - connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit - connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 - connect \logical_op__is_signed \pipe_start_logical_op__is_signed - connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 - connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe - connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 - connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok - connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 - connect \logical_op__output_carry \pipe_start_logical_op__output_carry - connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 - connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok - connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 - connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc - connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 - connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 - connect \logical_op__zero_a \pipe_start_logical_op__zero_a - connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 - connect \muxid \pipe_start_muxid - connect \muxid$1 \pipe_start_muxid$2 - connect \n_ready_i \pipe_start_n_ready_i - connect \n_valid_o \pipe_start_n_valid_o - connect \operation \pipe_start_operation - connect \p_ready_o \pipe_start_p_ready_o - connect \p_valid_i \pipe_start_p_valid_i - connect \ra \pipe_start_ra - connect \ra$20 \pipe_start_ra$21 - connect \rb \pipe_start_rb - connect \rb$21 \pipe_start_rb$22 - connect \xer_so \pipe_start_xer_so - connect \xer_so$22 \pipe_start_xer_so$23 - end - connect \muxid 2'00 - connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } - connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } - connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } - connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } - connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } - connect \muxid$71 \pipe_end_muxid$51 - connect \pipe_end_n_ready_i \n_ready_i - connect \n_valid_o \pipe_end_n_valid_o - connect \pipe_start_xer_so$23 \xer_so$1 - connect \pipe_start_rb$22 \rb - connect \pipe_start_ra$21 \ra - connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \pipe_start_muxid$2 2'00 - connect \p_ready_o \pipe_start_p_ready_o - connect \pipe_start_p_valid_i \p_valid_i - connect \pipe_end_remainder \pipe_middle_0_remainder - connect \pipe_end_quotient_root \pipe_middle_0_quotient_root - connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 - connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 - connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 - connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 - connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 - connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 - connect \pipe_end_rb \pipe_middle_0_rb$44 - connect \pipe_end_ra \pipe_middle_0_ra$43 - connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } - connect \pipe_end_muxid \pipe_middle_0_muxid$24 - connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o - connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o - connect \pipe_middle_0_operation \pipe_start_operation - connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand - connect \pipe_middle_0_dividend \pipe_start_dividend - connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero - connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 - connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 - connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg - connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg - connect \pipe_middle_0_xer_so \pipe_start_xer_so - connect \pipe_middle_0_rb \pipe_start_rb - connect \pipe_middle_0_ra \pipe_start_ra - connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } - connect \pipe_middle_0_muxid \pipe_start_muxid - connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o - connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o -end -attribute \src "libresoc.v:25868.1-25926.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" -attribute \generator "nMigen" -module \alu_l - attribute \src "libresoc.v:25869.7-25869.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:25914.3-25922.6" - wire $0\q_int$next[0:0]$852 - attribute \src "libresoc.v:25912.3-25913.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:25914.3-25922.6" - wire $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:25893.7-25893.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:25904.17-25904.96" - wire $and$libresoc.v:25904$842_Y - attribute \src "libresoc.v:25909.17-25909.96" - wire $and$libresoc.v:25909$847_Y - attribute \src "libresoc.v:25906.18-25906.93" - wire $not$libresoc.v:25906$844_Y - attribute \src "libresoc.v:25908.17-25908.92" - wire $not$libresoc.v:25908$846_Y - attribute \src "libresoc.v:25911.17-25911.92" - wire $not$libresoc.v:25911$849_Y - attribute \src "libresoc.v:25905.18-25905.98" - wire $or$libresoc.v:25905$843_Y - attribute \src "libresoc.v:25907.18-25907.99" - wire $or$libresoc.v:25907$845_Y - attribute \src "libresoc.v:25910.17-25910.97" - wire $or$libresoc.v:25910$848_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:25869.7-25869.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25904$842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:25904$842_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:25909$847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:25909$847_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:25906$844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:25906$844_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:25908$846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:25908$846_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:25911$849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:25911$849_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25905$843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:25905$843_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:25907$845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:25907$845_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:25910$848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:25910$848_Y - end - attribute \src "libresoc.v:25869.7-25869.20" - process $proc$libresoc.v:25869$854 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:25893.7-25893.19" - process $proc$libresoc.v:25893$855 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:25912.3-25913.27" - process $proc$libresoc.v:25912$850 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:25914.3-25922.6" - process $proc$libresoc.v:25914$851 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:25915.5-25915.29" - switch \initial - attribute \src "libresoc.v:25915.9-25915.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$853 1'0 - case - assign $1\q_int$next[0:0]$853 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$852 - end - connect \$9 $and$libresoc.v:25904$842_Y - connect \$11 $or$libresoc.v:25905$843_Y - connect \$13 $not$libresoc.v:25906$844_Y - connect \$15 $or$libresoc.v:25907$845_Y - connect \$1 $not$libresoc.v:25908$846_Y - connect \$3 $and$libresoc.v:25909$847_Y - connect \$5 $or$libresoc.v:25910$848_Y - connect \$7 $not$libresoc.v:25911$849_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:25930.1-25988.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" -attribute \generator "nMigen" -module \alu_l$107 - attribute \src "libresoc.v:25931.7-25931.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:25976.3-25984.6" - wire $0\q_int$next[0:0]$866 - attribute \src "libresoc.v:25974.3-25975.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:25976.3-25984.6" - wire $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:25955.7-25955.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:25966.17-25966.96" - wire $and$libresoc.v:25966$856_Y - attribute \src "libresoc.v:25971.17-25971.96" - wire $and$libresoc.v:25971$861_Y - attribute \src "libresoc.v:25968.18-25968.93" - wire $not$libresoc.v:25968$858_Y - attribute \src "libresoc.v:25970.17-25970.92" - wire $not$libresoc.v:25970$860_Y - attribute \src "libresoc.v:25973.17-25973.92" - wire $not$libresoc.v:25973$863_Y - attribute \src "libresoc.v:25967.18-25967.98" - wire $or$libresoc.v:25967$857_Y - attribute \src "libresoc.v:25969.18-25969.99" - wire $or$libresoc.v:25969$859_Y - attribute \src "libresoc.v:25972.17-25972.97" - wire $or$libresoc.v:25972$862_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:25931.7-25931.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:25966$856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:25966$856_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:25971$861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:25971$861_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:25968$858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:25968$858_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:25970$860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:25970$860_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:25973$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:25973$863_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:25967$857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:25967$857_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:25969$859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:25969$859_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:25972$862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:25972$862_Y - end - attribute \src "libresoc.v:25931.7-25931.20" - process $proc$libresoc.v:25931$868 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:25955.7-25955.19" - process $proc$libresoc.v:25955$869 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:25974.3-25975.27" - process $proc$libresoc.v:25974$864 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:25976.3-25984.6" - process $proc$libresoc.v:25976$865 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:25977.5-25977.29" - switch \initial - attribute \src "libresoc.v:25977.9-25977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$867 1'0 - case - assign $1\q_int$next[0:0]$867 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$866 - end - connect \$9 $and$libresoc.v:25966$856_Y - connect \$11 $or$libresoc.v:25967$857_Y - connect \$13 $not$libresoc.v:25968$858_Y - connect \$15 $or$libresoc.v:25969$859_Y - connect \$1 $not$libresoc.v:25970$860_Y - connect \$3 $and$libresoc.v:25971$861_Y - connect \$5 $or$libresoc.v:25972$862_Y - connect \$7 $not$libresoc.v:25973$863_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:25992.1-26050.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" -attribute \generator "nMigen" -module \alu_l$125 - attribute \src "libresoc.v:25993.7-25993.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26038.3-26046.6" - wire $0\q_int$next[0:0]$880 - attribute \src "libresoc.v:26036.3-26037.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26038.3-26046.6" - wire $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26017.7-26017.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26028.17-26028.96" - wire $and$libresoc.v:26028$870_Y - attribute \src "libresoc.v:26033.17-26033.96" - wire $and$libresoc.v:26033$875_Y - attribute \src "libresoc.v:26030.18-26030.93" - wire $not$libresoc.v:26030$872_Y - attribute \src "libresoc.v:26032.17-26032.92" - wire $not$libresoc.v:26032$874_Y - attribute \src "libresoc.v:26035.17-26035.92" - wire $not$libresoc.v:26035$877_Y - attribute \src "libresoc.v:26029.18-26029.98" - wire $or$libresoc.v:26029$871_Y - attribute \src "libresoc.v:26031.18-26031.99" - wire $or$libresoc.v:26031$873_Y - attribute \src "libresoc.v:26034.17-26034.97" - wire $or$libresoc.v:26034$876_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:25993.7-25993.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26028$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:26028$870_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26033$875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:26033$875_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26030$872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:26030$872_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26032$874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26032$874_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26035$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26035$877_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26029$871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:26029$871_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26031$873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:26031$873_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26034$876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:26034$876_Y - end - attribute \src "libresoc.v:25993.7-25993.20" - process $proc$libresoc.v:25993$882 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26017.7-26017.19" - process $proc$libresoc.v:26017$883 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:26036.3-26037.27" - process $proc$libresoc.v:26036$878 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:26038.3-26046.6" - process $proc$libresoc.v:26038$879 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26039.5-26039.29" - switch \initial - attribute \src "libresoc.v:26039.9-26039.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$881 1'0 - case - assign $1\q_int$next[0:0]$881 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$880 - end - connect \$9 $and$libresoc.v:26028$870_Y - connect \$11 $or$libresoc.v:26029$871_Y - connect \$13 $not$libresoc.v:26030$872_Y - connect \$15 $or$libresoc.v:26031$873_Y - connect \$1 $not$libresoc.v:26032$874_Y - connect \$3 $and$libresoc.v:26033$875_Y - connect \$5 $or$libresoc.v:26034$876_Y - connect \$7 $not$libresoc.v:26035$877_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:26054.1-26112.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" -attribute \generator "nMigen" -module \alu_l$128 - attribute \src "libresoc.v:26055.7-26055.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26100.3-26108.6" - wire $0\q_int$next[0:0]$894 - attribute \src "libresoc.v:26098.3-26099.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26100.3-26108.6" - wire $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26079.7-26079.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26090.17-26090.96" - wire $and$libresoc.v:26090$884_Y - attribute \src "libresoc.v:26095.17-26095.96" - wire $and$libresoc.v:26095$889_Y - attribute \src "libresoc.v:26092.18-26092.93" - wire $not$libresoc.v:26092$886_Y - attribute \src "libresoc.v:26094.17-26094.92" - wire $not$libresoc.v:26094$888_Y - attribute \src "libresoc.v:26097.17-26097.92" - wire $not$libresoc.v:26097$891_Y - attribute \src "libresoc.v:26091.18-26091.98" - wire $or$libresoc.v:26091$885_Y - attribute \src "libresoc.v:26093.18-26093.99" - wire $or$libresoc.v:26093$887_Y - attribute \src "libresoc.v:26096.17-26096.97" - wire $or$libresoc.v:26096$890_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:26055.7-26055.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26090$884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:26090$884_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26095$889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:26095$889_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26092$886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:26092$886_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26094$888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26094$888_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26097$891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26097$891_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26091$885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:26091$885_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26093$887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:26093$887_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26096$890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:26096$890_Y - end - attribute \src "libresoc.v:26055.7-26055.20" - process $proc$libresoc.v:26055$896 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26079.7-26079.19" - process $proc$libresoc.v:26079$897 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:26098.3-26099.27" - process $proc$libresoc.v:26098$892 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:26100.3-26108.6" - process $proc$libresoc.v:26100$893 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26101.5-26101.29" - switch \initial - attribute \src "libresoc.v:26101.9-26101.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$895 1'0 - case - assign $1\q_int$next[0:0]$895 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$894 - end - connect \$9 $and$libresoc.v:26090$884_Y - connect \$11 $or$libresoc.v:26091$885_Y - connect \$13 $not$libresoc.v:26092$886_Y - connect \$15 $or$libresoc.v:26093$887_Y - connect \$1 $not$libresoc.v:26094$888_Y - connect \$3 $and$libresoc.v:26095$889_Y - connect \$5 $or$libresoc.v:26096$890_Y - connect \$7 $not$libresoc.v:26097$891_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:26116.1-26174.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" -attribute \generator "nMigen" -module \alu_l$16 - attribute \src "libresoc.v:26117.7-26117.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26162.3-26170.6" - wire $0\q_int$next[0:0]$908 - attribute \src "libresoc.v:26160.3-26161.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26162.3-26170.6" - wire $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26141.7-26141.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26152.17-26152.96" - wire $and$libresoc.v:26152$898_Y - attribute \src "libresoc.v:26157.17-26157.96" - wire $and$libresoc.v:26157$903_Y - attribute \src "libresoc.v:26154.18-26154.93" - wire $not$libresoc.v:26154$900_Y - attribute \src "libresoc.v:26156.17-26156.92" - wire $not$libresoc.v:26156$902_Y - attribute \src "libresoc.v:26159.17-26159.92" - wire $not$libresoc.v:26159$905_Y - attribute \src "libresoc.v:26153.18-26153.98" - wire $or$libresoc.v:26153$899_Y - attribute \src "libresoc.v:26155.18-26155.99" - wire $or$libresoc.v:26155$901_Y - attribute \src "libresoc.v:26158.17-26158.97" - wire $or$libresoc.v:26158$904_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:26117.7-26117.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26152$898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:26152$898_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26157$903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:26157$903_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26154$900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:26154$900_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26156$902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26156$902_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26159$905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26159$905_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26153$899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:26153$899_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26155$901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:26155$901_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26158$904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:26158$904_Y - end - attribute \src "libresoc.v:26117.7-26117.20" - process $proc$libresoc.v:26117$910 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26141.7-26141.19" - process $proc$libresoc.v:26141$911 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:26160.3-26161.27" - process $proc$libresoc.v:26160$906 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:26162.3-26170.6" - process $proc$libresoc.v:26162$907 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26163.5-26163.29" - switch \initial - attribute \src "libresoc.v:26163.9-26163.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$909 1'0 - case - assign $1\q_int$next[0:0]$909 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$908 - end - connect \$9 $and$libresoc.v:26152$898_Y - connect \$11 $or$libresoc.v:26153$899_Y - connect \$13 $not$libresoc.v:26154$900_Y - connect \$15 $or$libresoc.v:26155$901_Y - connect \$1 $not$libresoc.v:26156$902_Y - connect \$3 $and$libresoc.v:26157$903_Y - connect \$5 $or$libresoc.v:26158$904_Y - connect \$7 $not$libresoc.v:26159$905_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:26178.1-26236.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" -attribute \generator "nMigen" -module \alu_l$29 - attribute \src "libresoc.v:26179.7-26179.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26224.3-26232.6" - wire $0\q_int$next[0:0]$922 - attribute \src "libresoc.v:26222.3-26223.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26224.3-26232.6" - wire $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26203.7-26203.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26214.17-26214.96" - wire $and$libresoc.v:26214$912_Y - attribute \src "libresoc.v:26219.17-26219.96" - wire $and$libresoc.v:26219$917_Y - attribute \src "libresoc.v:26216.18-26216.93" - wire $not$libresoc.v:26216$914_Y - attribute \src "libresoc.v:26218.17-26218.92" - wire $not$libresoc.v:26218$916_Y - attribute \src "libresoc.v:26221.17-26221.92" - wire $not$libresoc.v:26221$919_Y - attribute \src "libresoc.v:26215.18-26215.98" - wire $or$libresoc.v:26215$913_Y - attribute \src "libresoc.v:26217.18-26217.99" - wire $or$libresoc.v:26217$915_Y - attribute \src "libresoc.v:26220.17-26220.97" - wire $or$libresoc.v:26220$918_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:26179.7-26179.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26214$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:26214$912_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26219$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:26219$917_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26216$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:26216$914_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26218$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26218$916_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26221$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26221$919_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26215$913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:26215$913_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26217$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:26217$915_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26220$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:26220$918_Y - end - attribute \src "libresoc.v:26179.7-26179.20" - process $proc$libresoc.v:26179$924 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26203.7-26203.19" - process $proc$libresoc.v:26203$925 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:26222.3-26223.27" - process $proc$libresoc.v:26222$920 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:26224.3-26232.6" - process $proc$libresoc.v:26224$921 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26225.5-26225.29" - switch \initial - attribute \src "libresoc.v:26225.9-26225.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$923 1'0 - case - assign $1\q_int$next[0:0]$923 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$922 - end - connect \$9 $and$libresoc.v:26214$912_Y - connect \$11 $or$libresoc.v:26215$913_Y - connect \$13 $not$libresoc.v:26216$914_Y - connect \$15 $or$libresoc.v:26217$915_Y - connect \$1 $not$libresoc.v:26218$916_Y - connect \$3 $and$libresoc.v:26219$917_Y - connect \$5 $or$libresoc.v:26220$918_Y - connect \$7 $not$libresoc.v:26221$919_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:26240.1-26298.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" -attribute \generator "nMigen" -module \alu_l$45 - attribute \src "libresoc.v:26241.7-26241.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26286.3-26294.6" - wire $0\q_int$next[0:0]$936 - attribute \src "libresoc.v:26284.3-26285.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26286.3-26294.6" - wire $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26265.7-26265.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26276.17-26276.96" - wire $and$libresoc.v:26276$926_Y - attribute \src "libresoc.v:26281.17-26281.96" - wire $and$libresoc.v:26281$931_Y - attribute \src "libresoc.v:26278.18-26278.93" - wire $not$libresoc.v:26278$928_Y - attribute \src "libresoc.v:26280.17-26280.92" - wire $not$libresoc.v:26280$930_Y - attribute \src "libresoc.v:26283.17-26283.92" - wire $not$libresoc.v:26283$933_Y - attribute \src "libresoc.v:26277.18-26277.98" - wire $or$libresoc.v:26277$927_Y - attribute \src "libresoc.v:26279.18-26279.99" - wire $or$libresoc.v:26279$929_Y - attribute \src "libresoc.v:26282.17-26282.97" - wire $or$libresoc.v:26282$932_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:26241.7-26241.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26276$926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:26276$926_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26281$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:26281$931_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26278$928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:26278$928_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26280$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26280$930_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26283$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26283$933_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26277$927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:26277$927_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26279$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:26279$929_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26282$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:26282$932_Y - end - attribute \src "libresoc.v:26241.7-26241.20" - process $proc$libresoc.v:26241$938 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26265.7-26265.19" - process $proc$libresoc.v:26265$939 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:26284.3-26285.27" - process $proc$libresoc.v:26284$934 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:26286.3-26294.6" - process $proc$libresoc.v:26286$935 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26287.5-26287.29" - switch \initial - attribute \src "libresoc.v:26287.9-26287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$937 1'0 - case - assign $1\q_int$next[0:0]$937 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$936 - end - connect \$9 $and$libresoc.v:26276$926_Y - connect \$11 $or$libresoc.v:26277$927_Y - connect \$13 $not$libresoc.v:26278$928_Y - connect \$15 $or$libresoc.v:26279$929_Y - connect \$1 $not$libresoc.v:26280$930_Y - connect \$3 $and$libresoc.v:26281$931_Y - connect \$5 $or$libresoc.v:26282$932_Y - connect \$7 $not$libresoc.v:26283$933_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:26302.1-26360.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" -attribute \generator "nMigen" -module \alu_l$61 - attribute \src "libresoc.v:26303.7-26303.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26348.3-26356.6" - wire $0\q_int$next[0:0]$950 - attribute \src "libresoc.v:26346.3-26347.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26348.3-26356.6" - wire $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26327.7-26327.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26338.17-26338.96" - wire $and$libresoc.v:26338$940_Y - attribute \src "libresoc.v:26343.17-26343.96" - wire $and$libresoc.v:26343$945_Y - attribute \src "libresoc.v:26340.18-26340.93" - wire $not$libresoc.v:26340$942_Y - attribute \src "libresoc.v:26342.17-26342.92" - wire $not$libresoc.v:26342$944_Y - attribute \src "libresoc.v:26345.17-26345.92" - wire $not$libresoc.v:26345$947_Y - attribute \src "libresoc.v:26339.18-26339.98" - wire $or$libresoc.v:26339$941_Y - attribute \src "libresoc.v:26341.18-26341.99" - wire $or$libresoc.v:26341$943_Y - attribute \src "libresoc.v:26344.17-26344.97" - wire $or$libresoc.v:26344$946_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:26303.7-26303.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26338$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:26338$940_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26343$945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:26343$945_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26340$942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:26340$942_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26342$944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26342$944_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26345$947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26345$947_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26339$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:26339$941_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26341$943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:26341$943_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26344$946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:26344$946_Y - end - attribute \src "libresoc.v:26303.7-26303.20" - process $proc$libresoc.v:26303$952 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26327.7-26327.19" - process $proc$libresoc.v:26327$953 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:26346.3-26347.27" - process $proc$libresoc.v:26346$948 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:26348.3-26356.6" - process $proc$libresoc.v:26348$949 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26349.5-26349.29" - switch \initial - attribute \src "libresoc.v:26349.9-26349.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$951 1'0 - case - assign $1\q_int$next[0:0]$951 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$950 - end - connect \$9 $and$libresoc.v:26338$940_Y - connect \$11 $or$libresoc.v:26339$941_Y - connect \$13 $not$libresoc.v:26340$942_Y - connect \$15 $or$libresoc.v:26341$943_Y - connect \$1 $not$libresoc.v:26342$944_Y - connect \$3 $and$libresoc.v:26343$945_Y - connect \$5 $or$libresoc.v:26344$946_Y - connect \$7 $not$libresoc.v:26345$947_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:26364.1-26422.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" -attribute \generator "nMigen" -module \alu_l$73 - attribute \src "libresoc.v:26365.7-26365.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26410.3-26418.6" - wire $0\q_int$next[0:0]$964 - attribute \src "libresoc.v:26408.3-26409.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26410.3-26418.6" - wire $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26389.7-26389.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26400.17-26400.96" - wire $and$libresoc.v:26400$954_Y - attribute \src "libresoc.v:26405.17-26405.96" - wire $and$libresoc.v:26405$959_Y - attribute \src "libresoc.v:26402.18-26402.93" - wire $not$libresoc.v:26402$956_Y - attribute \src "libresoc.v:26404.17-26404.92" - wire $not$libresoc.v:26404$958_Y - attribute \src "libresoc.v:26407.17-26407.92" - wire $not$libresoc.v:26407$961_Y - attribute \src "libresoc.v:26401.18-26401.98" - wire $or$libresoc.v:26401$955_Y - attribute \src "libresoc.v:26403.18-26403.99" - wire $or$libresoc.v:26403$957_Y - attribute \src "libresoc.v:26406.17-26406.97" - wire $or$libresoc.v:26406$960_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:26365.7-26365.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26400$954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:26400$954_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:26405$959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:26405$959_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:26402$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $not$libresoc.v:26402$956_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:26404$958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26404$958_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:26407$961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $not$libresoc.v:26407$961_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:26401$955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alu - connect \Y $or$libresoc.v:26401$955_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:26403$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $or$libresoc.v:26403$957_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:26406$960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alu - connect \Y $or$libresoc.v:26406$960_Y - end - attribute \src "libresoc.v:26365.7-26365.20" - process $proc$libresoc.v:26365$966 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:26389.7-26389.19" - process $proc$libresoc.v:26389$967 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:26408.3-26409.27" - process $proc$libresoc.v:26408$962 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:26410.3-26418.6" - process $proc$libresoc.v:26410$963 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26411.5-26411.29" - switch \initial - attribute \src "libresoc.v:26411.9-26411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$965 1'0 - case - assign $1\q_int$next[0:0]$965 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$964 - end - connect \$9 $and$libresoc.v:26400$954_Y - connect \$11 $or$libresoc.v:26401$955_Y - connect \$13 $not$libresoc.v:26402$956_Y - connect \$15 $or$libresoc.v:26403$957_Y - connect \$1 $not$libresoc.v:26404$958_Y - connect \$3 $and$libresoc.v:26405$959_Y - connect \$5 $or$libresoc.v:26406$960_Y - connect \$7 $not$libresoc.v:26407$961_Y - connect \qlq_alu \$15 - connect \qn_alu \$13 - connect \q_alu \$11 -end -attribute \src "libresoc.v:26426.1-26484.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_l" -attribute \generator "nMigen" -module \alu_l$90 - attribute \src "libresoc.v:26427.7-26427.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:26472.3-26480.6" - wire $0\q_int$next[0:0]$978 - attribute \src "libresoc.v:26470.3-26471.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:26472.3-26480.6" - wire $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26451.7-26451.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:26462.17-26462.96" - wire $and$libresoc.v:26462$968_Y - attribute \src "libresoc.v:26467.17-26467.96" - wire $and$libresoc.v:26467$973_Y - attribute \src "libresoc.v:26464.18-26464.93" - wire $not$libresoc.v:26464$970_Y - attribute \src "libresoc.v:26466.17-26466.92" - wire $not$libresoc.v:26466$972_Y - attribute \src "libresoc.v:26469.17-26469.92" - wire $not$libresoc.v:26469$975_Y - attribute \src "libresoc.v:26463.18-26463.98" - wire $or$libresoc.v:26463$969_Y - attribute \src "libresoc.v:26465.18-26465.99" - wire $or$libresoc.v:26465$971_Y - attribute \src "libresoc.v:26468.17-26468.97" - wire $or$libresoc.v:26468$974_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:26427.7-26427.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:26462$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 22 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$61 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 7 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$48 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 16 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 23 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$62 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \logical_pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \logical_pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe1_logical_op__data_len - attribute \src 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"OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe2_logical_op__insn_type$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_in$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__output_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_pipe2_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe2_muxid$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \logical_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \logical_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \logical_pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \logical_pipe2_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \logical_pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \logical_pipe2_o_ok$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \logical_pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \logical_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \logical_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \logical_pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 5 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 4 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 28 \xer_so - attribute \module_not_derived 1 - attribute \src "libresoc.v:27343.17-27397.4" - cell \logical_pipe1 \logical_pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \logical_pipe1_cr_a - connect \cr_a_ok \logical_pipe1_cr_a_ok - connect \logical_op__data_len \logical_pipe1_logical_op__data_len - connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 - connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit - connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 - connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 - connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 - connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry - connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 - connect \logical_op__insn \logical_pipe1_logical_op__insn - connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 - connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type - connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 - connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in - connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 - connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out - connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 - connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit - connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 - connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed - connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 - connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe - connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 - connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok - connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 - connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry - connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 - connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok - connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 - connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc - connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 - connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 - connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a - connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 - connect \muxid \logical_pipe1_muxid - connect \muxid$1 \logical_pipe1_muxid$1 - connect \n_ready_i \logical_pipe1_n_ready_i - connect \n_valid_o \logical_pipe1_n_valid_o - connect \o \logical_pipe1_o - connect \o_ok \logical_pipe1_o_ok - connect \p_ready_o \logical_pipe1_p_ready_o - connect \p_valid_i \logical_pipe1_p_valid_i - connect \ra \logical_pipe1_ra - connect \rb \logical_pipe1_rb - connect \xer_so \logical_pipe1_xer_so - connect \xer_so$20 \logical_pipe1_xer_so$20 - connect \xer_so_ok \logical_pipe1_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:27398.17-27453.4" - cell \logical_pipe2 \logical_pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \logical_pipe2_cr_a - connect \cr_a$22 \logical_pipe2_cr_a$42 - connect \cr_a_ok \logical_pipe2_cr_a_ok - connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 - connect \logical_op__data_len \logical_pipe2_logical_op__data_len - connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 - connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit - connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry - connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 - connect \logical_op__insn \logical_pipe2_logical_op__insn - connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 - connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type - connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 - connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in - connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 - connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out - connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 - connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit - connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 - connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed - connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 - connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe - connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 - connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok - connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 - connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry - connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 - connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok - connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 - connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc - connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 - connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a - connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 - connect \muxid \logical_pipe2_muxid - connect \muxid$1 \logical_pipe2_muxid$21 - connect \n_ready_i \logical_pipe2_n_ready_i - connect \n_valid_o \logical_pipe2_n_valid_o - connect \o \logical_pipe2_o - connect \o$20 \logical_pipe2_o$40 - connect \o_ok \logical_pipe2_o_ok - connect \o_ok$21 \logical_pipe2_o_ok$41 - connect \p_ready_o \logical_pipe2_p_ready_o - connect \p_valid_i \logical_pipe2_p_valid_i - connect \xer_so \logical_pipe2_xer_so - connect \xer_so_ok \logical_pipe2_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:27454.10-27457.4" - cell \n$47 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:27458.10-27461.4" - cell \p$46 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - connect \muxid 2'00 - connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } - connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } - connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } - connect \muxid$44 \logical_pipe2_muxid$21 - connect \logical_pipe2_n_ready_i \n_ready_i - connect \n_valid_o \logical_pipe2_n_valid_o - connect \logical_pipe1_xer_so$20 \xer_so - connect \logical_pipe1_rb \rb - connect \logical_pipe1_ra \ra - connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \logical_pipe1_muxid$1 2'00 - connect \p_ready_o \logical_pipe1_p_ready_o - connect \logical_pipe1_p_valid_i \p_valid_i - connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } - connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } - connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } - connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } - connect \logical_pipe2_muxid \logical_pipe1_muxid - connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o - connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o -end -attribute \src "libresoc.v:27487.1-28680.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" -attribute \generator "nMigen" -module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \cr_a_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 9 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$61 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$58 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe1_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe1_mul_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__imm_data__ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn$14 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe1_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe1_mul_op__insn_type$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__is_32bit$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__is_signed$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__oe$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__oe__ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__rc__rc$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe1_mul_op__write_cr0$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \mul_pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \mul_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \mul_pipe1_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \mul_pipe1_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \mul_pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \mul_pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe1_xer_so$17 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe2_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe2_mul_op__fn_unit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__data$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__imm_data__ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn$30 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_32bit$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__is_signed$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__oe$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__oe__ok$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__rc__rc$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe2_mul_op__write_cr0$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid$18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \mul_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \mul_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \mul_pipe2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul_pipe2_neg_res$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \mul_pipe2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \mul_pipe2_neg_res32$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \mul_pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \mul_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe2_xer_so$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \mul_pipe3_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul_pipe3_cr_a_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe3_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_pipe3_mul_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__data$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__imm_data__ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn$46 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_32bit$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__is_signed$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__oe__ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_pipe3_mul_op__write_cr0$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \mul_pipe3_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \mul_pipe3_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul_pipe3_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \mul_pipe3_neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \mul_pipe3_o$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul_pipe3_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \mul_pipe3_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \mul_pipe3_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \mul_pipe3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul_pipe3_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul_pipe3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul_pipe3_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul_pipe3_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 7 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 28 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 27 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 26 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "libresoc.v:28508.13-28549.4" - cell \mul_pipe1 \mul_pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 - connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 - connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 - connect \mul_op__insn \mul_pipe1_mul_op__insn - connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 - connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type - connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 - connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 - connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed - connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 - connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 - connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 - connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 - connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 - connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 - connect \muxid \mul_pipe1_muxid - connect \muxid$1 \mul_pipe1_muxid$2 - connect \n_ready_i \mul_pipe1_n_ready_i - connect \n_valid_o \mul_pipe1_n_valid_o - connect \neg_res \mul_pipe1_neg_res - connect \neg_res32 \mul_pipe1_neg_res32 - connect \p_ready_o \mul_pipe1_p_ready_o - connect \p_valid_i \mul_pipe1_p_valid_i - connect \ra \mul_pipe1_ra - connect \ra$14 \mul_pipe1_ra$15 - connect \rb \mul_pipe1_rb - connect \rb$15 \mul_pipe1_rb$16 - connect \xer_so \mul_pipe1_xer_so - connect \xer_so$16 \mul_pipe1_xer_so$17 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:28550.13-28592.4" - cell \mul_pipe2 \mul_pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 - connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 - connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 - connect \mul_op__insn \mul_pipe2_mul_op__insn - connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 - connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type - connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 - connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 - connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed - connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 - connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 - connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 - connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 - connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 - connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 - connect \muxid \mul_pipe2_muxid - connect \muxid$1 \mul_pipe2_muxid$18 - connect \n_ready_i \mul_pipe2_n_ready_i - connect \n_valid_o \mul_pipe2_n_valid_o - connect \neg_res \mul_pipe2_neg_res - connect \neg_res$15 \mul_pipe2_neg_res$32 - connect \neg_res32 \mul_pipe2_neg_res32 - connect \neg_res32$16 \mul_pipe2_neg_res32$33 - connect \o \mul_pipe2_o - connect \p_ready_o \mul_pipe2_p_ready_o - connect \p_valid_i \mul_pipe2_p_valid_i - connect \ra \mul_pipe2_ra - connect \rb \mul_pipe2_rb - connect \xer_so \mul_pipe2_xer_so - connect \xer_so$14 \mul_pipe2_xer_so$31 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:28593.13-28638.4" - cell \mul_pipe3 \mul_pipe3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \mul_pipe3_cr_a - connect \cr_a_ok \mul_pipe3_cr_a_ok - connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 - connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 - connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 - connect \mul_op__insn \mul_pipe3_mul_op__insn - connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 - connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type - connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 - connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 - connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed - connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 - connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 - connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 - connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 - connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 - connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 - connect \muxid \mul_pipe3_muxid - connect \muxid$1 \mul_pipe3_muxid$34 - connect \n_ready_i \mul_pipe3_n_ready_i - connect \n_valid_o \mul_pipe3_n_valid_o - connect \neg_res \mul_pipe3_neg_res - connect \neg_res32 \mul_pipe3_neg_res32 - connect \o \mul_pipe3_o - connect \o$14 \mul_pipe3_o$47 - connect \o_ok \mul_pipe3_o_ok - connect \p_ready_o \mul_pipe3_p_ready_o - connect \p_valid_i \mul_pipe3_p_valid_i - connect \xer_ov \mul_pipe3_xer_ov - connect \xer_ov_ok \mul_pipe3_xer_ov_ok - connect \xer_so \mul_pipe3_xer_so - connect \xer_so$15 \mul_pipe3_xer_so$48 - connect \xer_so_ok \mul_pipe3_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:28639.10-28642.4" - cell \n$92 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:28643.10-28646.4" - cell \p$91 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - connect \muxid 2'00 - connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } - connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } - connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } - connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } - connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } - connect \muxid$49 \mul_pipe3_muxid$34 - connect \mul_pipe3_n_ready_i \n_ready_i - connect \n_valid_o \mul_pipe3_n_valid_o - connect \mul_pipe1_xer_so$17 \xer_so$1 - connect \mul_pipe1_rb$16 \rb - connect \mul_pipe1_ra$15 \ra - connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul_pipe1_muxid$2 2'00 - connect \p_ready_o \mul_pipe1_p_ready_o - connect \mul_pipe1_p_valid_i \p_valid_i - connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 - connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 - connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 - connect \mul_pipe3_o \mul_pipe2_o - connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } - connect \mul_pipe3_muxid \mul_pipe2_muxid$18 - connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o - connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o - connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 - connect \mul_pipe2_neg_res \mul_pipe1_neg_res - connect \mul_pipe2_xer_so \mul_pipe1_xer_so - connect \mul_pipe2_rb \mul_pipe1_rb - connect \mul_pipe2_ra \mul_pipe1_ra - connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } - connect \mul_pipe2_muxid \mul_pipe1_muxid - connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o - connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o -end -attribute \src "libresoc.v:28684.1-29699.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" -attribute \generator "nMigen" -module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 33 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 32 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_sr_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__imm_data__ok$6 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe1_sr_op__input_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute 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attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute 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wire \pipe2_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__invert_in$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__is_32bit$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__is_signed$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__oe__oe$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__oe__ok - attribute \src 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\pipe2_sr_op__rc__rc$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe2_sr_op__write_cr0$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe2_xer_ca$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_ca_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 29 \rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 8 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$50 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 23 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$63 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 21 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 22 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 26 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 31 \xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 30 \xer_so - attribute \module_not_derived 1 - attribute \src "libresoc.v:29551.11-29554.4" - cell \n$109 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:29555.11-29558.4" - cell \p$108 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:29559.15-29615.4" - cell \pipe1$110 \pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe1_cr_a - connect \cr_a_ok \pipe1_cr_a_ok - connect \muxid \pipe1_muxid - connect \muxid$1 \pipe1_muxid$2 - connect \n_ready_i \pipe1_n_ready_i - connect \n_valid_o \pipe1_n_valid_o - connect \o \pipe1_o - connect \o_ok \pipe1_o_ok - connect \p_ready_o \pipe1_p_ready_o - connect \p_valid_i \pipe1_p_valid_i - connect \ra \pipe1_ra - connect \rb \pipe1_rb - connect \rc \pipe1_rc - connect \sr_op__fn_unit \pipe1_sr_op__fn_unit - connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 - connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 - connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 - connect \sr_op__input_carry \pipe1_sr_op__input_carry - connect \sr_op__input_carry$12 \pipe1_sr_op__input_carry$13 - connect \sr_op__input_cr \pipe1_sr_op__input_cr - connect \sr_op__input_cr$14 \pipe1_sr_op__input_cr$15 - connect \sr_op__insn \pipe1_sr_op__insn - connect \sr_op__insn$18 \pipe1_sr_op__insn$19 - connect \sr_op__insn_type \pipe1_sr_op__insn_type - connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 - connect \sr_op__invert_in \pipe1_sr_op__invert_in - connect \sr_op__invert_in$11 \pipe1_sr_op__invert_in$12 - connect \sr_op__is_32bit \pipe1_sr_op__is_32bit - connect \sr_op__is_32bit$16 \pipe1_sr_op__is_32bit$17 - connect \sr_op__is_signed \pipe1_sr_op__is_signed - connect \sr_op__is_signed$17 \pipe1_sr_op__is_signed$18 - connect \sr_op__oe__oe \pipe1_sr_op__oe__oe - connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 - connect \sr_op__oe__ok \pipe1_sr_op__oe__ok - connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 - connect \sr_op__output_carry \pipe1_sr_op__output_carry - connect \sr_op__output_carry$13 \pipe1_sr_op__output_carry$14 - connect \sr_op__output_cr \pipe1_sr_op__output_cr - connect \sr_op__output_cr$15 \pipe1_sr_op__output_cr$16 - connect \sr_op__rc__ok \pipe1_sr_op__rc__ok - connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 - connect \sr_op__rc__rc \pipe1_sr_op__rc__rc - connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 - connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 - connect \xer_ca \pipe1_xer_ca - connect \xer_ca$20 \pipe1_xer_ca$21 - connect \xer_ca_ok \pipe1_xer_ca_ok - connect \xer_so \pipe1_xer_so - connect \xer_so$19 \pipe1_xer_so$20 - connect \xer_so_ok \pipe1_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:29616.15-29673.4" - cell \pipe2$115 \pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \pipe2_cr_a - connect \cr_a$21 \pipe2_cr_a$42 - connect \cr_a_ok \pipe2_cr_a_ok - connect \cr_a_ok$22 \pipe2_cr_a_ok$43 - connect \muxid \pipe2_muxid - connect \muxid$1 \pipe2_muxid$22 - connect \n_ready_i \pipe2_n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \o \pipe2_o - connect \o$19 \pipe2_o$40 - connect \o_ok \pipe2_o_ok - connect \o_ok$20 \pipe2_o_ok$41 - connect \p_ready_o \pipe2_p_ready_o - connect \p_valid_i \pipe2_p_valid_i - connect \sr_op__fn_unit \pipe2_sr_op__fn_unit - connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$24 - connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$25 - connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$26 - connect \sr_op__input_carry \pipe2_sr_op__input_carry - connect \sr_op__input_carry$12 \pipe2_sr_op__input_carry$33 - connect \sr_op__input_cr \pipe2_sr_op__input_cr - connect \sr_op__input_cr$14 \pipe2_sr_op__input_cr$35 - connect \sr_op__insn \pipe2_sr_op__insn - connect \sr_op__insn$18 \pipe2_sr_op__insn$39 - connect \sr_op__insn_type \pipe2_sr_op__insn_type - connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$23 - connect \sr_op__invert_in \pipe2_sr_op__invert_in - connect \sr_op__invert_in$11 \pipe2_sr_op__invert_in$32 - connect \sr_op__is_32bit \pipe2_sr_op__is_32bit - connect \sr_op__is_32bit$16 \pipe2_sr_op__is_32bit$37 - connect \sr_op__is_signed \pipe2_sr_op__is_signed - connect \sr_op__is_signed$17 \pipe2_sr_op__is_signed$38 - connect \sr_op__oe__oe \pipe2_sr_op__oe__oe - connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$29 - connect \sr_op__oe__ok \pipe2_sr_op__oe__ok - connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$30 - connect \sr_op__output_carry \pipe2_sr_op__output_carry - connect \sr_op__output_carry$13 \pipe2_sr_op__output_carry$34 - connect \sr_op__output_cr \pipe2_sr_op__output_cr - connect \sr_op__output_cr$15 \pipe2_sr_op__output_cr$36 - connect \sr_op__rc__ok \pipe2_sr_op__rc__ok - connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$28 - connect \sr_op__rc__rc \pipe2_sr_op__rc__rc - connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$27 - connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$31 - connect \xer_ca \pipe2_xer_ca - connect \xer_ca$23 \pipe2_xer_ca$44 - connect \xer_ca_ok \pipe2_xer_ca_ok - connect \xer_ca_ok$24 \pipe2_xer_ca_ok$45 - connect \xer_so \pipe2_xer_so - connect \xer_so_ok \pipe2_xer_so_ok - end - connect \muxid 2'00 - connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$45 \pipe2_xer_ca$44 } - connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$43 \pipe2_cr_a$42 } - connect { \o_ok \o } { \pipe2_o_ok$41 \pipe2_o$40 } - connect { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 \sr_op__invert_in$56 \sr_op__write_cr0$55 \sr_op__oe__ok$54 \sr_op__oe__oe$53 \sr_op__rc__ok$52 \sr_op__rc__rc$51 \sr_op__imm_data__ok$50 \sr_op__imm_data__data$49 \sr_op__fn_unit$48 \sr_op__insn_type$47 } { \pipe2_sr_op__insn$39 \pipe2_sr_op__is_signed$38 \pipe2_sr_op__is_32bit$37 \pipe2_sr_op__output_cr$36 \pipe2_sr_op__input_cr$35 \pipe2_sr_op__output_carry$34 \pipe2_sr_op__input_carry$33 \pipe2_sr_op__invert_in$32 \pipe2_sr_op__write_cr0$31 \pipe2_sr_op__oe__ok$30 \pipe2_sr_op__oe__oe$29 \pipe2_sr_op__rc__ok$28 \pipe2_sr_op__rc__rc$27 \pipe2_sr_op__imm_data__ok$26 \pipe2_sr_op__imm_data__data$25 \pipe2_sr_op__fn_unit$24 \pipe2_sr_op__insn_type$23 } - connect \muxid$46 \pipe2_muxid$22 - connect \pipe2_n_ready_i \n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \pipe1_xer_ca$21 \xer_ca$1 - connect \pipe1_xer_so$20 \xer_so - connect \pipe1_rc \rc - connect \pipe1_rb \rb - connect \pipe1_ra \ra - connect { \pipe1_sr_op__insn$19 \pipe1_sr_op__is_signed$18 \pipe1_sr_op__is_32bit$17 \pipe1_sr_op__output_cr$16 \pipe1_sr_op__input_cr$15 \pipe1_sr_op__output_carry$14 \pipe1_sr_op__input_carry$13 \pipe1_sr_op__invert_in$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \pipe1_muxid$2 2'00 - connect \p_ready_o \pipe1_p_ready_o - connect \pipe1_p_valid_i \p_valid_i - connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } - connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } - connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } - connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } - connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__invert_in \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__invert_in \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } - connect \pipe2_muxid \pipe1_muxid - connect \pipe1_n_ready_i \pipe2_p_ready_o - connect \pipe2_p_valid_i \pipe1_n_valid_o -end -attribute \src "libresoc.v:29703.1-30249.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" -attribute \generator "nMigen" -module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \fast1$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 6 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 9 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 8 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 27 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 26 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pipe_spr1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_spr1_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_spr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe_spr_op__fn_unit$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn$9 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \pipe_spr_op__is_32bit$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe_xer_ca$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \pipe_xer_ov$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \pipe_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_xer_so$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pipe_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 15 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 21 \spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 7 \spr1_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 11 \spr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \spr_op__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 10 \spr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \spr_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 19 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 25 \xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 18 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 24 \xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 23 \xer_so$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \xer_so_ok - attribute \module_not_derived 1 - attribute \src "libresoc.v:30184.10-30187.4" - cell \n$63 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:30188.10-30191.4" - cell \p$62 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:30192.13-30227.4" - cell \pipe$64 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \pipe_fast1 - connect \fast1$7 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \muxid \pipe_muxid - connect \muxid$1 \pipe_muxid$6 - connect \n_ready_i \pipe_n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \p_ready_o \pipe_p_ready_o - connect \p_valid_i \pipe_p_valid_i - connect \ra \pipe_ra - connect \spr1 \pipe_spr1 - connect \spr1$6 \pipe_spr1$11 - connect \spr1_ok \pipe_spr1_ok - connect \spr_op__fn_unit \pipe_spr_op__fn_unit - connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 - connect \spr_op__insn \pipe_spr_op__insn - connect \spr_op__insn$4 \pipe_spr_op__insn$9 - connect \spr_op__insn_type \pipe_spr_op__insn_type - connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 - connect \spr_op__is_32bit \pipe_spr_op__is_32bit - connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 - connect \xer_ca \pipe_xer_ca - connect \xer_ca$10 \pipe_xer_ca$15 - connect \xer_ca_ok \pipe_xer_ca_ok - connect \xer_ov \pipe_xer_ov - connect \xer_ov$9 \pipe_xer_ov$14 - connect \xer_ov_ok \pipe_xer_ov_ok - connect \xer_so \pipe_xer_so - connect \xer_so$8 \pipe_xer_so$13 - connect \xer_so_ok \pipe_xer_so_ok - end - connect \muxid 2'00 - connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } - connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } - connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } - connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } - connect { \o_ok \o } { \pipe_o_ok \pipe_o } - connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } - connect \muxid$16 \pipe_muxid$6 - connect \pipe_n_ready_i \n_ready_i - connect \n_valid_o \pipe_n_valid_o - connect \pipe_xer_ca \xer_ca$5 - connect \pipe_xer_ov \xer_ov$4 - connect \pipe_xer_so \xer_so$3 - connect \pipe_fast1 \fast1$2 - connect \pipe_spr1 \spr1$1 - connect \pipe_ra \ra - connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \pipe_muxid 2'00 - connect \p_ready_o \pipe_p_ready_o - connect \pipe_p_valid_i \p_valid_i -end -attribute \src "libresoc.v:30253.1-31108.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" -attribute \generator "nMigen" -module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 19 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 20 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 22 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 6 \msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 8 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 21 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 18 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 28 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 27 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_fast1$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_fast2$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_trap_op__cia$8 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_trap_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \pipe1_trap_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_trap_op__insn$6 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 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\enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 9 \trap_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 17 \trap_op__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 12 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 16 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 15 \trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$36 - attribute \module_not_derived 1 - attribute \src "libresoc.v:30996.10-30999.4" - cell \n$31 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:31000.10-31003.4" - cell \p$30 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:31004.14-31039.4" - cell \pipe1$32 \pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \pipe1_fast1 - connect \fast1$13 \pipe1_fast1$15 - connect \fast2 \pipe1_fast2 - connect \fast2$14 \pipe1_fast2$16 - connect \muxid \pipe1_muxid - connect \muxid$1 \pipe1_muxid$3 - connect \n_ready_i \pipe1_n_ready_i - connect \n_valid_o \pipe1_n_valid_o - connect \p_ready_o \pipe1_p_ready_o - connect \p_valid_i \pipe1_p_valid_i - connect \ra \pipe1_ra - connect \ra$11 \pipe1_ra$13 - connect \rb \pipe1_rb - connect \rb$12 \pipe1_rb$14 - connect \trap_op__cia \pipe1_trap_op__cia - connect \trap_op__cia$6 \pipe1_trap_op__cia$8 - connect \trap_op__fn_unit \pipe1_trap_op__fn_unit - connect \trap_op__fn_unit$3 \pipe1_trap_op__fn_unit$5 - connect \trap_op__insn \pipe1_trap_op__insn - connect \trap_op__insn$4 \pipe1_trap_op__insn$6 - connect \trap_op__insn_type \pipe1_trap_op__insn_type - connect \trap_op__insn_type$2 \pipe1_trap_op__insn_type$4 - connect \trap_op__is_32bit \pipe1_trap_op__is_32bit - connect \trap_op__is_32bit$7 \pipe1_trap_op__is_32bit$9 - connect \trap_op__ldst_exc \pipe1_trap_op__ldst_exc - connect \trap_op__ldst_exc$10 \pipe1_trap_op__ldst_exc$12 - connect \trap_op__msr \pipe1_trap_op__msr - connect \trap_op__msr$5 \pipe1_trap_op__msr$7 - connect \trap_op__trapaddr \pipe1_trap_op__trapaddr - connect \trap_op__trapaddr$9 \pipe1_trap_op__trapaddr$11 - connect \trap_op__traptype \pipe1_trap_op__traptype - connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:31040.14-31081.4" - cell \pipe2$35 \pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \pipe2_fast1 - connect \fast1$11 \pipe2_fast1$27 - connect \fast1_ok \pipe2_fast1_ok - connect \fast2 \pipe2_fast2 - connect \fast2$12 \pipe2_fast2$28 - connect \fast2_ok \pipe2_fast2_ok - connect \msr \pipe2_msr - connect \msr_ok \pipe2_msr_ok - connect \muxid \pipe2_muxid - connect \muxid$1 \pipe2_muxid$17 - connect \n_ready_i \pipe2_n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \nia \pipe2_nia - connect \nia_ok \pipe2_nia_ok - connect \o \pipe2_o - connect \o_ok \pipe2_o_ok - connect \p_ready_o \pipe2_p_ready_o - connect \p_valid_i \pipe2_p_valid_i - connect \ra \pipe2_ra - connect \rb \pipe2_rb - connect \trap_op__cia \pipe2_trap_op__cia - connect \trap_op__cia$6 \pipe2_trap_op__cia$22 - connect \trap_op__fn_unit \pipe2_trap_op__fn_unit - connect \trap_op__fn_unit$3 \pipe2_trap_op__fn_unit$19 - connect \trap_op__insn \pipe2_trap_op__insn - connect \trap_op__insn$4 \pipe2_trap_op__insn$20 - connect \trap_op__insn_type \pipe2_trap_op__insn_type - connect \trap_op__insn_type$2 \pipe2_trap_op__insn_type$18 - connect \trap_op__is_32bit \pipe2_trap_op__is_32bit - connect \trap_op__is_32bit$7 \pipe2_trap_op__is_32bit$23 - connect \trap_op__ldst_exc \pipe2_trap_op__ldst_exc - connect \trap_op__ldst_exc$10 \pipe2_trap_op__ldst_exc$26 - connect \trap_op__msr \pipe2_trap_op__msr - connect \trap_op__msr$5 \pipe2_trap_op__msr$21 - connect \trap_op__trapaddr \pipe2_trap_op__trapaddr - connect \trap_op__trapaddr$9 \pipe2_trap_op__trapaddr$25 - connect \trap_op__traptype \pipe2_trap_op__traptype - connect \trap_op__traptype$8 \pipe2_trap_op__traptype$24 - end - connect \muxid 2'00 - connect { \msr_ok \msr } { \pipe2_msr_ok \pipe2_msr } - connect { \nia_ok \nia } { \pipe2_nia_ok \pipe2_nia } - connect { \fast2_ok \fast2 } { \pipe2_fast2_ok \pipe2_fast2$28 } - connect { \fast1_ok \fast1 } { \pipe2_fast1_ok \pipe2_fast1$27 } - connect { \o_ok \o } { \pipe2_o_ok \pipe2_o } - connect { \trap_op__ldst_exc$38 \trap_op__trapaddr$37 \trap_op__traptype$36 \trap_op__is_32bit$35 \trap_op__cia$34 \trap_op__msr$33 \trap_op__insn$32 \trap_op__fn_unit$31 \trap_op__insn_type$30 } { \pipe2_trap_op__ldst_exc$26 \pipe2_trap_op__trapaddr$25 \pipe2_trap_op__traptype$24 \pipe2_trap_op__is_32bit$23 \pipe2_trap_op__cia$22 \pipe2_trap_op__msr$21 \pipe2_trap_op__insn$20 \pipe2_trap_op__fn_unit$19 \pipe2_trap_op__insn_type$18 } - connect \muxid$29 \pipe2_muxid$17 - connect \pipe2_n_ready_i \n_ready_i - connect \n_valid_o \pipe2_n_valid_o - connect \pipe1_fast2$16 \fast2$2 - connect \pipe1_fast1$15 \fast1$1 - connect \pipe1_rb$14 \rb - connect \pipe1_ra$13 \ra - connect { \pipe1_trap_op__ldst_exc$12 \pipe1_trap_op__trapaddr$11 \pipe1_trap_op__traptype$10 \pipe1_trap_op__is_32bit$9 \pipe1_trap_op__cia$8 \pipe1_trap_op__msr$7 \pipe1_trap_op__insn$6 \pipe1_trap_op__fn_unit$5 \pipe1_trap_op__insn_type$4 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \pipe1_muxid$3 2'00 - connect \p_ready_o \pipe1_p_ready_o - connect \pipe1_p_valid_i \p_valid_i - connect \pipe2_fast2 \pipe1_fast2 - connect \pipe2_fast1 \pipe1_fast1 - connect \pipe2_rb \pipe1_rb - connect \pipe2_ra \pipe1_ra - connect { \pipe2_trap_op__ldst_exc \pipe2_trap_op__trapaddr \pipe2_trap_op__traptype \pipe2_trap_op__is_32bit \pipe2_trap_op__cia \pipe2_trap_op__msr \pipe2_trap_op__insn \pipe2_trap_op__fn_unit \pipe2_trap_op__insn_type } { \pipe1_trap_op__ldst_exc \pipe1_trap_op__trapaddr \pipe1_trap_op__traptype \pipe1_trap_op__is_32bit \pipe1_trap_op__cia \pipe1_trap_op__msr \pipe1_trap_op__insn \pipe1_trap_op__fn_unit \pipe1_trap_op__insn_type } - connect \pipe2_muxid \pipe1_muxid - connect \pipe1_n_ready_i \pipe2_p_ready_o - connect \pipe2_p_valid_i \pipe1_n_valid_o -end -attribute \src "libresoc.v:31112.1-31170.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" -attribute \generator "nMigen" -module \alui_l - attribute \src "libresoc.v:31113.7-31113.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31158.3-31166.6" - wire $0\q_int$next[0:0]$992 - attribute \src "libresoc.v:31156.3-31157.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31158.3-31166.6" - wire $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31137.7-31137.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31148.17-31148.96" - wire $and$libresoc.v:31148$982_Y - attribute \src "libresoc.v:31153.17-31153.96" - wire $and$libresoc.v:31153$987_Y - attribute \src "libresoc.v:31150.18-31150.94" - wire $not$libresoc.v:31150$984_Y - attribute \src "libresoc.v:31152.17-31152.93" - wire $not$libresoc.v:31152$986_Y - attribute \src "libresoc.v:31155.17-31155.93" - wire $not$libresoc.v:31155$989_Y - attribute \src "libresoc.v:31149.18-31149.99" - wire $or$libresoc.v:31149$983_Y - attribute \src "libresoc.v:31151.18-31151.100" - wire $or$libresoc.v:31151$985_Y - attribute \src "libresoc.v:31154.17-31154.98" - wire $or$libresoc.v:31154$988_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31113.7-31113.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31148$982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31148$982_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31153$987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31153$987_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31150$984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31150$984_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31152$986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31152$986_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31155$989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31155$989_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31149$983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31149$983_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31151$985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31151$985_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31154$988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31154$988_Y - end - attribute \src "libresoc.v:31113.7-31113.20" - process $proc$libresoc.v:31113$994 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31137.7-31137.19" - process $proc$libresoc.v:31137$995 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31156.3-31157.27" - process $proc$libresoc.v:31156$990 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31158.3-31166.6" - process $proc$libresoc.v:31158$991 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31159.5-31159.29" - switch \initial - attribute \src "libresoc.v:31159.9-31159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$993 1'0 - case - assign $1\q_int$next[0:0]$993 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$992 - end - connect \$9 $and$libresoc.v:31148$982_Y - connect \$11 $or$libresoc.v:31149$983_Y - connect \$13 $not$libresoc.v:31150$984_Y - connect \$15 $or$libresoc.v:31151$985_Y - connect \$1 $not$libresoc.v:31152$986_Y - connect \$3 $and$libresoc.v:31153$987_Y - connect \$5 $or$libresoc.v:31154$988_Y - connect \$7 $not$libresoc.v:31155$989_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31174.1-31232.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" -attribute \generator "nMigen" -module \alui_l$106 - attribute \src "libresoc.v:31175.7-31175.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31220.3-31228.6" - wire $0\q_int$next[0:0]$1006 - attribute \src "libresoc.v:31218.3-31219.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31220.3-31228.6" - wire $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31199.7-31199.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31210.17-31210.96" - wire $and$libresoc.v:31210$996_Y - attribute \src "libresoc.v:31215.17-31215.96" - wire $and$libresoc.v:31215$1001_Y - attribute \src "libresoc.v:31212.18-31212.94" - wire $not$libresoc.v:31212$998_Y - attribute \src "libresoc.v:31214.17-31214.93" - wire $not$libresoc.v:31214$1000_Y - attribute \src "libresoc.v:31217.17-31217.93" - wire $not$libresoc.v:31217$1003_Y - attribute \src "libresoc.v:31211.18-31211.99" - wire $or$libresoc.v:31211$997_Y - attribute \src "libresoc.v:31213.18-31213.100" - wire $or$libresoc.v:31213$999_Y - attribute \src "libresoc.v:31216.17-31216.98" - wire $or$libresoc.v:31216$1002_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31175.7-31175.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31210$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31210$996_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31215$1001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31215$1001_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31212$998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31212$998_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31214$1000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31214$1000_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31217$1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31217$1003_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31211$997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31211$997_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31213$999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31213$999_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31216$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31216$1002_Y - end - attribute \src "libresoc.v:31175.7-31175.20" - process $proc$libresoc.v:31175$1008 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31199.7-31199.19" - process $proc$libresoc.v:31199$1009 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31218.3-31219.27" - process $proc$libresoc.v:31218$1004 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31220.3-31228.6" - process $proc$libresoc.v:31220$1005 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31221.5-31221.29" - switch \initial - attribute \src "libresoc.v:31221.9-31221.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1007 1'0 - case - assign $1\q_int$next[0:0]$1007 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1006 - end - connect \$9 $and$libresoc.v:31210$996_Y - connect \$11 $or$libresoc.v:31211$997_Y - connect \$13 $not$libresoc.v:31212$998_Y - connect \$15 $or$libresoc.v:31213$999_Y - connect \$1 $not$libresoc.v:31214$1000_Y - connect \$3 $and$libresoc.v:31215$1001_Y - connect \$5 $or$libresoc.v:31216$1002_Y - connect \$7 $not$libresoc.v:31217$1003_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31236.1-31294.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" -attribute \generator "nMigen" -module \alui_l$124 - attribute \src "libresoc.v:31237.7-31237.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31282.3-31290.6" - wire $0\q_int$next[0:0]$1020 - attribute \src "libresoc.v:31280.3-31281.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31282.3-31290.6" - wire $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31261.7-31261.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31272.17-31272.96" - wire $and$libresoc.v:31272$1010_Y - attribute \src "libresoc.v:31277.17-31277.96" - wire $and$libresoc.v:31277$1015_Y - attribute \src "libresoc.v:31274.18-31274.94" - wire $not$libresoc.v:31274$1012_Y - attribute \src "libresoc.v:31276.17-31276.93" - wire $not$libresoc.v:31276$1014_Y - attribute \src "libresoc.v:31279.17-31279.93" - wire $not$libresoc.v:31279$1017_Y - attribute \src "libresoc.v:31273.18-31273.99" - wire $or$libresoc.v:31273$1011_Y - attribute \src "libresoc.v:31275.18-31275.100" - wire $or$libresoc.v:31275$1013_Y - attribute \src "libresoc.v:31278.17-31278.98" - wire $or$libresoc.v:31278$1016_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31237.7-31237.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31272$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31272$1010_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31277$1015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31277$1015_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31274$1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31274$1012_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31276$1014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31276$1014_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31279$1017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31279$1017_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31273$1011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31273$1011_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31275$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31275$1013_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31278$1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31278$1016_Y - end - attribute \src "libresoc.v:31237.7-31237.20" - process $proc$libresoc.v:31237$1022 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31261.7-31261.19" - process $proc$libresoc.v:31261$1023 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31280.3-31281.27" - process $proc$libresoc.v:31280$1018 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31282.3-31290.6" - process $proc$libresoc.v:31282$1019 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31283.5-31283.29" - switch \initial - attribute \src "libresoc.v:31283.9-31283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1021 1'0 - case - assign $1\q_int$next[0:0]$1021 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1020 - end - connect \$9 $and$libresoc.v:31272$1010_Y - connect \$11 $or$libresoc.v:31273$1011_Y - connect \$13 $not$libresoc.v:31274$1012_Y - connect \$15 $or$libresoc.v:31275$1013_Y - connect \$1 $not$libresoc.v:31276$1014_Y - connect \$3 $and$libresoc.v:31277$1015_Y - connect \$5 $or$libresoc.v:31278$1016_Y - connect \$7 $not$libresoc.v:31279$1017_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31298.1-31356.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" -attribute \generator "nMigen" -module \alui_l$15 - attribute \src "libresoc.v:31299.7-31299.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31344.3-31352.6" - wire $0\q_int$next[0:0]$1034 - attribute \src "libresoc.v:31342.3-31343.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31344.3-31352.6" - wire $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31323.7-31323.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31334.17-31334.96" - wire $and$libresoc.v:31334$1024_Y - attribute \src "libresoc.v:31339.17-31339.96" - wire $and$libresoc.v:31339$1029_Y - attribute \src "libresoc.v:31336.18-31336.94" - wire $not$libresoc.v:31336$1026_Y - attribute \src "libresoc.v:31338.17-31338.93" - wire $not$libresoc.v:31338$1028_Y - attribute \src "libresoc.v:31341.17-31341.93" - wire $not$libresoc.v:31341$1031_Y - attribute \src "libresoc.v:31335.18-31335.99" - wire $or$libresoc.v:31335$1025_Y - attribute \src "libresoc.v:31337.18-31337.100" - wire $or$libresoc.v:31337$1027_Y - attribute \src "libresoc.v:31340.17-31340.98" - wire $or$libresoc.v:31340$1030_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31299.7-31299.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31334$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31334$1024_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31339$1029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31339$1029_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31336$1026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31336$1026_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31338$1028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31338$1028_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31341$1031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31341$1031_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31335$1025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31335$1025_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31337$1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31337$1027_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31340$1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31340$1030_Y - end - attribute \src "libresoc.v:31299.7-31299.20" - process $proc$libresoc.v:31299$1036 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31323.7-31323.19" - process $proc$libresoc.v:31323$1037 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31342.3-31343.27" - process $proc$libresoc.v:31342$1032 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31344.3-31352.6" - process $proc$libresoc.v:31344$1033 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31345.5-31345.29" - switch \initial - attribute \src "libresoc.v:31345.9-31345.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1035 1'0 - case - assign $1\q_int$next[0:0]$1035 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1034 - end - connect \$9 $and$libresoc.v:31334$1024_Y - connect \$11 $or$libresoc.v:31335$1025_Y - connect \$13 $not$libresoc.v:31336$1026_Y - connect \$15 $or$libresoc.v:31337$1027_Y - connect \$1 $not$libresoc.v:31338$1028_Y - connect \$3 $and$libresoc.v:31339$1029_Y - connect \$5 $or$libresoc.v:31340$1030_Y - connect \$7 $not$libresoc.v:31341$1031_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31360.1-31418.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" -attribute \generator "nMigen" -module \alui_l$28 - attribute \src "libresoc.v:31361.7-31361.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31406.3-31414.6" - wire $0\q_int$next[0:0]$1048 - attribute \src "libresoc.v:31404.3-31405.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31406.3-31414.6" - wire $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31385.7-31385.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31396.17-31396.96" - wire $and$libresoc.v:31396$1038_Y - attribute \src "libresoc.v:31401.17-31401.96" - wire $and$libresoc.v:31401$1043_Y - attribute \src "libresoc.v:31398.18-31398.94" - wire $not$libresoc.v:31398$1040_Y - attribute \src "libresoc.v:31400.17-31400.93" - wire $not$libresoc.v:31400$1042_Y - attribute \src "libresoc.v:31403.17-31403.93" - wire $not$libresoc.v:31403$1045_Y - attribute \src "libresoc.v:31397.18-31397.99" - wire $or$libresoc.v:31397$1039_Y - attribute \src "libresoc.v:31399.18-31399.100" - wire $or$libresoc.v:31399$1041_Y - attribute \src "libresoc.v:31402.17-31402.98" - wire $or$libresoc.v:31402$1044_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31361.7-31361.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31396$1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31396$1038_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31401$1043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31401$1043_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31398$1040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31398$1040_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31400$1042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31400$1042_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31403$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31403$1045_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31397$1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31397$1039_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31399$1041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31399$1041_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31402$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31402$1044_Y - end - attribute \src "libresoc.v:31361.7-31361.20" - process $proc$libresoc.v:31361$1050 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31385.7-31385.19" - process $proc$libresoc.v:31385$1051 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31404.3-31405.27" - process $proc$libresoc.v:31404$1046 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31406.3-31414.6" - process $proc$libresoc.v:31406$1047 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31407.5-31407.29" - switch \initial - attribute \src "libresoc.v:31407.9-31407.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1049 1'0 - case - assign $1\q_int$next[0:0]$1049 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1048 - end - connect \$9 $and$libresoc.v:31396$1038_Y - connect \$11 $or$libresoc.v:31397$1039_Y - connect \$13 $not$libresoc.v:31398$1040_Y - connect \$15 $or$libresoc.v:31399$1041_Y - connect \$1 $not$libresoc.v:31400$1042_Y - connect \$3 $and$libresoc.v:31401$1043_Y - connect \$5 $or$libresoc.v:31402$1044_Y - connect \$7 $not$libresoc.v:31403$1045_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31422.1-31480.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" -attribute \generator "nMigen" -module \alui_l$44 - attribute \src "libresoc.v:31423.7-31423.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31468.3-31476.6" - wire $0\q_int$next[0:0]$1062 - attribute \src "libresoc.v:31466.3-31467.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31468.3-31476.6" - wire $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31447.7-31447.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31458.17-31458.96" - wire $and$libresoc.v:31458$1052_Y - attribute \src "libresoc.v:31463.17-31463.96" - wire $and$libresoc.v:31463$1057_Y - attribute \src "libresoc.v:31460.18-31460.94" - wire $not$libresoc.v:31460$1054_Y - attribute \src "libresoc.v:31462.17-31462.93" - wire $not$libresoc.v:31462$1056_Y - attribute \src "libresoc.v:31465.17-31465.93" - wire $not$libresoc.v:31465$1059_Y - attribute \src "libresoc.v:31459.18-31459.99" - wire $or$libresoc.v:31459$1053_Y - attribute \src "libresoc.v:31461.18-31461.100" - wire $or$libresoc.v:31461$1055_Y - attribute \src "libresoc.v:31464.17-31464.98" - wire $or$libresoc.v:31464$1058_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31423.7-31423.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31458$1052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31458$1052_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31463$1057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31463$1057_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31460$1054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31460$1054_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31462$1056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31462$1056_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31465$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31465$1059_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31459$1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31459$1053_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31461$1055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31461$1055_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31464$1058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31464$1058_Y - end - attribute \src "libresoc.v:31423.7-31423.20" - process $proc$libresoc.v:31423$1064 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31447.7-31447.19" - process $proc$libresoc.v:31447$1065 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31466.3-31467.27" - process $proc$libresoc.v:31466$1060 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31468.3-31476.6" - process $proc$libresoc.v:31468$1061 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31469.5-31469.29" - switch \initial - attribute \src "libresoc.v:31469.9-31469.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1063 1'0 - case - assign $1\q_int$next[0:0]$1063 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1062 - end - connect \$9 $and$libresoc.v:31458$1052_Y - connect \$11 $or$libresoc.v:31459$1053_Y - connect \$13 $not$libresoc.v:31460$1054_Y - connect \$15 $or$libresoc.v:31461$1055_Y - connect \$1 $not$libresoc.v:31462$1056_Y - connect \$3 $and$libresoc.v:31463$1057_Y - connect \$5 $or$libresoc.v:31464$1058_Y - connect \$7 $not$libresoc.v:31465$1059_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31484.1-31542.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" -attribute \generator "nMigen" -module \alui_l$60 - attribute \src "libresoc.v:31485.7-31485.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31530.3-31538.6" - wire $0\q_int$next[0:0]$1076 - attribute \src "libresoc.v:31528.3-31529.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31530.3-31538.6" - wire $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31509.7-31509.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31520.17-31520.96" - wire $and$libresoc.v:31520$1066_Y - attribute \src "libresoc.v:31525.17-31525.96" - wire $and$libresoc.v:31525$1071_Y - attribute \src "libresoc.v:31522.18-31522.94" - wire $not$libresoc.v:31522$1068_Y - attribute \src "libresoc.v:31524.17-31524.93" - wire $not$libresoc.v:31524$1070_Y - attribute \src "libresoc.v:31527.17-31527.93" - wire $not$libresoc.v:31527$1073_Y - attribute \src "libresoc.v:31521.18-31521.99" - wire $or$libresoc.v:31521$1067_Y - attribute \src "libresoc.v:31523.18-31523.100" - wire $or$libresoc.v:31523$1069_Y - attribute \src "libresoc.v:31526.17-31526.98" - wire $or$libresoc.v:31526$1072_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31485.7-31485.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31520$1066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31520$1066_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31525$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31525$1071_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31522$1068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31522$1068_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31524$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31524$1070_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31527$1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31527$1073_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31521$1067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31521$1067_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31523$1069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31523$1069_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31526$1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31526$1072_Y - end - attribute \src "libresoc.v:31485.7-31485.20" - process $proc$libresoc.v:31485$1078 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31509.7-31509.19" - process $proc$libresoc.v:31509$1079 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31528.3-31529.27" - process $proc$libresoc.v:31528$1074 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31530.3-31538.6" - process $proc$libresoc.v:31530$1075 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31531.5-31531.29" - switch \initial - attribute \src "libresoc.v:31531.9-31531.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1077 1'0 - case - assign $1\q_int$next[0:0]$1077 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1076 - end - connect \$9 $and$libresoc.v:31520$1066_Y - connect \$11 $or$libresoc.v:31521$1067_Y - connect \$13 $not$libresoc.v:31522$1068_Y - connect \$15 $or$libresoc.v:31523$1069_Y - connect \$1 $not$libresoc.v:31524$1070_Y - connect \$3 $and$libresoc.v:31525$1071_Y - connect \$5 $or$libresoc.v:31526$1072_Y - connect \$7 $not$libresoc.v:31527$1073_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31546.1-31604.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" -attribute \generator "nMigen" -module \alui_l$72 - attribute \src "libresoc.v:31547.7-31547.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31592.3-31600.6" - wire $0\q_int$next[0:0]$1090 - attribute \src "libresoc.v:31590.3-31591.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31592.3-31600.6" - wire $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:31571.7-31571.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31582.17-31582.96" - wire $and$libresoc.v:31582$1080_Y - attribute \src "libresoc.v:31587.17-31587.96" - wire $and$libresoc.v:31587$1085_Y - attribute \src "libresoc.v:31584.18-31584.94" - wire $not$libresoc.v:31584$1082_Y - attribute \src "libresoc.v:31586.17-31586.93" - wire $not$libresoc.v:31586$1084_Y - attribute \src "libresoc.v:31589.17-31589.93" - wire $not$libresoc.v:31589$1087_Y - attribute \src "libresoc.v:31583.18-31583.99" - wire $or$libresoc.v:31583$1081_Y - attribute \src "libresoc.v:31585.18-31585.100" - wire $or$libresoc.v:31585$1083_Y - attribute \src "libresoc.v:31588.17-31588.98" - wire $or$libresoc.v:31588$1086_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:31547.7-31547.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:31582$1080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:31582$1080_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:31587$1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:31587$1085_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:31584$1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $not$libresoc.v:31584$1082_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:31586$1084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31586$1084_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:31589$1087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $not$libresoc.v:31589$1087_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:31583$1081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_alui - connect \Y $or$libresoc.v:31583$1081_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:31585$1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $or$libresoc.v:31585$1083_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:31588$1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_alui - connect \Y $or$libresoc.v:31588$1086_Y - end - attribute \src "libresoc.v:31547.7-31547.20" - process $proc$libresoc.v:31547$1092 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31571.7-31571.19" - process $proc$libresoc.v:31571$1093 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:31590.3-31591.27" - process $proc$libresoc.v:31590$1088 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:31592.3-31600.6" - process $proc$libresoc.v:31592$1089 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:31593.5-31593.29" - switch \initial - attribute \src "libresoc.v:31593.9-31593.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1091 1'0 - case - assign $1\q_int$next[0:0]$1091 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1090 - end - connect \$9 $and$libresoc.v:31582$1080_Y - connect \$11 $or$libresoc.v:31583$1081_Y - connect \$13 $not$libresoc.v:31584$1082_Y - connect \$15 $or$libresoc.v:31585$1083_Y - connect \$1 $not$libresoc.v:31586$1084_Y - connect \$3 $and$libresoc.v:31587$1085_Y - connect \$5 $or$libresoc.v:31588$1086_Y - connect \$7 $not$libresoc.v:31589$1087_Y - connect \qlq_alui \$15 - connect \qn_alui \$13 - connect \q_alui \$11 -end -attribute \src "libresoc.v:31608.1-31666.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" -attribute \generator "nMigen" -module \alui_l$89 - attribute \src "libresoc.v:31609.7-31609.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:31654.3-31662.6" - wire $0\q_int$next[0:0]$1104 - attribute \src "libresoc.v:31652.3-31653.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:31654.3-31662.6" - wire $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:31633.7-31633.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:31644.17-31644.96" - wire $and$libresoc.v:31644$1094_Y - attribute \src "libresoc.v:31649.17-31649.96" - wire $and$libresoc.v:31649$1099_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire \rb64_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" - wire width 64 input 3 \rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31840$1108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_4 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31840$1108_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31841$1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_5 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31841$1109_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31842$1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_6 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31842$1110_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31843$1111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_7 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31843$1111_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31844$1112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_0 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31844$1112_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31845$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_1 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31845$1113_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31846$1114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_2 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31846$1114_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:31847$1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_3 - connect \B 7'1000000 - connect \Y $lt$libresoc.v:31847$1115_Y - end - attribute \src "libresoc.v:31671.7-31671.20" - process $proc$libresoc.v:31671$1117 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:31848.3-32939.6" - process $proc$libresoc.v:31848$1116 - assign { } { } - assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 - assign $0\perm[63:0] [0] $1\perm[0:0] - assign $0\perm[63:0] [1] $3\perm[1:1] - assign $0\perm[63:0] [2] $5\perm[2:2] - assign $0\perm[63:0] [3] $7\perm[3:3] - assign $0\perm[63:0] [4] $9\perm[4:4] - assign $0\perm[63:0] [5] $11\perm[5:5] - assign $0\perm[63:0] [6] $13\perm[6:6] - assign $0\perm[63:0] [7] $15\perm[7:7] - attribute \src "libresoc.v:31849.5-31849.29" - switch \initial - attribute \src "libresoc.v:31849.9-31849.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\perm[0:0] $2\perm[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $2\perm[0:0] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $2\perm[0:0] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $2\perm[0:0] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $2\perm[0:0] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $2\perm[0:0] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $2\perm[0:0] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $2\perm[0:0] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $2\perm[0:0] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $2\perm[0:0] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $2\perm[0:0] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $2\perm[0:0] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $2\perm[0:0] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $2\perm[0:0] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $2\perm[0:0] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $2\perm[0:0] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $2\perm[0:0] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $2\perm[0:0] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $2\perm[0:0] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $2\perm[0:0] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $2\perm[0:0] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $2\perm[0:0] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $2\perm[0:0] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $2\perm[0:0] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $2\perm[0:0] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $2\perm[0:0] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $2\perm[0:0] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $2\perm[0:0] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $2\perm[0:0] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $2\perm[0:0] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $2\perm[0:0] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $2\perm[0:0] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $2\perm[0:0] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $2\perm[0:0] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $2\perm[0:0] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $2\perm[0:0] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $2\perm[0:0] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $2\perm[0:0] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $2\perm[0:0] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $2\perm[0:0] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $2\perm[0:0] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $2\perm[0:0] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $2\perm[0:0] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $2\perm[0:0] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $2\perm[0:0] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $2\perm[0:0] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $2\perm[0:0] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $2\perm[0:0] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $2\perm[0:0] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $2\perm[0:0] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $2\perm[0:0] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $2\perm[0:0] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $2\perm[0:0] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $2\perm[0:0] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $2\perm[0:0] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $2\perm[0:0] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $2\perm[0:0] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $2\perm[0:0] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $2\perm[0:0] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $2\perm[0:0] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $2\perm[0:0] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $2\perm[0:0] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $2\perm[0:0] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $2\perm[0:0] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $2\perm[0:0] \rb64_63 - case - assign $2\perm[0:0] 1'0 - end - case - assign $1\perm[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\perm[1:1] $4\perm[1:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $4\perm[1:1] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $4\perm[1:1] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $4\perm[1:1] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $4\perm[1:1] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $4\perm[1:1] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $4\perm[1:1] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $4\perm[1:1] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $4\perm[1:1] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $4\perm[1:1] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $4\perm[1:1] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $4\perm[1:1] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $4\perm[1:1] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $4\perm[1:1] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $4\perm[1:1] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $4\perm[1:1] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $4\perm[1:1] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $4\perm[1:1] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $4\perm[1:1] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $4\perm[1:1] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $4\perm[1:1] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $4\perm[1:1] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $4\perm[1:1] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $4\perm[1:1] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $4\perm[1:1] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $4\perm[1:1] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $4\perm[1:1] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $4\perm[1:1] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $4\perm[1:1] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $4\perm[1:1] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $4\perm[1:1] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $4\perm[1:1] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $4\perm[1:1] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $4\perm[1:1] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $4\perm[1:1] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $4\perm[1:1] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $4\perm[1:1] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $4\perm[1:1] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $4\perm[1:1] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $4\perm[1:1] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $4\perm[1:1] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $4\perm[1:1] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $4\perm[1:1] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $4\perm[1:1] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $4\perm[1:1] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $4\perm[1:1] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $4\perm[1:1] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $4\perm[1:1] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $4\perm[1:1] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $4\perm[1:1] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $4\perm[1:1] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $4\perm[1:1] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $4\perm[1:1] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $4\perm[1:1] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $4\perm[1:1] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $4\perm[1:1] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $4\perm[1:1] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $4\perm[1:1] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $4\perm[1:1] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $4\perm[1:1] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $4\perm[1:1] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $4\perm[1:1] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $4\perm[1:1] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $4\perm[1:1] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $4\perm[1:1] \rb64_63 - case - assign $4\perm[1:1] 1'0 - end - case - assign $3\perm[1:1] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\perm[2:2] $6\perm[2:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $6\perm[2:2] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $6\perm[2:2] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $6\perm[2:2] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $6\perm[2:2] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $6\perm[2:2] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $6\perm[2:2] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $6\perm[2:2] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $6\perm[2:2] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $6\perm[2:2] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $6\perm[2:2] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $6\perm[2:2] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $6\perm[2:2] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $6\perm[2:2] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $6\perm[2:2] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $6\perm[2:2] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $6\perm[2:2] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $6\perm[2:2] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $6\perm[2:2] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $6\perm[2:2] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $6\perm[2:2] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $6\perm[2:2] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $6\perm[2:2] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $6\perm[2:2] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $6\perm[2:2] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $6\perm[2:2] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $6\perm[2:2] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $6\perm[2:2] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $6\perm[2:2] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $6\perm[2:2] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $6\perm[2:2] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $6\perm[2:2] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $6\perm[2:2] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $6\perm[2:2] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $6\perm[2:2] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $6\perm[2:2] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $6\perm[2:2] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $6\perm[2:2] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $6\perm[2:2] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $6\perm[2:2] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $6\perm[2:2] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $6\perm[2:2] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $6\perm[2:2] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $6\perm[2:2] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $6\perm[2:2] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $6\perm[2:2] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $6\perm[2:2] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $6\perm[2:2] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $6\perm[2:2] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $6\perm[2:2] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $6\perm[2:2] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $6\perm[2:2] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $6\perm[2:2] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $6\perm[2:2] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $6\perm[2:2] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $6\perm[2:2] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $6\perm[2:2] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $6\perm[2:2] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $6\perm[2:2] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $6\perm[2:2] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $6\perm[2:2] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $6\perm[2:2] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $6\perm[2:2] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $6\perm[2:2] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $6\perm[2:2] \rb64_63 - case - assign $6\perm[2:2] 1'0 - end - case - assign $5\perm[2:2] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\perm[3:3] $8\perm[3:3] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $8\perm[3:3] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $8\perm[3:3] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $8\perm[3:3] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $8\perm[3:3] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $8\perm[3:3] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $8\perm[3:3] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $8\perm[3:3] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $8\perm[3:3] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $8\perm[3:3] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $8\perm[3:3] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $8\perm[3:3] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $8\perm[3:3] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $8\perm[3:3] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $8\perm[3:3] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $8\perm[3:3] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $8\perm[3:3] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $8\perm[3:3] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $8\perm[3:3] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $8\perm[3:3] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $8\perm[3:3] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $8\perm[3:3] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $8\perm[3:3] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $8\perm[3:3] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $8\perm[3:3] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $8\perm[3:3] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $8\perm[3:3] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $8\perm[3:3] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $8\perm[3:3] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $8\perm[3:3] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $8\perm[3:3] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $8\perm[3:3] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $8\perm[3:3] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $8\perm[3:3] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $8\perm[3:3] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $8\perm[3:3] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $8\perm[3:3] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $8\perm[3:3] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $8\perm[3:3] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $8\perm[3:3] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $8\perm[3:3] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $8\perm[3:3] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $8\perm[3:3] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $8\perm[3:3] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $8\perm[3:3] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $8\perm[3:3] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $8\perm[3:3] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $8\perm[3:3] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $8\perm[3:3] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $8\perm[3:3] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $8\perm[3:3] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $8\perm[3:3] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $8\perm[3:3] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $8\perm[3:3] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $8\perm[3:3] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $8\perm[3:3] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $8\perm[3:3] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $8\perm[3:3] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $8\perm[3:3] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $8\perm[3:3] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $8\perm[3:3] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $8\perm[3:3] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $8\perm[3:3] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $8\perm[3:3] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $8\perm[3:3] \rb64_63 - case - assign $8\perm[3:3] 1'0 - end - case - assign $7\perm[3:3] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\perm[4:4] $10\perm[4:4] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $10\perm[4:4] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $10\perm[4:4] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $10\perm[4:4] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $10\perm[4:4] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $10\perm[4:4] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $10\perm[4:4] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $10\perm[4:4] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $10\perm[4:4] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $10\perm[4:4] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $10\perm[4:4] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $10\perm[4:4] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $10\perm[4:4] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $10\perm[4:4] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $10\perm[4:4] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $10\perm[4:4] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $10\perm[4:4] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $10\perm[4:4] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $10\perm[4:4] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $10\perm[4:4] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $10\perm[4:4] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $10\perm[4:4] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $10\perm[4:4] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $10\perm[4:4] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $10\perm[4:4] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $10\perm[4:4] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $10\perm[4:4] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $10\perm[4:4] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $10\perm[4:4] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $10\perm[4:4] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $10\perm[4:4] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $10\perm[4:4] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $10\perm[4:4] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $10\perm[4:4] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $10\perm[4:4] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $10\perm[4:4] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $10\perm[4:4] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $10\perm[4:4] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $10\perm[4:4] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $10\perm[4:4] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $10\perm[4:4] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $10\perm[4:4] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $10\perm[4:4] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $10\perm[4:4] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $10\perm[4:4] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $10\perm[4:4] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $10\perm[4:4] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $10\perm[4:4] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $10\perm[4:4] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $10\perm[4:4] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $10\perm[4:4] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $10\perm[4:4] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $10\perm[4:4] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $10\perm[4:4] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $10\perm[4:4] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $10\perm[4:4] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $10\perm[4:4] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $10\perm[4:4] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $10\perm[4:4] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $10\perm[4:4] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $10\perm[4:4] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $10\perm[4:4] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $10\perm[4:4] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $10\perm[4:4] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $10\perm[4:4] \rb64_63 - case - assign $10\perm[4:4] 1'0 - end - case - assign $9\perm[4:4] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\perm[5:5] $12\perm[5:5] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $12\perm[5:5] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $12\perm[5:5] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $12\perm[5:5] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $12\perm[5:5] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $12\perm[5:5] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $12\perm[5:5] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $12\perm[5:5] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $12\perm[5:5] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $12\perm[5:5] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $12\perm[5:5] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $12\perm[5:5] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $12\perm[5:5] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $12\perm[5:5] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $12\perm[5:5] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $12\perm[5:5] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $12\perm[5:5] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $12\perm[5:5] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $12\perm[5:5] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $12\perm[5:5] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $12\perm[5:5] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $12\perm[5:5] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $12\perm[5:5] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $12\perm[5:5] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $12\perm[5:5] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $12\perm[5:5] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $12\perm[5:5] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $12\perm[5:5] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $12\perm[5:5] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $12\perm[5:5] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $12\perm[5:5] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $12\perm[5:5] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $12\perm[5:5] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $12\perm[5:5] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $12\perm[5:5] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $12\perm[5:5] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $12\perm[5:5] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $12\perm[5:5] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $12\perm[5:5] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $12\perm[5:5] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $12\perm[5:5] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $12\perm[5:5] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $12\perm[5:5] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $12\perm[5:5] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $12\perm[5:5] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $12\perm[5:5] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $12\perm[5:5] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $12\perm[5:5] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $12\perm[5:5] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $12\perm[5:5] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $12\perm[5:5] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $12\perm[5:5] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $12\perm[5:5] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $12\perm[5:5] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $12\perm[5:5] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $12\perm[5:5] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $12\perm[5:5] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $12\perm[5:5] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $12\perm[5:5] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $12\perm[5:5] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $12\perm[5:5] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $12\perm[5:5] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $12\perm[5:5] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $12\perm[5:5] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $12\perm[5:5] \rb64_63 - case - assign $12\perm[5:5] 1'0 - end - case - assign $11\perm[5:5] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\perm[6:6] $14\perm[6:6] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $14\perm[6:6] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $14\perm[6:6] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $14\perm[6:6] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $14\perm[6:6] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $14\perm[6:6] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $14\perm[6:6] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $14\perm[6:6] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $14\perm[6:6] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $14\perm[6:6] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $14\perm[6:6] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $14\perm[6:6] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $14\perm[6:6] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $14\perm[6:6] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $14\perm[6:6] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $14\perm[6:6] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $14\perm[6:6] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $14\perm[6:6] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $14\perm[6:6] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $14\perm[6:6] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $14\perm[6:6] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $14\perm[6:6] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $14\perm[6:6] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $14\perm[6:6] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $14\perm[6:6] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $14\perm[6:6] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $14\perm[6:6] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $14\perm[6:6] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $14\perm[6:6] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $14\perm[6:6] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $14\perm[6:6] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $14\perm[6:6] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $14\perm[6:6] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $14\perm[6:6] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $14\perm[6:6] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $14\perm[6:6] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $14\perm[6:6] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $14\perm[6:6] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $14\perm[6:6] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $14\perm[6:6] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $14\perm[6:6] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $14\perm[6:6] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $14\perm[6:6] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $14\perm[6:6] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $14\perm[6:6] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $14\perm[6:6] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $14\perm[6:6] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $14\perm[6:6] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $14\perm[6:6] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $14\perm[6:6] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $14\perm[6:6] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $14\perm[6:6] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $14\perm[6:6] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $14\perm[6:6] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $14\perm[6:6] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $14\perm[6:6] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $14\perm[6:6] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $14\perm[6:6] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $14\perm[6:6] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $14\perm[6:6] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $14\perm[6:6] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $14\perm[6:6] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $14\perm[6:6] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $14\perm[6:6] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $14\perm[6:6] \rb64_63 - case - assign $14\perm[6:6] 1'0 - end - case - assign $13\perm[6:6] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\perm[7:7] $16\perm[7:7] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000000 - assign { } { } - assign $16\perm[7:7] \rb64_0 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000001 - assign { } { } - assign $16\perm[7:7] \rb64_1 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000010 - assign { } { } - assign $16\perm[7:7] \rb64_2 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000011 - assign { } { } - assign $16\perm[7:7] \rb64_3 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000100 - assign { } { } - assign $16\perm[7:7] \rb64_4 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000101 - assign { } { } - assign $16\perm[7:7] \rb64_5 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000110 - assign { } { } - assign $16\perm[7:7] \rb64_6 - attribute \src "libresoc.v:0.0-0.0" - case 8'00000111 - assign { } { } - assign $16\perm[7:7] \rb64_7 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001000 - assign { } { } - assign $16\perm[7:7] \rb64_8 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001001 - assign { } { } - assign $16\perm[7:7] \rb64_9 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001010 - assign { } { } - assign $16\perm[7:7] \rb64_10 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001011 - assign { } { } - assign $16\perm[7:7] \rb64_11 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001100 - assign { } { } - assign $16\perm[7:7] \rb64_12 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001101 - assign { } { } - assign $16\perm[7:7] \rb64_13 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001110 - assign { } { } - assign $16\perm[7:7] \rb64_14 - attribute \src "libresoc.v:0.0-0.0" - case 8'00001111 - assign { } { } - assign $16\perm[7:7] \rb64_15 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010000 - assign { } { } - assign $16\perm[7:7] \rb64_16 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010001 - assign { } { } - assign $16\perm[7:7] \rb64_17 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010010 - assign { } { } - assign $16\perm[7:7] \rb64_18 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010011 - assign { } { } - assign $16\perm[7:7] \rb64_19 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010100 - assign { } { } - assign $16\perm[7:7] \rb64_20 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010101 - assign { } { } - assign $16\perm[7:7] \rb64_21 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010110 - assign { } { } - assign $16\perm[7:7] \rb64_22 - attribute \src "libresoc.v:0.0-0.0" - case 8'00010111 - assign { } { } - assign $16\perm[7:7] \rb64_23 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011000 - assign { } { } - assign $16\perm[7:7] \rb64_24 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011001 - assign { } { } - assign $16\perm[7:7] \rb64_25 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011010 - assign { } { } - assign $16\perm[7:7] \rb64_26 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011011 - assign { } { } - assign $16\perm[7:7] \rb64_27 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011100 - assign { } { } - assign $16\perm[7:7] \rb64_28 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011101 - assign { } { } - assign $16\perm[7:7] \rb64_29 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011110 - assign { } { } - assign $16\perm[7:7] \rb64_30 - attribute \src "libresoc.v:0.0-0.0" - case 8'00011111 - assign { } { } - assign $16\perm[7:7] \rb64_31 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100000 - assign { } { } - assign $16\perm[7:7] \rb64_32 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100001 - assign { } { } - assign $16\perm[7:7] \rb64_33 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100010 - assign { } { } - assign $16\perm[7:7] \rb64_34 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100011 - assign { } { } - assign $16\perm[7:7] \rb64_35 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100100 - assign { } { } - assign $16\perm[7:7] \rb64_36 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100101 - assign { } { } - assign $16\perm[7:7] \rb64_37 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100110 - assign { } { } - assign $16\perm[7:7] \rb64_38 - attribute \src "libresoc.v:0.0-0.0" - case 8'00100111 - assign { } { } - assign $16\perm[7:7] \rb64_39 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101000 - assign { } { } - assign $16\perm[7:7] \rb64_40 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101001 - assign { } { } - assign $16\perm[7:7] \rb64_41 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101010 - assign { } { } - assign $16\perm[7:7] \rb64_42 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101011 - assign { } { } - assign $16\perm[7:7] \rb64_43 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101100 - assign { } { } - assign $16\perm[7:7] \rb64_44 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101101 - assign { } { } - assign $16\perm[7:7] \rb64_45 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101110 - assign { } { } - assign $16\perm[7:7] \rb64_46 - attribute \src "libresoc.v:0.0-0.0" - case 8'00101111 - assign { } { } - assign $16\perm[7:7] \rb64_47 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110000 - assign { } { } - assign $16\perm[7:7] \rb64_48 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110001 - assign { } { } - assign $16\perm[7:7] \rb64_49 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110010 - assign { } { } - assign $16\perm[7:7] \rb64_50 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110011 - assign { } { } - assign $16\perm[7:7] \rb64_51 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110100 - assign { } { } - assign $16\perm[7:7] \rb64_52 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110101 - assign { } { } - assign $16\perm[7:7] \rb64_53 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110110 - assign { } { } - assign $16\perm[7:7] \rb64_54 - attribute \src "libresoc.v:0.0-0.0" - case 8'00110111 - assign { } { } - assign $16\perm[7:7] \rb64_55 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111000 - assign { } { } - assign $16\perm[7:7] \rb64_56 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111001 - assign { } { } - assign $16\perm[7:7] \rb64_57 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111010 - assign { } { } - assign $16\perm[7:7] \rb64_58 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111011 - assign { } { } - assign $16\perm[7:7] \rb64_59 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111100 - assign { } { } - assign $16\perm[7:7] \rb64_60 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111101 - assign { } { } - assign $16\perm[7:7] \rb64_61 - attribute \src "libresoc.v:0.0-0.0" - case 8'00111110 - assign { } { } - assign $16\perm[7:7] \rb64_62 - attribute \src "libresoc.v:0.0-0.0" - case 8'-------- - assign { } { } - assign $16\perm[7:7] \rb64_63 - case - assign $16\perm[7:7] 1'0 - end - case - assign $15\perm[7:7] 1'0 - end - sync always - update \perm $0\perm[63:0] - end - connect \$9 $lt$libresoc.v:31840$1108_Y - connect \$11 $lt$libresoc.v:31841$1109_Y - connect \$13 $lt$libresoc.v:31842$1110_Y - connect \$15 $lt$libresoc.v:31843$1111_Y - connect \$1 $lt$libresoc.v:31844$1112_Y - connect \$3 $lt$libresoc.v:31845$1113_Y - connect \$5 $lt$libresoc.v:31846$1114_Y - connect \$7 $lt$libresoc.v:31847$1115_Y - connect \ra [7:0] \perm [7:0] - connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 - connect \idx_7 \rs [63:56] - connect \idx_6 \rs [55:48] - connect \idx_5 \rs [47:40] - connect \idx_4 \rs [39:32] - connect \idx_3 \rs [31:24] - connect \idx_2 \rs [23:16] - connect \idx_1 \rs [15:8] - connect \idx_0 \rs [7:0] - connect \rb64_63 \rb [0] - connect \rb64_62 \rb [1] - connect \rb64_61 \rb [2] - connect \rb64_60 \rb [3] - connect \rb64_59 \rb [4] - connect \rb64_58 \rb [5] - connect \rb64_57 \rb [6] - connect \rb64_56 \rb [7] - connect \rb64_55 \rb [8] - connect \rb64_54 \rb [9] - connect \rb64_53 \rb [10] - connect \rb64_52 \rb [11] - connect \rb64_51 \rb [12] - connect \rb64_50 \rb [13] - connect \rb64_49 \rb [14] - connect \rb64_48 \rb [15] - connect \rb64_47 \rb [16] - connect \rb64_46 \rb [17] - connect \rb64_45 \rb [18] - connect \rb64_44 \rb [19] - connect \rb64_43 \rb [20] - connect \rb64_42 \rb [21] - connect \rb64_41 \rb [22] - connect \rb64_40 \rb [23] - connect \rb64_39 \rb [24] - connect \rb64_38 \rb [25] - connect \rb64_37 \rb [26] - connect \rb64_36 \rb [27] - connect \rb64_35 \rb [28] - connect \rb64_34 \rb [29] - connect \rb64_33 \rb [30] - connect \rb64_32 \rb [31] - connect \rb64_31 \rb [32] - connect \rb64_30 \rb [33] - connect \rb64_29 \rb [34] - connect \rb64_28 \rb [35] - connect \rb64_27 \rb [36] - connect \rb64_26 \rb [37] - connect \rb64_25 \rb [38] - connect \rb64_24 \rb [39] - connect \rb64_23 \rb [40] - connect \rb64_22 \rb [41] - connect \rb64_21 \rb [42] - connect \rb64_20 \rb [43] - connect \rb64_19 \rb [44] - connect \rb64_18 \rb [45] - connect \rb64_17 \rb [46] - connect \rb64_16 \rb [47] - connect \rb64_15 \rb [48] - connect \rb64_14 \rb [49] - connect \rb64_13 \rb [50] - connect \rb64_12 \rb [51] - connect \rb64_11 \rb [52] - connect \rb64_10 \rb [53] - connect \rb64_9 \rb [54] - connect \rb64_8 \rb [55] - connect \rb64_7 \rb [56] - connect \rb64_6 \rb [57] - connect \rb64_5 \rb [58] - connect \rb64_4 \rb [59] - connect \rb64_3 \rb [60] - connect \rb64_2 \rb [61] - connect \rb64_1 \rb [62] - connect \rb64_0 \rb [63] -end -attribute \src "libresoc.v:33018.1-34067.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" -attribute \generator "nMigen" -module \branch0 - attribute \src "libresoc.v:33684.3-33685.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 - attribute \src "libresoc.v:33644.3-33645.61" - wire width 64 $0\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 - attribute \src "libresoc.v:33648.3-33649.69" - wire width 12 $0\alu_branch0_br_op__fn_unit[11:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 - attribute \src "libresoc.v:33652.3-33653.83" - wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 - attribute \src "libresoc.v:33654.3-33655.79" - wire $0\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 - attribute \src "libresoc.v:33650.3-33651.63" - wire width 32 $0\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 - attribute \src "libresoc.v:33646.3-33647.73" - wire width 7 $0\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 - attribute \src "libresoc.v:33658.3-33659.71" - wire $0\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire $0\alu_branch0_br_op__lk$next[0:0]$1246 - attribute \src "libresoc.v:33656.3-33657.59" - wire $0\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33682.3-33683.43" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:33989.3-33997.6" - wire $0\alu_l_r_alu$next[0:0]$1294 - attribute \src "libresoc.v:33622.3-33623.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:33980.3-33988.6" - wire $0\alui_l_r_alui$next[0:0]$1291 - attribute \src "libresoc.v:33624.3-33625.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:33884.3-33905.6" - wire width 64 $0\data_r0__fast1$next[63:0]$1258 - attribute \src "libresoc.v:33640.3-33641.45" - wire width 64 $0\data_r0__fast1[63:0] - attribute \src "libresoc.v:33884.3-33905.6" - wire $0\data_r0__fast1_ok$next[0:0]$1259 - attribute \src "libresoc.v:33642.3-33643.51" - wire $0\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:33906.3-33927.6" - wire width 64 $0\data_r1__fast2$next[63:0]$1266 - attribute \src "libresoc.v:33636.3-33637.45" - wire width 64 $0\data_r1__fast2[63:0] - attribute \src "libresoc.v:33906.3-33927.6" - wire $0\data_r1__fast2_ok$next[0:0]$1267 - attribute \src "libresoc.v:33638.3-33639.51" - wire $0\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:33928.3-33949.6" - wire width 64 $0\data_r2__nia$next[63:0]$1274 - attribute \src "libresoc.v:33632.3-33633.41" - wire width 64 $0\data_r2__nia[63:0] - attribute \src "libresoc.v:33928.3-33949.6" - wire $0\data_r2__nia_ok$next[0:0]$1275 - attribute \src "libresoc.v:33634.3-33635.47" - wire $0\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:33998.3-34007.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:34008.3-34017.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:34018.3-34027.6" - wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:33019.7-33019.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:33814.3-33822.6" - wire $0\opc_l_r_opc$next[0:0]$1224 - attribute \src "libresoc.v:33668.3-33669.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:33805.3-33813.6" - wire $0\opc_l_s_opc$next[0:0]$1221 - attribute \src "libresoc.v:33670.3-33671.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34028.3-34036.6" - wire width 3 $0\prev_wr_go$next[2:0]$1300 - attribute \src "libresoc.v:33680.3-33681.37" - wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:33759.3-33768.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:33850.3-33858.6" - wire width 3 $0\req_l_r_req$next[2:0]$1236 - attribute \src "libresoc.v:33660.3-33661.39" - wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:33841.3-33849.6" - wire width 3 $0\req_l_s_req$next[2:0]$1233 - attribute \src "libresoc.v:33662.3-33663.39" - wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:33778.3-33786.6" - wire $0\rok_l_r_rdok$next[0:0]$1212 - attribute \src "libresoc.v:33676.3-33677.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:33769.3-33777.6" - wire $0\rok_l_s_rdok$next[0:0]$1209 - attribute \src "libresoc.v:33678.3-33679.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:33796.3-33804.6" - wire $0\rst_l_r_rst$next[0:0]$1218 - attribute \src "libresoc.v:33672.3-33673.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:33787.3-33795.6" - wire $0\rst_l_s_rst$next[0:0]$1215 - attribute \src "libresoc.v:33674.3-33675.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:33832.3-33840.6" - wire width 3 $0\src_l_r_src$next[2:0]$1230 - attribute \src "libresoc.v:33664.3-33665.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:33823.3-33831.6" - wire width 3 $0\src_l_s_src$next[2:0]$1227 - attribute \src "libresoc.v:33666.3-33667.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:33950.3-33959.6" - wire width 64 $0\src_r0$next[63:0]$1282 - attribute \src "libresoc.v:33630.3-33631.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:33960.3-33969.6" - wire width 64 $0\src_r1$next[63:0]$1285 - attribute \src "libresoc.v:33628.3-33629.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:33970.3-33979.6" - wire width 4 $0\src_r2$next[3:0]$1288 - attribute \src "libresoc.v:33626.3-33627.29" - wire width 4 $0\src_r2[3:0] - attribute \src "libresoc.v:33137.7-33137.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 - attribute \src "libresoc.v:33145.14-33145.59" - wire width 64 $1\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 - attribute \src "libresoc.v:33162.14-33162.50" - wire width 12 $1\alu_branch0_br_op__fn_unit[11:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - attribute \src "libresoc.v:33166.14-33166.70" - wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - attribute \src "libresoc.v:33170.7-33170.45" - wire $1\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 - attribute \src "libresoc.v:33174.14-33174.45" - wire width 32 $1\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 - attribute \src "libresoc.v:33252.13-33252.49" - wire width 7 $1\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 - attribute \src "libresoc.v:33256.7-33256.41" - wire $1\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire $1\alu_branch0_br_op__lk$next[0:0]$1254 - attribute \src "libresoc.v:33260.7-33260.35" - wire $1\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33286.7-33286.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:33989.3-33997.6" - wire $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:33294.7-33294.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:33980.3-33988.6" - wire $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:33306.7-33306.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:33884.3-33905.6" - wire width 64 $1\data_r0__fast1$next[63:0]$1260 - attribute \src "libresoc.v:33338.14-33338.51" - wire width 64 $1\data_r0__fast1[63:0] - attribute \src "libresoc.v:33884.3-33905.6" - wire $1\data_r0__fast1_ok$next[0:0]$1261 - attribute \src "libresoc.v:33342.7-33342.31" - wire $1\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:33906.3-33927.6" - wire width 64 $1\data_r1__fast2$next[63:0]$1268 - attribute \src "libresoc.v:33346.14-33346.51" - wire width 64 $1\data_r1__fast2[63:0] - attribute \src "libresoc.v:33906.3-33927.6" - wire $1\data_r1__fast2_ok$next[0:0]$1269 - attribute \src "libresoc.v:33350.7-33350.31" - wire $1\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:33928.3-33949.6" - wire width 64 $1\data_r2__nia$next[63:0]$1276 - attribute \src "libresoc.v:33354.14-33354.49" - wire width 64 $1\data_r2__nia[63:0] - attribute \src "libresoc.v:33928.3-33949.6" - wire $1\data_r2__nia_ok$next[0:0]$1277 - attribute \src "libresoc.v:33358.7-33358.29" - wire $1\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:33998.3-34007.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:34008.3-34017.6" - wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:34018.3-34027.6" - wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:33814.3-33822.6" - wire $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:33379.7-33379.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:33805.3-33813.6" - wire $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:33383.7-33383.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34028.3-34036.6" - wire width 3 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:33490.13-33490.30" - wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:33759.3-33768.6" - wire $1\req_done[0:0] - attribute \src "libresoc.v:33850.3-33858.6" - wire width 3 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:33498.13-33498.31" - wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:33841.3-33849.6" - wire width 3 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:33502.13-33502.31" - wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:33778.3-33786.6" - wire $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:33514.7-33514.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:33769.3-33777.6" - wire $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:33518.7-33518.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:33796.3-33804.6" - wire $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:33522.7-33522.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:33787.3-33795.6" - wire $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:33526.7-33526.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:33832.3-33840.6" - wire width 3 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:33540.13-33540.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:33823.3-33831.6" - wire width 3 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:33544.13-33544.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:33950.3-33959.6" - wire width 64 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:33550.14-33550.43" - wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:33960.3-33969.6" - wire width 64 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:33554.14-33554.43" - wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:33970.3-33979.6" - wire width 4 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:33558.13-33558.26" - wire width 4 $1\src_r2[3:0] - attribute \src "libresoc.v:33859.3-33883.6" - wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 - attribute \src "libresoc.v:33859.3-33883.6" - wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:33884.3-33905.6" - wire width 64 $2\data_r0__fast1$next[63:0]$1262 - attribute \src "libresoc.v:33884.3-33905.6" - wire $2\data_r0__fast1_ok$next[0:0]$1263 - attribute \src "libresoc.v:33906.3-33927.6" - wire width 64 $2\data_r1__fast2$next[63:0]$1270 - attribute \src "libresoc.v:33906.3-33927.6" - wire $2\data_r1__fast2_ok$next[0:0]$1271 - attribute \src "libresoc.v:33928.3-33949.6" - wire width 64 $2\data_r2__nia$next[63:0]$1278 - attribute \src "libresoc.v:33928.3-33949.6" - wire $2\data_r2__nia_ok$next[0:0]$1279 - attribute \src "libresoc.v:33884.3-33905.6" - wire $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:33906.3-33927.6" - wire $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:33928.3-33949.6" - wire $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:33566.18-33566.112" - wire width 3 $and$libresoc.v:33566$1119_Y - attribute \src "libresoc.v:33567.19-33567.125" - wire $and$libresoc.v:33567$1120_Y - attribute \src "libresoc.v:33568.19-33568.125" - wire $and$libresoc.v:33568$1121_Y - attribute \src "libresoc.v:33569.19-33569.125" - wire $and$libresoc.v:33569$1122_Y - attribute \src "libresoc.v:33570.19-33570.141" - wire width 3 $and$libresoc.v:33570$1123_Y - attribute \src "libresoc.v:33571.19-33571.121" - wire width 3 $and$libresoc.v:33571$1124_Y - attribute \src "libresoc.v:33572.19-33572.127" - wire $and$libresoc.v:33572$1125_Y - attribute \src "libresoc.v:33573.19-33573.127" - wire $and$libresoc.v:33573$1126_Y - attribute \src "libresoc.v:33574.19-33574.127" - wire $and$libresoc.v:33574$1127_Y - attribute \src "libresoc.v:33575.18-33575.110" - wire $and$libresoc.v:33575$1128_Y - attribute \src "libresoc.v:33577.18-33577.98" - wire $and$libresoc.v:33577$1130_Y - attribute \src "libresoc.v:33579.18-33579.100" - wire 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$and$libresoc.v:33594$1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$41 - connect \B \$45 - connect \Y $and$libresoc.v:33594$1147_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33596$1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \alu_branch0_n_ready_i - connect \Y $and$libresoc.v:33596$1149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33597$1150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \alu_branch0_n_valid_o - connect \Y $and$libresoc.v:33597$1150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:33598$1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \cu_busy_o - connect \Y $and$libresoc.v:33598$1151_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:33603$1156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$libresoc.v:33603$1156_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:33604$1157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:33604$1157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33607$1160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:33607$1160_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33608$1161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast2_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:33608$1161_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:33609$1162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \nia_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:33609$1162_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:33615$1168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:33615$1168_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:33617$1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:33617$1170_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:33618$1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - 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1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:33595$1148_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:33576$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$libresoc.v:33576$1129_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:33578$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$libresoc.v:33578$1131_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33581$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:33581$1134_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:33584$1137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:33584$1137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:33590$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_ready_i - connect \Y $not$libresoc.v:33590$1143_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:33605$1158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:33605$1158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:33619$1172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $not$libresoc.v:33619$1172_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:33621$1174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:33621$1174_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:33588$1141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$libresoc.v:33588$1141_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:33599$1152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33599$1152_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:33600$1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:33600$1153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:33601$1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33601$1154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:33602$1155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:33602$1155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:33606$1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:33606$1159_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:33616$1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:33616$1169_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:33565$1118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$libresoc.v:33565$1118_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:33583$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$libresoc.v:33583$1136_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33586$1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:33586$1139_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:33587$1140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:33587$1140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:33610$1163 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33610$1163_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:33611$1164 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_branch0_br_op__imm_data__data - connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:33611$1164_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33612$1165 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:33612$1165_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33613$1166 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:33613$1166_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:33614$1167 - parameter \WIDTH 4 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:33614$1167_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33686.15-33710.4" - cell \alu_branch0 \alu_branch0 - connect \br_op__cia \alu_branch0_br_op__cia - connect \br_op__fn_unit \alu_branch0_br_op__fn_unit - connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data - connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok - connect \br_op__insn \alu_branch0_br_op__insn - connect \br_op__insn_type \alu_branch0_br_op__insn_type - connect \br_op__is_32bit \alu_branch0_br_op__is_32bit - connect \br_op__lk \alu_branch0_br_op__lk - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_branch0_cr_a - connect \fast1 \alu_branch0_fast1 - connect \fast1$1 \alu_branch0_fast1$1 - connect \fast1_ok \fast1_ok - connect \fast2 \alu_branch0_fast2 - connect \fast2$2 \alu_branch0_fast2$2 - connect \fast2_ok \fast2_ok - connect \n_ready_i \alu_branch0_n_ready_i - connect \n_valid_o \alu_branch0_n_valid_o - connect \nia \alu_branch0_nia - connect \nia_ok \nia_ok - connect \p_ready_o \alu_branch0_p_ready_o - connect \p_valid_i \alu_branch0_p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33711.14-33717.4" - cell \alu_l$29 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33718.15-33724.4" - cell \alui_l$28 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33725.14-33731.4" - cell \opc_l$24 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33732.14-33738.4" - cell \req_l$25 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33739.14-33745.4" - cell \rok_l$27 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33746.14-33751.4" - cell \rst_l$26 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:33752.14-33758.4" - cell \src_l$23 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:33019.7-33019.20" - process $proc$libresoc.v:33019$1302 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:33137.7-33137.24" - process $proc$libresoc.v:33137$1303 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:33145.14-33145.59" - process $proc$libresoc.v:33145$1304 - assign { } { } - assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] - end - attribute \src "libresoc.v:33162.14-33162.50" - process $proc$libresoc.v:33162$1305 - assign { } { } - assign $1\alu_branch0_br_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[11:0] - end - attribute \src "libresoc.v:33166.14-33166.70" - process $proc$libresoc.v:33166$1306 - assign { } { } - assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:33170.7-33170.45" - process $proc$libresoc.v:33170$1307 - assign { } { } - assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:33174.14-33174.45" - process $proc$libresoc.v:33174$1308 - assign { } { } - assign $1\alu_branch0_br_op__insn[31:0] 0 - sync always - sync init - update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] - end - attribute \src "libresoc.v:33252.13-33252.49" - process $proc$libresoc.v:33252$1309 - assign { } { } - assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] - end - attribute \src "libresoc.v:33256.7-33256.41" - process $proc$libresoc.v:33256$1310 - assign { } { } - assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] - end - attribute \src "libresoc.v:33260.7-33260.35" - process $proc$libresoc.v:33260$1311 - assign { } { } - assign $1\alu_branch0_br_op__lk[0:0] 1'0 - sync always - sync init - update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] - end - attribute \src "libresoc.v:33286.7-33286.26" - process $proc$libresoc.v:33286$1312 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:33294.7-33294.25" - process $proc$libresoc.v:33294$1313 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:33306.7-33306.27" - process $proc$libresoc.v:33306$1314 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:33338.14-33338.51" - process $proc$libresoc.v:33338$1315 - assign { } { } - assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__fast1 $1\data_r0__fast1[63:0] - end - attribute \src "libresoc.v:33342.7-33342.31" - process $proc$libresoc.v:33342$1316 - assign { } { } - assign $1\data_r0__fast1_ok[0:0] 1'0 - sync always - sync init - update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] - end - attribute \src "libresoc.v:33346.14-33346.51" - process $proc$libresoc.v:33346$1317 - assign { } { } - assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r1__fast2 $1\data_r1__fast2[63:0] - end - attribute \src "libresoc.v:33350.7-33350.31" - process $proc$libresoc.v:33350$1318 - assign { } { } - assign $1\data_r1__fast2_ok[0:0] 1'0 - sync always - sync init - update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] - end - attribute \src "libresoc.v:33354.14-33354.49" - process $proc$libresoc.v:33354$1319 - assign { } { } - assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r2__nia $1\data_r2__nia[63:0] - end - attribute \src "libresoc.v:33358.7-33358.29" - process $proc$libresoc.v:33358$1320 - assign { } { } - assign $1\data_r2__nia_ok[0:0] 1'0 - sync always - sync init - update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] - end - attribute \src "libresoc.v:33379.7-33379.25" - process $proc$libresoc.v:33379$1321 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:33383.7-33383.25" - process $proc$libresoc.v:33383$1322 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:33490.13-33490.30" - process $proc$libresoc.v:33490$1323 - assign { } { } - assign $1\prev_wr_go[2:0] 3'000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[2:0] - end - attribute \src "libresoc.v:33498.13-33498.31" - process $proc$libresoc.v:33498$1324 - assign { } { } - assign $1\req_l_r_req[2:0] 3'111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[2:0] - end - attribute \src "libresoc.v:33502.13-33502.31" - process $proc$libresoc.v:33502$1325 - assign { } { } - assign $1\req_l_s_req[2:0] 3'000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[2:0] - end - attribute \src "libresoc.v:33514.7-33514.26" - process $proc$libresoc.v:33514$1326 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:33518.7-33518.26" - process $proc$libresoc.v:33518$1327 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:33522.7-33522.25" - process $proc$libresoc.v:33522$1328 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:33526.7-33526.25" - process $proc$libresoc.v:33526$1329 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:33540.13-33540.31" - process $proc$libresoc.v:33540$1330 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "libresoc.v:33544.13-33544.31" - process $proc$libresoc.v:33544$1331 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "libresoc.v:33550.14-33550.43" - process $proc$libresoc.v:33550$1332 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:33554.14-33554.43" - process $proc$libresoc.v:33554$1333 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:33558.13-33558.26" - process $proc$libresoc.v:33558$1334 - assign { } { } - assign $1\src_r2[3:0] 4'0000 - sync always - sync init - update \src_r2 $1\src_r2[3:0] - end - attribute \src "libresoc.v:33622.3-33623.39" - process $proc$libresoc.v:33622$1175 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:33624.3-33625.43" - process $proc$libresoc.v:33624$1176 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:33626.3-33627.29" - process $proc$libresoc.v:33626$1177 - assign { } { } - assign $0\src_r2[3:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[3:0] - end - attribute \src "libresoc.v:33628.3-33629.29" - process $proc$libresoc.v:33628$1178 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:33630.3-33631.29" - process $proc$libresoc.v:33630$1179 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:33632.3-33633.41" - process $proc$libresoc.v:33632$1180 - assign { } { } - assign $0\data_r2__nia[63:0] \data_r2__nia$next - sync posedge \coresync_clk - update \data_r2__nia $0\data_r2__nia[63:0] - end - attribute \src "libresoc.v:33634.3-33635.47" - process $proc$libresoc.v:33634$1181 - assign { } { } - assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next - sync posedge \coresync_clk - update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] - end - attribute \src "libresoc.v:33636.3-33637.45" - process $proc$libresoc.v:33636$1182 - assign { } { } - assign $0\data_r1__fast2[63:0] \data_r1__fast2$next - sync posedge \coresync_clk - update \data_r1__fast2 $0\data_r1__fast2[63:0] - end - attribute \src "libresoc.v:33638.3-33639.51" - process $proc$libresoc.v:33638$1183 - assign { } { } - assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next - sync posedge \coresync_clk - update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] - end - attribute \src "libresoc.v:33640.3-33641.45" - process $proc$libresoc.v:33640$1184 - assign { } { } - assign $0\data_r0__fast1[63:0] \data_r0__fast1$next - sync posedge \coresync_clk - update \data_r0__fast1 $0\data_r0__fast1[63:0] - end - attribute \src "libresoc.v:33642.3-33643.51" - process $proc$libresoc.v:33642$1185 - assign { } { } - assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next - sync posedge \coresync_clk - update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] - end - attribute \src "libresoc.v:33644.3-33645.61" - process $proc$libresoc.v:33644$1186 - assign { } { } - assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next - sync posedge \coresync_clk - update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] - end - attribute \src "libresoc.v:33646.3-33647.73" - process $proc$libresoc.v:33646$1187 - assign { } { } - assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next - sync posedge \coresync_clk - update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] - end - attribute \src "libresoc.v:33648.3-33649.69" - process $proc$libresoc.v:33648$1188 - assign { } { } - assign $0\alu_branch0_br_op__fn_unit[11:0] \alu_branch0_br_op__fn_unit$next - sync posedge \coresync_clk - update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[11:0] - end - attribute \src "libresoc.v:33650.3-33651.63" - process $proc$libresoc.v:33650$1189 - assign { } { } - assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next - sync posedge \coresync_clk - update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] - end - attribute \src "libresoc.v:33652.3-33653.83" - process $proc$libresoc.v:33652$1190 - assign { } { } - assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:33654.3-33655.79" - process $proc$libresoc.v:33654$1191 - assign { } { } - assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:33656.3-33657.59" - process $proc$libresoc.v:33656$1192 - assign { } { } - assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next - sync posedge \coresync_clk - update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] - end - attribute \src "libresoc.v:33658.3-33659.71" - process $proc$libresoc.v:33658$1193 - assign { } { } - assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next - sync posedge \coresync_clk - update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] - end - attribute \src "libresoc.v:33660.3-33661.39" - process $proc$libresoc.v:33660$1194 - assign { } { } - assign $0\req_l_r_req[2:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[2:0] - end - attribute \src "libresoc.v:33662.3-33663.39" - process $proc$libresoc.v:33662$1195 - assign { } { } - assign $0\req_l_s_req[2:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[2:0] - end - attribute \src "libresoc.v:33664.3-33665.39" - process $proc$libresoc.v:33664$1196 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "libresoc.v:33666.3-33667.39" - process $proc$libresoc.v:33666$1197 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "libresoc.v:33668.3-33669.39" - process $proc$libresoc.v:33668$1198 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:33670.3-33671.39" - process $proc$libresoc.v:33670$1199 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:33672.3-33673.39" - process $proc$libresoc.v:33672$1200 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:33674.3-33675.39" - process $proc$libresoc.v:33674$1201 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:33676.3-33677.41" - process $proc$libresoc.v:33676$1202 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:33678.3-33679.41" - process $proc$libresoc.v:33678$1203 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:33680.3-33681.37" - process $proc$libresoc.v:33680$1204 - assign { } { } - assign $0\prev_wr_go[2:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[2:0] - end - attribute \src "libresoc.v:33682.3-33683.43" - process $proc$libresoc.v:33682$1205 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:33684.3-33685.25" - process $proc$libresoc.v:33684$1206 - assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:33759.3-33768.6" - process $proc$libresoc.v:33759$1207 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:33760.5-33760.29" - switch \initial - attribute \src "libresoc.v:33760.9-33760.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:33769.3-33777.6" - process $proc$libresoc.v:33769$1208 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:33770.5-33770.29" - switch \initial - attribute \src "libresoc.v:33770.9-33770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$1210 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$1210 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 - end - attribute \src "libresoc.v:33778.3-33786.6" - process $proc$libresoc.v:33778$1211 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:33779.5-33779.29" - switch \initial - attribute \src "libresoc.v:33779.9-33779.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$1213 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$1213 \$65 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 - end - attribute \src "libresoc.v:33787.3-33795.6" - process $proc$libresoc.v:33787$1214 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:33788.5-33788.29" - switch \initial - attribute \src "libresoc.v:33788.9-33788.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$1216 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$1216 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 - end - attribute \src "libresoc.v:33796.3-33804.6" - process $proc$libresoc.v:33796$1217 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:33797.5-33797.29" - switch \initial - attribute \src "libresoc.v:33797.9-33797.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$1219 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$1219 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 - end - attribute \src "libresoc.v:33805.3-33813.6" - process $proc$libresoc.v:33805$1220 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:33806.5-33806.29" - switch \initial - attribute \src "libresoc.v:33806.9-33806.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$1222 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$1222 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 - end - attribute \src "libresoc.v:33814.3-33822.6" - process $proc$libresoc.v:33814$1223 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:33815.5-33815.29" - switch \initial - attribute \src "libresoc.v:33815.9-33815.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$1225 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$1225 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 - end - attribute \src "libresoc.v:33823.3-33831.6" - process $proc$libresoc.v:33823$1226 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:33824.5-33824.29" - switch \initial - attribute \src "libresoc.v:33824.9-33824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$1228 3'000 - case - assign $1\src_l_s_src$next[2:0]$1228 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 - end - attribute \src "libresoc.v:33832.3-33840.6" - process $proc$libresoc.v:33832$1229 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:33833.5-33833.29" - switch \initial - attribute \src "libresoc.v:33833.9-33833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$1231 3'111 - case - assign $1\src_l_r_src$next[2:0]$1231 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 - end - attribute \src "libresoc.v:33841.3-33849.6" - process $proc$libresoc.v:33841$1232 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:33842.5-33842.29" - switch \initial - attribute \src "libresoc.v:33842.9-33842.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[2:0]$1234 3'000 - case - assign $1\req_l_s_req$next[2:0]$1234 \$67 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 - end - attribute \src "libresoc.v:33850.3-33858.6" - process $proc$libresoc.v:33850$1235 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:33851.5-33851.29" - switch \initial - attribute \src "libresoc.v:33851.9-33851.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[2:0]$1237 3'111 - case - assign $1\req_l_r_req$next[2:0]$1237 \$69 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 - end - attribute \src "libresoc.v:33859.3-33883.6" - process $proc$libresoc.v:33859$1238 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 - assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 - assign { } { } - assign { } { } - assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 - assign $0\alu_branch0_br_op__insn_type$next[6:0]$1244 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 - assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 - assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 - assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 - assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:33860.5-33860.29" - switch \initial - attribute \src "libresoc.v:33860.9-33860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } - case - assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia - assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1248 \alu_branch0_br_op__fn_unit - assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data - assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok - assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn - assign $1\alu_branch0_br_op__insn_type$next[6:0]$1252 \alu_branch0_br_op__insn_type - assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 \alu_branch0_br_op__is_32bit - assign $1\alu_branch0_br_op__lk$next[0:0]$1254 \alu_branch0_br_op__lk - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 1'0 - case - assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - end - sync always - update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 - update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1240 - update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 - update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 - update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 - update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1244 - update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 - update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 - end - attribute \src "libresoc.v:33884.3-33905.6" - process $proc$libresoc.v:33884$1257 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 - assign { } { } - assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:33885.5-33885.29" - switch \initial - attribute \src "libresoc.v:33885.9-33885.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__fast1_ok$next[0:0]$1261 $1\data_r0__fast1$next[63:0]$1260 } { \fast1_ok \alu_branch0_fast1 } - case - assign $1\data_r0__fast1$next[63:0]$1260 \data_r0__fast1 - assign $1\data_r0__fast1_ok$next[0:0]$1261 \data_r0__fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__fast1_ok$next[0:0]$1263 $2\data_r0__fast1$next[63:0]$1262 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__fast1$next[63:0]$1262 $1\data_r0__fast1$next[63:0]$1260 - assign $2\data_r0__fast1_ok$next[0:0]$1263 $1\data_r0__fast1_ok$next[0:0]$1261 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__fast1_ok$next[0:0]$1264 1'0 - case - assign $3\data_r0__fast1_ok$next[0:0]$1264 $2\data_r0__fast1_ok$next[0:0]$1263 - end - sync always - update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 - update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 - end - attribute \src "libresoc.v:33906.3-33927.6" - process $proc$libresoc.v:33906$1265 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 - assign { } { } - assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:33907.5-33907.29" - switch \initial - attribute \src "libresoc.v:33907.9-33907.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__fast2_ok$next[0:0]$1269 $1\data_r1__fast2$next[63:0]$1268 } { \fast2_ok \alu_branch0_fast2 } - case - assign $1\data_r1__fast2$next[63:0]$1268 \data_r1__fast2 - assign $1\data_r1__fast2_ok$next[0:0]$1269 \data_r1__fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__fast2_ok$next[0:0]$1271 $2\data_r1__fast2$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r1__fast2$next[63:0]$1270 $1\data_r1__fast2$next[63:0]$1268 - assign $2\data_r1__fast2_ok$next[0:0]$1271 $1\data_r1__fast2_ok$next[0:0]$1269 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__fast2_ok$next[0:0]$1272 1'0 - case - assign $3\data_r1__fast2_ok$next[0:0]$1272 $2\data_r1__fast2_ok$next[0:0]$1271 - end - sync always - update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 - update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 - end - attribute \src "libresoc.v:33928.3-33949.6" - process $proc$libresoc.v:33928$1273 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 - assign { } { } - assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:33929.5-33929.29" - switch \initial - attribute \src "libresoc.v:33929.9-33929.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__nia_ok$next[0:0]$1277 $1\data_r2__nia$next[63:0]$1276 } { \nia_ok \alu_branch0_nia } - case - assign $1\data_r2__nia$next[63:0]$1276 \data_r2__nia - assign $1\data_r2__nia_ok$next[0:0]$1277 \data_r2__nia_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__nia_ok$next[0:0]$1279 $2\data_r2__nia$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r2__nia$next[63:0]$1278 $1\data_r2__nia$next[63:0]$1276 - assign $2\data_r2__nia_ok$next[0:0]$1279 $1\data_r2__nia_ok$next[0:0]$1277 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__nia_ok$next[0:0]$1280 1'0 - case - assign $3\data_r2__nia_ok$next[0:0]$1280 $2\data_r2__nia_ok$next[0:0]$1279 - end - sync always - update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 - update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 - end - attribute \src "libresoc.v:33950.3-33959.6" - process $proc$libresoc.v:33950$1281 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:33951.5-33951.29" - switch \initial - attribute \src "libresoc.v:33951.9-33951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$1283 \src1_i - case - assign $1\src_r0$next[63:0]$1283 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$1282 - end - attribute \src "libresoc.v:33960.3-33969.6" - process $proc$libresoc.v:33960$1284 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:33961.5-33961.29" - switch \initial - attribute \src "libresoc.v:33961.9-33961.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$1286 \src_or_imm - case - assign $1\src_r1$next[63:0]$1286 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$1285 - end - attribute \src "libresoc.v:33970.3-33979.6" - process $proc$libresoc.v:33970$1287 - assign { } { } - assign { } { } - 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assign { } { } - assign $1\alui_l_r_alui$next[0:0]$1292 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$1292 \$87 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 - end - attribute \src "libresoc.v:33989.3-33997.6" - process $proc$libresoc.v:33989$1293 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:33990.5-33990.29" - switch \initial - attribute \src "libresoc.v:33990.9-33990.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$1295 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$1295 \$89 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 - end - attribute \src "libresoc.v:33998.3-34007.6" - process $proc$libresoc.v:33998$1296 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:33999.5-33999.29" - switch \initial - attribute \src "libresoc.v:33999.9-33999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$111 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__fast1 - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:34008.3-34017.6" - process $proc$libresoc.v:34008$1297 - assign { } { } - assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:34009.5-34009.29" - switch \initial - attribute \src "libresoc.v:34009.9-34009.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[63:0] \data_r1__fast2 - case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest2_o $0\dest2_o[63:0] - end - attribute \src "libresoc.v:34018.3-34027.6" - process $proc$libresoc.v:34018$1298 - assign { } { } - assign { } { } - assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:34019.5-34019.29" - switch \initial - attribute \src "libresoc.v:34019.9-34019.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[63:0] \data_r2__nia - case - assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest3_o $0\dest3_o[63:0] - end - attribute \src "libresoc.v:34028.3-34036.6" - process $proc$libresoc.v:34028$1299 - assign { } { } - assign { } { } - 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$and$libresoc.v:33597$1150_Y - connect \$55 $and$libresoc.v:33598$1151_Y - connect \$57 $or$libresoc.v:33599$1152_Y - connect \$59 $or$libresoc.v:33600$1153_Y - connect \$61 $or$libresoc.v:33601$1154_Y - connect \$63 $or$libresoc.v:33602$1155_Y - connect \$65 $and$libresoc.v:33603$1156_Y - connect \$67 $and$libresoc.v:33604$1157_Y - connect \$6 $not$libresoc.v:33605$1158_Y - connect \$69 $or$libresoc.v:33606$1159_Y - connect \$71 $and$libresoc.v:33607$1160_Y - connect \$73 $and$libresoc.v:33608$1161_Y - connect \$75 $and$libresoc.v:33609$1162_Y - connect \$77 $ternary$libresoc.v:33610$1163_Y - connect \$79 $ternary$libresoc.v:33611$1164_Y - connect \$81 $ternary$libresoc.v:33612$1165_Y - connect \$83 $ternary$libresoc.v:33613$1166_Y - connect \$85 $ternary$libresoc.v:33614$1167_Y - connect \$87 $and$libresoc.v:33615$1168_Y - connect \$8 $or$libresoc.v:33616$1169_Y - connect \$89 $and$libresoc.v:33617$1170_Y - connect \$91 $and$libresoc.v:33618$1171_Y - connect \$93 $not$libresoc.v:33619$1172_Y - connect \$95 $and$libresoc.v:33620$1173_Y - connect \$97 $not$libresoc.v:33621$1174_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$109 - connect \cu_rd__rel_o \$99 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_branch0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_branch0_p_valid_i \alui_l_q_alui - connect \alu_branch0_cr_a \$85 - connect \alu_branch0_fast2$2 \$83 - connect \alu_branch0_fast1$1 \$81 - connect \src_or_imm \$79 - connect \src_sel \$77 - connect \cu_wrmask_o { \$75 \$73 \$71 } - connect \reset_r \$63 - connect \reset_w \$61 - connect \rst_r \$59 - connect \reset \$57 - connect \wr_any \$37 - connect \cu_done_o \$31 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$19 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_branch0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$15 - connect \all_rd_dly$next \all_rd - connect \all_rd \$11 -end -attribute \src "libresoc.v:34071.1-34129.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" -attribute \generator "nMigen" -module \busy_l - attribute \src "libresoc.v:34072.7-34072.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:34117.3-34125.6" - wire $0\q_int$next[0:0]$1345 - attribute \src "libresoc.v:34115.3-34116.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:34117.3-34125.6" - wire $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34096.7-34096.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:34107.17-34107.96" - wire $and$libresoc.v:34107$1335_Y - attribute \src "libresoc.v:34112.17-34112.96" - wire $and$libresoc.v:34112$1340_Y - attribute \src "libresoc.v:34109.18-34109.94" - wire $not$libresoc.v:34109$1337_Y - attribute \src "libresoc.v:34111.17-34111.93" - wire $not$libresoc.v:34111$1339_Y - attribute \src "libresoc.v:34114.17-34114.93" - wire $not$libresoc.v:34114$1342_Y - attribute \src "libresoc.v:34108.18-34108.99" - wire $or$libresoc.v:34108$1336_Y - attribute \src "libresoc.v:34110.18-34110.100" - wire $or$libresoc.v:34110$1338_Y - attribute \src "libresoc.v:34113.17-34113.98" - wire $or$libresoc.v:34113$1341_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:34072.7-34072.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:34107$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:34107$1335_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:34112$1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:34112$1340_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:34109$1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \Y $not$libresoc.v:34109$1337_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:34111$1339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $not$libresoc.v:34111$1339_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:34114$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $not$libresoc.v:34114$1342_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:34108$1336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_busy - connect \Y $or$libresoc.v:34108$1336_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:34110$1338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \B \q_int - connect \Y $or$libresoc.v:34110$1338_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:34113$1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_busy - connect \Y $or$libresoc.v:34113$1341_Y - end - attribute \src "libresoc.v:34072.7-34072.20" - process $proc$libresoc.v:34072$1347 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:34096.7-34096.19" - process $proc$libresoc.v:34096$1348 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:34115.3-34116.27" - process $proc$libresoc.v:34115$1343 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:34117.3-34125.6" - process $proc$libresoc.v:34117$1344 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34118.5-34118.29" - switch \initial - attribute \src "libresoc.v:34118.9-34118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$1346 1'0 - case - assign $1\q_int$next[0:0]$1346 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$1345 - end - connect \$9 $and$libresoc.v:34107$1335_Y - connect \$11 $or$libresoc.v:34108$1336_Y - connect \$13 $not$libresoc.v:34109$1337_Y - connect \$15 $or$libresoc.v:34110$1338_Y - connect \$1 $not$libresoc.v:34111$1339_Y - connect \$3 $and$libresoc.v:34112$1340_Y - connect \$5 $or$libresoc.v:34113$1341_Y - connect \$7 $not$libresoc.v:34114$1342_Y - connect \qlq_busy \$15 - connect \qn_busy \$13 - connect \q_busy \$11 -end -attribute \src "libresoc.v:34133.1-34316.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.clksel" -attribute \generator "nMigen" -module \clksel - attribute \src "libresoc.v:34267.3-34286.6" - wire $0\clk1$next[0:0]$1378 - attribute \src "libresoc.v:34201.3-34202.25" - wire $0\clk1[0:0] - attribute \src "libresoc.v:34220.3-34234.6" - wire $0\clk2$next[0:0]$1366 - attribute \src "libresoc.v:34207.3-34208.25" - wire $0\clk2[0:0] - attribute \src "libresoc.v:34252.3-34266.6" - wire $0\clk3$next[0:0]$1374 - attribute \src "libresoc.v:34203.3-34204.25" - wire $0\clk3[0:0] - attribute \src "libresoc.v:34211.3-34219.6" - wire $0\clk4$next[0:0]$1363 - attribute \src "libresoc.v:34209.3-34210.25" - wire $0\clk4[0:0] - attribute \src "libresoc.v:34287.3-34309.6" - wire $0\core_clk_o[0:0] - attribute \src "libresoc.v:34235.3-34251.6" - wire width 2 $0\counter3$next[1:0]$1370 - attribute \src "libresoc.v:34205.3-34206.33" - wire width 2 $0\counter3[1:0] - attribute \src "libresoc.v:34134.7-34134.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:34267.3-34286.6" - wire $1\clk1$next[0:0]$1379 - attribute \src "libresoc.v:34156.7-34156.18" - wire $1\clk1[0:0] - attribute \src "libresoc.v:34220.3-34234.6" - wire $1\clk2$next[0:0]$1367 - attribute \src "libresoc.v:34160.7-34160.18" - wire $1\clk2[0:0] - attribute \src "libresoc.v:34252.3-34266.6" - wire $1\clk3$next[0:0]$1375 - attribute \src "libresoc.v:34164.7-34164.18" - wire $1\clk3[0:0] - attribute \src "libresoc.v:34211.3-34219.6" - wire $1\clk4$next[0:0]$1364 - attribute \src "libresoc.v:34168.7-34168.18" - wire $1\clk4[0:0] - attribute \src "libresoc.v:34287.3-34309.6" - wire $1\core_clk_o[0:0] - attribute \src "libresoc.v:34235.3-34251.6" - wire width 2 $1\counter3$next[1:0]$1371 - attribute \src "libresoc.v:34184.13-34184.28" - wire width 2 $1\counter3[1:0] - attribute \src "libresoc.v:34267.3-34286.6" - wire $2\clk1$next[0:0]$1380 - attribute \src "libresoc.v:34220.3-34234.6" - wire $2\clk2$next[0:0]$1368 - attribute \src "libresoc.v:34252.3-34266.6" - wire $2\clk3$next[0:0]$1376 - attribute \src "libresoc.v:34235.3-34251.6" - wire width 2 $2\counter3$next[1:0]$1372 - attribute \src "libresoc.v:34267.3-34286.6" - wire $3\clk1$next[0:0]$1381 - attribute \src "libresoc.v:34200.17-34200.101" - wire width 3 $add$libresoc.v:34200$1356_Y - attribute \src "libresoc.v:34193.18-34193.103" - wire $eq$libresoc.v:34193$1349_Y - attribute \src "libresoc.v:34195.18-34195.103" - wire $eq$libresoc.v:34195$1351_Y - attribute \src "libresoc.v:34199.17-34199.102" - wire $eq$libresoc.v:34199$1355_Y - attribute \src "libresoc.v:34194.18-34194.93" - wire $not$libresoc.v:34194$1350_Y - attribute \src "libresoc.v:34196.18-34196.93" - wire $not$libresoc.v:34196$1352_Y - attribute \src "libresoc.v:34197.17-34197.92" - wire $not$libresoc.v:34197$1353_Y - attribute \src "libresoc.v:34198.17-34198.92" - wire $not$libresoc.v:34198$1354_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - wire \$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" - wire width 3 \$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:44" - wire \clk7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" - wire input 1 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" - wire width 3 input 3 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:37" - wire \core_clk_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:45" - wire width 2 \counter3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:45" - wire width 2 \counter3$next - attribute \src "libresoc.v:34134.7-34134.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" - wire output 4 \pll_48_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" - wire input 5 \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" - wire input 2 \pllclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:62" - cell $add $add$libresoc.v:34200$1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \counter3 - connect \B 1'1 - connect \Y $add$libresoc.v:34200$1356_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - cell $eq $eq$libresoc.v:34193$1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \counter3 - connect \B 2'10 - connect \Y $eq$libresoc.v:34193$1349_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - cell $eq $eq$libresoc.v:34195$1351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \counter3 - connect \B 2'10 - connect \Y $eq$libresoc.v:34195$1351_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - cell $eq $eq$libresoc.v:34199$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \counter3 - connect \B 2'10 - connect \Y $eq$libresoc.v:34199$1355_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:58" - cell $not $not$libresoc.v:34194$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk3 - connect \Y $not$libresoc.v:34194$1350_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:60" - cell $not $not$libresoc.v:34196$1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk1 - connect \Y $not$libresoc.v:34196$1352_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:53" - cell $not $not$libresoc.v:34197$1353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk4 - connect \Y $not$libresoc.v:34197$1353_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:55" - cell $not $not$libresoc.v:34198$1354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clk2 - connect \Y $not$libresoc.v:34198$1354_Y - end - attribute \src "libresoc.v:34134.7-34134.20" - process $proc$libresoc.v:34134$1383 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:34156.7-34156.18" - process $proc$libresoc.v:34156$1384 - assign { } { } - assign $1\clk1[0:0] 1'0 - sync always - sync init - update \clk1 $1\clk1[0:0] - end - attribute \src "libresoc.v:34160.7-34160.18" - process $proc$libresoc.v:34160$1385 - assign { } { } - assign $1\clk2[0:0] 1'0 - sync always - sync init - update \clk2 $1\clk2[0:0] - end - attribute \src "libresoc.v:34164.7-34164.18" - process $proc$libresoc.v:34164$1386 - assign { } { } - assign $1\clk3[0:0] 1'0 - sync always - sync init - update \clk3 $1\clk3[0:0] - end - attribute \src "libresoc.v:34168.7-34168.18" - process $proc$libresoc.v:34168$1387 - assign { } { } - assign $1\clk4[0:0] 1'0 - sync always - sync init - update \clk4 $1\clk4[0:0] - end - attribute \src "libresoc.v:34184.13-34184.28" - process $proc$libresoc.v:34184$1388 - assign { } { } - assign $1\counter3[1:0] 2'00 - sync always - sync init - update \counter3 $1\counter3[1:0] - end - attribute \src "libresoc.v:34201.3-34202.25" - process $proc$libresoc.v:34201$1357 - assign { } { } - assign $0\clk1[0:0] \clk1$next - sync posedge \pllclk_clk - update \clk1 $0\clk1[0:0] - end - attribute \src "libresoc.v:34203.3-34204.25" - process $proc$libresoc.v:34203$1358 - assign { } { } - assign $0\clk3[0:0] \clk3$next - sync posedge \pllclk_clk - update \clk3 $0\clk3[0:0] - end - attribute \src "libresoc.v:34205.3-34206.33" - process $proc$libresoc.v:34205$1359 - assign { } { } - assign $0\counter3[1:0] \counter3$next - sync posedge \pllclk_clk - update \counter3 $0\counter3[1:0] - end - attribute \src "libresoc.v:34207.3-34208.25" - process $proc$libresoc.v:34207$1360 - assign { } { } - assign $0\clk2[0:0] \clk2$next - sync posedge \pllclk_clk - update \clk2 $0\clk2[0:0] - end - attribute \src "libresoc.v:34209.3-34210.25" - process $proc$libresoc.v:34209$1361 - assign { } { } - assign $0\clk4[0:0] \clk4$next - sync posedge \pllclk_clk - update \clk4 $0\clk4[0:0] - end - attribute \src "libresoc.v:34211.3-34219.6" - process $proc$libresoc.v:34211$1362 - assign { } { } - assign { } { } - assign $0\clk4$next[0:0]$1363 $1\clk4$next[0:0]$1364 - attribute \src "libresoc.v:34212.5-34212.29" - switch \initial - attribute \src "libresoc.v:34212.9-34212.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk4$next[0:0]$1364 1'0 - case - assign $1\clk4$next[0:0]$1364 \$1 - end - sync always - update \clk4$next $0\clk4$next[0:0]$1363 - end - attribute \src "libresoc.v:34220.3-34234.6" - process $proc$libresoc.v:34220$1365 - assign { } { } - assign { } { } - assign { } { } - assign $0\clk2$next[0:0]$1366 $2\clk2$next[0:0]$1368 - attribute \src "libresoc.v:34221.5-34221.29" - switch \initial - attribute \src "libresoc.v:34221.9-34221.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:54" - switch \clk4 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk2$next[0:0]$1367 \$3 - case - assign $1\clk2$next[0:0]$1367 \clk2 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\clk2$next[0:0]$1368 1'0 - case - assign $2\clk2$next[0:0]$1368 $1\clk2$next[0:0]$1367 - end - sync always - update \clk2$next $0\clk2$next[0:0]$1366 - end - attribute \src "libresoc.v:34235.3-34251.6" - process $proc$libresoc.v:34235$1369 - assign { } { } - assign { } { } - assign $0\counter3$next[1:0]$1370 $2\counter3$next[1:0]$1372 - attribute \src "libresoc.v:34236.5-34236.29" - switch \initial - attribute \src "libresoc.v:34236.9-34236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\counter3$next[1:0]$1371 2'00 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\counter3$next[1:0]$1371 \$7 [1:0] - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\counter3$next[1:0]$1372 2'00 - case - assign $2\counter3$next[1:0]$1372 $1\counter3$next[1:0]$1371 - end - sync always - update \counter3$next $0\counter3$next[1:0]$1370 - end - attribute \src "libresoc.v:34252.3-34266.6" - process $proc$libresoc.v:34252$1373 - assign { } { } - assign { } { } - assign { } { } - assign $0\clk3$next[0:0]$1374 $2\clk3$next[0:0]$1376 - attribute \src "libresoc.v:34253.5-34253.29" - switch \initial - attribute \src "libresoc.v:34253.9-34253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - switch \$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk3$next[0:0]$1375 \$12 - case - assign $1\clk3$next[0:0]$1375 \clk3 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\clk3$next[0:0]$1376 1'0 - case - assign $2\clk3$next[0:0]$1376 $1\clk3$next[0:0]$1375 - end - sync always - update \clk3$next $0\clk3$next[0:0]$1374 - end - attribute \src "libresoc.v:34267.3-34286.6" - process $proc$libresoc.v:34267$1377 - assign { } { } - assign { } { } - assign { } { } - assign $0\clk1$next[0:0]$1378 $3\clk1$next[0:0]$1381 - attribute \src "libresoc.v:34268.5-34268.29" - switch \initial - attribute \src "libresoc.v:34268.9-34268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:56" - switch \$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\clk1$next[0:0]$1379 $2\clk1$next[0:0]$1380 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:59" - switch \clk3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\clk1$next[0:0]$1380 \$16 - case - assign $2\clk1$next[0:0]$1380 \clk1 - end - case - assign $1\clk1$next[0:0]$1379 \clk1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \pllclk_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\clk1$next[0:0]$1381 1'0 - case - assign $3\clk1$next[0:0]$1381 $1\clk1$next[0:0]$1379 - end - sync always - update \clk1$next $0\clk1$next[0:0]$1378 - end - attribute \src "libresoc.v:34287.3-34309.6" - process $proc$libresoc.v:34287$1382 - assign { } { } - assign { } { } - assign $0\core_clk_o[0:0] $1\core_clk_o[0:0] - attribute \src "libresoc.v:34288.5-34288.29" - switch \initial - attribute \src "libresoc.v:34288.9-34288.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:65" - switch \clk_sel_i - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\core_clk_o[0:0] \clk0 - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\core_clk_o[0:0] \clk1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\core_clk_o[0:0] \clk2 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\core_clk_o[0:0] \clk3 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\core_clk_o[0:0] \clk4 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\core_clk_o[0:0] \clk5 - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\core_clk_o[0:0] \clk6 - attribute \src "libresoc.v:0.0-0.0" - case 3'--- - assign { } { } - assign $1\core_clk_o[0:0] \clk7 - case - assign $1\core_clk_o[0:0] 1'0 - end - sync always - update \core_clk_o $0\core_clk_o[0:0] - end - connect \$10 $eq$libresoc.v:34193$1349_Y - connect \$12 $not$libresoc.v:34194$1350_Y - connect \$14 $eq$libresoc.v:34195$1351_Y - connect \$16 $not$libresoc.v:34196$1352_Y - connect \$1 $not$libresoc.v:34197$1353_Y - connect \$3 $not$libresoc.v:34198$1354_Y - connect \$5 $eq$libresoc.v:34199$1355_Y - connect \$8 $add$libresoc.v:34200$1356_Y - connect \$7 \$8 - connect \clk5 1'0 - connect \pll_48_o \clk1 - connect \clk7 1'1 - connect \clk6 1'0 - connect \clk0 \clk_24_i -end -attribute \src "libresoc.v:34320.1-35928.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" -attribute \generator "nMigen" -module \clz - attribute \src "libresoc.v:34795.3-34809.6" - wire width 2 $0\cnt_1_0[1:0] - attribute \src "libresoc.v:34885.3-34899.6" - wire width 2 $0\cnt_1_10[1:0] - attribute \src "libresoc.v:34900.3-34914.6" - wire width 2 $0\cnt_1_11[1:0] - attribute \src "libresoc.v:34915.3-34929.6" - wire width 2 $0\cnt_1_12[1:0] - attribute \src "libresoc.v:34930.3-34944.6" - wire width 2 $0\cnt_1_13[1:0] - attribute \src "libresoc.v:34945.3-34959.6" - wire width 2 $0\cnt_1_14[1:0] - attribute \src "libresoc.v:34975.3-34989.6" - wire width 2 $0\cnt_1_15[1:0] - attribute \src "libresoc.v:34990.3-35004.6" - wire width 2 $0\cnt_1_16[1:0] - attribute \src "libresoc.v:35005.3-35019.6" - wire width 2 $0\cnt_1_17[1:0] - attribute \src "libresoc.v:35020.3-35034.6" - wire width 2 $0\cnt_1_18[1:0] - attribute \src "libresoc.v:35035.3-35049.6" - wire width 2 $0\cnt_1_19[1:0] - attribute \src "libresoc.v:34960.3-34974.6" - wire width 2 $0\cnt_1_1[1:0] - attribute \src "libresoc.v:35050.3-35064.6" - wire width 2 $0\cnt_1_20[1:0] - attribute \src "libresoc.v:35065.3-35079.6" - wire width 2 $0\cnt_1_21[1:0] - attribute \src "libresoc.v:35080.3-35094.6" - wire width 2 $0\cnt_1_22[1:0] - attribute \src "libresoc.v:35095.3-35109.6" - wire width 2 $0\cnt_1_23[1:0] - attribute \src "libresoc.v:35110.3-35124.6" - wire width 2 $0\cnt_1_24[1:0] - attribute \src "libresoc.v:35140.3-35154.6" - wire width 2 $0\cnt_1_25[1:0] - attribute \src "libresoc.v:35155.3-35169.6" - wire width 2 $0\cnt_1_26[1:0] - attribute \src "libresoc.v:35170.3-35184.6" - wire width 2 $0\cnt_1_27[1:0] - attribute \src "libresoc.v:35185.3-35199.6" - wire width 2 $0\cnt_1_28[1:0] - attribute \src "libresoc.v:35200.3-35214.6" - wire width 2 $0\cnt_1_29[1:0] - attribute \src "libresoc.v:35125.3-35139.6" - wire width 2 $0\cnt_1_2[1:0] - attribute \src "libresoc.v:35215.3-35229.6" - wire width 2 $0\cnt_1_30[1:0] - attribute \src "libresoc.v:35230.3-35244.6" - wire width 2 $0\cnt_1_31[1:0] - attribute \src "libresoc.v:35365.3-35379.6" - wire width 2 $0\cnt_1_3[1:0] - attribute \src "libresoc.v:35780.3-35794.6" - wire width 2 $0\cnt_1_4[1:0] - attribute \src "libresoc.v:34810.3-34824.6" - wire width 2 $0\cnt_1_5[1:0] - attribute \src "libresoc.v:34825.3-34839.6" - wire width 2 $0\cnt_1_6[1:0] - attribute \src "libresoc.v:34840.3-34854.6" - wire width 2 $0\cnt_1_7[1:0] - attribute \src "libresoc.v:34855.3-34869.6" - wire width 2 $0\cnt_1_8[1:0] - attribute \src "libresoc.v:34870.3-34884.6" - wire width 2 $0\cnt_1_9[1:0] - attribute \src "libresoc.v:35245.3-35264.6" - wire width 3 $0\cnt_2_0[2:0] - attribute \src "libresoc.v:35345.3-35364.6" - wire width 3 $0\cnt_2_10[2:0] - attribute \src "libresoc.v:35380.3-35399.6" - wire width 3 $0\cnt_2_12[2:0] - attribute \src "libresoc.v:35400.3-35419.6" - wire width 3 $0\cnt_2_14[2:0] - attribute \src "libresoc.v:35420.3-35439.6" - wire width 3 $0\cnt_2_16[2:0] - attribute \src "libresoc.v:35440.3-35459.6" - wire width 3 $0\cnt_2_18[2:0] - attribute \src "libresoc.v:35460.3-35479.6" - wire width 3 $0\cnt_2_20[2:0] - attribute \src "libresoc.v:35480.3-35499.6" - wire width 3 $0\cnt_2_22[2:0] - attribute \src "libresoc.v:35500.3-35519.6" - wire width 3 $0\cnt_2_24[2:0] - attribute \src "libresoc.v:35520.3-35539.6" - wire width 3 $0\cnt_2_26[2:0] - attribute \src "libresoc.v:35540.3-35559.6" - wire width 3 $0\cnt_2_28[2:0] - attribute \src "libresoc.v:35265.3-35284.6" - wire width 3 $0\cnt_2_2[2:0] - attribute \src "libresoc.v:35560.3-35579.6" - wire width 3 $0\cnt_2_30[2:0] - attribute \src "libresoc.v:35285.3-35304.6" - wire width 3 $0\cnt_2_4[2:0] - attribute \src "libresoc.v:35305.3-35324.6" - wire width 3 $0\cnt_2_6[2:0] - attribute \src "libresoc.v:35325.3-35344.6" - wire width 3 $0\cnt_2_8[2:0] - attribute \src "libresoc.v:35580.3-35599.6" - wire width 4 $0\cnt_3_0[3:0] - attribute \src "libresoc.v:35680.3-35699.6" - wire width 4 $0\cnt_3_10[3:0] - attribute \src "libresoc.v:35700.3-35719.6" - wire width 4 $0\cnt_3_12[3:0] - attribute \src "libresoc.v:35720.3-35739.6" - wire width 4 $0\cnt_3_14[3:0] - attribute \src "libresoc.v:35600.3-35619.6" - wire width 4 $0\cnt_3_2[3:0] - attribute \src "libresoc.v:35620.3-35639.6" - wire width 4 $0\cnt_3_4[3:0] - attribute \src "libresoc.v:35640.3-35659.6" - wire width 4 $0\cnt_3_6[3:0] - attribute \src "libresoc.v:35660.3-35679.6" - wire width 4 $0\cnt_3_8[3:0] - attribute \src "libresoc.v:35740.3-35759.6" - wire width 5 $0\cnt_4_0[4:0] - attribute \src "libresoc.v:35760.3-35779.6" - wire width 5 $0\cnt_4_2[4:0] - attribute \src "libresoc.v:35795.3-35814.6" - wire width 5 $0\cnt_4_4[4:0] - attribute \src "libresoc.v:35815.3-35834.6" - wire width 5 $0\cnt_4_6[4:0] - attribute \src "libresoc.v:35835.3-35854.6" - wire width 6 $0\cnt_5_0[5:0] - attribute \src "libresoc.v:35855.3-35874.6" - wire width 6 $0\cnt_5_2[5:0] - attribute \src "libresoc.v:35875.3-35894.6" - wire width 7 $0\cnt_6_0[6:0] - attribute \src "libresoc.v:34321.7-34321.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:34795.3-34809.6" - wire width 2 $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34885.3-34899.6" - wire width 2 $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34900.3-34914.6" - wire width 2 $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34915.3-34929.6" - wire width 2 $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34930.3-34944.6" - wire width 2 $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34945.3-34959.6" - wire width 2 $1\cnt_1_14[1:0] - attribute \src "libresoc.v:34975.3-34989.6" - wire width 2 $1\cnt_1_15[1:0] - attribute \src "libresoc.v:34990.3-35004.6" - wire width 2 $1\cnt_1_16[1:0] - attribute \src "libresoc.v:35005.3-35019.6" - wire width 2 $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35020.3-35034.6" - wire width 2 $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35035.3-35049.6" - wire width 2 $1\cnt_1_19[1:0] - attribute \src "libresoc.v:34960.3-34974.6" - wire width 2 $1\cnt_1_1[1:0] - attribute \src "libresoc.v:35050.3-35064.6" - wire width 2 $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35065.3-35079.6" - wire width 2 $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35080.3-35094.6" - wire width 2 $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35095.3-35109.6" - wire width 2 $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35110.3-35124.6" - wire width 2 $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35140.3-35154.6" - wire width 2 $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35155.3-35169.6" - wire width 2 $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35170.3-35184.6" - wire width 2 $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35185.3-35199.6" - wire width 2 $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35200.3-35214.6" - wire width 2 $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35125.3-35139.6" - wire width 2 $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35215.3-35229.6" - wire width 2 $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35230.3-35244.6" - wire width 2 $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35365.3-35379.6" - wire width 2 $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35780.3-35794.6" - wire width 2 $1\cnt_1_4[1:0] - attribute \src "libresoc.v:34810.3-34824.6" - wire width 2 $1\cnt_1_5[1:0] - attribute \src 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$1\cnt_3_4[3:0] - attribute \src "libresoc.v:35640.3-35659.6" - wire width 4 $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35660.3-35679.6" - wire width 4 $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35740.3-35759.6" - wire width 5 $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35760.3-35779.6" - wire width 5 $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35795.3-35814.6" - wire width 5 $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35815.3-35834.6" - wire width 5 $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35835.3-35854.6" - wire width 6 $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35855.3-35874.6" - wire width 6 $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35875.3-35894.6" - wire width 7 $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35245.3-35264.6" - wire width 3 $2\cnt_2_0[2:0] - attribute \src "libresoc.v:35345.3-35364.6" - wire width 3 $2\cnt_2_10[2:0] - attribute \src "libresoc.v:35380.3-35399.6" - wire width 3 $2\cnt_2_12[2:0] - attribute \src "libresoc.v:35400.3-35419.6" - wire width 3 $2\cnt_2_14[2:0] - attribute \src "libresoc.v:35420.3-35439.6" - wire width 3 $2\cnt_2_16[2:0] - attribute \src "libresoc.v:35440.3-35459.6" - wire width 3 $2\cnt_2_18[2:0] - attribute \src "libresoc.v:35460.3-35479.6" - wire width 3 $2\cnt_2_20[2:0] - attribute \src "libresoc.v:35480.3-35499.6" - wire width 3 $2\cnt_2_22[2:0] - attribute \src "libresoc.v:35500.3-35519.6" - wire width 3 $2\cnt_2_24[2:0] - attribute \src "libresoc.v:35520.3-35539.6" - wire width 3 $2\cnt_2_26[2:0] - attribute \src "libresoc.v:35540.3-35559.6" - wire width 3 $2\cnt_2_28[2:0] - attribute \src "libresoc.v:35265.3-35284.6" - wire width 3 $2\cnt_2_2[2:0] - attribute \src "libresoc.v:35560.3-35579.6" - wire width 3 $2\cnt_2_30[2:0] - attribute \src "libresoc.v:35285.3-35304.6" - wire width 3 $2\cnt_2_4[2:0] - attribute \src "libresoc.v:35305.3-35324.6" - wire width 3 $2\cnt_2_6[2:0] - attribute \src "libresoc.v:35325.3-35344.6" - wire width 3 $2\cnt_2_8[2:0] - attribute \src "libresoc.v:35580.3-35599.6" - wire width 4 $2\cnt_3_0[3:0] - attribute \src "libresoc.v:35680.3-35699.6" - wire width 4 $2\cnt_3_10[3:0] - attribute \src "libresoc.v:35700.3-35719.6" - wire width 4 $2\cnt_3_12[3:0] - attribute \src "libresoc.v:35720.3-35739.6" - wire width 4 $2\cnt_3_14[3:0] - attribute \src "libresoc.v:35600.3-35619.6" - wire width 4 $2\cnt_3_2[3:0] - attribute \src "libresoc.v:35620.3-35639.6" - wire width 4 $2\cnt_3_4[3:0] - attribute \src "libresoc.v:35640.3-35659.6" - wire width 4 $2\cnt_3_6[3:0] - attribute \src "libresoc.v:35660.3-35679.6" - wire width 4 $2\cnt_3_8[3:0] - attribute \src "libresoc.v:35740.3-35759.6" - wire width 5 $2\cnt_4_0[4:0] - attribute \src "libresoc.v:35760.3-35779.6" - wire width 5 $2\cnt_4_2[4:0] - attribute \src "libresoc.v:35795.3-35814.6" - wire width 5 $2\cnt_4_4[4:0] - attribute \src "libresoc.v:35815.3-35834.6" - wire width 5 $2\cnt_4_6[4:0] - attribute \src "libresoc.v:35835.3-35854.6" - wire width 6 $2\cnt_5_0[5:0] - attribute \src "libresoc.v:35855.3-35874.6" - wire width 6 $2\cnt_5_2[5:0] - attribute \src "libresoc.v:35875.3-35894.6" - wire width 7 $2\cnt_6_0[6:0] - attribute \src "libresoc.v:34702.17-34702.101" - wire $eq$libresoc.v:34702$1389_Y - attribute \src "libresoc.v:34703.18-34703.102" - wire $eq$libresoc.v:34703$1390_Y - attribute \src "libresoc.v:34705.19-34705.103" - wire $eq$libresoc.v:34705$1392_Y - attribute \src "libresoc.v:34706.19-34706.103" - wire $eq$libresoc.v:34706$1393_Y - attribute \src "libresoc.v:34708.19-34708.104" - wire $eq$libresoc.v:34708$1395_Y - attribute \src "libresoc.v:34709.19-34709.103" - wire $eq$libresoc.v:34709$1396_Y - attribute \src "libresoc.v:34711.19-34711.104" - wire $eq$libresoc.v:34711$1398_Y - attribute \src "libresoc.v:34712.19-34712.104" - wire $eq$libresoc.v:34712$1399_Y - attribute \src "libresoc.v:34715.19-34715.104" - wire $eq$libresoc.v:34715$1402_Y - attribute \src "libresoc.v:34716.19-34716.104" - wire $eq$libresoc.v:34716$1403_Y - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 7 \cnt_6_0 - attribute \src "libresoc.v:34321.7-34321.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 7 output 1 \lz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair38 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair54 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" - wire width 64 input 2 \sig_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34702$1389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_2 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34702$1389_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34703$1390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_0 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34703$1390_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34705$1392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_6 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34705$1392_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34706$1393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_4 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34706$1393_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34708$1395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_10 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34708$1395_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34709$1396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_8 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34709$1396_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34711$1398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_14 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34711$1398_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34712$1399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_12 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34712$1399_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34715$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_18 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34715$1402_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34716$1403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_16 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34716$1403_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34718$1405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_22 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34718$1405_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34719$1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_20 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34719$1406_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34721$1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_26 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34721$1408_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34722$1409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_24 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34722$1409_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34724$1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_5 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34724$1411_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34725$1412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_30 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34725$1412_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34726$1413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_28 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34726$1413_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34728$1415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_2 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34728$1415_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34729$1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_0 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34729$1416_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34731$1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_6 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34731$1418_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34732$1419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_4 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34732$1419_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34734$1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_10 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34734$1421_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34735$1422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_4 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34735$1422_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34736$1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_8 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34736$1423_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34738$1425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_14 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34738$1425_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34739$1426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_12 [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:34739$1426_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34741$1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_2 [4] - connect \B 1'1 - connect \Y $eq$libresoc.v:34741$1428_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34742$1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_0 [4] - connect \B 1'1 - connect \Y $eq$libresoc.v:34742$1429_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34744$1431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_6 [4] - connect \B 1'1 - connect \Y $eq$libresoc.v:34744$1431_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34745$1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_4 [4] - connect \B 1'1 - connect \Y $eq$libresoc.v:34745$1432_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34748$1435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_2 [5] - connect \B 1'1 - connect \Y $eq$libresoc.v:34748$1435_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34749$1436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_0 [5] - connect \B 1'1 - connect \Y $eq$libresoc.v:34749$1436_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34751$1438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_1 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34751$1438_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34752$1439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_7 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34752$1439_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34753$1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_6 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34753$1440_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34755$1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_9 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34755$1442_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34756$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_8 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34756$1443_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34758$1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_11 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34758$1445_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34759$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_10 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34759$1446_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34761$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_13 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34761$1448_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34762$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_0 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34762$1449_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34763$1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_12 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34763$1450_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34765$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_15 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34765$1452_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34766$1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_14 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34766$1453_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34768$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_17 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34768$1455_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34769$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_16 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34769$1456_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34771$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_19 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34771$1458_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34772$1459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_18 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34772$1459_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34775$1462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_21 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34775$1462_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34776$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_20 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34776$1463_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34778$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_23 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34778$1465_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34779$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_22 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34779$1466_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34781$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_25 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34781$1468_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34782$1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_24 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34782$1469_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34784$1471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_3 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34784$1471_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34785$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_27 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34785$1472_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34786$1473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_26 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34786$1473_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34788$1475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_29 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34788$1475_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34789$1476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_28 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34789$1476_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34791$1478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_31 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34791$1478_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $eq$libresoc.v:34792$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_30 [1] - connect \B 1'1 - connect \Y $eq$libresoc.v:34792$1479_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $eq$libresoc.v:34794$1481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_2 [2] - connect \B 1'1 - connect \Y $eq$libresoc.v:34794$1481_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34704$1391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_0 [1:0] } - connect \Y $pos$libresoc.v:34704$1391_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34707$1394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_4 [1:0] } - connect \Y $pos$libresoc.v:34707$1394_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34710$1397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_8 [1:0] } - connect \Y $pos$libresoc.v:34710$1397_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34713$1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_2 [0] } - connect \Y $pos$libresoc.v:34713$1400_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34714$1401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_12 [1:0] } - connect \Y $pos$libresoc.v:34714$1401_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34717$1404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_16 [1:0] } - connect \Y $pos$libresoc.v:34717$1404_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34720$1407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_20 [1:0] } - connect \Y $pos$libresoc.v:34720$1407_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34723$1410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_24 [1:0] } - connect \Y $pos$libresoc.v:34723$1410_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34727$1414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'01 \cnt_2_28 [1:0] } - connect \Y $pos$libresoc.v:34727$1414_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34730$1417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_0 [2:0] } - connect \Y $pos$libresoc.v:34730$1417_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34733$1420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_4 [2:0] } - connect \Y $pos$libresoc.v:34733$1420_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34737$1424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_8 [2:0] } - connect \Y $pos$libresoc.v:34737$1424_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34740$1427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'01 \cnt_3_12 [2:0] } - connect \Y $pos$libresoc.v:34740$1427_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34743$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'01 \cnt_4_0 [3:0] } - connect \Y $pos$libresoc.v:34743$1430_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34746$1433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_4 [0] } - connect \Y $pos$libresoc.v:34746$1433_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34747$1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'01 \cnt_4_4 [3:0] } - connect \Y $pos$libresoc.v:34747$1434_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34750$1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'01 \cnt_5_0 [4:0] } - connect \Y $pos$libresoc.v:34750$1437_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34754$1441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_6 [0] } - connect \Y $pos$libresoc.v:34754$1441_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34757$1444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_8 [0] } - connect \Y $pos$libresoc.v:34757$1444_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34760$1447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_10 [0] } - connect \Y $pos$libresoc.v:34760$1447_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34764$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_12 [0] } - connect \Y $pos$libresoc.v:34764$1451_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34767$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_14 [0] } - connect \Y $pos$libresoc.v:34767$1454_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34770$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_16 [0] } - connect \Y $pos$libresoc.v:34770$1457_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34773$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_0 [0] } - connect \Y $pos$libresoc.v:34773$1460_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34774$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_18 [0] } - connect \Y $pos$libresoc.v:34774$1461_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34777$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_20 [0] } - connect \Y $pos$libresoc.v:34777$1464_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34780$1467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_22 [0] } - connect \Y $pos$libresoc.v:34780$1467_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34783$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_24 [0] } - connect \Y $pos$libresoc.v:34783$1470_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34787$1474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_26 [0] } - connect \Y $pos$libresoc.v:34787$1474_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34790$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_28 [0] } - connect \Y $pos$libresoc.v:34790$1477_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $pos$libresoc.v:34793$1480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'01 \cnt_1_30 [0] } - connect \Y $pos$libresoc.v:34793$1480_Y - end - attribute \src "libresoc.v:34321.7-34321.20" - process $proc$libresoc.v:34321$1545 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:34795.3-34809.6" - process $proc$libresoc.v:34795$1482 - assign { } { } - assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] - attribute \src "libresoc.v:34796.5-34796.29" - switch \initial - attribute \src "libresoc.v:34796.9-34796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair0 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_0[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_0[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_0[1:0] 2'00 - end - sync always - update \cnt_1_0 $0\cnt_1_0[1:0] - end - attribute \src "libresoc.v:34810.3-34824.6" - process $proc$libresoc.v:34810$1483 - assign { } { } - assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] - attribute \src "libresoc.v:34811.5-34811.29" - switch \initial - attribute \src "libresoc.v:34811.9-34811.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair10 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_5[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_5[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_5[1:0] 2'00 - end - sync always - update \cnt_1_5 $0\cnt_1_5[1:0] - end - attribute \src "libresoc.v:34825.3-34839.6" - process $proc$libresoc.v:34825$1484 - assign { } { } - assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] - attribute \src "libresoc.v:34826.5-34826.29" - switch \initial - attribute \src "libresoc.v:34826.9-34826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair12 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_6[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_6[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_6[1:0] 2'00 - end - sync always - update \cnt_1_6 $0\cnt_1_6[1:0] - end - attribute \src "libresoc.v:34840.3-34854.6" - process $proc$libresoc.v:34840$1485 - assign { } { } - assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] - attribute \src "libresoc.v:34841.5-34841.29" - switch \initial - attribute \src "libresoc.v:34841.9-34841.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair14 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_7[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_7[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_7[1:0] 2'00 - end - sync always - update \cnt_1_7 $0\cnt_1_7[1:0] - end - attribute \src "libresoc.v:34855.3-34869.6" - process $proc$libresoc.v:34855$1486 - assign { } { } - assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] - attribute \src "libresoc.v:34856.5-34856.29" - switch \initial - attribute \src "libresoc.v:34856.9-34856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair16 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_8[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_8[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_8[1:0] 2'00 - end - sync always - update \cnt_1_8 $0\cnt_1_8[1:0] - end - attribute \src "libresoc.v:34870.3-34884.6" - process $proc$libresoc.v:34870$1487 - assign { } { } - assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] - attribute \src "libresoc.v:34871.5-34871.29" - switch \initial - attribute \src "libresoc.v:34871.9-34871.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair18 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_9[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_9[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_9[1:0] 2'00 - end - sync always - update \cnt_1_9 $0\cnt_1_9[1:0] - end - attribute \src "libresoc.v:34885.3-34899.6" - process $proc$libresoc.v:34885$1488 - assign { } { } - assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] - attribute \src "libresoc.v:34886.5-34886.29" - switch \initial - attribute \src "libresoc.v:34886.9-34886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair20 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_10[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_10[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_10[1:0] 2'00 - end - sync always - update \cnt_1_10 $0\cnt_1_10[1:0] - end - attribute \src "libresoc.v:34900.3-34914.6" - process $proc$libresoc.v:34900$1489 - assign { } { } - assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] - attribute \src "libresoc.v:34901.5-34901.29" - switch \initial - attribute \src "libresoc.v:34901.9-34901.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair22 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_11[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_11[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_11[1:0] 2'00 - end - sync always - update \cnt_1_11 $0\cnt_1_11[1:0] - end - attribute \src "libresoc.v:34915.3-34929.6" - process $proc$libresoc.v:34915$1490 - assign { } { } - assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] - attribute \src "libresoc.v:34916.5-34916.29" - switch \initial - attribute \src "libresoc.v:34916.9-34916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair24 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_12[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_12[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_12[1:0] 2'00 - end - sync always - update \cnt_1_12 $0\cnt_1_12[1:0] - end - attribute \src "libresoc.v:34930.3-34944.6" - process $proc$libresoc.v:34930$1491 - assign { } { } - assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] - attribute \src "libresoc.v:34931.5-34931.29" - switch \initial - attribute \src "libresoc.v:34931.9-34931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair26 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_13[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_13[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_13[1:0] 2'00 - end - sync always - update \cnt_1_13 $0\cnt_1_13[1:0] - end - attribute \src "libresoc.v:34945.3-34959.6" - process $proc$libresoc.v:34945$1492 - assign { } { } - assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] - attribute \src "libresoc.v:34946.5-34946.29" - switch \initial - attribute \src "libresoc.v:34946.9-34946.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair28 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_14[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_14[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_14[1:0] 2'00 - end - sync always - update \cnt_1_14 $0\cnt_1_14[1:0] - end - attribute \src "libresoc.v:34960.3-34974.6" - process $proc$libresoc.v:34960$1493 - assign { } { } - assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] - attribute \src "libresoc.v:34961.5-34961.29" - switch \initial - attribute \src "libresoc.v:34961.9-34961.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair2 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_1[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_1[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_1[1:0] 2'00 - end - sync always - update \cnt_1_1 $0\cnt_1_1[1:0] - end - attribute \src "libresoc.v:34975.3-34989.6" - process $proc$libresoc.v:34975$1494 - assign { } { } - assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] - attribute \src "libresoc.v:34976.5-34976.29" - switch \initial - attribute \src "libresoc.v:34976.9-34976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair30 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_15[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_15[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_15[1:0] 2'00 - end - sync always - update \cnt_1_15 $0\cnt_1_15[1:0] - end - attribute \src "libresoc.v:34990.3-35004.6" - process $proc$libresoc.v:34990$1495 - assign { } { } - assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] - attribute \src "libresoc.v:34991.5-34991.29" - switch \initial - attribute \src "libresoc.v:34991.9-34991.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair32 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_16[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_16[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_16[1:0] 2'00 - end - sync always - update \cnt_1_16 $0\cnt_1_16[1:0] - end - attribute \src "libresoc.v:35005.3-35019.6" - process $proc$libresoc.v:35005$1496 - assign { } { } - assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35006.5-35006.29" - switch \initial - attribute \src "libresoc.v:35006.9-35006.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair34 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_17[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_17[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_17[1:0] 2'00 - end - sync always - update \cnt_1_17 $0\cnt_1_17[1:0] - end - attribute \src "libresoc.v:35020.3-35034.6" - process $proc$libresoc.v:35020$1497 - assign { } { } - assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35021.5-35021.29" - switch \initial - attribute \src "libresoc.v:35021.9-35021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair36 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_18[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_18[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_18[1:0] 2'00 - end - sync always - update \cnt_1_18 $0\cnt_1_18[1:0] - end - attribute \src "libresoc.v:35035.3-35049.6" - process $proc$libresoc.v:35035$1498 - assign { } { } - assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] - attribute \src "libresoc.v:35036.5-35036.29" - switch \initial - attribute \src "libresoc.v:35036.9-35036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair38 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_19[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_19[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_19[1:0] 2'00 - end - sync always - update \cnt_1_19 $0\cnt_1_19[1:0] - end - attribute \src "libresoc.v:35050.3-35064.6" - process $proc$libresoc.v:35050$1499 - assign { } { } - assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35051.5-35051.29" - switch \initial - attribute \src "libresoc.v:35051.9-35051.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair40 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_20[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_20[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_20[1:0] 2'00 - end - sync always - update \cnt_1_20 $0\cnt_1_20[1:0] - end - attribute \src "libresoc.v:35065.3-35079.6" - process $proc$libresoc.v:35065$1500 - assign { } { } - assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35066.5-35066.29" - switch \initial - attribute \src "libresoc.v:35066.9-35066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair42 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_21[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_21[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_21[1:0] 2'00 - end - sync always - update \cnt_1_21 $0\cnt_1_21[1:0] - end - attribute \src "libresoc.v:35080.3-35094.6" - process $proc$libresoc.v:35080$1501 - assign { } { } - assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35081.5-35081.29" - switch \initial - attribute \src "libresoc.v:35081.9-35081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair44 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_22[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_22[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_22[1:0] 2'00 - end - sync always - update \cnt_1_22 $0\cnt_1_22[1:0] - end - attribute \src "libresoc.v:35095.3-35109.6" - process $proc$libresoc.v:35095$1502 - assign { } { } - assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35096.5-35096.29" - switch \initial - attribute \src "libresoc.v:35096.9-35096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair46 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_23[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_23[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_23[1:0] 2'00 - end - sync always - update \cnt_1_23 $0\cnt_1_23[1:0] - end - attribute \src "libresoc.v:35110.3-35124.6" - process $proc$libresoc.v:35110$1503 - assign { } { } - assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35111.5-35111.29" - switch \initial - attribute \src "libresoc.v:35111.9-35111.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair48 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_24[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_24[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_24[1:0] 2'00 - end - sync always - update \cnt_1_24 $0\cnt_1_24[1:0] - end - attribute \src "libresoc.v:35125.3-35139.6" - process $proc$libresoc.v:35125$1504 - assign { } { } - assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35126.5-35126.29" - switch \initial - attribute \src "libresoc.v:35126.9-35126.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair4 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_2[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_2[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_2[1:0] 2'00 - end - sync always - update \cnt_1_2 $0\cnt_1_2[1:0] - end - attribute \src "libresoc.v:35140.3-35154.6" - process $proc$libresoc.v:35140$1505 - assign { } { } - assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35141.5-35141.29" - switch \initial - attribute \src "libresoc.v:35141.9-35141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair50 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_25[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_25[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_25[1:0] 2'00 - end - sync always - update \cnt_1_25 $0\cnt_1_25[1:0] - end - attribute \src "libresoc.v:35155.3-35169.6" - process $proc$libresoc.v:35155$1506 - assign { } { } - assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35156.5-35156.29" - switch \initial - attribute \src "libresoc.v:35156.9-35156.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair52 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_26[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_26[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_26[1:0] 2'00 - end - sync always - update \cnt_1_26 $0\cnt_1_26[1:0] - end - attribute \src "libresoc.v:35170.3-35184.6" - process $proc$libresoc.v:35170$1507 - assign { } { } - assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35171.5-35171.29" - switch \initial - attribute \src "libresoc.v:35171.9-35171.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair54 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_27[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_27[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_27[1:0] 2'00 - end - sync always - update \cnt_1_27 $0\cnt_1_27[1:0] - end - attribute \src "libresoc.v:35185.3-35199.6" - process $proc$libresoc.v:35185$1508 - assign { } { } - assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35186.5-35186.29" - switch \initial - attribute \src "libresoc.v:35186.9-35186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair56 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_28[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_28[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_28[1:0] 2'00 - end - sync always - update \cnt_1_28 $0\cnt_1_28[1:0] - end - attribute \src "libresoc.v:35200.3-35214.6" - process $proc$libresoc.v:35200$1509 - assign { } { } - assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35201.5-35201.29" - switch \initial - attribute \src "libresoc.v:35201.9-35201.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair58 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_29[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_29[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_29[1:0] 2'00 - end - sync always - update \cnt_1_29 $0\cnt_1_29[1:0] - end - attribute \src "libresoc.v:35215.3-35229.6" - process $proc$libresoc.v:35215$1510 - assign { } { } - assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35216.5-35216.29" - switch \initial - attribute \src "libresoc.v:35216.9-35216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair60 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_30[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_30[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_30[1:0] 2'00 - end - sync always - update \cnt_1_30 $0\cnt_1_30[1:0] - end - attribute \src "libresoc.v:35230.3-35244.6" - process $proc$libresoc.v:35230$1511 - assign { } { } - assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35231.5-35231.29" - switch \initial - attribute \src "libresoc.v:35231.9-35231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair62 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_31[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_31[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_31[1:0] 2'00 - end - sync always - update \cnt_1_31 $0\cnt_1_31[1:0] - end - attribute \src "libresoc.v:35245.3-35264.6" - process $proc$libresoc.v:35245$1512 - assign { } { } - assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35246.5-35246.29" - switch \initial - attribute \src "libresoc.v:35246.9-35246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_0[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_0[2:0] \$5 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } - end - sync always - update \cnt_2_0 $0\cnt_2_0[2:0] - end - attribute \src "libresoc.v:35265.3-35284.6" - process $proc$libresoc.v:35265$1513 - assign { } { } - assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35266.5-35266.29" - switch \initial - attribute \src "libresoc.v:35266.9-35266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_2[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_2[2:0] \$11 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } - end - sync always - update \cnt_2_2 $0\cnt_2_2[2:0] - end - attribute \src "libresoc.v:35285.3-35304.6" - process $proc$libresoc.v:35285$1514 - assign { } { } - assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35286.5-35286.29" - switch \initial - attribute \src "libresoc.v:35286.9-35286.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_4[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_4[2:0] \$17 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } - end - sync always - update \cnt_2_4 $0\cnt_2_4[2:0] - end - attribute \src "libresoc.v:35305.3-35324.6" - process $proc$libresoc.v:35305$1515 - assign { } { } - assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35306.5-35306.29" - switch \initial - attribute \src "libresoc.v:35306.9-35306.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_6[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_6[2:0] \$23 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } - end - sync always - update \cnt_2_6 $0\cnt_2_6[2:0] - end - attribute \src "libresoc.v:35325.3-35344.6" - process $proc$libresoc.v:35325$1516 - assign { } { } - assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35326.5-35326.29" - switch \initial - attribute \src "libresoc.v:35326.9-35326.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_8[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_8[2:0] \$29 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } - end - sync always - update \cnt_2_8 $0\cnt_2_8[2:0] - end - attribute \src "libresoc.v:35345.3-35364.6" - process $proc$libresoc.v:35345$1517 - assign { } { } - assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35346.5-35346.29" - switch \initial - attribute \src "libresoc.v:35346.9-35346.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_10[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_10[2:0] \$35 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } - end - sync always - update \cnt_2_10 $0\cnt_2_10[2:0] - end - attribute \src "libresoc.v:35365.3-35379.6" - process $proc$libresoc.v:35365$1518 - assign { } { } - assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35366.5-35366.29" - switch \initial - attribute \src "libresoc.v:35366.9-35366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair6 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_3[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_3[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_3[1:0] 2'00 - end - sync always - update \cnt_1_3 $0\cnt_1_3[1:0] - end - attribute \src "libresoc.v:35380.3-35399.6" - process $proc$libresoc.v:35380$1519 - assign { } { } - assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35381.5-35381.29" - switch \initial - attribute \src "libresoc.v:35381.9-35381.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$37 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$39 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_12[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_12[2:0] \$41 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } - end - sync always - update \cnt_2_12 $0\cnt_2_12[2:0] - end - attribute \src "libresoc.v:35400.3-35419.6" - process $proc$libresoc.v:35400$1520 - assign { } { } - assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35401.5-35401.29" - switch \initial - attribute \src "libresoc.v:35401.9-35401.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$43 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$45 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_14[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_14[2:0] \$47 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } - end - sync always - update \cnt_2_14 $0\cnt_2_14[2:0] - end - attribute \src "libresoc.v:35420.3-35439.6" - process $proc$libresoc.v:35420$1521 - assign { } { } - assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35421.5-35421.29" - switch \initial - attribute \src "libresoc.v:35421.9-35421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$49 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$51 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_16[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_16[2:0] \$53 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } - end - sync always - update \cnt_2_16 $0\cnt_2_16[2:0] - end - attribute \src "libresoc.v:35440.3-35459.6" - process $proc$libresoc.v:35440$1522 - assign { } { } - assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35441.5-35441.29" - switch \initial - attribute \src "libresoc.v:35441.9-35441.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$57 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_18[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_18[2:0] \$59 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } - end - sync always - update \cnt_2_18 $0\cnt_2_18[2:0] - end - attribute \src "libresoc.v:35460.3-35479.6" - process $proc$libresoc.v:35460$1523 - assign { } { } - assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35461.5-35461.29" - switch \initial - attribute \src "libresoc.v:35461.9-35461.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$61 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_20[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_20[2:0] \$65 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } - end - sync always - update \cnt_2_20 $0\cnt_2_20[2:0] - end - attribute \src "libresoc.v:35480.3-35499.6" - process $proc$libresoc.v:35480$1524 - assign { } { } - assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35481.5-35481.29" - switch \initial - attribute \src "libresoc.v:35481.9-35481.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$67 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_22[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_22[2:0] \$71 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } - end - sync always - update \cnt_2_22 $0\cnt_2_22[2:0] - end - attribute \src "libresoc.v:35500.3-35519.6" - process $proc$libresoc.v:35500$1525 - assign { } { } - assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35501.5-35501.29" - switch \initial - attribute \src "libresoc.v:35501.9-35501.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$73 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$75 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_24[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_24[2:0] \$77 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } - end - sync always - update \cnt_2_24 $0\cnt_2_24[2:0] - end - attribute \src "libresoc.v:35520.3-35539.6" - process $proc$libresoc.v:35520$1526 - assign { } { } - assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35521.5-35521.29" - switch \initial - attribute \src "libresoc.v:35521.9-35521.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$79 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_26[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_26[2:0] \$83 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } - end - sync always - update \cnt_2_26 $0\cnt_2_26[2:0] - end - attribute \src "libresoc.v:35540.3-35559.6" - process $proc$libresoc.v:35540$1527 - assign { } { } - assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35541.5-35541.29" - switch \initial - attribute \src "libresoc.v:35541.9-35541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_28[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_28[2:0] \$89 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } - end - sync always - update \cnt_2_28 $0\cnt_2_28[2:0] - end - attribute \src "libresoc.v:35560.3-35579.6" - process $proc$libresoc.v:35560$1528 - assign { } { } - assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35561.5-35561.29" - switch \initial - attribute \src "libresoc.v:35561.9-35561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$91 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_2_30[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_2_30[2:0] \$95 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } - end - sync always - update \cnt_2_30 $0\cnt_2_30[2:0] - end - attribute \src "libresoc.v:35580.3-35599.6" - process $proc$libresoc.v:35580$1529 - assign { } { } - assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35581.5-35581.29" - switch \initial - attribute \src "libresoc.v:35581.9-35581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$97 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$99 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_0[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_0[3:0] \$101 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } - end - sync always - update \cnt_3_0 $0\cnt_3_0[3:0] - end - attribute \src "libresoc.v:35600.3-35619.6" - process $proc$libresoc.v:35600$1530 - assign { } { } - assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35601.5-35601.29" - switch \initial - attribute \src "libresoc.v:35601.9-35601.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$105 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_2[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_2[3:0] \$107 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } - end - sync always - update \cnt_3_2 $0\cnt_3_2[3:0] - end - attribute \src "libresoc.v:35620.3-35639.6" - process $proc$libresoc.v:35620$1531 - assign { } { } - assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35621.5-35621.29" - switch \initial - attribute \src "libresoc.v:35621.9-35621.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$109 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$111 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_4[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_4[3:0] \$113 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } - end - sync always - update \cnt_3_4 $0\cnt_3_4[3:0] - end - attribute \src "libresoc.v:35640.3-35659.6" - process $proc$libresoc.v:35640$1532 - assign { } { } - assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35641.5-35641.29" - switch \initial - attribute \src "libresoc.v:35641.9-35641.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$117 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_6[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_6[3:0] \$119 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } - end - sync always - update \cnt_3_6 $0\cnt_3_6[3:0] - end - attribute \src "libresoc.v:35660.3-35679.6" - process $proc$libresoc.v:35660$1533 - assign { } { } - assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35661.5-35661.29" - switch \initial - attribute \src "libresoc.v:35661.9-35661.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$121 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$123 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_8[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_8[3:0] \$125 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } - end - sync always - update \cnt_3_8 $0\cnt_3_8[3:0] - end - attribute \src "libresoc.v:35680.3-35699.6" - process $proc$libresoc.v:35680$1534 - assign { } { } - assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35681.5-35681.29" - switch \initial - attribute \src "libresoc.v:35681.9-35681.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$127 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$129 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_10[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_10[3:0] \$131 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } - end - sync always - update \cnt_3_10 $0\cnt_3_10[3:0] - end - attribute \src "libresoc.v:35700.3-35719.6" - process $proc$libresoc.v:35700$1535 - assign { } { } - assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35701.5-35701.29" - switch \initial - attribute \src "libresoc.v:35701.9-35701.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$133 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$135 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_12[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_12[3:0] \$137 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } - end - sync always - update \cnt_3_12 $0\cnt_3_12[3:0] - end - attribute \src "libresoc.v:35720.3-35739.6" - process $proc$libresoc.v:35720$1536 - assign { } { } - assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35721.5-35721.29" - switch \initial - attribute \src "libresoc.v:35721.9-35721.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$139 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$141 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_3_14[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_3_14[3:0] \$143 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } - end - sync always - update \cnt_3_14 $0\cnt_3_14[3:0] - end - attribute \src "libresoc.v:35740.3-35759.6" - process $proc$libresoc.v:35740$1537 - assign { } { } - assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] - attribute \src "libresoc.v:35741.5-35741.29" - switch \initial - attribute \src "libresoc.v:35741.9-35741.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$145 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$147 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_0[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_0[4:0] \$149 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } - end - sync always - update \cnt_4_0 $0\cnt_4_0[4:0] - end - attribute \src "libresoc.v:35760.3-35779.6" - process $proc$libresoc.v:35760$1538 - assign { } { } - assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] - attribute \src "libresoc.v:35761.5-35761.29" - switch \initial - attribute \src "libresoc.v:35761.9-35761.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$151 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$153 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_2[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_2[4:0] \$155 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } - end - sync always - update \cnt_4_2 $0\cnt_4_2[4:0] - end - attribute \src "libresoc.v:35780.3-35794.6" - process $proc$libresoc.v:35780$1539 - assign { } { } - assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] - attribute \src "libresoc.v:35781.5-35781.29" - switch \initial - attribute \src "libresoc.v:35781.9-35781.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair8 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cnt_1_4[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cnt_1_4[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_1_4[1:0] 2'00 - end - sync always - update \cnt_1_4 $0\cnt_1_4[1:0] - end - attribute \src "libresoc.v:35795.3-35814.6" - process $proc$libresoc.v:35795$1540 - assign { } { } - assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] - attribute \src "libresoc.v:35796.5-35796.29" - switch \initial - attribute \src "libresoc.v:35796.9-35796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$157 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$159 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_4[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_4[4:0] \$161 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } - end - sync always - update \cnt_4_4 $0\cnt_4_4[4:0] - end - attribute \src "libresoc.v:35815.3-35834.6" - process $proc$libresoc.v:35815$1541 - assign { } { } - assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] - attribute \src "libresoc.v:35816.5-35816.29" - switch \initial - attribute \src "libresoc.v:35816.9-35816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$163 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$165 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_4_6[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_4_6[4:0] \$167 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } - end - sync always - update \cnt_4_6 $0\cnt_4_6[4:0] - end - attribute \src "libresoc.v:35835.3-35854.6" - process $proc$libresoc.v:35835$1542 - assign { } { } - assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] - attribute \src "libresoc.v:35836.5-35836.29" - switch \initial - attribute \src "libresoc.v:35836.9-35836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$169 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$171 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_5_0[5:0] 6'100000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_5_0[5:0] \$173 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } - end - sync always - update \cnt_5_0 $0\cnt_5_0[5:0] - end - attribute \src "libresoc.v:35855.3-35874.6" - process $proc$libresoc.v:35855$1543 - assign { } { } - assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] - attribute \src "libresoc.v:35856.5-35856.29" - switch \initial - attribute \src "libresoc.v:35856.9-35856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$175 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$177 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_5_2[5:0] 6'100000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_5_2[5:0] \$179 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } - end - sync always - update \cnt_5_2 $0\cnt_5_2[5:0] - end - attribute \src "libresoc.v:35875.3-35894.6" - process $proc$libresoc.v:35875$1544 - assign { } { } - assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35876.5-35876.29" - switch \initial - attribute \src "libresoc.v:35876.9-35876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch \$181 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch \$183 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cnt_6_0[6:0] 7'1000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cnt_6_0[6:0] \$185 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } - end - sync always - update \cnt_6_0 $0\cnt_6_0[6:0] - end - connect \$9 $eq$libresoc.v:34702$1389_Y - connect \$99 $eq$libresoc.v:34703$1390_Y - connect \$101 $pos$libresoc.v:34704$1391_Y - connect \$103 $eq$libresoc.v:34705$1392_Y - connect \$105 $eq$libresoc.v:34706$1393_Y - connect \$107 $pos$libresoc.v:34707$1394_Y - connect \$109 $eq$libresoc.v:34708$1395_Y - connect \$111 $eq$libresoc.v:34709$1396_Y - connect \$113 $pos$libresoc.v:34710$1397_Y - connect \$115 $eq$libresoc.v:34711$1398_Y - connect \$117 $eq$libresoc.v:34712$1399_Y - connect \$11 $pos$libresoc.v:34713$1400_Y - connect \$119 $pos$libresoc.v:34714$1401_Y - connect \$121 $eq$libresoc.v:34715$1402_Y - connect \$123 $eq$libresoc.v:34716$1403_Y - connect \$125 $pos$libresoc.v:34717$1404_Y - connect \$127 $eq$libresoc.v:34718$1405_Y - connect \$129 $eq$libresoc.v:34719$1406_Y - connect \$131 $pos$libresoc.v:34720$1407_Y - connect \$133 $eq$libresoc.v:34721$1408_Y - connect \$135 $eq$libresoc.v:34722$1409_Y - connect \$137 $pos$libresoc.v:34723$1410_Y - connect \$13 $eq$libresoc.v:34724$1411_Y - connect \$139 $eq$libresoc.v:34725$1412_Y - connect \$141 $eq$libresoc.v:34726$1413_Y - connect \$143 $pos$libresoc.v:34727$1414_Y - connect \$145 $eq$libresoc.v:34728$1415_Y - connect \$147 $eq$libresoc.v:34729$1416_Y - connect \$149 $pos$libresoc.v:34730$1417_Y - connect \$151 $eq$libresoc.v:34731$1418_Y - connect \$153 $eq$libresoc.v:34732$1419_Y - connect \$155 $pos$libresoc.v:34733$1420_Y - connect \$157 $eq$libresoc.v:34734$1421_Y - connect \$15 $eq$libresoc.v:34735$1422_Y - connect \$159 $eq$libresoc.v:34736$1423_Y - connect \$161 $pos$libresoc.v:34737$1424_Y - connect \$163 $eq$libresoc.v:34738$1425_Y - connect \$165 $eq$libresoc.v:34739$1426_Y - connect \$167 $pos$libresoc.v:34740$1427_Y - connect \$169 $eq$libresoc.v:34741$1428_Y - connect \$171 $eq$libresoc.v:34742$1429_Y - connect \$173 $pos$libresoc.v:34743$1430_Y - connect \$175 $eq$libresoc.v:34744$1431_Y - connect \$177 $eq$libresoc.v:34745$1432_Y - connect \$17 $pos$libresoc.v:34746$1433_Y - connect \$179 $pos$libresoc.v:34747$1434_Y - connect \$181 $eq$libresoc.v:34748$1435_Y - connect \$183 $eq$libresoc.v:34749$1436_Y - connect \$185 $pos$libresoc.v:34750$1437_Y - connect \$1 $eq$libresoc.v:34751$1438_Y - connect \$19 $eq$libresoc.v:34752$1439_Y - connect \$21 $eq$libresoc.v:34753$1440_Y - connect \$23 $pos$libresoc.v:34754$1441_Y - connect \$25 $eq$libresoc.v:34755$1442_Y - connect \$27 $eq$libresoc.v:34756$1443_Y - connect \$29 $pos$libresoc.v:34757$1444_Y - connect \$31 $eq$libresoc.v:34758$1445_Y - connect \$33 $eq$libresoc.v:34759$1446_Y - connect \$35 $pos$libresoc.v:34760$1447_Y - connect \$37 $eq$libresoc.v:34761$1448_Y - connect \$3 $eq$libresoc.v:34762$1449_Y - connect \$39 $eq$libresoc.v:34763$1450_Y - connect \$41 $pos$libresoc.v:34764$1451_Y - connect \$43 $eq$libresoc.v:34765$1452_Y - connect \$45 $eq$libresoc.v:34766$1453_Y - connect \$47 $pos$libresoc.v:34767$1454_Y - connect \$49 $eq$libresoc.v:34768$1455_Y - connect \$51 $eq$libresoc.v:34769$1456_Y - connect \$53 $pos$libresoc.v:34770$1457_Y - connect \$55 $eq$libresoc.v:34771$1458_Y - connect \$57 $eq$libresoc.v:34772$1459_Y - connect \$5 $pos$libresoc.v:34773$1460_Y - connect \$59 $pos$libresoc.v:34774$1461_Y - connect \$61 $eq$libresoc.v:34775$1462_Y - connect \$63 $eq$libresoc.v:34776$1463_Y - connect \$65 $pos$libresoc.v:34777$1464_Y - connect \$67 $eq$libresoc.v:34778$1465_Y - connect \$69 $eq$libresoc.v:34779$1466_Y - connect \$71 $pos$libresoc.v:34780$1467_Y - connect \$73 $eq$libresoc.v:34781$1468_Y - connect \$75 $eq$libresoc.v:34782$1469_Y - connect \$77 $pos$libresoc.v:34783$1470_Y - connect \$7 $eq$libresoc.v:34784$1471_Y - connect \$79 $eq$libresoc.v:34785$1472_Y - connect \$81 $eq$libresoc.v:34786$1473_Y - connect \$83 $pos$libresoc.v:34787$1474_Y - connect \$85 $eq$libresoc.v:34788$1475_Y - connect \$87 $eq$libresoc.v:34789$1476_Y - connect \$89 $pos$libresoc.v:34790$1477_Y - connect \$91 $eq$libresoc.v:34791$1478_Y - connect \$93 $eq$libresoc.v:34792$1479_Y - connect \$95 $pos$libresoc.v:34793$1480_Y - connect \$97 $eq$libresoc.v:34794$1481_Y - connect \lz \cnt_6_0 - connect \pair62 \sig_in [63:62] - connect \pair60 \sig_in [61:60] - connect \pair58 \sig_in [59:58] - connect \pair56 \sig_in [57:56] - connect \pair54 \sig_in [55:54] - connect \pair52 \sig_in [53:52] - connect \pair50 \sig_in [51:50] - connect \pair48 \sig_in [49:48] - connect \pair46 \sig_in [47:46] - connect \pair44 \sig_in [45:44] - connect \pair42 \sig_in [43:42] - connect \pair40 \sig_in [41:40] - connect \pair38 \sig_in [39:38] - connect \pair36 \sig_in [37:36] - connect \pair34 \sig_in [35:34] - connect \pair32 \sig_in [33:32] - connect \pair30 \sig_in [31:30] - connect \pair28 \sig_in [29:28] - connect \pair26 \sig_in [27:26] - connect \pair24 \sig_in [25:24] - connect \pair22 \sig_in [23:22] - connect \pair20 \sig_in [21:20] - connect \pair18 \sig_in [19:18] - connect \pair16 \sig_in [17:16] - connect \pair14 \sig_in [15:14] - connect \pair12 \sig_in [13:12] - connect \pair10 \sig_in [11:10] - connect \pair8 \sig_in [9:8] - connect \pair6 \sig_in [7:6] - connect \pair4 \sig_in [5:4] - connect \pair2 \sig_in [3:2] - connect \pair0 \sig_in [1:0] -end -attribute \src "libresoc.v:35932.1-48737.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core" -attribute \generator "nMigen" -module \core - attribute \src "libresoc.v:45707.3-45727.6" - wire $0\core_terminate_o$next[0:0]$2628 - attribute \src "libresoc.v:42599.3-42600.49" - wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:45532.3-45558.6" - wire width 2 $0\counter$next[1:0]$2605 - attribute \src "libresoc.v:42601.3-42602.31" - wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:46017.3-46025.6" - wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2687 - attribute \src "libresoc.v:42535.3-42536.57" - wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:45998.3-46006.6" - wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2681 - attribute \src "libresoc.v:42537.3-42538.49" - wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46036.3-46044.6" - wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2693 - attribute \src "libresoc.v:42533.3-42534.49" - wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46085.3-46093.6" - wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2700 - attribute \src "libresoc.v:42531.3-42532.49" - wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:45949.3-45957.6" - wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2674 - attribute \src "libresoc.v:42539.3-42540.55" - wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46104.3-46112.6" - wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2706 - attribute \src "libresoc.v:42529.3-42530.63" - wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46171.3-46179.6" - wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2719 - attribute \src "libresoc.v:42525.3-42526.57" - wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46123.3-46131.6" - wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2712 - attribute \src "libresoc.v:42527.3-42528.59" - wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46219.3-46227.6" - wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2726 - attribute \src "libresoc.v:42523.3-42524.63" - wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46238.3-46246.6" - wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2732 - attribute \src "libresoc.v:42521.3-42522.59" - wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45171.3-45179.6" - wire $0\dp_INT_ra_alu0_0$next[0:0]$2497 - attribute \src "libresoc.v:42597.3-42598.49" - wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45190.3-45198.6" - wire $0\dp_INT_ra_cr0_1$next[0:0]$2501 - attribute \src "libresoc.v:42595.3-42596.47" - wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45266.3-45274.6" - wire $0\dp_INT_ra_div0_5$next[0:0]$2525 - attribute \src "libresoc.v:42587.3-42588.49" - wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45323.3-45331.6" - wire $0\dp_INT_ra_ldst0_8$next[0:0]$2543 - attribute \src "libresoc.v:42581.3-42582.51" - wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45228.3-45236.6" - wire $0\dp_INT_ra_logical0_3$next[0:0]$2513 - attribute \src "libresoc.v:42591.3-42592.57" - wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45285.3-45293.6" - wire $0\dp_INT_ra_mul0_6$next[0:0]$2531 - attribute \src "libresoc.v:42585.3-42586.49" - wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45304.3-45312.6" - wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2537 - attribute \src "libresoc.v:42583.3-42584.59" - wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45247.3-45255.6" - wire $0\dp_INT_ra_spr0_4$next[0:0]$2519 - attribute \src "libresoc.v:42589.3-42590.49" - wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45209.3-45217.6" - wire $0\dp_INT_ra_trap0_2$next[0:0]$2507 - attribute \src "libresoc.v:42593.3-42594.51" - wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45342.3-45350.6" - wire $0\dp_INT_rb_alu0_0$next[0:0]$2549 - attribute \src "libresoc.v:42579.3-42580.49" - wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45361.3-45369.6" - wire $0\dp_INT_rb_cr0_1$next[0:0]$2553 - attribute \src "libresoc.v:42577.3-42578.47" - wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45418.3-45426.6" - wire $0\dp_INT_rb_div0_4$next[0:0]$2571 - attribute \src "libresoc.v:42571.3-42572.49" - wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45475.3-45483.6" - wire $0\dp_INT_rb_ldst0_7$next[0:0]$2589 - attribute \src "libresoc.v:42565.3-42566.51" - wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45399.3-45407.6" - wire $0\dp_INT_rb_logical0_3$next[0:0]$2565 - attribute \src "libresoc.v:42573.3-42574.57" - wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45437.3-45445.6" - wire $0\dp_INT_rb_mul0_5$next[0:0]$2577 - attribute \src "libresoc.v:42569.3-42570.49" - wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45456.3-45464.6" - wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2583 - attribute \src "libresoc.v:42567.3-42568.59" - wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45380.3-45388.6" - wire $0\dp_INT_rb_trap0_2$next[0:0]$2559 - attribute \src "libresoc.v:42575.3-42576.51" - wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45513.3-45521.6" - wire $0\dp_INT_rc_ldst0_1$next[0:0]$2599 - attribute \src "libresoc.v:42561.3-42562.51" - wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45494.3-45502.6" - wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2595 - attribute \src "libresoc.v:42563.3-42564.59" - wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46286.3-46294.6" - wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2739 - attribute \src "libresoc.v:42519.3-42520.53" - wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45814.3-45822.6" - wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2652 - attribute \src "libresoc.v:42547.3-42548.57" - wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45881.3-45889.6" - wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2663 - attribute \src "libresoc.v:42543.3-42544.67" - wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45862.3-45870.6" - wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2659 - attribute \src "libresoc.v:42545.3-42546.57" - wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:45930.3-45938.6" - wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2668 - attribute \src "libresoc.v:42541.3-42542.57" - wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45559.3-45567.6" - wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2611 - attribute \src "libresoc.v:42559.3-42560.57" - wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45728.3-45736.6" - wire $0\dp_XER_xer_so_div0_3$next[0:0]$2633 - attribute \src "libresoc.v:42553.3-42554.57" - wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45669.3-45677.6" - wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2618 - attribute \src "libresoc.v:42557.3-42558.65" - wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45747.3-45755.6" - wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2639 - attribute \src "libresoc.v:42551.3-42552.57" - wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45795.3-45803.6" - wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2646 - attribute \src "libresoc.v:42549.3-42550.67" - wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45688.3-45696.6" - wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2624 - attribute \src "libresoc.v:42555.3-42556.57" - wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46806.3-46834.6" - wire $0\fus_cu_issue_i$11[0:0]$2808 - attribute \src "libresoc.v:47203.3-47231.6" - wire $0\fus_cu_issue_i$14[0:0]$2870 - attribute \src "libresoc.v:47567.3-47595.6" - wire $0\fus_cu_issue_i$17[0:0]$2904 - attribute \src "libresoc.v:48063.3-48091.6" - wire $0\fus_cu_issue_i$20[0:0]$2929 - attribute \src "libresoc.v:43390.3-43418.6" - wire $0\fus_cu_issue_i$23[0:0]$2396 - attribute \src "libresoc.v:43886.3-43914.6" - wire $0\fus_cu_issue_i$26[0:0]$2421 - attribute \src "libresoc.v:44208.3-44236.6" - wire $0\fus_cu_issue_i$29[0:0]$2440 - attribute \src "libresoc.v:44675.3-44703.6" - wire $0\fus_cu_issue_i$32[0:0]$2464 - attribute \src "libresoc.v:45113.3-45141.6" - wire $0\fus_cu_issue_i$35[0:0]$2487 - attribute \src "libresoc.v:46598.3-46626.6" - wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46844.3-46872.6" - wire width 6 $0\fus_cu_rdmaskn_i$13[5:0]$2816 - attribute \src "libresoc.v:47241.3-47269.6" - wire width 3 $0\fus_cu_rdmaskn_i$16[2:0]$2878 - attribute \src "libresoc.v:47596.3-47624.6" - wire width 4 $0\fus_cu_rdmaskn_i$19[3:0]$2909 - attribute \src "libresoc.v:48092.3-48120.6" - wire width 3 $0\fus_cu_rdmaskn_i$22[2:0]$2934 - attribute \src "libresoc.v:43419.3-43447.6" - wire width 6 $0\fus_cu_rdmaskn_i$25[5:0]$2401 - attribute \src "libresoc.v:43915.3-43943.6" - wire width 3 $0\fus_cu_rdmaskn_i$28[2:0]$2426 - attribute \src "libresoc.v:44237.3-44265.6" - wire width 3 $0\fus_cu_rdmaskn_i$31[2:0]$2445 - attribute \src "libresoc.v:44704.3-44732.6" - wire width 5 $0\fus_cu_rdmaskn_i$34[4:0]$2469 - attribute \src "libresoc.v:45142.3-45170.6" - wire width 3 $0\fus_cu_rdmaskn_i$37[2:0]$2492 - attribute \src "libresoc.v:46636.3-46664.6" - wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46513.3-46541.6" - wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45823.3-45851.6" - wire width 12 $0\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46343.3-46371.6" - wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46560.3-46588.6" - wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45766.3-45794.6" - wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46142.3-46170.6" - wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46257.3-46285.6" - wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46428.3-46456.6" - wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46475.3-46503.6" - wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46055.3-46084.6" - wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46055.3-46084.6" - wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46390.3-46418.6" - wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45968.3-45997.6" - wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45968.3-45997.6" - wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46305.3-46333.6" - wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46190.3-46218.6" - wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46891.3-46919.6" - wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46976.3-47004.6" - wire width 12 $0\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:47061.3-47090.6" - wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47061.3-47090.6" - wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47014.3-47042.6" - wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46929.3-46957.6" - wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47156.3-47184.6" - wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47118.3-47146.6" - wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46721.3-46749.6" - wire width 12 $0\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46768.3-46796.6" - wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46674.3-46702.6" - wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43828.3-43856.6" - wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43477.3-43505.6" - wire width 12 $0\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43506.3-43535.6" - wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43506.3-43535.6" - wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43654.3-43682.6" - wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43857.3-43885.6" - wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43448.3-43476.6" - wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43596.3-43624.6" - wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43683.3-43711.6" - wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43770.3-43798.6" - wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43799.3-43827.6" - wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43566.3-43595.6" - wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43566.3-43595.6" - wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43741.3-43769.6" - wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43536.3-43565.6" - wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43536.3-43565.6" - wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43712.3-43740.6" - wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43625.3-43653.6" - wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48005.3-48033.6" - wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47654.3-47682.6" - wire width 12 $0\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47683.3-47712.6" - wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47683.3-47712.6" - wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47831.3-47859.6" - wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48034.3-48062.6" - wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47625.3-47653.6" - wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47773.3-47801.6" - wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47860.3-47888.6" - wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47947.3-47975.6" - wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47976.3-48004.6" - wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47918.3-47946.6" - wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47889.3-47917.6" - wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47802.3-47830.6" - wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43973.3-44001.6" - wire width 12 $0\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44179.3-44207.6" - wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43944.3-43972.6" - wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44121.3-44149.6" - wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44150.3-44178.6" - wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44092.3-44120.6" - wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44295.3-44323.6" - wire width 12 $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44324.3-44353.6" - wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44324.3-44353.6" - wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44472.3-44500.6" - wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44530.3-44558.6" - wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44646.3-44674.6" - wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44266.3-44294.6" - wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44443.3-44471.6" - wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44588.3-44616.6" - wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44617.3-44645.6" - wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44384.3-44413.6" - wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44384.3-44413.6" - wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44501.3-44529.6" - wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44559.3-44587.6" - wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44354.3-44383.6" - wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44354.3-44383.6" - wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44414.3-44442.6" - wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48150.3-48178.6" - wire width 12 $0\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:43332.3-43360.6" - wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48121.3-48149.6" - wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43361.3-43389.6" - wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47422.3-47450.6" - wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47326.3-47354.6" - wire width 12 $0\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47364.3-47392.6" - wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47279.3-47307.6" - wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47451.3-47479.6" - wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47538.3-47566.6" - wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47393.3-47421.6" - wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47509.3-47537.6" - wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47480.3-47508.6" - wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:44997.3-45025.6" - wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44968.3-44996.6" - wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44762.3-44790.6" - wire width 12 $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44791.3-44820.6" - wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44791.3-44820.6" - wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45084.3-45112.6" - wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44733.3-44761.6" - wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44910.3-44938.6" - wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44939.3-44967.6" - wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45055.3-45083.6" - wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44880.3-44909.6" - wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44880.3-44909.6" - wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44850.3-44879.6" - wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44850.3-44879.6" - wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45026.3-45054.6" - wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44821.3-44849.6" - wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45199.3-45208.6" - wire width 64 $0\fus_src1_i$40[63:0]$2504 - attribute \src "libresoc.v:45218.3-45227.6" - wire width 64 $0\fus_src1_i$43[63:0]$2510 - attribute \src "libresoc.v:45237.3-45246.6" - wire width 64 $0\fus_src1_i$46[63:0]$2516 - attribute \src "libresoc.v:45256.3-45265.6" - wire width 64 $0\fus_src1_i$49[63:0]$2522 - attribute \src "libresoc.v:45275.3-45284.6" - wire width 64 $0\fus_src1_i$52[63:0]$2528 - attribute \src "libresoc.v:45294.3-45303.6" - wire width 64 $0\fus_src1_i$55[63:0]$2534 - attribute \src "libresoc.v:45313.3-45322.6" - wire width 64 $0\fus_src1_i$58[63:0]$2540 - attribute \src "libresoc.v:45332.3-45341.6" - wire width 64 $0\fus_src1_i$61[63:0]$2546 - attribute \src "libresoc.v:46113.3-46122.6" - wire width 64 $0\fus_src1_i$84[63:0]$2709 - attribute \src "libresoc.v:45180.3-45189.6" - wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:45370.3-45379.6" - wire width 64 $0\fus_src2_i$62[63:0]$2556 - attribute \src "libresoc.v:45389.3-45398.6" - wire width 64 $0\fus_src2_i$63[63:0]$2562 - attribute \src "libresoc.v:45408.3-45417.6" - wire width 64 $0\fus_src2_i$64[63:0]$2568 - attribute \src "libresoc.v:45427.3-45436.6" - wire width 64 $0\fus_src2_i$65[63:0]$2574 - attribute \src "libresoc.v:45446.3-45455.6" - wire width 64 $0\fus_src2_i$66[63:0]$2580 - attribute \src "libresoc.v:45465.3-45474.6" - wire width 64 $0\fus_src2_i$67[63:0]$2586 - attribute \src "libresoc.v:45484.3-45493.6" - wire width 64 $0\fus_src2_i$68[63:0]$2592 - attribute \src "libresoc.v:46228.3-46237.6" - wire width 64 $0\fus_src2_i$87[63:0]$2729 - attribute \src "libresoc.v:46295.3-46304.6" - wire width 64 $0\fus_src2_i$89[63:0]$2742 - attribute \src "libresoc.v:45351.3-45360.6" - wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:45522.3-45531.6" - wire width 64 $0\fus_src3_i$69[63:0]$2602 - attribute \src "libresoc.v:45568.3-45577.6" - wire $0\fus_src3_i$70[0:0]$2614 - attribute \src "libresoc.v:45678.3-45687.6" - wire $0\fus_src3_i$71[0:0]$2621 - attribute \src "libresoc.v:45737.3-45746.6" - wire $0\fus_src3_i$72[0:0]$2636 - attribute \src "libresoc.v:45756.3-45765.6" - wire $0\fus_src3_i$73[0:0]$2642 - attribute \src "libresoc.v:45958.3-45967.6" - wire width 32 $0\fus_src3_i$77[31:0]$2677 - attribute \src "libresoc.v:46026.3-46035.6" - wire width 4 $0\fus_src3_i$81[3:0]$2690 - attribute \src "libresoc.v:46132.3-46141.6" - wire width 64 $0\fus_src3_i$85[63:0]$2715 - attribute \src "libresoc.v:46180.3-46189.6" - wire width 64 $0\fus_src3_i$86[63:0]$2722 - attribute \src "libresoc.v:45503.3-45512.6" - wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:45804.3-45813.6" - wire $0\fus_src4_i$74[0:0]$2649 - attribute \src "libresoc.v:45852.3-45861.6" - wire width 2 $0\fus_src4_i$75[1:0]$2656 - attribute \src "libresoc.v:46007.3-46016.6" - wire width 4 $0\fus_src4_i$78[3:0]$2684 - attribute \src "libresoc.v:46247.3-46256.6" - wire width 64 $0\fus_src4_i$88[63:0]$2735 - attribute \src "libresoc.v:45697.3-45706.6" - wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:45939.3-45948.6" - wire width 2 $0\fus_src5_i$76[1:0]$2671 - attribute \src "libresoc.v:46045.3-46054.6" - wire width 4 $0\fus_src5_i$82[3:0]$2696 - attribute \src "libresoc.v:45920.3-45929.6" - wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:46094.3-46103.6" - wire width 4 $0\fus_src6_i$83[3:0]$2703 - attribute \src "libresoc.v:45871.3-45880.6" - wire width 2 $0\fus_src6_i[1:0] - attribute \src "libresoc.v:35933.7-35933.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:46381.3-46389.6" - wire $0\wr_pick_dly$1000$next[0:0]$2753 - attribute \src "libresoc.v:42513.3-42514.51" - wire $0\wr_pick_dly$1000[0:0]$2347 - attribute \src "libresoc.v:41343.7-41343.32" - wire $0\wr_pick_dly$1000[0:0]$2985 - attribute \src "libresoc.v:46419.3-46427.6" - wire $0\wr_pick_dly$1021$next[0:0]$2757 - attribute \src "libresoc.v:42511.3-42512.51" - wire $0\wr_pick_dly$1021[0:0]$2345 - attribute \src "libresoc.v:41347.7-41347.32" - wire $0\wr_pick_dly$1021[0:0]$2987 - attribute \src "libresoc.v:46457.3-46465.6" - wire $0\wr_pick_dly$1039$next[0:0]$2761 - attribute \src "libresoc.v:42509.3-42510.51" - wire $0\wr_pick_dly$1039[0:0]$2343 - attribute \src "libresoc.v:41351.7-41351.32" - wire $0\wr_pick_dly$1039[0:0]$2989 - attribute \src "libresoc.v:46466.3-46474.6" - wire $0\wr_pick_dly$1061$next[0:0]$2764 - attribute \src "libresoc.v:42507.3-42508.51" - wire $0\wr_pick_dly$1061[0:0]$2341 - attribute \src "libresoc.v:41355.7-41355.32" - wire $0\wr_pick_dly$1061[0:0]$2991 - attribute \src "libresoc.v:46504.3-46512.6" - wire $0\wr_pick_dly$1081$next[0:0]$2768 - attribute \src "libresoc.v:42505.3-42506.51" - wire $0\wr_pick_dly$1081[0:0]$2339 - attribute \src "libresoc.v:41359.7-41359.32" - wire $0\wr_pick_dly$1081[0:0]$2993 - attribute \src "libresoc.v:46542.3-46550.6" - wire $0\wr_pick_dly$1101$next[0:0]$2772 - attribute \src "libresoc.v:42503.3-42504.51" - wire $0\wr_pick_dly$1101[0:0]$2337 - attribute \src "libresoc.v:41363.7-41363.32" - wire $0\wr_pick_dly$1101[0:0]$2995 - attribute \src "libresoc.v:46551.3-46559.6" - wire $0\wr_pick_dly$1120$next[0:0]$2775 - attribute \src "libresoc.v:42501.3-42502.51" - wire $0\wr_pick_dly$1120[0:0]$2335 - attribute \src "libresoc.v:41367.7-41367.32" - wire $0\wr_pick_dly$1120[0:0]$2997 - attribute \src "libresoc.v:46589.3-46597.6" - wire $0\wr_pick_dly$1138$next[0:0]$2779 - attribute \src "libresoc.v:42499.3-42500.51" - wire $0\wr_pick_dly$1138[0:0]$2333 - attribute \src "libresoc.v:41371.7-41371.32" - wire $0\wr_pick_dly$1138[0:0]$2999 - attribute \src "libresoc.v:46627.3-46635.6" - wire $0\wr_pick_dly$1211$next[0:0]$2783 - attribute \src "libresoc.v:42497.3-42498.51" - wire $0\wr_pick_dly$1211[0:0]$2331 - attribute \src "libresoc.v:41375.7-41375.32" - wire $0\wr_pick_dly$1211[0:0]$3001 - attribute \src "libresoc.v:46665.3-46673.6" - wire $0\wr_pick_dly$1239$next[0:0]$2787 - attribute \src "libresoc.v:42495.3-42496.51" - wire $0\wr_pick_dly$1239[0:0]$2329 - attribute \src "libresoc.v:41379.7-41379.32" - wire $0\wr_pick_dly$1239[0:0]$3003 - attribute \src "libresoc.v:46703.3-46711.6" - wire $0\wr_pick_dly$1259$next[0:0]$2791 - attribute \src "libresoc.v:42493.3-42494.51" - wire $0\wr_pick_dly$1259[0:0]$2327 - attribute \src "libresoc.v:41383.7-41383.32" - wire $0\wr_pick_dly$1259[0:0]$3005 - attribute \src "libresoc.v:46712.3-46720.6" - wire $0\wr_pick_dly$1279$next[0:0]$2794 - attribute \src "libresoc.v:42491.3-42492.51" - wire $0\wr_pick_dly$1279[0:0]$2325 - attribute \src "libresoc.v:41387.7-41387.32" - wire $0\wr_pick_dly$1279[0:0]$3007 - attribute \src "libresoc.v:46750.3-46758.6" - wire $0\wr_pick_dly$1299$next[0:0]$2798 - attribute \src "libresoc.v:42489.3-42490.51" - wire $0\wr_pick_dly$1299[0:0]$2323 - attribute \src "libresoc.v:41391.7-41391.32" - wire $0\wr_pick_dly$1299[0:0]$3009 - attribute \src "libresoc.v:46759.3-46767.6" - wire $0\wr_pick_dly$1319$next[0:0]$2801 - attribute \src "libresoc.v:42487.3-42488.51" - wire $0\wr_pick_dly$1319[0:0]$2321 - attribute \src "libresoc.v:41395.7-41395.32" - wire $0\wr_pick_dly$1319[0:0]$3011 - attribute \src "libresoc.v:46797.3-46805.6" - wire $0\wr_pick_dly$1339$next[0:0]$2805 - attribute \src "libresoc.v:42485.3-42486.51" - wire $0\wr_pick_dly$1339[0:0]$2319 - attribute \src "libresoc.v:41399.7-41399.32" - wire $0\wr_pick_dly$1339[0:0]$3013 - attribute \src "libresoc.v:46835.3-46843.6" - wire $0\wr_pick_dly$1386$next[0:0]$2813 - attribute \src "libresoc.v:42483.3-42484.51" - wire $0\wr_pick_dly$1386[0:0]$2317 - attribute \src "libresoc.v:41403.7-41403.32" - wire $0\wr_pick_dly$1386[0:0]$3015 - attribute \src "libresoc.v:46873.3-46881.6" - wire $0\wr_pick_dly$1402$next[0:0]$2821 - attribute \src "libresoc.v:42481.3-42482.51" - wire $0\wr_pick_dly$1402[0:0]$2315 - attribute \src "libresoc.v:41407.7-41407.32" - wire $0\wr_pick_dly$1402[0:0]$3017 - attribute \src "libresoc.v:46882.3-46890.6" - wire $0\wr_pick_dly$1418$next[0:0]$2824 - attribute \src "libresoc.v:42479.3-42480.51" - wire $0\wr_pick_dly$1418[0:0]$2313 - attribute \src "libresoc.v:41411.7-41411.32" - wire $0\wr_pick_dly$1418[0:0]$3019 - attribute \src "libresoc.v:46920.3-46928.6" - wire $0\wr_pick_dly$1452$next[0:0]$2828 - attribute \src "libresoc.v:42477.3-42478.51" - wire $0\wr_pick_dly$1452[0:0]$2311 - attribute \src "libresoc.v:41415.7-41415.32" - wire $0\wr_pick_dly$1452[0:0]$3021 - attribute \src "libresoc.v:46958.3-46966.6" - wire $0\wr_pick_dly$1468$next[0:0]$2832 - attribute \src "libresoc.v:42475.3-42476.51" - wire $0\wr_pick_dly$1468[0:0]$2309 - attribute \src "libresoc.v:41419.7-41419.32" - wire $0\wr_pick_dly$1468[0:0]$3023 - attribute \src "libresoc.v:46967.3-46975.6" - wire $0\wr_pick_dly$1484$next[0:0]$2835 - attribute \src "libresoc.v:42473.3-42474.51" - wire $0\wr_pick_dly$1484[0:0]$2307 - attribute \src "libresoc.v:41423.7-41423.32" - wire $0\wr_pick_dly$1484[0:0]$3025 - attribute \src "libresoc.v:47005.3-47013.6" - wire $0\wr_pick_dly$1500$next[0:0]$2839 - attribute \src "libresoc.v:42471.3-42472.51" - wire $0\wr_pick_dly$1500[0:0]$2305 - attribute \src "libresoc.v:41427.7-41427.32" - wire $0\wr_pick_dly$1500[0:0]$3027 - attribute \src "libresoc.v:47043.3-47051.6" - wire $0\wr_pick_dly$1536$next[0:0]$2843 - attribute \src "libresoc.v:42469.3-42470.51" - wire $0\wr_pick_dly$1536[0:0]$2303 - attribute \src "libresoc.v:41431.7-41431.32" - wire $0\wr_pick_dly$1536[0:0]$3029 - attribute \src "libresoc.v:47052.3-47060.6" - wire $0\wr_pick_dly$1552$next[0:0]$2846 - attribute \src "libresoc.v:42467.3-42468.51" - wire $0\wr_pick_dly$1552[0:0]$2301 - attribute \src "libresoc.v:41435.7-41435.32" - wire $0\wr_pick_dly$1552[0:0]$3031 - attribute \src "libresoc.v:47091.3-47099.6" - wire $0\wr_pick_dly$1568$next[0:0]$2850 - attribute \src "libresoc.v:42465.3-42466.51" - wire $0\wr_pick_dly$1568[0:0]$2299 - attribute \src "libresoc.v:41439.7-41439.32" - wire $0\wr_pick_dly$1568[0:0]$3033 - attribute \src "libresoc.v:47100.3-47108.6" - wire $0\wr_pick_dly$1584$next[0:0]$2853 - attribute \src "libresoc.v:42463.3-42464.51" - wire $0\wr_pick_dly$1584[0:0]$2297 - attribute \src "libresoc.v:41443.7-41443.32" - wire $0\wr_pick_dly$1584[0:0]$3035 - attribute \src "libresoc.v:47109.3-47117.6" - wire $0\wr_pick_dly$1626$next[0:0]$2856 - attribute \src "libresoc.v:42461.3-42462.51" - wire $0\wr_pick_dly$1626[0:0]$2295 - attribute \src "libresoc.v:41447.7-41447.32" - wire $0\wr_pick_dly$1626[0:0]$3037 - attribute \src "libresoc.v:47147.3-47155.6" - wire $0\wr_pick_dly$1645$next[0:0]$2860 - attribute \src "libresoc.v:42459.3-42460.51" - wire $0\wr_pick_dly$1645[0:0]$2293 - attribute \src "libresoc.v:41451.7-41451.32" - wire $0\wr_pick_dly$1645[0:0]$3039 - attribute \src "libresoc.v:47185.3-47193.6" - wire $0\wr_pick_dly$1661$next[0:0]$2864 - attribute \src "libresoc.v:42457.3-42458.51" - wire $0\wr_pick_dly$1661[0:0]$2291 - attribute \src "libresoc.v:41455.7-41455.32" - wire $0\wr_pick_dly$1661[0:0]$3041 - attribute \src "libresoc.v:47194.3-47202.6" - wire $0\wr_pick_dly$1677$next[0:0]$2867 - attribute \src "libresoc.v:42455.3-42456.51" - wire $0\wr_pick_dly$1677[0:0]$2289 - attribute \src "libresoc.v:41459.7-41459.32" - wire $0\wr_pick_dly$1677[0:0]$3043 - attribute \src "libresoc.v:47232.3-47240.6" - wire $0\wr_pick_dly$1693$next[0:0]$2875 - attribute \src "libresoc.v:42453.3-42454.51" - wire $0\wr_pick_dly$1693[0:0]$2287 - attribute \src "libresoc.v:41463.7-41463.32" - wire $0\wr_pick_dly$1693[0:0]$3045 - attribute \src "libresoc.v:47270.3-47278.6" - wire $0\wr_pick_dly$1737$next[0:0]$2883 - attribute \src "libresoc.v:42451.3-42452.51" - wire $0\wr_pick_dly$1737[0:0]$2285 - attribute \src "libresoc.v:41467.7-41467.32" - wire $0\wr_pick_dly$1737[0:0]$3047 - attribute \src "libresoc.v:47308.3-47316.6" - wire $0\wr_pick_dly$1753$next[0:0]$2887 - attribute \src "libresoc.v:42449.3-42450.51" - wire $0\wr_pick_dly$1753[0:0]$2283 - attribute \src "libresoc.v:41471.7-41471.32" - wire $0\wr_pick_dly$1753[0:0]$3049 - attribute \src "libresoc.v:47317.3-47325.6" - wire $0\wr_pick_dly$1777$next[0:0]$2890 - attribute \src "libresoc.v:42447.3-42448.51" - wire $0\wr_pick_dly$1777[0:0]$2281 - attribute \src "libresoc.v:41475.7-41475.32" - wire $0\wr_pick_dly$1777[0:0]$3051 - attribute \src "libresoc.v:47355.3-47363.6" - wire $0\wr_pick_dly$1797$next[0:0]$2894 - attribute \src "libresoc.v:42445.3-42446.51" - wire $0\wr_pick_dly$1797[0:0]$2279 - attribute \src "libresoc.v:41479.7-41479.32" - wire $0\wr_pick_dly$1797[0:0]$3053 - attribute \src "libresoc.v:46372.3-46380.6" - wire $0\wr_pick_dly$981$next[0:0]$2750 - attribute \src "libresoc.v:42515.3-42516.49" - wire $0\wr_pick_dly$981[0:0]$2349 - attribute \src "libresoc.v:41483.7-41483.31" - wire $0\wr_pick_dly$981[0:0]$3055 - attribute \src "libresoc.v:46334.3-46342.6" - wire $0\wr_pick_dly$next[0:0]$2746 - attribute \src "libresoc.v:42517.3-42518.39" - wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:45707.3-45727.6" - wire $1\core_terminate_o$next[0:0]$2629 - attribute \src "libresoc.v:37965.7-37965.30" - wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:45532.3-45558.6" - wire width 2 $1\counter$next[1:0]$2606 - attribute \src "libresoc.v:37978.13-37978.27" - wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:46017.3-46025.6" - wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 - attribute \src "libresoc.v:39108.7-39108.34" - wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:45998.3-46006.6" - wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 - attribute \src "libresoc.v:39112.7-39112.30" - wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46036.3-46044.6" - wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 - attribute \src "libresoc.v:39116.7-39116.30" - wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46085.3-46093.6" - wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 - attribute \src "libresoc.v:39120.7-39120.30" - wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:45949.3-45957.6" - wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 - attribute \src "libresoc.v:39124.7-39124.33" - wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46104.3-46112.6" - wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 - attribute \src "libresoc.v:39128.7-39128.37" - wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46171.3-46179.6" - wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 - attribute \src "libresoc.v:39132.7-39132.34" - wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46123.3-46131.6" - wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 - attribute \src "libresoc.v:39136.7-39136.35" - wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46219.3-46227.6" - wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 - attribute \src "libresoc.v:39140.7-39140.37" - wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46238.3-46246.6" - wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 - attribute \src "libresoc.v:39144.7-39144.35" - wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45171.3-45179.6" - wire $1\dp_INT_ra_alu0_0$next[0:0]$2498 - attribute \src "libresoc.v:39148.7-39148.30" - wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45190.3-45198.6" - wire $1\dp_INT_ra_cr0_1$next[0:0]$2502 - attribute \src "libresoc.v:39152.7-39152.29" - wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45266.3-45274.6" - wire $1\dp_INT_ra_div0_5$next[0:0]$2526 - attribute \src "libresoc.v:39156.7-39156.30" - wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45323.3-45331.6" - wire $1\dp_INT_ra_ldst0_8$next[0:0]$2544 - attribute \src "libresoc.v:39160.7-39160.31" - wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45228.3-45236.6" - wire $1\dp_INT_ra_logical0_3$next[0:0]$2514 - attribute \src "libresoc.v:39164.7-39164.34" - wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45285.3-45293.6" - wire $1\dp_INT_ra_mul0_6$next[0:0]$2532 - attribute \src "libresoc.v:39168.7-39168.30" - wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45304.3-45312.6" - wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 - attribute \src "libresoc.v:39172.7-39172.35" - wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45247.3-45255.6" - wire $1\dp_INT_ra_spr0_4$next[0:0]$2520 - attribute \src "libresoc.v:39176.7-39176.30" - wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45209.3-45217.6" - wire $1\dp_INT_ra_trap0_2$next[0:0]$2508 - attribute \src "libresoc.v:39180.7-39180.31" - wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45342.3-45350.6" - wire $1\dp_INT_rb_alu0_0$next[0:0]$2550 - attribute \src "libresoc.v:39184.7-39184.30" - wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:45361.3-45369.6" - wire $1\dp_INT_rb_cr0_1$next[0:0]$2554 - attribute \src "libresoc.v:39188.7-39188.29" - wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:45418.3-45426.6" - wire $1\dp_INT_rb_div0_4$next[0:0]$2572 - attribute \src "libresoc.v:39192.7-39192.30" - wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:45475.3-45483.6" - wire $1\dp_INT_rb_ldst0_7$next[0:0]$2590 - attribute \src "libresoc.v:39196.7-39196.31" - wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:45399.3-45407.6" - wire $1\dp_INT_rb_logical0_3$next[0:0]$2566 - attribute \src "libresoc.v:39200.7-39200.34" - wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:45437.3-45445.6" - wire $1\dp_INT_rb_mul0_5$next[0:0]$2578 - attribute \src "libresoc.v:39204.7-39204.30" - wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:45456.3-45464.6" - wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 - attribute \src "libresoc.v:39208.7-39208.35" - wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:45380.3-45388.6" - wire $1\dp_INT_rb_trap0_2$next[0:0]$2560 - attribute \src "libresoc.v:39212.7-39212.31" - wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:45513.3-45521.6" - wire $1\dp_INT_rc_ldst0_1$next[0:0]$2600 - attribute \src "libresoc.v:39216.7-39216.31" - wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:45494.3-45502.6" - wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 - attribute \src "libresoc.v:39220.7-39220.35" - wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46286.3-46294.6" - wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 - attribute \src "libresoc.v:39224.7-39224.32" - wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:45814.3-45822.6" - wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 - attribute \src "libresoc.v:39228.7-39228.34" - wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:45881.3-45889.6" - wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 - attribute \src "libresoc.v:39232.7-39232.39" - wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:45862.3-45870.6" - wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 - attribute \src "libresoc.v:39236.7-39236.34" - wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:45930.3-45938.6" - wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 - attribute \src "libresoc.v:39240.7-39240.34" - wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:45559.3-45567.6" - wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 - attribute \src "libresoc.v:39244.7-39244.34" - wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:45728.3-45736.6" - wire $1\dp_XER_xer_so_div0_3$next[0:0]$2634 - attribute \src "libresoc.v:39248.7-39248.34" - wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:45669.3-45677.6" - wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 - attribute \src "libresoc.v:39252.7-39252.38" - wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:45747.3-45755.6" - wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 - attribute \src "libresoc.v:39256.7-39256.34" - wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:45795.3-45803.6" - wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 - attribute \src "libresoc.v:39260.7-39260.39" - wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:45688.3-45696.6" - wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 - attribute \src "libresoc.v:39264.7-39264.34" - wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:46806.3-46834.6" - wire $1\fus_cu_issue_i$11[0:0]$2809 - attribute \src "libresoc.v:47203.3-47231.6" - wire $1\fus_cu_issue_i$14[0:0]$2871 - attribute \src "libresoc.v:47567.3-47595.6" - wire $1\fus_cu_issue_i$17[0:0]$2905 - attribute \src "libresoc.v:48063.3-48091.6" - wire $1\fus_cu_issue_i$20[0:0]$2930 - attribute \src "libresoc.v:43390.3-43418.6" - wire $1\fus_cu_issue_i$23[0:0]$2397 - attribute \src "libresoc.v:43886.3-43914.6" - wire $1\fus_cu_issue_i$26[0:0]$2422 - attribute \src "libresoc.v:44208.3-44236.6" - wire $1\fus_cu_issue_i$29[0:0]$2441 - attribute \src "libresoc.v:44675.3-44703.6" - wire $1\fus_cu_issue_i$32[0:0]$2465 - attribute \src "libresoc.v:45113.3-45141.6" - wire $1\fus_cu_issue_i$35[0:0]$2488 - attribute \src "libresoc.v:46598.3-46626.6" - wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46844.3-46872.6" - wire width 6 $1\fus_cu_rdmaskn_i$13[5:0]$2817 - attribute \src "libresoc.v:47241.3-47269.6" - wire width 3 $1\fus_cu_rdmaskn_i$16[2:0]$2879 - attribute \src "libresoc.v:47596.3-47624.6" - wire width 4 $1\fus_cu_rdmaskn_i$19[3:0]$2910 - attribute \src "libresoc.v:48092.3-48120.6" - wire width 3 $1\fus_cu_rdmaskn_i$22[2:0]$2935 - attribute \src "libresoc.v:43419.3-43447.6" - wire width 6 $1\fus_cu_rdmaskn_i$25[5:0]$2402 - attribute \src "libresoc.v:43915.3-43943.6" - wire width 3 $1\fus_cu_rdmaskn_i$28[2:0]$2427 - attribute \src "libresoc.v:44237.3-44265.6" - wire width 3 $1\fus_cu_rdmaskn_i$31[2:0]$2446 - attribute \src "libresoc.v:44704.3-44732.6" - wire width 5 $1\fus_cu_rdmaskn_i$34[4:0]$2470 - attribute \src "libresoc.v:45142.3-45170.6" - wire width 3 $1\fus_cu_rdmaskn_i$37[2:0]$2493 - attribute \src "libresoc.v:46636.3-46664.6" - wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46513.3-46541.6" - wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45823.3-45851.6" - wire width 12 $1\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46343.3-46371.6" - wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46560.3-46588.6" - wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45766.3-45794.6" - wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46142.3-46170.6" - wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46257.3-46285.6" - wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46428.3-46456.6" - wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46475.3-46503.6" - wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46055.3-46084.6" - wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46055.3-46084.6" - wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46390.3-46418.6" - wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45968.3-45997.6" - wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45968.3-45997.6" - wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46305.3-46333.6" - wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src 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"libresoc.v:46768.3-46796.6" - wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46674.3-46702.6" - wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43828.3-43856.6" - wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43477.3-43505.6" - wire width 12 $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43506.3-43535.6" - wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43506.3-43535.6" - wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43654.3-43682.6" - wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43857.3-43885.6" - wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43448.3-43476.6" - wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43596.3-43624.6" - wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src 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attribute \src "libresoc.v:47654.3-47682.6" - wire width 12 $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47683.3-47712.6" - wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47683.3-47712.6" - wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47831.3-47859.6" - wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48034.3-48062.6" - wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47625.3-47653.6" - wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47773.3-47801.6" - wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47860.3-47888.6" - wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47947.3-47975.6" - wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47976.3-48004.6" - wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47918.3-47946.6" - wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47889.3-47917.6" - wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47802.3-47830.6" - wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43973.3-44001.6" - wire width 12 $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44179.3-44207.6" - wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43944.3-43972.6" - wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44121.3-44149.6" - wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44150.3-44178.6" - wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44092.3-44120.6" - wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44295.3-44323.6" - wire width 12 $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src 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attribute \src "libresoc.v:44384.3-44413.6" - wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44501.3-44529.6" - wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44559.3-44587.6" - wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44354.3-44383.6" - wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44354.3-44383.6" - wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44414.3-44442.6" - wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48150.3-48178.6" - wire width 12 $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:43332.3-43360.6" - wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48121.3-48149.6" - wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43361.3-43389.6" - wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src 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"libresoc.v:46228.3-46237.6" - wire width 64 $1\fus_src2_i$87[63:0]$2730 - attribute \src "libresoc.v:46295.3-46304.6" - wire width 64 $1\fus_src2_i$89[63:0]$2743 - attribute \src "libresoc.v:45351.3-45360.6" - wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45522.3-45531.6" - wire width 64 $1\fus_src3_i$69[63:0]$2603 - attribute \src "libresoc.v:45568.3-45577.6" - wire $1\fus_src3_i$70[0:0]$2615 - attribute \src "libresoc.v:45678.3-45687.6" - wire $1\fus_src3_i$71[0:0]$2622 - attribute \src "libresoc.v:45737.3-45746.6" - wire $1\fus_src3_i$72[0:0]$2637 - attribute \src "libresoc.v:45756.3-45765.6" - wire $1\fus_src3_i$73[0:0]$2643 - attribute \src "libresoc.v:45958.3-45967.6" - wire width 32 $1\fus_src3_i$77[31:0]$2678 - attribute \src "libresoc.v:46026.3-46035.6" - wire width 4 $1\fus_src3_i$81[3:0]$2691 - attribute \src "libresoc.v:46132.3-46141.6" - wire width 64 $1\fus_src3_i$85[63:0]$2716 - attribute \src "libresoc.v:46180.3-46189.6" - wire width 64 $1\fus_src3_i$86[63:0]$2723 - attribute \src "libresoc.v:45503.3-45512.6" - wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45804.3-45813.6" - wire $1\fus_src4_i$74[0:0]$2650 - attribute \src "libresoc.v:45852.3-45861.6" - wire width 2 $1\fus_src4_i$75[1:0]$2657 - attribute \src "libresoc.v:46007.3-46016.6" - wire width 4 $1\fus_src4_i$78[3:0]$2685 - attribute \src "libresoc.v:46247.3-46256.6" - wire width 64 $1\fus_src4_i$88[63:0]$2736 - attribute \src "libresoc.v:45697.3-45706.6" - wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:45939.3-45948.6" - wire width 2 $1\fus_src5_i$76[1:0]$2672 - attribute \src "libresoc.v:46045.3-46054.6" - wire width 4 $1\fus_src5_i$82[3:0]$2697 - attribute \src "libresoc.v:45920.3-45929.6" - wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46094.3-46103.6" - wire width 4 $1\fus_src6_i$83[3:0]$2704 - attribute \src "libresoc.v:45871.3-45880.6" - wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46381.3-46389.6" - wire $1\wr_pick_dly$1000$next[0:0]$2754 - attribute \src "libresoc.v:46419.3-46427.6" - wire $1\wr_pick_dly$1021$next[0:0]$2758 - attribute \src "libresoc.v:46457.3-46465.6" - wire $1\wr_pick_dly$1039$next[0:0]$2762 - attribute \src "libresoc.v:46466.3-46474.6" - wire $1\wr_pick_dly$1061$next[0:0]$2765 - attribute \src "libresoc.v:46504.3-46512.6" - wire $1\wr_pick_dly$1081$next[0:0]$2769 - attribute \src "libresoc.v:46542.3-46550.6" - wire $1\wr_pick_dly$1101$next[0:0]$2773 - attribute \src "libresoc.v:46551.3-46559.6" - wire $1\wr_pick_dly$1120$next[0:0]$2776 - attribute \src "libresoc.v:46589.3-46597.6" - wire $1\wr_pick_dly$1138$next[0:0]$2780 - attribute \src "libresoc.v:46627.3-46635.6" - wire $1\wr_pick_dly$1211$next[0:0]$2784 - attribute \src "libresoc.v:46665.3-46673.6" - wire $1\wr_pick_dly$1239$next[0:0]$2788 - attribute \src "libresoc.v:46703.3-46711.6" - wire $1\wr_pick_dly$1259$next[0:0]$2792 - attribute \src "libresoc.v:46712.3-46720.6" - wire $1\wr_pick_dly$1279$next[0:0]$2795 - attribute \src "libresoc.v:46750.3-46758.6" - wire $1\wr_pick_dly$1299$next[0:0]$2799 - attribute \src "libresoc.v:46759.3-46767.6" - wire $1\wr_pick_dly$1319$next[0:0]$2802 - attribute \src "libresoc.v:46797.3-46805.6" - wire $1\wr_pick_dly$1339$next[0:0]$2806 - attribute \src "libresoc.v:46835.3-46843.6" - wire $1\wr_pick_dly$1386$next[0:0]$2814 - attribute \src "libresoc.v:46873.3-46881.6" - wire $1\wr_pick_dly$1402$next[0:0]$2822 - attribute \src "libresoc.v:46882.3-46890.6" - wire $1\wr_pick_dly$1418$next[0:0]$2825 - attribute \src "libresoc.v:46920.3-46928.6" - wire $1\wr_pick_dly$1452$next[0:0]$2829 - attribute \src "libresoc.v:46958.3-46966.6" - wire $1\wr_pick_dly$1468$next[0:0]$2833 - attribute \src "libresoc.v:46967.3-46975.6" - wire $1\wr_pick_dly$1484$next[0:0]$2836 - attribute \src "libresoc.v:47005.3-47013.6" - wire $1\wr_pick_dly$1500$next[0:0]$2840 - attribute \src "libresoc.v:47043.3-47051.6" - wire $1\wr_pick_dly$1536$next[0:0]$2844 - attribute \src "libresoc.v:47052.3-47060.6" - wire $1\wr_pick_dly$1552$next[0:0]$2847 - attribute \src "libresoc.v:47091.3-47099.6" - wire $1\wr_pick_dly$1568$next[0:0]$2851 - attribute \src "libresoc.v:47100.3-47108.6" - wire $1\wr_pick_dly$1584$next[0:0]$2854 - attribute \src "libresoc.v:47109.3-47117.6" - wire $1\wr_pick_dly$1626$next[0:0]$2857 - attribute \src "libresoc.v:47147.3-47155.6" - wire $1\wr_pick_dly$1645$next[0:0]$2861 - attribute \src "libresoc.v:47185.3-47193.6" - wire $1\wr_pick_dly$1661$next[0:0]$2865 - attribute \src "libresoc.v:47194.3-47202.6" - wire $1\wr_pick_dly$1677$next[0:0]$2868 - attribute \src "libresoc.v:47232.3-47240.6" - wire $1\wr_pick_dly$1693$next[0:0]$2876 - attribute \src "libresoc.v:47270.3-47278.6" - wire $1\wr_pick_dly$1737$next[0:0]$2884 - attribute \src "libresoc.v:47308.3-47316.6" - wire $1\wr_pick_dly$1753$next[0:0]$2888 - attribute \src "libresoc.v:47317.3-47325.6" - wire $1\wr_pick_dly$1777$next[0:0]$2891 - attribute \src "libresoc.v:47355.3-47363.6" - wire $1\wr_pick_dly$1797$next[0:0]$2895 - attribute \src "libresoc.v:46372.3-46380.6" - wire $1\wr_pick_dly$981$next[0:0]$2751 - attribute \src "libresoc.v:46334.3-46342.6" - wire $1\wr_pick_dly$next[0:0]$2747 - attribute \src "libresoc.v:41341.7-41341.25" - wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:45707.3-45727.6" - wire $2\core_terminate_o$next[0:0]$2630 - attribute \src "libresoc.v:45578.3-45668.6" - wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:45532.3-45558.6" - wire width 2 $2\counter$next[1:0]$2607 - attribute \src "libresoc.v:46806.3-46834.6" - wire $2\fus_cu_issue_i$11[0:0]$2810 - attribute \src "libresoc.v:47203.3-47231.6" - wire $2\fus_cu_issue_i$14[0:0]$2872 - attribute \src "libresoc.v:47567.3-47595.6" - wire $2\fus_cu_issue_i$17[0:0]$2906 - attribute \src "libresoc.v:48063.3-48091.6" - wire $2\fus_cu_issue_i$20[0:0]$2931 - attribute \src "libresoc.v:43390.3-43418.6" - wire $2\fus_cu_issue_i$23[0:0]$2398 - attribute \src "libresoc.v:43886.3-43914.6" - wire $2\fus_cu_issue_i$26[0:0]$2423 - attribute \src "libresoc.v:44208.3-44236.6" - wire $2\fus_cu_issue_i$29[0:0]$2442 - attribute \src "libresoc.v:44675.3-44703.6" - wire $2\fus_cu_issue_i$32[0:0]$2466 - attribute \src "libresoc.v:45113.3-45141.6" - wire $2\fus_cu_issue_i$35[0:0]$2489 - attribute \src "libresoc.v:46598.3-46626.6" - wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46844.3-46872.6" - wire width 6 $2\fus_cu_rdmaskn_i$13[5:0]$2818 - attribute \src "libresoc.v:47241.3-47269.6" - wire width 3 $2\fus_cu_rdmaskn_i$16[2:0]$2880 - attribute \src "libresoc.v:47596.3-47624.6" - wire width 4 $2\fus_cu_rdmaskn_i$19[3:0]$2911 - attribute \src "libresoc.v:48092.3-48120.6" - wire width 3 $2\fus_cu_rdmaskn_i$22[2:0]$2936 - attribute \src "libresoc.v:43419.3-43447.6" - wire width 6 $2\fus_cu_rdmaskn_i$25[5:0]$2403 - attribute \src "libresoc.v:43915.3-43943.6" - wire width 3 $2\fus_cu_rdmaskn_i$28[2:0]$2428 - attribute \src "libresoc.v:44237.3-44265.6" - wire width 3 $2\fus_cu_rdmaskn_i$31[2:0]$2447 - attribute \src "libresoc.v:44704.3-44732.6" - wire width 5 $2\fus_cu_rdmaskn_i$34[4:0]$2471 - attribute \src "libresoc.v:45142.3-45170.6" - wire width 3 $2\fus_cu_rdmaskn_i$37[2:0]$2494 - attribute \src "libresoc.v:46636.3-46664.6" - wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46513.3-46541.6" - wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45823.3-45851.6" - wire width 12 $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46343.3-46371.6" - wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46560.3-46588.6" - wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:45766.3-45794.6" - wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46142.3-46170.6" - wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46257.3-46285.6" - wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46428.3-46456.6" - wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46475.3-46503.6" - wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46055.3-46084.6" - wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46055.3-46084.6" - wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46390.3-46418.6" - wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:45968.3-45997.6" - wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:45968.3-45997.6" - wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46305.3-46333.6" - wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46190.3-46218.6" - wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46891.3-46919.6" - wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46976.3-47004.6" - wire width 12 $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:47061.3-47090.6" - wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47061.3-47090.6" - wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47014.3-47042.6" - wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46929.3-46957.6" - wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47156.3-47184.6" - wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47118.3-47146.6" - wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:46721.3-46749.6" - wire width 12 $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46768.3-46796.6" - wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46674.3-46702.6" - wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:43828.3-43856.6" - wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43477.3-43505.6" - wire width 12 $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43506.3-43535.6" - wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:43506.3-43535.6" - wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43654.3-43682.6" - wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43857.3-43885.6" - wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43448.3-43476.6" - wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43596.3-43624.6" - wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43683.3-43711.6" - wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43770.3-43798.6" - wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43799.3-43827.6" - wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43566.3-43595.6" - wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:43566.3-43595.6" - wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43741.3-43769.6" - wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43536.3-43565.6" - wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:43536.3-43565.6" - wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43712.3-43740.6" - wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43625.3-43653.6" - wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:48005.3-48033.6" - wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:47654.3-47682.6" - wire width 12 $2\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47683.3-47712.6" - wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:47683.3-47712.6" - wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47831.3-47859.6" - wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48034.3-48062.6" - wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:47625.3-47653.6" - wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47773.3-47801.6" - wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47860.3-47888.6" - wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47947.3-47975.6" - wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47976.3-48004.6" - wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47918.3-47946.6" - wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47889.3-47917.6" - wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47802.3-47830.6" - wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43973.3-44001.6" - wire width 12 $2\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44179.3-44207.6" - wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43944.3-43972.6" - wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44121.3-44149.6" - wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44150.3-44178.6" - wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44092.3-44120.6" - wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44295.3-44323.6" - wire width 12 $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44324.3-44353.6" - wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44324.3-44353.6" - wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44472.3-44500.6" - wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44530.3-44558.6" - wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44646.3-44674.6" - wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44266.3-44294.6" - wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44443.3-44471.6" - wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44588.3-44616.6" - wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44617.3-44645.6" - wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44384.3-44413.6" - wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - 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attribute \src "libresoc.v:43915.3-43943.6" - wire width 3 $3\fus_cu_rdmaskn_i$28[2:0]$2429 - attribute \src "libresoc.v:44237.3-44265.6" - wire width 3 $3\fus_cu_rdmaskn_i$31[2:0]$2448 - attribute \src "libresoc.v:44704.3-44732.6" - wire width 5 $3\fus_cu_rdmaskn_i$34[4:0]$2472 - attribute \src "libresoc.v:45142.3-45170.6" - wire width 3 $3\fus_cu_rdmaskn_i$37[2:0]$2495 - attribute \src "libresoc.v:46636.3-46664.6" - wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46513.3-46541.6" - wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:45823.3-45851.6" - wire width 12 $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:45890.3-45919.6" - wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46343.3-46371.6" - wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src 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attribute \src "libresoc.v:46305.3-46333.6" - wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46190.3-46218.6" - wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46891.3-46919.6" - wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46976.3-47004.6" - wire width 12 $3\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:47061.3-47090.6" - wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47061.3-47090.6" - wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47014.3-47042.6" - wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:46929.3-46957.6" - wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47156.3-47184.6" - wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47118.3-47146.6" - wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src 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attribute \src "libresoc.v:47976.3-48004.6" - wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:47743.3-47772.6" - wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47918.3-47946.6" - wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:47713.3-47742.6" - wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47889.3-47917.6" - wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47802.3-47830.6" - wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:43973.3-44001.6" - wire width 12 $3\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44002.3-44031.6" - wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44179.3-44207.6" - wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:43944.3-43972.6" - wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44121.3-44149.6" - wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44150.3-44178.6" - wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44062.3-44091.6" - wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44032.3-44061.6" - wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44092.3-44120.6" - wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44295.3-44323.6" - wire width 12 $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44324.3-44353.6" - wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44324.3-44353.6" - wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44472.3-44500.6" - wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44530.3-44558.6" - wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44646.3-44674.6" - wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44266.3-44294.6" - wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44443.3-44471.6" - wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44588.3-44616.6" - wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44617.3-44645.6" - wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44384.3-44413.6" - wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:44384.3-44413.6" - wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44501.3-44529.6" - wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44559.3-44587.6" - wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44354.3-44383.6" - wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:44354.3-44383.6" - wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44414.3-44442.6" - wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:48150.3-48178.6" - wire width 12 $3\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:43332.3-43360.6" - wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:48121.3-48149.6" - wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43361.3-43389.6" - wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:47422.3-47450.6" - wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47326.3-47354.6" - wire width 12 $3\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47364.3-47392.6" - wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47279.3-47307.6" - wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47451.3-47479.6" - wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47538.3-47566.6" - wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47393.3-47421.6" - wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47509.3-47537.6" - wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47480.3-47508.6" - wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:44997.3-45025.6" - wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44968.3-44996.6" - wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44762.3-44790.6" - wire width 12 $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44791.3-44820.6" - wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:44791.3-44820.6" - wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45084.3-45112.6" - wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:44733.3-44761.6" - wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44910.3-44938.6" - wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44939.3-44967.6" - wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45055.3-45083.6" - wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:44880.3-44909.6" - wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:44880.3-44909.6" - wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44850.3-44879.6" - wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:44850.3-44879.6" - wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45026.3-45054.6" - wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:44821.3-44849.6" - wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:45532.3-45558.6" - wire width 2 $4\counter$next[1:0]$2609 - attribute \src "libresoc.v:45578.3-45668.6" - wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:45578.3-45668.6" - wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:41721.20-41721.109" - wire $and$libresoc.v:41721$1547_Y - attribute \src "libresoc.v:41722.20-41722.122" - wire $and$libresoc.v:41722$1548_Y - attribute \src "libresoc.v:41724.20-41724.122" - wire $and$libresoc.v:41724$1550_Y - attribute \src "libresoc.v:41725.20-41725.126" - wire $and$libresoc.v:41725$1551_Y - attribute \src "libresoc.v:41727.20-41727.110" - wire $and$libresoc.v:41727$1553_Y - attribute \src "libresoc.v:41728.20-41728.123" - wire $and$libresoc.v:41728$1554_Y - attribute \src "libresoc.v:41730.20-41730.122" - wire $and$libresoc.v:41730$1556_Y - attribute \src "libresoc.v:41731.20-41731.126" - wire $and$libresoc.v:41731$1557_Y - attribute \src "libresoc.v:41733.20-41733.110" - wire $and$libresoc.v:41733$1559_Y - attribute \src "libresoc.v:41734.20-41734.123" - wire $and$libresoc.v:41734$1560_Y - attribute \src "libresoc.v:41736.20-41736.123" - wire $and$libresoc.v:41736$1562_Y - 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$and$libresoc.v:41754$1580_Y - attribute \src "libresoc.v:41755.20-41755.126" - wire $and$libresoc.v:41755$1581_Y - attribute \src "libresoc.v:41757.20-41757.110" - wire $and$libresoc.v:41757$1583_Y - attribute \src "libresoc.v:41758.20-41758.123" - wire $and$libresoc.v:41758$1584_Y - attribute \src "libresoc.v:41760.20-41760.114" - wire $and$libresoc.v:41760$1586_Y - attribute \src "libresoc.v:41761.20-41761.126" - wire $and$libresoc.v:41761$1587_Y - attribute \src "libresoc.v:41763.20-41763.110" - wire $and$libresoc.v:41763$1589_Y - attribute \src "libresoc.v:41764.20-41764.123" - wire $and$libresoc.v:41764$1590_Y - attribute \src "libresoc.v:41793.20-41793.123" - wire $and$libresoc.v:41793$1619_Y - attribute \src "libresoc.v:41794.20-41794.128" - wire $and$libresoc.v:41794$1620_Y - attribute \src "libresoc.v:41795.20-41795.133" - wire $and$libresoc.v:41795$1621_Y - attribute \src "libresoc.v:41797.20-41797.110" - wire $and$libresoc.v:41797$1623_Y - attribute \src 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$and$libresoc.v:41814$1640_Y - attribute \src "libresoc.v:41815.20-41815.130" - wire $and$libresoc.v:41815$1641_Y - attribute \src "libresoc.v:41817.20-41817.110" - wire $and$libresoc.v:41817$1643_Y - attribute \src "libresoc.v:41818.20-41818.125" - wire $and$libresoc.v:41818$1644_Y - attribute \src "libresoc.v:41822.20-41822.126" - wire $and$libresoc.v:41822$1648_Y - attribute \src "libresoc.v:41823.20-41823.130" - wire $and$libresoc.v:41823$1649_Y - attribute \src "libresoc.v:41825.20-41825.110" - wire $and$libresoc.v:41825$1651_Y - attribute \src "libresoc.v:41826.20-41826.125" - wire $and$libresoc.v:41826$1652_Y - attribute \src "libresoc.v:41830.20-41830.126" - wire $and$libresoc.v:41830$1656_Y - attribute \src "libresoc.v:41831.20-41831.130" - wire $and$libresoc.v:41831$1657_Y - attribute \src "libresoc.v:41833.20-41833.110" - wire $and$libresoc.v:41833$1659_Y - attribute \src "libresoc.v:41834.20-41834.125" - wire $and$libresoc.v:41834$1660_Y - attribute \src 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$and$libresoc.v:41904$1731_Y - attribute \src "libresoc.v:41906.20-41906.128" - wire $and$libresoc.v:41906$1733_Y - attribute \src "libresoc.v:41907.20-41907.136" - wire $and$libresoc.v:41907$1734_Y - attribute \src "libresoc.v:41909.20-41909.110" - wire $and$libresoc.v:41909$1736_Y - attribute \src "libresoc.v:41910.20-41910.128" - wire $and$libresoc.v:41910$1737_Y - attribute \src "libresoc.v:41912.20-41912.128" - wire $and$libresoc.v:41912$1739_Y - attribute \src "libresoc.v:41913.20-41913.136" - wire $and$libresoc.v:41913$1740_Y - attribute \src "libresoc.v:41915.20-41915.110" - wire $and$libresoc.v:41915$1742_Y - attribute \src "libresoc.v:41916.20-41916.128" - wire $and$libresoc.v:41916$1743_Y - attribute \src "libresoc.v:41924.20-41924.118" - wire $and$libresoc.v:41924$1751_Y - attribute \src "libresoc.v:41925.20-41925.123" - wire $and$libresoc.v:41925$1752_Y - attribute \src "libresoc.v:41926.20-41926.129" - wire $and$libresoc.v:41926$1753_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire \dec_SHIFT_ROT_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 \dec_SHIFT_ROT_raw_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \dec_SPR_SPR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_SPR_SPR__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_SPR_SPR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \dec_SPR_SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire \dec_SPR_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 \dec_SPR_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 69 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 71 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 70 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_cr_c_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast2_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_FAST_fast2_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rc_ldst0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_SPR_spr1_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ca_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ca_shiftrot0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_div0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_logical0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_mul0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:273" - wire \dp_XER_xer_so_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_ldst0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire \en_trap0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire \fus_src4_i$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src4_i$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src4_i$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src4_i$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src5_i$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src5_i$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 \fus_src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 \fus_src6_i$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ca_ok$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ca_ok$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ov_ok$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ov_ok$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \fus_xer_ov_ok$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \int_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \int_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \int_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 76 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 79 \issue__addr$10 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:271" - wire \pick_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" - wire width 32 input 62 \raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_CR_cr_a_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_CR_cr_b_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_CR_cr_c_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_CR_full_cr_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_FAST_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_FAST_fast2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_INT_ra_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_INT_rb_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_INT_rc_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_SPR_spr1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:247" - wire \rdflag_XER_xer_so_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_cr_a_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_cr_b_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_CR_cr_b_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_CR_cr_b_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_cr_c_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_CR_cr_c_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_CR_cr_c_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_CR_full_cr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_FAST_fast1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \rdpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \rdpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_FAST_fast2_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_FAST_fast2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_FAST_fast2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_INT_ra_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 9 \rdpick_INT_ra_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 9 \rdpick_INT_ra_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_INT_rb_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \rdpick_INT_rb_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \rdpick_INT_rb_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_INT_rc_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_INT_rc_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_INT_rc_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_SPR_spr1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_XER_xer_ca_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \rdpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \rdpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_XER_xer_ov_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \rdpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \rdpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \rdpick_XER_xer_so_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 \rdpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" - wire \rp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr$173 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \spr_spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \spr_spr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i$172 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 68 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \state_wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire input 82 \wb_dcache_en - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1028 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1050 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1070 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1090 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1324 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1344 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1391 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1473 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1489 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1505 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1541 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1557 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1573 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1589 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1634 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1650 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1666 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1682 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1698 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1742 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1758 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1782 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$1802 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" - wire \wp$989 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1058 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1078 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1098 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1481 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1497 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1533 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1549 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1565 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1581 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1623 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1642 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1658 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1674 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1690 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1734 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1750 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1774 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$1794 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$978 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire \wr_pick$997 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1000$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1021 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1021$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1039 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1039$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1061 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1061$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1081 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1081$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1101$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1120 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1120$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1138 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1138$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1211 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1211$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1239 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1239$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1259 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1259$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1279 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1279$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1299 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1299$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1319 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1319$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1339 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1339$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1386 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1386$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1402 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1402$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1418 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1418$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1452 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1452$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1468 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1468$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1484 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1484$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1500 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1500$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1536 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1536$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1552 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1552$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1568 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1568$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1584 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1584$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1626 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1626$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1645 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1645$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1661 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1661$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1677 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1677$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1693 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1693$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1737 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1737$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1753 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1753$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1777 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1777$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1797 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$1797$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$981 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$981$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \wr_pick_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1001 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1006 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1007 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1008 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1009 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1022 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1027 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1040 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1045 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1046 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1047 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1048 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1049 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1062 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1067 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1068 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1069 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1082 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1087 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1088 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1089 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1102 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1108 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1126 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1627 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1632 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$1633 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$968 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$969 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$970 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$971 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$982 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$987 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \wr_pick_rise$988 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:397" - wire \wrflag_trap0_o_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_CR_cr_a_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 \wrpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 \wrpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_CR_full_cr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \wrpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \wrpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_FAST_fast1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 5 \wrpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 5 \wrpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_INT_o_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 10 \wrpick_INT_o_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 10 \wrpick_INT_o_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_SPR_spr1_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \wrpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \wrpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_STATE_msr_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire \wrpick_STATE_msr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire \wrpick_STATE_msr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_STATE_nia_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \wrpick_STATE_nia_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \wrpick_STATE_nia_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_XER_xer_ca_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \wrpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \wrpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_XER_xer_ov_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 \wrpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 \wrpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \wrpick_XER_xer_so_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 \wrpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 \wrpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$168 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$170 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$171 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41721$1547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$997 - connect \B \$1002 - connect \Y $and$libresoc.v:41721$1547_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41722$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$997 - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41722$1548_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41724$1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$96 - connect \B \fus_cu_busy_o$21 - connect \Y $and$libresoc.v:41724$1550_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - cell $and $and$libresoc.v:41725$1551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [3] - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41725$1551_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:41727$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1018 - connect \B \$1023 - connect \Y $and$libresoc.v:41727$1553_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" - cell $and $and$libresoc.v:41728$1554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1018 - connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:41728$1554_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - cell $and $and$libresoc.v:41730$1556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$99 - connect \B \fus_cu_busy_o$24 - connect \Y $and$libresoc.v:41730$1556_Y - end - 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\A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 10'1000000000 - connect \Y $and$libresoc.v:42051$1882_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:42053$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 9 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 9'100000000 - connect \Y $and$libresoc.v:42053$1884_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:42055$1886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 4'1000 - connect \Y $and$libresoc.v:42055$1886_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179" - cell $and $and$libresoc.v:42057$1888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 12 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 12 - connect \A \core_core_fn_unit - connect \B 3'100 - connect \Y $and$libresoc.v:42057$1888_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42062$1893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42062$1893_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42063$1894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$libresoc.v:42063$1894_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42066$1897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42066$1897_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42069$1900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $and$libresoc.v:42069$1900_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42076$1907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42076$1907_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42077$1908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$libresoc.v:42077$1908_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42080$1911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42080$1911_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42083$1914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42083$1914_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42084$1915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$libresoc.v:42084$1915_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42087$1918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42087$1918_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42089$1920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42089$1920_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42090$1921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 2'10 - connect \Y $and$libresoc.v:42090$1921_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42094$1925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $and$libresoc.v:42094$1925_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42098$1929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42098$1929_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42099$1930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$libresoc.v:42099$1930_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42102$1933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42102$1933_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42105$1936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42105$1936_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42106$1937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$libresoc.v:42106$1937_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42109$1940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42109$1940_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42112$1943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42112$1943_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42113$1944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $and$libresoc.v:42113$1944_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42116$1947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42116$1947_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42119$1950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $and$libresoc.v:42119$1950_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42124$1955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [0] - connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42124$1955_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42125$1956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$345 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42125$1956_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42127$1958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$347 - connect \B \$349 - connect \Y $and$libresoc.v:42127$1958_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42128$1959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [0] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42128$1959_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42130$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$38 [0] - connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42130$1961_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42131$1962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$357 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42131$1962_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42133$1964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $and$libresoc.v:42133$1964_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42134$1965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [1] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42134$1965_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42136$1967 - parameter \A_SIGNED 0 - parameter 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parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [2] - connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42140$1971_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42142$1973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$44 [0] - connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42142$1973_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:276" - cell $and $and$libresoc.v:42143$1974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$381 - connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42143$1974_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $and $and$libresoc.v:42145$1976 - parameter \A_SIGNED 0 - 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\A \$310 - connect \B 1'1 - connect \Y $eq$libresoc.v:42107$1938_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42114$1945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$324 - connect \B 1'1 - connect \Y $eq$libresoc.v:42114$1945_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42118$1949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $eq$libresoc.v:42118$1949_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42120$1951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$336 - 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\S \wp$1143 - connect \Y $ternary$libresoc.v:41765$1591_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41799$1625 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B \core_core_cr_wr - connect \S \wp$1216 - connect \Y $ternary$libresoc.v:41799$1625_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41813$1639 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1250 - connect \S \wp$1244 - connect \Y $ternary$libresoc.v:41813$1639_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41821$1647 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$1270 - connect \S \wp$1264 - connect \Y $ternary$libresoc.v:41821$1647_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41829$1655 - parameter \WIDTH 16 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cell $mux $ternary$libresoc.v:41872$1698 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1391 - connect \Y $ternary$libresoc.v:41872$1698_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41878$1704 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1407 - connect \Y $ternary$libresoc.v:41878$1704_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41884$1710 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1423 - connect \Y $ternary$libresoc.v:41884$1710_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41899$1726 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1457 - connect \Y $ternary$libresoc.v:41899$1726_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41905$1732 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1473 - connect \Y $ternary$libresoc.v:41905$1732_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41911$1738 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1489 - connect \Y $ternary$libresoc.v:41911$1738_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41917$1744 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1505 - connect \Y $ternary$libresoc.v:41917$1744_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41933$1760 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1541 - connect \Y $ternary$libresoc.v:41933$1760_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux 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$ternary$libresoc.v:41976$1805 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1650 - connect \Y $ternary$libresoc.v:41976$1805_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41982$1811 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1666 - connect \Y $ternary$libresoc.v:41982$1811_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41988$1817 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto2 - connect \S \wp$1682 - connect \Y $ternary$libresoc.v:41988$1817_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:41994$1823 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto2 - connect \S \wp$1698 - connect \Y $ternary$libresoc.v:41994$1823_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42014$1843 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1742 - connect \Y $ternary$libresoc.v:42014$1843_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42021$1850 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1758 - connect \Y $ternary$libresoc.v:42021$1850_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42032$1862 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1782 - connect \Y $ternary$libresoc.v:42032$1862_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42041$1872 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \core_spro - connect \S \wp$1802 - connect \Y $ternary$libresoc.v:42041$1872_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42129$1960 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$libresoc.v:42129$1960_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42135$1966 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$libresoc.v:42135$1966_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42141$1972 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$libresoc.v:42141$1972_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42147$1978 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$libresoc.v:42147$1978_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42153$1984 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$libresoc.v:42153$1984_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42159$1990 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$libresoc.v:42159$1990_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42165$1996 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$libresoc.v:42165$1996_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42171$2002 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$libresoc.v:42171$2002_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42177$2008 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$libresoc.v:42177$2008_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42192$2023 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$libresoc.v:42192$2023_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42198$2029 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$libresoc.v:42198$2029_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42204$2035 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$libresoc.v:42204$2035_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42210$2041 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$libresoc.v:42210$2041_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42216$2047 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$libresoc.v:42216$2047_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42222$2053 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$libresoc.v:42222$2053_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42228$2059 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$libresoc.v:42228$2059_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42234$2065 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$libresoc.v:42234$2065_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42248$2079 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg3 - connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$libresoc.v:42248$2079_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42254$2085 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg3 - connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$libresoc.v:42254$2085_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42268$2099 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:42268$2099_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42274$2105 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:42274$2105_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42280$2111 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:42280$2111_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42286$2117 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:42286$2117_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42292$2123 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:42292$2123_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42298$2129 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:42298$2129_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42314$2146 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:42314$2146_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42320$2152 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:42320$2152_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42326$2158 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:42326$2158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42339$2172 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:42339$2172_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42345$2178 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B \core_core_cr_rd - connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:42345$2178_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42353$2186 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$801 - connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:42353$2186_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42361$2194 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$817 - connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:42361$2194_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42370$2203 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$836 - connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:42370$2203_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42378$2211 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B \$852 - connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:42378$2211_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42384$2217 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:42384$2217_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42390$2223 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:42390$2223_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42396$2229 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:42396$2229_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42405$2238 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast2 - connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$libresoc.v:42405$2238_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42411$2244 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast2 - connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$libresoc.v:42411$2244_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" - cell $mux $ternary$libresoc.v:42419$2252 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \core_spr1 - connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:42419$2252_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42436$2269 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp - connect \Y $ternary$libresoc.v:42436$2269_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:415" - cell $mux $ternary$libresoc.v:42442$2275 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$989 - connect \Y $ternary$libresoc.v:42442$2275_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42603.6-42620.4" - cell \cr \cr - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \data_i \cr_data_i - connect \full_rd2__data_o \full_rd2__data_o - connect \full_rd2__ren \full_rd2__ren - connect \full_rd__data_o \cr_full_rd__data_o - connect \full_rd__ren \cr_full_rd__ren - connect \full_wr__data_i \cr_full_wr__data_i - connect \full_wr__wen \cr_full_wr__wen - connect \src1__data_o \cr_src1__data_o - connect \src1__ren \cr_src1__ren - connect \src2__data_o \cr_src2__data_o - connect \src2__ren \cr_src2__ren - connect \src3__data_o \cr_src3__data_o - connect \src3__ren \cr_src3__ren - connect \wen \cr_wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42621.11-42642.4" - cell \dec_ALU \dec_ALU - connect \ALU__data_len \dec_ALU_ALU__data_len - connect \ALU__fn_unit \dec_ALU_ALU__fn_unit - connect \ALU__imm_data__data \dec_ALU_ALU__imm_data__data - connect \ALU__imm_data__ok \dec_ALU_ALU__imm_data__ok - connect \ALU__input_carry \dec_ALU_ALU__input_carry - connect \ALU__insn \dec_ALU_ALU__insn - connect \ALU__insn_type \dec_ALU_ALU__insn_type - connect \ALU__invert_in \dec_ALU_ALU__invert_in - connect \ALU__invert_out \dec_ALU_ALU__invert_out - connect \ALU__is_32bit \dec_ALU_ALU__is_32bit - connect \ALU__is_signed \dec_ALU_ALU__is_signed - connect \ALU__oe__oe \dec_ALU_ALU__oe__oe - connect \ALU__oe__ok \dec_ALU_ALU__oe__ok - connect \ALU__output_carry \dec_ALU_ALU__output_carry - connect \ALU__rc__ok \dec_ALU_ALU__rc__ok - connect \ALU__rc__rc \dec_ALU_ALU__rc__rc - connect \ALU__write_cr0 \dec_ALU_ALU__write_cr0 - connect \ALU__zero_a \dec_ALU_ALU__zero_a - connect \bigendian \dec_ALU_bigendian - connect \raw_opcode_in \dec_ALU_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42643.14-42655.4" - cell \dec_BRANCH \dec_BRANCH - connect \BRANCH__cia \dec_BRANCH_BRANCH__cia - connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit - connect \BRANCH__imm_data__data \dec_BRANCH_BRANCH__imm_data__data - connect \BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__ok - connect \BRANCH__insn \dec_BRANCH_BRANCH__insn - connect \BRANCH__insn_type \dec_BRANCH_BRANCH__insn_type - connect \BRANCH__is_32bit \dec_BRANCH_BRANCH__is_32bit - connect \BRANCH__lk \dec_BRANCH_BRANCH__lk - connect \bigendian \dec_BRANCH_bigendian - connect \core_pc \core_pc - connect \raw_opcode_in \dec_BRANCH_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42656.10-42662.4" - cell \dec_CR \dec_CR - connect \CR__fn_unit \dec_CR_CR__fn_unit - connect \CR__insn \dec_CR_CR__insn - connect \CR__insn_type \dec_CR_CR__insn_type - connect \bigendian \dec_CR_bigendian - connect \raw_opcode_in \dec_CR_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42663.11-42684.4" - cell \dec_DIV \dec_DIV - connect \DIV__data_len \dec_DIV_DIV__data_len - connect \DIV__fn_unit \dec_DIV_DIV__fn_unit - connect \DIV__imm_data__data \dec_DIV_DIV__imm_data__data - connect \DIV__imm_data__ok \dec_DIV_DIV__imm_data__ok - connect \DIV__input_carry \dec_DIV_DIV__input_carry - connect \DIV__insn \dec_DIV_DIV__insn - connect \DIV__insn_type \dec_DIV_DIV__insn_type - connect \DIV__invert_in \dec_DIV_DIV__invert_in - connect \DIV__invert_out \dec_DIV_DIV__invert_out - connect \DIV__is_32bit \dec_DIV_DIV__is_32bit - connect \DIV__is_signed \dec_DIV_DIV__is_signed - connect \DIV__oe__oe \dec_DIV_DIV__oe__oe - connect \DIV__oe__ok \dec_DIV_DIV__oe__ok - connect \DIV__output_carry \dec_DIV_DIV__output_carry - connect \DIV__rc__ok \dec_DIV_DIV__rc__ok - connect \DIV__rc__rc \dec_DIV_DIV__rc__rc - connect \DIV__write_cr0 \dec_DIV_DIV__write_cr0 - connect \DIV__zero_a \dec_DIV_DIV__zero_a - connect \bigendian \dec_DIV_bigendian - connect \raw_opcode_in \dec_DIV_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42685.12-42704.4" - cell \dec_LDST \dec_LDST - connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse - connect \LDST__data_len \dec_LDST_LDST__data_len - connect \LDST__fn_unit \dec_LDST_LDST__fn_unit - connect \LDST__imm_data__data \dec_LDST_LDST__imm_data__data - connect \LDST__imm_data__ok \dec_LDST_LDST__imm_data__ok - connect \LDST__insn \dec_LDST_LDST__insn - connect \LDST__insn_type \dec_LDST_LDST__insn_type - connect \LDST__is_32bit \dec_LDST_LDST__is_32bit - connect \LDST__is_signed \dec_LDST_LDST__is_signed - connect \LDST__ldst_mode \dec_LDST_LDST__ldst_mode - connect \LDST__oe__oe \dec_LDST_LDST__oe__oe - connect \LDST__oe__ok \dec_LDST_LDST__oe__ok - connect \LDST__rc__ok \dec_LDST_LDST__rc__ok - connect \LDST__rc__rc \dec_LDST_LDST__rc__rc - connect \LDST__sign_extend \dec_LDST_LDST__sign_extend - connect \LDST__zero_a \dec_LDST_LDST__zero_a - connect \bigendian \dec_LDST_bigendian - connect \raw_opcode_in \dec_LDST_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42705.15-42726.4" - cell \dec_LOGICAL \dec_LOGICAL - connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len - connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit - connect \LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL__imm_data__data - connect \LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__ok - connect \LOGICAL__input_carry \dec_LOGICAL_LOGICAL__input_carry - connect \LOGICAL__insn \dec_LOGICAL_LOGICAL__insn - connect \LOGICAL__insn_type \dec_LOGICAL_LOGICAL__insn_type - connect \LOGICAL__invert_in \dec_LOGICAL_LOGICAL__invert_in - connect \LOGICAL__invert_out \dec_LOGICAL_LOGICAL__invert_out - connect \LOGICAL__is_32bit \dec_LOGICAL_LOGICAL__is_32bit - connect \LOGICAL__is_signed \dec_LOGICAL_LOGICAL__is_signed - connect \LOGICAL__oe__oe \dec_LOGICAL_LOGICAL__oe__oe - connect \LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__ok - connect \LOGICAL__output_carry \dec_LOGICAL_LOGICAL__output_carry - connect \LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__ok - connect \LOGICAL__rc__rc \dec_LOGICAL_LOGICAL__rc__rc - connect \LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL__write_cr0 - connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a - connect \bigendian \dec_LOGICAL_bigendian - connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42727.11-42742.4" - cell \dec_MUL \dec_MUL - connect \MUL__fn_unit \dec_MUL_MUL__fn_unit - connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data - connect \MUL__imm_data__ok \dec_MUL_MUL__imm_data__ok - connect \MUL__insn \dec_MUL_MUL__insn - connect \MUL__insn_type \dec_MUL_MUL__insn_type - connect \MUL__is_32bit \dec_MUL_MUL__is_32bit - connect \MUL__is_signed \dec_MUL_MUL__is_signed - connect \MUL__oe__oe \dec_MUL_MUL__oe__oe - connect \MUL__oe__ok \dec_MUL_MUL__oe__ok - connect \MUL__rc__ok \dec_MUL_MUL__rc__ok - connect \MUL__rc__rc \dec_MUL_MUL__rc__rc - connect \MUL__write_cr0 \dec_MUL_MUL__write_cr0 - connect \bigendian \dec_MUL_bigendian - connect \raw_opcode_in \dec_MUL_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42743.17-42763.4" - cell \dec_SHIFT_ROT \dec_SHIFT_ROT - connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit - connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data - connect \SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok - connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT__input_carry - connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT__input_cr - connect \SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT__insn - connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT__insn_type - connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_SHIFT_ROT__invert_in - connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT__is_32bit - connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT__is_signed - connect \SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT__oe__oe - connect \SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__ok - connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT__output_carry - connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT__output_cr - connect \SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__ok - connect \SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT__rc__rc - connect \SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 - connect \bigendian \dec_SHIFT_ROT_bigendian - connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42764.11-42771.4" - cell \dec_SPR \dec_SPR - connect \SPR__fn_unit \dec_SPR_SPR__fn_unit - connect \SPR__insn \dec_SPR_SPR__insn - connect \SPR__insn_type \dec_SPR_SPR__insn_type - connect \SPR__is_32bit \dec_SPR_SPR__is_32bit - connect \bigendian \dec_SPR_bigendian - connect \raw_opcode_in \dec_SPR_raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42772.8-42790.4" - cell \fast \fast - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest1__addr \fast_dest1__addr - connect \dest1__data_i \fast_dest1__data_i - connect \dest1__wen \fast_dest1__wen - connect \issue__addr \issue__addr - connect \issue__addr$1 \issue__addr$10 - connect \issue__data_i \issue__data_i - connect \issue__data_o \issue__data_o - connect \issue__ren \issue__ren - connect \issue__wen \issue__wen - connect \src1__addr \fast_src1__addr - connect \src1__data_o \fast_src1__data_o - connect \src1__ren \fast_src1__ren - connect \src2__addr \fast_src2__addr - connect \src2__data_o \fast_src2__data_o - connect \src2__ren \fast_src2__ren - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:42791.7-43122.4" - cell \fus \fus - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$110 \fus_cr_a_ok$120 - connect \cr_a_ok$111 \fus_cr_a_ok$121 - connect \cr_a_ok$112 \fus_cr_a_ok$122 - connect \cr_a_ok$113 \fus_cr_a_ok$123 - connect \cr_a_ok$114 \fus_cr_a_ok$124 - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_busy_o \fus_cu_busy_o - connect \cu_busy_o$11 \fus_cu_busy_o$21 - connect \cu_busy_o$14 \fus_cu_busy_o$24 - connect \cu_busy_o$17 \fus_cu_busy_o$27 - connect \cu_busy_o$2 \fus_cu_busy_o$12 - connect \cu_busy_o$20 \fus_cu_busy_o$30 - connect \cu_busy_o$23 \fus_cu_busy_o$33 - connect \cu_busy_o$26 \fus_cu_busy_o$36 - connect \cu_busy_o$5 \fus_cu_busy_o$15 - connect \cu_busy_o$8 \fus_cu_busy_o$18 - connect \cu_issue_i \fus_cu_issue_i - connect \cu_issue_i$1 \fus_cu_issue_i$11 - connect \cu_issue_i$10 \fus_cu_issue_i$20 - connect \cu_issue_i$13 \fus_cu_issue_i$23 - connect \cu_issue_i$16 \fus_cu_issue_i$26 - connect \cu_issue_i$19 \fus_cu_issue_i$29 - connect \cu_issue_i$22 \fus_cu_issue_i$32 - connect \cu_issue_i$25 \fus_cu_issue_i$35 - connect \cu_issue_i$4 \fus_cu_issue_i$14 - connect \cu_issue_i$7 \fus_cu_issue_i$17 - connect \cu_rd__go_i \fus_cu_rd__go_i - connect \cu_rd__go_i$29 \fus_cu_rd__go_i$39 - connect \cu_rd__go_i$32 \fus_cu_rd__go_i$42 - connect \cu_rd__go_i$35 \fus_cu_rd__go_i$45 - connect \cu_rd__go_i$38 \fus_cu_rd__go_i$48 - connect \cu_rd__go_i$41 \fus_cu_rd__go_i$51 - connect \cu_rd__go_i$44 \fus_cu_rd__go_i$54 - connect \cu_rd__go_i$47 \fus_cu_rd__go_i$57 - connect \cu_rd__go_i$50 \fus_cu_rd__go_i$60 - connect \cu_rd__go_i$70 \fus_cu_rd__go_i$80 - connect \cu_rd__rel_o \fus_cu_rd__rel_o - connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$38 - connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$41 - connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$44 - connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$47 - connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$50 - connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$53 - connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$56 - connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$59 - connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$79 - connect \cu_rdmaskn_i \fus_cu_rdmaskn_i - connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$22 - connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$25 - connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$28 - connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$31 - connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$34 - connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$37 - connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$13 - connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$16 - connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$19 - connect \cu_st__go_i \cu_st__go_i - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_wr__go_i \fus_cu_wr__go_i - connect \cu_wr__go_i$100 \fus_cu_wr__go_i$110 - connect \cu_wr__go_i$102 \fus_cu_wr__go_i$112 - connect \cu_wr__go_i$137 \fus_cu_wr__go_i$147 - connect \cu_wr__go_i$82 \fus_cu_wr__go_i$92 - connect \cu_wr__go_i$85 \fus_cu_wr__go_i$95 - connect \cu_wr__go_i$88 \fus_cu_wr__go_i$98 - connect \cu_wr__go_i$91 \fus_cu_wr__go_i$101 - connect \cu_wr__go_i$94 \fus_cu_wr__go_i$104 - connect \cu_wr__go_i$97 \fus_cu_wr__go_i$107 - connect \cu_wr__rel_o \fus_cu_wr__rel_o - connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$111 - connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$146 - connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$91 - connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$94 - connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$97 - connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$100 - connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$103 - connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$106 - connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$109 - connect \dest1_o \fus_dest1_o - connect \dest1_o$103 \fus_dest1_o$113 - connect \dest1_o$104 \fus_dest1_o$114 - connect \dest1_o$105 \fus_dest1_o$115 - connect \dest1_o$106 \fus_dest1_o$116 - connect \dest1_o$107 \fus_dest1_o$117 - connect \dest1_o$108 \fus_dest1_o$118 - connect \dest1_o$109 \fus_dest1_o$119 - connect \dest1_o$141 \fus_dest1_o$151 - connect \dest2_o \fus_dest2_o - connect \dest2_o$115 \fus_dest2_o$125 - connect \dest2_o$116 \fus_dest2_o$126 - connect \dest2_o$117 \fus_dest2_o$127 - connect \dest2_o$118 \fus_dest2_o$128 - connect \dest2_o$119 \fus_dest2_o$129 - connect \dest2_o$142 \fus_dest2_o$152 - connect \dest2_o$144 \fus_dest2_o$154 - connect \dest2_o$150 \fus_dest2_o$160 - connect \dest3_o \fus_dest3_o - connect \dest3_o$122 \fus_dest3_o$132 - connect \dest3_o$123 \fus_dest3_o$133 - connect \dest3_o$127 \fus_dest3_o$137 - connect \dest3_o$128 \fus_dest3_o$138 - connect \dest3_o$143 \fus_dest3_o$153 - connect \dest3_o$145 \fus_dest3_o$155 - connect \dest3_o$147 \fus_dest3_o$157 - connect \dest4_o \fus_dest4_o - connect \dest4_o$133 \fus_dest4_o$143 - connect \dest4_o$134 \fus_dest4_o$144 - connect \dest4_o$135 \fus_dest4_o$145 - connect \dest4_o$148 \fus_dest4_o$158 - connect \dest5_o \fus_dest5_o - connect \dest5_o$132 \fus_dest5_o$142 - connect \dest5_o$149 \fus_dest5_o$159 - connect \dest6_o \fus_dest6_o - connect \ea \fus_ea - connect \fast1_ok \fus_fast1_ok - connect \fast1_ok$138 \fus_fast1_ok$148 - connect \fast1_ok$139 \fus_fast1_ok$149 - connect \fast2_ok \fus_fast2_ok - connect \fast2_ok$140 \fus_fast2_ok$150 - connect \full_cr_ok \fus_full_cr_ok - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$161 - connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$162 - connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$163 - connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$164 - connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$165 - connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$166 - connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$167 - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - connect \msr_ok \fus_msr_ok - connect \nia_ok \fus_nia_ok - connect \nia_ok$146 \fus_nia_ok$156 - connect \o \fus_o - connect \o_ok \fus_o_ok - connect \o_ok$80 \fus_o_ok$90 - connect \o_ok$83 \fus_o_ok$93 - connect \o_ok$86 \fus_o_ok$96 - connect \o_ok$89 \fus_o_ok$99 - connect \o_ok$92 \fus_o_ok$102 - connect \o_ok$95 \fus_o_ok$105 - connect \o_ok$98 \fus_o_ok$108 - connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data - connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok - connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn - connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok - connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok - connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a - connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data - connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok - connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit - connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk - connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type - connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len - connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data - connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok - connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn - connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok - connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok - connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a - connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data - connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok - connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn - connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok - connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok - connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a - connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data - connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok - connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn - connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok - connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok - connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 - connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data - connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok - connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn - connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__invert_in \fus_oper_i_alu_shift_rot0__invert_in - connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok - connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok - connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 - connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit - connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__ldst_exc \fus_oper_i_alu_trap0__ldst_exc - connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr - connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype - connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit - connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data - connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok - connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn - connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode - connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok - connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok - connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a - connect \spr1_ok \fus_spr1_ok - connect \src1_i \fus_src1_i - connect \src1_i$30 \fus_src1_i$40 - connect \src1_i$33 \fus_src1_i$43 - connect \src1_i$36 \fus_src1_i$46 - connect \src1_i$39 \fus_src1_i$49 - connect \src1_i$42 \fus_src1_i$52 - connect \src1_i$45 \fus_src1_i$55 - connect \src1_i$48 \fus_src1_i$58 - connect \src1_i$51 \fus_src1_i$61 - connect \src1_i$74 \fus_src1_i$84 - connect \src2_i \fus_src2_i - connect \src2_i$52 \fus_src2_i$62 - connect \src2_i$53 \fus_src2_i$63 - connect \src2_i$54 \fus_src2_i$64 - connect \src2_i$55 \fus_src2_i$65 - connect \src2_i$56 \fus_src2_i$66 - connect \src2_i$57 \fus_src2_i$67 - connect \src2_i$58 \fus_src2_i$68 - connect \src2_i$77 \fus_src2_i$87 - connect \src2_i$79 \fus_src2_i$89 - connect \src3_i \fus_src3_i - connect \src3_i$59 \fus_src3_i$69 - connect \src3_i$60 \fus_src3_i$70 - connect \src3_i$61 \fus_src3_i$71 - connect \src3_i$62 \fus_src3_i$72 - connect \src3_i$63 \fus_src3_i$73 - connect \src3_i$67 \fus_src3_i$77 - connect \src3_i$71 \fus_src3_i$81 - connect \src3_i$75 \fus_src3_i$85 - connect \src3_i$76 \fus_src3_i$86 - connect \src4_i \fus_src4_i - connect \src4_i$64 \fus_src4_i$74 - connect \src4_i$65 \fus_src4_i$75 - connect \src4_i$68 \fus_src4_i$78 - connect \src4_i$78 \fus_src4_i$88 - connect \src5_i \fus_src5_i - connect \src5_i$66 \fus_src5_i$76 - connect \src5_i$72 \fus_src5_i$82 - connect \src6_i \fus_src6_i - connect \src6_i$73 \fus_src6_i$83 - connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$120 \fus_xer_ca_ok$130 - connect \xer_ca_ok$121 \fus_xer_ca_ok$131 - connect \xer_ov_ok \fus_xer_ov_ok - connect \xer_ov_ok$124 \fus_xer_ov_ok$134 - connect \xer_ov_ok$125 \fus_xer_ov_ok$135 - connect \xer_ov_ok$126 \fus_xer_ov_ok$136 - connect \xer_so_ok \fus_xer_so_ok - connect \xer_so_ok$129 \fus_xer_so_ok$139 - connect \xer_so_ok$130 \fus_xer_so_ok$140 - connect \xer_so_ok$131 \fus_xer_so_ok$141 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43123.9-43141.4" - cell \int \int - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest1__addr \int_dest1__addr - connect \dest1__data_i \int_dest1__data_i - connect \dest1__wen \int_dest1__wen - connect \dmi__addr \dmi__addr - connect \dmi__data_o \dmi__data_o - connect \dmi__ren \dmi__ren - connect \src1__addr \int_src1__addr - connect \src1__data_o \int_src1__data_o - connect \src1__ren \int_src1__ren - connect \src2__addr \int_src2__addr - connect \src2__data_o \int_src2__data_o - connect \src2__ren \int_src2__ren - connect \src3__addr \int_src3__addr - connect \src3__data_o \int_src3__data_o - connect \src3__ren \int_src3__ren - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43142.6-43174.4" - cell \l0 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$161 - connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$162 - connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$163 - connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$164 - connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$165 - connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$166 - connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$167 - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - connect \wb_dcache_en \wb_dcache_en - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43175.18-43179.4" - cell \rdpick_CR_cr_a \rdpick_CR_cr_a - connect \en_o \rdpick_CR_cr_a_en_o - connect \i \rdpick_CR_cr_a_i - connect \o \rdpick_CR_cr_a_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43180.18-43184.4" - cell \rdpick_CR_cr_b \rdpick_CR_cr_b - connect \en_o \rdpick_CR_cr_b_en_o - connect \i \rdpick_CR_cr_b_i - connect \o \rdpick_CR_cr_b_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43185.18-43189.4" - cell \rdpick_CR_cr_c \rdpick_CR_cr_c - connect \en_o \rdpick_CR_cr_c_en_o - connect \i \rdpick_CR_cr_c_i - connect \o \rdpick_CR_cr_c_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43190.21-43194.4" - cell \rdpick_CR_full_cr \rdpick_CR_full_cr - connect \en_o \rdpick_CR_full_cr_en_o - connect \i \rdpick_CR_full_cr_i - connect \o \rdpick_CR_full_cr_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43195.21-43199.4" - cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 - connect \en_o \rdpick_FAST_fast1_en_o - connect \i \rdpick_FAST_fast1_i - connect \o \rdpick_FAST_fast1_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43200.21-43204.4" - cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 - connect \en_o \rdpick_FAST_fast2_en_o - connect \i \rdpick_FAST_fast2_i - connect \o \rdpick_FAST_fast2_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43205.17-43209.4" - cell \rdpick_INT_ra \rdpick_INT_ra - connect \en_o \rdpick_INT_ra_en_o - connect \i \rdpick_INT_ra_i - connect \o \rdpick_INT_ra_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43210.17-43214.4" - cell \rdpick_INT_rb \rdpick_INT_rb - connect \en_o \rdpick_INT_rb_en_o - connect \i \rdpick_INT_rb_i - connect \o \rdpick_INT_rb_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43215.17-43219.4" - cell \rdpick_INT_rc \rdpick_INT_rc - connect \en_o \rdpick_INT_rc_en_o - connect \i \rdpick_INT_rc_i - connect \o \rdpick_INT_rc_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43220.19-43224.4" - cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 - connect \en_o \rdpick_SPR_spr1_en_o - connect \i \rdpick_SPR_spr1_i - connect \o \rdpick_SPR_spr1_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43225.21-43229.4" - cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca - connect \en_o \rdpick_XER_xer_ca_en_o - connect \i \rdpick_XER_xer_ca_i - connect \o \rdpick_XER_xer_ca_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43230.21-43234.4" - cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov - connect \en_o \rdpick_XER_xer_ov_en_o - connect \i \rdpick_XER_xer_ov_i - connect \o \rdpick_XER_xer_ov_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43235.21-43239.4" - cell \rdpick_XER_xer_so \rdpick_XER_xer_so - connect \en_o \rdpick_XER_xer_so_en_o - connect \i \rdpick_XER_xer_so_i - connect \o \rdpick_XER_xer_so_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43240.7-43249.4" - cell \spr \spr - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \spr1__addr \spr_spr1__addr - connect \spr1__addr$1 \spr_spr1__addr$173 - connect \spr1__data_i \spr_spr1__data_i - connect \spr1__data_o \spr_spr1__data_o - connect \spr1__ren \spr_spr1__ren - connect \spr1__wen \spr_spr1__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43250.9-43263.4" - cell \state \state - connect \cia__data_o \cia__data_o - connect \cia__ren \cia__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \data_i \data_i - connect \data_i$1 \state_data_i - connect \data_i$2 \state_data_i$172 - connect \msr__data_o \msr__data_o - connect \msr__ren \msr__ren - connect \state_nia_wen \state_nia_wen - connect \wen \wen - connect \wen$3 \state_wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43264.18-43268.4" - cell \wrpick_CR_cr_a \wrpick_CR_cr_a - connect \en_o \wrpick_CR_cr_a_en_o - connect \i \wrpick_CR_cr_a_i - connect \o \wrpick_CR_cr_a_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43269.21-43273.4" - cell \wrpick_CR_full_cr \wrpick_CR_full_cr - connect \en_o \wrpick_CR_full_cr_en_o - connect \i \wrpick_CR_full_cr_i - connect \o \wrpick_CR_full_cr_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43274.21-43278.4" - cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 - connect \en_o \wrpick_FAST_fast1_en_o - connect \i \wrpick_FAST_fast1_i - connect \o \wrpick_FAST_fast1_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43279.16-43283.4" - cell \wrpick_INT_o \wrpick_INT_o - connect \en_o \wrpick_INT_o_en_o - connect \i \wrpick_INT_o_i - connect \o \wrpick_INT_o_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43284.19-43288.4" - cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 - connect \en_o \wrpick_SPR_spr1_en_o - connect \i \wrpick_SPR_spr1_i - connect \o \wrpick_SPR_spr1_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43289.20-43293.4" - cell \wrpick_STATE_msr \wrpick_STATE_msr - connect \en_o \wrpick_STATE_msr_en_o - connect \i \wrpick_STATE_msr_i - connect \o \wrpick_STATE_msr_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43294.20-43298.4" - cell \wrpick_STATE_nia \wrpick_STATE_nia - connect \en_o \wrpick_STATE_nia_en_o - connect \i \wrpick_STATE_nia_i - connect \o \wrpick_STATE_nia_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43299.21-43303.4" - cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca - connect \en_o \wrpick_XER_xer_ca_en_o - connect \i \wrpick_XER_xer_ca_i - connect \o \wrpick_XER_xer_ca_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43304.21-43308.4" - cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov - connect \en_o \wrpick_XER_xer_ov_en_o - connect \i \wrpick_XER_xer_ov_i - connect \o \wrpick_XER_xer_ov_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43309.21-43313.4" - cell \wrpick_XER_xer_so \wrpick_XER_xer_so - connect \en_o \wrpick_XER_xer_so_en_o - connect \i \wrpick_XER_xer_so_i - connect \o \wrpick_XER_xer_so_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:43314.7-43331.4" - cell \xer \xer - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \data_i \xer_data_i - connect \data_i$1 \xer_data_i$168 - connect \data_i$3 \xer_data_i$170 - connect \full_rd__data_o \full_rd__data_o - connect \full_rd__ren \full_rd__ren - connect \src1__data_o \xer_src1__data_o - connect \src1__ren \xer_src1__ren - connect \src2__data_o \xer_src2__data_o - connect \src2__ren \xer_src2__ren - connect \src3__data_o \xer_src3__data_o - connect \src3__ren \xer_src3__ren - connect \wen \xer_wen - connect \wen$2 \xer_wen$169 - connect \wen$4 \xer_wen$171 - end - attribute \src "libresoc.v:35933.7-35933.20" - process $proc$libresoc.v:35933$2940 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:37965.7-37965.30" - process $proc$libresoc.v:37965$2941 - assign { } { } - assign $1\core_terminate_o[0:0] 1'0 - sync always - sync init - update \core_terminate_o $1\core_terminate_o[0:0] - end - attribute \src "libresoc.v:37978.13-37978.27" - process $proc$libresoc.v:37978$2942 - assign { } { } - assign $1\counter[1:0] 2'00 - sync always - sync init - update \counter $1\counter[1:0] - end - attribute \src "libresoc.v:39108.7-39108.34" - process $proc$libresoc.v:39108$2943 - assign { } { } - assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] - end - attribute \src "libresoc.v:39112.7-39112.30" - process $proc$libresoc.v:39112$2944 - assign { } { } - assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] - end - attribute \src "libresoc.v:39116.7-39116.30" - process $proc$libresoc.v:39116$2945 - assign { } { } - assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] - end - attribute \src "libresoc.v:39120.7-39120.30" - process $proc$libresoc.v:39120$2946 - assign { } { } - assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] - end - attribute \src "libresoc.v:39124.7-39124.33" - process $proc$libresoc.v:39124$2947 - assign { } { } - assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 - sync always - sync init - update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] - end - attribute \src "libresoc.v:39128.7-39128.37" - process $proc$libresoc.v:39128$2948 - assign { } { } - assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] - end - attribute \src "libresoc.v:39132.7-39132.34" - process $proc$libresoc.v:39132$2949 - assign { } { } - assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] - end - attribute \src "libresoc.v:39136.7-39136.35" - process $proc$libresoc.v:39136$2950 - assign { } { } - assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] - end - attribute \src "libresoc.v:39140.7-39140.37" - process $proc$libresoc.v:39140$2951 - assign { } { } - assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] - end - attribute \src "libresoc.v:39144.7-39144.35" - process $proc$libresoc.v:39144$2952 - assign { } { } - assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 - sync always - sync init - update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] - end - attribute \src "libresoc.v:39148.7-39148.30" - process $proc$libresoc.v:39148$2953 - assign { } { } - assign $1\dp_INT_ra_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] - end - attribute \src "libresoc.v:39152.7-39152.29" - process $proc$libresoc.v:39152$2954 - assign { } { } - assign $1\dp_INT_ra_cr0_1[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] - end - attribute \src "libresoc.v:39156.7-39156.30" - process $proc$libresoc.v:39156$2955 - assign { } { } - assign $1\dp_INT_ra_div0_5[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] - end - attribute \src "libresoc.v:39160.7-39160.31" - process $proc$libresoc.v:39160$2956 - assign { } { } - assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] - end - attribute \src "libresoc.v:39164.7-39164.34" - process $proc$libresoc.v:39164$2957 - assign { } { } - assign $1\dp_INT_ra_logical0_3[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] - end - attribute \src "libresoc.v:39168.7-39168.30" - process $proc$libresoc.v:39168$2958 - assign { } { } - assign $1\dp_INT_ra_mul0_6[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] - end - attribute \src "libresoc.v:39172.7-39172.35" - process $proc$libresoc.v:39172$2959 - assign { } { } - assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] - end - attribute \src "libresoc.v:39176.7-39176.30" - process $proc$libresoc.v:39176$2960 - assign { } { } - assign $1\dp_INT_ra_spr0_4[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] - end - attribute \src "libresoc.v:39180.7-39180.31" - process $proc$libresoc.v:39180$2961 - assign { } { } - assign $1\dp_INT_ra_trap0_2[0:0] 1'0 - sync always - sync init - update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] - end - attribute \src "libresoc.v:39184.7-39184.30" - process $proc$libresoc.v:39184$2962 - assign { } { } - assign $1\dp_INT_rb_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] - end - attribute \src "libresoc.v:39188.7-39188.29" - process $proc$libresoc.v:39188$2963 - assign { } { } - assign $1\dp_INT_rb_cr0_1[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] - end - attribute \src "libresoc.v:39192.7-39192.30" - process $proc$libresoc.v:39192$2964 - assign { } { } - assign $1\dp_INT_rb_div0_4[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] - end - attribute \src "libresoc.v:39196.7-39196.31" - process $proc$libresoc.v:39196$2965 - assign { } { } - assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] - end - attribute \src "libresoc.v:39200.7-39200.34" - process $proc$libresoc.v:39200$2966 - assign { } { } - assign $1\dp_INT_rb_logical0_3[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] - end - attribute \src "libresoc.v:39204.7-39204.30" - process $proc$libresoc.v:39204$2967 - assign { } { } - assign $1\dp_INT_rb_mul0_5[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] - end - attribute \src "libresoc.v:39208.7-39208.35" - process $proc$libresoc.v:39208$2968 - assign { } { } - assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] - end - attribute \src "libresoc.v:39212.7-39212.31" - process $proc$libresoc.v:39212$2969 - assign { } { } - assign $1\dp_INT_rb_trap0_2[0:0] 1'0 - sync always - sync init - update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] - end - attribute \src "libresoc.v:39216.7-39216.31" - process $proc$libresoc.v:39216$2970 - assign { } { } - assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 - sync always - sync init - update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] - end - attribute \src "libresoc.v:39220.7-39220.35" - process $proc$libresoc.v:39220$2971 - assign { } { } - assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 - sync always - sync init - update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] - end - attribute \src "libresoc.v:39224.7-39224.32" - process $proc$libresoc.v:39224$2972 - assign { } { } - assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 - sync always - sync init - update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] - end - attribute \src "libresoc.v:39228.7-39228.34" - process $proc$libresoc.v:39228$2973 - assign { } { } - assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] - end - attribute \src "libresoc.v:39232.7-39232.39" - process $proc$libresoc.v:39232$2974 - assign { } { } - assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] - end - attribute \src "libresoc.v:39236.7-39236.34" - process $proc$libresoc.v:39236$2975 - assign { } { } - assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] - end - attribute \src "libresoc.v:39240.7-39240.34" - process $proc$libresoc.v:39240$2976 - assign { } { } - assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] - end - attribute \src "libresoc.v:39244.7-39244.34" - process $proc$libresoc.v:39244$2977 - assign { } { } - assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] - end - attribute \src "libresoc.v:39248.7-39248.34" - process $proc$libresoc.v:39248$2978 - assign { } { } - assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] - end - attribute \src "libresoc.v:39252.7-39252.38" - process $proc$libresoc.v:39252$2979 - assign { } { } - assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] - end - attribute \src "libresoc.v:39256.7-39256.34" - process $proc$libresoc.v:39256$2980 - assign { } { } - assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] - end - attribute \src "libresoc.v:39260.7-39260.39" - process $proc$libresoc.v:39260$2981 - assign { } { } - assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] - end - attribute \src "libresoc.v:39264.7-39264.34" - process $proc$libresoc.v:39264$2982 - assign { } { } - assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 - sync always - sync init - update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] - end - attribute \src "libresoc.v:41341.7-41341.25" - process $proc$libresoc.v:41341$2983 - assign { } { } - assign $1\wr_pick_dly[0:0] 1'0 - sync always - sync init - update \wr_pick_dly $1\wr_pick_dly[0:0] - end - attribute \src "libresoc.v:41343.7-41343.32" - process $proc$libresoc.v:41343$2984 - assign { } { } - assign $0\wr_pick_dly$1000[0:0]$2985 1'0 - sync always - sync init - update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2985 - end - attribute \src "libresoc.v:41347.7-41347.32" - process $proc$libresoc.v:41347$2986 - assign { } { } - assign $0\wr_pick_dly$1021[0:0]$2987 1'0 - sync always - sync init - update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2987 - end - attribute \src "libresoc.v:41351.7-41351.32" - process $proc$libresoc.v:41351$2988 - assign { } { } - assign $0\wr_pick_dly$1039[0:0]$2989 1'0 - sync always - sync init - update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2989 - end - attribute \src "libresoc.v:41355.7-41355.32" - process $proc$libresoc.v:41355$2990 - assign { } { } - assign $0\wr_pick_dly$1061[0:0]$2991 1'0 - sync always - sync init - update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2991 - end - attribute \src "libresoc.v:41359.7-41359.32" - process $proc$libresoc.v:41359$2992 - assign { } { } - assign $0\wr_pick_dly$1081[0:0]$2993 1'0 - sync always - sync init - update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2993 - end - attribute \src "libresoc.v:41363.7-41363.32" - process $proc$libresoc.v:41363$2994 - assign { } { } - assign $0\wr_pick_dly$1101[0:0]$2995 1'0 - sync always - sync init - update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2995 - end - attribute \src "libresoc.v:41367.7-41367.32" - process $proc$libresoc.v:41367$2996 - assign { } { } - assign $0\wr_pick_dly$1120[0:0]$2997 1'0 - sync always - sync init - update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2997 - end - attribute \src "libresoc.v:41371.7-41371.32" - process $proc$libresoc.v:41371$2998 - assign { } { } - assign $0\wr_pick_dly$1138[0:0]$2999 1'0 - sync always - sync init - update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2999 - end - attribute \src "libresoc.v:41375.7-41375.32" - process $proc$libresoc.v:41375$3000 - assign { } { } - assign $0\wr_pick_dly$1211[0:0]$3001 1'0 - sync always - sync init - update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$3001 - end - attribute \src "libresoc.v:41379.7-41379.32" - process $proc$libresoc.v:41379$3002 - assign { } { } - assign $0\wr_pick_dly$1239[0:0]$3003 1'0 - sync always - sync init - update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$3003 - end - attribute \src "libresoc.v:41383.7-41383.32" - process $proc$libresoc.v:41383$3004 - assign { } { } - assign $0\wr_pick_dly$1259[0:0]$3005 1'0 - sync always - sync init - update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$3005 - end - attribute \src "libresoc.v:41387.7-41387.32" - process $proc$libresoc.v:41387$3006 - assign { } { } - assign $0\wr_pick_dly$1279[0:0]$3007 1'0 - sync always - sync init - update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$3007 - end - attribute \src "libresoc.v:41391.7-41391.32" - process $proc$libresoc.v:41391$3008 - assign { } { } - assign $0\wr_pick_dly$1299[0:0]$3009 1'0 - sync always - sync init - update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$3009 - end - attribute \src "libresoc.v:41395.7-41395.32" - process $proc$libresoc.v:41395$3010 - assign { } { } - assign $0\wr_pick_dly$1319[0:0]$3011 1'0 - sync always - sync init - update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$3011 - end - attribute \src "libresoc.v:41399.7-41399.32" - process $proc$libresoc.v:41399$3012 - assign { } { } - assign $0\wr_pick_dly$1339[0:0]$3013 1'0 - sync always - sync init - update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$3013 - end - attribute \src "libresoc.v:41403.7-41403.32" - process $proc$libresoc.v:41403$3014 - assign { } { } - assign $0\wr_pick_dly$1386[0:0]$3015 1'0 - sync always - sync init - update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$3015 - end - attribute \src "libresoc.v:41407.7-41407.32" - process $proc$libresoc.v:41407$3016 - assign { } { } - assign $0\wr_pick_dly$1402[0:0]$3017 1'0 - sync always - sync init - update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$3017 - end - attribute \src "libresoc.v:41411.7-41411.32" - process $proc$libresoc.v:41411$3018 - assign { } { } - assign $0\wr_pick_dly$1418[0:0]$3019 1'0 - sync always - sync init - update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$3019 - end - attribute \src "libresoc.v:41415.7-41415.32" - process $proc$libresoc.v:41415$3020 - assign { } { } - assign $0\wr_pick_dly$1452[0:0]$3021 1'0 - sync always - sync init - update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$3021 - end - attribute \src "libresoc.v:41419.7-41419.32" - process $proc$libresoc.v:41419$3022 - assign { } { } - assign $0\wr_pick_dly$1468[0:0]$3023 1'0 - sync always - sync init - update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$3023 - end - attribute \src "libresoc.v:41423.7-41423.32" - process $proc$libresoc.v:41423$3024 - assign { } { } - assign $0\wr_pick_dly$1484[0:0]$3025 1'0 - sync always - sync init - update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$3025 - end - attribute \src "libresoc.v:41427.7-41427.32" - process $proc$libresoc.v:41427$3026 - assign { } { } - assign $0\wr_pick_dly$1500[0:0]$3027 1'0 - sync always - sync init - update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$3027 - end - attribute \src "libresoc.v:41431.7-41431.32" - process $proc$libresoc.v:41431$3028 - assign { } { } - assign $0\wr_pick_dly$1536[0:0]$3029 1'0 - sync always - sync init - update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$3029 - end - attribute \src "libresoc.v:41435.7-41435.32" - process $proc$libresoc.v:41435$3030 - assign { } { } - assign $0\wr_pick_dly$1552[0:0]$3031 1'0 - sync always - sync init - update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$3031 - end - attribute \src "libresoc.v:41439.7-41439.32" - process $proc$libresoc.v:41439$3032 - assign { } { } - assign $0\wr_pick_dly$1568[0:0]$3033 1'0 - sync always - sync init - update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$3033 - end - attribute \src "libresoc.v:41443.7-41443.32" - process $proc$libresoc.v:41443$3034 - assign { } { } - assign $0\wr_pick_dly$1584[0:0]$3035 1'0 - sync always - sync init - update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$3035 - end - attribute \src "libresoc.v:41447.7-41447.32" - process $proc$libresoc.v:41447$3036 - assign { } { } - assign $0\wr_pick_dly$1626[0:0]$3037 1'0 - sync always - sync init - update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$3037 - end - attribute \src "libresoc.v:41451.7-41451.32" - process $proc$libresoc.v:41451$3038 - assign { } { } - assign $0\wr_pick_dly$1645[0:0]$3039 1'0 - sync always - sync init - update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$3039 - end - attribute \src "libresoc.v:41455.7-41455.32" - process $proc$libresoc.v:41455$3040 - assign { } { } - assign $0\wr_pick_dly$1661[0:0]$3041 1'0 - sync always - sync init - update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$3041 - end - attribute \src "libresoc.v:41459.7-41459.32" - process $proc$libresoc.v:41459$3042 - assign { } { } - assign $0\wr_pick_dly$1677[0:0]$3043 1'0 - sync always - sync init - update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$3043 - end - attribute \src "libresoc.v:41463.7-41463.32" - process $proc$libresoc.v:41463$3044 - assign { } { } - assign $0\wr_pick_dly$1693[0:0]$3045 1'0 - sync always - sync init - update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$3045 - end - attribute \src "libresoc.v:41467.7-41467.32" - process $proc$libresoc.v:41467$3046 - assign { } { } - assign $0\wr_pick_dly$1737[0:0]$3047 1'0 - sync always - sync init - update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$3047 - end - attribute \src "libresoc.v:41471.7-41471.32" - process $proc$libresoc.v:41471$3048 - assign { } { } - assign $0\wr_pick_dly$1753[0:0]$3049 1'0 - sync always - sync init - update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$3049 - end - attribute \src "libresoc.v:41475.7-41475.32" - process $proc$libresoc.v:41475$3050 - assign { } { } - assign $0\wr_pick_dly$1777[0:0]$3051 1'0 - sync always - sync init - update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$3051 - end - attribute \src "libresoc.v:41479.7-41479.32" - process $proc$libresoc.v:41479$3052 - assign { } { } - assign $0\wr_pick_dly$1797[0:0]$3053 1'0 - sync always - sync init - update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$3053 - end - attribute \src "libresoc.v:41483.7-41483.31" - process $proc$libresoc.v:41483$3054 - assign { } { } - assign $0\wr_pick_dly$981[0:0]$3055 1'0 - sync always - sync init - update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$3055 - end - attribute \src "libresoc.v:42445.3-42446.51" - process $proc$libresoc.v:42445$2278 - assign { } { } - assign $0\wr_pick_dly$1797[0:0]$2279 \wr_pick_dly$1797$next - sync posedge \coresync_clk - update \wr_pick_dly$1797 $0\wr_pick_dly$1797[0:0]$2279 - end - attribute \src "libresoc.v:42447.3-42448.51" - process $proc$libresoc.v:42447$2280 - assign { } { } - assign $0\wr_pick_dly$1777[0:0]$2281 \wr_pick_dly$1777$next - sync posedge \coresync_clk - update \wr_pick_dly$1777 $0\wr_pick_dly$1777[0:0]$2281 - end - attribute \src "libresoc.v:42449.3-42450.51" - process $proc$libresoc.v:42449$2282 - assign { } { } - assign $0\wr_pick_dly$1753[0:0]$2283 \wr_pick_dly$1753$next - sync posedge \coresync_clk - update \wr_pick_dly$1753 $0\wr_pick_dly$1753[0:0]$2283 - end - attribute \src "libresoc.v:42451.3-42452.51" - process $proc$libresoc.v:42451$2284 - assign { } { } - assign $0\wr_pick_dly$1737[0:0]$2285 \wr_pick_dly$1737$next - sync posedge \coresync_clk - update \wr_pick_dly$1737 $0\wr_pick_dly$1737[0:0]$2285 - end - attribute \src "libresoc.v:42453.3-42454.51" - process $proc$libresoc.v:42453$2286 - assign { } { } - assign $0\wr_pick_dly$1693[0:0]$2287 \wr_pick_dly$1693$next - sync posedge \coresync_clk - update \wr_pick_dly$1693 $0\wr_pick_dly$1693[0:0]$2287 - end - attribute \src "libresoc.v:42455.3-42456.51" - process $proc$libresoc.v:42455$2288 - assign { } { } - assign $0\wr_pick_dly$1677[0:0]$2289 \wr_pick_dly$1677$next - sync posedge \coresync_clk - update \wr_pick_dly$1677 $0\wr_pick_dly$1677[0:0]$2289 - end - attribute \src "libresoc.v:42457.3-42458.51" - process $proc$libresoc.v:42457$2290 - assign { } { } - assign $0\wr_pick_dly$1661[0:0]$2291 \wr_pick_dly$1661$next - sync posedge \coresync_clk - update \wr_pick_dly$1661 $0\wr_pick_dly$1661[0:0]$2291 - end - attribute \src "libresoc.v:42459.3-42460.51" - process $proc$libresoc.v:42459$2292 - assign { } { } - assign $0\wr_pick_dly$1645[0:0]$2293 \wr_pick_dly$1645$next - sync posedge \coresync_clk - update \wr_pick_dly$1645 $0\wr_pick_dly$1645[0:0]$2293 - end - attribute \src "libresoc.v:42461.3-42462.51" - process $proc$libresoc.v:42461$2294 - assign { } { } - assign $0\wr_pick_dly$1626[0:0]$2295 \wr_pick_dly$1626$next - sync posedge \coresync_clk - update \wr_pick_dly$1626 $0\wr_pick_dly$1626[0:0]$2295 - end - attribute \src "libresoc.v:42463.3-42464.51" - process $proc$libresoc.v:42463$2296 - assign { } { } - assign $0\wr_pick_dly$1584[0:0]$2297 \wr_pick_dly$1584$next - sync posedge \coresync_clk - update \wr_pick_dly$1584 $0\wr_pick_dly$1584[0:0]$2297 - end - attribute \src "libresoc.v:42465.3-42466.51" - process $proc$libresoc.v:42465$2298 - assign { } { } - assign $0\wr_pick_dly$1568[0:0]$2299 \wr_pick_dly$1568$next - sync posedge \coresync_clk - update \wr_pick_dly$1568 $0\wr_pick_dly$1568[0:0]$2299 - end - attribute \src "libresoc.v:42467.3-42468.51" - process $proc$libresoc.v:42467$2300 - assign { } { } - assign $0\wr_pick_dly$1552[0:0]$2301 \wr_pick_dly$1552$next - sync posedge \coresync_clk - update \wr_pick_dly$1552 $0\wr_pick_dly$1552[0:0]$2301 - end - attribute \src "libresoc.v:42469.3-42470.51" - process $proc$libresoc.v:42469$2302 - assign { } { } - assign $0\wr_pick_dly$1536[0:0]$2303 \wr_pick_dly$1536$next - sync posedge \coresync_clk - update \wr_pick_dly$1536 $0\wr_pick_dly$1536[0:0]$2303 - end - attribute \src "libresoc.v:42471.3-42472.51" - process $proc$libresoc.v:42471$2304 - assign { } { } - assign $0\wr_pick_dly$1500[0:0]$2305 \wr_pick_dly$1500$next - sync posedge \coresync_clk - update \wr_pick_dly$1500 $0\wr_pick_dly$1500[0:0]$2305 - end - attribute \src "libresoc.v:42473.3-42474.51" - process $proc$libresoc.v:42473$2306 - assign { } { } - assign $0\wr_pick_dly$1484[0:0]$2307 \wr_pick_dly$1484$next - sync posedge \coresync_clk - update \wr_pick_dly$1484 $0\wr_pick_dly$1484[0:0]$2307 - end - attribute \src "libresoc.v:42475.3-42476.51" - process $proc$libresoc.v:42475$2308 - assign { } { } - assign $0\wr_pick_dly$1468[0:0]$2309 \wr_pick_dly$1468$next - sync posedge \coresync_clk - update \wr_pick_dly$1468 $0\wr_pick_dly$1468[0:0]$2309 - end - attribute \src "libresoc.v:42477.3-42478.51" - process $proc$libresoc.v:42477$2310 - assign { } { } - assign $0\wr_pick_dly$1452[0:0]$2311 \wr_pick_dly$1452$next - sync posedge \coresync_clk - update \wr_pick_dly$1452 $0\wr_pick_dly$1452[0:0]$2311 - end - attribute \src "libresoc.v:42479.3-42480.51" - process $proc$libresoc.v:42479$2312 - assign { } { } - assign $0\wr_pick_dly$1418[0:0]$2313 \wr_pick_dly$1418$next - sync posedge \coresync_clk - update \wr_pick_dly$1418 $0\wr_pick_dly$1418[0:0]$2313 - end - attribute \src "libresoc.v:42481.3-42482.51" - process $proc$libresoc.v:42481$2314 - assign { } { } - assign $0\wr_pick_dly$1402[0:0]$2315 \wr_pick_dly$1402$next - sync posedge \coresync_clk - update \wr_pick_dly$1402 $0\wr_pick_dly$1402[0:0]$2315 - end - attribute \src "libresoc.v:42483.3-42484.51" - process $proc$libresoc.v:42483$2316 - assign { } { } - assign $0\wr_pick_dly$1386[0:0]$2317 \wr_pick_dly$1386$next - sync posedge \coresync_clk - update \wr_pick_dly$1386 $0\wr_pick_dly$1386[0:0]$2317 - end - attribute \src "libresoc.v:42485.3-42486.51" - process $proc$libresoc.v:42485$2318 - assign { } { } - assign $0\wr_pick_dly$1339[0:0]$2319 \wr_pick_dly$1339$next - sync posedge \coresync_clk - update \wr_pick_dly$1339 $0\wr_pick_dly$1339[0:0]$2319 - end - attribute \src "libresoc.v:42487.3-42488.51" - process $proc$libresoc.v:42487$2320 - assign { } { } - assign $0\wr_pick_dly$1319[0:0]$2321 \wr_pick_dly$1319$next - sync posedge \coresync_clk - update \wr_pick_dly$1319 $0\wr_pick_dly$1319[0:0]$2321 - end - attribute \src "libresoc.v:42489.3-42490.51" - process $proc$libresoc.v:42489$2322 - assign { } { } - assign $0\wr_pick_dly$1299[0:0]$2323 \wr_pick_dly$1299$next - sync posedge \coresync_clk - update \wr_pick_dly$1299 $0\wr_pick_dly$1299[0:0]$2323 - end - attribute \src "libresoc.v:42491.3-42492.51" - process $proc$libresoc.v:42491$2324 - assign { } { } - assign $0\wr_pick_dly$1279[0:0]$2325 \wr_pick_dly$1279$next - sync posedge \coresync_clk - update \wr_pick_dly$1279 $0\wr_pick_dly$1279[0:0]$2325 - end - attribute \src "libresoc.v:42493.3-42494.51" - process $proc$libresoc.v:42493$2326 - assign { } { } - assign $0\wr_pick_dly$1259[0:0]$2327 \wr_pick_dly$1259$next - sync posedge \coresync_clk - update \wr_pick_dly$1259 $0\wr_pick_dly$1259[0:0]$2327 - end - attribute \src "libresoc.v:42495.3-42496.51" - process $proc$libresoc.v:42495$2328 - assign { } { } - assign $0\wr_pick_dly$1239[0:0]$2329 \wr_pick_dly$1239$next - sync posedge \coresync_clk - update \wr_pick_dly$1239 $0\wr_pick_dly$1239[0:0]$2329 - end - attribute \src "libresoc.v:42497.3-42498.51" - process $proc$libresoc.v:42497$2330 - assign { } { } - assign $0\wr_pick_dly$1211[0:0]$2331 \wr_pick_dly$1211$next - sync posedge \coresync_clk - update \wr_pick_dly$1211 $0\wr_pick_dly$1211[0:0]$2331 - end - attribute \src "libresoc.v:42499.3-42500.51" - process $proc$libresoc.v:42499$2332 - assign { } { } - assign $0\wr_pick_dly$1138[0:0]$2333 \wr_pick_dly$1138$next - sync posedge \coresync_clk - update \wr_pick_dly$1138 $0\wr_pick_dly$1138[0:0]$2333 - end - attribute \src "libresoc.v:42501.3-42502.51" - process $proc$libresoc.v:42501$2334 - assign { } { } - assign $0\wr_pick_dly$1120[0:0]$2335 \wr_pick_dly$1120$next - sync posedge \coresync_clk - update \wr_pick_dly$1120 $0\wr_pick_dly$1120[0:0]$2335 - end - attribute \src "libresoc.v:42503.3-42504.51" - process $proc$libresoc.v:42503$2336 - assign { } { } - assign $0\wr_pick_dly$1101[0:0]$2337 \wr_pick_dly$1101$next - sync posedge \coresync_clk - update \wr_pick_dly$1101 $0\wr_pick_dly$1101[0:0]$2337 - end - attribute \src "libresoc.v:42505.3-42506.51" - process $proc$libresoc.v:42505$2338 - assign { } { } - assign $0\wr_pick_dly$1081[0:0]$2339 \wr_pick_dly$1081$next - sync posedge \coresync_clk - update \wr_pick_dly$1081 $0\wr_pick_dly$1081[0:0]$2339 - end - attribute \src "libresoc.v:42507.3-42508.51" - process $proc$libresoc.v:42507$2340 - assign { } { } - assign $0\wr_pick_dly$1061[0:0]$2341 \wr_pick_dly$1061$next - sync posedge \coresync_clk - update \wr_pick_dly$1061 $0\wr_pick_dly$1061[0:0]$2341 - end - attribute \src "libresoc.v:42509.3-42510.51" - process $proc$libresoc.v:42509$2342 - assign { } { } - assign $0\wr_pick_dly$1039[0:0]$2343 \wr_pick_dly$1039$next - sync posedge \coresync_clk - update \wr_pick_dly$1039 $0\wr_pick_dly$1039[0:0]$2343 - end - attribute \src "libresoc.v:42511.3-42512.51" - process $proc$libresoc.v:42511$2344 - assign { } { } - assign $0\wr_pick_dly$1021[0:0]$2345 \wr_pick_dly$1021$next - sync posedge \coresync_clk - update \wr_pick_dly$1021 $0\wr_pick_dly$1021[0:0]$2345 - end - attribute \src "libresoc.v:42513.3-42514.51" - process $proc$libresoc.v:42513$2346 - assign { } { } - assign $0\wr_pick_dly$1000[0:0]$2347 \wr_pick_dly$1000$next - sync posedge \coresync_clk - update \wr_pick_dly$1000 $0\wr_pick_dly$1000[0:0]$2347 - end - attribute \src "libresoc.v:42515.3-42516.49" - process $proc$libresoc.v:42515$2348 - assign { } { } - assign $0\wr_pick_dly$981[0:0]$2349 \wr_pick_dly$981$next - sync posedge \coresync_clk - update \wr_pick_dly$981 $0\wr_pick_dly$981[0:0]$2349 - end - attribute \src "libresoc.v:42517.3-42518.39" - process $proc$libresoc.v:42517$2350 - assign { } { } - assign $0\wr_pick_dly[0:0] \wr_pick_dly$next - sync posedge \coresync_clk - update \wr_pick_dly $0\wr_pick_dly[0:0] - end - attribute \src "libresoc.v:42519.3-42520.53" - process $proc$libresoc.v:42519$2351 - assign { } { } - assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next - sync posedge \coresync_clk - update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] - end - attribute \src "libresoc.v:42521.3-42522.59" - process $proc$libresoc.v:42521$2352 - assign { } { } - assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next - sync posedge \coresync_clk - update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] - end - attribute \src "libresoc.v:42523.3-42524.63" - process $proc$libresoc.v:42523$2353 - assign { } { } - assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next - sync posedge \coresync_clk - update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] - end - attribute \src "libresoc.v:42525.3-42526.57" - process $proc$libresoc.v:42525$2354 - assign { } { } - assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next - sync posedge \coresync_clk - update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] - end - attribute \src "libresoc.v:42527.3-42528.59" - process $proc$libresoc.v:42527$2355 - assign { } { } - assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next - sync posedge \coresync_clk - update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] - end - attribute \src "libresoc.v:42529.3-42530.63" - process $proc$libresoc.v:42529$2356 - assign { } { } - assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next - sync posedge \coresync_clk - update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] - end - attribute \src "libresoc.v:42531.3-42532.49" - process $proc$libresoc.v:42531$2357 - assign { } { } - assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] - end - attribute \src "libresoc.v:42533.3-42534.49" - process $proc$libresoc.v:42533$2358 - assign { } { } - assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] - end - attribute \src "libresoc.v:42535.3-42536.57" - process $proc$libresoc.v:42535$2359 - assign { } { } - assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next - sync posedge \coresync_clk - update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] - end - attribute \src "libresoc.v:42537.3-42538.49" - process $proc$libresoc.v:42537$2360 - assign { } { } - assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] - end - attribute \src "libresoc.v:42539.3-42540.55" - process $proc$libresoc.v:42539$2361 - assign { } { } - assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next - sync posedge \coresync_clk - update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] - end - attribute \src "libresoc.v:42541.3-42542.57" - process $proc$libresoc.v:42541$2362 - assign { } { } - assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next - sync posedge \coresync_clk - update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] - end - attribute \src "libresoc.v:42543.3-42544.67" - process $proc$libresoc.v:42543$2363 - assign { } { } - assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next - sync posedge \coresync_clk - update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] - end - attribute \src "libresoc.v:42545.3-42546.57" - process $proc$libresoc.v:42545$2364 - assign { } { } - assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next - sync posedge \coresync_clk - update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] - end - attribute \src "libresoc.v:42547.3-42548.57" - process $proc$libresoc.v:42547$2365 - assign { } { } - assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next - sync posedge \coresync_clk - update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] - end - attribute \src "libresoc.v:42549.3-42550.67" - process $proc$libresoc.v:42549$2366 - assign { } { } - assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next - sync posedge \coresync_clk - update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] - end - attribute \src "libresoc.v:42551.3-42552.57" - process $proc$libresoc.v:42551$2367 - assign { } { } - assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next - sync posedge \coresync_clk - update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] - end - attribute \src "libresoc.v:42553.3-42554.57" - process $proc$libresoc.v:42553$2368 - assign { } { } - assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next - sync posedge \coresync_clk - update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] - end - attribute \src "libresoc.v:42555.3-42556.57" - process $proc$libresoc.v:42555$2369 - assign { } { } - assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next - sync posedge \coresync_clk - update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] - end - attribute \src "libresoc.v:42557.3-42558.65" - process $proc$libresoc.v:42557$2370 - assign { } { } - assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next - sync posedge \coresync_clk - update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] - end - attribute \src "libresoc.v:42559.3-42560.57" - process $proc$libresoc.v:42559$2371 - assign { } { } - assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next - sync posedge \coresync_clk - update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] - end - attribute \src "libresoc.v:42561.3-42562.51" - process $proc$libresoc.v:42561$2372 - assign { } { } - assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next - sync posedge \coresync_clk - update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] - end - attribute \src "libresoc.v:42563.3-42564.59" - process $proc$libresoc.v:42563$2373 - assign { } { } - assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next - sync posedge \coresync_clk - update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] - end - attribute \src "libresoc.v:42565.3-42566.51" - process $proc$libresoc.v:42565$2374 - assign { } { } - assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next - sync posedge \coresync_clk - update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] - end - attribute \src "libresoc.v:42567.3-42568.59" - process $proc$libresoc.v:42567$2375 - assign { } { } - assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next - sync posedge \coresync_clk - update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] - end - attribute \src "libresoc.v:42569.3-42570.49" - process $proc$libresoc.v:42569$2376 - assign { } { } - assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next - sync posedge \coresync_clk - update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] - end - attribute \src "libresoc.v:42571.3-42572.49" - process $proc$libresoc.v:42571$2377 - assign { } { } - assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next - sync posedge \coresync_clk - update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] - end - attribute \src "libresoc.v:42573.3-42574.57" - process $proc$libresoc.v:42573$2378 - assign { } { } - assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next - sync posedge \coresync_clk - update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] - end - attribute \src "libresoc.v:42575.3-42576.51" - process $proc$libresoc.v:42575$2379 - assign { } { } - assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next - sync posedge \coresync_clk - update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] - end - attribute \src "libresoc.v:42577.3-42578.47" - process $proc$libresoc.v:42577$2380 - assign { } { } - assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next - sync posedge \coresync_clk - update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] - end - attribute \src "libresoc.v:42579.3-42580.49" - process $proc$libresoc.v:42579$2381 - assign { } { } - assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next - sync posedge \coresync_clk - update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] - end - attribute \src "libresoc.v:42581.3-42582.51" - process $proc$libresoc.v:42581$2382 - assign { } { } - assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next - sync posedge \coresync_clk - update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] - end - attribute \src "libresoc.v:42583.3-42584.59" - process $proc$libresoc.v:42583$2383 - assign { } { } - assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next - sync posedge \coresync_clk - update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] - end - attribute \src "libresoc.v:42585.3-42586.49" - process $proc$libresoc.v:42585$2384 - assign { } { } - assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next - sync posedge \coresync_clk - update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] - end - attribute \src "libresoc.v:42587.3-42588.49" - process $proc$libresoc.v:42587$2385 - assign { } { } - assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next - sync posedge \coresync_clk - update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] - end - attribute \src "libresoc.v:42589.3-42590.49" - process $proc$libresoc.v:42589$2386 - assign { } { } - assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next - sync posedge \coresync_clk - update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] - end - attribute \src "libresoc.v:42591.3-42592.57" - process $proc$libresoc.v:42591$2387 - assign { } { } - assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next - sync posedge \coresync_clk - update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] - end - attribute \src "libresoc.v:42593.3-42594.51" - process $proc$libresoc.v:42593$2388 - assign { } { } - assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next - sync posedge \coresync_clk - update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] - end - attribute \src "libresoc.v:42595.3-42596.47" - process $proc$libresoc.v:42595$2389 - assign { } { } - assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next - sync posedge \coresync_clk - update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] - end - attribute \src "libresoc.v:42597.3-42598.49" - process $proc$libresoc.v:42597$2390 - assign { } { } - assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next - sync posedge \coresync_clk - update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] - end - attribute \src "libresoc.v:42599.3-42600.49" - process $proc$libresoc.v:42599$2391 - assign { } { } - assign $0\core_terminate_o[0:0] \core_terminate_o$next - sync posedge \coresync_clk - update \core_terminate_o $0\core_terminate_o[0:0] - end - attribute \src "libresoc.v:42601.3-42602.31" - process $proc$libresoc.v:42601$2392 - assign { } { } - assign $0\counter[1:0] \counter$next - sync posedge \coresync_clk - update \counter $0\counter[1:0] - end - attribute \src "libresoc.v:43332.3-43360.6" - process $proc$libresoc.v:43332$2393 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43333.5-43333.29" - switch \initial - attribute \src "libresoc.v:43333.9-43333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn - case - assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] - end - attribute \src "libresoc.v:43361.3-43389.6" - process $proc$libresoc.v:43361$2394 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:43362.5-43362.29" - switch \initial - attribute \src "libresoc.v:43362.9-43362.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit - case - assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] - end - attribute \src "libresoc.v:43390.3-43418.6" - process $proc$libresoc.v:43390$2395 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$23[0:0]$2396 $1\fus_cu_issue_i$23[0:0]$2397 - attribute \src "libresoc.v:43391.5-43391.29" - switch \initial - attribute \src "libresoc.v:43391.9-43391.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$23[0:0]$2397 $2\fus_cu_issue_i$23[0:0]$2398 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$23[0:0]$2398 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$23[0:0]$2398 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$23[0:0]$2398 $3\fus_cu_issue_i$23[0:0]$2399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$23[0:0]$2399 \issue_i - case - assign $3\fus_cu_issue_i$23[0:0]$2399 1'0 - end - end - case - assign $1\fus_cu_issue_i$23[0:0]$2397 1'0 - end - sync always - update \fus_cu_issue_i$23 $0\fus_cu_issue_i$23[0:0]$2396 - end - attribute \src "libresoc.v:43419.3-43447.6" - process $proc$libresoc.v:43419$2400 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$25[5:0]$2401 $1\fus_cu_rdmaskn_i$25[5:0]$2402 - attribute \src "libresoc.v:43420.5-43420.29" - switch \initial - attribute \src "libresoc.v:43420.9-43420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$25[5:0]$2402 $2\fus_cu_rdmaskn_i$25[5:0]$2403 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$25[5:0]$2403 6'000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$25[5:0]$2403 6'000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$25[5:0]$2403 $3\fus_cu_rdmaskn_i$25[5:0]$2404 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$25[5:0]$2404 \$263 - case - assign $3\fus_cu_rdmaskn_i$25[5:0]$2404 6'000000 - end - end - case - assign $1\fus_cu_rdmaskn_i$25[5:0]$2402 6'000000 - end - sync always - update \fus_cu_rdmaskn_i$25 $0\fus_cu_rdmaskn_i$25[5:0]$2401 - end - attribute \src "libresoc.v:43448.3-43476.6" - process $proc$libresoc.v:43448$2405 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:43449.5-43449.29" - switch \initial - attribute \src "libresoc.v:43449.9-43449.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV__insn_type - case - assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] - end - attribute \src "libresoc.v:43477.3-43505.6" - process $proc$libresoc.v:43477$2406 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__fn_unit[11:0] $1\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "libresoc.v:43478.5-43478.29" - switch \initial - attribute \src "libresoc.v:43478.9-43478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__fn_unit[11:0] $2\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__fn_unit[11:0] $3\fus_oper_i_alu_div0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV__fn_unit - case - assign $3\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[11:0] - end - attribute \src "libresoc.v:43506.3-43535.6" - process $proc$libresoc.v:43506$2407 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:43507.5-43507.29" - switch \initial - attribute \src "libresoc.v:43507.9-43507.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV__imm_data__ok \dec_DIV_DIV__imm_data__data } - case - assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] - update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - end - attribute \src "libresoc.v:43536.3-43565.6" - process $proc$libresoc.v:43536$2408 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] - assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:43537.5-43537.29" - switch \initial - attribute \src "libresoc.v:43537.9-43537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] - assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] - assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV__rc__ok \dec_DIV_DIV__rc__rc } - case - assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] - update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] - end - attribute \src "libresoc.v:43566.3-43595.6" - process $proc$libresoc.v:43566$2409 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] - assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:43567.5-43567.29" - switch \initial - attribute \src "libresoc.v:43567.9-43567.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] - assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] - assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV__oe__ok \dec_DIV_DIV__oe__oe } - case - assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] - update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] - end - attribute \src "libresoc.v:43596.3-43624.6" - process $proc$libresoc.v:43596$2410 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:43597.5-43597.29" - switch \initial - attribute \src "libresoc.v:43597.9-43597.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV__invert_in - case - assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] - end - attribute \src "libresoc.v:43625.3-43653.6" - process $proc$libresoc.v:43625$2411 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43626.5-43626.29" - switch \initial - attribute \src "libresoc.v:43626.9-43626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV__zero_a - case - assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] - end - attribute \src "libresoc.v:43654.3-43682.6" - process $proc$libresoc.v:43654$2412 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:43655.5-43655.29" - switch \initial - attribute \src "libresoc.v:43655.9-43655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV__input_carry - case - assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 - end - end - case - assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 - end - sync always - update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] - end - attribute \src "libresoc.v:43683.3-43711.6" - process $proc$libresoc.v:43683$2413 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:43684.5-43684.29" - switch \initial - attribute \src "libresoc.v:43684.9-43684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV__invert_out - case - assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] - end - attribute \src "libresoc.v:43712.3-43740.6" - process $proc$libresoc.v:43712$2414 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:43713.5-43713.29" - switch \initial - attribute \src "libresoc.v:43713.9-43713.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV__write_cr0 - case - assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] - end - attribute \src "libresoc.v:43741.3-43769.6" - process $proc$libresoc.v:43741$2415 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:43742.5-43742.29" - switch \initial - attribute \src "libresoc.v:43742.9-43742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV__output_carry - case - assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] - end - attribute \src "libresoc.v:43770.3-43798.6" - process $proc$libresoc.v:43770$2416 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:43771.5-43771.29" - switch \initial - attribute \src "libresoc.v:43771.9-43771.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV__is_32bit - case - assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] - end - attribute \src "libresoc.v:43799.3-43827.6" - process $proc$libresoc.v:43799$2417 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:43800.5-43800.29" - switch \initial - attribute \src "libresoc.v:43800.9-43800.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV__is_signed - case - assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] - end - attribute \src "libresoc.v:43828.3-43856.6" - process $proc$libresoc.v:43828$2418 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:43829.5-43829.29" - switch \initial - attribute \src "libresoc.v:43829.9-43829.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV__data_len - case - assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] - end - attribute \src "libresoc.v:43857.3-43885.6" - process $proc$libresoc.v:43857$2419 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:43858.5-43858.29" - switch \initial - attribute \src "libresoc.v:43858.9-43858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_div0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_div0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV__insn - case - assign $3\fus_oper_i_alu_div0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_div0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] - end - attribute \src "libresoc.v:43886.3-43914.6" - process $proc$libresoc.v:43886$2420 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$26[0:0]$2421 $1\fus_cu_issue_i$26[0:0]$2422 - attribute \src "libresoc.v:43887.5-43887.29" - switch \initial - attribute \src "libresoc.v:43887.9-43887.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$26[0:0]$2422 $2\fus_cu_issue_i$26[0:0]$2423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$26[0:0]$2423 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$26[0:0]$2423 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$26[0:0]$2423 $3\fus_cu_issue_i$26[0:0]$2424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$26[0:0]$2424 \issue_i - case - assign $3\fus_cu_issue_i$26[0:0]$2424 1'0 - end - end - case - assign $1\fus_cu_issue_i$26[0:0]$2422 1'0 - end - sync always - update \fus_cu_issue_i$26 $0\fus_cu_issue_i$26[0:0]$2421 - end - attribute \src "libresoc.v:43915.3-43943.6" - process $proc$libresoc.v:43915$2425 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$28[2:0]$2426 $1\fus_cu_rdmaskn_i$28[2:0]$2427 - attribute \src "libresoc.v:43916.5-43916.29" - switch \initial - attribute \src "libresoc.v:43916.9-43916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$28[2:0]$2427 $2\fus_cu_rdmaskn_i$28[2:0]$2428 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$28[2:0]$2428 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$28[2:0]$2428 3'000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$28[2:0]$2428 $3\fus_cu_rdmaskn_i$28[2:0]$2429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$28[2:0]$2429 \$293 - case - assign $3\fus_cu_rdmaskn_i$28[2:0]$2429 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$28[2:0]$2427 3'000 - end - sync always - update \fus_cu_rdmaskn_i$28 $0\fus_cu_rdmaskn_i$28[2:0]$2426 - end - attribute \src "libresoc.v:43944.3-43972.6" - process $proc$libresoc.v:43944$2430 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:43945.5-43945.29" - switch \initial - attribute \src "libresoc.v:43945.9-43945.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL__insn_type - case - assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] - end - attribute \src "libresoc.v:43973.3-44001.6" - process $proc$libresoc.v:43973$2431 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__fn_unit[11:0] $1\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "libresoc.v:43974.5-43974.29" - switch \initial - attribute \src "libresoc.v:43974.9-43974.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] $2\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] $3\fus_oper_i_alu_mul0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL__fn_unit - case - assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[11:0] - end - attribute \src "libresoc.v:44002.3-44031.6" - process $proc$libresoc.v:44002$2432 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44003.5-44003.29" - switch \initial - attribute \src "libresoc.v:44003.9-44003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL__imm_data__ok \dec_MUL_MUL__imm_data__data } - case - assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - end - attribute \src "libresoc.v:44032.3-44061.6" - process $proc$libresoc.v:44032$2433 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] - assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44033.5-44033.29" - switch \initial - attribute \src "libresoc.v:44033.9-44033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] - assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] - assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL__rc__ok \dec_MUL_MUL__rc__rc } - case - assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] - update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] - end - attribute \src "libresoc.v:44062.3-44091.6" - process $proc$libresoc.v:44062$2434 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] - assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44063.5-44063.29" - switch \initial - attribute \src "libresoc.v:44063.9-44063.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] - assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] - assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL__oe__ok \dec_MUL_MUL__oe__oe } - case - assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] - update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] - end - attribute \src "libresoc.v:44092.3-44120.6" - process $proc$libresoc.v:44092$2435 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44093.5-44093.29" - switch \initial - attribute \src "libresoc.v:44093.9-44093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL__write_cr0 - case - assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] - end - attribute \src "libresoc.v:44121.3-44149.6" - process $proc$libresoc.v:44121$2436 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44122.5-44122.29" - switch \initial - attribute \src "libresoc.v:44122.9-44122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL__is_32bit - case - assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] - end - attribute \src "libresoc.v:44150.3-44178.6" - process $proc$libresoc.v:44150$2437 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44151.5-44151.29" - switch \initial - attribute \src "libresoc.v:44151.9-44151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL__is_signed - case - assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] - end - attribute \src "libresoc.v:44179.3-44207.6" - process $proc$libresoc.v:44179$2438 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44180.5-44180.29" - switch \initial - attribute \src "libresoc.v:44180.9-44180.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL__insn - case - assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] - end - attribute \src "libresoc.v:44208.3-44236.6" - process $proc$libresoc.v:44208$2439 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$29[0:0]$2440 $1\fus_cu_issue_i$29[0:0]$2441 - attribute \src "libresoc.v:44209.5-44209.29" - switch \initial - attribute \src "libresoc.v:44209.9-44209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$29[0:0]$2441 $2\fus_cu_issue_i$29[0:0]$2442 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$29[0:0]$2442 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$29[0:0]$2442 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$29[0:0]$2442 $3\fus_cu_issue_i$29[0:0]$2443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$29[0:0]$2443 \issue_i - case - assign $3\fus_cu_issue_i$29[0:0]$2443 1'0 - end - end - case - assign $1\fus_cu_issue_i$29[0:0]$2441 1'0 - end - sync always - update \fus_cu_issue_i$29 $0\fus_cu_issue_i$29[0:0]$2440 - end - attribute \src "libresoc.v:44237.3-44265.6" - process $proc$libresoc.v:44237$2444 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$31[2:0]$2445 $1\fus_cu_rdmaskn_i$31[2:0]$2446 - attribute \src "libresoc.v:44238.5-44238.29" - switch \initial - attribute \src "libresoc.v:44238.9-44238.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$31[2:0]$2446 $2\fus_cu_rdmaskn_i$31[2:0]$2447 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$31[2:0]$2447 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$31[2:0]$2447 3'000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$31[2:0]$2447 $3\fus_cu_rdmaskn_i$31[2:0]$2448 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$31[2:0]$2448 \$307 - case - assign $3\fus_cu_rdmaskn_i$31[2:0]$2448 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$31[2:0]$2446 3'000 - end - sync always - update \fus_cu_rdmaskn_i$31 $0\fus_cu_rdmaskn_i$31[2:0]$2445 - end - attribute \src "libresoc.v:44266.3-44294.6" - process $proc$libresoc.v:44266$2449 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44267.5-44267.29" - switch \initial - attribute \src "libresoc.v:44267.9-44267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT__insn_type - case - assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - end - attribute \src "libresoc.v:44295.3-44323.6" - process $proc$libresoc.v:44295$2450 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "libresoc.v:44296.5-44296.29" - switch \initial - attribute \src "libresoc.v:44296.9-44296.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit - case - assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] - end - attribute \src "libresoc.v:44324.3-44353.6" - process $proc$libresoc.v:44324$2451 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44325.5-44325.29" - switch \initial - attribute \src "libresoc.v:44325.9-44325.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data } - case - assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - end - attribute \src "libresoc.v:44354.3-44383.6" - process $proc$libresoc.v:44354$2452 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:44355.5-44355.29" - switch \initial - attribute \src "libresoc.v:44355.9-44355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__rc } - case - assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - end - attribute \src "libresoc.v:44384.3-44413.6" - process $proc$libresoc.v:44384$2453 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:44385.5-44385.29" - switch \initial - attribute \src "libresoc.v:44385.9-44385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__oe } - case - assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - end - attribute \src "libresoc.v:44414.3-44442.6" - process $proc$libresoc.v:44414$2454 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:44415.5-44415.29" - switch \initial - attribute \src "libresoc.v:44415.9-44415.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 - case - assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - end - attribute \src "libresoc.v:44443.3-44471.6" - process $proc$libresoc.v:44443$2455 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:44444.5-44444.29" - switch \initial - attribute \src "libresoc.v:44444.9-44444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] \dec_SHIFT_ROT_SHIFT_ROT__invert_in - case - assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - end - attribute \src "libresoc.v:44472.3-44500.6" - process $proc$libresoc.v:44472$2456 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:44473.5-44473.29" - switch \initial - attribute \src "libresoc.v:44473.9-44473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT__input_carry - case - assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 - end - sync always - update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - end - attribute \src "libresoc.v:44501.3-44529.6" - process $proc$libresoc.v:44501$2457 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:44502.5-44502.29" - switch \initial - attribute \src "libresoc.v:44502.9-44502.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_carry - case - assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - end - attribute \src "libresoc.v:44530.3-44558.6" - process $proc$libresoc.v:44530$2458 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:44531.5-44531.29" - switch \initial - attribute \src "libresoc.v:44531.9-44531.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__input_cr - case - assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - end - attribute \src "libresoc.v:44559.3-44587.6" - process $proc$libresoc.v:44559$2459 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:44560.5-44560.29" - switch \initial - attribute \src "libresoc.v:44560.9-44560.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_cr - case - assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - end - attribute \src "libresoc.v:44588.3-44616.6" - process $proc$libresoc.v:44588$2460 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:44589.5-44589.29" - switch \initial - attribute \src "libresoc.v:44589.9-44589.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_32bit - case - assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - end - attribute \src "libresoc.v:44617.3-44645.6" - process $proc$libresoc.v:44617$2461 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:44618.5-44618.29" - switch \initial - attribute \src "libresoc.v:44618.9-44618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_signed - case - assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - end - attribute \src "libresoc.v:44646.3-44674.6" - process $proc$libresoc.v:44646$2462 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44647.5-44647.29" - switch \initial - attribute \src "libresoc.v:44647.9-44647.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT__insn - case - assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] - end - attribute \src "libresoc.v:44675.3-44703.6" - process $proc$libresoc.v:44675$2463 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$32[0:0]$2464 $1\fus_cu_issue_i$32[0:0]$2465 - attribute \src "libresoc.v:44676.5-44676.29" - switch \initial - attribute \src "libresoc.v:44676.9-44676.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$32[0:0]$2465 $2\fus_cu_issue_i$32[0:0]$2466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$32[0:0]$2466 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$32[0:0]$2466 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$32[0:0]$2466 $3\fus_cu_issue_i$32[0:0]$2467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$32[0:0]$2467 \issue_i - case - assign $3\fus_cu_issue_i$32[0:0]$2467 1'0 - end - end - case - assign $1\fus_cu_issue_i$32[0:0]$2465 1'0 - end - sync always - update \fus_cu_issue_i$32 $0\fus_cu_issue_i$32[0:0]$2464 - end - attribute \src "libresoc.v:44704.3-44732.6" - process $proc$libresoc.v:44704$2468 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$34[4:0]$2469 $1\fus_cu_rdmaskn_i$34[4:0]$2470 - attribute \src "libresoc.v:44705.5-44705.29" - switch \initial - attribute \src "libresoc.v:44705.9-44705.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$34[4:0]$2470 $2\fus_cu_rdmaskn_i$34[4:0]$2471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$34[4:0]$2471 5'00000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$34[4:0]$2471 5'00000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$34[4:0]$2471 $3\fus_cu_rdmaskn_i$34[4:0]$2472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$34[4:0]$2472 \$321 - case - assign $3\fus_cu_rdmaskn_i$34[4:0]$2472 5'00000 - end - end - case - assign $1\fus_cu_rdmaskn_i$34[4:0]$2470 5'00000 - end - sync always - update \fus_cu_rdmaskn_i$34 $0\fus_cu_rdmaskn_i$34[4:0]$2469 - end - attribute \src "libresoc.v:44733.3-44761.6" - process $proc$libresoc.v:44733$2473 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:44734.5-44734.29" - switch \initial - attribute \src "libresoc.v:44734.9-44734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST__insn_type - case - assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - end - attribute \src "libresoc.v:44762.3-44790.6" - process $proc$libresoc.v:44762$2474 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "libresoc.v:44763.5-44763.29" - switch \initial - attribute \src "libresoc.v:44763.9-44763.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST__fn_unit - case - assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] - end - attribute \src "libresoc.v:44791.3-44820.6" - process $proc$libresoc.v:44791$2475 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:44792.5-44792.29" - switch \initial - attribute \src "libresoc.v:44792.9-44792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST__imm_data__ok \dec_LDST_LDST__imm_data__data } - case - assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - end - attribute \src "libresoc.v:44821.3-44849.6" - process $proc$libresoc.v:44821$2476 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:44822.5-44822.29" - switch \initial - attribute \src "libresoc.v:44822.9-44822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST__zero_a - case - assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - end - attribute \src "libresoc.v:44850.3-44879.6" - process $proc$libresoc.v:44850$2477 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:44851.5-44851.29" - switch \initial - attribute \src "libresoc.v:44851.9-44851.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST__rc__ok \dec_LDST_LDST__rc__rc } - case - assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - end - attribute \src "libresoc.v:44880.3-44909.6" - process $proc$libresoc.v:44880$2478 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:44881.5-44881.29" - switch \initial - attribute \src "libresoc.v:44881.9-44881.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST__oe__ok \dec_LDST_LDST__oe__oe } - case - assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - end - attribute \src "libresoc.v:44910.3-44938.6" - process $proc$libresoc.v:44910$2479 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:44911.5-44911.29" - switch \initial - attribute \src "libresoc.v:44911.9-44911.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST__is_32bit - case - assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - end - attribute \src "libresoc.v:44939.3-44967.6" - process $proc$libresoc.v:44939$2480 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:44940.5-44940.29" - switch \initial - attribute \src "libresoc.v:44940.9-44940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST__is_signed - case - assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - end - attribute \src "libresoc.v:44968.3-44996.6" - process $proc$libresoc.v:44968$2481 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:44969.5-44969.29" - switch \initial - attribute \src "libresoc.v:44969.9-44969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST__data_len - case - assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] - end - attribute \src "libresoc.v:44997.3-45025.6" - process $proc$libresoc.v:44997$2482 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:44998.5-44998.29" - switch \initial - attribute \src "libresoc.v:44998.9-44998.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST__byte_reverse - case - assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - end - attribute \src "libresoc.v:45026.3-45054.6" - process $proc$libresoc.v:45026$2483 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45027.5-45027.29" - switch \initial - attribute \src "libresoc.v:45027.9-45027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST__sign_extend - case - assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 - end - sync always - update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - end - attribute \src "libresoc.v:45055.3-45083.6" - process $proc$libresoc.v:45055$2484 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45056.5-45056.29" - switch \initial - attribute \src "libresoc.v:45056.9-45056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST__ldst_mode - case - assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 - end - sync always - update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - end - attribute \src "libresoc.v:45084.3-45112.6" - process $proc$libresoc.v:45084$2485 - assign { } { } - assign { } { } - assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45085.5-45085.29" - switch \initial - attribute \src "libresoc.v:45085.9-45085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST__insn - case - assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 - end - sync always - update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] - end - attribute \src "libresoc.v:45113.3-45141.6" - process $proc$libresoc.v:45113$2486 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$35[0:0]$2487 $1\fus_cu_issue_i$35[0:0]$2488 - attribute \src "libresoc.v:45114.5-45114.29" - switch \initial - attribute \src "libresoc.v:45114.9-45114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$35[0:0]$2488 $2\fus_cu_issue_i$35[0:0]$2489 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$35[0:0]$2489 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$35[0:0]$2489 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$35[0:0]$2489 $3\fus_cu_issue_i$35[0:0]$2490 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$35[0:0]$2490 \issue_i - case - assign $3\fus_cu_issue_i$35[0:0]$2490 1'0 - end - end - case - assign $1\fus_cu_issue_i$35[0:0]$2488 1'0 - end - sync always - update \fus_cu_issue_i$35 $0\fus_cu_issue_i$35[0:0]$2487 - end - attribute \src "libresoc.v:45142.3-45170.6" - process $proc$libresoc.v:45142$2491 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$37[2:0]$2492 $1\fus_cu_rdmaskn_i$37[2:0]$2493 - attribute \src "libresoc.v:45143.5-45143.29" - switch \initial - attribute \src "libresoc.v:45143.9-45143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$37[2:0]$2493 $2\fus_cu_rdmaskn_i$37[2:0]$2494 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$37[2:0]$2494 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$37[2:0]$2494 3'000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$37[2:0]$2494 $3\fus_cu_rdmaskn_i$37[2:0]$2495 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$37[2:0]$2495 \$343 - case - assign $3\fus_cu_rdmaskn_i$37[2:0]$2495 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$37[2:0]$2493 3'000 - end - sync always - update \fus_cu_rdmaskn_i$37 $0\fus_cu_rdmaskn_i$37[2:0]$2492 - end - attribute \src "libresoc.v:45171.3-45179.6" - process $proc$libresoc.v:45171$2496 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_alu0_0$next[0:0]$2497 $1\dp_INT_ra_alu0_0$next[0:0]$2498 - attribute \src "libresoc.v:45172.5-45172.29" - switch \initial - attribute \src "libresoc.v:45172.9-45172.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_alu0_0$next[0:0]$2498 1'0 - case - assign $1\dp_INT_ra_alu0_0$next[0:0]$2498 \rp_INT_ra_alu0_0 - end - sync always - update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2497 - end - attribute \src "libresoc.v:45180.3-45189.6" - process $proc$libresoc.v:45180$2499 - assign { } { } - assign { } { } - assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45181.5-45181.29" - switch \initial - attribute \src "libresoc.v:45181.9-45181.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_alu0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i[63:0] \int_src1__data_o - case - assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i $0\fus_src1_i[63:0] - end - attribute \src "libresoc.v:45190.3-45198.6" - process $proc$libresoc.v:45190$2500 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_cr0_1$next[0:0]$2501 $1\dp_INT_ra_cr0_1$next[0:0]$2502 - attribute \src "libresoc.v:45191.5-45191.29" - switch \initial - attribute \src "libresoc.v:45191.9-45191.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_cr0_1$next[0:0]$2502 1'0 - case - assign $1\dp_INT_ra_cr0_1$next[0:0]$2502 \rp_INT_ra_cr0_1 - end - sync always - update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2501 - end - attribute \src "libresoc.v:45199.3-45208.6" - process $proc$libresoc.v:45199$2503 - assign { } { } - assign { } { } - assign $0\fus_src1_i$40[63:0]$2504 $1\fus_src1_i$40[63:0]$2505 - attribute \src "libresoc.v:45200.5-45200.29" - switch \initial - attribute \src "libresoc.v:45200.9-45200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_cr0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$40[63:0]$2505 \int_src1__data_o - case - assign $1\fus_src1_i$40[63:0]$2505 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$40 $0\fus_src1_i$40[63:0]$2504 - end - attribute \src "libresoc.v:45209.3-45217.6" - process $proc$libresoc.v:45209$2506 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_trap0_2$next[0:0]$2507 $1\dp_INT_ra_trap0_2$next[0:0]$2508 - attribute \src "libresoc.v:45210.5-45210.29" - switch \initial - attribute \src "libresoc.v:45210.9-45210.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_trap0_2$next[0:0]$2508 1'0 - case - assign $1\dp_INT_ra_trap0_2$next[0:0]$2508 \rp_INT_ra_trap0_2 - end - sync always - update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2507 - end - attribute \src "libresoc.v:45218.3-45227.6" - process $proc$libresoc.v:45218$2509 - assign { } { } - assign { } { } - assign $0\fus_src1_i$43[63:0]$2510 $1\fus_src1_i$43[63:0]$2511 - attribute \src "libresoc.v:45219.5-45219.29" - switch \initial - attribute \src "libresoc.v:45219.9-45219.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_trap0_2 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$43[63:0]$2511 \int_src1__data_o - case - assign $1\fus_src1_i$43[63:0]$2511 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$43 $0\fus_src1_i$43[63:0]$2510 - end - attribute \src "libresoc.v:45228.3-45236.6" - process $proc$libresoc.v:45228$2512 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_logical0_3$next[0:0]$2513 $1\dp_INT_ra_logical0_3$next[0:0]$2514 - attribute \src "libresoc.v:45229.5-45229.29" - switch \initial - attribute \src "libresoc.v:45229.9-45229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_logical0_3$next[0:0]$2514 1'0 - case - assign $1\dp_INT_ra_logical0_3$next[0:0]$2514 \rp_INT_ra_logical0_3 - end - sync always - update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2513 - end - attribute \src "libresoc.v:45237.3-45246.6" - process $proc$libresoc.v:45237$2515 - assign { } { } - assign { } { } - assign $0\fus_src1_i$46[63:0]$2516 $1\fus_src1_i$46[63:0]$2517 - attribute \src "libresoc.v:45238.5-45238.29" - switch \initial - attribute \src "libresoc.v:45238.9-45238.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_logical0_3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$46[63:0]$2517 \int_src1__data_o - case - assign $1\fus_src1_i$46[63:0]$2517 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$46 $0\fus_src1_i$46[63:0]$2516 - end - attribute \src "libresoc.v:45247.3-45255.6" - process $proc$libresoc.v:45247$2518 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_spr0_4$next[0:0]$2519 $1\dp_INT_ra_spr0_4$next[0:0]$2520 - attribute \src "libresoc.v:45248.5-45248.29" - switch \initial - attribute \src "libresoc.v:45248.9-45248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_spr0_4$next[0:0]$2520 1'0 - case - assign $1\dp_INT_ra_spr0_4$next[0:0]$2520 \rp_INT_ra_spr0_4 - end - sync always - update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2519 - end - attribute \src "libresoc.v:45256.3-45265.6" - process $proc$libresoc.v:45256$2521 - assign { } { } - assign { } { } - assign $0\fus_src1_i$49[63:0]$2522 $1\fus_src1_i$49[63:0]$2523 - attribute \src "libresoc.v:45257.5-45257.29" - switch \initial - attribute \src "libresoc.v:45257.9-45257.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_spr0_4 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$49[63:0]$2523 \int_src1__data_o - case - assign $1\fus_src1_i$49[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$49 $0\fus_src1_i$49[63:0]$2522 - end - attribute \src "libresoc.v:45266.3-45274.6" - process $proc$libresoc.v:45266$2524 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_div0_5$next[0:0]$2525 $1\dp_INT_ra_div0_5$next[0:0]$2526 - attribute \src "libresoc.v:45267.5-45267.29" - switch \initial - attribute \src "libresoc.v:45267.9-45267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_div0_5$next[0:0]$2526 1'0 - case - assign $1\dp_INT_ra_div0_5$next[0:0]$2526 \rp_INT_ra_div0_5 - end - sync always - update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2525 - end - attribute \src "libresoc.v:45275.3-45284.6" - process $proc$libresoc.v:45275$2527 - assign { } { } - assign { } { } - assign $0\fus_src1_i$52[63:0]$2528 $1\fus_src1_i$52[63:0]$2529 - attribute \src "libresoc.v:45276.5-45276.29" - switch \initial - attribute \src "libresoc.v:45276.9-45276.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_div0_5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$52[63:0]$2529 \int_src1__data_o - case - assign $1\fus_src1_i$52[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$52 $0\fus_src1_i$52[63:0]$2528 - end - attribute \src "libresoc.v:45285.3-45293.6" - process $proc$libresoc.v:45285$2530 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_mul0_6$next[0:0]$2531 $1\dp_INT_ra_mul0_6$next[0:0]$2532 - attribute \src "libresoc.v:45286.5-45286.29" - switch \initial - attribute \src "libresoc.v:45286.9-45286.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_mul0_6$next[0:0]$2532 1'0 - case - assign $1\dp_INT_ra_mul0_6$next[0:0]$2532 \rp_INT_ra_mul0_6 - end - sync always - update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2531 - end - attribute \src "libresoc.v:45294.3-45303.6" - process $proc$libresoc.v:45294$2533 - assign { } { } - assign { } { } - assign $0\fus_src1_i$55[63:0]$2534 $1\fus_src1_i$55[63:0]$2535 - attribute \src "libresoc.v:45295.5-45295.29" - switch \initial - attribute \src "libresoc.v:45295.9-45295.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_mul0_6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$55[63:0]$2535 \int_src1__data_o - case - assign $1\fus_src1_i$55[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$55 $0\fus_src1_i$55[63:0]$2534 - end - attribute \src "libresoc.v:45304.3-45312.6" - process $proc$libresoc.v:45304$2536 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2537 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 - attribute \src "libresoc.v:45305.5-45305.29" - switch \initial - attribute \src "libresoc.v:45305.9-45305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 1'0 - case - assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2538 \rp_INT_ra_shiftrot0_7 - end - sync always - update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2537 - end - attribute \src "libresoc.v:45313.3-45322.6" - process $proc$libresoc.v:45313$2539 - assign { } { } - assign { } { } - assign $0\fus_src1_i$58[63:0]$2540 $1\fus_src1_i$58[63:0]$2541 - attribute \src "libresoc.v:45314.5-45314.29" - switch \initial - attribute \src "libresoc.v:45314.9-45314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_shiftrot0_7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$58[63:0]$2541 \int_src1__data_o - case - assign $1\fus_src1_i$58[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$58 $0\fus_src1_i$58[63:0]$2540 - end - attribute \src "libresoc.v:45323.3-45331.6" - process $proc$libresoc.v:45323$2542 - assign { } { } - assign { } { } - assign $0\dp_INT_ra_ldst0_8$next[0:0]$2543 $1\dp_INT_ra_ldst0_8$next[0:0]$2544 - attribute \src "libresoc.v:45324.5-45324.29" - switch \initial - attribute \src "libresoc.v:45324.9-45324.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2544 1'0 - case - assign $1\dp_INT_ra_ldst0_8$next[0:0]$2544 \rp_INT_ra_ldst0_8 - end - sync always - update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2543 - end - attribute \src "libresoc.v:45332.3-45341.6" - process $proc$libresoc.v:45332$2545 - assign { } { } - assign { } { } - assign $0\fus_src1_i$61[63:0]$2546 $1\fus_src1_i$61[63:0]$2547 - attribute \src "libresoc.v:45333.5-45333.29" - switch \initial - attribute \src "libresoc.v:45333.9-45333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_ra_ldst0_8 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$61[63:0]$2547 \int_src1__data_o - case - assign $1\fus_src1_i$61[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$61 $0\fus_src1_i$61[63:0]$2546 - end - attribute \src "libresoc.v:45342.3-45350.6" - process $proc$libresoc.v:45342$2548 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_alu0_0$next[0:0]$2549 $1\dp_INT_rb_alu0_0$next[0:0]$2550 - attribute \src "libresoc.v:45343.5-45343.29" - switch \initial - attribute \src "libresoc.v:45343.9-45343.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_alu0_0$next[0:0]$2550 1'0 - case - assign $1\dp_INT_rb_alu0_0$next[0:0]$2550 \rp_INT_rb_alu0_0 - end - sync always - update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2549 - end - attribute \src "libresoc.v:45351.3-45360.6" - process $proc$libresoc.v:45351$2551 - assign { } { } - assign { } { } - assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:45352.5-45352.29" - switch \initial - attribute \src "libresoc.v:45352.9-45352.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_alu0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i[63:0] \int_src2__data_o - case - assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i $0\fus_src2_i[63:0] - end - attribute \src "libresoc.v:45361.3-45369.6" - process $proc$libresoc.v:45361$2552 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_cr0_1$next[0:0]$2553 $1\dp_INT_rb_cr0_1$next[0:0]$2554 - attribute \src "libresoc.v:45362.5-45362.29" - switch \initial - attribute \src "libresoc.v:45362.9-45362.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_cr0_1$next[0:0]$2554 1'0 - case - assign $1\dp_INT_rb_cr0_1$next[0:0]$2554 \rp_INT_rb_cr0_1 - end - sync always - update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2553 - end - attribute \src "libresoc.v:45370.3-45379.6" - process $proc$libresoc.v:45370$2555 - assign { } { } - assign { } { } - assign $0\fus_src2_i$62[63:0]$2556 $1\fus_src2_i$62[63:0]$2557 - attribute \src "libresoc.v:45371.5-45371.29" - switch \initial - attribute \src "libresoc.v:45371.9-45371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_cr0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$62[63:0]$2557 \int_src2__data_o - case - assign $1\fus_src2_i$62[63:0]$2557 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$62 $0\fus_src2_i$62[63:0]$2556 - end - attribute \src "libresoc.v:45380.3-45388.6" - process $proc$libresoc.v:45380$2558 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_trap0_2$next[0:0]$2559 $1\dp_INT_rb_trap0_2$next[0:0]$2560 - attribute \src "libresoc.v:45381.5-45381.29" - switch \initial - attribute \src "libresoc.v:45381.9-45381.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_trap0_2$next[0:0]$2560 1'0 - case - assign $1\dp_INT_rb_trap0_2$next[0:0]$2560 \rp_INT_rb_trap0_2 - end - sync always - update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2559 - end - attribute \src "libresoc.v:45389.3-45398.6" - process $proc$libresoc.v:45389$2561 - assign { } { } - assign { } { } - assign $0\fus_src2_i$63[63:0]$2562 $1\fus_src2_i$63[63:0]$2563 - attribute \src "libresoc.v:45390.5-45390.29" - switch \initial - attribute \src "libresoc.v:45390.9-45390.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_trap0_2 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$63[63:0]$2563 \int_src2__data_o - case - assign $1\fus_src2_i$63[63:0]$2563 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$63 $0\fus_src2_i$63[63:0]$2562 - end - attribute \src "libresoc.v:45399.3-45407.6" - process $proc$libresoc.v:45399$2564 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_logical0_3$next[0:0]$2565 $1\dp_INT_rb_logical0_3$next[0:0]$2566 - attribute \src "libresoc.v:45400.5-45400.29" - switch \initial - attribute \src "libresoc.v:45400.9-45400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_logical0_3$next[0:0]$2566 1'0 - case - assign $1\dp_INT_rb_logical0_3$next[0:0]$2566 \rp_INT_rb_logical0_3 - end - sync always - update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2565 - end - attribute \src "libresoc.v:45408.3-45417.6" - process $proc$libresoc.v:45408$2567 - assign { } { } - assign { } { } - assign $0\fus_src2_i$64[63:0]$2568 $1\fus_src2_i$64[63:0]$2569 - attribute \src "libresoc.v:45409.5-45409.29" - switch \initial - attribute \src "libresoc.v:45409.9-45409.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_logical0_3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$64[63:0]$2569 \int_src2__data_o - case - assign $1\fus_src2_i$64[63:0]$2569 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2568 - end - attribute \src "libresoc.v:45418.3-45426.6" - process $proc$libresoc.v:45418$2570 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_div0_4$next[0:0]$2571 $1\dp_INT_rb_div0_4$next[0:0]$2572 - attribute \src "libresoc.v:45419.5-45419.29" - switch \initial - attribute \src "libresoc.v:45419.9-45419.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_div0_4$next[0:0]$2572 1'0 - case - assign $1\dp_INT_rb_div0_4$next[0:0]$2572 \rp_INT_rb_div0_4 - end - sync always - update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2571 - end - attribute \src "libresoc.v:45427.3-45436.6" - process $proc$libresoc.v:45427$2573 - assign { } { } - assign { } { } - assign $0\fus_src2_i$65[63:0]$2574 $1\fus_src2_i$65[63:0]$2575 - attribute \src "libresoc.v:45428.5-45428.29" - switch \initial - attribute \src "libresoc.v:45428.9-45428.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_div0_4 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$65[63:0]$2575 \int_src2__data_o - case - assign $1\fus_src2_i$65[63:0]$2575 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2574 - end - attribute \src "libresoc.v:45437.3-45445.6" - process $proc$libresoc.v:45437$2576 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_mul0_5$next[0:0]$2577 $1\dp_INT_rb_mul0_5$next[0:0]$2578 - attribute \src "libresoc.v:45438.5-45438.29" - switch \initial - attribute \src "libresoc.v:45438.9-45438.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_mul0_5$next[0:0]$2578 1'0 - case - assign $1\dp_INT_rb_mul0_5$next[0:0]$2578 \rp_INT_rb_mul0_5 - end - sync always - update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2577 - end - attribute \src "libresoc.v:45446.3-45455.6" - process $proc$libresoc.v:45446$2579 - assign { } { } - assign { } { } - assign $0\fus_src2_i$66[63:0]$2580 $1\fus_src2_i$66[63:0]$2581 - attribute \src "libresoc.v:45447.5-45447.29" - switch \initial - attribute \src "libresoc.v:45447.9-45447.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_mul0_5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$66[63:0]$2581 \int_src2__data_o - case - assign $1\fus_src2_i$66[63:0]$2581 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2580 - end - attribute \src "libresoc.v:45456.3-45464.6" - process $proc$libresoc.v:45456$2582 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2583 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 - attribute \src "libresoc.v:45457.5-45457.29" - switch \initial - attribute \src "libresoc.v:45457.9-45457.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 1'0 - case - assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2584 \rp_INT_rb_shiftrot0_6 - end - sync always - update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2583 - end - attribute \src "libresoc.v:45465.3-45474.6" - process $proc$libresoc.v:45465$2585 - assign { } { } - assign { } { } - assign $0\fus_src2_i$67[63:0]$2586 $1\fus_src2_i$67[63:0]$2587 - attribute \src "libresoc.v:45466.5-45466.29" - switch \initial - attribute \src "libresoc.v:45466.9-45466.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_shiftrot0_6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$67[63:0]$2587 \int_src2__data_o - case - assign $1\fus_src2_i$67[63:0]$2587 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2586 - end - attribute \src "libresoc.v:45475.3-45483.6" - process $proc$libresoc.v:45475$2588 - assign { } { } - assign { } { } - assign $0\dp_INT_rb_ldst0_7$next[0:0]$2589 $1\dp_INT_rb_ldst0_7$next[0:0]$2590 - attribute \src "libresoc.v:45476.5-45476.29" - switch \initial - attribute \src "libresoc.v:45476.9-45476.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2590 1'0 - case - assign $1\dp_INT_rb_ldst0_7$next[0:0]$2590 \rp_INT_rb_ldst0_7 - end - sync always - update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2589 - end - attribute \src "libresoc.v:45484.3-45493.6" - process $proc$libresoc.v:45484$2591 - assign { } { } - assign { } { } - assign $0\fus_src2_i$68[63:0]$2592 $1\fus_src2_i$68[63:0]$2593 - attribute \src "libresoc.v:45485.5-45485.29" - switch \initial - attribute \src "libresoc.v:45485.9-45485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rb_ldst0_7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$68[63:0]$2593 \int_src2__data_o - case - assign $1\fus_src2_i$68[63:0]$2593 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2592 - end - attribute \src "libresoc.v:45494.3-45502.6" - process $proc$libresoc.v:45494$2594 - assign { } { } - assign { } { } - assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2595 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 - attribute \src "libresoc.v:45495.5-45495.29" - switch \initial - attribute \src "libresoc.v:45495.9-45495.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 1'0 - case - assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2596 \rp_INT_rc_shiftrot0_0 - end - sync always - update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2595 - end - attribute \src "libresoc.v:45503.3-45512.6" - process $proc$libresoc.v:45503$2597 - assign { } { } - assign { } { } - assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:45504.5-45504.29" - switch \initial - attribute \src "libresoc.v:45504.9-45504.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rc_shiftrot0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i[63:0] \int_src3__data_o - case - assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i $0\fus_src3_i[63:0] - end - attribute \src "libresoc.v:45513.3-45521.6" - process $proc$libresoc.v:45513$2598 - assign { } { } - assign { } { } - assign $0\dp_INT_rc_ldst0_1$next[0:0]$2599 $1\dp_INT_rc_ldst0_1$next[0:0]$2600 - attribute \src "libresoc.v:45514.5-45514.29" - switch \initial - attribute \src "libresoc.v:45514.9-45514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2600 1'0 - case - assign $1\dp_INT_rc_ldst0_1$next[0:0]$2600 \rp_INT_rc_ldst0_1 - end - sync always - update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2599 - end - attribute \src "libresoc.v:45522.3-45531.6" - process $proc$libresoc.v:45522$2601 - assign { } { } - assign { } { } - assign $0\fus_src3_i$69[63:0]$2602 $1\fus_src3_i$69[63:0]$2603 - attribute \src "libresoc.v:45523.5-45523.29" - switch \initial - attribute \src "libresoc.v:45523.9-45523.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_INT_rc_ldst0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$69[63:0]$2603 \int_src3__data_o - case - assign $1\fus_src3_i$69[63:0]$2603 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i$69 $0\fus_src3_i$69[63:0]$2602 - end - attribute \src "libresoc.v:45532.3-45558.6" - process $proc$libresoc.v:45532$2604 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\counter$next[1:0]$2605 $4\counter$next[1:0]$2609 - attribute \src "libresoc.v:45533.5-45533.29" - switch \initial - attribute \src "libresoc.v:45533.9-45533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - switch \$214 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\counter$next[1:0]$2606 \$216 [1:0] - case - assign $1\counter$next[1:0]$2606 \counter - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\counter$next[1:0]$2607 $3\counter$next[1:0]$2608 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\counter$next[1:0]$2608 2'10 - case - assign $3\counter$next[1:0]$2608 $1\counter$next[1:0]$2606 - end - case - assign $2\counter$next[1:0]$2607 $1\counter$next[1:0]$2606 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\counter$next[1:0]$2609 2'00 - case - assign $4\counter$next[1:0]$2609 $2\counter$next[1:0]$2607 - end - sync always - update \counter$next $0\counter$next[1:0]$2605 - end - attribute \src "libresoc.v:45559.3-45567.6" - process $proc$libresoc.v:45559$2610 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2611 $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 - attribute \src "libresoc.v:45560.5-45560.29" - switch \initial - attribute \src "libresoc.v:45560.9-45560.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 1'0 - case - assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2612 \rp_XER_xer_so_alu0_0 - end - sync always - update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2611 - end - attribute \src "libresoc.v:45568.3-45577.6" - process $proc$libresoc.v:45568$2613 - assign { } { } - assign { } { } - assign $0\fus_src3_i$70[0:0]$2614 $1\fus_src3_i$70[0:0]$2615 - attribute \src "libresoc.v:45569.5-45569.29" - switch \initial - attribute \src "libresoc.v:45569.9-45569.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_alu0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$70[0:0]$2615 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$70[0:0]$2615 1'0 - end - sync always - update \fus_src3_i$70 $0\fus_src3_i$70[0:0]$2614 - end - attribute \src "libresoc.v:45578.3-45668.6" - process $proc$libresoc.v:45578$2616 - assign { } { } - assign { } { } - assign { } { } - assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:45579.5-45579.29" - switch \initial - attribute \src "libresoc.v:45579.9-45579.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - switch \$219 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\corebusy_o[0:0] 1'1 - case - assign $1\corebusy_o[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign { } { } - assign $3\corebusy_o[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\corebusy_o[0:0] \fus_cu_busy_o - case - assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\corebusy_o[0:0] \fus_cu_busy_o$12 - case - assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\corebusy_o[0:0] \fus_cu_busy_o$15 - case - assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\corebusy_o[0:0] \fus_cu_busy_o$18 - case - assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\corebusy_o[0:0] \fus_cu_busy_o$21 - case - assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\corebusy_o[0:0] \fus_cu_busy_o$24 - case - assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [6] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\corebusy_o[0:0] \fus_cu_busy_o$27 - case - assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [7] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\corebusy_o[0:0] \fus_cu_busy_o$30 - case - assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [8] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\corebusy_o[0:0] \fus_cu_busy_o$33 - case - assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [9] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\corebusy_o[0:0] \fus_cu_busy_o$36 - case - assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] - end - end - case - assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] - end - sync always - update \corebusy_o $0\corebusy_o[0:0] - end - attribute \src "libresoc.v:45669.3-45677.6" - process $proc$libresoc.v:45669$2617 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2618 $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 - attribute \src "libresoc.v:45670.5-45670.29" - switch \initial - attribute \src "libresoc.v:45670.9-45670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 1'0 - case - assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2619 \rp_XER_xer_so_logical0_1 - end - sync always - update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2618 - end - attribute \src "libresoc.v:45678.3-45687.6" - process $proc$libresoc.v:45678$2620 - assign { } { } - assign { } { } - assign $0\fus_src3_i$71[0:0]$2621 $1\fus_src3_i$71[0:0]$2622 - attribute \src "libresoc.v:45679.5-45679.29" - switch \initial - attribute \src "libresoc.v:45679.9-45679.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_logical0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$71[0:0]$2622 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$71[0:0]$2622 1'0 - end - sync always - update \fus_src3_i$71 $0\fus_src3_i$71[0:0]$2621 - end - attribute \src "libresoc.v:45688.3-45696.6" - process $proc$libresoc.v:45688$2623 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2624 $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 - attribute \src "libresoc.v:45689.5-45689.29" - switch \initial - attribute \src "libresoc.v:45689.9-45689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 1'0 - case - assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2625 \rp_XER_xer_so_spr0_2 - end - sync always - update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2624 - end - attribute \src "libresoc.v:45697.3-45706.6" - process $proc$libresoc.v:45697$2626 - assign { } { } - assign { } { } - assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:45698.5-45698.29" - switch \initial - attribute \src "libresoc.v:45698.9-45698.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_spr0_2 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] - case - assign $1\fus_src4_i[0:0] 1'0 - end - sync always - update \fus_src4_i $0\fus_src4_i[0:0] - end - attribute \src "libresoc.v:45707.3-45727.6" - process $proc$libresoc.v:45707$2627 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_terminate_o$next[0:0]$2628 $3\core_terminate_o$next[0:0]$2631 - attribute \src "libresoc.v:45708.5-45708.29" - switch \initial - attribute \src "libresoc.v:45708.9-45708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\core_terminate_o$next[0:0]$2629 $2\core_terminate_o$next[0:0]$2630 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign { } { } - assign $2\core_terminate_o$next[0:0]$2630 1'1 - case - assign $2\core_terminate_o$next[0:0]$2630 \core_terminate_o - end - case - assign $1\core_terminate_o$next[0:0]$2629 \core_terminate_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_terminate_o$next[0:0]$2631 1'0 - case - assign $3\core_terminate_o$next[0:0]$2631 $1\core_terminate_o$next[0:0]$2629 - end - sync always - update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2628 - end - attribute \src "libresoc.v:45728.3-45736.6" - process $proc$libresoc.v:45728$2632 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_div0_3$next[0:0]$2633 $1\dp_XER_xer_so_div0_3$next[0:0]$2634 - attribute \src "libresoc.v:45729.5-45729.29" - switch \initial - attribute \src "libresoc.v:45729.9-45729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2634 1'0 - case - assign $1\dp_XER_xer_so_div0_3$next[0:0]$2634 \rp_XER_xer_so_div0_3 - end - sync always - update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2633 - end - attribute \src "libresoc.v:45737.3-45746.6" - process $proc$libresoc.v:45737$2635 - assign { } { } - assign { } { } - assign $0\fus_src3_i$72[0:0]$2636 $1\fus_src3_i$72[0:0]$2637 - attribute \src "libresoc.v:45738.5-45738.29" - switch \initial - attribute \src "libresoc.v:45738.9-45738.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_div0_3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$72[0:0]$2637 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$72[0:0]$2637 1'0 - end - sync always - update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2636 - end - attribute \src "libresoc.v:45747.3-45755.6" - process $proc$libresoc.v:45747$2638 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2639 $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 - attribute \src "libresoc.v:45748.5-45748.29" - switch \initial - attribute \src "libresoc.v:45748.9-45748.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 1'0 - case - assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2640 \rp_XER_xer_so_mul0_4 - end - sync always - update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2639 - end - attribute \src "libresoc.v:45756.3-45765.6" - process $proc$libresoc.v:45756$2641 - assign { } { } - assign { } { } - assign $0\fus_src3_i$73[0:0]$2642 $1\fus_src3_i$73[0:0]$2643 - attribute \src "libresoc.v:45757.5-45757.29" - switch \initial - attribute \src "libresoc.v:45757.9-45757.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_mul0_4 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$73[0:0]$2643 \xer_src1__data_o [0] - case - assign $1\fus_src3_i$73[0:0]$2643 1'0 - end - sync always - update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2642 - end - attribute \src "libresoc.v:45766.3-45794.6" - process $proc$libresoc.v:45766$2644 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:45767.5-45767.29" - switch \initial - attribute \src "libresoc.v:45767.9-45767.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type - case - assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] - end - attribute \src "libresoc.v:45795.3-45803.6" - process $proc$libresoc.v:45795$2645 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2646 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 - attribute \src "libresoc.v:45796.5-45796.29" - switch \initial - attribute \src "libresoc.v:45796.9-45796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 1'0 - case - assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2647 \rp_XER_xer_so_shiftrot0_5 - end - sync always - update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2646 - end - attribute \src "libresoc.v:45804.3-45813.6" - process $proc$libresoc.v:45804$2648 - assign { } { } - assign { } { } - assign $0\fus_src4_i$74[0:0]$2649 $1\fus_src4_i$74[0:0]$2650 - attribute \src "libresoc.v:45805.5-45805.29" - switch \initial - attribute \src "libresoc.v:45805.9-45805.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_so_shiftrot0_5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$74[0:0]$2650 \xer_src1__data_o [0] - case - assign $1\fus_src4_i$74[0:0]$2650 1'0 - end - sync always - update \fus_src4_i$74 $0\fus_src4_i$74[0:0]$2649 - end - attribute \src "libresoc.v:45814.3-45822.6" - process $proc$libresoc.v:45814$2651 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2652 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 - attribute \src "libresoc.v:45815.5-45815.29" - switch \initial - attribute \src "libresoc.v:45815.9-45815.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 1'0 - case - assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2653 \rp_XER_xer_ca_alu0_0 - end - sync always - update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2652 - end - attribute \src "libresoc.v:45823.3-45851.6" - process $proc$libresoc.v:45823$2654 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__fn_unit[11:0] $1\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "libresoc.v:45824.5-45824.29" - switch \initial - attribute \src "libresoc.v:45824.9-45824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] $2\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] $3\fus_oper_i_alu_alu0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU__fn_unit - case - assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[11:0] - end - attribute \src "libresoc.v:45852.3-45861.6" - process $proc$libresoc.v:45852$2655 - assign { } { } - assign { } { } - assign $0\fus_src4_i$75[1:0]$2656 $1\fus_src4_i$75[1:0]$2657 - attribute \src "libresoc.v:45853.5-45853.29" - switch \initial - attribute \src "libresoc.v:45853.9-45853.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ca_alu0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$75[1:0]$2657 \xer_src2__data_o - case - assign $1\fus_src4_i$75[1:0]$2657 2'00 - end - sync always - update \fus_src4_i$75 $0\fus_src4_i$75[1:0]$2656 - end - attribute \src "libresoc.v:45862.3-45870.6" - process $proc$libresoc.v:45862$2658 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2659 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 - attribute \src "libresoc.v:45863.5-45863.29" - switch \initial - attribute \src "libresoc.v:45863.9-45863.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 1'0 - case - assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2660 \rp_XER_xer_ca_spr0_1 - end - sync always - update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2659 - end - attribute \src "libresoc.v:45871.3-45880.6" - process $proc$libresoc.v:45871$2661 - assign { } { } - assign { } { } - assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:45872.5-45872.29" - switch \initial - attribute \src "libresoc.v:45872.9-45872.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ca_spr0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src6_i[1:0] \xer_src2__data_o - case - assign $1\fus_src6_i[1:0] 2'00 - end - sync always - update \fus_src6_i $0\fus_src6_i[1:0] - end - attribute \src "libresoc.v:45881.3-45889.6" - process $proc$libresoc.v:45881$2662 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2663 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 - attribute \src "libresoc.v:45882.5-45882.29" - switch \initial - attribute \src "libresoc.v:45882.9-45882.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 1'0 - case - assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2664 \rp_XER_xer_ca_shiftrot0_2 - end - sync always - update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2663 - end - attribute \src "libresoc.v:45890.3-45919.6" - process $proc$libresoc.v:45890$2665 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:45891.5-45891.29" - switch \initial - attribute \src "libresoc.v:45891.9-45891.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } - case - assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - end - attribute \src "libresoc.v:45920.3-45929.6" - process $proc$libresoc.v:45920$2666 - assign { } { } - assign { } { } - assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:45921.5-45921.29" - switch \initial - attribute \src "libresoc.v:45921.9-45921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ca_shiftrot0_2 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src5_i[1:0] \xer_src2__data_o - case - assign $1\fus_src5_i[1:0] 2'00 - end - sync always - update \fus_src5_i $0\fus_src5_i[1:0] - end - attribute \src "libresoc.v:45930.3-45938.6" - process $proc$libresoc.v:45930$2667 - assign { } { } - assign { } { } - assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2668 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 - attribute \src "libresoc.v:45931.5-45931.29" - switch \initial - attribute \src "libresoc.v:45931.9-45931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 1'0 - case - assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2669 \rp_XER_xer_ov_spr0_0 - end - sync always - update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2668 - end - attribute \src "libresoc.v:45939.3-45948.6" - process $proc$libresoc.v:45939$2670 - assign { } { } - assign { } { } - assign $0\fus_src5_i$76[1:0]$2671 $1\fus_src5_i$76[1:0]$2672 - attribute \src "libresoc.v:45940.5-45940.29" - switch \initial - attribute \src "libresoc.v:45940.9-45940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_XER_xer_ov_spr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src5_i$76[1:0]$2672 \xer_src3__data_o - case - assign $1\fus_src5_i$76[1:0]$2672 2'00 - end - sync always - update \fus_src5_i$76 $0\fus_src5_i$76[1:0]$2671 - end - attribute \src "libresoc.v:45949.3-45957.6" - process $proc$libresoc.v:45949$2673 - assign { } { } - assign { } { } - assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2674 $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 - attribute \src "libresoc.v:45950.5-45950.29" - switch \initial - attribute \src "libresoc.v:45950.9-45950.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 1'0 - case - assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2675 \rp_CR_full_cr_cr0_0 - end - sync always - update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2674 - end - attribute \src "libresoc.v:45958.3-45967.6" - process $proc$libresoc.v:45958$2676 - assign { } { } - assign { } { } - assign $0\fus_src3_i$77[31:0]$2677 $1\fus_src3_i$77[31:0]$2678 - attribute \src "libresoc.v:45959.5-45959.29" - switch \initial - attribute \src "libresoc.v:45959.9-45959.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_full_cr_cr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$77[31:0]$2678 \cr_full_rd__data_o - case - assign $1\fus_src3_i$77[31:0]$2678 0 - end - sync always - update \fus_src3_i$77 $0\fus_src3_i$77[31:0]$2677 - end - attribute \src "libresoc.v:45968.3-45997.6" - process $proc$libresoc.v:45968$2679 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:45969.5-45969.29" - switch \initial - attribute \src "libresoc.v:45969.9-45969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] - assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } - case - assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] - update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] - end - attribute \src "libresoc.v:45998.3-46006.6" - process $proc$libresoc.v:45998$2680 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2681 $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 - attribute \src "libresoc.v:45999.5-45999.29" - switch \initial - attribute \src "libresoc.v:45999.9-45999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 1'0 - case - assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2682 \rp_CR_cr_a_cr0_0 - end - sync always - update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2681 - end - attribute \src "libresoc.v:46007.3-46016.6" - process $proc$libresoc.v:46007$2683 - assign { } { } - assign { } { } - assign $0\fus_src4_i$78[3:0]$2684 $1\fus_src4_i$78[3:0]$2685 - attribute \src "libresoc.v:46008.5-46008.29" - switch \initial - attribute \src "libresoc.v:46008.9-46008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_a_cr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$78[3:0]$2685 \cr_src1__data_o - case - assign $1\fus_src4_i$78[3:0]$2685 4'0000 - end - sync always - update \fus_src4_i$78 $0\fus_src4_i$78[3:0]$2684 - end - attribute \src "libresoc.v:46017.3-46025.6" - process $proc$libresoc.v:46017$2686 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2687 $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 - attribute \src "libresoc.v:46018.5-46018.29" - switch \initial - attribute \src "libresoc.v:46018.9-46018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 1'0 - case - assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2688 \rp_CR_cr_a_branch0_1 - end - sync always - update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2687 - end - attribute \src "libresoc.v:46026.3-46035.6" - process $proc$libresoc.v:46026$2689 - assign { } { } - assign { } { } - assign $0\fus_src3_i$81[3:0]$2690 $1\fus_src3_i$81[3:0]$2691 - attribute \src "libresoc.v:46027.5-46027.29" - switch \initial - attribute \src "libresoc.v:46027.9-46027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_a_branch0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$81[3:0]$2691 \cr_src1__data_o - case - assign $1\fus_src3_i$81[3:0]$2691 4'0000 - end - sync always - update \fus_src3_i$81 $0\fus_src3_i$81[3:0]$2690 - end - attribute \src "libresoc.v:46036.3-46044.6" - process $proc$libresoc.v:46036$2692 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2693 $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 - attribute \src "libresoc.v:46037.5-46037.29" - switch \initial - attribute \src "libresoc.v:46037.9-46037.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 1'0 - case - assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2694 \rp_CR_cr_b_cr0_0 - end - sync always - update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2693 - end - attribute \src "libresoc.v:46045.3-46054.6" - process $proc$libresoc.v:46045$2695 - assign { } { } - assign { } { } - assign $0\fus_src5_i$82[3:0]$2696 $1\fus_src5_i$82[3:0]$2697 - attribute \src "libresoc.v:46046.5-46046.29" - switch \initial - attribute \src "libresoc.v:46046.9-46046.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_b_cr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src5_i$82[3:0]$2697 \cr_src2__data_o - case - assign $1\fus_src5_i$82[3:0]$2697 4'0000 - end - sync always - update \fus_src5_i$82 $0\fus_src5_i$82[3:0]$2696 - end - attribute \src "libresoc.v:46055.3-46084.6" - process $proc$libresoc.v:46055$2698 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46056.5-46056.29" - switch \initial - attribute \src "libresoc.v:46056.9-46056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] - assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } - case - assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] - update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] - end - attribute \src "libresoc.v:46085.3-46093.6" - process $proc$libresoc.v:46085$2699 - assign { } { } - assign { } { } - assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2700 $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 - attribute \src "libresoc.v:46086.5-46086.29" - switch \initial - attribute \src "libresoc.v:46086.9-46086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 1'0 - case - assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2701 \rp_CR_cr_c_cr0_0 - end - sync always - update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2700 - end - attribute \src "libresoc.v:46094.3-46103.6" - process $proc$libresoc.v:46094$2702 - assign { } { } - assign { } { } - assign $0\fus_src6_i$83[3:0]$2703 $1\fus_src6_i$83[3:0]$2704 - attribute \src "libresoc.v:46095.5-46095.29" - switch \initial - attribute \src "libresoc.v:46095.9-46095.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_CR_cr_c_cr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src6_i$83[3:0]$2704 \cr_src3__data_o - case - assign $1\fus_src6_i$83[3:0]$2704 4'0000 - end - sync always - update \fus_src6_i$83 $0\fus_src6_i$83[3:0]$2703 - end - attribute \src "libresoc.v:46104.3-46112.6" - process $proc$libresoc.v:46104$2705 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2706 $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 - attribute \src "libresoc.v:46105.5-46105.29" - switch \initial - attribute \src "libresoc.v:46105.9-46105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 1'0 - case - assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2707 \rp_FAST_fast1_branch0_0 - end - sync always - update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2706 - end - attribute \src "libresoc.v:46113.3-46122.6" - process $proc$libresoc.v:46113$2708 - assign { } { } - assign { } { } - assign $0\fus_src1_i$84[63:0]$2709 $1\fus_src1_i$84[63:0]$2710 - attribute \src "libresoc.v:46114.5-46114.29" - switch \initial - attribute \src "libresoc.v:46114.9-46114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast1_branch0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src1_i$84[63:0]$2710 \fast_src1__data_o - case - assign $1\fus_src1_i$84[63:0]$2710 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src1_i$84 $0\fus_src1_i$84[63:0]$2709 - end - attribute \src "libresoc.v:46123.3-46131.6" - process $proc$libresoc.v:46123$2711 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2712 $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 - attribute \src "libresoc.v:46124.5-46124.29" - switch \initial - attribute \src "libresoc.v:46124.9-46124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 1'0 - case - assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2713 \rp_FAST_fast1_trap0_1 - end - sync always - update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2712 - end - attribute \src "libresoc.v:46132.3-46141.6" - process $proc$libresoc.v:46132$2714 - assign { } { } - assign { } { } - assign $0\fus_src3_i$85[63:0]$2715 $1\fus_src3_i$85[63:0]$2716 - attribute \src "libresoc.v:46133.5-46133.29" - switch \initial - attribute \src "libresoc.v:46133.9-46133.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast1_trap0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$85[63:0]$2716 \fast_src1__data_o - case - assign $1\fus_src3_i$85[63:0]$2716 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i$85 $0\fus_src3_i$85[63:0]$2715 - end - attribute \src "libresoc.v:46142.3-46170.6" - process $proc$libresoc.v:46142$2717 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46143.5-46143.29" - switch \initial - attribute \src "libresoc.v:46143.9-46143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in - case - assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] - end - attribute \src "libresoc.v:46171.3-46179.6" - process $proc$libresoc.v:46171$2718 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2719 $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 - attribute \src "libresoc.v:46172.5-46172.29" - switch \initial - attribute \src "libresoc.v:46172.9-46172.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 1'0 - case - assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2720 \rp_FAST_fast1_spr0_2 - end - sync always - update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2719 - end - attribute \src "libresoc.v:46180.3-46189.6" - process $proc$libresoc.v:46180$2721 - assign { } { } - assign { } { } - assign $0\fus_src3_i$86[63:0]$2722 $1\fus_src3_i$86[63:0]$2723 - attribute \src "libresoc.v:46181.5-46181.29" - switch \initial - attribute \src "libresoc.v:46181.9-46181.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast1_spr0_2 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src3_i$86[63:0]$2723 \fast_src1__data_o - case - assign $1\fus_src3_i$86[63:0]$2723 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src3_i$86 $0\fus_src3_i$86[63:0]$2722 - end - attribute \src "libresoc.v:46190.3-46218.6" - process $proc$libresoc.v:46190$2724 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46191.5-46191.29" - switch \initial - attribute \src "libresoc.v:46191.9-46191.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a - case - assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] - end - attribute \src "libresoc.v:46219.3-46227.6" - process $proc$libresoc.v:46219$2725 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2726 $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 - attribute \src "libresoc.v:46220.5-46220.29" - switch \initial - attribute \src "libresoc.v:46220.9-46220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 1'0 - case - assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2727 \rp_FAST_fast2_branch0_0 - end - sync always - update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2726 - end - attribute \src "libresoc.v:46228.3-46237.6" - process $proc$libresoc.v:46228$2728 - assign { } { } - assign { } { } - assign $0\fus_src2_i$87[63:0]$2729 $1\fus_src2_i$87[63:0]$2730 - attribute \src "libresoc.v:46229.5-46229.29" - switch \initial - attribute \src "libresoc.v:46229.9-46229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast2_branch0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$87[63:0]$2730 \fast_src2__data_o - case - assign $1\fus_src2_i$87[63:0]$2730 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$87 $0\fus_src2_i$87[63:0]$2729 - end - attribute \src "libresoc.v:46238.3-46246.6" - process $proc$libresoc.v:46238$2731 - assign { } { } - assign { } { } - assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2732 $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 - attribute \src "libresoc.v:46239.5-46239.29" - switch \initial - attribute \src "libresoc.v:46239.9-46239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 1'0 - case - assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2733 \rp_FAST_fast2_trap0_1 - end - sync always - update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2732 - end - attribute \src "libresoc.v:46247.3-46256.6" - process $proc$libresoc.v:46247$2734 - assign { } { } - assign { } { } - assign $0\fus_src4_i$88[63:0]$2735 $1\fus_src4_i$88[63:0]$2736 - attribute \src "libresoc.v:46248.5-46248.29" - switch \initial - attribute \src "libresoc.v:46248.9-46248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_FAST_fast2_trap0_1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src4_i$88[63:0]$2736 \fast_src2__data_o - case - assign $1\fus_src4_i$88[63:0]$2736 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src4_i$88 $0\fus_src4_i$88[63:0]$2735 - end - attribute \src "libresoc.v:46257.3-46285.6" - process $proc$libresoc.v:46257$2737 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:46258.5-46258.29" - switch \initial - attribute \src "libresoc.v:46258.9-46258.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU__invert_out - case - assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] - end - attribute \src "libresoc.v:46286.3-46294.6" - process $proc$libresoc.v:46286$2738 - assign { } { } - assign { } { } - assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2739 $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 - attribute \src "libresoc.v:46287.5-46287.29" - switch \initial - attribute \src "libresoc.v:46287.9-46287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 1'0 - case - assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2740 \rp_SPR_spr1_spr0_0 - end - sync always - update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2739 - end - attribute \src "libresoc.v:46295.3-46304.6" - process $proc$libresoc.v:46295$2741 - assign { } { } - assign { } { } - assign $0\fus_src2_i$89[63:0]$2742 $1\fus_src2_i$89[63:0]$2743 - attribute \src "libresoc.v:46296.5-46296.29" - switch \initial - attribute \src "libresoc.v:46296.9-46296.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:295" - switch \dp_SPR_spr1_spr0_0 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_src2_i$89[63:0]$2743 \spr_spr1__data_o - case - assign $1\fus_src2_i$89[63:0]$2743 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2742 - end - attribute \src "libresoc.v:46305.3-46333.6" - process $proc$libresoc.v:46305$2744 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46306.5-46306.29" - switch \initial - attribute \src "libresoc.v:46306.9-46306.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU__write_cr0 - case - assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] - end - attribute \src "libresoc.v:46334.3-46342.6" - process $proc$libresoc.v:46334$2745 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$next[0:0]$2746 $1\wr_pick_dly$next[0:0]$2747 - attribute \src "libresoc.v:46335.5-46335.29" - switch \initial - attribute \src "libresoc.v:46335.9-46335.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$next[0:0]$2747 1'0 - case - assign $1\wr_pick_dly$next[0:0]$2747 \wr_pick - end - sync always - update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2746 - end - attribute \src "libresoc.v:46343.3-46371.6" - process $proc$libresoc.v:46343$2748 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:46344.5-46344.29" - switch \initial - attribute \src "libresoc.v:46344.9-46344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU__input_carry - case - assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - end - end - case - assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 - end - sync always - update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] - end - attribute \src "libresoc.v:46372.3-46380.6" - process $proc$libresoc.v:46372$2749 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$981$next[0:0]$2750 $1\wr_pick_dly$981$next[0:0]$2751 - attribute \src "libresoc.v:46373.5-46373.29" - switch \initial - attribute \src "libresoc.v:46373.9-46373.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$981$next[0:0]$2751 1'0 - case - assign $1\wr_pick_dly$981$next[0:0]$2751 \wr_pick$978 - end - sync always - update \wr_pick_dly$981$next $0\wr_pick_dly$981$next[0:0]$2750 - end - attribute \src "libresoc.v:46381.3-46389.6" - process $proc$libresoc.v:46381$2752 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1000$next[0:0]$2753 $1\wr_pick_dly$1000$next[0:0]$2754 - attribute \src "libresoc.v:46382.5-46382.29" - switch \initial - attribute \src "libresoc.v:46382.9-46382.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1000$next[0:0]$2754 1'0 - case - assign $1\wr_pick_dly$1000$next[0:0]$2754 \wr_pick$997 - end - sync always - update \wr_pick_dly$1000$next $0\wr_pick_dly$1000$next[0:0]$2753 - end - attribute \src "libresoc.v:46390.3-46418.6" - process $proc$libresoc.v:46390$2755 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46391.5-46391.29" - switch \initial - attribute \src "libresoc.v:46391.9-46391.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU__output_carry - case - assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] - end - attribute \src "libresoc.v:46419.3-46427.6" - process $proc$libresoc.v:46419$2756 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1021$next[0:0]$2757 $1\wr_pick_dly$1021$next[0:0]$2758 - attribute \src "libresoc.v:46420.5-46420.29" - switch \initial - attribute \src "libresoc.v:46420.9-46420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1021$next[0:0]$2758 1'0 - case - assign $1\wr_pick_dly$1021$next[0:0]$2758 \wr_pick$1018 - end - sync always - update \wr_pick_dly$1021$next $0\wr_pick_dly$1021$next[0:0]$2757 - end - attribute \src "libresoc.v:46428.3-46456.6" - process $proc$libresoc.v:46428$2759 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:46429.5-46429.29" - switch \initial - attribute \src "libresoc.v:46429.9-46429.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU__is_32bit - case - assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] - end - attribute \src "libresoc.v:46457.3-46465.6" - process $proc$libresoc.v:46457$2760 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1039$next[0:0]$2761 $1\wr_pick_dly$1039$next[0:0]$2762 - attribute \src "libresoc.v:46458.5-46458.29" - switch \initial - attribute \src "libresoc.v:46458.9-46458.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1039$next[0:0]$2762 1'0 - case - assign $1\wr_pick_dly$1039$next[0:0]$2762 \wr_pick$1036 - end - sync always - update \wr_pick_dly$1039$next $0\wr_pick_dly$1039$next[0:0]$2761 - end - attribute \src "libresoc.v:46466.3-46474.6" - process $proc$libresoc.v:46466$2763 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1061$next[0:0]$2764 $1\wr_pick_dly$1061$next[0:0]$2765 - attribute \src "libresoc.v:46467.5-46467.29" - switch \initial - attribute \src "libresoc.v:46467.9-46467.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1061$next[0:0]$2765 1'0 - case - assign $1\wr_pick_dly$1061$next[0:0]$2765 \wr_pick$1058 - end - sync always - update \wr_pick_dly$1061$next $0\wr_pick_dly$1061$next[0:0]$2764 - end - attribute \src "libresoc.v:46475.3-46503.6" - process $proc$libresoc.v:46475$2766 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46476.5-46476.29" - switch \initial - attribute \src "libresoc.v:46476.9-46476.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU__is_signed - case - assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] - end - attribute \src "libresoc.v:46504.3-46512.6" - process $proc$libresoc.v:46504$2767 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1081$next[0:0]$2768 $1\wr_pick_dly$1081$next[0:0]$2769 - attribute \src "libresoc.v:46505.5-46505.29" - switch \initial - attribute \src "libresoc.v:46505.9-46505.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1081$next[0:0]$2769 1'0 - case - assign $1\wr_pick_dly$1081$next[0:0]$2769 \wr_pick$1078 - end - sync always - update \wr_pick_dly$1081$next $0\wr_pick_dly$1081$next[0:0]$2768 - end - attribute \src "libresoc.v:46513.3-46541.6" - process $proc$libresoc.v:46513$2770 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46514.5-46514.29" - switch \initial - attribute \src "libresoc.v:46514.9-46514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU__data_len - case - assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] - end - attribute \src "libresoc.v:46542.3-46550.6" - process $proc$libresoc.v:46542$2771 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1101$next[0:0]$2772 $1\wr_pick_dly$1101$next[0:0]$2773 - attribute \src "libresoc.v:46543.5-46543.29" - switch \initial - attribute \src "libresoc.v:46543.9-46543.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1101$next[0:0]$2773 1'0 - case - assign $1\wr_pick_dly$1101$next[0:0]$2773 \wr_pick$1098 - end - sync always - update \wr_pick_dly$1101$next $0\wr_pick_dly$1101$next[0:0]$2772 - end - attribute \src "libresoc.v:46551.3-46559.6" - process $proc$libresoc.v:46551$2774 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1120$next[0:0]$2775 $1\wr_pick_dly$1120$next[0:0]$2776 - attribute \src "libresoc.v:46552.5-46552.29" - switch \initial - attribute \src "libresoc.v:46552.9-46552.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1120$next[0:0]$2776 1'0 - case - assign $1\wr_pick_dly$1120$next[0:0]$2776 \wr_pick$1117 - end - sync always - update \wr_pick_dly$1120$next $0\wr_pick_dly$1120$next[0:0]$2775 - end - attribute \src "libresoc.v:46560.3-46588.6" - process $proc$libresoc.v:46560$2777 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46561.5-46561.29" - switch \initial - attribute \src "libresoc.v:46561.9-46561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU__insn - case - assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] - end - attribute \src "libresoc.v:46589.3-46597.6" - process $proc$libresoc.v:46589$2778 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1138$next[0:0]$2779 $1\wr_pick_dly$1138$next[0:0]$2780 - attribute \src "libresoc.v:46590.5-46590.29" - switch \initial - attribute \src "libresoc.v:46590.9-46590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1138$next[0:0]$2780 1'0 - case - assign $1\wr_pick_dly$1138$next[0:0]$2780 \wr_pick$1135 - end - sync always - update \wr_pick_dly$1138$next $0\wr_pick_dly$1138$next[0:0]$2779 - end - attribute \src "libresoc.v:46598.3-46626.6" - process $proc$libresoc.v:46598$2781 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:46599.5-46599.29" - switch \initial - attribute \src "libresoc.v:46599.9-46599.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i[0:0] \issue_i - case - assign $3\fus_cu_issue_i[0:0] 1'0 - end - end - case - assign $1\fus_cu_issue_i[0:0] 1'0 - end - sync always - update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] - end - attribute \src "libresoc.v:46627.3-46635.6" - process $proc$libresoc.v:46627$2782 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1211$next[0:0]$2783 $1\wr_pick_dly$1211$next[0:0]$2784 - attribute \src "libresoc.v:46628.5-46628.29" - switch \initial - attribute \src "libresoc.v:46628.9-46628.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1211$next[0:0]$2784 1'0 - case - assign $1\wr_pick_dly$1211$next[0:0]$2784 \wr_pick$1208 - end - sync always - update \wr_pick_dly$1211$next $0\wr_pick_dly$1211$next[0:0]$2783 - end - attribute \src "libresoc.v:46636.3-46664.6" - process $proc$libresoc.v:46636$2785 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:46637.5-46637.29" - switch \initial - attribute \src "libresoc.v:46637.9-46637.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i[3:0] \$221 - case - assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 - end - end - case - assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 - end - sync always - update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] - end - attribute \src "libresoc.v:46665.3-46673.6" - process $proc$libresoc.v:46665$2786 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1239$next[0:0]$2787 $1\wr_pick_dly$1239$next[0:0]$2788 - attribute \src "libresoc.v:46666.5-46666.29" - switch \initial - attribute \src "libresoc.v:46666.9-46666.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1239$next[0:0]$2788 1'0 - case - assign $1\wr_pick_dly$1239$next[0:0]$2788 \wr_pick$1236 - end - sync always - update \wr_pick_dly$1239$next $0\wr_pick_dly$1239$next[0:0]$2787 - end - attribute \src "libresoc.v:46674.3-46702.6" - process $proc$libresoc.v:46674$2789 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:46675.5-46675.29" - switch \initial - attribute \src "libresoc.v:46675.9-46675.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR__insn_type - case - assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] - end - attribute \src "libresoc.v:46703.3-46711.6" - process $proc$libresoc.v:46703$2790 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1259$next[0:0]$2791 $1\wr_pick_dly$1259$next[0:0]$2792 - attribute \src "libresoc.v:46704.5-46704.29" - switch \initial - attribute \src "libresoc.v:46704.9-46704.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1259$next[0:0]$2792 1'0 - case - assign $1\wr_pick_dly$1259$next[0:0]$2792 \wr_pick$1256 - end - sync always - update \wr_pick_dly$1259$next $0\wr_pick_dly$1259$next[0:0]$2791 - end - attribute \src "libresoc.v:46712.3-46720.6" - process $proc$libresoc.v:46712$2793 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1279$next[0:0]$2794 $1\wr_pick_dly$1279$next[0:0]$2795 - attribute \src "libresoc.v:46713.5-46713.29" - switch \initial - attribute \src "libresoc.v:46713.9-46713.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1279$next[0:0]$2795 1'0 - case - assign $1\wr_pick_dly$1279$next[0:0]$2795 \wr_pick$1276 - end - sync always - update \wr_pick_dly$1279$next $0\wr_pick_dly$1279$next[0:0]$2794 - end - attribute \src "libresoc.v:46721.3-46749.6" - process $proc$libresoc.v:46721$2796 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_cr0__fn_unit[11:0] $1\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "libresoc.v:46722.5-46722.29" - switch \initial - attribute \src "libresoc.v:46722.9-46722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] $2\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] $3\fus_oper_i_alu_cr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR__fn_unit - case - assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[11:0] - end - attribute \src "libresoc.v:46750.3-46758.6" - process $proc$libresoc.v:46750$2797 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1299$next[0:0]$2798 $1\wr_pick_dly$1299$next[0:0]$2799 - attribute \src "libresoc.v:46751.5-46751.29" - switch \initial - attribute \src "libresoc.v:46751.9-46751.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1299$next[0:0]$2799 1'0 - case - assign $1\wr_pick_dly$1299$next[0:0]$2799 \wr_pick$1296 - end - sync always - update \wr_pick_dly$1299$next $0\wr_pick_dly$1299$next[0:0]$2798 - end - attribute \src "libresoc.v:46759.3-46767.6" - process $proc$libresoc.v:46759$2800 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1319$next[0:0]$2801 $1\wr_pick_dly$1319$next[0:0]$2802 - attribute \src "libresoc.v:46760.5-46760.29" - switch \initial - attribute \src "libresoc.v:46760.9-46760.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1319$next[0:0]$2802 1'0 - case - assign $1\wr_pick_dly$1319$next[0:0]$2802 \wr_pick$1316 - end - sync always - update \wr_pick_dly$1319$next $0\wr_pick_dly$1319$next[0:0]$2801 - end - attribute \src "libresoc.v:46768.3-46796.6" - process $proc$libresoc.v:46768$2803 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:46769.5-46769.29" - switch \initial - attribute \src "libresoc.v:46769.9-46769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR__insn - case - assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] - end - attribute \src "libresoc.v:46797.3-46805.6" - process $proc$libresoc.v:46797$2804 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1339$next[0:0]$2805 $1\wr_pick_dly$1339$next[0:0]$2806 - attribute \src "libresoc.v:46798.5-46798.29" - switch \initial - attribute \src "libresoc.v:46798.9-46798.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1339$next[0:0]$2806 1'0 - case - assign $1\wr_pick_dly$1339$next[0:0]$2806 \wr_pick$1336 - end - sync always - update \wr_pick_dly$1339$next $0\wr_pick_dly$1339$next[0:0]$2805 - end - attribute \src "libresoc.v:46806.3-46834.6" - process $proc$libresoc.v:46806$2807 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$11[0:0]$2808 $1\fus_cu_issue_i$11[0:0]$2809 - attribute \src "libresoc.v:46807.5-46807.29" - switch \initial - attribute \src "libresoc.v:46807.9-46807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$11[0:0]$2809 $2\fus_cu_issue_i$11[0:0]$2810 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$11[0:0]$2810 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$11[0:0]$2810 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$11[0:0]$2810 $3\fus_cu_issue_i$11[0:0]$2811 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$11[0:0]$2811 \issue_i - case - assign $3\fus_cu_issue_i$11[0:0]$2811 1'0 - end - end - case - assign $1\fus_cu_issue_i$11[0:0]$2809 1'0 - end - sync always - update \fus_cu_issue_i$11 $0\fus_cu_issue_i$11[0:0]$2808 - end - attribute \src "libresoc.v:46835.3-46843.6" - process $proc$libresoc.v:46835$2812 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1386$next[0:0]$2813 $1\wr_pick_dly$1386$next[0:0]$2814 - attribute \src "libresoc.v:46836.5-46836.29" - switch \initial - attribute \src "libresoc.v:46836.9-46836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1386$next[0:0]$2814 1'0 - case - assign $1\wr_pick_dly$1386$next[0:0]$2814 \wr_pick$1383 - end - sync always - update \wr_pick_dly$1386$next $0\wr_pick_dly$1386$next[0:0]$2813 - end - attribute \src "libresoc.v:46844.3-46872.6" - process $proc$libresoc.v:46844$2815 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$13[5:0]$2816 $1\fus_cu_rdmaskn_i$13[5:0]$2817 - attribute \src "libresoc.v:46845.5-46845.29" - switch \initial - attribute \src "libresoc.v:46845.9-46845.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$13[5:0]$2817 $2\fus_cu_rdmaskn_i$13[5:0]$2818 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$13[5:0]$2818 6'000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$13[5:0]$2818 6'000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$13[5:0]$2818 $3\fus_cu_rdmaskn_i$13[5:0]$2819 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$13[5:0]$2819 \$243 - case - assign $3\fus_cu_rdmaskn_i$13[5:0]$2819 6'000000 - end - end - case - assign $1\fus_cu_rdmaskn_i$13[5:0]$2817 6'000000 - end - sync always - update \fus_cu_rdmaskn_i$13 $0\fus_cu_rdmaskn_i$13[5:0]$2816 - end - attribute \src "libresoc.v:46873.3-46881.6" - process $proc$libresoc.v:46873$2820 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1402$next[0:0]$2821 $1\wr_pick_dly$1402$next[0:0]$2822 - attribute \src "libresoc.v:46874.5-46874.29" - switch \initial - attribute \src "libresoc.v:46874.9-46874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1402$next[0:0]$2822 1'0 - case - assign $1\wr_pick_dly$1402$next[0:0]$2822 \wr_pick$1399 - end - sync always - update \wr_pick_dly$1402$next $0\wr_pick_dly$1402$next[0:0]$2821 - end - attribute \src "libresoc.v:46882.3-46890.6" - process $proc$libresoc.v:46882$2823 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1418$next[0:0]$2824 $1\wr_pick_dly$1418$next[0:0]$2825 - attribute \src "libresoc.v:46883.5-46883.29" - switch \initial - attribute \src "libresoc.v:46883.9-46883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1418$next[0:0]$2825 1'0 - case - assign $1\wr_pick_dly$1418$next[0:0]$2825 \wr_pick$1415 - end - sync always - update \wr_pick_dly$1418$next $0\wr_pick_dly$1418$next[0:0]$2824 - end - attribute \src "libresoc.v:46891.3-46919.6" - process $proc$libresoc.v:46891$2826 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:46892.5-46892.29" - switch \initial - attribute \src "libresoc.v:46892.9-46892.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH__cia - case - assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] - end - attribute \src "libresoc.v:46920.3-46928.6" - process $proc$libresoc.v:46920$2827 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1452$next[0:0]$2828 $1\wr_pick_dly$1452$next[0:0]$2829 - attribute \src "libresoc.v:46921.5-46921.29" - switch \initial - attribute \src "libresoc.v:46921.9-46921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1452$next[0:0]$2829 1'0 - case - assign $1\wr_pick_dly$1452$next[0:0]$2829 \wr_pick$1449 - end - sync always - update \wr_pick_dly$1452$next $0\wr_pick_dly$1452$next[0:0]$2828 - end - attribute \src "libresoc.v:46929.3-46957.6" - process $proc$libresoc.v:46929$2830 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:46930.5-46930.29" - switch \initial - attribute \src "libresoc.v:46930.9-46930.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH__insn_type - case - assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] - end - attribute \src "libresoc.v:46958.3-46966.6" - process $proc$libresoc.v:46958$2831 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1468$next[0:0]$2832 $1\wr_pick_dly$1468$next[0:0]$2833 - attribute \src "libresoc.v:46959.5-46959.29" - switch \initial - attribute \src "libresoc.v:46959.9-46959.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1468$next[0:0]$2833 1'0 - case - assign $1\wr_pick_dly$1468$next[0:0]$2833 \wr_pick$1465 - end - sync always - update \wr_pick_dly$1468$next $0\wr_pick_dly$1468$next[0:0]$2832 - end - attribute \src "libresoc.v:46967.3-46975.6" - process $proc$libresoc.v:46967$2834 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1484$next[0:0]$2835 $1\wr_pick_dly$1484$next[0:0]$2836 - attribute \src "libresoc.v:46968.5-46968.29" - switch \initial - attribute \src "libresoc.v:46968.9-46968.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1484$next[0:0]$2836 1'0 - case - assign $1\wr_pick_dly$1484$next[0:0]$2836 \wr_pick$1481 - end - sync always - update \wr_pick_dly$1484$next $0\wr_pick_dly$1484$next[0:0]$2835 - end - attribute \src "libresoc.v:46976.3-47004.6" - process $proc$libresoc.v:46976$2837 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__fn_unit[11:0] $1\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "libresoc.v:46977.5-46977.29" - switch \initial - attribute \src "libresoc.v:46977.9-46977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] $2\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] $3\fus_oper_i_alu_branch0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH__fn_unit - case - assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[11:0] - end - attribute \src "libresoc.v:47005.3-47013.6" - process $proc$libresoc.v:47005$2838 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1500$next[0:0]$2839 $1\wr_pick_dly$1500$next[0:0]$2840 - attribute \src "libresoc.v:47006.5-47006.29" - switch \initial - attribute \src "libresoc.v:47006.9-47006.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1500$next[0:0]$2840 1'0 - case - assign $1\wr_pick_dly$1500$next[0:0]$2840 \wr_pick$1497 - end - sync always - update \wr_pick_dly$1500$next $0\wr_pick_dly$1500$next[0:0]$2839 - end - attribute \src "libresoc.v:47014.3-47042.6" - process $proc$libresoc.v:47014$2841 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47015.5-47015.29" - switch \initial - attribute \src "libresoc.v:47015.9-47015.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH__insn - case - assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] - end - attribute \src "libresoc.v:47043.3-47051.6" - process $proc$libresoc.v:47043$2842 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1536$next[0:0]$2843 $1\wr_pick_dly$1536$next[0:0]$2844 - attribute \src "libresoc.v:47044.5-47044.29" - switch \initial - attribute \src "libresoc.v:47044.9-47044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1536$next[0:0]$2844 1'0 - case - assign $1\wr_pick_dly$1536$next[0:0]$2844 \wr_pick$1533 - end - sync always - update \wr_pick_dly$1536$next $0\wr_pick_dly$1536$next[0:0]$2843 - end - attribute \src "libresoc.v:47052.3-47060.6" - process $proc$libresoc.v:47052$2845 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1552$next[0:0]$2846 $1\wr_pick_dly$1552$next[0:0]$2847 - attribute \src "libresoc.v:47053.5-47053.29" - switch \initial - attribute \src "libresoc.v:47053.9-47053.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1552$next[0:0]$2847 1'0 - case - assign $1\wr_pick_dly$1552$next[0:0]$2847 \wr_pick$1549 - end - sync always - update \wr_pick_dly$1552$next $0\wr_pick_dly$1552$next[0:0]$2846 - end - attribute \src "libresoc.v:47061.3-47090.6" - process $proc$libresoc.v:47061$2848 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47062.5-47062.29" - switch \initial - attribute \src "libresoc.v:47062.9-47062.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__data } - case - assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - end - attribute \src "libresoc.v:47091.3-47099.6" - process $proc$libresoc.v:47091$2849 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1568$next[0:0]$2850 $1\wr_pick_dly$1568$next[0:0]$2851 - attribute \src "libresoc.v:47092.5-47092.29" - switch \initial - attribute \src "libresoc.v:47092.9-47092.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1568$next[0:0]$2851 1'0 - case - assign $1\wr_pick_dly$1568$next[0:0]$2851 \wr_pick$1565 - end - sync always - update \wr_pick_dly$1568$next $0\wr_pick_dly$1568$next[0:0]$2850 - end - attribute \src "libresoc.v:47100.3-47108.6" - process $proc$libresoc.v:47100$2852 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1584$next[0:0]$2853 $1\wr_pick_dly$1584$next[0:0]$2854 - attribute \src "libresoc.v:47101.5-47101.29" - switch \initial - attribute \src "libresoc.v:47101.9-47101.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1584$next[0:0]$2854 1'0 - case - assign $1\wr_pick_dly$1584$next[0:0]$2854 \wr_pick$1581 - end - sync always - update \wr_pick_dly$1584$next $0\wr_pick_dly$1584$next[0:0]$2853 - end - attribute \src "libresoc.v:47109.3-47117.6" - process $proc$libresoc.v:47109$2855 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1626$next[0:0]$2856 $1\wr_pick_dly$1626$next[0:0]$2857 - attribute \src "libresoc.v:47110.5-47110.29" - switch \initial - attribute \src "libresoc.v:47110.9-47110.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1626$next[0:0]$2857 1'0 - case - assign $1\wr_pick_dly$1626$next[0:0]$2857 \wr_pick$1623 - end - sync always - update \wr_pick_dly$1626$next $0\wr_pick_dly$1626$next[0:0]$2856 - end - attribute \src "libresoc.v:47118.3-47146.6" - process $proc$libresoc.v:47118$2858 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47119.5-47119.29" - switch \initial - attribute \src "libresoc.v:47119.9-47119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk - case - assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] - end - attribute \src "libresoc.v:47147.3-47155.6" - process $proc$libresoc.v:47147$2859 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1645$next[0:0]$2860 $1\wr_pick_dly$1645$next[0:0]$2861 - attribute \src "libresoc.v:47148.5-47148.29" - switch \initial - attribute \src "libresoc.v:47148.9-47148.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1645$next[0:0]$2861 1'0 - case - assign $1\wr_pick_dly$1645$next[0:0]$2861 \wr_pick$1642 - end - sync always - update \wr_pick_dly$1645$next $0\wr_pick_dly$1645$next[0:0]$2860 - end - attribute \src "libresoc.v:47156.3-47184.6" - process $proc$libresoc.v:47156$2862 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47157.5-47157.29" - switch \initial - attribute \src "libresoc.v:47157.9-47157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit - case - assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] - end - attribute \src "libresoc.v:47185.3-47193.6" - process $proc$libresoc.v:47185$2863 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1661$next[0:0]$2864 $1\wr_pick_dly$1661$next[0:0]$2865 - attribute \src "libresoc.v:47186.5-47186.29" - switch \initial - attribute \src "libresoc.v:47186.9-47186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1661$next[0:0]$2865 1'0 - case - assign $1\wr_pick_dly$1661$next[0:0]$2865 \wr_pick$1658 - end - sync always - update \wr_pick_dly$1661$next $0\wr_pick_dly$1661$next[0:0]$2864 - end - attribute \src "libresoc.v:47194.3-47202.6" - process $proc$libresoc.v:47194$2866 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1677$next[0:0]$2867 $1\wr_pick_dly$1677$next[0:0]$2868 - attribute \src "libresoc.v:47195.5-47195.29" - switch \initial - attribute \src "libresoc.v:47195.9-47195.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1677$next[0:0]$2868 1'0 - case - assign $1\wr_pick_dly$1677$next[0:0]$2868 \wr_pick$1674 - end - sync always - update \wr_pick_dly$1677$next $0\wr_pick_dly$1677$next[0:0]$2867 - end - attribute \src "libresoc.v:47203.3-47231.6" - process $proc$libresoc.v:47203$2869 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$14[0:0]$2870 $1\fus_cu_issue_i$14[0:0]$2871 - attribute \src "libresoc.v:47204.5-47204.29" - switch \initial - attribute \src "libresoc.v:47204.9-47204.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$14[0:0]$2871 $2\fus_cu_issue_i$14[0:0]$2872 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$14[0:0]$2872 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$14[0:0]$2872 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$14[0:0]$2872 $3\fus_cu_issue_i$14[0:0]$2873 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$14[0:0]$2873 \issue_i - case - assign $3\fus_cu_issue_i$14[0:0]$2873 1'0 - end - end - case - assign $1\fus_cu_issue_i$14[0:0]$2871 1'0 - end - sync always - update \fus_cu_issue_i$14 $0\fus_cu_issue_i$14[0:0]$2870 - end - attribute \src "libresoc.v:47232.3-47240.6" - process $proc$libresoc.v:47232$2874 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1693$next[0:0]$2875 $1\wr_pick_dly$1693$next[0:0]$2876 - attribute \src "libresoc.v:47233.5-47233.29" - switch \initial - attribute \src "libresoc.v:47233.9-47233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1693$next[0:0]$2876 1'0 - case - assign $1\wr_pick_dly$1693$next[0:0]$2876 \wr_pick$1690 - end - sync always - update \wr_pick_dly$1693$next $0\wr_pick_dly$1693$next[0:0]$2875 - end - attribute \src "libresoc.v:47241.3-47269.6" - process $proc$libresoc.v:47241$2877 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$16[2:0]$2878 $1\fus_cu_rdmaskn_i$16[2:0]$2879 - attribute \src "libresoc.v:47242.5-47242.29" - switch \initial - attribute \src "libresoc.v:47242.9-47242.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$16[2:0]$2879 $2\fus_cu_rdmaskn_i$16[2:0]$2880 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$16[2:0]$2880 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$16[2:0]$2880 3'000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$16[2:0]$2880 $3\fus_cu_rdmaskn_i$16[2:0]$2881 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$16[2:0]$2881 \$245 - case - assign $3\fus_cu_rdmaskn_i$16[2:0]$2881 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$16[2:0]$2879 3'000 - end - sync always - update \fus_cu_rdmaskn_i$16 $0\fus_cu_rdmaskn_i$16[2:0]$2878 - end - attribute \src "libresoc.v:47270.3-47278.6" - process $proc$libresoc.v:47270$2882 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1737$next[0:0]$2883 $1\wr_pick_dly$1737$next[0:0]$2884 - attribute \src "libresoc.v:47271.5-47271.29" - switch \initial - attribute \src "libresoc.v:47271.9-47271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1737$next[0:0]$2884 1'0 - case - assign $1\wr_pick_dly$1737$next[0:0]$2884 \wr_pick$1734 - end - sync always - update \wr_pick_dly$1737$next $0\wr_pick_dly$1737$next[0:0]$2883 - end - attribute \src "libresoc.v:47279.3-47307.6" - process $proc$libresoc.v:47279$2885 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47280.5-47280.29" - switch \initial - attribute \src "libresoc.v:47280.9-47280.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type - case - assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] - end - attribute \src "libresoc.v:47308.3-47316.6" - process $proc$libresoc.v:47308$2886 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1753$next[0:0]$2887 $1\wr_pick_dly$1753$next[0:0]$2888 - attribute \src "libresoc.v:47309.5-47309.29" - switch \initial - attribute \src "libresoc.v:47309.9-47309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1753$next[0:0]$2888 1'0 - case - assign $1\wr_pick_dly$1753$next[0:0]$2888 \wr_pick$1750 - end - sync always - update \wr_pick_dly$1753$next $0\wr_pick_dly$1753$next[0:0]$2887 - end - attribute \src "libresoc.v:47317.3-47325.6" - process $proc$libresoc.v:47317$2889 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1777$next[0:0]$2890 $1\wr_pick_dly$1777$next[0:0]$2891 - attribute \src "libresoc.v:47318.5-47318.29" - switch \initial - attribute \src "libresoc.v:47318.9-47318.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1777$next[0:0]$2891 1'0 - case - assign $1\wr_pick_dly$1777$next[0:0]$2891 \wr_pick$1774 - end - sync always - update \wr_pick_dly$1777$next $0\wr_pick_dly$1777$next[0:0]$2890 - end - attribute \src "libresoc.v:47326.3-47354.6" - process $proc$libresoc.v:47326$2892 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__fn_unit[11:0] $1\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "libresoc.v:47327.5-47327.29" - switch \initial - attribute \src "libresoc.v:47327.9-47327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] $2\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] $3\fus_oper_i_alu_trap0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] \core_core_fn_unit - case - assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[11:0] - end - attribute \src "libresoc.v:47355.3-47363.6" - process $proc$libresoc.v:47355$2893 - assign { } { } - assign { } { } - assign $0\wr_pick_dly$1797$next[0:0]$2894 $1\wr_pick_dly$1797$next[0:0]$2895 - attribute \src "libresoc.v:47356.5-47356.29" - switch \initial - attribute \src "libresoc.v:47356.9-47356.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wr_pick_dly$1797$next[0:0]$2895 1'0 - case - assign $1\wr_pick_dly$1797$next[0:0]$2895 \wr_pick$1794 - end - sync always - update \wr_pick_dly$1797$next $0\wr_pick_dly$1797$next[0:0]$2894 - end - attribute \src "libresoc.v:47364.3-47392.6" - process $proc$libresoc.v:47364$2896 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47365.5-47365.29" - switch \initial - attribute \src "libresoc.v:47365.9-47365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn - case - assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] - end - attribute \src "libresoc.v:47393.3-47421.6" - process $proc$libresoc.v:47393$2897 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:47394.5-47394.29" - switch \initial - attribute \src "libresoc.v:47394.9-47394.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr - case - assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] - end - attribute \src "libresoc.v:47422.3-47450.6" - process $proc$libresoc.v:47422$2898 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47423.5-47423.29" - switch \initial - attribute \src "libresoc.v:47423.9-47423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia - case - assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] - end - attribute \src "libresoc.v:47451.3-47479.6" - process $proc$libresoc.v:47451$2899 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:47452.5-47452.29" - switch \initial - attribute \src "libresoc.v:47452.9-47452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit - case - assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] - end - attribute \src "libresoc.v:47480.3-47508.6" - process $proc$libresoc.v:47480$2900 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:47481.5-47481.29" - switch \initial - attribute \src "libresoc.v:47481.9-47481.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype - case - assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 - end - sync always - update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] - end - attribute \src "libresoc.v:47509.3-47537.6" - process $proc$libresoc.v:47509$2901 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:47510.5-47510.29" - switch \initial - attribute \src "libresoc.v:47510.9-47510.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr - case - assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 - end - sync always - update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] - end - attribute \src "libresoc.v:47538.3-47566.6" - process $proc$libresoc.v:47538$2902 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:47539.5-47539.29" - switch \initial - attribute \src "libresoc.v:47539.9-47539.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } - case - assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - end - end - case - assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 - end - sync always - update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - end - attribute \src "libresoc.v:47567.3-47595.6" - process $proc$libresoc.v:47567$2903 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$17[0:0]$2904 $1\fus_cu_issue_i$17[0:0]$2905 - attribute \src "libresoc.v:47568.5-47568.29" - switch \initial - attribute \src "libresoc.v:47568.9-47568.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$17[0:0]$2905 $2\fus_cu_issue_i$17[0:0]$2906 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$17[0:0]$2906 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$17[0:0]$2906 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$17[0:0]$2906 $3\fus_cu_issue_i$17[0:0]$2907 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$17[0:0]$2907 \issue_i - case - assign $3\fus_cu_issue_i$17[0:0]$2907 1'0 - end - end - case - assign $1\fus_cu_issue_i$17[0:0]$2905 1'0 - end - sync always - update \fus_cu_issue_i$17 $0\fus_cu_issue_i$17[0:0]$2904 - end - attribute \src "libresoc.v:47596.3-47624.6" - process $proc$libresoc.v:47596$2908 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$19[3:0]$2909 $1\fus_cu_rdmaskn_i$19[3:0]$2910 - attribute \src "libresoc.v:47597.5-47597.29" - switch \initial - attribute \src "libresoc.v:47597.9-47597.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$19[3:0]$2910 $2\fus_cu_rdmaskn_i$19[3:0]$2911 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$19[3:0]$2911 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$19[3:0]$2911 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$19[3:0]$2911 $3\fus_cu_rdmaskn_i$19[3:0]$2912 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$19[3:0]$2912 \$247 - case - assign $3\fus_cu_rdmaskn_i$19[3:0]$2912 4'0000 - end - end - case - assign $1\fus_cu_rdmaskn_i$19[3:0]$2910 4'0000 - end - sync always - update \fus_cu_rdmaskn_i$19 $0\fus_cu_rdmaskn_i$19[3:0]$2909 - end - attribute \src "libresoc.v:47625.3-47653.6" - process $proc$libresoc.v:47625$2913 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:47626.5-47626.29" - switch \initial - attribute \src "libresoc.v:47626.9-47626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL__insn_type - case - assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] - end - attribute \src "libresoc.v:47654.3-47682.6" - process $proc$libresoc.v:47654$2914 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__fn_unit[11:0] $1\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "libresoc.v:47655.5-47655.29" - switch \initial - attribute \src "libresoc.v:47655.9-47655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] $2\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] $3\fus_oper_i_alu_logical0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL__fn_unit - case - assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[11:0] - end - attribute \src "libresoc.v:47683.3-47712.6" - process $proc$libresoc.v:47683$2915 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:47684.5-47684.29" - switch \initial - attribute \src "libresoc.v:47684.9-47684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__data } - case - assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - end - attribute \src "libresoc.v:47713.3-47742.6" - process $proc$libresoc.v:47713$2916 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] - assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:47714.5-47714.29" - switch \initial - attribute \src "libresoc.v:47714.9-47714.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] - assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] - assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__rc } - case - assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 - assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] - update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] - end - attribute \src "libresoc.v:47743.3-47772.6" - process $proc$libresoc.v:47743$2917 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] - assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:47744.5-47744.29" - switch \initial - attribute \src "libresoc.v:47744.9-47744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] - assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] - assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__oe } - case - assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 - assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] - update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] - end - attribute \src "libresoc.v:47773.3-47801.6" - process $proc$libresoc.v:47773$2918 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:47774.5-47774.29" - switch \initial - attribute \src "libresoc.v:47774.9-47774.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL__invert_in - case - assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] - end - attribute \src "libresoc.v:47802.3-47830.6" - process $proc$libresoc.v:47802$2919 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:47803.5-47803.29" - switch \initial - attribute \src "libresoc.v:47803.9-47803.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL__zero_a - case - assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] - end - attribute \src "libresoc.v:47831.3-47859.6" - process $proc$libresoc.v:47831$2920 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:47832.5-47832.29" - switch \initial - attribute \src "libresoc.v:47832.9-47832.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL__input_carry - case - assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - end - end - case - assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 - end - sync always - update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] - end - attribute \src "libresoc.v:47860.3-47888.6" - process $proc$libresoc.v:47860$2921 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:47861.5-47861.29" - switch \initial - attribute \src "libresoc.v:47861.9-47861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL__invert_out - case - assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] - end - attribute \src "libresoc.v:47889.3-47917.6" - process $proc$libresoc.v:47889$2922 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:47890.5-47890.29" - switch \initial - attribute \src "libresoc.v:47890.9-47890.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL__write_cr0 - case - assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] - end - attribute \src "libresoc.v:47918.3-47946.6" - process $proc$libresoc.v:47918$2923 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:47919.5-47919.29" - switch \initial - attribute \src "libresoc.v:47919.9-47919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry - case - assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] - end - attribute \src "libresoc.v:47947.3-47975.6" - process $proc$libresoc.v:47947$2924 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:47948.5-47948.29" - switch \initial - attribute \src "libresoc.v:47948.9-47948.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit - case - assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] - end - attribute \src "libresoc.v:47976.3-48004.6" - process $proc$libresoc.v:47976$2925 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:47977.5-47977.29" - switch \initial - attribute \src "libresoc.v:47977.9-47977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed - case - assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - end - case - assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 - end - sync always - update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] - end - attribute \src "libresoc.v:48005.3-48033.6" - process $proc$libresoc.v:48005$2926 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48006.5-48006.29" - switch \initial - attribute \src "libresoc.v:48006.9-48006.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len - case - assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - end - case - assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 - end - sync always - update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] - end - attribute \src "libresoc.v:48034.3-48062.6" - process $proc$libresoc.v:48034$2927 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48035.5-48035.29" - switch \initial - attribute \src "libresoc.v:48035.9-48035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn - case - assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 - end - end - case - assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 - end - sync always - update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] - end - attribute \src "libresoc.v:48063.3-48091.6" - process $proc$libresoc.v:48063$2928 - assign { } { } - assign { } { } - assign $0\fus_cu_issue_i$20[0:0]$2929 $1\fus_cu_issue_i$20[0:0]$2930 - attribute \src "libresoc.v:48064.5-48064.29" - switch \initial - attribute \src "libresoc.v:48064.9-48064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_issue_i$20[0:0]$2930 $2\fus_cu_issue_i$20[0:0]$2931 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_issue_i$20[0:0]$2931 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_issue_i$20[0:0]$2931 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_issue_i$20[0:0]$2931 $3\fus_cu_issue_i$20[0:0]$2932 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_issue_i$20[0:0]$2932 \issue_i - case - assign $3\fus_cu_issue_i$20[0:0]$2932 1'0 - end - end - case - assign $1\fus_cu_issue_i$20[0:0]$2930 1'0 - end - sync always - update \fus_cu_issue_i$20 $0\fus_cu_issue_i$20[0:0]$2929 - end - attribute \src "libresoc.v:48092.3-48120.6" - process $proc$libresoc.v:48092$2933 - assign { } { } - assign { } { } - assign $0\fus_cu_rdmaskn_i$22[2:0]$2934 $1\fus_cu_rdmaskn_i$22[2:0]$2935 - attribute \src "libresoc.v:48093.5-48093.29" - switch \initial - attribute \src "libresoc.v:48093.9-48093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_cu_rdmaskn_i$22[2:0]$2935 $2\fus_cu_rdmaskn_i$22[2:0]$2936 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_cu_rdmaskn_i$22[2:0]$2936 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_cu_rdmaskn_i$22[2:0]$2936 3'000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_cu_rdmaskn_i$22[2:0]$2936 $3\fus_cu_rdmaskn_i$22[2:0]$2937 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_cu_rdmaskn_i$22[2:0]$2937 \$249 - case - assign $3\fus_cu_rdmaskn_i$22[2:0]$2937 3'000 - end - end - case - assign $1\fus_cu_rdmaskn_i$22[2:0]$2935 3'000 - end - sync always - update \fus_cu_rdmaskn_i$22 $0\fus_cu_rdmaskn_i$22[2:0]$2934 - end - attribute \src "libresoc.v:48121.3-48149.6" - process $proc$libresoc.v:48121$2938 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:48122.5-48122.29" - switch \initial - attribute \src "libresoc.v:48122.9-48122.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type - case - assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 - end - sync always - update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] - end - attribute \src "libresoc.v:48150.3-48178.6" - process $proc$libresoc.v:48150$2939 - assign { } { } - assign { } { } - assign $0\fus_oper_i_alu_spr0__fn_unit[11:0] $1\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "libresoc.v:48151.5-48151.29" - switch \initial - attribute \src "libresoc.v:48151.9-48151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" - switch \ivalid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] $2\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - switch \core_core_insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000001 - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] $3\fus_oper_i_alu_spr0__fn_unit[11:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" - switch \fu_enable [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR__fn_unit - case - assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - end - end - case - assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 - end - sync always - update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[11:0] - end - connect \$1002 $not$libresoc.v:41720$1546_Y - connect \$1004 $and$libresoc.v:41721$1547_Y - connect \$1011 $and$libresoc.v:41722$1548_Y - connect \$1014 $ternary$libresoc.v:41723$1549_Y - connect \$1016 $and$libresoc.v:41724$1550_Y - connect \$1019 $and$libresoc.v:41725$1551_Y - connect \$1023 $not$libresoc.v:41726$1552_Y - connect \$1025 $and$libresoc.v:41727$1553_Y - connect \$1029 $and$libresoc.v:41728$1554_Y - connect \$1032 $ternary$libresoc.v:41729$1555_Y - connect \$1034 $and$libresoc.v:41730$1556_Y - connect \$1037 $and$libresoc.v:41731$1557_Y - connect \$1041 $not$libresoc.v:41732$1558_Y - connect \$1043 $and$libresoc.v:41733$1559_Y - connect \$1051 $and$libresoc.v:41734$1560_Y - connect \$1054 $ternary$libresoc.v:41735$1561_Y - connect \$1056 $and$libresoc.v:41736$1562_Y - connect \$1059 $and$libresoc.v:41737$1563_Y - connect \$1063 $not$libresoc.v:41738$1564_Y - connect \$1065 $and$libresoc.v:41739$1565_Y - connect \$1071 $and$libresoc.v:41740$1566_Y - connect \$1074 $ternary$libresoc.v:41741$1567_Y - connect \$1076 $and$libresoc.v:41742$1568_Y - connect \$1079 $and$libresoc.v:41743$1569_Y - connect \$1083 $not$libresoc.v:41744$1570_Y - connect \$1085 $and$libresoc.v:41745$1571_Y - connect \$1091 $and$libresoc.v:41746$1572_Y - connect \$1094 $ternary$libresoc.v:41747$1573_Y - connect \$1096 $and$libresoc.v:41748$1574_Y - connect \$1099 $and$libresoc.v:41749$1575_Y - connect \$1103 $not$libresoc.v:41750$1576_Y - connect \$1105 $and$libresoc.v:41751$1577_Y - connect \$1110 $and$libresoc.v:41752$1578_Y - connect \$1113 $ternary$libresoc.v:41753$1579_Y - connect \$1115 $and$libresoc.v:41754$1580_Y - connect \$1118 $and$libresoc.v:41755$1581_Y - connect \$1122 $not$libresoc.v:41756$1582_Y - connect \$1124 $and$libresoc.v:41757$1583_Y - connect \$1128 $and$libresoc.v:41758$1584_Y - connect \$1131 $ternary$libresoc.v:41759$1585_Y - connect \$1133 $and$libresoc.v:41760$1586_Y - connect \$1136 $and$libresoc.v:41761$1587_Y - connect \$1139 $not$libresoc.v:41762$1588_Y - connect \$1141 $and$libresoc.v:41763$1589_Y - connect \$1144 $and$libresoc.v:41764$1590_Y - connect \$1147 $ternary$libresoc.v:41765$1591_Y - connect \$1150 $or$libresoc.v:41766$1592_Y - connect \$1152 $or$libresoc.v:41767$1593_Y - connect \$1154 $or$libresoc.v:41768$1594_Y - connect \$1156 $or$libresoc.v:41769$1595_Y - connect \$1158 $or$libresoc.v:41770$1596_Y - connect \$1160 $or$libresoc.v:41771$1597_Y - connect \$1162 $or$libresoc.v:41772$1598_Y - connect \$1164 $or$libresoc.v:41773$1599_Y - connect \$1166 $or$libresoc.v:41774$1600_Y - connect \$1168 $or$libresoc.v:41775$1601_Y - connect \$1170 $or$libresoc.v:41776$1602_Y - connect \$1172 $or$libresoc.v:41777$1603_Y - connect \$1174 $or$libresoc.v:41778$1604_Y - connect \$1176 $or$libresoc.v:41779$1605_Y - connect \$1178 $or$libresoc.v:41780$1606_Y - connect \$1180 $or$libresoc.v:41781$1607_Y - connect \$1182 $or$libresoc.v:41782$1608_Y - connect \$1184 $or$libresoc.v:41783$1609_Y - connect \$1186 $or$libresoc.v:41784$1610_Y - connect \$1188 $or$libresoc.v:41785$1611_Y - connect \$1190 $or$libresoc.v:41786$1612_Y - connect \$1192 $or$libresoc.v:41787$1613_Y - connect \$1194 $or$libresoc.v:41788$1614_Y - connect \$1196 $or$libresoc.v:41789$1615_Y - connect \$1198 $or$libresoc.v:41790$1616_Y - connect \$1200 $or$libresoc.v:41791$1617_Y - connect \$1202 $or$libresoc.v:41792$1618_Y - connect \$1204 $and$libresoc.v:41793$1619_Y - connect \$1206 $and$libresoc.v:41794$1620_Y - connect \$1209 $and$libresoc.v:41795$1621_Y - connect \$1212 $not$libresoc.v:41796$1622_Y - connect \$1214 $and$libresoc.v:41797$1623_Y - connect \$1217 $and$libresoc.v:41798$1624_Y - connect \$1220 $ternary$libresoc.v:41799$1625_Y - connect \$1222 $and$libresoc.v:41800$1626_Y - connect \$1224 $and$libresoc.v:41801$1627_Y - connect \$1226 $and$libresoc.v:41802$1628_Y - connect \$1228 $and$libresoc.v:41803$1629_Y - connect \$1230 $and$libresoc.v:41804$1630_Y - connect \$1232 $and$libresoc.v:41805$1631_Y - connect \$1234 $and$libresoc.v:41806$1632_Y - connect \$1237 $and$libresoc.v:41807$1633_Y - connect \$1240 $not$libresoc.v:41808$1634_Y - connect \$1242 $and$libresoc.v:41809$1635_Y - connect \$1245 $and$libresoc.v:41810$1636_Y - connect \$1248 $sub$libresoc.v:41811$1637_Y - connect \$1250 $sshl$libresoc.v:41812$1638_Y - connect \$1252 $ternary$libresoc.v:41813$1639_Y - connect \$1254 $and$libresoc.v:41814$1640_Y - connect \$1257 $and$libresoc.v:41815$1641_Y - connect \$1260 $not$libresoc.v:41816$1642_Y - connect \$1262 $and$libresoc.v:41817$1643_Y - connect \$1265 $and$libresoc.v:41818$1644_Y - connect \$1268 $sub$libresoc.v:41819$1645_Y - connect \$1270 $sshl$libresoc.v:41820$1646_Y - connect \$1272 $ternary$libresoc.v:41821$1647_Y - connect \$1274 $and$libresoc.v:41822$1648_Y - connect \$1277 $and$libresoc.v:41823$1649_Y - connect \$1280 $not$libresoc.v:41824$1650_Y - connect \$1282 $and$libresoc.v:41825$1651_Y - connect \$1285 $and$libresoc.v:41826$1652_Y - connect \$1288 $sub$libresoc.v:41827$1653_Y - connect \$1290 $sshl$libresoc.v:41828$1654_Y - connect \$1292 $ternary$libresoc.v:41829$1655_Y - connect \$1294 $and$libresoc.v:41830$1656_Y - connect \$1297 $and$libresoc.v:41831$1657_Y - connect \$1300 $not$libresoc.v:41832$1658_Y - connect \$1302 $and$libresoc.v:41833$1659_Y - connect \$1305 $and$libresoc.v:41834$1660_Y - connect \$1308 $sub$libresoc.v:41835$1661_Y - connect \$1310 $sshl$libresoc.v:41836$1662_Y - connect \$1312 $ternary$libresoc.v:41837$1663_Y - connect \$1314 $and$libresoc.v:41838$1664_Y - connect \$1317 $and$libresoc.v:41839$1665_Y - connect \$1320 $not$libresoc.v:41840$1666_Y - connect \$1322 $and$libresoc.v:41841$1667_Y - connect \$1325 $and$libresoc.v:41842$1668_Y - connect \$1328 $sub$libresoc.v:41843$1669_Y - connect \$1330 $sshl$libresoc.v:41844$1670_Y - connect \$1332 $ternary$libresoc.v:41845$1671_Y - connect \$1334 $and$libresoc.v:41846$1672_Y - connect \$1337 $and$libresoc.v:41847$1673_Y - connect \$1340 $not$libresoc.v:41848$1674_Y - connect \$1342 $and$libresoc.v:41849$1675_Y - connect \$1345 $and$libresoc.v:41850$1676_Y - connect \$1348 $sub$libresoc.v:41851$1677_Y - connect \$1350 $sshl$libresoc.v:41852$1678_Y - connect \$1352 $ternary$libresoc.v:41853$1679_Y - connect \$1354 $or$libresoc.v:41854$1680_Y - connect \$1356 $or$libresoc.v:41855$1681_Y - connect \$1358 $or$libresoc.v:41856$1682_Y - connect \$1360 $or$libresoc.v:41857$1683_Y - connect \$1362 $or$libresoc.v:41858$1684_Y - connect \$1365 $or$libresoc.v:41859$1685_Y - connect \$1367 $or$libresoc.v:41860$1686_Y - connect \$1369 $or$libresoc.v:41861$1687_Y - connect \$1371 $or$libresoc.v:41862$1688_Y - connect \$1373 $or$libresoc.v:41863$1689_Y - connect \$1375 $and$libresoc.v:41864$1690_Y - connect \$1377 $and$libresoc.v:41865$1691_Y - connect \$1379 $and$libresoc.v:41866$1692_Y - connect \$1381 $and$libresoc.v:41867$1693_Y - connect \$1384 $and$libresoc.v:41868$1694_Y - connect \$1387 $not$libresoc.v:41869$1695_Y - connect \$1389 $and$libresoc.v:41870$1696_Y - connect \$1392 $and$libresoc.v:41871$1697_Y - connect \$1395 $ternary$libresoc.v:41872$1698_Y - connect \$1397 $and$libresoc.v:41873$1699_Y - connect \$1400 $and$libresoc.v:41874$1700_Y - connect \$1403 $not$libresoc.v:41875$1701_Y - connect \$1405 $and$libresoc.v:41876$1702_Y - connect \$1408 $and$libresoc.v:41877$1703_Y - connect \$1411 $ternary$libresoc.v:41878$1704_Y - connect \$1413 $and$libresoc.v:41879$1705_Y - connect \$1416 $and$libresoc.v:41880$1706_Y - connect \$1419 $not$libresoc.v:41881$1707_Y - connect \$1421 $and$libresoc.v:41882$1708_Y - connect \$1424 $and$libresoc.v:41883$1709_Y - connect \$1427 $ternary$libresoc.v:41884$1710_Y - connect \$1429 $or$libresoc.v:41885$1711_Y - connect \$1431 $or$libresoc.v:41886$1712_Y - connect \$1434 $or$libresoc.v:41887$1713_Y - connect \$1436 $or$libresoc.v:41888$1714_Y - connect \$1433 $pos$libresoc.v:41889$1716_Y - connect \$1439 $and$libresoc.v:41890$1717_Y - connect \$1441 $and$libresoc.v:41891$1718_Y - connect \$1443 $and$libresoc.v:41892$1719_Y - connect \$1445 $and$libresoc.v:41893$1720_Y - connect \$1447 $and$libresoc.v:41894$1721_Y - connect \$1450 $and$libresoc.v:41895$1722_Y - connect \$1453 $not$libresoc.v:41896$1723_Y - connect \$1455 $and$libresoc.v:41897$1724_Y - connect \$1458 $and$libresoc.v:41898$1725_Y - connect \$1461 $ternary$libresoc.v:41899$1726_Y - connect \$1463 $and$libresoc.v:41900$1727_Y - connect \$1466 $and$libresoc.v:41901$1728_Y - connect \$1469 $not$libresoc.v:41902$1729_Y - connect \$1471 $and$libresoc.v:41903$1730_Y - connect \$1474 $and$libresoc.v:41904$1731_Y - connect \$1477 $ternary$libresoc.v:41905$1732_Y - connect \$1479 $and$libresoc.v:41906$1733_Y - connect \$1482 $and$libresoc.v:41907$1734_Y - connect \$1485 $not$libresoc.v:41908$1735_Y - connect \$1487 $and$libresoc.v:41909$1736_Y - connect \$1490 $and$libresoc.v:41910$1737_Y - connect \$1493 $ternary$libresoc.v:41911$1738_Y - connect \$1495 $and$libresoc.v:41912$1739_Y - connect \$1498 $and$libresoc.v:41913$1740_Y - connect \$1501 $not$libresoc.v:41914$1741_Y - connect \$1503 $and$libresoc.v:41915$1742_Y - connect \$1506 $and$libresoc.v:41916$1743_Y - connect \$1509 $ternary$libresoc.v:41917$1744_Y - connect \$1511 $or$libresoc.v:41918$1745_Y - connect \$1513 $or$libresoc.v:41919$1746_Y - connect \$1515 $or$libresoc.v:41920$1747_Y - connect \$1517 $or$libresoc.v:41921$1748_Y - connect \$1519 $or$libresoc.v:41922$1749_Y - connect \$1521 $or$libresoc.v:41923$1750_Y - connect \$1523 $and$libresoc.v:41924$1751_Y - connect \$1525 $and$libresoc.v:41925$1752_Y - connect \$1527 $and$libresoc.v:41926$1753_Y - connect \$1529 $and$libresoc.v:41927$1754_Y - connect \$1531 $and$libresoc.v:41928$1755_Y - connect \$1534 $and$libresoc.v:41929$1756_Y - connect \$1537 $not$libresoc.v:41930$1757_Y - connect \$1539 $and$libresoc.v:41931$1758_Y - connect \$1542 $and$libresoc.v:41932$1759_Y - connect \$1545 $ternary$libresoc.v:41933$1760_Y - connect \$1547 $and$libresoc.v:41934$1761_Y - connect \$1550 $and$libresoc.v:41935$1762_Y - connect \$1553 $not$libresoc.v:41936$1763_Y - connect \$1555 $and$libresoc.v:41937$1764_Y - connect \$1558 $and$libresoc.v:41938$1765_Y - connect \$1561 $ternary$libresoc.v:41939$1766_Y - connect \$1563 $and$libresoc.v:41940$1767_Y - connect \$1566 $and$libresoc.v:41941$1768_Y - connect \$1569 $not$libresoc.v:41942$1769_Y - connect \$1571 $and$libresoc.v:41943$1770_Y - connect \$1574 $and$libresoc.v:41944$1771_Y - connect \$1577 $ternary$libresoc.v:41945$1772_Y - connect \$1579 $and$libresoc.v:41946$1773_Y - connect \$1582 $and$libresoc.v:41947$1774_Y - connect \$1585 $not$libresoc.v:41948$1775_Y - connect \$1587 $and$libresoc.v:41949$1776_Y - connect \$1590 $and$libresoc.v:41950$1777_Y - connect \$1593 $ternary$libresoc.v:41951$1778_Y - connect \$1596 $or$libresoc.v:41952$1779_Y - connect \$1598 $or$libresoc.v:41953$1780_Y - connect \$1600 $or$libresoc.v:41954$1781_Y - connect \$1595 $pos$libresoc.v:41955$1783_Y - connect \$1604 $or$libresoc.v:41956$1784_Y - connect \$1606 $or$libresoc.v:41957$1785_Y - connect \$1608 $or$libresoc.v:41958$1786_Y - connect \$1603 $pos$libresoc.v:41959$1788_Y - connect \$1611 $and$libresoc.v:41960$1789_Y - connect \$1613 $and$libresoc.v:41961$1790_Y - connect \$1615 $and$libresoc.v:41962$1791_Y - connect \$1617 $and$libresoc.v:41963$1792_Y - connect \$1619 $and$libresoc.v:41964$1793_Y - connect \$1621 $and$libresoc.v:41965$1794_Y - connect \$1624 $and$libresoc.v:41966$1795_Y - connect \$1628 $not$libresoc.v:41967$1796_Y - connect \$1630 $and$libresoc.v:41968$1797_Y - connect \$1635 $and$libresoc.v:41969$1798_Y - connect \$1638 $ternary$libresoc.v:41970$1799_Y - connect \$1640 $and$libresoc.v:41971$1800_Y - connect \$1643 $and$libresoc.v:41972$1801_Y - connect \$1646 $not$libresoc.v:41973$1802_Y - connect \$1648 $and$libresoc.v:41974$1803_Y - connect \$1651 $and$libresoc.v:41975$1804_Y - connect \$1654 $ternary$libresoc.v:41976$1805_Y - connect \$1656 $and$libresoc.v:41977$1806_Y - connect \$1659 $and$libresoc.v:41978$1807_Y - connect \$1662 $not$libresoc.v:41979$1808_Y - connect \$1664 $and$libresoc.v:41980$1809_Y - connect \$1667 $and$libresoc.v:41981$1810_Y - connect \$1670 $ternary$libresoc.v:41982$1811_Y - connect \$1672 $and$libresoc.v:41983$1812_Y - connect \$1675 $and$libresoc.v:41984$1813_Y - connect \$1678 $not$libresoc.v:41985$1814_Y - connect \$1680 $and$libresoc.v:41986$1815_Y - connect \$1683 $and$libresoc.v:41987$1816_Y - connect \$1686 $ternary$libresoc.v:41988$1817_Y - connect \$1688 $and$libresoc.v:41989$1818_Y - connect \$1691 $and$libresoc.v:41990$1819_Y - connect \$1694 $not$libresoc.v:41991$1820_Y - connect \$1696 $and$libresoc.v:41992$1821_Y - connect \$1699 $and$libresoc.v:41993$1822_Y - connect \$1702 $ternary$libresoc.v:41994$1823_Y - connect \$1704 $or$libresoc.v:41995$1824_Y - connect \$1706 $or$libresoc.v:41996$1825_Y - connect \$1708 $or$libresoc.v:41997$1826_Y - connect \$1710 $or$libresoc.v:41998$1827_Y - connect \$1712 $or$libresoc.v:41999$1828_Y - connect \$1714 $or$libresoc.v:42000$1829_Y - connect \$1716 $or$libresoc.v:42001$1830_Y - connect \$1718 $or$libresoc.v:42002$1831_Y - connect \$1720 $or$libresoc.v:42003$1832_Y - connect \$1722 $or$libresoc.v:42004$1833_Y - connect \$1724 $or$libresoc.v:42005$1834_Y - connect \$1726 $or$libresoc.v:42006$1835_Y - connect \$1728 $and$libresoc.v:42007$1836_Y - connect \$1730 $and$libresoc.v:42008$1837_Y - connect \$1732 $and$libresoc.v:42009$1838_Y - connect \$1735 $and$libresoc.v:42010$1839_Y - connect \$1738 $not$libresoc.v:42011$1840_Y - connect \$1740 $and$libresoc.v:42012$1841_Y - connect \$1743 $and$libresoc.v:42013$1842_Y - connect \$1746 $ternary$libresoc.v:42014$1843_Y - connect \$1748 $and$libresoc.v:42015$1844_Y - connect \$1751 $and$libresoc.v:42016$1845_Y - connect \$1754 $not$libresoc.v:42017$1846_Y - connect \$1756 $and$libresoc.v:42018$1847_Y - connect \$175 $and$libresoc.v:42019$1848_Y - connect \$1759 $and$libresoc.v:42020$1849_Y - connect \$1762 $ternary$libresoc.v:42021$1850_Y - connect \$1764 $or$libresoc.v:42022$1851_Y - connect \$1767 $or$libresoc.v:42023$1852_Y - connect \$1766 $pos$libresoc.v:42024$1854_Y - connect \$174 $reduce_or$libresoc.v:42025$1855_Y - connect \$1770 $and$libresoc.v:42026$1856_Y - connect \$1772 $and$libresoc.v:42027$1857_Y - connect \$1775 $and$libresoc.v:42028$1858_Y - connect \$1778 $not$libresoc.v:42029$1859_Y - connect \$1780 $and$libresoc.v:42030$1860_Y - connect \$1783 $and$libresoc.v:42031$1861_Y - connect \$1786 $ternary$libresoc.v:42032$1862_Y - connect \$1788 $pos$libresoc.v:42033$1864_Y - connect \$1790 $and$libresoc.v:42034$1865_Y - connect \$1792 $and$libresoc.v:42035$1866_Y - connect \$1795 $and$libresoc.v:42036$1867_Y - connect \$1798 $not$libresoc.v:42037$1868_Y - connect \$179 $and$libresoc.v:42038$1869_Y - connect \$1800 $and$libresoc.v:42039$1870_Y - connect \$1803 $and$libresoc.v:42040$1871_Y - connect \$1806 $ternary$libresoc.v:42041$1872_Y - connect \$178 $reduce_or$libresoc.v:42042$1873_Y - connect \$183 $and$libresoc.v:42043$1874_Y - connect \$182 $reduce_or$libresoc.v:42044$1875_Y - connect \$187 $and$libresoc.v:42045$1876_Y - connect \$186 $reduce_or$libresoc.v:42046$1877_Y - connect \$191 $and$libresoc.v:42047$1878_Y - connect \$190 $reduce_or$libresoc.v:42048$1879_Y - connect \$195 $and$libresoc.v:42049$1880_Y - connect \$194 $reduce_or$libresoc.v:42050$1881_Y - connect \$199 $and$libresoc.v:42051$1882_Y - connect \$198 $reduce_or$libresoc.v:42052$1883_Y - connect \$203 $and$libresoc.v:42053$1884_Y - connect \$202 $reduce_or$libresoc.v:42054$1885_Y - connect \$207 $and$libresoc.v:42055$1886_Y - connect \$206 $reduce_or$libresoc.v:42056$1887_Y - connect \$211 $and$libresoc.v:42057$1888_Y - connect \$210 $reduce_or$libresoc.v:42058$1889_Y - connect \$214 $ne$libresoc.v:42059$1890_Y - connect \$217 $sub$libresoc.v:42060$1891_Y - connect \$219 $ne$libresoc.v:42061$1892_Y - connect \$222 $and$libresoc.v:42062$1893_Y - connect \$224 $and$libresoc.v:42063$1894_Y - connect \$226 $eq$libresoc.v:42064$1895_Y - connect \$228 $or$libresoc.v:42065$1896_Y - connect \$230 $and$libresoc.v:42066$1897_Y - connect \$232 $or$libresoc.v:42067$1898_Y - connect \$234 $eq$libresoc.v:42068$1899_Y - connect \$236 $and$libresoc.v:42069$1900_Y - connect \$238 $eq$libresoc.v:42070$1901_Y - connect \$240 $or$libresoc.v:42071$1902_Y - connect \$221 $not$libresoc.v:42072$1903_Y - connect \$243 $not$libresoc.v:42073$1904_Y - connect \$245 $not$libresoc.v:42074$1905_Y - connect \$247 $not$libresoc.v:42075$1906_Y - connect \$250 $and$libresoc.v:42076$1907_Y - connect \$252 $and$libresoc.v:42077$1908_Y - connect \$254 $eq$libresoc.v:42078$1909_Y - connect \$256 $or$libresoc.v:42079$1910_Y - connect \$258 $and$libresoc.v:42080$1911_Y - connect \$260 $or$libresoc.v:42081$1912_Y - connect \$249 $not$libresoc.v:42082$1913_Y - connect \$264 $and$libresoc.v:42083$1914_Y - connect \$266 $and$libresoc.v:42084$1915_Y - connect \$268 $eq$libresoc.v:42085$1916_Y - connect \$270 $or$libresoc.v:42086$1917_Y - connect \$272 $and$libresoc.v:42087$1918_Y - connect \$274 $or$libresoc.v:42088$1919_Y - connect \$276 $and$libresoc.v:42089$1920_Y - connect \$278 $and$libresoc.v:42090$1921_Y - connect \$280 $eq$libresoc.v:42091$1922_Y - connect \$282 $or$libresoc.v:42092$1923_Y - connect \$284 $eq$libresoc.v:42093$1924_Y - connect \$286 $and$libresoc.v:42094$1925_Y - connect \$288 $eq$libresoc.v:42095$1926_Y - connect \$290 $or$libresoc.v:42096$1927_Y - connect \$263 $not$libresoc.v:42097$1928_Y - connect \$294 $and$libresoc.v:42098$1929_Y - connect \$296 $and$libresoc.v:42099$1930_Y - connect \$298 $eq$libresoc.v:42100$1931_Y - connect \$300 $or$libresoc.v:42101$1932_Y - connect \$302 $and$libresoc.v:42102$1933_Y - connect \$304 $or$libresoc.v:42103$1934_Y - connect \$293 $not$libresoc.v:42104$1935_Y - connect \$308 $and$libresoc.v:42105$1936_Y - connect \$310 $and$libresoc.v:42106$1937_Y - connect \$312 $eq$libresoc.v:42107$1938_Y - connect \$314 $or$libresoc.v:42108$1939_Y - connect \$316 $and$libresoc.v:42109$1940_Y - connect \$318 $or$libresoc.v:42110$1941_Y - connect \$307 $not$libresoc.v:42111$1942_Y - connect \$322 $and$libresoc.v:42112$1943_Y - connect \$324 $and$libresoc.v:42113$1944_Y - connect \$326 $eq$libresoc.v:42114$1945_Y - connect \$328 $or$libresoc.v:42115$1946_Y - connect \$330 $and$libresoc.v:42116$1947_Y - connect \$332 $or$libresoc.v:42117$1948_Y - connect \$334 $eq$libresoc.v:42118$1949_Y - connect \$336 $and$libresoc.v:42119$1950_Y - connect \$338 $eq$libresoc.v:42120$1951_Y - connect \$340 $or$libresoc.v:42121$1952_Y - connect \$321 $not$libresoc.v:42122$1953_Y - connect \$343 $not$libresoc.v:42123$1954_Y - connect \$345 $and$libresoc.v:42124$1955_Y - connect \$347 $and$libresoc.v:42125$1956_Y - connect \$349 $not$libresoc.v:42126$1957_Y - connect \$351 $and$libresoc.v:42127$1958_Y - connect \$353 $and$libresoc.v:42128$1959_Y - connect \$355 $ternary$libresoc.v:42129$1960_Y - connect \$357 $and$libresoc.v:42130$1961_Y - connect \$359 $and$libresoc.v:42131$1962_Y - connect \$361 $not$libresoc.v:42132$1963_Y - connect \$363 $and$libresoc.v:42133$1964_Y - connect \$365 $and$libresoc.v:42134$1965_Y - connect \$367 $ternary$libresoc.v:42135$1966_Y - connect \$369 $and$libresoc.v:42136$1967_Y - connect \$371 $and$libresoc.v:42137$1968_Y - connect \$373 $not$libresoc.v:42138$1969_Y - connect \$375 $and$libresoc.v:42139$1970_Y - connect \$377 $and$libresoc.v:42140$1971_Y - connect \$379 $ternary$libresoc.v:42141$1972_Y - connect \$381 $and$libresoc.v:42142$1973_Y - connect \$383 $and$libresoc.v:42143$1974_Y - connect \$385 $not$libresoc.v:42144$1975_Y - connect \$387 $and$libresoc.v:42145$1976_Y - connect \$389 $and$libresoc.v:42146$1977_Y - connect \$391 $ternary$libresoc.v:42147$1978_Y - connect \$393 $and$libresoc.v:42148$1979_Y - connect \$395 $and$libresoc.v:42149$1980_Y - connect \$397 $not$libresoc.v:42150$1981_Y - connect \$399 $and$libresoc.v:42151$1982_Y - connect \$401 $and$libresoc.v:42152$1983_Y - connect \$403 $ternary$libresoc.v:42153$1984_Y - connect \$405 $and$libresoc.v:42154$1985_Y - connect \$407 $and$libresoc.v:42155$1986_Y - connect \$409 $not$libresoc.v:42156$1987_Y - connect \$411 $and$libresoc.v:42157$1988_Y - connect \$413 $and$libresoc.v:42158$1989_Y - connect \$415 $ternary$libresoc.v:42159$1990_Y - connect \$417 $and$libresoc.v:42160$1991_Y - connect \$419 $and$libresoc.v:42161$1992_Y - connect \$421 $not$libresoc.v:42162$1993_Y - connect \$423 $and$libresoc.v:42163$1994_Y - connect \$425 $and$libresoc.v:42164$1995_Y - connect \$427 $ternary$libresoc.v:42165$1996_Y - connect \$429 $and$libresoc.v:42166$1997_Y - connect \$431 $and$libresoc.v:42167$1998_Y - connect \$433 $not$libresoc.v:42168$1999_Y - connect \$435 $and$libresoc.v:42169$2000_Y - connect \$437 $and$libresoc.v:42170$2001_Y - connect \$439 $ternary$libresoc.v:42171$2002_Y - connect \$441 $and$libresoc.v:42172$2003_Y - connect \$443 $and$libresoc.v:42173$2004_Y - connect \$445 $not$libresoc.v:42174$2005_Y - connect \$447 $and$libresoc.v:42175$2006_Y - connect \$449 $and$libresoc.v:42176$2007_Y - connect \$451 $ternary$libresoc.v:42177$2008_Y - connect \$453 $or$libresoc.v:42178$2009_Y - connect \$455 $or$libresoc.v:42179$2010_Y - connect \$457 $or$libresoc.v:42180$2011_Y - connect \$459 $or$libresoc.v:42181$2012_Y - connect \$461 $or$libresoc.v:42182$2013_Y - connect \$463 $or$libresoc.v:42183$2014_Y - connect \$465 $or$libresoc.v:42184$2015_Y - connect \$467 $or$libresoc.v:42185$2016_Y - connect \$469 $reduce_or$libresoc.v:42186$2017_Y - connect \$471 $and$libresoc.v:42187$2018_Y - connect \$473 $and$libresoc.v:42188$2019_Y - connect \$475 $not$libresoc.v:42189$2020_Y - connect \$477 $and$libresoc.v:42190$2021_Y - connect \$479 $and$libresoc.v:42191$2022_Y - connect \$481 $ternary$libresoc.v:42192$2023_Y - connect \$483 $and$libresoc.v:42193$2024_Y - connect \$485 $and$libresoc.v:42194$2025_Y - connect \$487 $not$libresoc.v:42195$2026_Y - connect \$489 $and$libresoc.v:42196$2027_Y - connect \$491 $and$libresoc.v:42197$2028_Y - connect \$493 $ternary$libresoc.v:42198$2029_Y - connect \$495 $and$libresoc.v:42199$2030_Y - connect \$497 $and$libresoc.v:42200$2031_Y - connect \$499 $not$libresoc.v:42201$2032_Y - connect \$501 $and$libresoc.v:42202$2033_Y - connect \$503 $and$libresoc.v:42203$2034_Y - connect \$505 $ternary$libresoc.v:42204$2035_Y - connect \$507 $and$libresoc.v:42205$2036_Y - connect \$509 $and$libresoc.v:42206$2037_Y - connect \$511 $not$libresoc.v:42207$2038_Y - connect \$513 $and$libresoc.v:42208$2039_Y - connect \$515 $and$libresoc.v:42209$2040_Y - connect \$517 $ternary$libresoc.v:42210$2041_Y - connect \$519 $and$libresoc.v:42211$2042_Y - connect \$521 $and$libresoc.v:42212$2043_Y - connect \$523 $not$libresoc.v:42213$2044_Y - connect \$525 $and$libresoc.v:42214$2045_Y - connect \$527 $and$libresoc.v:42215$2046_Y - connect \$529 $ternary$libresoc.v:42216$2047_Y - connect \$531 $and$libresoc.v:42217$2048_Y - connect \$533 $and$libresoc.v:42218$2049_Y - connect \$535 $not$libresoc.v:42219$2050_Y - connect \$537 $and$libresoc.v:42220$2051_Y - connect \$539 $and$libresoc.v:42221$2052_Y - connect \$541 $ternary$libresoc.v:42222$2053_Y - connect \$543 $and$libresoc.v:42223$2054_Y - connect \$545 $and$libresoc.v:42224$2055_Y - connect \$547 $not$libresoc.v:42225$2056_Y - connect \$549 $and$libresoc.v:42226$2057_Y - connect \$551 $and$libresoc.v:42227$2058_Y - connect \$553 $ternary$libresoc.v:42228$2059_Y - connect \$555 $and$libresoc.v:42229$2060_Y - connect \$557 $and$libresoc.v:42230$2061_Y - connect \$559 $not$libresoc.v:42231$2062_Y - connect \$561 $and$libresoc.v:42232$2063_Y - connect \$563 $and$libresoc.v:42233$2064_Y - connect \$565 $ternary$libresoc.v:42234$2065_Y - connect \$567 $or$libresoc.v:42235$2066_Y - connect \$569 $or$libresoc.v:42236$2067_Y - connect \$571 $or$libresoc.v:42237$2068_Y - connect \$573 $or$libresoc.v:42238$2069_Y - connect \$575 $or$libresoc.v:42239$2070_Y - connect \$577 $or$libresoc.v:42240$2071_Y - connect \$579 $or$libresoc.v:42241$2072_Y - connect \$581 $reduce_or$libresoc.v:42242$2073_Y - connect \$583 $and$libresoc.v:42243$2074_Y - connect \$585 $and$libresoc.v:42244$2075_Y - connect \$587 $not$libresoc.v:42245$2076_Y - connect \$589 $and$libresoc.v:42246$2077_Y - connect \$591 $and$libresoc.v:42247$2078_Y - connect \$593 $ternary$libresoc.v:42248$2079_Y - connect \$595 $and$libresoc.v:42249$2080_Y - connect \$597 $and$libresoc.v:42250$2081_Y - connect \$599 $not$libresoc.v:42251$2082_Y - connect \$601 $and$libresoc.v:42252$2083_Y - connect \$603 $and$libresoc.v:42253$2084_Y - connect \$605 $ternary$libresoc.v:42254$2085_Y - connect \$607 $or$libresoc.v:42255$2086_Y - connect \$609 $reduce_or$libresoc.v:42256$2087_Y - connect \$611 $and$libresoc.v:42257$2088_Y - connect \$613 $and$libresoc.v:42258$2089_Y - connect \$615 $eq$libresoc.v:42259$2090_Y - connect \$617 $or$libresoc.v:42260$2091_Y - connect \$619 $and$libresoc.v:42261$2092_Y - connect \$621 $or$libresoc.v:42262$2093_Y - connect \$623 $and$libresoc.v:42263$2094_Y - connect \$625 $and$libresoc.v:42264$2095_Y - connect \$627 $not$libresoc.v:42265$2096_Y - connect \$629 $and$libresoc.v:42266$2097_Y - connect \$631 $and$libresoc.v:42267$2098_Y - connect \$633 $ternary$libresoc.v:42268$2099_Y - connect \$635 $and$libresoc.v:42269$2100_Y - connect \$637 $and$libresoc.v:42270$2101_Y - connect \$639 $not$libresoc.v:42271$2102_Y - connect \$641 $and$libresoc.v:42272$2103_Y - connect \$643 $and$libresoc.v:42273$2104_Y - connect \$645 $ternary$libresoc.v:42274$2105_Y - connect \$647 $and$libresoc.v:42275$2106_Y - connect \$649 $and$libresoc.v:42276$2107_Y - connect \$651 $not$libresoc.v:42277$2108_Y - connect \$653 $and$libresoc.v:42278$2109_Y - connect \$655 $and$libresoc.v:42279$2110_Y - connect \$657 $ternary$libresoc.v:42280$2111_Y - connect \$659 $and$libresoc.v:42281$2112_Y - connect \$661 $and$libresoc.v:42282$2113_Y - connect \$663 $not$libresoc.v:42283$2114_Y - connect \$665 $and$libresoc.v:42284$2115_Y - connect \$667 $and$libresoc.v:42285$2116_Y - connect \$669 $ternary$libresoc.v:42286$2117_Y - connect \$671 $and$libresoc.v:42287$2118_Y - connect \$673 $and$libresoc.v:42288$2119_Y - connect \$675 $not$libresoc.v:42289$2120_Y - connect \$677 $and$libresoc.v:42290$2121_Y - connect \$679 $and$libresoc.v:42291$2122_Y - connect \$681 $ternary$libresoc.v:42292$2123_Y - connect \$683 $and$libresoc.v:42293$2124_Y - connect \$685 $and$libresoc.v:42294$2125_Y - connect \$687 $not$libresoc.v:42295$2126_Y - connect \$689 $and$libresoc.v:42296$2127_Y - connect \$691 $and$libresoc.v:42297$2128_Y - connect \$693 $ternary$libresoc.v:42298$2129_Y - connect \$696 $or$libresoc.v:42299$2130_Y - connect \$698 $or$libresoc.v:42300$2131_Y - connect \$700 $or$libresoc.v:42301$2132_Y - connect \$702 $or$libresoc.v:42302$2133_Y - connect \$704 $or$libresoc.v:42303$2134_Y - connect \$695 $pos$libresoc.v:42304$2136_Y - connect \$707 $eq$libresoc.v:42305$2137_Y - connect \$709 $and$libresoc.v:42306$2138_Y - connect \$711 $eq$libresoc.v:42307$2139_Y - connect \$713 $or$libresoc.v:42308$2140_Y - connect \$715 $and$libresoc.v:42309$2141_Y - connect \$717 $and$libresoc.v:42310$2142_Y - connect \$719 $not$libresoc.v:42311$2143_Y - connect \$721 $and$libresoc.v:42312$2144_Y - connect \$723 $and$libresoc.v:42313$2145_Y - connect \$725 $ternary$libresoc.v:42314$2146_Y - connect \$727 $and$libresoc.v:42315$2147_Y - connect \$729 $and$libresoc.v:42316$2148_Y - connect \$731 $not$libresoc.v:42317$2149_Y - connect \$733 $and$libresoc.v:42318$2150_Y - connect \$735 $and$libresoc.v:42319$2151_Y - connect \$737 $ternary$libresoc.v:42320$2152_Y - connect \$739 $and$libresoc.v:42321$2153_Y - connect \$741 $and$libresoc.v:42322$2154_Y - connect \$743 $not$libresoc.v:42323$2155_Y - connect \$745 $and$libresoc.v:42324$2156_Y - connect \$747 $and$libresoc.v:42325$2157_Y - connect \$749 $ternary$libresoc.v:42326$2158_Y - connect \$752 $or$libresoc.v:42327$2159_Y - connect \$754 $or$libresoc.v:42328$2160_Y - connect \$751 $pos$libresoc.v:42329$2162_Y - connect \$757 $and$libresoc.v:42330$2163_Y - connect \$759 $and$libresoc.v:42331$2164_Y - connect \$761 $eq$libresoc.v:42332$2165_Y - connect \$763 $or$libresoc.v:42333$2166_Y - connect \$765 $and$libresoc.v:42334$2167_Y - connect \$767 $and$libresoc.v:42335$2168_Y - connect \$769 $not$libresoc.v:42336$2169_Y - connect \$771 $and$libresoc.v:42337$2170_Y - connect \$773 $and$libresoc.v:42338$2171_Y - connect \$775 $ternary$libresoc.v:42339$2172_Y - connect \$777 $and$libresoc.v:42340$2173_Y - connect \$779 $and$libresoc.v:42341$2174_Y - connect \$781 $not$libresoc.v:42342$2175_Y - connect \$783 $and$libresoc.v:42343$2176_Y - connect \$785 $and$libresoc.v:42344$2177_Y - connect \$787 $ternary$libresoc.v:42345$2178_Y - connect \$789 $and$libresoc.v:42346$2179_Y - connect \$791 $and$libresoc.v:42347$2180_Y - connect \$793 $not$libresoc.v:42348$2181_Y - connect \$795 $and$libresoc.v:42349$2182_Y - connect \$797 $and$libresoc.v:42350$2183_Y - connect \$799 $sub$libresoc.v:42351$2184_Y - connect \$801 $sshl$libresoc.v:42352$2185_Y - connect \$803 $ternary$libresoc.v:42353$2186_Y - connect \$805 $and$libresoc.v:42354$2187_Y - connect \$807 $and$libresoc.v:42355$2188_Y - connect \$809 $not$libresoc.v:42356$2189_Y - connect \$811 $and$libresoc.v:42357$2190_Y - connect \$813 $and$libresoc.v:42358$2191_Y - connect \$815 $sub$libresoc.v:42359$2192_Y - connect \$817 $sshl$libresoc.v:42360$2193_Y - connect \$819 $ternary$libresoc.v:42361$2194_Y - connect \$822 $or$libresoc.v:42362$2195_Y - connect \$824 $and$libresoc.v:42363$2196_Y - connect \$826 $and$libresoc.v:42364$2197_Y - connect \$828 $not$libresoc.v:42365$2198_Y - connect \$830 $and$libresoc.v:42366$2199_Y - connect \$832 $and$libresoc.v:42367$2200_Y - connect \$834 $sub$libresoc.v:42368$2201_Y - connect \$836 $sshl$libresoc.v:42369$2202_Y - connect \$838 $ternary$libresoc.v:42370$2203_Y - connect \$840 $and$libresoc.v:42371$2204_Y - connect \$842 $and$libresoc.v:42372$2205_Y - connect \$844 $not$libresoc.v:42373$2206_Y - connect \$846 $and$libresoc.v:42374$2207_Y - connect \$848 $and$libresoc.v:42375$2208_Y - connect \$850 $sub$libresoc.v:42376$2209_Y - connect \$852 $sshl$libresoc.v:42377$2210_Y - connect \$854 $ternary$libresoc.v:42378$2211_Y - connect \$856 $and$libresoc.v:42379$2212_Y - connect \$858 $and$libresoc.v:42380$2213_Y - connect \$860 $not$libresoc.v:42381$2214_Y - connect \$862 $and$libresoc.v:42382$2215_Y - connect \$864 $and$libresoc.v:42383$2216_Y - connect \$866 $ternary$libresoc.v:42384$2217_Y - connect \$868 $and$libresoc.v:42385$2218_Y - connect \$870 $and$libresoc.v:42386$2219_Y - connect \$872 $not$libresoc.v:42387$2220_Y - connect \$874 $and$libresoc.v:42388$2221_Y - connect \$876 $and$libresoc.v:42389$2222_Y - connect \$878 $ternary$libresoc.v:42390$2223_Y - connect \$880 $and$libresoc.v:42391$2224_Y - connect \$882 $and$libresoc.v:42392$2225_Y - connect \$884 $not$libresoc.v:42393$2226_Y - connect \$886 $and$libresoc.v:42394$2227_Y - connect \$888 $and$libresoc.v:42395$2228_Y - connect \$890 $ternary$libresoc.v:42396$2229_Y - connect \$892 $or$libresoc.v:42397$2230_Y - connect \$894 $or$libresoc.v:42398$2231_Y - connect \$896 $reduce_or$libresoc.v:42399$2232_Y - connect \$898 $and$libresoc.v:42400$2233_Y - connect \$900 $and$libresoc.v:42401$2234_Y - connect \$902 $not$libresoc.v:42402$2235_Y - connect \$904 $and$libresoc.v:42403$2236_Y - connect \$906 $and$libresoc.v:42404$2237_Y - connect \$908 $ternary$libresoc.v:42405$2238_Y - connect \$910 $and$libresoc.v:42406$2239_Y - connect \$912 $and$libresoc.v:42407$2240_Y - connect \$914 $not$libresoc.v:42408$2241_Y - connect \$916 $and$libresoc.v:42409$2242_Y - connect \$918 $and$libresoc.v:42410$2243_Y - connect \$920 $ternary$libresoc.v:42411$2244_Y - connect \$922 $or$libresoc.v:42412$2245_Y - connect \$924 $reduce_or$libresoc.v:42413$2246_Y - connect \$926 $and$libresoc.v:42414$2247_Y - connect \$928 $and$libresoc.v:42415$2248_Y - connect \$930 $not$libresoc.v:42416$2249_Y - connect \$932 $and$libresoc.v:42417$2250_Y - connect \$934 $and$libresoc.v:42418$2251_Y - connect \$936 $ternary$libresoc.v:42419$2252_Y - connect \$938 $reduce_or$libresoc.v:42420$2253_Y - connect \$940 $and$libresoc.v:42421$2254_Y - connect \$942 $and$libresoc.v:42422$2255_Y - connect \$944 $and$libresoc.v:42423$2256_Y - connect \$946 $and$libresoc.v:42424$2257_Y - connect \$948 $and$libresoc.v:42425$2258_Y - connect \$950 $and$libresoc.v:42426$2259_Y - connect \$952 $and$libresoc.v:42427$2260_Y - connect \$954 $and$libresoc.v:42428$2261_Y - connect \$956 $and$libresoc.v:42429$2262_Y - connect \$958 $and$libresoc.v:42430$2263_Y - connect \$960 $and$libresoc.v:42431$2264_Y - connect \$962 $and$libresoc.v:42432$2265_Y - connect \$964 $not$libresoc.v:42433$2266_Y - connect \$966 $and$libresoc.v:42434$2267_Y - connect \$972 $and$libresoc.v:42435$2268_Y - connect \$974 $ternary$libresoc.v:42436$2269_Y - connect \$976 $and$libresoc.v:42437$2270_Y - connect \$979 $and$libresoc.v:42438$2271_Y - connect \$983 $not$libresoc.v:42439$2272_Y - connect \$985 $and$libresoc.v:42440$2273_Y - connect \$990 $and$libresoc.v:42441$2274_Y - connect \$993 $ternary$libresoc.v:42442$2275_Y - connect \$995 $and$libresoc.v:42443$2276_Y - connect \$998 $and$libresoc.v:42444$2277_Y - connect \$216 \$217 - connect \$821 \$822 - connect \$1149 \$1166 - connect \$1364 \$1373 - connect \o_ok 1'0 - connect \ea_ok 1'0 - connect \spr_spr1__wen \wp$1802 - connect \spr_spr1__addr$173 \addr_en$1805 [6:0] - connect \spr_spr1__data_i \fus_dest2_o$160 - connect \addr_en$1805 \$1806 - connect \wp$1802 \$1803 - connect \wr_pick_rise$1049 \$1800 - connect \wr_pick$1794 \$1795 - connect \wrpick_SPR_spr1_i \$1792 - connect \wrflag_spr0_spr1_1 \$1790 - connect \state_wen \$1788 - connect \state_data_i$172 \fus_dest5_o$159 - connect \addr_en$1785 \$1786 - connect \wp$1782 \$1783 - connect \wr_pick_rise$1009 \$1780 - connect \wr_pick$1774 \$1775 - connect \wrpick_STATE_msr_i \$1772 - connect \wrflag_trap0_msr_4 \$1770 - connect \state_nia_wen \$1766 - connect \state_data_i \$1764 - connect \addr_en$1761 \$1762 - connect \wp$1758 \$1759 - connect \wr_pick_rise$1008 \$1756 - connect \wr_pick$1750 \$1751 - connect \wrflag_trap0_nia_3 \$1748 - connect \addr_en$1745 \$1746 - connect \wp$1742 \$1743 - connect \wr_pick_rise$1633 \$1740 - connect \wr_pick$1734 \$1735 - connect \wrpick_STATE_nia_i [1] \$1732 - connect \wrpick_STATE_nia_i [0] \$1730 - connect \wrflag_branch0_nia_2 \$1728 - connect \fast_dest1__wen \$1726 - connect \fast_dest1__addr \$1718 - connect \fast_dest1__data_i \$1710 - connect \addr_en$1701 \$1702 - connect \wp$1698 \$1699 - connect \wr_pick_rise$1007 \$1696 - connect \wr_pick$1690 \$1691 - connect \wrflag_trap0_fast1_2 \$1688 - connect \addr_en$1685 \$1686 - connect \wp$1682 \$1683 - connect \wr_pick_rise$1632 \$1680 - connect \wr_pick$1674 \$1675 - connect \wrflag_branch0_fast1_1 \$1672 - connect \addr_en$1669 \$1670 - connect \wp$1666 \$1667 - connect \wr_pick_rise$1048 \$1664 - connect \wr_pick$1658 \$1659 - connect \wrflag_spr0_fast1_2 \$1656 - connect \addr_en$1653 \$1654 - connect \wp$1650 \$1651 - connect \wr_pick_rise$1006 \$1648 - connect \wr_pick$1642 \$1643 - connect \wrflag_trap0_fast1_1 \$1640 - connect \addr_en$1637 \$1638 - connect \wp$1634 \$1635 - connect \fus_cu_wr__go_i$147 [2] \wr_pick_rise$1633 - connect \fus_cu_wr__go_i$147 [1] \wr_pick_rise$1632 - connect \fus_cu_wr__go_i$147 [0] \wr_pick_rise$1627 - connect \wr_pick_rise$1627 \$1630 - connect \wr_pick$1623 \$1624 - connect \wrpick_FAST_fast1_i [4] \$1621 - connect \wrpick_FAST_fast1_i [3] \$1619 - connect \wrpick_FAST_fast1_i [2] \$1617 - connect \wrpick_FAST_fast1_i [1] \$1615 - connect \wrpick_FAST_fast1_i [0] \$1613 - connect \wrflag_branch0_fast1_0 \$1611 - connect \xer_wen$171 \$1603 - connect \xer_data_i$170 \$1595 - connect \addr_en$1592 \$1593 - connect \wp$1589 \$1590 - connect \wr_pick_rise$1089 \$1587 - connect \wr_pick$1581 \$1582 - connect \wrflag_mul0_xer_so_3 \$1579 - connect \addr_en$1576 \$1577 - connect \wp$1573 \$1574 - connect \wr_pick_rise$1069 \$1571 - connect \wr_pick$1565 \$1566 - connect \wrflag_div0_xer_so_3 \$1563 - connect \addr_en$1560 \$1561 - connect \wp$1557 \$1558 - connect \wr_pick_rise$1047 \$1555 - connect \wr_pick$1549 \$1550 - connect \wrflag_spr0_xer_so_3 \$1547 - connect \addr_en$1544 \$1545 - connect \wp$1541 \$1542 - connect \wr_pick_rise$971 \$1539 - connect \wr_pick$1533 \$1534 - connect \wrpick_XER_xer_so_i [3] \$1531 - connect \wrpick_XER_xer_so_i [2] \$1529 - connect \wrpick_XER_xer_so_i [1] \$1527 - connect \wrpick_XER_xer_so_i [0] \$1525 - connect \wrflag_alu0_xer_so_4 \$1523 - connect \xer_wen$169 \$1521 - connect \xer_data_i$168 \$1515 - connect \addr_en$1508 \$1509 - connect \wp$1505 \$1506 - connect \wr_pick_rise$1088 \$1503 - connect \wr_pick$1497 \$1498 - connect \wrflag_mul0_xer_ov_2 \$1495 - connect \addr_en$1492 \$1493 - connect \wp$1489 \$1490 - connect \wr_pick_rise$1068 \$1487 - connect \wr_pick$1481 \$1482 - connect \wrflag_div0_xer_ov_2 \$1479 - connect \addr_en$1476 \$1477 - connect \wp$1473 \$1474 - connect \wr_pick_rise$1046 \$1471 - connect \wr_pick$1465 \$1466 - connect \wrflag_spr0_xer_ov_4 \$1463 - connect \addr_en$1460 \$1461 - connect \wp$1457 \$1458 - connect \wr_pick_rise$970 \$1455 - connect \wr_pick$1449 \$1450 - connect \wrpick_XER_xer_ov_i [3] \$1447 - connect \wrpick_XER_xer_ov_i [2] \$1445 - connect \wrpick_XER_xer_ov_i [1] \$1443 - connect \wrpick_XER_xer_ov_i [0] \$1441 - connect \wrflag_alu0_xer_ov_3 \$1439 - connect \xer_wen \$1433 - connect \xer_data_i \$1431 - connect \addr_en$1426 \$1427 - connect \wp$1423 \$1424 - connect \wr_pick_rise$1108 \$1421 - connect \wr_pick$1415 \$1416 - connect \wrflag_shiftrot0_xer_ca_2 \$1413 - connect \addr_en$1410 \$1411 - connect \wp$1407 \$1408 - connect \wr_pick_rise$1045 \$1405 - connect \wr_pick$1399 \$1400 - connect \wrflag_spr0_xer_ca_5 \$1397 - connect \addr_en$1394 \$1395 - connect \wp$1391 \$1392 - connect \wr_pick_rise$969 \$1389 - connect \wr_pick$1383 \$1384 - connect \wrpick_XER_xer_ca_i [2] \$1381 - connect \wrpick_XER_xer_ca_i [1] \$1379 - connect \wrpick_XER_xer_ca_i [0] \$1377 - connect \wrflag_alu0_xer_ca_2 \$1375 - connect \cr_wen \$1373 [7:0] - connect \cr_data_i \$1362 - connect \addr_en$1347 \$1352 - connect \wp$1344 \$1345 - connect \wr_pick_rise$1107 \$1342 - connect \wr_pick$1336 \$1337 - connect \wrflag_shiftrot0_cr_a_1 \$1334 - connect \addr_en$1327 \$1332 - connect \wp$1324 \$1325 - connect \wr_pick_rise$1087 \$1322 - connect \wr_pick$1316 \$1317 - connect \wrflag_mul0_cr_a_1 \$1314 - connect \addr_en$1307 \$1312 - connect \wp$1304 \$1305 - connect \wr_pick_rise$1067 \$1302 - connect \wr_pick$1296 \$1297 - connect \wrflag_div0_cr_a_1 \$1294 - connect \addr_en$1287 \$1292 - connect \wp$1284 \$1285 - connect \wr_pick_rise$1027 \$1282 - connect \wr_pick$1276 \$1277 - connect \wrflag_logical0_cr_a_1 \$1274 - connect \addr_en$1267 \$1272 - connect \wp$1264 \$1265 - connect \wr_pick_rise$988 \$1262 - connect \wr_pick$1256 \$1257 - connect \wrflag_cr0_cr_a_2 \$1254 - connect \addr_en$1247 \$1252 - connect \wp$1244 \$1245 - connect \wr_pick_rise$968 \$1242 - connect \wr_pick$1236 \$1237 - connect \wrpick_CR_cr_a_i [5] \$1234 - connect \wrpick_CR_cr_a_i [4] \$1232 - connect \wrpick_CR_cr_a_i [3] \$1230 - connect \wrpick_CR_cr_a_i [2] \$1228 - connect \wrpick_CR_cr_a_i [1] \$1226 - connect \wrpick_CR_cr_a_i [0] \$1224 - connect \wrflag_alu0_cr_a_1 \$1222 - connect \cr_full_wr__wen \addr_en$1219 - connect \cr_full_wr__data_i \fus_dest2_o - connect \addr_en$1219 \$1220 - connect \wp$1216 \$1217 - connect \wr_pick_rise$987 \$1214 - connect \wr_pick$1208 \$1209 - connect \wrpick_CR_full_cr_i \$1206 - connect \wrflag_cr0_full_cr_1 \$1204 - connect \int_dest1__wen \$1202 - connect \int_dest1__addr \$1184 - connect \int_dest1__data_i \$1166 [63:0] - connect \addr_en$1146 \$1147 - connect \wp$1143 \$1144 - connect \wr_pick_rise$1126 \$1141 - connect \wr_pick$1135 \$1136 - connect \wrflag_ldst0_o_1 \$1133 - connect \addr_en$1130 \$1131 - connect \wp$1127 \$1128 - connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1126 - connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1121 - connect \wr_pick_rise$1121 \$1124 - connect \wr_pick$1117 \$1118 - connect \wrflag_ldst0_o_0 \$1115 - connect \addr_en$1112 \$1113 - connect \wp$1109 \$1110 - connect \fus_cu_wr__go_i$110 [2] \wr_pick_rise$1108 - connect \fus_cu_wr__go_i$110 [1] \wr_pick_rise$1107 - connect \fus_cu_wr__go_i$110 [0] \wr_pick_rise$1102 - connect \wr_pick_rise$1102 \$1105 - connect \wr_pick$1098 \$1099 - connect \wrflag_shiftrot0_o_0 \$1096 - connect \addr_en$1093 \$1094 - connect \wp$1090 \$1091 - connect \fus_cu_wr__go_i$107 [3] \wr_pick_rise$1089 - connect \fus_cu_wr__go_i$107 [2] \wr_pick_rise$1088 - connect \fus_cu_wr__go_i$107 [1] \wr_pick_rise$1087 - connect \fus_cu_wr__go_i$107 [0] \wr_pick_rise$1082 - connect \wr_pick_rise$1082 \$1085 - connect \wr_pick$1078 \$1079 - connect \wrflag_mul0_o_0 \$1076 - connect \addr_en$1073 \$1074 - connect \wp$1070 \$1071 - connect \fus_cu_wr__go_i$104 [3] \wr_pick_rise$1069 - connect \fus_cu_wr__go_i$104 [2] \wr_pick_rise$1068 - connect \fus_cu_wr__go_i$104 [1] \wr_pick_rise$1067 - connect \fus_cu_wr__go_i$104 [0] \wr_pick_rise$1062 - connect \wr_pick_rise$1062 \$1065 - connect \wr_pick$1058 \$1059 - connect \wrflag_div0_o_0 \$1056 - connect \addr_en$1053 \$1054 - connect \wp$1050 \$1051 - connect \fus_cu_wr__go_i$101 [1] \wr_pick_rise$1049 - connect \fus_cu_wr__go_i$101 [2] \wr_pick_rise$1048 - connect \fus_cu_wr__go_i$101 [3] \wr_pick_rise$1047 - connect \fus_cu_wr__go_i$101 [4] \wr_pick_rise$1046 - connect \fus_cu_wr__go_i$101 [5] \wr_pick_rise$1045 - connect \fus_cu_wr__go_i$101 [0] \wr_pick_rise$1040 - connect \wr_pick_rise$1040 \$1043 - connect \wr_pick$1036 \$1037 - connect \wrflag_spr0_o_0 \$1034 - connect \addr_en$1031 \$1032 - connect \wp$1028 \$1029 - connect \fus_cu_wr__go_i$98 [1] \wr_pick_rise$1027 - connect \fus_cu_wr__go_i$98 [0] \wr_pick_rise$1022 - connect \wr_pick_rise$1022 \$1025 - connect \wr_pick$1018 \$1019 - connect \wrflag_logical0_o_0 \$1016 - connect \addr_en$1013 \$1014 - connect \wp$1010 \$1011 - connect \fus_cu_wr__go_i$95 [4] \wr_pick_rise$1009 - connect \fus_cu_wr__go_i$95 [3] \wr_pick_rise$1008 - connect \fus_cu_wr__go_i$95 [2] \wr_pick_rise$1007 - connect \fus_cu_wr__go_i$95 [1] \wr_pick_rise$1006 - connect \fus_cu_wr__go_i$95 [0] \wr_pick_rise$1001 - connect \wr_pick_rise$1001 \$1004 - connect \wr_pick$997 \$998 - connect \wrflag_trap0_o_0 \$995 - connect \addr_en$992 \$993 - connect \wp$989 \$990 - connect \fus_cu_wr__go_i$92 [2] \wr_pick_rise$988 - connect \fus_cu_wr__go_i$92 [1] \wr_pick_rise$987 - connect \fus_cu_wr__go_i$92 [0] \wr_pick_rise$982 - connect \wr_pick_rise$982 \$985 - connect \wr_pick$978 \$979 - connect \wrflag_cr0_o_0 \$976 - connect \addr_en \$974 - connect \wp \$972 - connect \fus_cu_wr__go_i [4] \wr_pick_rise$971 - connect \fus_cu_wr__go_i [3] \wr_pick_rise$970 - connect \fus_cu_wr__go_i [2] \wr_pick_rise$969 - connect \fus_cu_wr__go_i [1] \wr_pick_rise$968 - connect \fus_cu_wr__go_i [0] \wr_pick_rise - connect \wr_pick_rise \$966 - connect \wr_pick \$962 - connect \wrpick_INT_o_i [9] \$960 - connect \wrpick_INT_o_i [8] \$958 - connect \wrpick_INT_o_i [7] \$956 - connect \wrpick_INT_o_i [6] \$954 - connect \wrpick_INT_o_i [5] \$952 - connect \wrpick_INT_o_i [4] \$950 - connect \wrpick_INT_o_i [3] \$948 - connect \wrpick_INT_o_i [2] \$946 - connect \wrpick_INT_o_i [1] \$944 - connect \wrpick_INT_o_i [0] \$942 - connect \wrflag_alu0_o_0 \$940 - connect \spr_spr1__ren \$938 - connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] - connect \addr_en_SPR_spr1_spr0_0 \$936 - connect \rp_SPR_spr1_spr0_0 \$934 - connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 - connect \pick_SPR_spr1_spr0_0 \$932 - connect \rdflag_SPR_spr1_0 \core_spr1_ok - connect \fast_src2__ren \$924 - connect \fast_src2__addr \$922 - connect \addr_en_FAST_fast2_trap0_1 \$920 - connect \rp_FAST_fast2_trap0_1 \$918 - connect \pick_FAST_fast2_trap0_1 \$916 - connect \addr_en_FAST_fast2_branch0_0 \$908 - connect \rp_FAST_fast2_branch0_0 \$906 - connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 - connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 - connect \pick_FAST_fast2_branch0_0 \$904 - connect \rdflag_FAST_fast2_0 \core_fast2_ok - connect \fast_src1__ren \$896 - connect \fast_src1__addr \$894 - connect \addr_en_FAST_fast1_spr0_2 \$890 - connect \rp_FAST_fast1_spr0_2 \$888 - connect \pick_FAST_fast1_spr0_2 \$886 - connect \addr_en_FAST_fast1_trap0_1 \$878 - connect \rp_FAST_fast1_trap0_1 \$876 - connect \pick_FAST_fast1_trap0_1 \$874 - connect \addr_en_FAST_fast1_branch0_0 \$866 - connect \rp_FAST_fast1_branch0_0 \$864 - connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 - connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 - connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 - connect \pick_FAST_fast1_branch0_0 \$862 - connect \rdflag_FAST_fast1_0 \core_fast1_ok - connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - connect \addr_en_CR_cr_c_cr0_0 \$854 - connect \rp_CR_cr_c_cr0_0 \$848 - connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 - connect \pick_CR_cr_c_cr0_0 \$846 - connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 - connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - connect \addr_en_CR_cr_b_cr0_0 \$838 - connect \rp_CR_cr_b_cr0_0 \$832 - connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 - connect \pick_CR_cr_b_cr0_0 \$830 - connect \rdflag_CR_cr_b_0 \core_cr_in2_ok - connect \cr_src1__ren \$822 [7:0] - connect \addr_en_CR_cr_a_branch0_1 \$819 - connect \rp_CR_cr_a_branch0_1 \$813 - connect \fus_cu_rd__go_i$80 [1] \dp_FAST_fast2_branch0_0 - connect \fus_cu_rd__go_i$80 [0] \dp_FAST_fast1_branch0_0 - connect \fus_cu_rd__go_i$80 [2] \dp_CR_cr_a_branch0_1 - connect \pick_CR_cr_a_branch0_1 \$811 - connect \addr_en_CR_cr_a_cr0_0 \$803 - connect \rp_CR_cr_a_cr0_0 \$797 - connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 - connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 - connect \pick_CR_cr_a_cr0_0 \$795 - connect \rdflag_CR_cr_a_0 \core_cr_in1_ok - connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 - connect \addr_en_CR_full_cr_cr0_0 \$787 - connect \rp_CR_full_cr_cr0_0 \$785 - connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 - connect \pick_CR_full_cr_cr0_0 \$783 - connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok - connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 - connect \addr_en_XER_xer_ov_spr0_0 \$775 - connect \rp_XER_xer_ov_spr0_0 \$773 - connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 - connect \pick_XER_xer_ov_spr0_0 \$771 - connect \rdflag_XER_xer_ov_0 \$763 - connect \xer_src2__ren \$751 - connect \addr_en_XER_xer_ca_shiftrot0_2 \$749 - connect \rp_XER_xer_ca_shiftrot0_2 \$747 - connect \pick_XER_xer_ca_shiftrot0_2 \$745 - connect \addr_en_XER_xer_ca_spr0_1 \$737 - connect \rp_XER_xer_ca_spr0_1 \$735 - connect \pick_XER_xer_ca_spr0_1 \$733 - connect \addr_en_XER_xer_ca_alu0_0 \$725 - connect \rp_XER_xer_ca_alu0_0 \$723 - connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 - connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 - connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 - connect \pick_XER_xer_ca_alu0_0 \$721 - connect \rdflag_XER_xer_ca_0 \$713 - connect \xer_src1__ren \$695 - connect \addr_en_XER_xer_so_shiftrot0_5 \$693 - connect \rp_XER_xer_so_shiftrot0_5 \$691 - connect \pick_XER_xer_so_shiftrot0_5 \$689 - connect \addr_en_XER_xer_so_mul0_4 \$681 - connect \rp_XER_xer_so_mul0_4 \$679 - connect \pick_XER_xer_so_mul0_4 \$677 - connect \addr_en_XER_xer_so_div0_3 \$669 - connect \rp_XER_xer_so_div0_3 \$667 - connect \pick_XER_xer_so_div0_3 \$665 - connect \addr_en_XER_xer_so_spr0_2 \$657 - connect \rp_XER_xer_so_spr0_2 \$655 - connect \pick_XER_xer_so_spr0_2 \$653 - connect \addr_en_XER_xer_so_logical0_1 \$645 - connect \rp_XER_xer_so_logical0_1 \$643 - connect \pick_XER_xer_so_logical0_1 \$641 - connect \addr_en_XER_xer_so_alu0_0 \$633 - connect \rp_XER_xer_so_alu0_0 \$631 - connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 - connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 - connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 - connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 - connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 - connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - connect \pick_XER_xer_so_alu0_0 \$629 - connect \rdflag_XER_xer_so_0 \$621 - connect \int_src3__ren \$609 - connect \int_src3__addr \$607 - connect \addr_en_INT_rc_ldst0_1 \$605 - connect \rp_INT_rc_ldst0_1 \$603 - connect \pick_INT_rc_ldst0_1 \$601 - connect \addr_en_INT_rc_shiftrot0_0 \$593 - connect \rp_INT_rc_shiftrot0_0 \$591 - connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 - connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 - connect \pick_INT_rc_shiftrot0_0 \$589 - connect \rdflag_INT_rc_0 \core_reg3_ok - connect \int_src2__ren \$581 - connect \int_src2__addr \$579 - connect \addr_en_INT_rb_ldst0_7 \$565 - connect \rp_INT_rb_ldst0_7 \$563 - connect \pick_INT_rb_ldst0_7 \$561 - connect \addr_en_INT_rb_shiftrot0_6 \$553 - connect \rp_INT_rb_shiftrot0_6 \$551 - connect \pick_INT_rb_shiftrot0_6 \$549 - connect \addr_en_INT_rb_mul0_5 \$541 - connect \rp_INT_rb_mul0_5 \$539 - connect \pick_INT_rb_mul0_5 \$537 - connect \addr_en_INT_rb_div0_4 \$529 - connect \rp_INT_rb_div0_4 \$527 - connect \pick_INT_rb_div0_4 \$525 - connect \addr_en_INT_rb_logical0_3 \$517 - connect \rp_INT_rb_logical0_3 \$515 - connect \pick_INT_rb_logical0_3 \$513 - connect \addr_en_INT_rb_trap0_2 \$505 - connect \rp_INT_rb_trap0_2 \$503 - connect \pick_INT_rb_trap0_2 \$501 - connect \addr_en_INT_rb_cr0_1 \$493 - connect \rp_INT_rb_cr0_1 \$491 - connect \pick_INT_rb_cr0_1 \$489 - connect \addr_en_INT_rb_alu0_0 \$481 - connect \rp_INT_rb_alu0_0 \$479 - connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 - connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 - connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 - connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 - connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 - connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 - connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 - connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 - connect \pick_INT_rb_alu0_0 \$477 - connect \rdflag_INT_rb_0 \core_reg2_ok - connect \int_src1__ren \$469 - connect \int_src1__addr \$467 - connect \addr_en_INT_ra_ldst0_8 \$451 - connect \rp_INT_ra_ldst0_8 \$449 - connect \fus_cu_rd__go_i$60 [2] \dp_INT_rc_ldst0_1 - connect \fus_cu_rd__go_i$60 [1] \dp_INT_rb_ldst0_7 - connect \fus_cu_rd__go_i$60 [0] \dp_INT_ra_ldst0_8 - connect \pick_INT_ra_ldst0_8 \$447 - connect \addr_en_INT_ra_shiftrot0_7 \$439 - connect \rp_INT_ra_shiftrot0_7 \$437 - connect \fus_cu_rd__go_i$57 [4] \dp_XER_xer_ca_shiftrot0_2 - connect \fus_cu_rd__go_i$57 [3] \dp_XER_xer_so_shiftrot0_5 - connect \fus_cu_rd__go_i$57 [2] \dp_INT_rc_shiftrot0_0 - connect \fus_cu_rd__go_i$57 [1] \dp_INT_rb_shiftrot0_6 - connect \fus_cu_rd__go_i$57 [0] \dp_INT_ra_shiftrot0_7 - connect \pick_INT_ra_shiftrot0_7 \$435 - connect \addr_en_INT_ra_mul0_6 \$427 - connect \rp_INT_ra_mul0_6 \$425 - connect \fus_cu_rd__go_i$54 [2] \dp_XER_xer_so_mul0_4 - connect \fus_cu_rd__go_i$54 [1] \dp_INT_rb_mul0_5 - connect \fus_cu_rd__go_i$54 [0] \dp_INT_ra_mul0_6 - connect \pick_INT_ra_mul0_6 \$423 - connect \addr_en_INT_ra_div0_5 \$415 - connect \rp_INT_ra_div0_5 \$413 - connect \fus_cu_rd__go_i$51 [2] \dp_XER_xer_so_div0_3 - connect \fus_cu_rd__go_i$51 [1] \dp_INT_rb_div0_4 - connect \fus_cu_rd__go_i$51 [0] \dp_INT_ra_div0_5 - connect \pick_INT_ra_div0_5 \$411 - connect \addr_en_INT_ra_spr0_4 \$403 - connect \rp_INT_ra_spr0_4 \$401 - connect \fus_cu_rd__go_i$48 [1] \dp_SPR_spr1_spr0_0 - connect \fus_cu_rd__go_i$48 [2] \dp_FAST_fast1_spr0_2 - connect \fus_cu_rd__go_i$48 [4] \dp_XER_xer_ov_spr0_0 - connect \fus_cu_rd__go_i$48 [5] \dp_XER_xer_ca_spr0_1 - connect \fus_cu_rd__go_i$48 [3] \dp_XER_xer_so_spr0_2 - connect \fus_cu_rd__go_i$48 [0] \dp_INT_ra_spr0_4 - connect \pick_INT_ra_spr0_4 \$399 - connect \addr_en_INT_ra_logical0_3 \$391 - connect \rp_INT_ra_logical0_3 \$389 - connect \fus_cu_rd__go_i$45 [2] \dp_XER_xer_so_logical0_1 - connect \fus_cu_rd__go_i$45 [1] \dp_INT_rb_logical0_3 - connect \fus_cu_rd__go_i$45 [0] \dp_INT_ra_logical0_3 - connect \pick_INT_ra_logical0_3 \$387 - connect \addr_en_INT_ra_trap0_2 \$379 - connect \rp_INT_ra_trap0_2 \$377 - connect \fus_cu_rd__go_i$42 [3] \dp_FAST_fast2_trap0_1 - connect \fus_cu_rd__go_i$42 [2] \dp_FAST_fast1_trap0_1 - connect \fus_cu_rd__go_i$42 [1] \dp_INT_rb_trap0_2 - connect \fus_cu_rd__go_i$42 [0] \dp_INT_ra_trap0_2 - connect \pick_INT_ra_trap0_2 \$375 - connect \addr_en_INT_ra_cr0_1 \$367 - connect \rp_INT_ra_cr0_1 \$365 - connect \fus_cu_rd__go_i$39 [5] \dp_CR_cr_c_cr0_0 - connect \fus_cu_rd__go_i$39 [4] \dp_CR_cr_b_cr0_0 - connect \fus_cu_rd__go_i$39 [3] \dp_CR_cr_a_cr0_0 - connect \fus_cu_rd__go_i$39 [2] \dp_CR_full_cr_cr0_0 - connect \fus_cu_rd__go_i$39 [1] \dp_INT_rb_cr0_1 - connect \fus_cu_rd__go_i$39 [0] \dp_INT_ra_cr0_1 - connect \pick_INT_ra_cr0_1 \$363 - connect \addr_en_INT_ra_alu0_0 \$355 - connect \rp_INT_ra_alu0_0 \$353 - connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 - connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 - connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 - connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 - connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 - connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 - connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 - connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 - connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 - connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 - connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 - connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 - connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 - connect \pick_INT_ra_alu0_0 \$351 - connect \rdflag_INT_ra_0 \core_reg1_ok - connect \en_ldst0 \$210 - connect \en_shiftrot0 \$206 - connect \en_mul0 \$202 - connect \en_div0 \$198 - connect \en_spr0 \$194 - connect \en_logical0 \$190 - connect \en_trap0 \$186 - connect \en_branch0 \$182 - connect \en_cr0 \$178 - connect \fu_enable [9] \en_ldst0 - connect \fu_enable [8] \en_shiftrot0 - connect \fu_enable [7] \en_mul0 - connect \fu_enable [6] \en_div0 - connect \fu_enable [5] \en_spr0 - connect \fu_enable [4] \en_logical0 - connect \fu_enable [3] \en_trap0 - connect \fu_enable [2] \en_branch0 - connect \fu_enable [1] \en_cr0 - connect \fu_enable [0] \en_alu0 - connect \en_alu0 \$174 - connect \dec_LDST_bigendian \bigendian_i - connect \dec_LDST_raw_opcode_in \raw_insn_i - connect \dec_SHIFT_ROT_bigendian \bigendian_i - connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i - connect \dec_MUL_bigendian \bigendian_i - connect \dec_MUL_raw_opcode_in \raw_insn_i - connect \dec_DIV_bigendian \bigendian_i - connect \dec_DIV_raw_opcode_in \raw_insn_i - connect \dec_SPR_bigendian \bigendian_i - connect \dec_SPR_raw_opcode_in \raw_insn_i - connect \dec_LOGICAL_bigendian \bigendian_i - connect \dec_LOGICAL_raw_opcode_in \raw_insn_i - connect \dec_BRANCH_bigendian \bigendian_i - connect \dec_BRANCH_raw_opcode_in \raw_insn_i - connect \dec_CR_bigendian \bigendian_i - connect \dec_CR_raw_opcode_in \raw_insn_i - connect \dec_ALU_bigendian \bigendian_i - connect \dec_ALU_raw_opcode_in \raw_insn_i -end -attribute \src "libresoc.v:48741.1-49374.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr" -attribute \generator "nMigen" -module \cr - attribute \src "libresoc.v:48742.7-48742.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:49288.3-49296.6" - wire width 8 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_6_src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_6_src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_6_w6__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_dest27__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_r27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_r27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_r7__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_7_w7__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$34$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 6 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 7 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 8 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 9 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 10 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 11 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 15 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \wen$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49098$3056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src14__data_o - connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49098$3056_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49099$3057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src16__data_o - connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49099$3057_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49100$3058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \$11 - connect \Y $or$libresoc.v:49100$3058_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49101$3059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$7 - connect \B \$13 - connect \Y $or$libresoc.v:49101$3059_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49104$3062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src20__data_o - connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49104$3062_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49105$3063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src22__data_o - connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49105$3063_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49106$3064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$20 - connect \B \$22 - connect \Y $or$libresoc.v:49106$3064_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49107$3065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src24__data_o - connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49107$3065_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49108$3066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src26__data_o - connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49108$3066_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49109$3067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$26 - connect \B \$28 - connect \Y $or$libresoc.v:49109$3067_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49110$3068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$24 - connect \B \$30 - connect \Y $or$libresoc.v:49110$3068_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49112$3070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src30__data_o - connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49112$3070_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49113$3071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src10__data_o - connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49113$3071_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49114$3072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src32__data_o - connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49114$3072_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49115$3073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$37 - connect \B \$39 - connect \Y $or$libresoc.v:49115$3073_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49116$3074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src34__data_o - connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49116$3074_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49117$3075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src36__data_o - connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49117$3075_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49118$3076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$43 - connect \B \$45 - connect \Y $or$libresoc.v:49118$3076_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49119$3077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$41 - connect \B \$47 - connect \Y $or$libresoc.v:49119$3077_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:49120$3078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src12__data_o - connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49120$3078_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:49121$3079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \$5 - connect \Y $or$libresoc.v:49121$3079_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49102$3060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49102$3060_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49103$3061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49103$3061_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49111$3069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49111$3069_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49128.9-49147.4" - cell \reg_0 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest10__data_i \reg_0_dest10__data_i - connect \dest10__wen \reg_0_dest10__wen - connect \dest20__data_i \reg_0_dest20__data_i - connect \dest20__wen \reg_0_dest20__wen - connect \r0__data_o \reg_0_r0__data_o - connect \r0__ren \reg_0_r0__ren - connect \r20__data_o \reg_0_r20__data_o - connect \r20__ren \reg_0_r20__ren - connect \src10__data_o \reg_0_src10__data_o - connect \src10__ren \reg_0_src10__ren - connect \src20__data_o \reg_0_src20__data_o - connect \src20__ren \reg_0_src20__ren - connect \src30__data_o \reg_0_src30__data_o - connect \src30__ren \reg_0_src30__ren - connect \w0__data_i \reg_0_w0__data_i - connect \w0__wen \reg_0_w0__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49148.9-49167.4" - cell \reg_1 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest11__data_i \reg_1_dest11__data_i - connect \dest11__wen \reg_1_dest11__wen - connect \dest21__data_i \reg_1_dest21__data_i - connect \dest21__wen \reg_1_dest21__wen - connect \r1__data_o \reg_1_r1__data_o - connect \r1__ren \reg_1_r1__ren - connect \r21__data_o \reg_1_r21__data_o - connect \r21__ren \reg_1_r21__ren - connect \src11__data_o \reg_1_src11__data_o - connect \src11__ren \reg_1_src11__ren - connect \src21__data_o \reg_1_src21__data_o - connect \src21__ren \reg_1_src21__ren - connect \src31__data_o \reg_1_src31__data_o - connect \src31__ren \reg_1_src31__ren - connect \w1__data_i \reg_1_w1__data_i - connect \w1__wen \reg_1_w1__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49168.9-49187.4" - cell \reg_2 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest12__data_i \reg_2_dest12__data_i - connect \dest12__wen \reg_2_dest12__wen - connect \dest22__data_i \reg_2_dest22__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \r22__data_o \reg_2_r22__data_o - connect \r22__ren \reg_2_r22__ren - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src12__ren \reg_2_src12__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src22__ren \reg_2_src22__ren - connect \src32__data_o \reg_2_src32__data_o - connect \src32__ren \reg_2_src32__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49188.9-49207.4" - cell \reg_3 \reg_3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest13__data_i \reg_3_dest13__data_i - connect \dest13__wen \reg_3_dest13__wen - connect \dest23__data_i \reg_3_dest23__data_i - connect \dest23__wen \reg_3_dest23__wen - connect \r23__data_o \reg_3_r23__data_o - connect \r23__ren \reg_3_r23__ren - connect \r3__data_o \reg_3_r3__data_o - connect \r3__ren \reg_3_r3__ren - connect \src13__data_o \reg_3_src13__data_o - connect \src13__ren \reg_3_src13__ren - connect \src23__data_o \reg_3_src23__data_o - connect \src23__ren \reg_3_src23__ren - connect \src33__data_o \reg_3_src33__data_o - connect \src33__ren \reg_3_src33__ren - connect \w3__data_i \reg_3_w3__data_i - connect \w3__wen \reg_3_w3__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49208.9-49227.4" - cell \reg_4 \reg_4 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest14__data_i \reg_4_dest14__data_i - connect \dest14__wen \reg_4_dest14__wen - connect \dest24__data_i \reg_4_dest24__data_i - connect \dest24__wen \reg_4_dest24__wen - connect \r24__data_o \reg_4_r24__data_o - connect \r24__ren \reg_4_r24__ren - connect \r4__data_o \reg_4_r4__data_o - connect \r4__ren \reg_4_r4__ren - connect \src14__data_o \reg_4_src14__data_o - connect \src14__ren \reg_4_src14__ren - connect \src24__data_o \reg_4_src24__data_o - connect \src24__ren \reg_4_src24__ren - connect \src34__data_o \reg_4_src34__data_o - connect \src34__ren \reg_4_src34__ren - connect \w4__data_i \reg_4_w4__data_i - connect \w4__wen \reg_4_w4__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49228.9-49247.4" - cell \reg_5 \reg_5 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest15__data_i \reg_5_dest15__data_i - connect \dest15__wen \reg_5_dest15__wen - connect \dest25__data_i \reg_5_dest25__data_i - connect \dest25__wen \reg_5_dest25__wen - connect \r25__data_o \reg_5_r25__data_o - connect \r25__ren \reg_5_r25__ren - connect \r5__data_o \reg_5_r5__data_o - connect \r5__ren \reg_5_r5__ren - connect \src15__data_o \reg_5_src15__data_o - connect \src15__ren \reg_5_src15__ren - connect \src25__data_o \reg_5_src25__data_o - connect \src25__ren \reg_5_src25__ren - connect \src35__data_o \reg_5_src35__data_o - connect \src35__ren \reg_5_src35__ren - connect \w5__data_i \reg_5_w5__data_i - connect \w5__wen \reg_5_w5__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49248.9-49267.4" - cell \reg_6 \reg_6 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest16__data_i \reg_6_dest16__data_i - connect \dest16__wen \reg_6_dest16__wen - connect \dest26__data_i \reg_6_dest26__data_i - connect \dest26__wen \reg_6_dest26__wen - connect \r26__data_o \reg_6_r26__data_o - connect \r26__ren \reg_6_r26__ren - connect \r6__data_o \reg_6_r6__data_o - connect \r6__ren \reg_6_r6__ren - connect \src16__data_o \reg_6_src16__data_o - connect \src16__ren \reg_6_src16__ren - connect \src26__data_o \reg_6_src26__data_o - connect \src26__ren \reg_6_src26__ren - connect \src36__data_o \reg_6_src36__data_o - connect \src36__ren \reg_6_src36__ren - connect \w6__data_i \reg_6_w6__data_i - connect \w6__wen \reg_6_w6__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:49268.9-49287.4" - cell \reg_7 \reg_7 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest17__data_i \reg_7_dest17__data_i - connect \dest17__wen \reg_7_dest17__wen - connect \dest27__data_i \reg_7_dest27__data_i - connect \dest27__wen \reg_7_dest27__wen - connect \r27__data_o \reg_7_r27__data_o - connect \r27__ren \reg_7_r27__ren - connect \r7__data_o \reg_7_r7__data_o - connect \r7__ren \reg_7_r7__ren - connect \src17__data_o \reg_7_src17__data_o - connect \src17__ren \reg_7_src17__ren - connect \src27__data_o \reg_7_src27__data_o - connect \src27__ren \reg_7_src27__ren - connect \src37__data_o \reg_7_src37__data_o - connect \src37__ren \reg_7_src37__ren - connect \w7__data_i \reg_7_w7__data_i - connect \w7__wen \reg_7_w7__wen - end - attribute \src "libresoc.v:48742.7-48742.20" - process $proc$libresoc.v:48742$3097 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:49068.13-49068.30" - process $proc$libresoc.v:49068$3098 - assign { } { } - assign $1\ren_delay[7:0] 8'00000000 - sync always - sync init - update \ren_delay $1\ren_delay[7:0] - end - attribute \src "libresoc.v:49070.13-49070.35" - process $proc$libresoc.v:49070$3099 - assign { } { } - assign $0\ren_delay$17[7:0]$3100 8'00000000 - sync always - sync init - update \ren_delay$17 $0\ren_delay$17[7:0]$3100 - end - attribute \src "libresoc.v:49074.13-49074.35" - process $proc$libresoc.v:49074$3101 - assign { } { } - assign $0\ren_delay$34[7:0]$3102 8'00000000 - sync always - sync init - update \ren_delay$34 $0\ren_delay$34[7:0]$3102 - end - attribute \src "libresoc.v:49122.3-49123.43" - process $proc$libresoc.v:49122$3080 - assign { } { } - assign $0\ren_delay$34[7:0]$3081 \ren_delay$34$next - sync posedge \coresync_clk - update \ren_delay$34 $0\ren_delay$34[7:0]$3081 - end - attribute \src "libresoc.v:49124.3-49125.43" - process $proc$libresoc.v:49124$3082 - assign { } { } - assign $0\ren_delay$17[7:0]$3083 \ren_delay$17$next - sync posedge \coresync_clk - update \ren_delay$17 $0\ren_delay$17[7:0]$3083 - end - attribute \src "libresoc.v:49126.3-49127.35" - process $proc$libresoc.v:49126$3084 - assign { } { } - assign $0\ren_delay[7:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[7:0] - end - attribute \src "libresoc.v:49288.3-49296.6" - process $proc$libresoc.v:49288$3085 - assign { } { } - assign { } { } - assign $0\ren_delay$17$next[7:0]$3086 $1\ren_delay$17$next[7:0]$3087 - attribute \src "libresoc.v:49289.5-49289.29" - switch \initial - attribute \src "libresoc.v:49289.9-49289.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$17$next[7:0]$3087 8'00000000 - case - assign $1\ren_delay$17$next[7:0]$3087 \src2__ren - end - sync always - update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3086 - end - attribute \src "libresoc.v:49297.3-49306.6" - process $proc$libresoc.v:49297$3088 - assign { } { } - assign { } { } - assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49298.5-49298.29" - switch \initial - attribute \src "libresoc.v:49298.9-49298.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$18 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[3:0] \$32 - case - assign $1\src2__data_o[3:0] 4'0000 - end - sync always - update \src2__data_o $0\src2__data_o[3:0] - end - attribute \src "libresoc.v:49307.3-49315.6" - process $proc$libresoc.v:49307$3089 - assign { } { } - assign { } { } - assign $0\ren_delay$34$next[7:0]$3090 $1\ren_delay$34$next[7:0]$3091 - attribute \src "libresoc.v:49308.5-49308.29" - switch \initial - attribute \src "libresoc.v:49308.9-49308.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$34$next[7:0]$3091 8'00000000 - case - assign $1\ren_delay$34$next[7:0]$3091 \src3__ren - end - sync always - update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3090 - end - attribute \src "libresoc.v:49316.3-49325.6" - process $proc$libresoc.v:49316$3092 - assign { } { } - assign { } { } - assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49317.5-49317.29" - switch \initial - attribute \src "libresoc.v:49317.9-49317.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$35 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src3__data_o[3:0] \$49 - case - assign $1\src3__data_o[3:0] 4'0000 - end - sync always - update \src3__data_o $0\src3__data_o[3:0] - end - attribute \src "libresoc.v:49326.3-49334.6" - process $proc$libresoc.v:49326$3093 - assign { } { } - assign { } { } - assign $0\ren_delay$next[7:0]$3094 $1\ren_delay$next[7:0]$3095 - attribute \src "libresoc.v:49327.5-49327.29" - switch \initial - attribute \src "libresoc.v:49327.9-49327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[7:0]$3095 8'00000000 - case - assign $1\ren_delay$next[7:0]$3095 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[7:0]$3094 - end - attribute \src "libresoc.v:49335.3-49344.6" - process $proc$libresoc.v:49335$3096 - assign { } { } - assign { } { } - assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49336.5-49336.29" - switch \initial - attribute \src "libresoc.v:49336.9-49336.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[3:0] \$15 - case - assign $1\src1__data_o[3:0] 4'0000 - end - sync always - update \src1__data_o $0\src1__data_o[3:0] - end - connect \$9 $or$libresoc.v:49098$3056_Y - connect \$11 $or$libresoc.v:49099$3057_Y - connect \$13 $or$libresoc.v:49100$3058_Y - connect \$15 $or$libresoc.v:49101$3059_Y - connect \$18 $reduce_or$libresoc.v:49102$3060_Y - connect \$1 $reduce_or$libresoc.v:49103$3061_Y - connect \$20 $or$libresoc.v:49104$3062_Y - connect \$22 $or$libresoc.v:49105$3063_Y - connect \$24 $or$libresoc.v:49106$3064_Y - connect \$26 $or$libresoc.v:49107$3065_Y - connect \$28 $or$libresoc.v:49108$3066_Y - connect \$30 $or$libresoc.v:49109$3067_Y - connect \$32 $or$libresoc.v:49110$3068_Y - connect \$35 $reduce_or$libresoc.v:49111$3069_Y - connect \$37 $or$libresoc.v:49112$3070_Y - connect \$3 $or$libresoc.v:49113$3071_Y - connect \$39 $or$libresoc.v:49114$3072_Y - connect \$41 $or$libresoc.v:49115$3073_Y - connect \$43 $or$libresoc.v:49116$3074_Y - connect \$45 $or$libresoc.v:49117$3075_Y - connect \$47 $or$libresoc.v:49118$3076_Y - connect \$49 $or$libresoc.v:49119$3077_Y - connect \$5 $or$libresoc.v:49120$3078_Y - connect \$7 $or$libresoc.v:49121$3079_Y - connect \wen$51 8'00000000 - connect \data_i$52 4'0000 - connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen - connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i - connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren - connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } - connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } - connect \reg_7_dest27__data_i 4'0000 - connect \reg_6_dest26__data_i 4'0000 - connect \reg_5_dest25__data_i 4'0000 - connect \reg_4_dest24__data_i 4'0000 - connect \reg_3_dest23__data_i 4'0000 - connect \reg_2_dest22__data_i 4'0000 - connect \reg_1_dest21__data_i 4'0000 - connect \reg_0_dest20__data_i 4'0000 - connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 - connect \reg_7_dest17__data_i \data_i - connect \reg_6_dest16__data_i \data_i - connect \reg_5_dest15__data_i \data_i - connect \reg_4_dest14__data_i \data_i - connect \reg_3_dest13__data_i \data_i - connect \reg_2_dest12__data_i \data_i - connect \reg_1_dest11__data_i \data_i - connect \reg_0_dest10__data_i \data_i - connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen - connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren - connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren - connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren -end -attribute \src "libresoc.v:49378.1-50429.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" -attribute \generator "nMigen" -module \cr0 - attribute \src "libresoc.v:50030.3-50031.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50203.3-50214.6" - wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3222 - attribute \src "libresoc.v:50002.3-50003.61" - wire width 12 $0\alu_cr0_cr_op__fn_unit[11:0] - attribute \src "libresoc.v:50203.3-50214.6" - wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3223 - attribute \src "libresoc.v:50004.3-50005.55" - wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50203.3-50214.6" - wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3224 - attribute \src "libresoc.v:50000.3-50001.65" - wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50028.3-50029.39" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50350.3-50358.6" - wire $0\alu_l_r_alu$next[0:0]$3274 - attribute \src "libresoc.v:49972.3-49973.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50341.3-50349.6" - wire $0\alui_l_r_alui$next[0:0]$3271 - attribute \src "libresoc.v:49974.3-49975.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50215.3-50236.6" - wire width 64 $0\data_r0__o$next[63:0]$3229 - attribute \src "libresoc.v:49996.3-49997.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50215.3-50236.6" - wire $0\data_r0__o_ok$next[0:0]$3230 - attribute \src "libresoc.v:49998.3-49999.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50237.3-50258.6" - wire width 32 $0\data_r1__full_cr$next[31:0]$3237 - attribute \src "libresoc.v:49992.3-49993.49" - wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50237.3-50258.6" - wire $0\data_r1__full_cr_ok$next[0:0]$3238 - attribute \src "libresoc.v:49994.3-49995.55" - wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50259.3-50280.6" - wire width 4 $0\data_r2__cr_a$next[3:0]$3245 - attribute \src "libresoc.v:49988.3-49989.43" - wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50259.3-50280.6" - wire $0\data_r2__cr_a_ok$next[0:0]$3246 - attribute \src "libresoc.v:49990.3-49991.49" - wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50359.3-50368.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50369.3-50378.6" - wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50379.3-50388.6" - wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49379.7-49379.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:50158.3-50166.6" - wire $0\opc_l_r_opc$next[0:0]$3207 - attribute \src "libresoc.v:50014.3-50015.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50149.3-50157.6" - wire $0\opc_l_s_opc$next[0:0]$3204 - attribute \src "libresoc.v:50016.3-50017.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50389.3-50397.6" - wire width 3 $0\prev_wr_go$next[2:0]$3280 - attribute \src "libresoc.v:50026.3-50027.37" - wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50103.3-50112.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:50194.3-50202.6" - wire width 3 $0\req_l_r_req$next[2:0]$3219 - attribute \src "libresoc.v:50006.3-50007.39" - wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50185.3-50193.6" - wire width 3 $0\req_l_s_req$next[2:0]$3216 - attribute \src "libresoc.v:50008.3-50009.39" - wire width 3 $0\req_l_s_req[2:0] - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:49938$3126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$libresoc.v:49938$3126_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:49949$3137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:49949$3137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:49950$3138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:49950$3138_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:49951$3139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:49951$3139_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:49952$3140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:49952$3140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:49956$3144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:49956$3144_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:49966$3154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:49966$3154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:49915$3103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$libresoc.v:49915$3103_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:49933$3121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$libresoc.v:49933$3121_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:49936$3124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:49936$3124_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:49937$3125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:49937$3125_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49960$3148 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:49960$3148_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49961$3149 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:49961$3149_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49962$3150 - parameter \WIDTH 32 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:49962$3150_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49963$3151 - parameter \WIDTH 4 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:49963$3151_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49964$3152 - parameter \WIDTH 4 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:49964$3152_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:49965$3153 - parameter \WIDTH 4 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:49965$3153_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50032.11-50054.4" - cell \alu_cr0 \alu_cr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_cr0_cr_a - connect \cr_a$2 \alu_cr0_cr_a$2 - connect \cr_a_ok \cr_a_ok - connect \cr_b \alu_cr0_cr_b - connect \cr_c \alu_cr0_cr_c - connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit - connect \cr_op__insn \alu_cr0_cr_op__insn - connect \cr_op__insn_type \alu_cr0_cr_op__insn_type - connect \full_cr \alu_cr0_full_cr - connect \full_cr$1 \alu_cr0_full_cr$1 - connect \full_cr_ok \full_cr_ok - connect \n_ready_i \alu_cr0_n_ready_i - connect \n_valid_o \alu_cr0_n_valid_o - connect \o \alu_cr0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_cr0_p_ready_o - connect \p_valid_i \alu_cr0_p_valid_i - connect \ra \alu_cr0_ra - connect \rb \alu_cr0_rb - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50055.14-50061.4" - cell \alu_l$16 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50062.15-50068.4" - cell \alui_l$15 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50069.14-50075.4" - cell \opc_l$11 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50076.14-50082.4" - cell \req_l$12 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50083.14-50089.4" - cell \rok_l$14 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50090.14-50095.4" - cell \rst_l$13 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:50096.14-50102.4" - cell \src_l$10 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:49379.7-49379.20" - process $proc$libresoc.v:49379$3282 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:49497.7-49497.24" - process $proc$libresoc.v:49497$3283 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:49526.14-49526.46" - process $proc$libresoc.v:49526$3284 - assign { } { } - assign $1\alu_cr0_cr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:49530.14-49530.41" - process $proc$libresoc.v:49530$3285 - assign { } { } - assign $1\alu_cr0_cr_op__insn[31:0] 0 - sync always - sync init - update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] - end - attribute \src "libresoc.v:49608.13-49608.45" - process $proc$libresoc.v:49608$3286 - assign { } { } - assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] - end - attribute \src "libresoc.v:49632.7-49632.26" - process $proc$libresoc.v:49632$3287 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:49640.7-49640.25" - process $proc$libresoc.v:49640$3288 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:49652.7-49652.27" - process $proc$libresoc.v:49652$3289 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:49686.14-49686.47" - process $proc$libresoc.v:49686$3290 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:49690.7-49690.27" - process $proc$libresoc.v:49690$3291 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:49694.14-49694.38" - process $proc$libresoc.v:49694$3292 - assign { } { } - assign $1\data_r1__full_cr[31:0] 0 - sync always - sync init - update \data_r1__full_cr $1\data_r1__full_cr[31:0] - end - attribute \src "libresoc.v:49698.7-49698.33" - process $proc$libresoc.v:49698$3293 - assign { } { } - assign $1\data_r1__full_cr_ok[0:0] 1'0 - sync always - sync init - update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] - end - attribute \src "libresoc.v:49702.13-49702.33" - process $proc$libresoc.v:49702$3294 - assign { } { } - assign $1\data_r2__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r2__cr_a $1\data_r2__cr_a[3:0] - end - attribute \src "libresoc.v:49706.7-49706.30" - process $proc$libresoc.v:49706$3295 - assign { } { } - assign $1\data_r2__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] - end - attribute \src "libresoc.v:49725.7-49725.25" - process $proc$libresoc.v:49725$3296 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:49729.7-49729.25" - process $proc$libresoc.v:49729$3297 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:49826.13-49826.30" - process $proc$libresoc.v:49826$3298 - assign { } { } - assign $1\prev_wr_go[2:0] 3'000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[2:0] - end - attribute \src "libresoc.v:49834.13-49834.31" - process $proc$libresoc.v:49834$3299 - assign { } { } - assign $1\req_l_r_req[2:0] 3'111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[2:0] - end - attribute \src "libresoc.v:49838.13-49838.31" - process $proc$libresoc.v:49838$3300 - assign { } { } - assign $1\req_l_s_req[2:0] 3'000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[2:0] - end - attribute \src "libresoc.v:49850.7-49850.26" - process $proc$libresoc.v:49850$3301 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:49854.7-49854.26" - process $proc$libresoc.v:49854$3302 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:49858.7-49858.25" - process $proc$libresoc.v:49858$3303 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:49862.7-49862.25" - process $proc$libresoc.v:49862$3304 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:49882.13-49882.32" - process $proc$libresoc.v:49882$3305 - assign { } { } - assign $1\src_l_r_src[5:0] 6'111111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[5:0] - end - attribute \src "libresoc.v:49886.13-49886.32" - process $proc$libresoc.v:49886$3306 - assign { } { } - assign $1\src_l_s_src[5:0] 6'000000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[5:0] - end - attribute \src "libresoc.v:49890.14-49890.43" - process $proc$libresoc.v:49890$3307 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:49894.14-49894.43" - process $proc$libresoc.v:49894$3308 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:49898.14-49898.28" - process $proc$libresoc.v:49898$3309 - assign { } { } - assign $1\src_r2[31:0] 0 - sync always - sync init - update \src_r2 $1\src_r2[31:0] - end - attribute \src "libresoc.v:49902.13-49902.26" - process $proc$libresoc.v:49902$3310 - assign { } { } - assign $1\src_r3[3:0] 4'0000 - sync always - sync init - update \src_r3 $1\src_r3[3:0] - end - attribute \src "libresoc.v:49906.13-49906.26" - process $proc$libresoc.v:49906$3311 - assign { } { } - assign $1\src_r4[3:0] 4'0000 - sync always - sync init - update \src_r4 $1\src_r4[3:0] - end - attribute \src "libresoc.v:49910.13-49910.26" - process $proc$libresoc.v:49910$3312 - assign { } { } - assign $1\src_r5[3:0] 4'0000 - sync always - sync init - update \src_r5 $1\src_r5[3:0] - end - attribute \src "libresoc.v:49972.3-49973.39" - process $proc$libresoc.v:49972$3160 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:49974.3-49975.43" - process $proc$libresoc.v:49974$3161 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:49976.3-49977.29" - process $proc$libresoc.v:49976$3162 - assign { } { } - assign $0\src_r5[3:0] \src_r5$next - sync posedge \coresync_clk - update \src_r5 $0\src_r5[3:0] - end - attribute \src "libresoc.v:49978.3-49979.29" - process $proc$libresoc.v:49978$3163 - assign { } { } - assign $0\src_r4[3:0] \src_r4$next - sync posedge \coresync_clk - update \src_r4 $0\src_r4[3:0] - end - attribute \src "libresoc.v:49980.3-49981.29" - process $proc$libresoc.v:49980$3164 - assign { } { } - assign $0\src_r3[3:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[3:0] - end - attribute \src "libresoc.v:49982.3-49983.29" - process $proc$libresoc.v:49982$3165 - assign { } { } - assign $0\src_r2[31:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[31:0] - end - attribute \src "libresoc.v:49984.3-49985.29" - process $proc$libresoc.v:49984$3166 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:49986.3-49987.29" - process $proc$libresoc.v:49986$3167 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:49988.3-49989.43" - process $proc$libresoc.v:49988$3168 - assign { } { } - assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next - sync posedge \coresync_clk - update \data_r2__cr_a $0\data_r2__cr_a[3:0] - end - attribute \src "libresoc.v:49990.3-49991.49" - process $proc$libresoc.v:49990$3169 - assign { } { } - assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next - sync posedge \coresync_clk - update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] - end - attribute \src "libresoc.v:49992.3-49993.49" - process $proc$libresoc.v:49992$3170 - assign { } { } - assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next - sync posedge \coresync_clk - update \data_r1__full_cr $0\data_r1__full_cr[31:0] - end - attribute \src "libresoc.v:49994.3-49995.55" - process $proc$libresoc.v:49994$3171 - assign { } { } - assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next - sync posedge \coresync_clk - update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] - end - attribute \src "libresoc.v:49996.3-49997.37" - process $proc$libresoc.v:49996$3172 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:49998.3-49999.43" - process $proc$libresoc.v:49998$3173 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:50000.3-50001.65" - process $proc$libresoc.v:50000$3174 - assign { } { } - assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next - sync posedge \coresync_clk - update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] - end - attribute \src "libresoc.v:50002.3-50003.61" - process $proc$libresoc.v:50002$3175 - assign { } { } - assign $0\alu_cr0_cr_op__fn_unit[11:0] \alu_cr0_cr_op__fn_unit$next - sync posedge \coresync_clk - update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:50004.3-50005.55" - process $proc$libresoc.v:50004$3176 - assign { } { } - assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next - sync posedge \coresync_clk - update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] - end - attribute \src "libresoc.v:50006.3-50007.39" - process $proc$libresoc.v:50006$3177 - assign { } { } - assign $0\req_l_r_req[2:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[2:0] - end - attribute \src "libresoc.v:50008.3-50009.39" - process $proc$libresoc.v:50008$3178 - assign { } { } - assign $0\req_l_s_req[2:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[2:0] - end - attribute \src "libresoc.v:50010.3-50011.39" - process $proc$libresoc.v:50010$3179 - assign { } { } - assign $0\src_l_r_src[5:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[5:0] - end - attribute \src "libresoc.v:50012.3-50013.39" - process $proc$libresoc.v:50012$3180 - assign { } { } - assign $0\src_l_s_src[5:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[5:0] - end - attribute \src "libresoc.v:50014.3-50015.39" - process $proc$libresoc.v:50014$3181 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:50016.3-50017.39" - process $proc$libresoc.v:50016$3182 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:50018.3-50019.39" - process $proc$libresoc.v:50018$3183 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:50020.3-50021.39" - process $proc$libresoc.v:50020$3184 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:50022.3-50023.41" - process $proc$libresoc.v:50022$3185 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:50024.3-50025.41" - process $proc$libresoc.v:50024$3186 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:50026.3-50027.37" - process $proc$libresoc.v:50026$3187 - assign { } { } - assign $0\prev_wr_go[2:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[2:0] - end - attribute \src "libresoc.v:50028.3-50029.39" - process $proc$libresoc.v:50028$3188 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:50030.3-50031.25" - process $proc$libresoc.v:50030$3189 - assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:50103.3-50112.6" - process $proc$libresoc.v:50103$3190 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50104.5-50104.29" - switch \initial - attribute \src "libresoc.v:50104.9-50104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$47 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:50113.3-50121.6" - process $proc$libresoc.v:50113$3191 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$3192 $1\rok_l_s_rdok$next[0:0]$3193 - attribute \src "libresoc.v:50114.5-50114.29" - switch \initial - attribute \src "libresoc.v:50114.9-50114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$3193 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$3193 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3192 - end - attribute \src "libresoc.v:50122.3-50130.6" - process $proc$libresoc.v:50122$3194 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$3195 $1\rok_l_r_rdok$next[0:0]$3196 - attribute \src "libresoc.v:50123.5-50123.29" - switch \initial - attribute \src "libresoc.v:50123.9-50123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$3196 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$3196 \$65 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3195 - end - attribute \src "libresoc.v:50131.3-50139.6" - process $proc$libresoc.v:50131$3197 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$3198 $1\rst_l_s_rst$next[0:0]$3199 - attribute \src "libresoc.v:50132.5-50132.29" - switch \initial - attribute \src "libresoc.v:50132.9-50132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$3199 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$3199 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3198 - end - attribute \src "libresoc.v:50140.3-50148.6" - process $proc$libresoc.v:50140$3200 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$3201 $1\rst_l_r_rst$next[0:0]$3202 - attribute \src "libresoc.v:50141.5-50141.29" - switch \initial - attribute \src "libresoc.v:50141.9-50141.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$3202 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$3202 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3201 - end - attribute \src "libresoc.v:50149.3-50157.6" - process $proc$libresoc.v:50149$3203 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$3204 $1\opc_l_s_opc$next[0:0]$3205 - attribute \src "libresoc.v:50150.5-50150.29" - switch \initial - attribute \src "libresoc.v:50150.9-50150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$3205 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$3205 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3204 - end - attribute \src "libresoc.v:50158.3-50166.6" - process $proc$libresoc.v:50158$3206 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$3207 $1\opc_l_r_opc$next[0:0]$3208 - attribute \src "libresoc.v:50159.5-50159.29" - switch \initial - attribute \src "libresoc.v:50159.9-50159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$3208 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$3208 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3207 - end - attribute \src "libresoc.v:50167.3-50175.6" - process $proc$libresoc.v:50167$3209 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[5:0]$3210 $1\src_l_s_src$next[5:0]$3211 - attribute \src "libresoc.v:50168.5-50168.29" - switch \initial - attribute \src "libresoc.v:50168.9-50168.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[5:0]$3211 6'000000 - case - assign $1\src_l_s_src$next[5:0]$3211 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3210 - end - attribute \src "libresoc.v:50176.3-50184.6" - process $proc$libresoc.v:50176$3212 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[5:0]$3213 $1\src_l_r_src$next[5:0]$3214 - attribute \src "libresoc.v:50177.5-50177.29" - switch \initial - attribute \src "libresoc.v:50177.9-50177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[5:0]$3214 6'111111 - case - assign $1\src_l_r_src$next[5:0]$3214 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3213 - end - attribute \src "libresoc.v:50185.3-50193.6" - process $proc$libresoc.v:50185$3215 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[2:0]$3216 $1\req_l_s_req$next[2:0]$3217 - attribute \src "libresoc.v:50186.5-50186.29" - switch \initial - attribute \src "libresoc.v:50186.9-50186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[2:0]$3217 3'000 - case - assign $1\req_l_s_req$next[2:0]$3217 \$67 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3216 - end - attribute \src "libresoc.v:50194.3-50202.6" - process $proc$libresoc.v:50194$3218 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[2:0]$3219 $1\req_l_r_req$next[2:0]$3220 - attribute \src "libresoc.v:50195.5-50195.29" - switch \initial - attribute \src "libresoc.v:50195.9-50195.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[2:0]$3220 3'111 - case - assign $1\req_l_r_req$next[2:0]$3220 \$69 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3219 - end - attribute \src "libresoc.v:50203.3-50214.6" - process $proc$libresoc.v:50203$3221 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3222 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3225 - assign $0\alu_cr0_cr_op__insn$next[31:0]$3223 $1\alu_cr0_cr_op__insn$next[31:0]$3226 - assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3224 $1\alu_cr0_cr_op__insn_type$next[6:0]$3227 - attribute \src "libresoc.v:50204.5-50204.29" - switch \initial - attribute \src "libresoc.v:50204.9-50204.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_cr0_cr_op__insn$next[31:0]$3226 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3225 $1\alu_cr0_cr_op__insn_type$next[6:0]$3227 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } - case - assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3225 \alu_cr0_cr_op__fn_unit - assign $1\alu_cr0_cr_op__insn$next[31:0]$3226 \alu_cr0_cr_op__insn - assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3227 \alu_cr0_cr_op__insn_type - end - sync always - update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3222 - update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3223 - update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3224 - end - attribute \src "libresoc.v:50215.3-50236.6" - process $proc$libresoc.v:50215$3228 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$3229 $2\data_r0__o$next[63:0]$3233 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$3230 $3\data_r0__o_ok$next[0:0]$3235 - attribute \src "libresoc.v:50216.5-50216.29" - switch \initial - attribute \src "libresoc.v:50216.9-50216.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$3232 $1\data_r0__o$next[63:0]$3231 } { \o_ok \alu_cr0_o } - case - assign $1\data_r0__o$next[63:0]$3231 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$3232 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$3234 $2\data_r0__o$next[63:0]$3233 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$3233 $1\data_r0__o$next[63:0]$3231 - assign $2\data_r0__o_ok$next[0:0]$3234 $1\data_r0__o_ok$next[0:0]$3232 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$3235 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$3235 $2\data_r0__o_ok$next[0:0]$3234 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$3229 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3230 - end - attribute \src "libresoc.v:50237.3-50258.6" - process $proc$libresoc.v:50237$3236 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__full_cr$next[31:0]$3237 $2\data_r1__full_cr$next[31:0]$3241 - assign { } { } - assign $0\data_r1__full_cr_ok$next[0:0]$3238 $3\data_r1__full_cr_ok$next[0:0]$3243 - attribute \src "libresoc.v:50238.5-50238.29" - switch \initial - attribute \src "libresoc.v:50238.9-50238.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__full_cr_ok$next[0:0]$3240 $1\data_r1__full_cr$next[31:0]$3239 } { \full_cr_ok \alu_cr0_full_cr } - case - assign $1\data_r1__full_cr$next[31:0]$3239 \data_r1__full_cr - assign $1\data_r1__full_cr_ok$next[0:0]$3240 \data_r1__full_cr_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__full_cr_ok$next[0:0]$3242 $2\data_r1__full_cr$next[31:0]$3241 } 33'000000000000000000000000000000000 - case - assign $2\data_r1__full_cr$next[31:0]$3241 $1\data_r1__full_cr$next[31:0]$3239 - assign $2\data_r1__full_cr_ok$next[0:0]$3242 $1\data_r1__full_cr_ok$next[0:0]$3240 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__full_cr_ok$next[0:0]$3243 1'0 - case - assign $3\data_r1__full_cr_ok$next[0:0]$3243 $2\data_r1__full_cr_ok$next[0:0]$3242 - end - sync always - update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3237 - update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3238 - end - attribute \src "libresoc.v:50259.3-50280.6" - process $proc$libresoc.v:50259$3244 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__cr_a$next[3:0]$3245 $2\data_r2__cr_a$next[3:0]$3249 - assign { } { } - assign $0\data_r2__cr_a_ok$next[0:0]$3246 $3\data_r2__cr_a_ok$next[0:0]$3251 - attribute \src "libresoc.v:50260.5-50260.29" - switch \initial - attribute \src "libresoc.v:50260.9-50260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__cr_a_ok$next[0:0]$3248 $1\data_r2__cr_a$next[3:0]$3247 } { \cr_a_ok \alu_cr0_cr_a } - case - assign $1\data_r2__cr_a$next[3:0]$3247 \data_r2__cr_a - assign $1\data_r2__cr_a_ok$next[0:0]$3248 \data_r2__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__cr_a_ok$next[0:0]$3250 $2\data_r2__cr_a$next[3:0]$3249 } 5'00000 - case - assign $2\data_r2__cr_a$next[3:0]$3249 $1\data_r2__cr_a$next[3:0]$3247 - assign $2\data_r2__cr_a_ok$next[0:0]$3250 $1\data_r2__cr_a_ok$next[0:0]$3248 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__cr_a_ok$next[0:0]$3251 1'0 - case - assign $3\data_r2__cr_a_ok$next[0:0]$3251 $2\data_r2__cr_a_ok$next[0:0]$3250 - end - sync always - update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3245 - update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3246 - end - attribute \src "libresoc.v:50281.3-50290.6" - process $proc$libresoc.v:50281$3252 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$3253 $1\src_r0$next[63:0]$3254 - attribute \src "libresoc.v:50282.5-50282.29" - switch \initial - attribute \src "libresoc.v:50282.9-50282.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$3254 \src1_i - case - assign $1\src_r0$next[63:0]$3254 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$3253 - end - attribute \src "libresoc.v:50291.3-50300.6" - process $proc$libresoc.v:50291$3255 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$3256 $1\src_r1$next[63:0]$3257 - attribute \src "libresoc.v:50292.5-50292.29" - switch \initial - attribute \src "libresoc.v:50292.9-50292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$3257 \src2_i - case - assign $1\src_r1$next[63:0]$3257 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$3256 - end - attribute \src "libresoc.v:50301.3-50310.6" - process $proc$libresoc.v:50301$3258 - assign { } { } - assign { } { } - assign $0\src_r2$next[31:0]$3259 $1\src_r2$next[31:0]$3260 - attribute \src "libresoc.v:50302.5-50302.29" - switch \initial - attribute \src "libresoc.v:50302.9-50302.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[31:0]$3260 \src3_i - case - assign $1\src_r2$next[31:0]$3260 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[31:0]$3259 - end - attribute \src "libresoc.v:50311.3-50320.6" - process $proc$libresoc.v:50311$3261 - assign { } { } - assign { } { } - assign $0\src_r3$next[3:0]$3262 $1\src_r3$next[3:0]$3263 - attribute \src "libresoc.v:50312.5-50312.29" - switch \initial - attribute \src "libresoc.v:50312.9-50312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r3$next[3:0]$3263 \src4_i - case - assign $1\src_r3$next[3:0]$3263 \src_r3 - end - sync always - update \src_r3$next $0\src_r3$next[3:0]$3262 - end - attribute \src "libresoc.v:50321.3-50330.6" - process $proc$libresoc.v:50321$3264 - assign { } { } - assign { } { } - assign $0\src_r4$next[3:0]$3265 $1\src_r4$next[3:0]$3266 - attribute \src "libresoc.v:50322.5-50322.29" - switch \initial - attribute \src "libresoc.v:50322.9-50322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r4$next[3:0]$3266 \src5_i - case - assign $1\src_r4$next[3:0]$3266 \src_r4 - end - sync always - update \src_r4$next $0\src_r4$next[3:0]$3265 - end - attribute \src "libresoc.v:50331.3-50340.6" - process $proc$libresoc.v:50331$3267 - assign { } { } - assign { } { } - assign $0\src_r5$next[3:0]$3268 $1\src_r5$next[3:0]$3269 - attribute \src "libresoc.v:50332.5-50332.29" - switch \initial - attribute \src "libresoc.v:50332.9-50332.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [5] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r5$next[3:0]$3269 \src6_i - case - assign $1\src_r5$next[3:0]$3269 \src_r5 - end - sync always - update \src_r5$next $0\src_r5$next[3:0]$3268 - end - attribute \src "libresoc.v:50341.3-50349.6" - process $proc$libresoc.v:50341$3270 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$3271 $1\alui_l_r_alui$next[0:0]$3272 - attribute \src "libresoc.v:50342.5-50342.29" - switch \initial - attribute \src "libresoc.v:50342.9-50342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$3272 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$3272 \$89 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3271 - end - attribute \src "libresoc.v:50350.3-50358.6" - process $proc$libresoc.v:50350$3273 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$3274 $1\alu_l_r_alu$next[0:0]$3275 - attribute \src "libresoc.v:50351.5-50351.29" - switch \initial - attribute \src "libresoc.v:50351.9-50351.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$3275 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$3275 \$91 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3274 - end - attribute \src "libresoc.v:50359.3-50368.6" - process $proc$libresoc.v:50359$3276 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50360.5-50360.29" - switch \initial - attribute \src "libresoc.v:50360.9-50360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$111 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:50369.3-50378.6" - process $proc$libresoc.v:50369$3277 - assign { } { } - assign { } { } - assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50370.5-50370.29" - switch \initial - attribute \src "libresoc.v:50370.9-50370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[31:0] \data_r1__full_cr - case - assign $1\dest2_o[31:0] 0 - end - sync always - update \dest2_o $0\dest2_o[31:0] - end - attribute \src "libresoc.v:50379.3-50388.6" - process $proc$libresoc.v:50379$3278 - assign { } { } - assign { } { } - assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50380.5-50380.29" - switch \initial - attribute \src "libresoc.v:50380.9-50380.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[3:0] \data_r2__cr_a - case - assign $1\dest3_o[3:0] 4'0000 - end - sync always - update \dest3_o $0\dest3_o[3:0] - end - attribute \src "libresoc.v:50389.3-50397.6" - process $proc$libresoc.v:50389$3279 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[2:0]$3280 $1\prev_wr_go$next[2:0]$3281 - attribute \src "libresoc.v:50390.5-50390.29" - switch \initial - attribute \src "libresoc.v:50390.9-50390.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[2:0]$3281 3'000 - case - assign $1\prev_wr_go$next[2:0]$3281 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3280 - end - connect \$5 $reduce_and$libresoc.v:49915$3103_Y - connect \$99 $and$libresoc.v:49916$3104_Y - connect \$101 $and$libresoc.v:49917$3105_Y - connect \$103 $and$libresoc.v:49918$3106_Y - connect \$105 $and$libresoc.v:49919$3107_Y - connect \$107 $and$libresoc.v:49920$3108_Y - connect \$109 $and$libresoc.v:49921$3109_Y - connect \$111 $and$libresoc.v:49922$3110_Y - connect \$113 $and$libresoc.v:49923$3111_Y - connect \$115 $and$libresoc.v:49924$3112_Y - connect \$11 $and$libresoc.v:49925$3113_Y - connect \$13 $not$libresoc.v:49926$3114_Y - connect \$15 $and$libresoc.v:49927$3115_Y - connect \$17 $not$libresoc.v:49928$3116_Y - connect \$19 $and$libresoc.v:49929$3117_Y - connect \$21 $and$libresoc.v:49930$3118_Y - connect \$25 $not$libresoc.v:49931$3119_Y - connect \$27 $and$libresoc.v:49932$3120_Y - connect \$24 $reduce_or$libresoc.v:49933$3121_Y - connect \$23 $not$libresoc.v:49934$3122_Y - connect \$31 $and$libresoc.v:49935$3123_Y - connect \$33 $reduce_or$libresoc.v:49936$3124_Y - connect \$35 $reduce_or$libresoc.v:49937$3125_Y - connect \$37 $or$libresoc.v:49938$3126_Y - connect \$3 $and$libresoc.v:49939$3127_Y - connect \$39 $not$libresoc.v:49940$3128_Y - connect \$41 $and$libresoc.v:49941$3129_Y - connect \$43 $and$libresoc.v:49942$3130_Y - connect \$45 $eq$libresoc.v:49943$3131_Y - connect \$47 $and$libresoc.v:49944$3132_Y - connect \$49 $eq$libresoc.v:49945$3133_Y - connect \$51 $and$libresoc.v:49946$3134_Y - connect \$53 $and$libresoc.v:49947$3135_Y - connect \$55 $and$libresoc.v:49948$3136_Y - connect \$57 $or$libresoc.v:49949$3137_Y - connect \$59 $or$libresoc.v:49950$3138_Y - connect \$61 $or$libresoc.v:49951$3139_Y - connect \$63 $or$libresoc.v:49952$3140_Y - connect \$65 $and$libresoc.v:49953$3141_Y - connect \$67 $and$libresoc.v:49954$3142_Y - connect \$6 $not$libresoc.v:49955$3143_Y - connect \$69 $or$libresoc.v:49956$3144_Y - connect \$71 $and$libresoc.v:49957$3145_Y - connect \$73 $and$libresoc.v:49958$3146_Y - connect \$75 $and$libresoc.v:49959$3147_Y - connect \$77 $ternary$libresoc.v:49960$3148_Y - connect \$79 $ternary$libresoc.v:49961$3149_Y - connect \$81 $ternary$libresoc.v:49962$3150_Y - connect \$83 $ternary$libresoc.v:49963$3151_Y - connect \$85 $ternary$libresoc.v:49964$3152_Y - connect \$87 $ternary$libresoc.v:49965$3153_Y - connect \$8 $or$libresoc.v:49966$3154_Y - connect \$89 $and$libresoc.v:49967$3155_Y - connect \$91 $and$libresoc.v:49968$3156_Y - connect \$93 $and$libresoc.v:49969$3157_Y - connect \$95 $and$libresoc.v:49970$3158_Y - connect \$97 $not$libresoc.v:49971$3159_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$109 - connect \cu_rd__rel_o \$99 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_cr0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_cr0_p_valid_i \alui_l_q_alui - connect \alu_cr0_cr_c \$87 - connect \alu_cr0_cr_b \$85 - connect \alu_cr0_cr_a$2 \$83 - connect \alu_cr0_full_cr$1 \$81 - connect \alu_cr0_rb \$79 - connect \alu_cr0_ra \$77 - connect \cu_wrmask_o { \$75 \$73 \$71 } - connect \reset_r \$63 - connect \reset_w \$61 - connect \rst_r \$59 - connect \reset \$57 - connect \wr_any \$37 - connect \cu_done_o \$31 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$19 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_cr0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$15 - connect \all_rd_dly$next \all_rd - connect \all_rd \$11 -end -attribute \src "libresoc.v:50433.1-50482.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" -attribute \generator "nMigen" -module \cyc_l - attribute \src "libresoc.v:50434.7-50434.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:50470.3-50478.6" - wire $0\q_int$next[0:0]$3320 - attribute \src "libresoc.v:50468.3-50469.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:50470.3-50478.6" - wire $1\q_int$next[0:0]$3321 - attribute \src "libresoc.v:50452.7-50452.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:50465.17-50465.96" - wire $and$libresoc.v:50465$3315_Y - attribute \src "libresoc.v:50464.17-50464.92" - wire $not$libresoc.v:50464$3314_Y - attribute \src "libresoc.v:50467.17-50467.92" - wire $not$libresoc.v:50467$3317_Y - attribute \src "libresoc.v:50463.17-50463.98" - wire $or$libresoc.v:50463$3313_Y - attribute \src "libresoc.v:50466.17-50466.97" - wire $or$libresoc.v:50466$3316_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:50434.7-50434.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:50465$3315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:50465$3315_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:50464$3314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_cyc - connect \Y $not$libresoc.v:50464$3314_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:50467$3317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \Y $not$libresoc.v:50467$3317_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:50463$3313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \B \q_int - connect \Y $or$libresoc.v:50463$3313_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:50466$3316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_cyc - connect \Y $or$libresoc.v:50466$3316_Y - end - attribute \src "libresoc.v:50434.7-50434.20" - process $proc$libresoc.v:50434$3322 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:50452.7-50452.19" - process $proc$libresoc.v:50452$3323 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:50468.3-50469.27" - process $proc$libresoc.v:50468$3318 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:50470.3-50478.6" - process $proc$libresoc.v:50470$3319 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$3320 $1\q_int$next[0:0]$3321 - attribute \src "libresoc.v:50471.5-50471.29" - switch \initial - attribute \src "libresoc.v:50471.9-50471.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$3321 1'0 - case - assign $1\q_int$next[0:0]$3321 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$3320 - end - connect \$9 $or$libresoc.v:50463$3313_Y - connect \$1 $not$libresoc.v:50464$3314_Y - connect \$3 $and$libresoc.v:50465$3315_Y - connect \$5 $or$libresoc.v:50466$3316_Y - connect \$7 $not$libresoc.v:50467$3317_Y - connect \qlq_cyc \$9 - connect \qn_cyc \$7 - connect \q_cyc \q_int -end -attribute \src "libresoc.v:50486.1-51200.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dbg" -attribute \generator "nMigen" -module \dbg - attribute \src "libresoc.v:51016.3-51025.6" - wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:50823.3-50832.6" - wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51026.3-51035.6" - wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:50805.3-50822.6" - wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51036.3-51066.6" - wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51007.3-51015.6" - wire $0\dmi_read_log_data$next[0:0]$3437 - attribute \src "libresoc.v:50783.3-50784.51" - wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:50998.3-51006.6" - wire $0\dmi_read_log_data_1$next[0:0]$3434 - attribute \src "libresoc.v:50785.3-50786.55" - wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50833.3-50841.6" - wire $0\dmi_req_i_1$next[0:0]$3400 - attribute \src "libresoc.v:50795.3-50796.39" - wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51157.3-51190.6" - wire $0\do_dmi_log_rd$next[0:0]$3464 - attribute \src "libresoc.v:50797.3-50798.43" - wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51127.3-51156.6" - wire $0\do_icreset$next[0:0]$3457 - attribute \src "libresoc.v:50799.3-50800.37" - wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51097.3-51126.6" - wire $0\do_reset$next[0:0]$3450 - attribute \src "libresoc.v:50801.3-50802.33" - wire $0\do_reset[0:0] - attribute \src "libresoc.v:51067.3-51096.6" - wire $0\do_step$next[0:0]$3443 - attribute \src "libresoc.v:50803.3-50804.31" - wire $0\do_step[0:0] - attribute \src "libresoc.v:50936.3-50963.6" - wire width 7 $0\gspr_index$next[6:0]$3422 - attribute \src "libresoc.v:50789.3-50790.37" - wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:50487.7-50487.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:50964.3-50997.6" - wire width 32 $0\log_dmi_addr$next[31:0]$3428 - attribute \src "libresoc.v:50787.3-50788.41" - wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:50892.3-50935.6" - wire $0\stopping$next[0:0]$3413 - attribute \src "libresoc.v:50791.3-50792.33" - wire $0\stopping[0:0] - attribute \src "libresoc.v:50842.3-50891.6" - wire $0\terminated$next[0:0]$3403 - attribute \src "libresoc.v:50793.3-50794.37" - wire $0\terminated[0:0] - attribute \src "libresoc.v:51016.3-51025.6" - wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:50823.3-50832.6" - wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51026.3-51035.6" - wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:50805.3-50822.6" - wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51036.3-51066.6" - wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51007.3-51015.6" - wire $1\dmi_read_log_data$next[0:0]$3438 - attribute \src "libresoc.v:50660.7-50660.31" - wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:50998.3-51006.6" - wire $1\dmi_read_log_data_1$next[0:0]$3435 - attribute \src "libresoc.v:50664.7-50664.33" - wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:50833.3-50841.6" - wire $1\dmi_req_i_1$next[0:0]$3401 - attribute \src "libresoc.v:50670.7-50670.25" - wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51157.3-51190.6" - wire $1\do_dmi_log_rd$next[0:0]$3465 - attribute \src "libresoc.v:50676.7-50676.27" - wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51127.3-51156.6" - wire $1\do_icreset$next[0:0]$3458 - attribute \src "libresoc.v:50680.7-50680.24" - wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51097.3-51126.6" - wire $1\do_reset$next[0:0]$3451 - attribute \src "libresoc.v:50684.7-50684.22" - wire $1\do_reset[0:0] - attribute \src "libresoc.v:51067.3-51096.6" - wire $1\do_step$next[0:0]$3444 - attribute \src "libresoc.v:50688.7-50688.21" - wire $1\do_step[0:0] - attribute \src "libresoc.v:50936.3-50963.6" - wire width 7 $1\gspr_index$next[6:0]$3423 - attribute \src "libresoc.v:50692.13-50692.31" - wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:50964.3-50997.6" - wire width 32 $1\log_dmi_addr$next[31:0]$3429 - attribute \src "libresoc.v:50698.14-50698.34" - wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:50892.3-50935.6" - wire $1\stopping$next[0:0]$3414 - attribute \src "libresoc.v:50710.7-50710.22" - wire $1\stopping[0:0] - attribute \src "libresoc.v:50842.3-50891.6" - wire $1\terminated$next[0:0]$3404 - attribute \src "libresoc.v:50716.7-50716.24" - wire $1\terminated[0:0] - attribute \src "libresoc.v:51157.3-51190.6" - wire $2\do_dmi_log_rd$next[0:0]$3466 - attribute \src "libresoc.v:51127.3-51156.6" - wire $2\do_icreset$next[0:0]$3459 - attribute \src "libresoc.v:51097.3-51126.6" - wire $2\do_reset$next[0:0]$3452 - attribute \src "libresoc.v:51067.3-51096.6" - wire $2\do_step$next[0:0]$3445 - attribute \src "libresoc.v:50936.3-50963.6" - wire width 7 $2\gspr_index$next[6:0]$3424 - attribute \src "libresoc.v:50964.3-50997.6" - wire width 32 $2\log_dmi_addr$next[31:0]$3430 - attribute \src "libresoc.v:50892.3-50935.6" - wire $2\stopping$next[0:0]$3415 - attribute \src "libresoc.v:50842.3-50891.6" - wire $2\terminated$next[0:0]$3405 - attribute \src "libresoc.v:51157.3-51190.6" - wire $3\do_dmi_log_rd$next[0:0]$3467 - attribute \src "libresoc.v:51127.3-51156.6" - wire $3\do_icreset$next[0:0]$3460 - attribute \src "libresoc.v:51097.3-51126.6" - wire $3\do_reset$next[0:0]$3453 - attribute \src "libresoc.v:51067.3-51096.6" - wire $3\do_step$next[0:0]$3446 - attribute \src "libresoc.v:50936.3-50963.6" - wire width 7 $3\gspr_index$next[6:0]$3425 - attribute \src "libresoc.v:50964.3-50997.6" - wire width 32 $3\log_dmi_addr$next[31:0]$3431 - attribute \src "libresoc.v:50892.3-50935.6" - wire $3\stopping$next[0:0]$3416 - attribute \src "libresoc.v:50842.3-50891.6" - wire $3\terminated$next[0:0]$3406 - attribute \src "libresoc.v:51157.3-51190.6" - wire $4\do_dmi_log_rd$next[0:0]$3468 - attribute \src "libresoc.v:51127.3-51156.6" - wire $4\do_icreset$next[0:0]$3461 - attribute \src "libresoc.v:51097.3-51126.6" - wire $4\do_reset$next[0:0]$3454 - attribute \src "libresoc.v:51067.3-51096.6" - wire $4\do_step$next[0:0]$3447 - attribute \src "libresoc.v:50936.3-50963.6" - wire width 7 $4\gspr_index$next[6:0]$3426 - attribute \src "libresoc.v:50964.3-50997.6" - wire width 32 $4\log_dmi_addr$next[31:0]$3432 - attribute \src "libresoc.v:50892.3-50935.6" - wire $4\stopping$next[0:0]$3417 - attribute \src "libresoc.v:50842.3-50891.6" - wire $4\terminated$next[0:0]$3407 - attribute \src "libresoc.v:51127.3-51156.6" - wire $5\do_icreset$next[0:0]$3462 - attribute \src "libresoc.v:51097.3-51126.6" - wire $5\do_reset$next[0:0]$3455 - attribute \src "libresoc.v:51067.3-51096.6" - wire $5\do_step$next[0:0]$3448 - attribute \src "libresoc.v:50892.3-50935.6" - wire $5\stopping$next[0:0]$3418 - attribute \src "libresoc.v:50842.3-50891.6" - wire $5\terminated$next[0:0]$3408 - attribute \src "libresoc.v:50892.3-50935.6" - wire $6\stopping$next[0:0]$3419 - attribute \src "libresoc.v:50842.3-50891.6" - wire $6\terminated$next[0:0]$3409 - attribute \src "libresoc.v:50892.3-50935.6" - wire $7\stopping$next[0:0]$3420 - attribute \src "libresoc.v:50842.3-50891.6" - wire $7\terminated$next[0:0]$3410 - attribute \src "libresoc.v:50842.3-50891.6" - wire $8\terminated$next[0:0]$3411 - attribute \src "libresoc.v:50730.19-50730.110" - wire width 3 $add$libresoc.v:50730$3333_Y - attribute \src "libresoc.v:50721.17-50721.109" - wire $and$libresoc.v:50721$3324_Y - attribute \src "libresoc.v:50724.19-50724.103" - wire $and$libresoc.v:50724$3327_Y - attribute \src "libresoc.v:50726.19-50726.113" - wire $and$libresoc.v:50726$3329_Y - attribute \src "libresoc.v:50733.19-50733.103" - wire $and$libresoc.v:50733$3336_Y - attribute \src "libresoc.v:50735.19-50735.102" - wire $and$libresoc.v:50735$3338_Y - attribute \src "libresoc.v:50740.18-50740.101" - wire $and$libresoc.v:50740$3343_Y - attribute \src "libresoc.v:50742.18-50742.111" - wire $and$libresoc.v:50742$3345_Y - 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$eq$libresoc.v:50722$3325_Y - attribute \src "libresoc.v:50727.19-50727.104" - wire $eq$libresoc.v:50727$3330_Y - attribute \src "libresoc.v:50728.19-50728.104" - wire $eq$libresoc.v:50728$3331_Y - attribute \src "libresoc.v:50729.19-50729.104" - wire $eq$libresoc.v:50729$3332_Y - attribute \src "libresoc.v:50731.19-50731.104" - wire $eq$libresoc.v:50731$3334_Y - attribute \src "libresoc.v:50732.18-50732.103" - wire $eq$libresoc.v:50732$3335_Y - attribute \src "libresoc.v:50736.18-50736.103" - wire $eq$libresoc.v:50736$3339_Y - attribute \src "libresoc.v:50737.18-50737.103" - wire $eq$libresoc.v:50737$3340_Y - attribute \src "libresoc.v:50743.18-50743.103" - wire $eq$libresoc.v:50743$3346_Y - attribute \src "libresoc.v:50744.18-50744.103" - wire $eq$libresoc.v:50744$3347_Y - attribute \src "libresoc.v:50745.18-50745.103" - wire $eq$libresoc.v:50745$3348_Y - attribute \src "libresoc.v:50751.18-50751.103" - wire $eq$libresoc.v:50751$3354_Y - attribute \src "libresoc.v:50752.18-50752.103" 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 24 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 11 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 10 \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" - wire output 8 \core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" - wire output 12 \core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" - wire input 13 \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 20 \d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 19 \d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 18 \d_cr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 17 \d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" - wire width 7 output 15 \d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 16 \d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 14 \d_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire input 23 \d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 input 22 \d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire output 21 \d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire output 6 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 input 2 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 input 5 \dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 output 7 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" - wire \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" - wire \dmi_read_log_data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" - wire \dmi_read_log_data_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" - wire \dmi_read_log_data_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire input 3 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire \dmi_req_i_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire \dmi_req_i_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire input 4 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - wire \do_dmi_log_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - wire \do_dmi_log_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire \do_icreset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire \do_icreset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire \do_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire \do_reset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" - wire \do_step - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" - wire \do_step$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" - wire width 7 \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" - wire width 7 \gspr_index$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" - wire \icache_rst_o - attribute \src "libresoc.v:50487.7-50487.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145" - wire width 32 \log_dmi_addr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - wire width 64 \log_dmi_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:119" - wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:134" - wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" - wire input 9 \terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122" - wire \terminated_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $add $add$libresoc.v:50730$3333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \log_dmi_addr [1:0] - connect \B 1'1 - connect \Y $add$libresoc.v:50730$3333_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50721$3324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$7 - connect \Y $and$libresoc.v:50721$3324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - cell $and $and$libresoc.v:50724$3327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$101 - connect \Y $and$libresoc.v:50724$3327_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $and$libresoc.v:50726$3329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B \$105 - connect \Y $and$libresoc.v:50726$3329_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" - cell $and $and$libresoc.v:50733$3336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B \$118 - connect \Y $and$libresoc.v:50733$3336_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" - cell $and $and$libresoc.v:50735$3338 - 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sync always - sync init - update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] - end - attribute \src "libresoc.v:50670.7-50670.25" - process $proc$libresoc.v:50670$3472 - assign { } { } - assign $1\dmi_req_i_1[0:0] 1'0 - sync always - sync init - update \dmi_req_i_1 $1\dmi_req_i_1[0:0] - end - attribute \src "libresoc.v:50676.7-50676.27" - process $proc$libresoc.v:50676$3473 - assign { } { } - assign $1\do_dmi_log_rd[0:0] 1'0 - sync always - sync init - update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] - end - attribute \src "libresoc.v:50680.7-50680.24" - process $proc$libresoc.v:50680$3474 - assign { } { } - assign $1\do_icreset[0:0] 1'0 - sync always - sync init - update \do_icreset $1\do_icreset[0:0] - end - attribute \src "libresoc.v:50684.7-50684.22" - process $proc$libresoc.v:50684$3475 - assign { } { } - assign $1\do_reset[0:0] 1'0 - sync always - sync init - update \do_reset $1\do_reset[0:0] - end - attribute \src "libresoc.v:50688.7-50688.21" - process $proc$libresoc.v:50688$3476 - assign { } { } - assign $1\do_step[0:0] 1'0 - sync always - sync init - update \do_step $1\do_step[0:0] - end - attribute \src "libresoc.v:50692.13-50692.31" - process $proc$libresoc.v:50692$3477 - assign { } { } - assign $1\gspr_index[6:0] 7'0000000 - sync always - sync init - update \gspr_index $1\gspr_index[6:0] - end - attribute \src "libresoc.v:50698.14-50698.34" - process $proc$libresoc.v:50698$3478 - assign { } { } - assign $1\log_dmi_addr[31:0] 0 - sync always - sync init - update \log_dmi_addr $1\log_dmi_addr[31:0] - end - attribute \src "libresoc.v:50710.7-50710.22" - process $proc$libresoc.v:50710$3479 - assign { } { } - assign $1\stopping[0:0] 1'0 - sync always - sync init - update \stopping $1\stopping[0:0] - end - attribute \src "libresoc.v:50716.7-50716.24" - process $proc$libresoc.v:50716$3480 - assign { } { } - assign $1\terminated[0:0] 1'0 - sync always - sync init - update \terminated $1\terminated[0:0] - end - attribute \src "libresoc.v:50783.3-50784.51" - process $proc$libresoc.v:50783$3386 - assign { } { } - assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next - sync posedge \clk - update \dmi_read_log_data $0\dmi_read_log_data[0:0] - end - attribute \src "libresoc.v:50785.3-50786.55" - process $proc$libresoc.v:50785$3387 - assign { } { } - assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next - sync posedge \clk - update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] - end - attribute \src "libresoc.v:50787.3-50788.41" - process $proc$libresoc.v:50787$3388 - assign { } { } - assign $0\log_dmi_addr[31:0] \log_dmi_addr$next - sync posedge \clk - update \log_dmi_addr $0\log_dmi_addr[31:0] - end - attribute \src "libresoc.v:50789.3-50790.37" - process $proc$libresoc.v:50789$3389 - assign { } { } - assign $0\gspr_index[6:0] \gspr_index$next - sync posedge \clk - update \gspr_index $0\gspr_index[6:0] - end - attribute \src "libresoc.v:50791.3-50792.33" - process $proc$libresoc.v:50791$3390 - assign { } { } - assign $0\stopping[0:0] \stopping$next - sync posedge \clk - update \stopping $0\stopping[0:0] - end - attribute \src "libresoc.v:50793.3-50794.37" - process $proc$libresoc.v:50793$3391 - assign { } { } - assign $0\terminated[0:0] \terminated$next - sync posedge \clk - update \terminated $0\terminated[0:0] - end - attribute \src "libresoc.v:50795.3-50796.39" - process $proc$libresoc.v:50795$3392 - assign { } { } - assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next - sync posedge \clk - update \dmi_req_i_1 $0\dmi_req_i_1[0:0] - end - attribute \src "libresoc.v:50797.3-50798.43" - process $proc$libresoc.v:50797$3393 - assign { } { } - assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next - sync posedge \clk - update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] - end - attribute \src "libresoc.v:50799.3-50800.37" - process $proc$libresoc.v:50799$3394 - assign { } { } - assign $0\do_icreset[0:0] \do_icreset$next - sync posedge \clk - update \do_icreset $0\do_icreset[0:0] - end - attribute \src "libresoc.v:50801.3-50802.33" - process $proc$libresoc.v:50801$3395 - assign { } { } - assign $0\do_reset[0:0] \do_reset$next - sync posedge \clk - update \do_reset $0\do_reset[0:0] - end - attribute \src "libresoc.v:50803.3-50804.31" - process $proc$libresoc.v:50803$3396 - assign { } { } - assign $0\do_step[0:0] \do_step$next - sync posedge \clk - update \do_step $0\do_step[0:0] - end - attribute \src "libresoc.v:50805.3-50822.6" - process $proc$libresoc.v:50805$3397 - assign { } { } - assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:50806.5-50806.29" - switch \initial - attribute \src "libresoc.v:50806.9-50806.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_gpr_ack - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_cr_ack - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dmi_ack_o[0:0] \d_xer_ack - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi_ack_o[0:0] \dmi_req_i - end - sync always - update \dmi_ack_o $0\dmi_ack_o[0:0] - end - attribute \src "libresoc.v:50823.3-50832.6" - process $proc$libresoc.v:50823$3398 - assign { } { } - assign { } { } - assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:50824.5-50824.29" - switch \initial - attribute \src "libresoc.v:50824.9-50824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\d_gpr_req[0:0] \dmi_req_i - case - assign $1\d_gpr_req[0:0] 1'0 - end - sync always - update \d_gpr_req $0\d_gpr_req[0:0] - end - attribute \src "libresoc.v:50833.3-50841.6" - process $proc$libresoc.v:50833$3399 - assign { } { } - assign { } { } - assign $0\dmi_req_i_1$next[0:0]$3400 $1\dmi_req_i_1$next[0:0]$3401 - attribute \src "libresoc.v:50834.5-50834.29" - switch \initial - attribute \src "libresoc.v:50834.9-50834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_req_i_1$next[0:0]$3401 1'0 - case - assign $1\dmi_req_i_1$next[0:0]$3401 \dmi_req_i - end - sync always - update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3400 - end - attribute \src "libresoc.v:50842.3-50891.6" - process $proc$libresoc.v:50842$3402 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\terminated$next[0:0]$3403 $8\terminated$next[0:0]$3411 - attribute \src "libresoc.v:50843.5-50843.29" - switch \initial - attribute \src "libresoc.v:50843.9-50843.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$65 \$61 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\terminated$next[0:0]$3404 $2\terminated$next[0:0]$3405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\terminated$next[0:0]$3405 $3\terminated$next[0:0]$3406 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$71 \$69 \$67 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign { } { } - assign $3\terminated$next[0:0]$3406 $6\terminated$next[0:0]$3409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch \dmi_din [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\terminated$next[0:0]$3407 1'0 - case - assign $4\terminated$next[0:0]$3407 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" - switch \dmi_din [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\terminated$next[0:0]$3408 1'0 - case - assign $5\terminated$next[0:0]$3408 $4\terminated$next[0:0]$3407 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - switch \dmi_din [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\terminated$next[0:0]$3409 1'0 - case - assign $6\terminated$next[0:0]$3409 $5\terminated$next[0:0]$3408 - end - case - assign $3\terminated$next[0:0]$3406 \terminated - end - case - assign $2\terminated$next[0:0]$3405 \terminated - end - case - assign $1\terminated$next[0:0]$3404 \terminated - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" - switch \terminate_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\terminated$next[0:0]$3410 1'1 - case - assign $7\terminated$next[0:0]$3410 $1\terminated$next[0:0]$3404 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\terminated$next[0:0]$3411 1'0 - case - assign $8\terminated$next[0:0]$3411 $7\terminated$next[0:0]$3410 - end - sync always - update \terminated$next $0\terminated$next[0:0]$3403 - end - attribute \src "libresoc.v:50892.3-50935.6" - process $proc$libresoc.v:50892$3412 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\stopping$next[0:0]$3413 $7\stopping$next[0:0]$3420 - attribute \src "libresoc.v:50893.5-50893.29" - switch \initial - attribute \src "libresoc.v:50893.9-50893.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$79 \$75 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\stopping$next[0:0]$3414 $2\stopping$next[0:0]$3415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\stopping$next[0:0]$3415 $3\stopping$next[0:0]$3416 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$85 \$83 \$81 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign { } { } - assign $3\stopping$next[0:0]$3416 $5\stopping$next[0:0]$3418 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" - switch \dmi_din [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\stopping$next[0:0]$3417 1'1 - case - assign $4\stopping$next[0:0]$3417 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" - switch \dmi_din [4] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\stopping$next[0:0]$3418 1'0 - case - assign $5\stopping$next[0:0]$3418 $4\stopping$next[0:0]$3417 - end - case - assign $3\stopping$next[0:0]$3416 \stopping - end - case - assign $2\stopping$next[0:0]$3415 \stopping - end - case - assign $1\stopping$next[0:0]$3414 \stopping - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" - switch \terminate_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\stopping$next[0:0]$3419 1'1 - case - assign $6\stopping$next[0:0]$3419 $1\stopping$next[0:0]$3414 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\stopping$next[0:0]$3420 1'0 - case - assign $7\stopping$next[0:0]$3420 $6\stopping$next[0:0]$3419 - end - sync always - update \stopping$next $0\stopping$next[0:0]$3413 - end - attribute \src "libresoc.v:50936.3-50963.6" - process $proc$libresoc.v:50936$3421 - assign { } { } - assign { } { } - assign { } { } - assign $0\gspr_index$next[6:0]$3422 $4\gspr_index$next[6:0]$3426 - attribute \src "libresoc.v:50937.5-50937.29" - switch \initial - attribute \src "libresoc.v:50937.9-50937.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$93 \$89 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\gspr_index$next[6:0]$3423 $2\gspr_index$next[6:0]$3424 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\gspr_index$next[6:0]$3424 $3\gspr_index$next[6:0]$3425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$99 \$97 \$95 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\gspr_index$next[6:0]$3425 \gspr_index - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $3\gspr_index$next[6:0]$3425 \dmi_din [6:0] - case - assign $3\gspr_index$next[6:0]$3425 \gspr_index - end - case - assign $2\gspr_index$next[6:0]$3424 \gspr_index - end - case - assign $1\gspr_index$next[6:0]$3423 \gspr_index - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\gspr_index$next[6:0]$3426 7'0000000 - case - assign $4\gspr_index$next[6:0]$3426 $1\gspr_index$next[6:0]$3423 - end - sync always - update \gspr_index$next $0\gspr_index$next[6:0]$3422 - end - attribute \src "libresoc.v:50964.3-50997.6" - process $proc$libresoc.v:50964$3427 - assign { } { } - assign { } { } - assign { } { } - assign $0\log_dmi_addr$next[31:0]$3428 $4\log_dmi_addr$next[31:0]$3432 - attribute \src "libresoc.v:50965.5-50965.29" - switch \initial - attribute \src "libresoc.v:50965.9-50965.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$107 \$103 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\log_dmi_addr$next[31:0]$3429 $2\log_dmi_addr$next[31:0]$3430 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\log_dmi_addr$next[31:0]$3430 $3\log_dmi_addr$next[31:0]$3431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$113 \$111 \$109 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\log_dmi_addr$next[31:0]$3431 \log_dmi_addr - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $3\log_dmi_addr$next[31:0]$3431 \log_dmi_addr - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\log_dmi_addr$next[31:0]$3431 \dmi_din [31:0] - case - assign $3\log_dmi_addr$next[31:0]$3431 \log_dmi_addr - end - case - assign $2\log_dmi_addr$next[31:0]$3430 \log_dmi_addr - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign $1\log_dmi_addr$next[31:0]$3429 [31:2] \log_dmi_addr [31:2] - assign $1\log_dmi_addr$next[31:0]$3429 [1:0] \$115 [1:0] - case - assign $1\log_dmi_addr$next[31:0]$3429 \log_dmi_addr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\log_dmi_addr$next[31:0]$3432 0 - case - assign $4\log_dmi_addr$next[31:0]$3432 $1\log_dmi_addr$next[31:0]$3429 - end - sync always - update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3428 - end - attribute \src "libresoc.v:50998.3-51006.6" - process $proc$libresoc.v:50998$3433 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data_1$next[0:0]$3434 $1\dmi_read_log_data_1$next[0:0]$3435 - attribute \src "libresoc.v:50999.5-50999.29" - switch \initial - attribute \src "libresoc.v:50999.9-50999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_read_log_data_1$next[0:0]$3435 1'0 - case - assign $1\dmi_read_log_data_1$next[0:0]$3435 \dmi_read_log_data - end - sync always - update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3434 - end - attribute \src "libresoc.v:51007.3-51015.6" - process $proc$libresoc.v:51007$3436 - assign { } { } - assign { } { } - assign $0\dmi_read_log_data$next[0:0]$3437 $1\dmi_read_log_data$next[0:0]$3438 - attribute \src "libresoc.v:51008.5-51008.29" - switch \initial - attribute \src "libresoc.v:51008.9-51008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi_read_log_data$next[0:0]$3438 1'0 - case - assign $1\dmi_read_log_data$next[0:0]$3438 \$120 - end - sync always - update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3437 - end - attribute \src "libresoc.v:51016.3-51025.6" - process $proc$libresoc.v:51016$3439 - assign { } { } - assign { } { } - assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51017.5-51017.29" - switch \initial - attribute \src "libresoc.v:51017.9-51017.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\d_cr_req[0:0] \dmi_req_i - case - assign $1\d_cr_req[0:0] 1'0 - end - sync always - update \d_cr_req $0\d_cr_req[0:0] - end - attribute \src "libresoc.v:51026.3-51035.6" - process $proc$libresoc.v:51026$3440 - assign { } { } - assign { } { } - assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51027.5-51027.29" - switch \initial - attribute \src "libresoc.v:51027.9-51027.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\d_xer_req[0:0] \dmi_req_i - case - assign $1\d_xer_req[0:0] 1'0 - end - sync always - update \d_xer_req $0\d_xer_req[0:0] - end - attribute \src "libresoc.v:51036.3-51066.6" - process $proc$libresoc.v:51036$3441 - assign { } { } - assign { } { } - assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51037.5-51037.29" - switch \initial - attribute \src "libresoc.v:51037.9-51037.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" - switch \dmi_addr_i - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dmi_dout[63:0] \stat_reg - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_pc - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dmi_dout[63:0] \core_dbg_msr - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dmi_dout[63:0] \d_gpr_data - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dmi_dout[63:0] \log_dmi_data - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dmi_dout[63:0] \d_cr_data - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dmi_dout[63:0] \d_xer_data - case - assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi_dout $0\dmi_dout[63:0] - end - attribute \src "libresoc.v:51067.3-51096.6" - process $proc$libresoc.v:51067$3442 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_step$next[0:0]$3443 $5\do_step$next[0:0]$3448 - attribute \src "libresoc.v:51068.5-51068.29" - switch \initial - attribute \src "libresoc.v:51068.9-51068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$9 \$5 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_step$next[0:0]$3444 $2\do_step$next[0:0]$3445 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_step$next[0:0]$3445 $3\do_step$next[0:0]$3446 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$15 \$13 \$11 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_step$next[0:0]$3446 $4\do_step$next[0:0]$3447 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" - switch \dmi_din [3] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_step$next[0:0]$3447 1'1 - case - assign $4\do_step$next[0:0]$3447 1'0 - end - case - assign $3\do_step$next[0:0]$3446 1'0 - end - case - assign $2\do_step$next[0:0]$3445 1'0 - end - case - assign $1\do_step$next[0:0]$3444 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_step$next[0:0]$3448 1'0 - case - assign $5\do_step$next[0:0]$3448 $1\do_step$next[0:0]$3444 - end - sync always - update \do_step$next $0\do_step$next[0:0]$3443 - end - attribute \src "libresoc.v:51097.3-51126.6" - process $proc$libresoc.v:51097$3449 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_reset$next[0:0]$3450 $5\do_reset$next[0:0]$3455 - attribute \src "libresoc.v:51098.5-51098.29" - switch \initial - attribute \src "libresoc.v:51098.9-51098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$23 \$19 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_reset$next[0:0]$3451 $2\do_reset$next[0:0]$3452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_reset$next[0:0]$3452 $3\do_reset$next[0:0]$3453 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$29 \$27 \$25 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_reset$next[0:0]$3453 $4\do_reset$next[0:0]$3454 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch \dmi_din [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_reset$next[0:0]$3454 1'1 - case - assign $4\do_reset$next[0:0]$3454 1'0 - end - case - assign $3\do_reset$next[0:0]$3453 1'0 - end - case - assign $2\do_reset$next[0:0]$3452 1'0 - end - case - assign $1\do_reset$next[0:0]$3451 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_reset$next[0:0]$3455 1'0 - case - assign $5\do_reset$next[0:0]$3455 $1\do_reset$next[0:0]$3451 - end - sync always - update \do_reset$next $0\do_reset$next[0:0]$3450 - end - attribute \src "libresoc.v:51127.3-51156.6" - process $proc$libresoc.v:51127$3456 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_icreset$next[0:0]$3457 $5\do_icreset$next[0:0]$3462 - attribute \src "libresoc.v:51128.5-51128.29" - switch \initial - attribute \src "libresoc.v:51128.9-51128.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$37 \$33 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_icreset$next[0:0]$3458 $2\do_icreset$next[0:0]$3459 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_icreset$next[0:0]$3459 $3\do_icreset$next[0:0]$3460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$43 \$41 \$39 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $3\do_icreset$next[0:0]$3460 $4\do_icreset$next[0:0]$3461 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" - switch \dmi_din [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_icreset$next[0:0]$3461 1'1 - case - assign $4\do_icreset$next[0:0]$3461 1'0 - end - case - assign $3\do_icreset$next[0:0]$3460 1'0 - end - case - assign $2\do_icreset$next[0:0]$3459 1'0 - end - case - assign $1\do_icreset$next[0:0]$3458 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\do_icreset$next[0:0]$3462 1'0 - case - assign $5\do_icreset$next[0:0]$3462 $1\do_icreset$next[0:0]$3458 - end - sync always - update \do_icreset$next $0\do_icreset$next[0:0]$3457 - end - attribute \src "libresoc.v:51157.3-51190.6" - process $proc$libresoc.v:51157$3463 - assign { } { } - assign { } { } - assign { } { } - assign $0\do_dmi_log_rd$next[0:0]$3464 $4\do_dmi_log_rd$next[0:0]$3468 - attribute \src "libresoc.v:51158.5-51158.29" - switch \initial - attribute \src "libresoc.v:51158.9-51158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \$51 \$47 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3465 $2\do_dmi_log_rd$next[0:0]$3466 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" - switch \dmi_we_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\do_dmi_log_rd$next[0:0]$3466 $3\do_dmi_log_rd$next[0:0]$3467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" - switch { \$57 \$55 \$53 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $3\do_dmi_log_rd$next[0:0]$3467 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $3\do_dmi_log_rd$next[0:0]$3467 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $3\do_dmi_log_rd$next[0:0]$3467 1'1 - case - assign $3\do_dmi_log_rd$next[0:0]$3467 1'0 - end - case - assign $2\do_dmi_log_rd$next[0:0]$3466 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\do_dmi_log_rd$next[0:0]$3465 1'1 - case - assign $1\do_dmi_log_rd$next[0:0]$3465 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\do_dmi_log_rd$next[0:0]$3468 1'0 - case - assign $4\do_dmi_log_rd$next[0:0]$3468 $1\do_dmi_log_rd$next[0:0]$3465 - end - sync always - update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3464 - end - connect \$9 $and$libresoc.v:50721$3324_Y - connect \$99 $eq$libresoc.v:50722$3325_Y - connect \$101 $not$libresoc.v:50723$3326_Y - connect \$103 $and$libresoc.v:50724$3327_Y - connect \$105 $not$libresoc.v:50725$3328_Y - connect \$107 $and$libresoc.v:50726$3329_Y - connect \$109 $eq$libresoc.v:50727$3330_Y - connect \$111 $eq$libresoc.v:50728$3331_Y - connect \$113 $eq$libresoc.v:50729$3332_Y - connect \$116 $add$libresoc.v:50730$3333_Y - connect \$118 $eq$libresoc.v:50731$3334_Y - connect \$11 $eq$libresoc.v:50732$3335_Y - connect \$120 $and$libresoc.v:50733$3336_Y - connect \$122 $not$libresoc.v:50734$3337_Y - connect \$124 $and$libresoc.v:50735$3338_Y - connect \$13 $eq$libresoc.v:50736$3339_Y - connect \$15 $eq$libresoc.v:50737$3340_Y - connect \$17 $not$libresoc.v:50738$3341_Y - connect \$1 $pos$libresoc.v:50739$3342_Y - connect \$19 $and$libresoc.v:50740$3343_Y - connect \$21 $not$libresoc.v:50741$3344_Y - connect \$23 $and$libresoc.v:50742$3345_Y - connect \$25 $eq$libresoc.v:50743$3346_Y - connect \$27 $eq$libresoc.v:50744$3347_Y - connect \$29 $eq$libresoc.v:50745$3348_Y - connect \$31 $not$libresoc.v:50746$3349_Y - connect \$33 $and$libresoc.v:50747$3350_Y - connect \$35 $not$libresoc.v:50748$3351_Y - connect \$37 $and$libresoc.v:50749$3352_Y - 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connect \$79 $and$libresoc.v:50773$3376_Y - connect \$81 $eq$libresoc.v:50774$3377_Y - connect \$83 $eq$libresoc.v:50775$3378_Y - connect \$85 $eq$libresoc.v:50776$3379_Y - connect \$87 $not$libresoc.v:50777$3380_Y - connect \$89 $and$libresoc.v:50778$3381_Y - connect \$91 $not$libresoc.v:50779$3382_Y - connect \$93 $and$libresoc.v:50780$3383_Y - connect \$95 $eq$libresoc.v:50781$3384_Y - connect \$97 $eq$libresoc.v:50782$3385_Y - connect \$115 \$116 - connect \log_write_addr_o 0 - connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \terminated_o \terminated - connect \icache_rst_o \do_icreset - connect \core_rst_o \do_reset - connect \core_stop_o \$124 - connect \d_gpr_addr \gspr_index - connect \stat_reg \$1 -end -attribute \src "libresoc.v:51204.1-53219.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" -attribute \generator "nMigen" -module \dec - attribute \src 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$0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52617.3-52650.6" - wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51205.7-51205.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:52787.3-52820.6" - wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:52821.3-52854.6" - wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52447.3-52480.6" - wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52549.3-52582.6" - wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:52651.3-52684.6" - wire width 12 $1\ALU_function_unit[11:0] - attribute \src "libresoc.v:52719.3-52752.6" - wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52753.3-52786.6" - wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52685.3-52718.6" - wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52481.3-52514.6" - wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52515.3-52548.6" - wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52583.3-52616.6" - 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\enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \ALU_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 10 \ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 3 \ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 output 21 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_me - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L3 - attribute \src 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\raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:52378$3481_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:52379.13-52395.4" - cell \ALU_dec19 \ALU_dec19 - connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in - connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out - connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in - connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out - connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit - connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel - connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel - connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op - connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a - connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out - connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b - connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len - connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel - connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn - connect \opcode_in \ALU_dec19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:52396.13-52412.4" - cell \ALU_dec31 \ALU_dec31 - connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in - connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out - connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in - connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out - connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit - connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel - connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel - connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op - connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a - connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out - connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b - connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len - connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel - connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn - connect \opcode_in \ALU_dec31_opcode_in - end - attribute \src "libresoc.v:51205.7-51205.20" - process $proc$libresoc.v:51205$3496 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:52413.3-52446.6" - process $proc$libresoc.v:52413$3482 - assign { } { } - assign { } { } - assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52414.5-52414.29" - switch \initial - attribute \src "libresoc.v:52414.9-52414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_rc_sel[1:0] 2'00 - case - assign $1\ALU_rc_sel[1:0] 2'00 - end - sync always - update \ALU_rc_sel $0\ALU_rc_sel[1:0] - end - attribute \src "libresoc.v:52447.3-52480.6" - process $proc$libresoc.v:52447$3483 - assign { } { } - assign { } { } - assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:52448.5-52448.29" - switch \initial - attribute \src "libresoc.v:52448.9-52448.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cry_in[1:0] 2'01 - case - assign $1\ALU_cry_in[1:0] 2'00 - end - sync always - update \ALU_cry_in $0\ALU_cry_in[1:0] - end - attribute \src "libresoc.v:52481.3-52514.6" - process $proc$libresoc.v:52481$3484 - assign { } { } - assign { } { } - assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:52482.5-52482.29" - switch \initial - attribute \src "libresoc.v:52482.9-52482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_inv_a[0:0] 1'1 - case - assign $1\ALU_inv_a[0:0] 1'0 - end - sync always - update \ALU_inv_a $0\ALU_inv_a[0:0] - end - attribute \src "libresoc.v:52515.3-52548.6" - process $proc$libresoc.v:52515$3485 - assign { } { } - assign { } { } - assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:52516.5-52516.29" - switch \initial - attribute \src "libresoc.v:52516.9-52516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_inv_out[0:0] 1'0 - case - assign $1\ALU_inv_out[0:0] 1'0 - end - sync always - update \ALU_inv_out $0\ALU_inv_out[0:0] - end - attribute \src "libresoc.v:52549.3-52582.6" - process $proc$libresoc.v:52549$3486 - assign { } { } - assign { } { } - assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:52550.5-52550.29" - switch \initial - attribute \src "libresoc.v:52550.9-52550.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cry_out[0:0] 1'1 - case - assign $1\ALU_cry_out[0:0] 1'0 - end - sync always - update \ALU_cry_out $0\ALU_cry_out[0:0] - end - attribute \src "libresoc.v:52583.3-52616.6" - process $proc$libresoc.v:52583$3487 - assign { } { } - assign { } { } - assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:52584.5-52584.29" - switch \initial - attribute \src "libresoc.v:52584.9-52584.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_is_32b[0:0] 1'0 - case - assign $1\ALU_is_32b[0:0] 1'0 - end - sync always - update \ALU_is_32b $0\ALU_is_32b[0:0] - end - attribute \src "libresoc.v:52617.3-52650.6" - process $proc$libresoc.v:52617$3488 - assign { } { } - assign { } { } - assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52618.5-52618.29" - switch \initial - attribute \src "libresoc.v:52618.9-52618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_sgn[0:0] 1'0 - case - assign $1\ALU_sgn[0:0] 1'0 - end - sync always - update \ALU_sgn $0\ALU_sgn[0:0] - end - attribute \src "libresoc.v:52651.3-52684.6" - process $proc$libresoc.v:52651$3489 - assign { } { } - assign { } { } - assign $0\ALU_function_unit[11:0] $1\ALU_function_unit[11:0] - attribute \src "libresoc.v:52652.5-52652.29" - switch \initial - attribute \src "libresoc.v:52652.9-52652.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_function_unit[11:0] \ALU_dec19_ALU_dec19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_function_unit[11:0] \ALU_dec31_ALU_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_function_unit[11:0] 12'000000000010 - case - assign $1\ALU_function_unit[11:0] 12'000000000000 - end - sync always - update \ALU_function_unit $0\ALU_function_unit[11:0] - end - attribute \src "libresoc.v:52685.3-52718.6" - process $proc$libresoc.v:52685$3490 - assign { } { } - assign { } { } - assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:52686.5-52686.29" - switch \initial - attribute \src "libresoc.v:52686.9-52686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_internal_op[6:0] 7'0000010 - case - assign $1\ALU_internal_op[6:0] 7'0000000 - end - sync always - update \ALU_internal_op $0\ALU_internal_op[6:0] - end - attribute \src "libresoc.v:52719.3-52752.6" - process $proc$libresoc.v:52719$3491 - assign { } { } - assign { } { } - assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:52720.5-52720.29" - switch \initial - attribute \src "libresoc.v:52720.9-52720.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_in1_sel[2:0] 3'001 - case - assign $1\ALU_in1_sel[2:0] 3'000 - end - sync always - update \ALU_in1_sel $0\ALU_in1_sel[2:0] - end - attribute \src "libresoc.v:52753.3-52786.6" - process $proc$libresoc.v:52753$3492 - assign { } { } - assign { } { } - assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:52754.5-52754.29" - switch \initial - attribute \src "libresoc.v:52754.9-52754.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_in2_sel[3:0] 4'0011 - case - assign $1\ALU_in2_sel[3:0] 4'0000 - end - sync always - update \ALU_in2_sel $0\ALU_in2_sel[3:0] - end - attribute \src "libresoc.v:52787.3-52820.6" - process $proc$libresoc.v:52787$3493 - assign { } { } - assign { } { } - assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:52788.5-52788.29" - switch \initial - attribute \src "libresoc.v:52788.9-52788.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cr_in[2:0] 3'000 - case - assign $1\ALU_cr_in[2:0] 3'000 - end - sync always - update \ALU_cr_in $0\ALU_cr_in[2:0] - end - attribute \src "libresoc.v:52821.3-52854.6" - process $proc$libresoc.v:52821$3494 - assign { } { } - assign { } { } - assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:52822.5-52822.29" - switch \initial - attribute \src "libresoc.v:52822.9-52822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_cr_out[2:0] 3'000 - case - assign $1\ALU_cr_out[2:0] 3'000 - end - sync always - update \ALU_cr_out $0\ALU_cr_out[2:0] - end - attribute \src "libresoc.v:52855.3-52888.6" - process $proc$libresoc.v:52855$3495 - assign { } { } - assign { } { } - assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52856.5-52856.29" - switch \initial - attribute \src "libresoc.v:52856.9-52856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ALU_ldst_len[3:0] 4'0000 - case - assign $1\ALU_ldst_len[3:0] 4'0000 - end - sync always - update \ALU_ldst_len $0\ALU_ldst_len[3:0] - end - connect \$1 $ternary$libresoc.v:52378$3481_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 18 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "libresoc.v:53224.7-53224.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 19 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:54241$3497 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:54241$3497_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:54242.12-54249.4" - cell \CR_dec19 \CR_dec19 - connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in - connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out - connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit - connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op - connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel - connect \opcode_in \CR_dec19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:54250.12-54257.4" - cell \CR_dec31 \CR_dec31 - connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in - connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out - connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit - connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op - connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel - connect \opcode_in \CR_dec31_opcode_in - end - attribute \src "libresoc.v:53224.7-53224.20" - process $proc$libresoc.v:53224$3503 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:54258.3-54270.6" - process $proc$libresoc.v:54258$3498 - assign { } { } - assign { } { } - assign $0\CR_function_unit[11:0] $1\CR_function_unit[11:0] - attribute \src "libresoc.v:54259.5-54259.29" - switch \initial - attribute \src "libresoc.v:54259.9-54259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_function_unit[11:0] \CR_dec19_CR_dec19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_function_unit[11:0] \CR_dec31_CR_dec31_function_unit - case - assign $1\CR_function_unit[11:0] 12'000000000000 - end - sync always - update \CR_function_unit $0\CR_function_unit[11:0] - end - attribute \src "libresoc.v:54271.3-54283.6" - process $proc$libresoc.v:54271$3499 - assign { } { } - assign { } { } - assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54272.5-54272.29" - switch \initial - attribute \src "libresoc.v:54272.9-54272.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op - case - assign $1\CR_internal_op[6:0] 7'0000000 - end - sync always - update \CR_internal_op $0\CR_internal_op[6:0] - end - attribute \src "libresoc.v:54284.3-54296.6" - process $proc$libresoc.v:54284$3500 - assign { } { } - assign { } { } - assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54285.5-54285.29" - switch \initial - attribute \src "libresoc.v:54285.9-54285.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in - case - assign $1\CR_cr_in[2:0] 3'000 - end - sync always - update \CR_cr_in $0\CR_cr_in[2:0] - end - attribute \src "libresoc.v:54297.3-54309.6" - process $proc$libresoc.v:54297$3501 - assign { } { } - assign { } { } - assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54298.5-54298.29" - switch \initial - attribute \src "libresoc.v:54298.9-54298.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out - case - assign $1\CR_cr_out[2:0] 3'000 - end - sync always - update \CR_cr_out $0\CR_cr_out[2:0] - end - attribute \src "libresoc.v:54310.3-54322.6" - process $proc$libresoc.v:54310$3502 - assign { } { } - assign { } { } - assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54311.5-54311.29" - switch \initial - attribute \src "libresoc.v:54311.9-54311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel - case - assign $1\CR_rc_sel[1:0] 2'00 - end - sync always - update \CR_rc_sel $0\CR_rc_sel[1:0] - end - connect \$1 $ternary$libresoc.v:54241$3497_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in 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\opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect 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wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VA_SHB - attribute \src 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connect \opcode_in \BRANCH_dec19_opcode_in - end - attribute \src "libresoc.v:54658.7-54658.20" - process $proc$libresoc.v:54658$3513 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:55615.3-55630.6" - process $proc$libresoc.v:55615$3505 - assign { } { } - assign { } { } - assign $0\BRANCH_function_unit[11:0] $1\BRANCH_function_unit[11:0] - attribute \src "libresoc.v:55616.5-55616.29" - switch \initial - attribute \src "libresoc.v:55616.9-55616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_function_unit[11:0] \BRANCH_dec19_BRANCH_dec19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_function_unit[11:0] 12'000000100000 - case - assign $1\BRANCH_function_unit[11:0] 12'000000000000 - end - sync always - update \BRANCH_function_unit $0\BRANCH_function_unit[11:0] - end - attribute \src "libresoc.v:55631.3-55646.6" - process $proc$libresoc.v:55631$3506 - assign { } { } - assign { } { } - assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:55632.5-55632.29" - switch \initial - attribute \src "libresoc.v:55632.9-55632.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_internal_op[6:0] 7'0000110 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_internal_op[6:0] 7'0000111 - case - assign $1\BRANCH_internal_op[6:0] 7'0000000 - end - sync always - update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] - end - attribute \src "libresoc.v:55647.3-55662.6" - process $proc$libresoc.v:55647$3507 - assign { } { } - assign { } { } - assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:55648.5-55648.29" - switch \initial - attribute \src "libresoc.v:55648.9-55648.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_in2_sel[3:0] 4'0110 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_in2_sel[3:0] 4'0111 - case - assign $1\BRANCH_in2_sel[3:0] 4'0000 - end - sync always - update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] - end - attribute \src "libresoc.v:55663.3-55678.6" - process $proc$libresoc.v:55663$3508 - assign { } { } - assign { } { } - assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:55664.5-55664.29" - switch \initial - attribute \src "libresoc.v:55664.9-55664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_cr_in[2:0] 3'010 - case - assign $1\BRANCH_cr_in[2:0] 3'000 - end - sync always - update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] - end - attribute \src "libresoc.v:55679.3-55694.6" - process $proc$libresoc.v:55679$3509 - assign { } { } - assign { } { } - assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:55680.5-55680.29" - switch \initial - attribute \src "libresoc.v:55680.9-55680.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_cr_out[2:0] 3'000 - case - assign $1\BRANCH_cr_out[2:0] 3'000 - end - sync always - update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] - end - attribute \src "libresoc.v:55695.3-55710.6" - process $proc$libresoc.v:55695$3510 - assign { } { } - assign { } { } - assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55696.5-55696.29" - switch \initial - attribute \src "libresoc.v:55696.9-55696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_rc_sel[1:0] 2'00 - case - assign $1\BRANCH_rc_sel[1:0] 2'00 - end - sync always - update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] - end - attribute \src "libresoc.v:55711.3-55726.6" - process $proc$libresoc.v:55711$3511 - assign { } { } - assign { } { } - assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:55712.5-55712.29" - switch \initial - attribute \src "libresoc.v:55712.9-55712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_is_32b[0:0] 1'0 - case - assign $1\BRANCH_is_32b[0:0] 1'0 - end - sync always - update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] - end - attribute \src "libresoc.v:55727.3-55742.6" - process $proc$libresoc.v:55727$3512 - assign { } { } - assign { } { } - assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:55728.5-55728.29" - switch \initial - attribute \src "libresoc.v:55728.9-55728.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\BRANCH_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\BRANCH_lk[0:0] 1'1 - case - assign $1\BRANCH_lk[0:0] 1'0 - end - sync always - update \BRANCH_lk $0\BRANCH_lk[0:0] - end - connect \$1 $ternary$libresoc.v:55603$3504_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "libresoc.v:56077.7-56077.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:57084$3514 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:57084$3514_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:57085.17-57101.4" - cell \LOGICAL_dec31 \LOGICAL_dec31 - connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in - connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out - connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in - connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out - connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit - connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel - connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel - connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op - connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a - connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out - connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b - connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len - connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel - connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn - connect \opcode_in \LOGICAL_dec31_opcode_in - end - attribute \src "libresoc.v:56077.7-56077.20" - process $proc$libresoc.v:56077$3529 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:57102.3-57129.6" - process $proc$libresoc.v:57102$3515 - assign { } { } - assign { } { } - assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57103.5-57103.29" - switch \initial - attribute \src "libresoc.v:57103.9-57103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cry_in[1:0] 2'00 - case - assign $1\LOGICAL_cry_in[1:0] 2'00 - end - sync always - update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] - end - attribute \src "libresoc.v:57130.3-57157.6" - process $proc$libresoc.v:57130$3516 - assign { } { } - assign { } { } - assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57131.5-57131.29" - switch \initial - attribute \src "libresoc.v:57131.9-57131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_inv_a[0:0] 1'0 - case - assign $1\LOGICAL_inv_a[0:0] 1'0 - end - sync always - update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] - end - attribute \src "libresoc.v:57158.3-57185.6" - process $proc$libresoc.v:57158$3517 - assign { } { } - assign { } { } - assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57159.5-57159.29" - switch \initial - attribute \src "libresoc.v:57159.9-57159.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_inv_out[0:0] 1'0 - case - assign $1\LOGICAL_inv_out[0:0] 1'0 - end - sync always - update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] - end - attribute \src "libresoc.v:57186.3-57213.6" - process $proc$libresoc.v:57186$3518 - assign { } { } - assign { } { } - assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57187.5-57187.29" - switch \initial - attribute \src "libresoc.v:57187.9-57187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cry_out[0:0] 1'0 - case - assign $1\LOGICAL_cry_out[0:0] 1'0 - end - sync always - update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] - end - attribute \src "libresoc.v:57214.3-57241.6" - process $proc$libresoc.v:57214$3519 - assign { } { } - assign { } { } - assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57215.5-57215.29" - switch \initial - attribute \src "libresoc.v:57215.9-57215.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_is_32b[0:0] 1'0 - case - assign $1\LOGICAL_is_32b[0:0] 1'0 - end - sync always - update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] - end - attribute \src "libresoc.v:57242.3-57269.6" - process $proc$libresoc.v:57242$3520 - assign { } { } - assign { } { } - assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57243.5-57243.29" - switch \initial - attribute \src "libresoc.v:57243.9-57243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_sgn[0:0] 1'0 - case - assign $1\LOGICAL_sgn[0:0] 1'0 - end - sync always - update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] - end - attribute \src "libresoc.v:57270.3-57297.6" - process $proc$libresoc.v:57270$3521 - assign { } { } - assign { } { } - assign $0\LOGICAL_function_unit[11:0] $1\LOGICAL_function_unit[11:0] - attribute \src "libresoc.v:57271.5-57271.29" - switch \initial - attribute \src "libresoc.v:57271.9-57271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_function_unit[11:0] 12'000000010000 - case - assign $1\LOGICAL_function_unit[11:0] 12'000000000000 - end - sync always - update \LOGICAL_function_unit $0\LOGICAL_function_unit[11:0] - end - attribute \src "libresoc.v:57298.3-57325.6" - process $proc$libresoc.v:57298$3522 - assign { } { } - assign { } { } - assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57299.5-57299.29" - switch \initial - attribute \src "libresoc.v:57299.9-57299.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'1000011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_internal_op[6:0] 7'1000011 - case - assign $1\LOGICAL_internal_op[6:0] 7'0000000 - end - sync always - update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] - end - attribute \src "libresoc.v:57326.3-57353.6" - process $proc$libresoc.v:57326$3523 - assign { } { } - assign { } { } - assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57327.5-57327.29" - switch \initial - attribute \src "libresoc.v:57327.9-57327.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_in1_sel[2:0] 3'100 - case - assign $1\LOGICAL_in1_sel[2:0] 3'000 - end - sync always - update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] - end - attribute \src "libresoc.v:57354.3-57381.6" - process $proc$libresoc.v:57354$3524 - assign { } { } - assign { } { } - assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57355.5-57355.29" - switch \initial - attribute \src "libresoc.v:57355.9-57355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_in2_sel[3:0] 4'0100 - case - assign $1\LOGICAL_in2_sel[3:0] 4'0000 - end - sync always - update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] - end - attribute \src "libresoc.v:57382.3-57409.6" - process $proc$libresoc.v:57382$3525 - assign { } { } - assign { } { } - assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:57383.5-57383.29" - switch \initial - attribute \src "libresoc.v:57383.9-57383.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cr_in[2:0] 3'000 - case - assign $1\LOGICAL_cr_in[2:0] 3'000 - end - sync always - update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] - end - attribute \src "libresoc.v:57410.3-57437.6" - process $proc$libresoc.v:57410$3526 - assign { } { } - assign { } { } - assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57411.5-57411.29" - switch \initial - attribute \src "libresoc.v:57411.9-57411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_cr_out[2:0] 3'000 - case - assign $1\LOGICAL_cr_out[2:0] 3'000 - end - sync always - update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] - end - attribute \src "libresoc.v:57438.3-57465.6" - process $proc$libresoc.v:57438$3527 - assign { } { } - assign { } { } - assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:57439.5-57439.29" - switch \initial - attribute \src "libresoc.v:57439.9-57439.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - case - assign $1\LOGICAL_ldst_len[3:0] 4'0000 - end - sync always - update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] - end - attribute \src "libresoc.v:57466.3-57493.6" - process $proc$libresoc.v:57466$3528 - assign { } { } - assign { } { } - assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57467.5-57467.29" - switch \initial - attribute \src "libresoc.v:57467.9-57467.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\LOGICAL_rc_sel[1:0] 2'00 - case - assign $1\LOGICAL_rc_sel[1:0] 2'00 - end - sync always - update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] - end - connect \$1 $ternary$libresoc.v:57084$3514_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \LOGICAL_SPR \opcode_in [20:11] - connect \LOGICAL_MB \opcode_in [10:6] - connect \LOGICAL_ME \opcode_in [5:1] - connect \LOGICAL_SH \opcode_in [15:11] - connect \LOGICAL_BC \opcode_in [10:6] - connect \LOGICAL_TO \opcode_in [25:21] - connect \LOGICAL_DS \opcode_in [15:2] - connect \LOGICAL_D \opcode_in [15:0] - connect \LOGICAL_BH \opcode_in [12:11] - connect \LOGICAL_BI \opcode_in [20:16] - connect \LOGICAL_BO \opcode_in [25:21] - connect \LOGICAL_FXM \opcode_in [19:12] - connect \LOGICAL_BT \opcode_in [25:21] - connect \LOGICAL_BA \opcode_in [20:16] - connect \LOGICAL_BB \opcode_in [15:11] - connect \LOGICAL_CR \opcode_in [10:1] - connect \LOGICAL_BF \opcode_in [25:23] - connect \LOGICAL_BD \opcode_in [15:2] - connect \LOGICAL_OE \opcode_in [10] - connect \LOGICAL_Rc \opcode_in [0] - connect \LOGICAL_AA \opcode_in [1] - connect \LOGICAL_LK \opcode_in [0] - connect \LOGICAL_LI \opcode_in [25:2] - connect \LOGICAL_ME32 \opcode_in [5:1] - connect \LOGICAL_MB32 \opcode_in [10:6] - connect \LOGICAL_sh { \opcode_in [1] \opcode_in [15:11] } - connect \LOGICAL_SH32 \opcode_in [15:11] - connect \LOGICAL_L \opcode_in [21] - connect \LOGICAL_UI \opcode_in [15:0] - connect \LOGICAL_SI \opcode_in [15:0] - connect \LOGICAL_RB \opcode_in [15:11] - connect \LOGICAL_RA \opcode_in [20:16] - connect \LOGICAL_RT \opcode_in [25:21] - connect \LOGICAL_RS \opcode_in [25:21] - connect \opcode_in \$1 - connect \LOGICAL_dec31_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "libresoc.v:57827.1-59132.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" -attribute \generator "nMigen" -module \dec$164 - attribute \src "libresoc.v:58763.3-58772.6" - wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:58773.3-58782.6" - wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:58743.3-58752.6" - wire width 12 $0\SPR_function_unit[11:0] - attribute \src "libresoc.v:58753.3-58762.6" - wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:58793.3-58802.6" - wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:58783.3-58792.6" - wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:57828.7-57828.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:58763.3-58772.6" - wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:58773.3-58782.6" - wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:58743.3-58752.6" - wire width 12 $1\SPR_function_unit[11:0] - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "libresoc.v:57828.7-57828.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:58733$3530 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:58733$3530_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:58734.13-58742.4" - cell \SPR_dec31 \SPR_dec31 - connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in - connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out - connect \SPR_dec31_function_unit \SPR_dec31_SPR_dec31_function_unit - connect \SPR_dec31_internal_op \SPR_dec31_SPR_dec31_internal_op - connect \SPR_dec31_is_32b \SPR_dec31_SPR_dec31_is_32b - connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel - connect \opcode_in \SPR_dec31_opcode_in - end - attribute \src "libresoc.v:57828.7-57828.20" - process $proc$libresoc.v:57828$3537 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:58743.3-58752.6" - process $proc$libresoc.v:58743$3531 - assign { } { } - assign { } { } - assign $0\SPR_function_unit[11:0] $1\SPR_function_unit[11:0] - attribute \src "libresoc.v:58744.5-58744.29" - switch \initial - attribute \src "libresoc.v:58744.9-58744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_function_unit[11:0] \SPR_dec31_SPR_dec31_function_unit - case - assign $1\SPR_function_unit[11:0] 12'000000000000 - end - sync always - update \SPR_function_unit $0\SPR_function_unit[11:0] - end - attribute \src "libresoc.v:58753.3-58762.6" - process $proc$libresoc.v:58753$3532 - assign { } { } - assign { } { } - assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:58754.5-58754.29" - switch \initial - attribute \src "libresoc.v:58754.9-58754.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op - case - assign $1\SPR_internal_op[6:0] 7'0000000 - end - sync always - update \SPR_internal_op $0\SPR_internal_op[6:0] - end - attribute \src "libresoc.v:58763.3-58772.6" - process $proc$libresoc.v:58763$3533 - assign { } { } - assign { } { } - assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:58764.5-58764.29" - switch \initial - attribute \src "libresoc.v:58764.9-58764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in - case - assign $1\SPR_cr_in[2:0] 3'000 - end - sync always - update \SPR_cr_in $0\SPR_cr_in[2:0] - end - attribute \src "libresoc.v:58773.3-58782.6" - process $proc$libresoc.v:58773$3534 - assign { } { } - assign { } { } - assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:58774.5-58774.29" - switch \initial - attribute \src "libresoc.v:58774.9-58774.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out - case - assign $1\SPR_cr_out[2:0] 3'000 - end - sync always - update \SPR_cr_out $0\SPR_cr_out[2:0] - end - attribute \src "libresoc.v:58783.3-58792.6" - process $proc$libresoc.v:58783$3535 - assign { } { } - assign { } { } - assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58784.5-58784.29" - switch \initial - attribute \src "libresoc.v:58784.9-58784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel - case - assign $1\SPR_rc_sel[1:0] 2'00 - end - sync always - update \SPR_rc_sel $0\SPR_rc_sel[1:0] - end - attribute \src "libresoc.v:58793.3-58802.6" - process $proc$libresoc.v:58793$3536 - assign { } { } - assign { } { } - assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:58794.5-58794.29" - switch \initial - attribute \src "libresoc.v:58794.9-58794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b - case - assign $1\SPR_is_32b[0:0] 1'0 - end - sync always - update \SPR_is_32b $0\SPR_is_32b[0:0] - end - connect \$1 $ternary$libresoc.v:58733$3530_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect 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connect \SPR_L \opcode_in [21] - connect \SPR_UI \opcode_in [15:0] - connect \SPR_SI \opcode_in [15:0] - connect \SPR_RB \opcode_in [15:11] - connect \SPR_RA \opcode_in [20:16] - connect \SPR_RT \opcode_in [25:21] - connect \SPR_RS \opcode_in [25:21] - connect \opcode_in \$1 - connect \SPR_dec31_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "libresoc.v:59136.1-60631.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" -attribute \generator "nMigen" -module \dec$171 - attribute \src "libresoc.v:60262.3-60271.6" - wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60272.3-60281.6" - wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60162.3-60171.6" - wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60192.3-60201.6" - wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60222.3-60231.6" - wire width 12 $0\DIV_function_unit[11:0] - attribute \src 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wire width 5 output 26 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 32 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 25 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 3 \DIV_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 2 \DIV_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 30 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 28 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \DIV_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \DIV_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 31 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 29 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \DIV_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 output 22 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \DIV_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 24 \DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 17 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 23 \DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 20 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 output 18 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \DIV_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \DIV_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 output 19 \DIV_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \DIV_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \DIV_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 14 \DIV_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \DIV_dec31_DIV_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \DIV_dec31_DIV_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \DIV_dec31_DIV_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \DIV_dec31_DIV_dec31_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \DIV_dec31_DIV_dec31_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \DIV_dec31_DIV_dec31_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \DIV_dec31_DIV_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \DIV_dec31_DIV_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \DIV_dec31_DIV_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \DIV_dec31_DIV_dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \DIV_dec31_DIV_dec31_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \DIV_dec31_DIV_dec31_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \DIV_dec31_DIV_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \DIV_dec31_DIV_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \DIV_dec31_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \DIV_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 8 \DIV_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 9 \DIV_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \DIV_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 10 \DIV_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 3 \DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 output 21 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 35 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 34 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src 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wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "libresoc.v:59137.7-59137.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 36 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:60144$3538 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:60144$3538_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:60145.13-60161.4" - cell \DIV_dec31 \DIV_dec31 - connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in - connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out - connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in - connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out - connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit - connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel - connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel - connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op - connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a - connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out - connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b - connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len - connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel - connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn - connect \opcode_in \DIV_dec31_opcode_in - end - attribute \src "libresoc.v:59137.7-59137.20" - process $proc$libresoc.v:59137$3553 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:60162.3-60171.6" - process $proc$libresoc.v:60162$3539 - assign { } { } - assign { } { } - assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60163.5-60163.29" - switch \initial - attribute \src "libresoc.v:60163.9-60163.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in - case - assign $1\DIV_cry_in[1:0] 2'00 - end - sync always - update \DIV_cry_in $0\DIV_cry_in[1:0] - end - attribute \src "libresoc.v:60172.3-60181.6" - process $proc$libresoc.v:60172$3540 - assign { } { } - assign { } { } - assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60173.5-60173.29" - switch \initial - attribute \src "libresoc.v:60173.9-60173.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a - case - assign $1\DIV_inv_a[0:0] 1'0 - end - sync always - update \DIV_inv_a $0\DIV_inv_a[0:0] - end - attribute \src "libresoc.v:60182.3-60191.6" - process $proc$libresoc.v:60182$3541 - assign { } { } - assign { } { } - assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60183.5-60183.29" - switch \initial - attribute \src "libresoc.v:60183.9-60183.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out - case - assign $1\DIV_inv_out[0:0] 1'0 - end - sync always - update \DIV_inv_out $0\DIV_inv_out[0:0] - end - attribute \src "libresoc.v:60192.3-60201.6" - process $proc$libresoc.v:60192$3542 - assign { } { } - assign { } { } - assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60193.5-60193.29" - switch \initial - attribute \src "libresoc.v:60193.9-60193.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out - case - assign $1\DIV_cry_out[0:0] 1'0 - end - sync always - update \DIV_cry_out $0\DIV_cry_out[0:0] - end - attribute \src "libresoc.v:60202.3-60211.6" - process $proc$libresoc.v:60202$3543 - assign { } { } - assign { } { } - assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60203.5-60203.29" - switch \initial - attribute \src "libresoc.v:60203.9-60203.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b - case - assign $1\DIV_is_32b[0:0] 1'0 - end - sync always - update \DIV_is_32b $0\DIV_is_32b[0:0] - end - attribute \src "libresoc.v:60212.3-60221.6" - process $proc$libresoc.v:60212$3544 - assign { } { } - assign { } { } - assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60213.5-60213.29" - switch \initial - attribute \src "libresoc.v:60213.9-60213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn - case - assign $1\DIV_sgn[0:0] 1'0 - end - sync always - update \DIV_sgn $0\DIV_sgn[0:0] - end - attribute \src "libresoc.v:60222.3-60231.6" - process $proc$libresoc.v:60222$3545 - assign { } { } - assign { } { } - assign $0\DIV_function_unit[11:0] $1\DIV_function_unit[11:0] - attribute \src "libresoc.v:60223.5-60223.29" - switch \initial - attribute \src "libresoc.v:60223.9-60223.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_function_unit[11:0] \DIV_dec31_DIV_dec31_function_unit - case - assign $1\DIV_function_unit[11:0] 12'000000000000 - end - sync always - update \DIV_function_unit $0\DIV_function_unit[11:0] - end - attribute \src "libresoc.v:60232.3-60241.6" - process $proc$libresoc.v:60232$3546 - assign { } { } - assign { } { } - assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60233.5-60233.29" - switch \initial - attribute \src "libresoc.v:60233.9-60233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op - case - assign $1\DIV_internal_op[6:0] 7'0000000 - end - sync always - update \DIV_internal_op $0\DIV_internal_op[6:0] - end - attribute \src "libresoc.v:60242.3-60251.6" - process $proc$libresoc.v:60242$3547 - assign { } { } - assign { } { } - assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60243.5-60243.29" - switch \initial - attribute \src "libresoc.v:60243.9-60243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel - case - assign $1\DIV_in1_sel[2:0] 3'000 - end - sync always - update \DIV_in1_sel $0\DIV_in1_sel[2:0] - end - attribute \src "libresoc.v:60252.3-60261.6" - process $proc$libresoc.v:60252$3548 - assign { } { } - assign { } { } - assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60253.5-60253.29" - switch \initial - attribute \src "libresoc.v:60253.9-60253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel - case - assign $1\DIV_in2_sel[3:0] 4'0000 - end - sync always - update \DIV_in2_sel $0\DIV_in2_sel[3:0] - end - attribute \src "libresoc.v:60262.3-60271.6" - process $proc$libresoc.v:60262$3549 - assign { } { } - assign { } { } - assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60263.5-60263.29" - switch \initial - attribute \src "libresoc.v:60263.9-60263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in - case - assign $1\DIV_cr_in[2:0] 3'000 - end - sync always - update \DIV_cr_in $0\DIV_cr_in[2:0] - end - attribute \src "libresoc.v:60272.3-60281.6" - process $proc$libresoc.v:60272$3550 - assign { } { } - assign { } { } - assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60273.5-60273.29" - switch \initial - attribute \src "libresoc.v:60273.9-60273.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out - case - assign $1\DIV_cr_out[2:0] 3'000 - end - sync always - update \DIV_cr_out $0\DIV_cr_out[2:0] - end - attribute \src "libresoc.v:60282.3-60291.6" - process $proc$libresoc.v:60282$3551 - assign { } { } - assign { } { } - assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60283.5-60283.29" - switch \initial - attribute \src "libresoc.v:60283.9-60283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len - case - assign $1\DIV_ldst_len[3:0] 4'0000 - end - sync always - update \DIV_ldst_len $0\DIV_ldst_len[3:0] - end - attribute \src "libresoc.v:60292.3-60301.6" - process $proc$libresoc.v:60292$3552 - assign { } { } - assign { } { } - assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60293.5-60293.29" - switch \initial - attribute \src "libresoc.v:60293.9-60293.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel - case - assign $1\DIV_rc_sel[1:0] 2'00 - end - sync always - update \DIV_rc_sel $0\DIV_rc_sel[1:0] - end - connect \$1 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\enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \MUL_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 3 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 output 14 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 28 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 26 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 27 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "libresoc.v:60636.7-60636.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 29 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:61581$3554 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:61581$3554_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:61582.13-61592.4" - cell \MUL_dec31 \MUL_dec31 - connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in - connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out - connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit - connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel - connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op - connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b - connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel - connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn - connect \opcode_in \MUL_dec31_opcode_in - end - attribute \src "libresoc.v:60636.7-60636.20" - process $proc$libresoc.v:60636$3563 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:61593.3-61605.6" - process $proc$libresoc.v:61593$3555 - assign { } { } - assign { } { } - assign $0\MUL_function_unit[11:0] $1\MUL_function_unit[11:0] - attribute \src "libresoc.v:61594.5-61594.29" - switch \initial - attribute \src "libresoc.v:61594.9-61594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_function_unit[11:0] \MUL_dec31_MUL_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_function_unit[11:0] 12'000100000000 - case - assign $1\MUL_function_unit[11:0] 12'000000000000 - end - sync always - update \MUL_function_unit $0\MUL_function_unit[11:0] - end - attribute \src "libresoc.v:61606.3-61618.6" - process $proc$libresoc.v:61606$3556 - assign { } { } - assign { } { } - assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:61607.5-61607.29" - switch \initial - attribute \src "libresoc.v:61607.9-61607.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_internal_op[6:0] 7'0110010 - case - assign $1\MUL_internal_op[6:0] 7'0000000 - end - sync always - update \MUL_internal_op $0\MUL_internal_op[6:0] - end - attribute \src "libresoc.v:61619.3-61631.6" - process $proc$libresoc.v:61619$3557 - assign { } { } - assign { } { } - assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:61620.5-61620.29" - switch \initial - attribute \src "libresoc.v:61620.9-61620.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_in2_sel[3:0] 4'0011 - case - assign $1\MUL_in2_sel[3:0] 4'0000 - end - sync always - update \MUL_in2_sel $0\MUL_in2_sel[3:0] - end - attribute \src "libresoc.v:61632.3-61644.6" - process $proc$libresoc.v:61632$3558 - assign { } { } - assign { } { } - assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:61633.5-61633.29" - switch \initial - attribute \src "libresoc.v:61633.9-61633.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_cr_in[2:0] 3'000 - case - assign $1\MUL_cr_in[2:0] 3'000 - end - sync always - update \MUL_cr_in $0\MUL_cr_in[2:0] - end - attribute \src "libresoc.v:61645.3-61657.6" - process $proc$libresoc.v:61645$3559 - assign { } { } - assign { } { } - assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:61646.5-61646.29" - switch \initial - attribute \src "libresoc.v:61646.9-61646.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_cr_out[2:0] 3'001 - case - assign $1\MUL_cr_out[2:0] 3'000 - end - sync always - update \MUL_cr_out $0\MUL_cr_out[2:0] - end - attribute \src "libresoc.v:61658.3-61670.6" - process $proc$libresoc.v:61658$3560 - assign { } { } - assign { } { } - assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:61659.5-61659.29" - switch \initial - attribute \src "libresoc.v:61659.9-61659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_rc_sel[1:0] 2'00 - case - assign $1\MUL_rc_sel[1:0] 2'00 - end - sync always - update \MUL_rc_sel $0\MUL_rc_sel[1:0] - end - attribute \src "libresoc.v:61671.3-61683.6" - process $proc$libresoc.v:61671$3561 - assign { } { } - assign { } { } - assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:61672.5-61672.29" - switch \initial - attribute \src "libresoc.v:61672.9-61672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_is_32b[0:0] 1'0 - case - assign $1\MUL_is_32b[0:0] 1'0 - end - sync always - update \MUL_is_32b $0\MUL_is_32b[0:0] - end - attribute \src "libresoc.v:61684.3-61696.6" - process $proc$libresoc.v:61684$3562 - assign { } { } - assign { } { } - assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:61685.5-61685.29" - switch \initial - attribute \src "libresoc.v:61685.9-61685.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\MUL_sgn[0:0] 1'1 - case - assign $1\MUL_sgn[0:0] 1'0 - end - sync always - update \MUL_sgn $0\MUL_sgn[0:0] - end - connect \$1 $ternary$libresoc.v:61581$3554_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \MUL_SPR \opcode_in [20:11] - connect \MUL_MB \opcode_in [10:6] - connect \MUL_ME \opcode_in [5:1] - connect \MUL_SH \opcode_in [15:11] - connect \MUL_BC \opcode_in [10:6] - connect \MUL_TO \opcode_in [25:21] - connect \MUL_DS \opcode_in [15:2] - connect \MUL_D \opcode_in [15:0] - connect \MUL_BH \opcode_in [12:11] - connect \MUL_BI \opcode_in [20:16] - connect \MUL_BO \opcode_in [25:21] - connect \MUL_FXM \opcode_in [19:12] - connect \MUL_BT \opcode_in [25:21] - connect \MUL_BA \opcode_in [20:16] - connect \MUL_BB \opcode_in [15:11] - connect \MUL_CR \opcode_in [10:1] - connect \MUL_BF \opcode_in [25:23] - connect \MUL_BD \opcode_in [15:2] - connect \MUL_OE \opcode_in [10] - connect \MUL_Rc \opcode_in [0] - connect \MUL_AA \opcode_in [1] - connect \MUL_LK \opcode_in [0] - connect \MUL_LI \opcode_in [25:2] - connect \MUL_ME32 \opcode_in [5:1] - connect \MUL_MB32 \opcode_in [10:6] - connect \MUL_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MUL_SH32 \opcode_in [15:11] - connect \MUL_L \opcode_in [21] - connect \MUL_UI \opcode_in [15:0] - connect \MUL_SI \opcode_in [15:0] - connect \MUL_RB \opcode_in [15:11] - connect \MUL_RA \opcode_in [20:16] - connect \MUL_RT \opcode_in [25:21] - connect \MUL_RS \opcode_in [25:21] - connect \opcode_in \$1 - connect \MUL_dec31_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "libresoc.v:62030.1-63748.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" -attribute \generator "nMigen" -module \dec$188 - attribute \src "libresoc.v:63330.3-63351.6" - wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63352.3-63373.6" - wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63396.3-63417.6" - wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63198.3-63219.6" - wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63264.3-63285.6" - wire width 12 $0\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:63308.3-63329.6" - wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63286.3-63307.6" - wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63176.3-63197.6" - wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63220.3-63241.6" - wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63374.3-63395.6" - wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63242.3-63263.6" - wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62031.7-62031.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:63330.3-63351.6" - wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63352.3-63373.6" - wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63396.3-63417.6" - wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63198.3-63219.6" - wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63264.3-63285.6" - wire width 12 $1\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:63308.3-63329.6" - wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63286.3-63307.6" - wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63176.3-63197.6" - wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63220.3-63241.6" - wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63374.3-63395.6" - wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63242.3-63263.6" - wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63147.17-63147.211" - wire width 32 $ternary$libresoc.v:63147$3564_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - wire width 32 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \DX_d0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \DX_d0_d1_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DX_d1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DX_d2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \D_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \SHIFT_ROT_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 23 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 22 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 28 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 21 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 3 \SHIFT_ROT_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 2 \SHIFT_ROT_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 26 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 24 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \SHIFT_ROT_CR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \SHIFT_ROT_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 output 27 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 25 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \SHIFT_ROT_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 output 18 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \SHIFT_ROT_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 20 \SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 19 \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 16 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 output 14 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 \SHIFT_ROT_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SHIFT_ROT_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 output 15 \SHIFT_ROT_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 4 \SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \SHIFT_ROT_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 10 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 11 \SHIFT_ROT_cry_out - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \SHIFT_ROT_dec30_opcode_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \SHIFT_ROT_dec31_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \SHIFT_ROT_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 8 \SHIFT_ROT_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 12 \SHIFT_ROT_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 3 \SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 13 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 output 17 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 31 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 29 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 30 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "libresoc.v:62031.7-62031.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 32 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:63147$3564 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:63147$3564_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:63148.19-63161.4" - cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 - connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in - connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out - connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out - connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit - connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel - connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - connect \SHIFT_ROT_dec30_inv_a \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a - connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b - connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - connect \opcode_in \SHIFT_ROT_dec30_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:63162.19-63175.4" - cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 - connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in - connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out - connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out - connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit - connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel - connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - connect \SHIFT_ROT_dec31_inv_a \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a - connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b - connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - connect \opcode_in \SHIFT_ROT_dec31_opcode_in - end - attribute \src "libresoc.v:62031.7-62031.20" - process $proc$libresoc.v:62031$3576 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:63176.3-63197.6" - process $proc$libresoc.v:63176$3565 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63177.5-63177.29" - switch \initial - attribute \src "libresoc.v:63177.9-63177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_inv_a[0:0] 1'0 - case - assign $1\SHIFT_ROT_inv_a[0:0] 1'0 - end - sync always - update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] - end - attribute \src "libresoc.v:63198.3-63219.6" - process $proc$libresoc.v:63198$3566 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63199.5-63199.29" - switch \initial - attribute \src "libresoc.v:63199.9-63199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - case - assign $1\SHIFT_ROT_cry_out[0:0] 1'0 - end - sync always - update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] - end - attribute \src "libresoc.v:63220.3-63241.6" - process $proc$libresoc.v:63220$3567 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:63221.5-63221.29" - switch \initial - attribute \src "libresoc.v:63221.9-63221.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_is_32b[0:0] 1'1 - case - assign $1\SHIFT_ROT_is_32b[0:0] 1'0 - end - sync always - update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] - end - attribute \src "libresoc.v:63242.3-63263.6" - process $proc$libresoc.v:63242$3568 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63243.5-63243.29" - switch \initial - attribute \src "libresoc.v:63243.9-63243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - case - assign $1\SHIFT_ROT_sgn[0:0] 1'0 - end - sync always - update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] - end - attribute \src "libresoc.v:63264.3-63285.6" - process $proc$libresoc.v:63264$3569 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_function_unit[11:0] $1\SHIFT_ROT_function_unit[11:0] - attribute \src "libresoc.v:63265.5-63265.29" - switch \initial - attribute \src "libresoc.v:63265.9-63265.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 - case - assign $1\SHIFT_ROT_function_unit[11:0] 12'000000000000 - end - sync always - update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[11:0] - end - attribute \src "libresoc.v:63286.3-63307.6" - process $proc$libresoc.v:63286$3570 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63287.5-63287.29" - switch \initial - attribute \src "libresoc.v:63287.9-63287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 - case - assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 - end - sync always - update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] - end - attribute \src "libresoc.v:63308.3-63329.6" - process $proc$libresoc.v:63308$3571 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:63309.5-63309.29" - switch \initial - attribute \src "libresoc.v:63309.9-63309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 - case - assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 - end - sync always - update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] - end - attribute \src "libresoc.v:63330.3-63351.6" - process $proc$libresoc.v:63330$3572 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:63331.5-63331.29" - switch \initial - attribute \src "libresoc.v:63331.9-63331.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - case - assign $1\SHIFT_ROT_cr_in[2:0] 3'000 - end - sync always - update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] - end - attribute \src "libresoc.v:63352.3-63373.6" - process $proc$libresoc.v:63352$3573 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:63353.5-63353.29" - switch \initial - attribute \src "libresoc.v:63353.9-63353.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cr_out[2:0] 3'001 - case - assign $1\SHIFT_ROT_cr_out[2:0] 3'000 - end - sync always - update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] - end - attribute \src "libresoc.v:63374.3-63395.6" - process $proc$libresoc.v:63374$3574 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:63375.5-63375.29" - switch \initial - attribute \src "libresoc.v:63375.9-63375.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 - case - assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 - end - sync always - update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] - end - attribute \src "libresoc.v:63396.3-63417.6" - process $proc$libresoc.v:63396$3575 - assign { } { } - assign { } { } - assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63397.5-63397.29" - switch \initial - attribute \src "libresoc.v:63397.9-63397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - case - assign $1\SHIFT_ROT_cry_in[1:0] 2'00 - end - sync always - update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] - end - connect \$1 $ternary$libresoc.v:63147$3564_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \SHIFT_ROT_SPR \opcode_in [20:11] - connect \SHIFT_ROT_MB \opcode_in [10:6] - connect \SHIFT_ROT_ME \opcode_in [5:1] - connect \SHIFT_ROT_SH \opcode_in [15:11] - connect \SHIFT_ROT_BC \opcode_in [10:6] - connect \SHIFT_ROT_TO \opcode_in [25:21] - connect \SHIFT_ROT_DS \opcode_in [15:2] - connect \SHIFT_ROT_D \opcode_in [15:0] - connect \SHIFT_ROT_BH \opcode_in [12:11] - connect \SHIFT_ROT_BI \opcode_in [20:16] - connect \SHIFT_ROT_BO \opcode_in [25:21] - connect \SHIFT_ROT_FXM \opcode_in [19:12] - connect \SHIFT_ROT_BT \opcode_in [25:21] - connect \SHIFT_ROT_BA \opcode_in [20:16] - connect \SHIFT_ROT_BB \opcode_in [15:11] - connect \SHIFT_ROT_CR \opcode_in [10:1] - connect \SHIFT_ROT_BF \opcode_in [25:23] - connect \SHIFT_ROT_BD \opcode_in [15:2] - connect \SHIFT_ROT_OE \opcode_in [10] - connect \SHIFT_ROT_Rc \opcode_in [0] - connect \SHIFT_ROT_AA \opcode_in [1] - connect \SHIFT_ROT_LK \opcode_in [0] - connect \SHIFT_ROT_LI \opcode_in [25:2] - connect \SHIFT_ROT_ME32 \opcode_in [5:1] - connect \SHIFT_ROT_MB32 \opcode_in [10:6] - connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } - connect \SHIFT_ROT_SH32 \opcode_in [15:11] - connect \SHIFT_ROT_L \opcode_in [21] - connect \SHIFT_ROT_UI \opcode_in [15:0] - connect \SHIFT_ROT_SI \opcode_in [15:0] - connect \SHIFT_ROT_RB \opcode_in [15:11] - connect \SHIFT_ROT_RA \opcode_in [20:16] - connect \SHIFT_ROT_RT \opcode_in [25:21] - connect \SHIFT_ROT_RS \opcode_in [25:21] - connect \opcode_in \$1 - connect \SHIFT_ROT_dec31_opcode_in \opcode_in - connect \SHIFT_ROT_dec30_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "libresoc.v:63752.1-66221.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" -attribute \generator "nMigen" -module \dec$196 - attribute \src "libresoc.v:65310.3-65367.6" - wire $0\LDST_br[0:0] - attribute \src "libresoc.v:65774.3-65831.6" - wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:65832.3-65889.6" - wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:65542.3-65599.6" - wire width 12 $0\LDST_function_unit[11:0] - attribute \src "libresoc.v:65658.3-65715.6" - wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:65716.3-65773.6" - wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65600.3-65657.6" - wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:65426.3-65483.6" - wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65136.3-65193.6" - wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65252.3-65309.6" - wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65484.3-65541.6" - wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:65368.3-65425.6" - wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65194.3-65251.6" - wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:63753.7-63753.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:65310.3-65367.6" - wire $1\LDST_br[0:0] - attribute \src "libresoc.v:65774.3-65831.6" - wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:65832.3-65889.6" - wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:65542.3-65599.6" - wire width 12 $1\LDST_function_unit[11:0] - attribute \src "libresoc.v:65658.3-65715.6" - wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:65716.3-65773.6" - wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65600.3-65657.6" - wire width 7 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\A_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \A_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \A_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \B_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 14 \B_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \B_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \B_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \B_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQE_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DQE_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 12 \DQ_DQ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \DQ_PT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DQ_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \DQ_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \DQ_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \DQ_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 14 \DS_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \DS_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \DS_XO - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRC - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 32 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 33 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_CT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \X_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_DRM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_E - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_EO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_EX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_E_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \X_IH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_IMM8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_L1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_L3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_MO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_NB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_PRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RIC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_RM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_RO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RSp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_RTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_R_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_SP - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_SR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_SX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_SX_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_TBR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \X_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \X_U - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \X_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \X_WC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \X_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \X_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \Z22_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DCM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_DGM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z22_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z22_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \Z22_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \Z22_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRAp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRBp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_FRTp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_R - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \Z23_RMC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \Z23_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \Z23_TE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \Z23_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_OPCD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \all_PO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "libresoc.v:63753.7-63753.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 35 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:65087$3577 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:65087$3577_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:65088.14-65103.4" - cell \LDST_dec31 \LDST_dec31 - connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br - connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in - connect \LDST_dec31_cr_out \LDST_dec31_LDST_dec31_cr_out - connect \LDST_dec31_function_unit \LDST_dec31_LDST_dec31_function_unit - connect \LDST_dec31_in1_sel \LDST_dec31_LDST_dec31_in1_sel - connect \LDST_dec31_in2_sel \LDST_dec31_LDST_dec31_in2_sel - connect \LDST_dec31_internal_op \LDST_dec31_LDST_dec31_internal_op - connect \LDST_dec31_is_32b \LDST_dec31_LDST_dec31_is_32b - connect \LDST_dec31_ldst_len \LDST_dec31_LDST_dec31_ldst_len - connect \LDST_dec31_rc_sel \LDST_dec31_LDST_dec31_rc_sel - connect \LDST_dec31_sgn \LDST_dec31_LDST_dec31_sgn - connect \LDST_dec31_sgn_ext \LDST_dec31_LDST_dec31_sgn_ext - connect \LDST_dec31_upd \LDST_dec31_LDST_dec31_upd - connect \opcode_in \LDST_dec31_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:65104.14-65119.4" - cell \LDST_dec58 \LDST_dec58 - connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br - connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in - connect \LDST_dec58_cr_out \LDST_dec58_LDST_dec58_cr_out - connect \LDST_dec58_function_unit \LDST_dec58_LDST_dec58_function_unit - connect \LDST_dec58_in1_sel \LDST_dec58_LDST_dec58_in1_sel - connect \LDST_dec58_in2_sel \LDST_dec58_LDST_dec58_in2_sel - connect \LDST_dec58_internal_op \LDST_dec58_LDST_dec58_internal_op - connect \LDST_dec58_is_32b \LDST_dec58_LDST_dec58_is_32b - connect \LDST_dec58_ldst_len \LDST_dec58_LDST_dec58_ldst_len - connect \LDST_dec58_rc_sel \LDST_dec58_LDST_dec58_rc_sel - connect \LDST_dec58_sgn \LDST_dec58_LDST_dec58_sgn - connect \LDST_dec58_sgn_ext \LDST_dec58_LDST_dec58_sgn_ext - connect \LDST_dec58_upd \LDST_dec58_LDST_dec58_upd - connect \opcode_in \LDST_dec58_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:65120.14-65135.4" - cell \LDST_dec62 \LDST_dec62 - connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br - connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in - connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out - connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit - connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel - connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel - connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op - connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b - connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len - connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel - connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn - connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext - connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd - connect \opcode_in \LDST_dec62_opcode_in - end - attribute \src "libresoc.v:63753.7-63753.20" - process $proc$libresoc.v:63753$3591 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:65136.3-65193.6" - process $proc$libresoc.v:65136$3578 - assign { } { } - assign { } { } - assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65137.5-65137.29" - switch \initial - attribute \src "libresoc.v:65137.9-65137.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_ldst_len[3:0] 4'0100 - case - assign $1\LDST_ldst_len[3:0] 4'0000 - end - sync always - update \LDST_ldst_len $0\LDST_ldst_len[3:0] - end - attribute \src "libresoc.v:65194.3-65251.6" - process $proc$libresoc.v:65194$3579 - assign { } { } - assign { } { } - assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:65195.5-65195.29" - switch \initial - attribute \src "libresoc.v:65195.9-65195.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_upd[1:0] 2'01 - case - assign $1\LDST_upd[1:0] 2'00 - end - sync always - update \LDST_upd $0\LDST_upd[1:0] - end - attribute \src "libresoc.v:65252.3-65309.6" - process $proc$libresoc.v:65252$3580 - assign { } { } - assign { } { } - assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:65253.5-65253.29" - switch \initial - attribute \src "libresoc.v:65253.9-65253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_rc_sel[1:0] 2'00 - case - assign $1\LDST_rc_sel[1:0] 2'00 - end - sync always - update \LDST_rc_sel $0\LDST_rc_sel[1:0] - end - attribute \src "libresoc.v:65310.3-65367.6" - process $proc$libresoc.v:65310$3581 - assign { } { } - assign { } { } - assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:65311.5-65311.29" - switch \initial - attribute \src "libresoc.v:65311.9-65311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_br[0:0] 1'0 - case - assign $1\LDST_br[0:0] 1'0 - end - sync always - update \LDST_br $0\LDST_br[0:0] - end - attribute \src "libresoc.v:65368.3-65425.6" - process $proc$libresoc.v:65368$3582 - assign { } { } - assign { } { } - assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:65369.5-65369.29" - switch \initial - attribute \src "libresoc.v:65369.9-65369.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_sgn_ext[0:0] 1'0 - case - assign $1\LDST_sgn_ext[0:0] 1'0 - end - sync always - update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] - end - attribute \src "libresoc.v:65426.3-65483.6" - process $proc$libresoc.v:65426$3583 - assign { } { } - assign { } { } - assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65427.5-65427.29" - switch \initial - attribute \src "libresoc.v:65427.9-65427.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_is_32b[0:0] 1'0 - case - assign $1\LDST_is_32b[0:0] 1'0 - end - sync always - update \LDST_is_32b $0\LDST_is_32b[0:0] - end - attribute \src "libresoc.v:65484.3-65541.6" - process $proc$libresoc.v:65484$3584 - assign { } { } - assign { } { } - assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:65485.5-65485.29" - switch \initial - attribute \src "libresoc.v:65485.9-65485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_sgn[0:0] 1'0 - case - assign $1\LDST_sgn[0:0] 1'0 - end - sync always - update \LDST_sgn $0\LDST_sgn[0:0] - end - attribute \src "libresoc.v:65542.3-65599.6" - process $proc$libresoc.v:65542$3585 - assign { } { } - assign { } { } - assign $0\LDST_function_unit[11:0] $1\LDST_function_unit[11:0] - attribute \src "libresoc.v:65543.5-65543.29" - switch \initial - attribute \src "libresoc.v:65543.9-65543.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec31_LDST_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec58_LDST_dec58_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_function_unit[11:0] \LDST_dec62_LDST_dec62_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_function_unit[11:0] 12'000000000100 - case - assign $1\LDST_function_unit[11:0] 12'000000000000 - end - sync always - update \LDST_function_unit $0\LDST_function_unit[11:0] - end - attribute \src "libresoc.v:65600.3-65657.6" - process $proc$libresoc.v:65600$3586 - assign { } { } - assign { } { } - assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:65601.5-65601.29" - switch \initial - attribute \src "libresoc.v:65601.9-65601.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_internal_op[6:0] 7'0100110 - case - assign $1\LDST_internal_op[6:0] 7'0000000 - end - sync always - update \LDST_internal_op $0\LDST_internal_op[6:0] - end - attribute \src "libresoc.v:65658.3-65715.6" - process $proc$libresoc.v:65658$3587 - assign { } { } - assign { } { } - assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:65659.5-65659.29" - switch \initial - attribute \src "libresoc.v:65659.9-65659.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_in1_sel[2:0] 3'010 - case - assign $1\LDST_in1_sel[2:0] 3'000 - end - sync always - update \LDST_in1_sel $0\LDST_in1_sel[2:0] - end - attribute \src "libresoc.v:65716.3-65773.6" - process $proc$libresoc.v:65716$3588 - assign { } { } - assign { } { } - assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:65717.5-65717.29" - switch \initial - attribute \src "libresoc.v:65717.9-65717.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_in2_sel[3:0] 4'0011 - case - assign $1\LDST_in2_sel[3:0] 4'0000 - end - sync always - update \LDST_in2_sel $0\LDST_in2_sel[3:0] - end - attribute \src "libresoc.v:65774.3-65831.6" - process $proc$libresoc.v:65774$3589 - assign { } { } - assign { } { } - assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:65775.5-65775.29" - switch \initial - attribute \src "libresoc.v:65775.9-65775.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_cr_in[2:0] 3'000 - case - assign $1\LDST_cr_in[2:0] 3'000 - end - sync always - update \LDST_cr_in $0\LDST_cr_in[2:0] - end - attribute \src "libresoc.v:65832.3-65889.6" - process $proc$libresoc.v:65832$3590 - assign { } { } - assign { } { } - assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:65833.5-65833.29" - switch \initial - attribute \src "libresoc.v:65833.9-65833.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\LDST_cr_out[2:0] 3'000 - case - assign $1\LDST_cr_out[2:0] 3'000 - end - sync always - update \LDST_cr_out $0\LDST_cr_out[2:0] - end - connect \$1 $ternary$libresoc.v:65087$3577_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_D - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_FRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \D_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \D_TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 16 \D_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \EVS_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 output 27 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_AA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 24 \I_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \I_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 11 \LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \MB32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_IS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MDS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MDS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XBI_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \MDS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MDS_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \MD_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \MD_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \MD_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \MD_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \ME32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_MB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_ME - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \M_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \M_SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 23 \OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 20 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 21 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 18 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 output 19 \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire output 22 \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \SC_LEV - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \SC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \SC_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 10 output 31 \SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \TO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \TX_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \TX_XBI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \TX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VA_SHB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VA_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \VA_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VC_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VC_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VC_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \VX_PS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_SIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \VX_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \VX_UIM_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \VX_UIM_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \VX_VRT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \VX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 11 \VX_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFL_FLM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFL_FRB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_L - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XFL_W - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_BHRBE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_DUI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_DUIS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XFX_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XFX_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_SPR - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 \XFX_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XL_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XL_BH - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XL_BO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 output 34 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 15 \XL_OC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XL_S - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 10 output 35 \XL_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XO_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XO_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XO_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XS_RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XS_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XS_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XS_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX2_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_DCMX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_EO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX2_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX2_UIM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX2_UIM_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX2_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 7 \XX2_dc_dm_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX2_dm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX2_dx - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \XX3_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_DM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX3_SHW - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX3_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX3_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX3_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 4 \XX3_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 8 \XX3_XO_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 9 \XX3_XO_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_AX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_AX_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_BX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_BX_B - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_CX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_CX_C - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \XX4_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \XX4_TX - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 6 \XX4_TX_T - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 2 \XX4_XO - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire \X_A - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 output 32 \X_BF - attribute \src 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attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 \form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 7 \function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 12 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 13 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \in3_sel - attribute \src "libresoc.v:66226.7-66226.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 6 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 9 \is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 10 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 output 2 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 6 \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 32 \opcode_switch$1 - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 15 \out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 1 \raw_opcode_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 3 \rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 17 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" - cell $mux $ternary$libresoc.v:68283$3592 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $ternary$libresoc.v:68283$3592_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:68284.9-68310.4" - cell \dec19 \dec19 - connect \dec19_asmcode \dec19_dec19_asmcode - connect \dec19_br \dec19_dec19_br - connect \dec19_cr_in \dec19_dec19_cr_in - connect \dec19_cr_out \dec19_dec19_cr_out - connect \dec19_cry_in \dec19_dec19_cry_in - connect \dec19_cry_out \dec19_dec19_cry_out - connect \dec19_form \dec19_dec19_form - connect \dec19_function_unit \dec19_dec19_function_unit - connect \dec19_in1_sel \dec19_dec19_in1_sel - connect \dec19_in2_sel \dec19_dec19_in2_sel - connect \dec19_in3_sel \dec19_dec19_in3_sel - connect \dec19_internal_op \dec19_dec19_internal_op - connect \dec19_inv_a \dec19_dec19_inv_a - connect \dec19_inv_out \dec19_dec19_inv_out - connect \dec19_is_32b \dec19_dec19_is_32b - connect \dec19_ldst_len \dec19_dec19_ldst_len - connect \dec19_lk \dec19_dec19_lk - connect \dec19_out_sel \dec19_dec19_out_sel - connect \dec19_rc_sel \dec19_dec19_rc_sel - connect \dec19_rsrv \dec19_dec19_rsrv - connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe - connect \dec19_sgn \dec19_dec19_sgn - connect \dec19_sgn_ext \dec19_dec19_sgn_ext - connect \dec19_upd \dec19_dec19_upd - connect \opcode_in \dec19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:68311.9-68337.4" - cell \dec30 \dec30 - connect \dec30_asmcode \dec30_dec30_asmcode - connect \dec30_br \dec30_dec30_br - connect \dec30_cr_in \dec30_dec30_cr_in - connect \dec30_cr_out \dec30_dec30_cr_out - connect \dec30_cry_in \dec30_dec30_cry_in - connect \dec30_cry_out \dec30_dec30_cry_out - connect \dec30_form \dec30_dec30_form - connect \dec30_function_unit \dec30_dec30_function_unit - connect \dec30_in1_sel \dec30_dec30_in1_sel - connect \dec30_in2_sel \dec30_dec30_in2_sel - connect \dec30_in3_sel \dec30_dec30_in3_sel - connect \dec30_internal_op \dec30_dec30_internal_op - connect \dec30_inv_a \dec30_dec30_inv_a - connect \dec30_inv_out \dec30_dec30_inv_out - connect \dec30_is_32b \dec30_dec30_is_32b - connect \dec30_ldst_len \dec30_dec30_ldst_len - connect \dec30_lk \dec30_dec30_lk - connect \dec30_out_sel \dec30_dec30_out_sel - connect \dec30_rc_sel \dec30_dec30_rc_sel - connect \dec30_rsrv \dec30_dec30_rsrv - connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe - connect \dec30_sgn \dec30_dec30_sgn - connect \dec30_sgn_ext \dec30_dec30_sgn_ext - connect \dec30_upd \dec30_dec30_upd - connect \opcode_in \dec30_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:68338.9-68364.4" - cell \dec31 \dec31 - connect \dec31_asmcode \dec31_dec31_asmcode - connect \dec31_br \dec31_dec31_br - connect \dec31_cr_in \dec31_dec31_cr_in - connect \dec31_cr_out \dec31_dec31_cr_out - connect \dec31_cry_in \dec31_dec31_cry_in - connect \dec31_cry_out \dec31_dec31_cry_out - connect \dec31_form \dec31_dec31_form - connect \dec31_function_unit \dec31_dec31_function_unit - connect \dec31_in1_sel \dec31_dec31_in1_sel - connect \dec31_in2_sel \dec31_dec31_in2_sel - connect \dec31_in3_sel \dec31_dec31_in3_sel - connect \dec31_internal_op \dec31_dec31_internal_op - connect \dec31_inv_a \dec31_dec31_inv_a - connect \dec31_inv_out \dec31_dec31_inv_out - connect \dec31_is_32b \dec31_dec31_is_32b - connect \dec31_ldst_len \dec31_dec31_ldst_len - connect \dec31_lk \dec31_dec31_lk - connect \dec31_out_sel \dec31_dec31_out_sel - connect \dec31_rc_sel \dec31_dec31_rc_sel - connect \dec31_rsrv \dec31_dec31_rsrv - connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe - connect \dec31_sgn \dec31_dec31_sgn - connect \dec31_sgn_ext \dec31_dec31_sgn_ext - connect \dec31_upd \dec31_dec31_upd - connect \opcode_in \dec31_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:68365.9-68391.4" - cell \dec58 \dec58 - connect \dec58_asmcode \dec58_dec58_asmcode - connect \dec58_br \dec58_dec58_br - connect \dec58_cr_in \dec58_dec58_cr_in - connect \dec58_cr_out \dec58_dec58_cr_out - connect \dec58_cry_in \dec58_dec58_cry_in - connect \dec58_cry_out \dec58_dec58_cry_out - connect \dec58_form \dec58_dec58_form - connect \dec58_function_unit \dec58_dec58_function_unit - connect \dec58_in1_sel \dec58_dec58_in1_sel - connect \dec58_in2_sel \dec58_dec58_in2_sel - connect \dec58_in3_sel \dec58_dec58_in3_sel - connect \dec58_internal_op \dec58_dec58_internal_op - connect \dec58_inv_a \dec58_dec58_inv_a - connect \dec58_inv_out \dec58_dec58_inv_out - connect \dec58_is_32b \dec58_dec58_is_32b - connect \dec58_ldst_len \dec58_dec58_ldst_len - connect \dec58_lk \dec58_dec58_lk - connect \dec58_out_sel \dec58_dec58_out_sel - connect \dec58_rc_sel \dec58_dec58_rc_sel - connect \dec58_rsrv \dec58_dec58_rsrv - connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe - connect \dec58_sgn \dec58_dec58_sgn - connect \dec58_sgn_ext \dec58_dec58_sgn_ext - connect \dec58_upd \dec58_dec58_upd - connect \opcode_in \dec58_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:68392.9-68418.4" - cell \dec62 \dec62 - connect \dec62_asmcode \dec62_dec62_asmcode - connect \dec62_br \dec62_dec62_br - connect \dec62_cr_in \dec62_dec62_cr_in - connect \dec62_cr_out \dec62_dec62_cr_out - connect \dec62_cry_in \dec62_dec62_cry_in - connect \dec62_cry_out \dec62_dec62_cry_out - connect \dec62_form \dec62_dec62_form - connect \dec62_function_unit \dec62_dec62_function_unit - connect \dec62_in1_sel \dec62_dec62_in1_sel - connect \dec62_in2_sel \dec62_dec62_in2_sel - connect \dec62_in3_sel \dec62_dec62_in3_sel - connect \dec62_internal_op \dec62_dec62_internal_op - connect \dec62_inv_a \dec62_dec62_inv_a - connect \dec62_inv_out \dec62_dec62_inv_out - connect \dec62_is_32b \dec62_dec62_is_32b - connect \dec62_ldst_len \dec62_dec62_ldst_len - connect \dec62_lk \dec62_dec62_lk - connect \dec62_out_sel \dec62_dec62_out_sel - connect \dec62_rc_sel \dec62_dec62_rc_sel - connect \dec62_rsrv \dec62_dec62_rsrv - connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe - connect \dec62_sgn \dec62_dec62_sgn - connect \dec62_sgn_ext \dec62_dec62_sgn_ext - connect \dec62_upd \dec62_dec62_upd - connect \opcode_in \dec62_opcode_in - end - attribute \src "libresoc.v:66226.7-66226.20" - process $proc$libresoc.v:66226$3617 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:68419.3-68557.6" - process $proc$libresoc.v:68419$3593 - assign { } { } - assign { } { } - assign { } { } - assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:68420.5-68420.29" - switch \initial - attribute \src "libresoc.v:68420.9-68420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\asmcode[7:0] \dec19_dec19_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\asmcode[7:0] \dec30_dec30_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\asmcode[7:0] \dec31_dec31_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\asmcode[7:0] \dec58_dec58_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\asmcode[7:0] \dec62_dec62_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\asmcode[7:0] 8'00000111 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\asmcode[7:0] 8'00001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\asmcode[7:0] 8'00000110 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\asmcode[7:0] 8'00001001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\asmcode[7:0] 8'00010001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\asmcode[7:0] 8'00010010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\asmcode[7:0] 8'00010100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\asmcode[7:0] 8'00010101 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\asmcode[7:0] 8'00011101 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\asmcode[7:0] 8'00011111 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\asmcode[7:0] 8'01001110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\asmcode[7:0] 8'01001111 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\asmcode[7:0] 8'01011000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\asmcode[7:0] 8'01011010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\asmcode[7:0] 8'01011110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\asmcode[7:0] 8'01011111 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\asmcode[7:0] 8'01100111 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\asmcode[7:0] 8'01101001 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\asmcode[7:0] 8'10000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\asmcode[7:0] 8'10001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\asmcode[7:0] 8'10001011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\asmcode[7:0] 8'10011000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\asmcode[7:0] 8'10011001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\asmcode[7:0] 8'10011010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\asmcode[7:0] 8'10100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\asmcode[7:0] 8'10101001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\asmcode[7:0] 8'10110010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\asmcode[7:0] 8'10110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\asmcode[7:0] 8'10111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\asmcode[7:0] 8'10111011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\asmcode[7:0] 8'11000011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\asmcode[7:0] 8'11001011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\asmcode[7:0] 8'11001111 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\asmcode[7:0] 8'11010001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\asmcode[7:0] 8'11010010 - case - assign $1\asmcode[7:0] 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\asmcode[7:0] 8'00010011 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\asmcode[7:0] 8'10000110 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\asmcode[7:0] 8'10011100 - case - assign $2\asmcode[7:0] $1\asmcode[7:0] - end - sync always - update \asmcode $0\asmcode[7:0] - end - attribute \src "libresoc.v:68558.3-68699.6" - process $proc$libresoc.v:68558$3594 - assign { } { } - assign { } { } - assign { } { } - assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:68559.5-68559.29" - switch \initial - attribute \src "libresoc.v:68559.9-68559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in1_sel[2:0] \dec19_dec19_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in1_sel[2:0] \dec30_dec30_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in1_sel[2:0] \dec31_dec31_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in1_sel[2:0] \dec58_dec58_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in1_sel[2:0] \dec62_dec62_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in1_sel[2:0] 3'100 - case - assign $1\in1_sel[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in1_sel[2:0] 3'000 - case - assign $2\in1_sel[2:0] $1\in1_sel[2:0] - end - sync always - update \in1_sel $0\in1_sel[2:0] - end - attribute \src "libresoc.v:68700.3-68841.6" - process $proc$libresoc.v:68700$3595 - assign { } { } - assign { } { } - assign { } { } - assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:68701.5-68701.29" - switch \initial - attribute \src "libresoc.v:68701.9-68701.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in2_sel[3:0] \dec19_dec19_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in2_sel[3:0] \dec30_dec30_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in2_sel[3:0] \dec31_dec31_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in2_sel[3:0] \dec58_dec58_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in2_sel[3:0] \dec62_dec62_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in2_sel[3:0] 4'0101 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in2_sel[3:0] 4'0110 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in2_sel[3:0] 4'0111 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in2_sel[3:0] 4'0011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in2_sel[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in2_sel[3:0] 4'0100 - case - assign $1\in2_sel[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in2_sel[3:0] 4'0000 - case - assign $2\in2_sel[3:0] $1\in2_sel[3:0] - end - sync always - update \in2_sel $0\in2_sel[3:0] - end - attribute \src "libresoc.v:68842.3-68983.6" - process $proc$libresoc.v:68842$3596 - assign { } { } - assign { } { } - assign { } { } - assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:68843.5-68843.29" - switch \initial - attribute \src "libresoc.v:68843.9-68843.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\in3_sel[1:0] \dec19_dec19_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\in3_sel[1:0] \dec30_dec30_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\in3_sel[1:0] \dec31_dec31_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\in3_sel[1:0] \dec58_dec58_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\in3_sel[1:0] \dec62_dec62_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\in3_sel[1:0] 2'00 - case - assign $1\in3_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\in3_sel[1:0] 2'00 - case - assign $2\in3_sel[1:0] $1\in3_sel[1:0] - end - sync always - update \in3_sel $0\in3_sel[1:0] - end - attribute \src "libresoc.v:68984.3-69125.6" - process $proc$libresoc.v:68984$3597 - assign { } { } - assign { } { } - assign { } { } - assign $0\out_sel[1:0] $2\out_sel[1:0] - attribute \src "libresoc.v:68985.5-68985.29" - switch \initial - attribute \src "libresoc.v:68985.9-68985.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\out_sel[1:0] \dec19_dec19_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\out_sel[1:0] \dec30_dec30_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\out_sel[1:0] \dec31_dec31_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\out_sel[1:0] \dec58_dec58_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\out_sel[1:0] \dec62_dec62_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\out_sel[1:0] 2'10 - case - assign $1\out_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\out_sel[1:0] 2'01 - case - assign $2\out_sel[1:0] $1\out_sel[1:0] - end - sync always - update \out_sel $0\out_sel[1:0] - end - attribute \src "libresoc.v:69126.3-69267.6" - process $proc$libresoc.v:69126$3598 - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:69127.5-69127.29" - switch \initial - attribute \src "libresoc.v:69127.9-69127.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_in[2:0] \dec19_dec19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_in[2:0] \dec30_dec30_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cr_in[2:0] \dec31_dec31_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cr_in[2:0] \dec58_dec58_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cr_in[2:0] \dec62_dec62_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cr_in[2:0] 3'000 - case - assign $1\cr_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cr_in[2:0] 3'000 - case - assign $2\cr_in[2:0] $1\cr_in[2:0] - end - sync always - update \cr_in $0\cr_in[2:0] - end - attribute \src "libresoc.v:69268.3-69409.6" - process $proc$libresoc.v:69268$3599 - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:69269.5-69269.29" - switch \initial - attribute \src "libresoc.v:69269.9-69269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cr_out[2:0] \dec19_dec19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cr_out[2:0] \dec30_dec30_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cr_out[2:0] \dec31_dec31_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cr_out[2:0] \dec58_dec58_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cr_out[2:0] \dec62_dec62_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cr_out[2:0] 3'000 - case - assign $1\cr_out[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cr_out[2:0] 3'000 - case - assign $2\cr_out[2:0] $1\cr_out[2:0] - end - sync always - update \cr_out $0\cr_out[2:0] - end - attribute \src "libresoc.v:69410.3-69551.6" - process $proc$libresoc.v:69410$3600 - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:69411.5-69411.29" - switch \initial - attribute \src "libresoc.v:69411.9-69411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\ldst_len[3:0] \dec19_dec19_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\ldst_len[3:0] \dec30_dec30_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\ldst_len[3:0] \dec31_dec31_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\ldst_len[3:0] \dec58_dec58_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\ldst_len[3:0] \dec62_dec62_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\ldst_len[3:0] 4'0000 - case - assign $1\ldst_len[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\ldst_len[3:0] 4'0000 - case - assign $2\ldst_len[3:0] $1\ldst_len[3:0] - end - sync always - update \ldst_len $0\ldst_len[3:0] - end - attribute \src "libresoc.v:69552.3-69693.6" - process $proc$libresoc.v:69552$3601 - assign { } { } - assign { } { } - assign { } { } - assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:69553.5-69553.29" - switch \initial - attribute \src "libresoc.v:69553.9-69553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\upd[1:0] \dec19_dec19_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\upd[1:0] \dec30_dec30_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\upd[1:0] \dec31_dec31_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\upd[1:0] \dec58_dec58_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\upd[1:0] \dec62_dec62_upd - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\upd[1:0] 2'00 - case - assign $1\upd[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\upd[1:0] 2'00 - case - assign $2\upd[1:0] $1\upd[1:0] - end - sync always - update \upd $0\upd[1:0] - end - attribute \src "libresoc.v:69694.3-69835.6" - process $proc$libresoc.v:69694$3602 - assign { } { } - assign { } { } - assign { } { } - assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:69695.5-69695.29" - switch \initial - attribute \src "libresoc.v:69695.9-69695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\rc_sel[1:0] \dec19_dec19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\rc_sel[1:0] \dec30_dec30_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\rc_sel[1:0] \dec31_dec31_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\rc_sel[1:0] \dec58_dec58_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\rc_sel[1:0] \dec62_dec62_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\rc_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\rc_sel[1:0] 2'00 - case - assign $1\rc_sel[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\rc_sel[1:0] 2'00 - case - assign $2\rc_sel[1:0] $1\rc_sel[1:0] - end - sync always - update \rc_sel $0\rc_sel[1:0] - end - attribute \src "libresoc.v:69836.3-69977.6" - process $proc$libresoc.v:69836$3603 - assign { } { } - assign { } { } - assign { } { } - assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:69837.5-69837.29" - switch \initial - attribute \src "libresoc.v:69837.9-69837.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_in[1:0] \dec19_dec19_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cry_in[1:0] \dec30_dec30_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cry_in[1:0] \dec31_dec31_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cry_in[1:0] \dec58_dec58_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cry_in[1:0] \dec62_dec62_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cry_in[1:0] 2'00 - case - assign $1\cry_in[1:0] 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cry_in[1:0] 2'00 - case - assign $2\cry_in[1:0] $1\cry_in[1:0] - end - sync always - update \cry_in $0\cry_in[1:0] - end - attribute \src "libresoc.v:69978.3-70119.6" - process $proc$libresoc.v:69978$3604 - assign { } { } - assign { } { } - assign { } { } - assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:69979.5-69979.29" - switch \initial - attribute \src "libresoc.v:69979.9-69979.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_a[0:0] \dec19_dec19_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\inv_a[0:0] \dec30_dec30_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\inv_a[0:0] \dec31_dec31_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\inv_a[0:0] \dec58_dec58_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\inv_a[0:0] \dec62_dec62_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\inv_a[0:0] 1'0 - case - assign $1\inv_a[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\inv_a[0:0] 1'0 - case - assign $2\inv_a[0:0] $1\inv_a[0:0] - end - sync always - update \inv_a $0\inv_a[0:0] - end - attribute \src "libresoc.v:70120.3-70261.6" - process $proc$libresoc.v:70120$3605 - assign { } { } - assign { } { } - assign { } { } - assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:70121.5-70121.29" - switch \initial - attribute \src "libresoc.v:70121.9-70121.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\inv_out[0:0] \dec19_dec19_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\inv_out[0:0] \dec30_dec30_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\inv_out[0:0] \dec31_dec31_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\inv_out[0:0] \dec58_dec58_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\inv_out[0:0] \dec62_dec62_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\inv_out[0:0] 1'0 - case - assign $1\inv_out[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\inv_out[0:0] 1'0 - case - assign $2\inv_out[0:0] $1\inv_out[0:0] - end - sync always - update \inv_out $0\inv_out[0:0] - end - attribute \src "libresoc.v:70262.3-70403.6" - process $proc$libresoc.v:70262$3606 - assign { } { } - assign { } { } - assign { } { } - assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:70263.5-70263.29" - switch \initial - attribute \src "libresoc.v:70263.9-70263.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\cry_out[0:0] \dec19_dec19_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\cry_out[0:0] \dec30_dec30_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\cry_out[0:0] \dec31_dec31_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\cry_out[0:0] \dec58_dec58_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\cry_out[0:0] \dec62_dec62_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\cry_out[0:0] 1'0 - case - assign $1\cry_out[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\cry_out[0:0] 1'0 - case - assign $2\cry_out[0:0] $1\cry_out[0:0] - end - sync always - update \cry_out $0\cry_out[0:0] - end - attribute \src "libresoc.v:70404.3-70545.6" - process $proc$libresoc.v:70404$3607 - assign { } { } - assign { } { } - assign { } { } - assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:70405.5-70405.29" - switch \initial - attribute \src "libresoc.v:70405.9-70405.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\br[0:0] \dec19_dec19_br - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\br[0:0] \dec30_dec30_br - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\br[0:0] \dec31_dec31_br - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\br[0:0] \dec58_dec58_br - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\br[0:0] \dec62_dec62_br - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\br[0:0] 1'0 - case - assign $1\br[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\br[0:0] 1'0 - case - assign $2\br[0:0] $1\br[0:0] - end - sync always - update \br $0\br[0:0] - end - attribute \src "libresoc.v:70546.3-70687.6" - process $proc$libresoc.v:70546$3608 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:70547.5-70547.29" - switch \initial - attribute \src "libresoc.v:70547.9-70547.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgn_ext[0:0] 1'0 - case - assign $1\sgn_ext[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgn_ext[0:0] 1'0 - case - assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] - end - sync always - update \sgn_ext $0\sgn_ext[0:0] - end - attribute \src "libresoc.v:70688.3-70829.6" - process $proc$libresoc.v:70688$3609 - assign { } { } - assign { } { } - assign { } { } - assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:70689.5-70689.29" - switch \initial - attribute \src "libresoc.v:70689.9-70689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\rsrv[0:0] \dec19_dec19_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\rsrv[0:0] \dec30_dec30_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\rsrv[0:0] \dec31_dec31_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\rsrv[0:0] \dec58_dec58_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\rsrv[0:0] \dec62_dec62_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\rsrv[0:0] 1'0 - case - assign $1\rsrv[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\rsrv[0:0] 1'0 - case - assign $2\rsrv[0:0] $1\rsrv[0:0] - end - sync always - update \rsrv $0\rsrv[0:0] - end - attribute \src "libresoc.v:70830.3-70971.6" - process $proc$libresoc.v:70830$3610 - assign { } { } - assign { } { } - assign { } { } - assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:70831.5-70831.29" - switch \initial - attribute \src "libresoc.v:70831.9-70831.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\is_32b[0:0] \dec19_dec19_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\is_32b[0:0] \dec30_dec30_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\is_32b[0:0] \dec31_dec31_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\is_32b[0:0] \dec58_dec58_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\is_32b[0:0] \dec62_dec62_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\is_32b[0:0] 1'0 - case - assign $1\is_32b[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\is_32b[0:0] 1'0 - case - assign $2\is_32b[0:0] $1\is_32b[0:0] - end - sync always - update \is_32b $0\is_32b[0:0] - end - attribute \src "libresoc.v:70972.3-71113.6" - process $proc$libresoc.v:70972$3611 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:70973.5-70973.29" - switch \initial - attribute \src "libresoc.v:70973.9-70973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgn[0:0] \dec19_dec19_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgn[0:0] \dec30_dec30_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgn[0:0] \dec31_dec31_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgn[0:0] \dec58_dec58_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgn[0:0] \dec62_dec62_sgn - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgn[0:0] 1'0 - case - assign $1\sgn[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgn[0:0] 1'0 - case - assign $2\sgn[0:0] $1\sgn[0:0] - end - sync always - update \sgn $0\sgn[0:0] - end - attribute \src "libresoc.v:71114.3-71255.6" - process $proc$libresoc.v:71114$3612 - assign { } { } - assign { } { } - assign { } { } - assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:71115.5-71115.29" - switch \initial - attribute \src "libresoc.v:71115.9-71115.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\lk[0:0] \dec19_dec19_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\lk[0:0] \dec30_dec30_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\lk[0:0] \dec31_dec31_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\lk[0:0] \dec58_dec58_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\lk[0:0] \dec62_dec62_lk - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\lk[0:0] 1'0 - case - assign $1\lk[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\lk[0:0] 1'0 - case - assign $2\lk[0:0] $1\lk[0:0] - end - sync always - update \lk $0\lk[0:0] - end - attribute \src "libresoc.v:71256.3-71397.6" - process $proc$libresoc.v:71256$3613 - assign { } { } - assign { } { } - assign { } { } - assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:71257.5-71257.29" - switch \initial - attribute \src "libresoc.v:71257.9-71257.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\sgl_pipe[0:0] 1'0 - case - assign $1\sgl_pipe[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\sgl_pipe[0:0] 1'1 - case - assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] - end - sync always - update \sgl_pipe $0\sgl_pipe[0:0] - end - attribute \src "libresoc.v:71398.3-71539.6" - process $proc$libresoc.v:71398$3614 - assign { } { } - assign { } { } - assign { } { } - assign $0\function_unit[11:0] $2\function_unit[11:0] - attribute \src "libresoc.v:71399.5-71399.29" - switch \initial - attribute \src "libresoc.v:71399.9-71399.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\function_unit[11:0] \dec19_dec19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\function_unit[11:0] \dec30_dec30_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\function_unit[11:0] \dec31_dec31_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\function_unit[11:0] \dec58_dec58_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\function_unit[11:0] \dec62_dec62_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\function_unit[11:0] 12'000000010000 - case - assign $1\function_unit[11:0] 12'000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\function_unit[11:0] 12'000000000000 - case - assign $2\function_unit[11:0] $1\function_unit[11:0] - end - sync always - update \function_unit $0\function_unit[11:0] - end - attribute \src "libresoc.v:71540.3-71681.6" - process $proc$libresoc.v:71540$3615 - assign { } { } - assign { } { } - assign { } { } - assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:71541.5-71541.29" - switch \initial - attribute \src "libresoc.v:71541.9-71541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\internal_op[6:0] \dec19_dec19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\internal_op[6:0] \dec30_dec30_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\internal_op[6:0] \dec31_dec31_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\internal_op[6:0] \dec58_dec58_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\internal_op[6:0] \dec62_dec62_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\internal_op[6:0] 7'1001001 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\internal_op[6:0] 7'0000110 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\internal_op[6:0] 7'0000111 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\internal_op[6:0] 7'0111111 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\internal_op[6:0] 7'0111111 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\internal_op[6:0] 7'1000011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\internal_op[6:0] 7'1000011 - case - assign $1\internal_op[6:0] 7'0000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\internal_op[6:0] 7'0000101 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\internal_op[6:0] 7'1000100 - case - assign $2\internal_op[6:0] $1\internal_op[6:0] - end - sync always - update \internal_op $0\internal_op[6:0] - end - attribute \src "libresoc.v:71682.3-71823.6" - process $proc$libresoc.v:71682$3616 - assign { } { } - assign { } { } - assign { } { } - assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:71683.5-71683.29" - switch \initial - attribute \src "libresoc.v:71683.9-71683.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 6'010011 - assign { } { } - assign $1\form[4:0] \dec19_dec19_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011110 - assign { } { } - assign $1\form[4:0] \dec30_dec30_form - attribute \src "libresoc.v:0.0-0.0" - case 6'011111 - assign { } { } - assign $1\form[4:0] \dec31_dec31_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111010 - assign { } { } - assign $1\form[4:0] \dec58_dec58_form - attribute \src "libresoc.v:0.0-0.0" - case 6'111110 - assign { } { } - assign $1\form[4:0] \dec62_dec62_form - attribute \src "libresoc.v:0.0-0.0" - case 6'001100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010001 - assign { } { } - assign $1\form[4:0] 5'00011 - attribute \src "libresoc.v:0.0-0.0" - case 6'011100 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'011101 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'010010 - assign { } { } - assign $1\form[4:0] 5'00001 - attribute \src "libresoc.v:0.0-0.0" - case 6'010000 - assign { } { } - assign $1\form[4:0] 5'00010 - attribute \src "libresoc.v:0.0-0.0" - case 6'001011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011001 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'010100 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010101 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'010111 - assign { } { } - assign $1\form[4:0] 5'10011 - attribute \src "libresoc.v:0.0-0.0" - case 6'100110 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100111 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'101101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100100 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'100101 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'001000 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'000011 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011010 - assign { } { } - assign $1\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 6'011011 - assign { } { } - assign $1\form[4:0] 5'00100 - case - assign $1\form[4:0] 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch$1 - attribute \src "libresoc.v:0.0-0.0" - case 32'000000---------------0100000000- - assign { } { } - assign $2\form[4:0] 5'00000 - attribute \src "libresoc.v:0.0-0.0" - case 1610612736 - assign { } { } - assign $2\form[4:0] 5'00100 - attribute \src "libresoc.v:0.0-0.0" - case 32'000001---------------0000000011- - assign { } { } - assign $2\form[4:0] 5'00000 - case - assign $2\form[4:0] $1\form[4:0] - end - sync always - update \form $0\form[4:0] - end - connect \$2 $ternary$libresoc.v:68283$3592_Y - connect \VC_XO \opcode_in [9:0] - connect \VC_VRT \opcode_in [25:21] - connect \VC_VRB \opcode_in [15:11] - connect \VC_VRA \opcode_in [20:16] - connect \VC_Rc \opcode_in [10] - connect \XS_XO \opcode_in [10:2] - connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } - connect \XS_RS \opcode_in [25:21] - connect \XS_Rc \opcode_in [0] - connect \XS_RA \opcode_in [20:16] - connect \VA_XO \opcode_in [5:0] - connect \VA_VRT \opcode_in [25:21] - connect \VA_VRC \opcode_in [10:6] - connect \VA_VRB \opcode_in [15:11] - connect \VA_VRA \opcode_in [20:16] - connect \VA_SHB \opcode_in [9:6] - connect \VA_RT \opcode_in [25:21] - connect \VA_RC \opcode_in [10:6] - connect \VA_RB \opcode_in [15:11] - connect \VA_RA \opcode_in [20:16] - connect \TX_XO \opcode_in [6:1] - connect \TX_XBI \opcode_in [10:7] - connect \TX_UI \opcode_in [15:11] - connect \TX_RA \opcode_in [20:16] - connect \DQE_XO \opcode_in [1:0] - connect \DQE_RT \opcode_in [25:21] - connect \DQE_RA \opcode_in [20:16] - connect \XO_XO \opcode_in [9:1] - connect \XO_RT \opcode_in [25:21] - connect \XO_Rc \opcode_in [0] - connect \XO_RB \opcode_in [15:11] - connect \XO_RA \opcode_in [20:16] - connect \XO_OE \opcode_in [10] - connect \all_PO \opcode_in [31:26] - connect \all_OPCD \opcode_in [31:26] - connect \MD_XO \opcode_in [4:2] - connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } - connect \MD_RS \opcode_in [25:21] - connect \MD_Rc \opcode_in [0] - connect \MD_RA \opcode_in [20:16] - connect \MD_me \opcode_in [10:5] - connect \MD_mb \opcode_in [10:5] - connect \M_SH \opcode_in [15:11] - connect \M_RS \opcode_in [25:21] - connect \M_Rc \opcode_in [0] - connect \M_RB \opcode_in [15:11] - connect \M_RA \opcode_in [20:16] - connect \M_ME \opcode_in [5:1] - connect \M_MB \opcode_in [10:6] - connect \SC_XO_1 \opcode_in [1:0] - connect \SC_XO \opcode_in [1] - connect \SC_LEV \opcode_in [11:5] - connect \MDS_XO \opcode_in [4:1] - connect \MDS_XBI_1 \opcode_in [10:7] - connect \MDS_XBI \opcode_in [10:7] - connect \MDS_RS \opcode_in [25:21] - connect \MDS_Rc \opcode_in [0] - connect \MDS_RB \opcode_in [15:11] - connect \MDS_RA \opcode_in [20:16] - connect \MDS_me \opcode_in [10:5] - connect \MDS_mb \opcode_in [10:5] - connect \MDS_IS \opcode_in [25:21] - connect \MDS_IB \opcode_in [15:11] - connect \Z23_XO \opcode_in [8:1] - connect \Z23_TE \opcode_in [20:16] - connect \Z23_RMC \opcode_in [10:9] - connect \Z23_Rc \opcode_in [0] - connect \Z23_R \opcode_in [16] - connect \Z23_FRTp \opcode_in [25:21] - connect \Z23_FRT \opcode_in [25:21] - connect \Z23_FRBp \opcode_in [15:11] - connect \Z23_FRB \opcode_in [15:11] - connect \Z23_FRAp \opcode_in [20:16] - connect \Z23_FRA \opcode_in [20:16] - connect \XFL_XO \opcode_in [10:1] - connect \XFL_W \opcode_in [16] - connect \XFL_Rc \opcode_in [0] - connect \XFL_L \opcode_in [25] - connect \XFL_FRB \opcode_in [15:11] - connect \XFL_FLM \opcode_in [24:17] - connect \VX_XO_1 \opcode_in [10:0] - connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } - connect \VX_VRT \opcode_in [25:21] - connect \VX_VRB \opcode_in [15:11] - connect \VX_VRA \opcode_in [20:16] - connect \VX_UIM_3 \opcode_in [17:16] - connect \VX_UIM_2 \opcode_in [18:16] - connect \VX_UIM_1 \opcode_in [19:16] - connect \VX_UIM \opcode_in [20:16] - connect \VX_SIM \opcode_in [20:16] - connect \VX_RT \opcode_in [25:21] - connect \VX_RA \opcode_in [20:16] - connect \VX_PS \opcode_in [9] - connect \VX_EO \opcode_in [20:16] - connect \DS_XO \opcode_in [1:0] - connect \DS_VRT \opcode_in [25:21] - connect \DS_VRS \opcode_in [25:21] - connect \DS_RT \opcode_in [25:21] - connect \DS_RSp \opcode_in [25:21] - connect \DS_RS \opcode_in [25:21] - connect \DS_RA \opcode_in [20:16] - connect \DS_FRTp \opcode_in [25:21] - connect \DS_FRSp \opcode_in [25:21] - connect \DS_DS \opcode_in [15:2] - connect \DQ_XO \opcode_in [2:0] - connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_T \opcode_in [25:21] - connect \DQ_TX \opcode_in [3] - connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } - connect \DQ_S \opcode_in [25:21] - connect \DQ_SX \opcode_in [3] - connect \DQ_RTp \opcode_in [25:21] - connect \DQ_RA \opcode_in [20:16] - connect \DQ_PT \opcode_in [3:0] - connect \DQ_DQ \opcode_in [15:4] - connect \DX_XO \opcode_in [5:1] - connect \DX_RT \opcode_in [25:21] - connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } - connect \DX_d2 \opcode_in [0] - connect \DX_d1 \opcode_in [20:16] - connect \DX_d0 \opcode_in [15:6] - connect \XFX_XO \opcode_in [10:1] - connect \XFX_SPR \opcode_in [20:11] - connect \XFX_RT \opcode_in [25:21] - connect \XFX_RS \opcode_in [25:21] - connect \XFX_FXM \opcode_in [19:12] - connect \XFX_DUIS \opcode_in [20:11] - connect \XFX_DUI \opcode_in [25:21] - connect \XFX_BHRBE \opcode_in [20:11] - connect \EVS_BFA \opcode_in [2:0] - connect \Z22_XO \opcode_in [9:1] - connect \Z22_SH \opcode_in [15:10] - connect \Z22_Rc \opcode_in [0] - connect \Z22_FRTp \opcode_in [25:21] - connect \Z22_FRT \opcode_in [25:21] - connect \Z22_FRAp \opcode_in [20:16] - connect \Z22_FRA \opcode_in [20:16] - connect \Z22_DGM \opcode_in [15:10] - connect \Z22_DCM \opcode_in [15:10] - connect \Z22_BF \opcode_in [25:23] - connect \XX2_XO_1 \opcode_in [10:2] - connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } - connect \XX2_UIM_1 \opcode_in [17:16] - connect \XX2_UIM \opcode_in [19:16] - connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX2_T \opcode_in [25:21] - connect \XX2_TX \opcode_in [0] - connect \XX2_RT \opcode_in [25:21] - connect \XX2_EO \opcode_in [20:16] - connect \XX2_DCMX \opcode_in [22:16] - connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } - connect \XX2_dx \opcode_in [20:16] - connect \XX2_dm \opcode_in [2] - connect \XX2_dc \opcode_in [6] - connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX2_B \opcode_in [15:11] - connect \XX2_BX \opcode_in [1] - connect \XX2_BF \opcode_in [25:23] - connect \D_UI \opcode_in [15:0] - connect \D_TO \opcode_in [25:21] - connect \D_SI \opcode_in [15:0] - connect \D_RT \opcode_in [25:21] - connect \D_RS \opcode_in [25:21] - connect \D_RA \opcode_in [20:16] - connect \D_L \opcode_in [21] - connect \D_FRT \opcode_in [25:21] - connect \D_FRS \opcode_in [25:21] - connect \D_D \opcode_in [15:0] - connect \D_BF \opcode_in [25:23] - connect \A_XO \opcode_in [5:1] - connect \A_RT \opcode_in [25:21] - connect \A_Rc \opcode_in [0] - connect \A_RB \opcode_in [15:11] - connect \A_RA \opcode_in [20:16] - connect \A_FRT \opcode_in [25:21] - connect \A_FRC \opcode_in [10:6] - connect \A_FRB \opcode_in [15:11] - connect \A_FRA \opcode_in [20:16] - connect \A_BC \opcode_in [10:6] - connect \XL_XO \opcode_in [10:1] - connect \XL_S \opcode_in [11] - connect \XL_OC \opcode_in [25:11] - connect \XL_LK \opcode_in [0] - connect \XL_BT \opcode_in [25:21] - connect \XL_BO_1 \opcode_in [25:21] - connect \XL_BO \opcode_in [25:21] - connect \XL_BI \opcode_in [20:16] - connect \XL_BH \opcode_in [12:11] - connect \XL_BFA \opcode_in [20:18] - connect \XL_BF \opcode_in [25:23] - connect \XL_BB \opcode_in [15:11] - connect \XL_BA \opcode_in [20:16] - connect \XX4_XO \opcode_in [5:4] - connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX4_T \opcode_in [25:21] - connect \XX4_TX \opcode_in [0] - connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } - connect \XX4_C \opcode_in [10:6] - connect \XX4_CX \opcode_in [3] - connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX4_B \opcode_in [15:11] - connect \XX4_BX \opcode_in [1] - connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX4_A \opcode_in [20:16] - connect \XX4_AX \opcode_in [2] - connect \XX3_XO_2 \opcode_in [9:1] - connect \XX3_XO_1 \opcode_in [10:3] - connect \XX3_XO \opcode_in [10:7] - connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \XX3_T \opcode_in [25:21] - connect \XX3_TX \opcode_in [0] - connect \XX3_SHW \opcode_in [9:8] - connect \XX3_Rc \opcode_in [10] - connect \XX3_DM \opcode_in [9:8] - connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } - connect \XX3_B \opcode_in [15:11] - connect \XX3_BX \opcode_in [1] - connect \XX3_BF \opcode_in [25:23] - connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } - connect \XX3_A \opcode_in [20:16] - connect \XX3_AX \opcode_in [2] - connect \I_LK \opcode_in [0] - connect \I_LI \opcode_in [25:2] - connect \I_AA \opcode_in [1] - connect \B_LK \opcode_in [0] - connect \B_BO \opcode_in [25:21] - connect \B_BI \opcode_in [20:16] - connect \B_BD \opcode_in [15:2] - connect \B_AA \opcode_in [1] - connect \X_XO_1 \opcode_in [8:1] - connect \X_XO \opcode_in [10:1] - connect \X_WC \opcode_in [22:21] - connect \X_W \opcode_in [16] - connect \X_VRT \opcode_in [25:21] - connect \X_VRS \opcode_in [25:21] - connect \X_UIM \opcode_in [20:16] - connect \X_U \opcode_in [15:12] - connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } - connect \X_TX \opcode_in [0] - connect \X_TO \opcode_in [25:21] - connect \X_TH \opcode_in [25:21] - connect \X_TBR \opcode_in [20:11] - connect \X_T \opcode_in [25:21] - connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } - connect \X_SX \opcode_in [0] - connect \X_SR \opcode_in [19:16] - connect \X_SP \opcode_in [20:19] - connect \X_SI \opcode_in [15:11] - connect \X_SH \opcode_in [15:11] - connect \X_S \opcode_in [25:21] - connect \X_RTp \opcode_in [25:21] - connect \X_RT \opcode_in [25:21] - connect \X_RSp \opcode_in [25:21] - connect \X_RS \opcode_in [25:21] - connect \X_RO \opcode_in [0] - connect \X_RM \opcode_in [12:11] - connect \X_RIC \opcode_in [19:18] - connect \X_Rc \opcode_in [0] - connect \X_RB \opcode_in [15:11] - connect \X_RA \opcode_in [20:16] - connect \X_R_1 \opcode_in [16] - connect \X_R \opcode_in [21] - connect \X_PRS \opcode_in [17] - connect \X_NB \opcode_in [15:11] - connect \X_MO \opcode_in [25:21] - connect \X_L3 \opcode_in [17:16] - connect \X_L1 \opcode_in [16] - connect \X_L \opcode_in [21] - connect \X_L2 \opcode_in [22:21] - connect \X_IMM8 \opcode_in [18:11] - connect \X_IH \opcode_in [23:21] - connect \X_FRTp \opcode_in [25:21] - connect \X_FRT \opcode_in [25:21] - connect \X_FRSp \opcode_in [25:21] - connect \X_FRS \opcode_in [25:21] - connect \X_FRBp \opcode_in [15:11] - connect \X_FRB \opcode_in [15:11] - connect \X_FRAp \opcode_in [20:16] - connect \X_FRA \opcode_in [20:16] - connect \X_FC \opcode_in [15:11] - connect \X_EX \opcode_in [0] - connect \X_EO_1 \opcode_in [20:16] - connect \X_EO \opcode_in [20:19] - connect \X_E_1 \opcode_in [19:16] - connect \X_E \opcode_in [15] - connect \X_DRM \opcode_in [13:11] - connect \X_DCMX \opcode_in [22:16] - connect \X_CT \opcode_in [24:21] - connect \X_BO \opcode_in [25:21] - connect \X_BFA \opcode_in [20:18] - connect \X_BF \opcode_in [25:23] - connect \X_A \opcode_in [25] - connect \SPR \opcode_in [20:11] - connect \MB \opcode_in [10:6] - connect \ME \opcode_in [5:1] - connect \SH \opcode_in [15:11] - connect \BC \opcode_in [10:6] - connect \TO \opcode_in [25:21] - connect \DS \opcode_in [15:2] - connect \D \opcode_in [15:0] - connect \BH \opcode_in [12:11] - connect \BI \opcode_in [20:16] - connect \BO \opcode_in [25:21] - connect \FXM \opcode_in [19:12] - connect \BT \opcode_in [25:21] - connect \BA \opcode_in [20:16] - connect \BB \opcode_in [15:11] - connect \CR \opcode_in [10:1] - connect \BF \opcode_in [25:23] - connect \BD \opcode_in [15:2] - connect \OE \opcode_in [10] - connect \Rc \opcode_in [0] - connect \AA \opcode_in [1] - connect \LK \opcode_in [0] - connect \LI \opcode_in [25:2] - connect \ME32 \opcode_in [5:1] - connect \MB32 \opcode_in [10:6] - connect \sh { \opcode_in [1] \opcode_in [15:11] } - connect \SH32 \opcode_in [15:11] - connect \L \opcode_in [21] - connect \UI \opcode_in [15:0] - connect \SI \opcode_in [15:0] - connect \RB \opcode_in [15:11] - connect \RA \opcode_in [20:16] - connect \RT \opcode_in [25:21] - connect \RS \opcode_in [25:21] - connect \opcode_in \$2 - connect \opcode_switch$1 \opcode_in - connect \dec62_opcode_in \opcode_in - connect \dec58_opcode_in \opcode_in - connect \dec31_opcode_in \opcode_in - connect \dec30_opcode_in \opcode_in - connect \dec19_opcode_in \opcode_in - connect \opcode_switch \opcode_in [31:26] -end -attribute \src "libresoc.v:72162.1-73669.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" -attribute \generator "nMigen" -module \dec19 - attribute \src "libresoc.v:72680.3-72731.6" - wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:72888.3-72939.6" - wire $0\dec19_br[0:0] - attribute \src "libresoc.v:73564.3-73615.6" - wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:73616.3-73667.6" - wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:72628.3-72679.6" - wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:72836.3-72887.6" - wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:73304.3-73355.6" - wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:72420.3-72471.6" - wire width 12 $0\dec19_function_unit[11:0] - attribute \src "libresoc.v:73356.3-73407.6" - wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:73408.3-73459.6" - wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:73460.3-73511.6" - wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:72992.3-73043.6" - wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:72732.3-72783.6" - wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:72784.3-72835.6" - wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:73096.3-73147.6" - wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:72472.3-72523.6" - wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:73200.3-73251.6" - wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:73512.3-73563.6" - wire width 2 $0\dec19_out_sel[1:0] - attribute \src "libresoc.v:72576.3-72627.6" - wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:73044.3-73095.6" - wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:73252.3-73303.6" - wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:73148.3-73199.6" - wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:72940.3-72991.6" - wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:72524.3-72575.6" - wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:72163.7-72163.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:72680.3-72731.6" - wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:72888.3-72939.6" - wire $1\dec19_br[0:0] - attribute \src "libresoc.v:73564.3-73615.6" - wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:73616.3-73667.6" - wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:72628.3-72679.6" - wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:72836.3-72887.6" - wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:73304.3-73355.6" - wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:72420.3-72471.6" - wire width 12 $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:73356.3-73407.6" - wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:73408.3-73459.6" - wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:73460.3-73511.6" - wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:72992.3-73043.6" - wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:72732.3-72783.6" - wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:72784.3-72835.6" - wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:73096.3-73147.6" - wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:72472.3-72523.6" - wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:73200.3-73251.6" - wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:73512.3-73563.6" - wire width 2 $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:72576.3-72627.6" - wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:73044.3-73095.6" - wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:73252.3-73303.6" - wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:73148.3-73199.6" - wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:72940.3-72991.6" - wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:72524.3-72575.6" - wire width 2 $1\dec19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute 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\enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec19_upd - attribute \src "libresoc.v:72163.7-72163.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \src "libresoc.v:72163.7-72163.20" - process $proc$libresoc.v:72163$3642 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:72420.3-72471.6" - process $proc$libresoc.v:72420$3618 - assign { } { } - assign { } { } - assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] - attribute \src "libresoc.v:72421.5-72421.29" - switch \initial - attribute \src "libresoc.v:72421.9-72421.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_function_unit[11:0] 12'000010000000 - case - assign $1\dec19_function_unit[11:0] 12'000000000000 - end - sync always - update \dec19_function_unit $0\dec19_function_unit[11:0] - end - attribute \src "libresoc.v:72472.3-72523.6" - process $proc$libresoc.v:72472$3619 - assign { } { } - assign { } { } - assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:72473.5-72473.29" - switch \initial - attribute \src "libresoc.v:72473.9-72473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_ldst_len[3:0] 4'0000 - case - assign $1\dec19_ldst_len[3:0] 4'0000 - end - sync always - update \dec19_ldst_len $0\dec19_ldst_len[3:0] - end - attribute \src "libresoc.v:72524.3-72575.6" - process $proc$libresoc.v:72524$3620 - assign { } { } - assign { } { } - assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:72525.5-72525.29" - switch \initial - attribute \src "libresoc.v:72525.9-72525.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_upd[1:0] 2'00 - case - assign $1\dec19_upd[1:0] 2'00 - end - sync always - update \dec19_upd $0\dec19_upd[1:0] - end - attribute \src "libresoc.v:72576.3-72627.6" - process $proc$libresoc.v:72576$3621 - assign { } { } - assign { } { } - assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:72577.5-72577.29" - switch \initial - attribute \src "libresoc.v:72577.9-72577.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_rc_sel[1:0] 2'00 - case - assign $1\dec19_rc_sel[1:0] 2'00 - end - sync always - update \dec19_rc_sel $0\dec19_rc_sel[1:0] - end - attribute \src "libresoc.v:72628.3-72679.6" - process $proc$libresoc.v:72628$3622 - assign { } { } - assign { } { } - assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:72629.5-72629.29" - switch \initial - attribute \src "libresoc.v:72629.9-72629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cry_in[1:0] 2'00 - case - assign $1\dec19_cry_in[1:0] 2'00 - end - sync always - update \dec19_cry_in $0\dec19_cry_in[1:0] - end - attribute \src "libresoc.v:72680.3-72731.6" - process $proc$libresoc.v:72680$3623 - assign { } { } - assign { } { } - assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:72681.5-72681.29" - switch \initial - attribute \src "libresoc.v:72681.9-72681.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'00011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'10010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_asmcode[7:0] 8'01001000 - case - assign $1\dec19_asmcode[7:0] 8'00000000 - end - sync always - update \dec19_asmcode $0\dec19_asmcode[7:0] - end - attribute \src "libresoc.v:72732.3-72783.6" - process $proc$libresoc.v:72732$3624 - assign { } { } - assign { } { } - assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:72733.5-72733.29" - switch \initial - attribute \src "libresoc.v:72733.9-72733.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_inv_a[0:0] 1'0 - case - assign $1\dec19_inv_a[0:0] 1'0 - end - sync always - update \dec19_inv_a $0\dec19_inv_a[0:0] - end - attribute \src "libresoc.v:72784.3-72835.6" - process $proc$libresoc.v:72784$3625 - assign { } { } - assign { } { } - assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:72785.5-72785.29" - switch \initial - attribute \src "libresoc.v:72785.9-72785.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_inv_out[0:0] 1'0 - case - assign $1\dec19_inv_out[0:0] 1'0 - end - sync always - update \dec19_inv_out $0\dec19_inv_out[0:0] - end - attribute \src "libresoc.v:72836.3-72887.6" - process $proc$libresoc.v:72836$3626 - assign { } { } - assign { } { } - assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:72837.5-72837.29" - switch \initial - attribute \src "libresoc.v:72837.9-72837.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cry_out[0:0] 1'0 - case - assign $1\dec19_cry_out[0:0] 1'0 - end - sync always - update \dec19_cry_out $0\dec19_cry_out[0:0] - end - attribute \src "libresoc.v:72888.3-72939.6" - process $proc$libresoc.v:72888$3627 - assign { } { } - assign { } { } - assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:72889.5-72889.29" - switch \initial - attribute \src "libresoc.v:72889.9-72889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_br[0:0] 1'0 - case - assign $1\dec19_br[0:0] 1'0 - end - sync always - update \dec19_br $0\dec19_br[0:0] - end - attribute \src "libresoc.v:72940.3-72991.6" - process $proc$libresoc.v:72940$3628 - assign { } { } - assign { } { } - assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:72941.5-72941.29" - switch \initial - attribute \src "libresoc.v:72941.9-72941.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgn_ext[0:0] 1'0 - case - assign $1\dec19_sgn_ext[0:0] 1'0 - end - sync always - update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] - end - attribute \src "libresoc.v:72992.3-73043.6" - process $proc$libresoc.v:72992$3629 - assign { } { } - assign { } { } - assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:72993.5-72993.29" - switch \initial - attribute \src "libresoc.v:72993.9-72993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'0100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_internal_op[6:0] 7'1000110 - case - assign $1\dec19_internal_op[6:0] 7'0000000 - end - sync always - update \dec19_internal_op $0\dec19_internal_op[6:0] - end - attribute \src "libresoc.v:73044.3-73095.6" - process $proc$libresoc.v:73044$3630 - assign { } { } - assign { } { } - assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:73045.5-73045.29" - switch \initial - attribute \src "libresoc.v:73045.9-73045.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_rsrv[0:0] 1'0 - case - assign $1\dec19_rsrv[0:0] 1'0 - end - sync always - update \dec19_rsrv $0\dec19_rsrv[0:0] - end - attribute \src "libresoc.v:73096.3-73147.6" - process $proc$libresoc.v:73096$3631 - assign { } { } - assign { } { } - assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:73097.5-73097.29" - switch \initial - attribute \src "libresoc.v:73097.9-73097.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_is_32b[0:0] 1'0 - case - assign $1\dec19_is_32b[0:0] 1'0 - end - sync always - update \dec19_is_32b $0\dec19_is_32b[0:0] - end - attribute \src "libresoc.v:73148.3-73199.6" - process $proc$libresoc.v:73148$3632 - assign { } { } - assign { } { } - assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:73149.5-73149.29" - switch \initial - attribute \src "libresoc.v:73149.9-73149.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgn[0:0] 1'0 - case - assign $1\dec19_sgn[0:0] 1'0 - end - sync always - update \dec19_sgn $0\dec19_sgn[0:0] - end - attribute \src "libresoc.v:73200.3-73251.6" - process $proc$libresoc.v:73200$3633 - assign { } { } - assign { } { } - assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:73201.5-73201.29" - switch \initial - attribute \src "libresoc.v:73201.9-73201.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_lk[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_lk[0:0] 1'0 - case - assign $1\dec19_lk[0:0] 1'0 - end - sync always - update \dec19_lk $0\dec19_lk[0:0] - end - attribute \src "libresoc.v:73252.3-73303.6" - process $proc$libresoc.v:73252$3634 - assign { } { } - assign { } { } - assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:73253.5-73253.29" - switch \initial - attribute \src "libresoc.v:73253.9-73253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_sgl_pipe[0:0] 1'0 - case - assign $1\dec19_sgl_pipe[0:0] 1'0 - end - sync always - update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] - end - attribute \src "libresoc.v:73304.3-73355.6" - process $proc$libresoc.v:73304$3635 - assign { } { } - assign { } { } - assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:73305.5-73305.29" - switch \initial - attribute \src "libresoc.v:73305.9-73305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_form[4:0] 5'01001 - case - assign $1\dec19_form[4:0] 5'00000 - end - sync always - update \dec19_form $0\dec19_form[4:0] - end - attribute \src "libresoc.v:73356.3-73407.6" - process $proc$libresoc.v:73356$3636 - assign { } { } - assign { } { } - assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:73357.5-73357.29" - switch \initial - attribute \src "libresoc.v:73357.9-73357.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in1_sel[2:0] 3'011 - case - assign $1\dec19_in1_sel[2:0] 3'000 - end - sync always - update \dec19_in1_sel $0\dec19_in1_sel[2:0] - end - attribute \src "libresoc.v:73408.3-73459.6" - process $proc$libresoc.v:73408$3637 - assign { } { } - assign { } { } - assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:73409.5-73409.29" - switch \initial - attribute \src "libresoc.v:73409.9-73409.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in2_sel[3:0] 4'1100 - case - assign $1\dec19_in2_sel[3:0] 4'0000 - end - sync always - update \dec19_in2_sel $0\dec19_in2_sel[3:0] - end - attribute \src "libresoc.v:73460.3-73511.6" - process $proc$libresoc.v:73460$3638 - assign { } { } - assign { } { } - assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:73461.5-73461.29" - switch \initial - attribute \src "libresoc.v:73461.9-73461.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_in3_sel[1:0] 2'00 - case - assign $1\dec19_in3_sel[1:0] 2'00 - end - sync always - update \dec19_in3_sel $0\dec19_in3_sel[1:0] - end - attribute \src "libresoc.v:73512.3-73563.6" - process $proc$libresoc.v:73512$3639 - assign { } { } - assign { } { } - assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] - attribute \src "libresoc.v:73513.5-73513.29" - switch \initial - attribute \src "libresoc.v:73513.9-73513.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_out_sel[1:0] 2'00 - case - assign $1\dec19_out_sel[1:0] 2'00 - end - sync always - update \dec19_out_sel $0\dec19_out_sel[1:0] - end - attribute \src "libresoc.v:73564.3-73615.6" - process $proc$libresoc.v:73564$3640 - assign { } { } - assign { } { } - assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:73565.5-73565.29" - switch \initial - attribute \src "libresoc.v:73565.9-73565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cr_in[2:0] 3'000 - case - assign $1\dec19_cr_in[2:0] 3'000 - end - sync always - update \dec19_cr_in $0\dec19_cr_in[2:0] - end - attribute \src "libresoc.v:73616.3-73667.6" - process $proc$libresoc.v:73616$3641 - assign { } { } - assign { } { } - assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:73617.5-73617.29" - switch \initial - attribute \src "libresoc.v:73617.9-73617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110100001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0011000001 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000010000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1000110000 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010110 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\dec19_cr_out[2:0] 3'000 - case - assign $1\dec19_cr_out[2:0] 3'000 - end - sync always - update \dec19_cr_out $0\dec19_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:73673.1-75710.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2" -attribute \generator "nMigen" -module \dec2 - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\cr_in1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\cr_in2$1[2:0]$3661 - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\cr_in2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\cr_in2_ok$2[0:0]$3662 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $0\ea[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\ea_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal$3[0:0]$3664 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal$4[0:0]$3665 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal$5[0:0]$3666 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal$6[0:0]$3667 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal$7[0:0]$3668 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal$8[0:0]$3669 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal$9[0:0]$3670 - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\exc_$signal[0:0]$3663 - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 12 $0\fn_unit[11:0] - attribute \src "libresoc.v:73674.7-73674.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\is_32bit[0:0] - attribute \src "libresoc.v:75464.3-75483.6" - wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\lk[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $0\reg1[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $0\reg2[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $0\reg3[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $0\rego[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\rego_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\spro_ok[0:0] - attribute \src "libresoc.v:75418.3-75427.6" - wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:75454.3-75463.6" - wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:75428.3-75443.6" - wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:75444.3-75453.6" - wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $0\xer_out[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\cr_in1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\cr_in2$1[2:0]$3671 - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\cr_in2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\cr_in2_ok$2[0:0]$3672 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $1\ea[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\ea_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal$3[0:0]$3674 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal$4[0:0]$3675 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal$5[0:0]$3676 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal$6[0:0]$3677 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal$7[0:0]$3678 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal$8[0:0]$3679 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal$9[0:0]$3680 - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\exc_$signal[0:0]$3673 - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 12 $1\fn_unit[11:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\is_32bit[0:0] - attribute \src "libresoc.v:75464.3-75483.6" - wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\lk[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\rc_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $1\reg1[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $1\reg2[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $1\reg3[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $1\rego[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\rego_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\spro_ok[0:0] - attribute \src "libresoc.v:75418.3-75427.6" - wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:75454.3-75463.6" - wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:75428.3-75443.6" - wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:75444.3-75453.6" - wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $1\xer_out[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $2\cr_in1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $2\cr_in2$1[2:0]$3681 - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $2\cr_in2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\cr_in2_ok$2[0:0]$3682 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 5 $2\ea[4:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\ea_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal$3[0:0]$3684 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal$4[0:0]$3685 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal$5[0:0]$3686 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal$6[0:0]$3687 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal$7[0:0]$3688 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal$8[0:0]$3689 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal$9[0:0]$3690 - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\exc_$signal[0:0]$3683 - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:75484.3-75641.6" - wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:75484.3-75641.6" - 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parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $eq$libresoc.v:75271$3649_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - cell $eq $eq$libresoc.v:75272$3650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0111111 - connect \Y $eq$libresoc.v:75272$3650_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" - cell $eq $eq$libresoc.v:75276$3654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $eq$libresoc.v:75276$3654_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" - cell $or $or$libresoc.v:75267$3645 - parameter \A_SIGNED 0 - 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assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:75429.5-75429.29" - switch \initial - attribute \src "libresoc.v:75429.9-75429.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" - switch \$42 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_xer_in[2:0] 3'111 - case - assign $1\tmp_xer_in[2:0] 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" - switch \$44 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\tmp_xer_in[2:0] 3'001 - case - assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] - end - sync always - update \tmp_xer_in $0\tmp_xer_in[2:0] - end - attribute \src "libresoc.v:75444.3-75453.6" - process $proc$libresoc.v:75444$3657 - assign { } { } - assign { } { } - assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:75445.5-75445.29" - switch \initial - attribute \src "libresoc.v:75445.9-75445.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" - switch \$46 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_xer_out[0:0] 1'1 - case - assign $1\tmp_xer_out[0:0] 1'0 - end - sync always - update \tmp_xer_out $0\tmp_xer_out[0:0] - end - attribute \src "libresoc.v:75454.3-75463.6" - process $proc$libresoc.v:75454$3658 - assign { } { } - assign { } { } - assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:75455.5-75455.29" - switch \initial - attribute \src "libresoc.v:75455.9-75455.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - switch \$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 - case - assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 - end - sync always - update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] - end - attribute \src "libresoc.v:75464.3-75483.6" - process $proc$libresoc.v:75464$3659 - assign { } { } - assign { } { } - assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:75465.5-75465.29" - switch \initial - attribute \src "libresoc.v:75465.9-75465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" - switch \dec_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 - assign { } { } - assign $1\is_priv_insn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 , 7'0110001 - assign { } { } - assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" - switch \tmp_tmp_insn [20] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\is_priv_insn[0:0] 1'1 - case - assign $2\is_priv_insn[0:0] 1'0 - end - case - assign $1\is_priv_insn[0:0] 1'0 - end - sync always - update \is_priv_insn $0\is_priv_insn[0:0] - end - attribute \src "libresoc.v:75484.3-75641.6" - process $proc$libresoc.v:75484$3660 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - assign $0\spr1[9:0] $1\spr1[9:0] - assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - assign $0\msr[63:0] $1\msr[63:0] - assign $0\ea_ok[0:0] $1\ea_ok[0:0] - assign $0\ea[4:0] $1\ea[4:0] - assign { } { } - assign $0\cr_out[2:0] $1\cr_out[2:0] - assign $0\lk[0:0] $1\lk[0:0] - assign $0\cia[63:0] $1\cia[63:0] - assign $0\cr_in1[2:0] $1\cr_in1[2:0] - assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] - assign $0\cr_in2[2:0] $1\cr_in2[2:0] - assign $0\cr_in2$1[2:0]$3661 $1\cr_in2$1[2:0]$3671 - assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] - assign $0\cr_in2_ok$2[0:0]$3662 $1\cr_in2_ok$2[0:0]$3672 - assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] - assign $0\cr_rd[7:0] $1\cr_rd[7:0] - assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] - assign $0\cr_wr[7:0] $1\cr_wr[7:0] - assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] - assign $0\exc_$signal[0:0]$3663 $1\exc_$signal[0:0]$3673 - assign $0\exc_$signal$3[0:0]$3664 $1\exc_$signal$3[0:0]$3674 - assign $0\exc_$signal$4[0:0]$3665 $1\exc_$signal$4[0:0]$3675 - assign $0\exc_$signal$5[0:0]$3666 $1\exc_$signal$5[0:0]$3676 - assign $0\exc_$signal$6[0:0]$3667 $1\exc_$signal$6[0:0]$3677 - assign $0\exc_$signal$7[0:0]$3668 $1\exc_$signal$7[0:0]$3678 - assign $0\exc_$signal$8[0:0]$3669 $1\exc_$signal$8[0:0]$3679 - assign $0\exc_$signal$9[0:0]$3670 $1\exc_$signal$9[0:0]$3680 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fn_unit[11:0] $1\fn_unit[11:0] - assign $0\input_carry[1:0] $1\input_carry[1:0] - assign $0\insn[31:0] $1\insn[31:0] - assign $0\insn_type[6:0] $1\insn_type[6:0] - assign $0\is_32bit[0:0] $1\is_32bit[0:0] - assign $0\oe[0:0] $1\oe[0:0] - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - assign $0\reg1[4:0] $1\reg1[4:0] - assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] - assign $0\reg2[4:0] $1\reg2[4:0] - assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] - assign $0\reg3[4:0] $1\reg3[4:0] - assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] - assign $0\rego[4:0] $1\rego[4:0] - assign $0\rego_ok[0:0] $1\rego_ok[0:0] - assign $0\spro[9:0] $1\spro[9:0] - assign $0\spro_ok[0:0] $1\spro_ok[0:0] - assign $0\trapaddr[12:0] $1\trapaddr[12:0] - assign $0\traptype[7:0] $1\traptype[7:0] - assign $0\xer_in[2:0] $1\xer_in[2:0] - assign $0\xer_out[0:0] $1\xer_out[0:0] - assign $0\fasto1[2:0] $5\fasto1[2:0] - assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] - assign $0\fasto2[2:0] $5\fasto2[2:0] - assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] - assign $0\fast1[2:0] $5\fast1[2:0] - assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] - assign $0\fast2[2:0] $5\fast2[2:0] - assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] - assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:75485.5-75485.29" - switch \initial - attribute \src "libresoc.v:75485.9-75485.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916" - switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } - attribute \src "libresoc.v:0.0-0.0" - case 5'----1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\fast1[2:0] $2\fast1[2:0] - assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - assign $1\fast2[2:0] $2\fast2[2:0] - assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] - assign $1\rc[0:0] $2\rc[0:0] - assign $1\spr1[9:0] $2\spr1[9:0] - assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] - assign $1\msr[63:0] $2\msr[63:0] - assign $1\ea_ok[0:0] $2\ea_ok[0:0] - assign $1\ea[4:0] $2\ea[4:0] - assign $1\asmcode[7:0] $2\asmcode[7:0] - assign $1\cr_out[2:0] $2\cr_out[2:0] - assign $1\lk[0:0] $2\lk[0:0] - assign $1\cia[63:0] $2\cia[63:0] - assign $1\cr_in1[2:0] $2\cr_in1[2:0] - assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] - assign $1\cr_in2[2:0] $2\cr_in2[2:0] - assign $1\cr_in2$1[2:0]$3671 $2\cr_in2$1[2:0]$3681 - assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] - assign $1\cr_in2_ok$2[0:0]$3672 $2\cr_in2_ok$2[0:0]$3682 - assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] - assign $1\cr_rd[7:0] $2\cr_rd[7:0] - assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] - assign $1\cr_wr[7:0] $2\cr_wr[7:0] - assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] - assign $1\exc_$signal[0:0]$3673 $2\exc_$signal[0:0]$3683 - assign $1\exc_$signal$3[0:0]$3674 $2\exc_$signal$3[0:0]$3684 - assign $1\exc_$signal$4[0:0]$3675 $2\exc_$signal$4[0:0]$3685 - assign $1\exc_$signal$5[0:0]$3676 $2\exc_$signal$5[0:0]$3686 - assign $1\exc_$signal$6[0:0]$3677 $2\exc_$signal$6[0:0]$3687 - assign $1\exc_$signal$7[0:0]$3678 $2\exc_$signal$7[0:0]$3688 - assign $1\exc_$signal$8[0:0]$3679 $2\exc_$signal$8[0:0]$3689 - assign $1\exc_$signal$9[0:0]$3680 $2\exc_$signal$9[0:0]$3690 - assign $1\fasto1[2:0] $2\fasto1[2:0] - assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] - assign $1\fasto2[2:0] $2\fasto2[2:0] - assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] - assign $1\fn_unit[11:0] $2\fn_unit[11:0] - assign $1\input_carry[1:0] $2\input_carry[1:0] - assign $1\insn[31:0] $2\insn[31:0] - assign $1\insn_type[6:0] $2\insn_type[6:0] - assign $1\is_32bit[0:0] $2\is_32bit[0:0] - assign $1\oe[0:0] $2\oe[0:0] - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - assign $1\rc_ok[0:0] $2\rc_ok[0:0] - assign $1\reg1[4:0] $2\reg1[4:0] - assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] - assign $1\reg2[4:0] $2\reg2[4:0] - assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] - assign $1\reg3[4:0] $2\reg3[4:0] - assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] - assign $1\rego[4:0] $2\rego[4:0] - assign $1\rego_ok[0:0] $2\rego_ok[0:0] - assign $1\spro[9:0] $2\spro[9:0] - assign $1\spro_ok[0:0] $2\spro_ok[0:0] - assign $1\trapaddr[12:0] $2\trapaddr[12:0] - assign $1\traptype[7:0] $2\traptype[7:0] - assign $1\xer_in[2:0] $2\xer_in[2:0] - assign $1\xer_out[0:0] $2\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" - switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3690 $2\exc_$signal$8[0:0]$3689 $2\exc_$signal$7[0:0]$3688 $2\exc_$signal$6[0:0]$3687 $2\exc_$signal$5[0:0]$3686 $2\exc_$signal$4[0:0]$3685 $2\exc_$signal$3[0:0]$3684 $2\exc_$signal[0:0]$3683 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$3682 $2\cr_in2$1[2:0]$3681 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $2\insn[31:0] \dec_opcode_in - assign $2\insn_type[6:0] 7'0111111 - assign $2\fn_unit[11:0] 12'000010000000 - assign $2\trapaddr[12:0] 13'0000001100000 - assign $2\traptype[7:0] 8'00000010 - assign $2\msr[63:0] \cur_msr - assign $2\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\fast1[2:0] $3\fast1[2:0] - assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] - assign $2\fast2[2:0] $3\fast2[2:0] - assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] - assign $2\rc[0:0] $3\rc[0:0] - assign $2\spr1[9:0] $3\spr1[9:0] - assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] - assign $2\msr[63:0] $3\msr[63:0] - assign $2\ea_ok[0:0] $3\ea_ok[0:0] - assign $2\ea[4:0] $3\ea[4:0] - assign $2\asmcode[7:0] $3\asmcode[7:0] - assign $2\cr_out[2:0] $3\cr_out[2:0] - assign $2\lk[0:0] $3\lk[0:0] - assign $2\cia[63:0] $3\cia[63:0] - assign $2\cr_in1[2:0] $3\cr_in1[2:0] - assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] - assign $2\cr_in2[2:0] $3\cr_in2[2:0] - assign $2\cr_in2$1[2:0]$3681 $3\cr_in2$1[2:0]$3691 - assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3682 $3\cr_in2_ok$2[0:0]$3692 - assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] - assign $2\cr_rd[7:0] $3\cr_rd[7:0] - assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] - assign $2\cr_wr[7:0] $3\cr_wr[7:0] - assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3683 $3\exc_$signal[0:0]$3693 - assign $2\exc_$signal$3[0:0]$3684 $3\exc_$signal$3[0:0]$3694 - assign $2\exc_$signal$4[0:0]$3685 $3\exc_$signal$4[0:0]$3695 - assign $2\exc_$signal$5[0:0]$3686 $3\exc_$signal$5[0:0]$3696 - assign $2\exc_$signal$6[0:0]$3687 $3\exc_$signal$6[0:0]$3697 - assign $2\exc_$signal$7[0:0]$3688 $3\exc_$signal$7[0:0]$3698 - assign $2\exc_$signal$8[0:0]$3689 $3\exc_$signal$8[0:0]$3699 - assign $2\exc_$signal$9[0:0]$3690 $3\exc_$signal$9[0:0]$3700 - assign $2\fasto1[2:0] $3\fasto1[2:0] - assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] - assign $2\fasto2[2:0] $3\fasto2[2:0] - assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] - assign $2\fn_unit[11:0] $3\fn_unit[11:0] - assign $2\input_carry[1:0] $3\input_carry[1:0] - assign $2\insn[31:0] $3\insn[31:0] - assign $2\insn_type[6:0] $3\insn_type[6:0] - assign $2\is_32bit[0:0] $3\is_32bit[0:0] - assign $2\oe[0:0] $3\oe[0:0] - assign $2\oe_ok[0:0] $3\oe_ok[0:0] - assign $2\rc_ok[0:0] $3\rc_ok[0:0] - assign $2\reg1[4:0] $3\reg1[4:0] - assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] - assign $2\reg2[4:0] $3\reg2[4:0] - assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] - assign $2\reg3[4:0] $3\reg3[4:0] - assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] - assign $2\rego[4:0] $3\rego[4:0] - assign $2\rego_ok[0:0] $3\rego_ok[0:0] - assign $2\spro[9:0] $3\spro[9:0] - assign $2\spro_ok[0:0] $3\spro_ok[0:0] - assign $2\trapaddr[12:0] $3\trapaddr[12:0] - assign $2\traptype[7:0] $3\traptype[7:0] - assign $2\xer_in[2:0] $3\xer_in[2:0] - assign $2\xer_out[0:0] $3\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - switch \dec2_exc_$signal$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3700 $3\exc_$signal$8[0:0]$3699 $3\exc_$signal$7[0:0]$3698 $3\exc_$signal$6[0:0]$3697 $3\exc_$signal$5[0:0]$3696 $3\exc_$signal$4[0:0]$3695 $3\exc_$signal$3[0:0]$3694 $3\exc_$signal[0:0]$3693 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3692 $3\cr_in2$1[2:0]$3691 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $3\insn[31:0] \dec_opcode_in - assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[11:0] 12'000010000000 - assign $3\trapaddr[12:0] 13'0000001001000 - assign $3\traptype[7:0] 8'00000010 - assign $3\msr[63:0] \cur_msr - assign $3\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$3692 $3\cr_in2$1[2:0]$3691 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $3\insn[31:0] \dec_opcode_in - assign $3\insn_type[6:0] 7'0111111 - assign $3\fn_unit[11:0] 12'000010000000 - assign $3\trapaddr[12:0] 13'0000001000000 - assign $3\traptype[7:0] 8'01000000 - assign { $3\exc_$signal$9[0:0]$3700 $3\exc_$signal$8[0:0]$3699 $3\exc_$signal$7[0:0]$3698 $3\exc_$signal$6[0:0]$3697 $3\exc_$signal$5[0:0]$3696 $3\exc_$signal$4[0:0]$3695 $3\exc_$signal$3[0:0]$3694 $3\exc_$signal[0:0]$3693 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } - assign $3\msr[63:0] \cur_msr - assign $3\cia[63:0] \cur_pc - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\fast1[2:0] $4\fast1[2:0] - assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] - assign $2\fast2[2:0] $4\fast2[2:0] - assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] - assign $2\rc[0:0] $4\rc[0:0] - assign $2\spr1[9:0] $4\spr1[9:0] - assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] - assign $2\msr[63:0] $4\msr[63:0] - assign $2\ea_ok[0:0] $4\ea_ok[0:0] - assign $2\ea[4:0] $4\ea[4:0] - assign $2\asmcode[7:0] $4\asmcode[7:0] - assign $2\cr_out[2:0] $4\cr_out[2:0] - assign $2\lk[0:0] $4\lk[0:0] - assign $2\cia[63:0] $4\cia[63:0] - assign $2\cr_in1[2:0] $4\cr_in1[2:0] - assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] - assign $2\cr_in2[2:0] $4\cr_in2[2:0] - assign $2\cr_in2$1[2:0]$3681 $4\cr_in2$1[2:0]$3701 - assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] - assign $2\cr_in2_ok$2[0:0]$3682 $4\cr_in2_ok$2[0:0]$3702 - assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] - assign $2\cr_rd[7:0] $4\cr_rd[7:0] - assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] - assign $2\cr_wr[7:0] $4\cr_wr[7:0] - assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] - assign $2\exc_$signal[0:0]$3683 $4\exc_$signal[0:0]$3703 - assign $2\exc_$signal$3[0:0]$3684 $4\exc_$signal$3[0:0]$3704 - assign $2\exc_$signal$4[0:0]$3685 $4\exc_$signal$4[0:0]$3705 - assign $2\exc_$signal$5[0:0]$3686 $4\exc_$signal$5[0:0]$3706 - assign $2\exc_$signal$6[0:0]$3687 $4\exc_$signal$6[0:0]$3707 - assign $2\exc_$signal$7[0:0]$3688 $4\exc_$signal$7[0:0]$3708 - assign $2\exc_$signal$8[0:0]$3689 $4\exc_$signal$8[0:0]$3709 - assign $2\exc_$signal$9[0:0]$3690 $4\exc_$signal$9[0:0]$3710 - assign $2\fasto1[2:0] $4\fasto1[2:0] - assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] - assign $2\fasto2[2:0] $4\fasto2[2:0] - assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] - assign $2\fn_unit[11:0] $4\fn_unit[11:0] - assign $2\input_carry[1:0] $4\input_carry[1:0] - assign $2\insn[31:0] $4\insn[31:0] - assign $2\insn_type[6:0] $4\insn_type[6:0] - assign $2\is_32bit[0:0] $4\is_32bit[0:0] - assign $2\oe[0:0] $4\oe[0:0] - assign $2\oe_ok[0:0] $4\oe_ok[0:0] - assign $2\rc_ok[0:0] $4\rc_ok[0:0] - assign $2\reg1[4:0] $4\reg1[4:0] - assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] - assign $2\reg2[4:0] $4\reg2[4:0] - assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] - assign $2\reg3[4:0] $4\reg3[4:0] - assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] - assign $2\rego[4:0] $4\rego[4:0] - assign $2\rego_ok[0:0] $4\rego_ok[0:0] - assign $2\spro[9:0] $4\spro[9:0] - assign $2\spro_ok[0:0] $4\spro_ok[0:0] - assign $2\trapaddr[12:0] $4\trapaddr[12:0] - assign $2\traptype[7:0] $4\traptype[7:0] - assign $2\xer_in[2:0] $4\xer_in[2:0] - assign $2\xer_out[0:0] $4\xer_out[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926" - switch \dec2_exc_$signal$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3710 $4\exc_$signal$8[0:0]$3709 $4\exc_$signal$7[0:0]$3708 $4\exc_$signal$6[0:0]$3707 $4\exc_$signal$5[0:0]$3706 $4\exc_$signal$4[0:0]$3705 $4\exc_$signal$3[0:0]$3704 $4\exc_$signal[0:0]$3703 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3702 $4\cr_in2$1[2:0]$3701 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $4\insn[31:0] \dec_opcode_in - assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[11:0] 12'000010000000 - assign $4\trapaddr[12:0] 13'0000000111000 - assign $4\traptype[7:0] 8'00000010 - assign $4\msr[63:0] \cur_msr - assign $4\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3710 $4\exc_$signal$8[0:0]$3709 $4\exc_$signal$7[0:0]$3708 $4\exc_$signal$6[0:0]$3707 $4\exc_$signal$5[0:0]$3706 $4\exc_$signal$4[0:0]$3705 $4\exc_$signal$3[0:0]$3704 $4\exc_$signal[0:0]$3703 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$3702 $4\cr_in2$1[2:0]$3701 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $4\insn[31:0] \dec_opcode_in - assign $4\insn_type[6:0] 7'0111111 - assign $4\fn_unit[11:0] 12'000010000000 - assign $4\trapaddr[12:0] 13'0000000110000 - assign $4\traptype[7:0] 8'00000010 - assign $4\msr[63:0] \cur_msr - assign $4\cia[63:0] \cur_pc - end - end - attribute \src "libresoc.v:0.0-0.0" - case 5'---1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000010010000 - assign $1\traptype[7:0] 8'00100000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 5'--1-- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001010000 - assign $1\traptype[7:0] 8'00010000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 5'-1--- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[7:0] 8'00000010 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case 5'1---- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $1\insn[31:0] \dec_opcode_in - assign $1\insn_type[6:0] 7'0111111 - assign $1\fn_unit[11:0] 12'000010000000 - assign $1\trapaddr[12:0] 13'0000001110000 - assign $1\traptype[7:0] 8'10000000 - assign $1\msr[63:0] \cur_msr - assign $1\cia[63:0] \cur_pc - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3680 $1\exc_$signal$8[0:0]$3679 $1\exc_$signal$7[0:0]$3678 $1\exc_$signal$6[0:0]$3677 $1\exc_$signal$5[0:0]$3676 $1\exc_$signal$4[0:0]$3675 $1\exc_$signal$3[0:0]$3674 $1\exc_$signal[0:0]$3673 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3672 $1\cr_in2$1[2:0]$3671 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" - switch \$32 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $5\fasto1[2:0] 3'011 - assign $5\fasto1_ok[0:0] 1'1 - assign $5\fasto2[2:0] 3'100 - assign $5\fasto2_ok[0:0] 1'1 - case - assign $5\fasto1[2:0] $1\fasto1[2:0] - assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] - assign $5\fasto2[2:0] $1\fasto2[2:0] - assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" - switch \$34 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $5\fast1[2:0] 3'011 - assign $5\fast1_ok[0:0] 1'1 - assign $5\fast2[2:0] 3'100 - assign $5\fast2_ok[0:0] 1'1 - case - assign $5\fast1[2:0] $1\fast1[2:0] - assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] - assign $5\fast2[2:0] $1\fast2[2:0] - assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] - end - sync always - update \fast1 $0\fast1[2:0] - update \fast1_ok $0\fast1_ok[0:0] - update \fast2 $0\fast2[2:0] - update \fast2_ok $0\fast2_ok[0:0] - update \rc $0\rc[0:0] - update \spr1 $0\spr1[9:0] - update \spr1_ok $0\spr1_ok[0:0] - update \msr $0\msr[63:0] - update \ea_ok $0\ea_ok[0:0] - update \ea $0\ea[4:0] - update \asmcode $0\asmcode[7:0] - update \cr_out $0\cr_out[2:0] - update \lk $0\lk[0:0] - update \cia $0\cia[63:0] - update \cr_in1 $0\cr_in1[2:0] - update \cr_in1_ok $0\cr_in1_ok[0:0] - update \cr_in2 $0\cr_in2[2:0] - update \cr_in2$1 $0\cr_in2$1[2:0]$3661 - update \cr_in2_ok $0\cr_in2_ok[0:0] - update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3662 - update \cr_out_ok $0\cr_out_ok[0:0] - update \cr_rd $0\cr_rd[7:0] - update \cr_rd_ok $0\cr_rd_ok[0:0] - update \cr_wr $0\cr_wr[7:0] - update \cr_wr_ok $0\cr_wr_ok[0:0] - update \exc_$signal $0\exc_$signal[0:0]$3663 - update \exc_$signal$3 $0\exc_$signal$3[0:0]$3664 - update \exc_$signal$4 $0\exc_$signal$4[0:0]$3665 - update \exc_$signal$5 $0\exc_$signal$5[0:0]$3666 - update \exc_$signal$6 $0\exc_$signal$6[0:0]$3667 - update \exc_$signal$7 $0\exc_$signal$7[0:0]$3668 - update \exc_$signal$8 $0\exc_$signal$8[0:0]$3669 - update \exc_$signal$9 $0\exc_$signal$9[0:0]$3670 - update \fasto1 $0\fasto1[2:0] - update \fasto1_ok $0\fasto1_ok[0:0] - update \fasto2 $0\fasto2[2:0] - update \fasto2_ok $0\fasto2_ok[0:0] - update \fn_unit $0\fn_unit[11:0] - update \input_carry $0\input_carry[1:0] - update \insn $0\insn[31:0] - update \insn_type $0\insn_type[6:0] - update \is_32bit $0\is_32bit[0:0] - update \oe $0\oe[0:0] - update \oe_ok $0\oe_ok[0:0] - update \rc_ok $0\rc_ok[0:0] - update \reg1 $0\reg1[4:0] - update \reg1_ok $0\reg1_ok[0:0] - update \reg2 $0\reg2[4:0] - update \reg2_ok $0\reg2_ok[0:0] - update \reg3 $0\reg3[4:0] - update \reg3_ok $0\reg3_ok[0:0] - update \rego $0\rego[4:0] - update \rego_ok $0\rego_ok[0:0] - update \spro $0\spro[9:0] - update \spro_ok $0\spro_ok[0:0] - update \trapaddr $0\trapaddr[12:0] - update \traptype $0\traptype[7:0] - update \xer_in $0\xer_in[2:0] - update \xer_out $0\xer_out[0:0] - end - connect \$28 $eq$libresoc.v:75265$3643_Y - connect \$30 $eq$libresoc.v:75266$3644_Y - connect \$32 $or$libresoc.v:75267$3645_Y - connect \$34 $eq$libresoc.v:75268$3646_Y - connect \$42 $eq$libresoc.v:75269$3647_Y - connect \$44 $eq$libresoc.v:75270$3648_Y - connect \$46 $eq$libresoc.v:75271$3649_Y - connect \$48 $eq$libresoc.v:75272$3650_Y - connect \$50 $and$libresoc.v:75273$3651_Y - connect \$52 $and$libresoc.v:75274$3652_Y - connect \$54 $and$libresoc.v:75275$3653_Y - connect \$56 $eq$libresoc.v:75276$3654_Y - connect \dec2_exc_$signal 1'0 - connect \dec2_exc_$signal$12 1'0 - connect \dec2_exc_$signal$13 1'0 - connect \dec2_exc_$signal$14 1'0 - connect \dec2_exc_$signal$15 1'0 - connect \dec2_exc_$signal$16 1'0 - connect \dec2_exc_$signal$17 1'0 - connect \dec2_exc_$signal$18 1'0 - connect \tmp_asmcode 8'00000000 - connect \tmp_tmp_traptype 8'00000000 - connect \tmp_tmp_exc_$signal 1'0 - connect \tmp_tmp_exc_$signal$21 1'0 - connect \tmp_tmp_exc_$signal$22 1'0 - connect \tmp_tmp_exc_$signal$23 1'0 - connect \tmp_tmp_exc_$signal$24 1'0 - connect \tmp_tmp_exc_$signal$25 1'0 - connect \tmp_tmp_exc_$signal$26 1'0 - connect \tmp_tmp_exc_$signal$27 1'0 - connect \illeg_ok \$56 - connect \priv_ok \$54 - connect \dec_irq_ok \$52 - connect \ext_irq_ok \$50 - connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } - connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } - connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } - connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } - connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } - connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } - connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } - connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } - connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } - connect \dec_o2_lk \tmp_tmp_lk - connect \sel_in \dec_out_sel - connect \dec_o_sel_in \dec_out_sel - connect \dec_c_sel_in \dec_in3_sel - connect \dec_b_sel_in \dec_in2_sel - connect \dec_a_sel_in \dec_in1_sel - connect \insn_in$41 \dec_opcode_in - connect \insn_in$40 \dec_opcode_in - connect \insn_in$39 \dec_opcode_in - connect \insn_in$38 \dec_opcode_in - connect \insn_in$37 \dec_opcode_in - connect \tmp_tmp_insn \dec_opcode_in - connect \tmp_tmp_is_32bit \dec_is_32b - connect \tmp_tmp_input_carry \dec_cry_in - connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } - connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } - connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } - connect \tmp_tmp_fn_unit \dec_function_unit - connect \tmp_tmp_insn_type \dec_internal_op - connect \tmp_tmp_cia \cur_pc - connect \tmp_tmp_msr \cur_msr - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_cr_out - connect \dec_cr_in_sel_in \dec_cr_in - connect \dec_oe_sel_in \dec_rc_sel - connect \dec_rc_sel_in \dec_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$36 \dec_opcode_in - connect \insn_in \dec_opcode_in -end -attribute \src "libresoc.v:75714.1-76861.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" -attribute \generator "nMigen" -module \dec30 - attribute \src "libresoc.v:76157.3-76193.6" - wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:76305.3-76341.6" - wire $0\dec30_br[0:0] - attribute \src "libresoc.v:76786.3-76822.6" - wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:76823.3-76859.6" - wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:76120.3-76156.6" - wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:76268.3-76304.6" - wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:76601.3-76637.6" - wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:75972.3-76008.6" - wire width 12 $0\dec30_function_unit[11:0] - attribute \src "libresoc.v:76638.3-76674.6" - wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:76675.3-76711.6" - wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:76712.3-76748.6" - wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:76379.3-76415.6" - wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:76194.3-76230.6" - wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:76231.3-76267.6" - wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:76453.3-76489.6" - wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:76009.3-76045.6" - wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:76527.3-76563.6" - wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:76749.3-76785.6" - wire width 2 $0\dec30_out_sel[1:0] - attribute \src "libresoc.v:76083.3-76119.6" - wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:76416.3-76452.6" - wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:76564.3-76600.6" - wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:76490.3-76526.6" - wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:76342.3-76378.6" - wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:76046.3-76082.6" - wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:75715.7-75715.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:76157.3-76193.6" - wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:76305.3-76341.6" - wire $1\dec30_br[0:0] - attribute \src "libresoc.v:76786.3-76822.6" - wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:76823.3-76859.6" - wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:76120.3-76156.6" - wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:76268.3-76304.6" - wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:76601.3-76637.6" - wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:75972.3-76008.6" - wire width 12 $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:76638.3-76674.6" - wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:76675.3-76711.6" - wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:76712.3-76748.6" - wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:76379.3-76415.6" - wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:76194.3-76230.6" - wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:76231.3-76267.6" - wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:76453.3-76489.6" - wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:76009.3-76045.6" - wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:76527.3-76563.6" - wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:76749.3-76785.6" - wire width 2 $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:76083.3-76119.6" - wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:76416.3-76452.6" - wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:76564.3-76600.6" - wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:76490.3-76526.6" - wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:76342.3-76378.6" - wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:76046.3-76082.6" - wire width 2 $1\dec30_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec30_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec30_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec30_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec30_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec30_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec30_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec30_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec30_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec30_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute 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\enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec30_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec30_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec30_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec30_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec30_upd - attribute \src "libresoc.v:75715.7-75715.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 4 \opcode_switch - attribute \src "libresoc.v:75715.7-75715.20" - process $proc$libresoc.v:75715$3736 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:75972.3-76008.6" - process $proc$libresoc.v:75972$3712 - assign { } { } - assign { } { } - assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] - attribute \src "libresoc.v:75973.5-75973.29" - switch \initial - attribute \src "libresoc.v:75973.9-75973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_function_unit[11:0] 12'000000001000 - case - assign $1\dec30_function_unit[11:0] 12'000000000000 - end - sync always - update \dec30_function_unit $0\dec30_function_unit[11:0] - end - attribute \src "libresoc.v:76009.3-76045.6" - process $proc$libresoc.v:76009$3713 - assign { } { } - assign { } { } - assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:76010.5-76010.29" - switch \initial - attribute \src "libresoc.v:76010.9-76010.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_ldst_len[3:0] 4'0000 - case - assign $1\dec30_ldst_len[3:0] 4'0000 - end - sync always - update \dec30_ldst_len $0\dec30_ldst_len[3:0] - end - attribute \src "libresoc.v:76046.3-76082.6" - process $proc$libresoc.v:76046$3714 - assign { } { } - assign { } { } - assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:76047.5-76047.29" - switch \initial - attribute \src "libresoc.v:76047.9-76047.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_upd[1:0] 2'00 - case - assign $1\dec30_upd[1:0] 2'00 - end - sync always - update \dec30_upd $0\dec30_upd[1:0] - end - attribute \src "libresoc.v:76083.3-76119.6" - process $proc$libresoc.v:76083$3715 - assign { } { } - assign { } { } - assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:76084.5-76084.29" - switch \initial - attribute \src "libresoc.v:76084.9-76084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_rc_sel[1:0] 2'10 - case - assign $1\dec30_rc_sel[1:0] 2'00 - end - sync always - update \dec30_rc_sel $0\dec30_rc_sel[1:0] - end - attribute \src "libresoc.v:76120.3-76156.6" - process $proc$libresoc.v:76120$3716 - assign { } { } - assign { } { } - assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:76121.5-76121.29" - switch \initial - attribute \src "libresoc.v:76121.9-76121.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cry_in[1:0] 2'00 - case - assign $1\dec30_cry_in[1:0] 2'00 - end - sync always - update \dec30_cry_in $0\dec30_cry_in[1:0] - end - attribute \src "libresoc.v:76157.3-76193.6" - process $proc$libresoc.v:76157$3717 - assign { } { } - assign { } { } - assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:76158.5-76158.29" - switch \initial - attribute \src "libresoc.v:76158.9-76158.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010110 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010111 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010010 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_asmcode[7:0] 8'10010011 - case - assign $1\dec30_asmcode[7:0] 8'00000000 - end - sync always - update \dec30_asmcode $0\dec30_asmcode[7:0] - end - attribute \src "libresoc.v:76194.3-76230.6" - process $proc$libresoc.v:76194$3718 - assign { } { } - assign { } { } - assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:76195.5-76195.29" - switch \initial - attribute \src "libresoc.v:76195.9-76195.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_inv_a[0:0] 1'0 - case - assign $1\dec30_inv_a[0:0] 1'0 - end - sync always - update \dec30_inv_a $0\dec30_inv_a[0:0] - end - attribute \src "libresoc.v:76231.3-76267.6" - process $proc$libresoc.v:76231$3719 - assign { } { } - assign { } { } - assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:76232.5-76232.29" - switch \initial - attribute \src "libresoc.v:76232.9-76232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_inv_out[0:0] 1'0 - case - assign $1\dec30_inv_out[0:0] 1'0 - end - sync always - update \dec30_inv_out $0\dec30_inv_out[0:0] - end - attribute \src "libresoc.v:76268.3-76304.6" - process $proc$libresoc.v:76268$3720 - assign { } { } - assign { } { } - assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:76269.5-76269.29" - switch \initial - attribute \src "libresoc.v:76269.9-76269.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cry_out[0:0] 1'0 - case - assign $1\dec30_cry_out[0:0] 1'0 - end - sync always - update \dec30_cry_out $0\dec30_cry_out[0:0] - end - attribute \src "libresoc.v:76305.3-76341.6" - process $proc$libresoc.v:76305$3721 - assign { } { } - assign { } { } - assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:76306.5-76306.29" - switch \initial - attribute \src "libresoc.v:76306.9-76306.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_br[0:0] 1'0 - case - assign $1\dec30_br[0:0] 1'0 - end - sync always - update \dec30_br $0\dec30_br[0:0] - end - attribute \src "libresoc.v:76342.3-76378.6" - process $proc$libresoc.v:76342$3722 - assign { } { } - assign { } { } - assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:76343.5-76343.29" - switch \initial - attribute \src "libresoc.v:76343.9-76343.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgn_ext[0:0] 1'0 - case - assign $1\dec30_sgn_ext[0:0] 1'0 - end - sync always - update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] - end - attribute \src "libresoc.v:76379.3-76415.6" - process $proc$libresoc.v:76379$3723 - assign { } { } - assign { } { } - assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:76380.5-76380.29" - switch \initial - attribute \src "libresoc.v:76380.9-76380.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_internal_op[6:0] 7'0111010 - case - assign $1\dec30_internal_op[6:0] 7'0000000 - end - sync always - update \dec30_internal_op $0\dec30_internal_op[6:0] - end - attribute \src "libresoc.v:76416.3-76452.6" - process $proc$libresoc.v:76416$3724 - assign { } { } - assign { } { } - assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:76417.5-76417.29" - switch \initial - attribute \src "libresoc.v:76417.9-76417.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_rsrv[0:0] 1'0 - case - assign $1\dec30_rsrv[0:0] 1'0 - end - sync always - update \dec30_rsrv $0\dec30_rsrv[0:0] - end - attribute \src "libresoc.v:76453.3-76489.6" - process $proc$libresoc.v:76453$3725 - assign { } { } - assign { } { } - assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:76454.5-76454.29" - switch \initial - attribute \src "libresoc.v:76454.9-76454.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_is_32b[0:0] 1'0 - case - assign $1\dec30_is_32b[0:0] 1'0 - end - sync always - update \dec30_is_32b $0\dec30_is_32b[0:0] - end - attribute \src "libresoc.v:76490.3-76526.6" - process $proc$libresoc.v:76490$3726 - assign { } { } - assign { } { } - assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:76491.5-76491.29" - switch \initial - attribute \src "libresoc.v:76491.9-76491.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgn[0:0] 1'0 - case - assign $1\dec30_sgn[0:0] 1'0 - end - sync always - update \dec30_sgn $0\dec30_sgn[0:0] - end - attribute \src "libresoc.v:76527.3-76563.6" - process $proc$libresoc.v:76527$3727 - assign { } { } - assign { } { } - assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:76528.5-76528.29" - switch \initial - attribute \src "libresoc.v:76528.9-76528.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_lk[0:0] 1'0 - case - assign $1\dec30_lk[0:0] 1'0 - end - sync always - update \dec30_lk $0\dec30_lk[0:0] - end - attribute \src "libresoc.v:76564.3-76600.6" - process $proc$libresoc.v:76564$3728 - assign { } { } - assign { } { } - assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:76565.5-76565.29" - switch \initial - attribute \src "libresoc.v:76565.9-76565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_sgl_pipe[0:0] 1'0 - case - assign $1\dec30_sgl_pipe[0:0] 1'0 - end - sync always - update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] - end - attribute \src "libresoc.v:76601.3-76637.6" - process $proc$libresoc.v:76601$3729 - assign { } { } - assign { } { } - assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:76602.5-76602.29" - switch \initial - attribute \src "libresoc.v:76602.9-76602.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_form[4:0] 5'10101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_form[4:0] 5'10101 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_form[4:0] 5'10100 - case - assign $1\dec30_form[4:0] 5'00000 - end - sync always - update \dec30_form $0\dec30_form[4:0] - end - attribute \src "libresoc.v:76638.3-76674.6" - process $proc$libresoc.v:76638$3730 - assign { } { } - assign { } { } - assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:76639.5-76639.29" - switch \initial - attribute \src "libresoc.v:76639.9-76639.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in1_sel[2:0] 3'000 - case - assign $1\dec30_in1_sel[2:0] 3'000 - end - sync always - update \dec30_in1_sel $0\dec30_in1_sel[2:0] - end - attribute \src "libresoc.v:76675.3-76711.6" - process $proc$libresoc.v:76675$3731 - assign { } { } - assign { } { } - assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:76676.5-76676.29" - switch \initial - attribute \src "libresoc.v:76676.9-76676.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in2_sel[3:0] 4'0001 - case - assign $1\dec30_in2_sel[3:0] 4'0000 - end - sync always - update \dec30_in2_sel $0\dec30_in2_sel[3:0] - end - attribute \src "libresoc.v:76712.3-76748.6" - process $proc$libresoc.v:76712$3732 - assign { } { } - assign { } { } - assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:76713.5-76713.29" - switch \initial - attribute \src "libresoc.v:76713.9-76713.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_in3_sel[1:0] 2'01 - case - assign $1\dec30_in3_sel[1:0] 2'00 - end - sync always - update \dec30_in3_sel $0\dec30_in3_sel[1:0] - end - attribute \src "libresoc.v:76749.3-76785.6" - process $proc$libresoc.v:76749$3733 - assign { } { } - assign { } { } - assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] - attribute \src "libresoc.v:76750.5-76750.29" - switch \initial - attribute \src "libresoc.v:76750.9-76750.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_out_sel[1:0] 2'10 - case - assign $1\dec30_out_sel[1:0] 2'00 - end - sync always - update \dec30_out_sel $0\dec30_out_sel[1:0] - end - attribute \src "libresoc.v:76786.3-76822.6" - process $proc$libresoc.v:76786$3734 - assign { } { } - assign { } { } - assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:76787.5-76787.29" - switch \initial - attribute \src "libresoc.v:76787.9-76787.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cr_in[2:0] 3'000 - case - assign $1\dec30_cr_in[2:0] 3'000 - end - sync always - update \dec30_cr_in $0\dec30_cr_in[2:0] - end - attribute \src "libresoc.v:76823.3-76859.6" - process $proc$libresoc.v:76823$3735 - assign { } { } - assign { } { } - assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:76824.5-76824.29" - switch \initial - attribute \src "libresoc.v:76824.9-76824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0000 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\dec30_cr_out[2:0] 3'001 - case - assign $1\dec30_cr_out[2:0] 3'000 - end - sync always - update \dec30_cr_out $0\dec30_cr_out[2:0] - end - connect \opcode_switch \opcode_in [4:1] -end -attribute \src "libresoc.v:76865.1-83235.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" -attribute \generator "nMigen" -module \dec31 - attribute \src "libresoc.v:81934.3-81994.6" - wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:82788.3-82848.6" - wire $0\dec31_br[0:0] - attribute \src "libresoc.v:82239.3-82299.6" - wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:82300.3-82360.6" - wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:82544.3-82604.6" - wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:82727.3-82787.6" - wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:81873.3-81933.6" - wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:81751.3-81811.6" - wire width 12 $0\dec31_function_unit[11:0] - attribute \src "libresoc.v:81995.3-82055.6" - wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:82056.3-82116.6" - wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:82117.3-82177.6" - wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:81812.3-81872.6" - wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:82605.3-82665.6" - wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:82666.3-82726.6" - wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:82971.3-83031.6" - wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:82361.3-82421.6" - wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:83093.3-83153.6" - wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:82178.3-82238.6" - wire width 2 $0\dec31_out_sel[1:0] - attribute \src "libresoc.v:82483.3-82543.6" - wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:82910.3-82970.6" - wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:83154.3-83214.6" - wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:83032.3-83092.6" - wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:82849.3-82909.6" - wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:82422.3-82482.6" - wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:76866.7-76866.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:81934.3-81994.6" - wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:82788.3-82848.6" - wire $1\dec31_br[0:0] - attribute \src "libresoc.v:82239.3-82299.6" - wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:82300.3-82360.6" - wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:82544.3-82604.6" - wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:82727.3-82787.6" - wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:81873.3-81933.6" - wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:81751.3-81811.6" - wire width 12 $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:81995.3-82055.6" - wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:82056.3-82116.6" - wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:82117.3-82177.6" - wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:81812.3-81872.6" - wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:82605.3-82665.6" - wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:82666.3-82726.6" - wire $1\dec31_inv_out[0:0] - attribute \src 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec31_dec_sub0_dec31_dec_sub0_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_upd - attribute \src "libresoc.v:76866.7-76866.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" - wire width 5 \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 10 \opcode_switch - attribute \module_not_derived 1 - attribute \src "libresoc.v:81265.18-81291.4" - cell \dec31_dec_sub0 \dec31_dec_sub0 - connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode - connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br - connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in - connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out - connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in - connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out - connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form - connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit - connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel - connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel - connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel - connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op - connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a - connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out - connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b - connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len - connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk - connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel - connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel - connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv - connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn - connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd - connect \opcode_in \dec31_dec_sub0_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81292.19-81318.4" - cell \dec31_dec_sub10 \dec31_dec_sub10 - connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode - connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br - connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in - connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out - connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in - connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out - connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form - connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit - connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel - connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel - connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel - connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op - connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a - connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out - connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b - connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len - connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk - connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel - connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel - connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv - connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn - connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd - connect \opcode_in \dec31_dec_sub10_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81319.19-81345.4" - cell \dec31_dec_sub11 \dec31_dec_sub11 - connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode - connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br - connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in - connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out - connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in - connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out - connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form - connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit - connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel - connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel - connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel - connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op - connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a - connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out - connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b - connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len - connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk - connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel - connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel - connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv - connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn - connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd - connect \opcode_in \dec31_dec_sub11_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81346.19-81372.4" - cell \dec31_dec_sub15 \dec31_dec_sub15 - connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode - connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br - connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in - connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out - connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in - connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out - connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form - connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit - connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel - connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel - connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel - connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op - connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a - connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out - connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b - connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len - connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk - connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel - connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel - connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv - connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn - connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd - connect \opcode_in \dec31_dec_sub15_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81373.19-81399.4" - cell \dec31_dec_sub16 \dec31_dec_sub16 - connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode - connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br - connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in - connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out - connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in - connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out - connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form - connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit - connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel - connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel - connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel - connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op - connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a - connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out - connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b - connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len - connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk - connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel - connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel - connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv - connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn - connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd - connect \opcode_in \dec31_dec_sub16_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81400.19-81426.4" - cell \dec31_dec_sub18 \dec31_dec_sub18 - connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode - connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br - connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in - connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out - connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in - connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out - connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form - connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit - connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel - connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel - connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel - connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op - connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a - connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out - connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b - connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len - connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk - connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel - connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel - connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv - connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn - connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd - connect \opcode_in \dec31_dec_sub18_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81427.19-81453.4" - cell \dec31_dec_sub19 \dec31_dec_sub19 - connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode - connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br - connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in - connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out - connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in - connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out - connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form - connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit - connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel - connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel - connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel - connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op - connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a - connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out - connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b - connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len - connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk - connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel - connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel - connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv - connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn - connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd - connect \opcode_in \dec31_dec_sub19_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81454.19-81480.4" - cell \dec31_dec_sub20 \dec31_dec_sub20 - connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode - connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br - connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in - connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out - connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in - connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out - connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form - connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit - connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel - connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel - connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel - connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op - connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a - connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out - connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b - connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len - connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk - connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel - connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel - connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv - connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn - connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd - connect \opcode_in \dec31_dec_sub20_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81481.19-81507.4" - cell \dec31_dec_sub21 \dec31_dec_sub21 - connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode - connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br - connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in - connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out - connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in - connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out - connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form - connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit - connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel - connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel - connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel - connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op - connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a - connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out - connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b - connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len - connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk - connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel - connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel - connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv - connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn - connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd - connect \opcode_in \dec31_dec_sub21_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81508.19-81534.4" - cell \dec31_dec_sub22 \dec31_dec_sub22 - connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode - connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br - connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in - connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out - connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in - connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out - connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form - connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit - connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel - connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel - connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel - connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op - connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a - connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out - connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b - connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len - connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk - connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel - connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel - connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv - connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn - connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd - connect \opcode_in \dec31_dec_sub22_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81535.19-81561.4" - cell \dec31_dec_sub23 \dec31_dec_sub23 - connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode - connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br - connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in - connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out - connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in - connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out - connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form - connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit - connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel - connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel - connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel - connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op - connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a - connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out - connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b - connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len - connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk - connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel - connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel - connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv - connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn - connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd - connect \opcode_in \dec31_dec_sub23_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81562.19-81588.4" - cell \dec31_dec_sub24 \dec31_dec_sub24 - connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode - connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br - connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in - connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out - connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in - connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out - connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form - connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit - connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel - connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel - connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel - connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op - connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a - connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out - connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b - connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len - connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk - connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel - connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel - connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv - connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn - connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd - connect \opcode_in \dec31_dec_sub24_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81589.19-81615.4" - cell \dec31_dec_sub26 \dec31_dec_sub26 - connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode - connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br - connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in - connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out - connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in - connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out - connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form - connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit - connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel - connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel - connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel - connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op - connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a - connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out - connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b - connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len - connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk - connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel - connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel - connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv - connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn - connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd - connect \opcode_in \dec31_dec_sub26_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81616.19-81642.4" - cell \dec31_dec_sub27 \dec31_dec_sub27 - connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode - connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br - connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in - connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out - connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in - connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out - connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form - connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit - connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel - connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel - connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel - connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op - connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a - connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out - connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b - connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len - connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk - connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel - connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel - connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv - connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn - connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd - connect \opcode_in \dec31_dec_sub27_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81643.19-81669.4" - cell \dec31_dec_sub28 \dec31_dec_sub28 - connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode - connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br - connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in - connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out - connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in - connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out - connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form - connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit - connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel - connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel - connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel - connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op - connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a - connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out - connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b - connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len - connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk - connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel - connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel - connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv - connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn - connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd - connect \opcode_in \dec31_dec_sub28_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81670.18-81696.4" - cell \dec31_dec_sub4 \dec31_dec_sub4 - connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode - connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br - connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in - connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out - connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in - connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out - connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form - connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit - connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel - connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel - connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel - connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op - connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a - connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out - connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b - connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len - connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk - connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel - connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel - connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv - connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn - connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd - connect \opcode_in \dec31_dec_sub4_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81697.18-81723.4" - cell \dec31_dec_sub8 \dec31_dec_sub8 - connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode - connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br - connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in - connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out - connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in - connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out - connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form - connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit - connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel - connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel - connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel - connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op - connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a - connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out - connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b - connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len - connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk - connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel - connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel - connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv - connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn - connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd - connect \opcode_in \dec31_dec_sub8_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:81724.18-81750.4" - cell \dec31_dec_sub9 \dec31_dec_sub9 - connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode - connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br - connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in - connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out - connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in - connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out - connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form - connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit - connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel - connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel - connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel - connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op - connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a - connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out - connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b - connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len - connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk - connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel - connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel - connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv - connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn - connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd - connect \opcode_in \dec31_dec_sub9_opcode_in - end - attribute \src "libresoc.v:76866.7-76866.20" - process $proc$libresoc.v:76866$3761 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:81751.3-81811.6" - process $proc$libresoc.v:81751$3737 - assign { } { } - assign { } { } - assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] - attribute \src "libresoc.v:81752.5-81752.29" - switch \initial - attribute \src "libresoc.v:81752.9-81752.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit - case - assign $1\dec31_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_function_unit $0\dec31_function_unit[11:0] - end - attribute \src "libresoc.v:81812.3-81872.6" - process $proc$libresoc.v:81812$3738 - assign { } { } - assign { } { } - assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:81813.5-81813.29" - switch \initial - attribute \src "libresoc.v:81813.9-81813.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op - case - assign $1\dec31_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_internal_op $0\dec31_internal_op[6:0] - end - attribute \src "libresoc.v:81873.3-81933.6" - process $proc$libresoc.v:81873$3739 - assign { } { } - assign { } { } - assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:81874.5-81874.29" - switch \initial - attribute \src "libresoc.v:81874.9-81874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form - case - assign $1\dec31_form[4:0] 5'00000 - end - sync always - update \dec31_form $0\dec31_form[4:0] - end - attribute \src "libresoc.v:81934.3-81994.6" - process $proc$libresoc.v:81934$3740 - assign { } { } - assign { } { } - assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:81935.5-81935.29" - switch \initial - attribute \src "libresoc.v:81935.9-81935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode - case - assign $1\dec31_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_asmcode $0\dec31_asmcode[7:0] - end - attribute \src "libresoc.v:81995.3-82055.6" - process $proc$libresoc.v:81995$3741 - assign { } { } - assign { } { } - assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:81996.5-81996.29" - switch \initial - attribute \src "libresoc.v:81996.9-81996.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel - case - assign $1\dec31_in1_sel[2:0] 3'000 - end - sync always - update \dec31_in1_sel $0\dec31_in1_sel[2:0] - end - attribute \src "libresoc.v:82056.3-82116.6" - process $proc$libresoc.v:82056$3742 - assign { } { } - assign { } { } - assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:82057.5-82057.29" - switch \initial - attribute \src "libresoc.v:82057.9-82057.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel - case - assign $1\dec31_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_in2_sel $0\dec31_in2_sel[3:0] - end - attribute \src "libresoc.v:82117.3-82177.6" - process $proc$libresoc.v:82117$3743 - assign { } { } - assign { } { } - assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:82118.5-82118.29" - switch \initial - attribute \src "libresoc.v:82118.9-82118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel - case - assign $1\dec31_in3_sel[1:0] 2'00 - end - sync always - update \dec31_in3_sel $0\dec31_in3_sel[1:0] - end - attribute \src "libresoc.v:82178.3-82238.6" - process $proc$libresoc.v:82178$3744 - assign { } { } - assign { } { } - assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] - attribute \src "libresoc.v:82179.5-82179.29" - switch \initial - attribute \src "libresoc.v:82179.9-82179.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel - case - assign $1\dec31_out_sel[1:0] 2'00 - end - sync always - update \dec31_out_sel $0\dec31_out_sel[1:0] - end - attribute \src "libresoc.v:82239.3-82299.6" - process $proc$libresoc.v:82239$3745 - assign { } { } - assign { } { } - assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:82240.5-82240.29" - switch \initial - attribute \src "libresoc.v:82240.9-82240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in - case - assign $1\dec31_cr_in[2:0] 3'000 - end - sync always - update \dec31_cr_in $0\dec31_cr_in[2:0] - end - attribute \src "libresoc.v:82300.3-82360.6" - process $proc$libresoc.v:82300$3746 - assign { } { } - assign { } { } - assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:82301.5-82301.29" - switch \initial - attribute \src "libresoc.v:82301.9-82301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out - case - assign $1\dec31_cr_out[2:0] 3'000 - end - sync always - update \dec31_cr_out $0\dec31_cr_out[2:0] - end - attribute \src "libresoc.v:82361.3-82421.6" - process $proc$libresoc.v:82361$3747 - assign { } { } - assign { } { } - assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:82362.5-82362.29" - switch \initial - attribute \src "libresoc.v:82362.9-82362.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len - case - assign $1\dec31_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_ldst_len $0\dec31_ldst_len[3:0] - end - attribute \src "libresoc.v:82422.3-82482.6" - process $proc$libresoc.v:82422$3748 - assign { } { } - assign { } { } - assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:82423.5-82423.29" - switch \initial - attribute \src "libresoc.v:82423.9-82423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd - case - assign $1\dec31_upd[1:0] 2'00 - end - sync always - update \dec31_upd $0\dec31_upd[1:0] - end - attribute \src "libresoc.v:82483.3-82543.6" - process $proc$libresoc.v:82483$3749 - assign { } { } - assign { } { } - assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:82484.5-82484.29" - switch \initial - attribute \src "libresoc.v:82484.9-82484.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel - case - assign $1\dec31_rc_sel[1:0] 2'00 - end - sync always - update \dec31_rc_sel $0\dec31_rc_sel[1:0] - end - attribute \src "libresoc.v:82544.3-82604.6" - process $proc$libresoc.v:82544$3750 - assign { } { } - assign { } { } - assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:82545.5-82545.29" - switch \initial - attribute \src "libresoc.v:82545.9-82545.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in - case - assign $1\dec31_cry_in[1:0] 2'00 - end - sync always - update \dec31_cry_in $0\dec31_cry_in[1:0] - end - attribute \src "libresoc.v:82605.3-82665.6" - process $proc$libresoc.v:82605$3751 - assign { } { } - assign { } { } - assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:82606.5-82606.29" - switch \initial - attribute \src "libresoc.v:82606.9-82606.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a - case - assign $1\dec31_inv_a[0:0] 1'0 - end - sync always - update \dec31_inv_a $0\dec31_inv_a[0:0] - end - attribute \src "libresoc.v:82666.3-82726.6" - process $proc$libresoc.v:82666$3752 - assign { } { } - assign { } { } - assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:82667.5-82667.29" - switch \initial - attribute \src "libresoc.v:82667.9-82667.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out - case - assign $1\dec31_inv_out[0:0] 1'0 - end - sync always - update \dec31_inv_out $0\dec31_inv_out[0:0] - end - attribute \src "libresoc.v:82727.3-82787.6" - process $proc$libresoc.v:82727$3753 - assign { } { } - assign { } { } - assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:82728.5-82728.29" - switch \initial - attribute \src "libresoc.v:82728.9-82728.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out - case - assign $1\dec31_cry_out[0:0] 1'0 - end - sync always - update \dec31_cry_out $0\dec31_cry_out[0:0] - end - attribute \src "libresoc.v:82788.3-82848.6" - process $proc$libresoc.v:82788$3754 - assign { } { } - assign { } { } - assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:82789.5-82789.29" - switch \initial - attribute \src "libresoc.v:82789.9-82789.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br - case - assign $1\dec31_br[0:0] 1'0 - end - sync always - update \dec31_br $0\dec31_br[0:0] - end - attribute \src "libresoc.v:82849.3-82909.6" - process $proc$libresoc.v:82849$3755 - assign { } { } - assign { } { } - assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:82850.5-82850.29" - switch \initial - attribute \src "libresoc.v:82850.9-82850.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext - case - assign $1\dec31_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] - end - attribute \src "libresoc.v:82910.3-82970.6" - process $proc$libresoc.v:82910$3756 - assign { } { } - assign { } { } - assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:82911.5-82911.29" - switch \initial - attribute \src "libresoc.v:82911.9-82911.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv - case - assign $1\dec31_rsrv[0:0] 1'0 - end - sync always - update \dec31_rsrv $0\dec31_rsrv[0:0] - end - attribute \src "libresoc.v:82971.3-83031.6" - process $proc$libresoc.v:82971$3757 - assign { } { } - assign { } { } - assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:82972.5-82972.29" - switch \initial - attribute \src "libresoc.v:82972.9-82972.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b - case - assign $1\dec31_is_32b[0:0] 1'0 - end - sync always - update \dec31_is_32b $0\dec31_is_32b[0:0] - end - attribute \src "libresoc.v:83032.3-83092.6" - process $proc$libresoc.v:83032$3758 - assign { } { } - assign { } { } - assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:83033.5-83033.29" - switch \initial - attribute \src "libresoc.v:83033.9-83033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn - case - assign $1\dec31_sgn[0:0] 1'0 - end - sync always - update \dec31_sgn $0\dec31_sgn[0:0] - end - attribute \src "libresoc.v:83093.3-83153.6" - process $proc$libresoc.v:83093$3759 - assign { } { } - assign { } { } - assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:83094.5-83094.29" - switch \initial - attribute \src "libresoc.v:83094.9-83094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk - case - assign $1\dec31_lk[0:0] 1'0 - end - sync always - update \dec31_lk $0\dec31_lk[0:0] - end - attribute \src "libresoc.v:83154.3-83214.6" - process $proc$libresoc.v:83154$3760 - assign { } { } - assign { } { } - assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:83155.5-83155.29" - switch \initial - attribute \src "libresoc.v:83155.9-83155.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opc_in - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe - case - assign $1\dec31_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] - end - connect \dec31_dec_sub4_opcode_in \opcode_in - connect \dec31_dec_sub24_opcode_in \opcode_in - connect \dec31_dec_sub8_opcode_in \opcode_in - connect \dec31_dec_sub18_opcode_in \opcode_in - connect \dec31_dec_sub16_opcode_in \opcode_in - connect \dec31_dec_sub23_opcode_in \opcode_in - connect \dec31_dec_sub21_opcode_in \opcode_in - connect \dec31_dec_sub20_opcode_in \opcode_in - connect \dec31_dec_sub15_opcode_in \opcode_in - connect \dec31_dec_sub27_opcode_in \opcode_in - connect \dec31_dec_sub11_opcode_in \opcode_in - connect \dec31_dec_sub9_opcode_in \opcode_in - connect \dec31_dec_sub22_opcode_in \opcode_in - connect \dec31_dec_sub19_opcode_in \opcode_in - connect \dec31_dec_sub26_opcode_in \opcode_in - connect \dec31_dec_sub0_opcode_in \opcode_in - connect \dec31_dec_sub28_opcode_in \opcode_in - connect \dec31_dec_sub10_opcode_in \opcode_in - connect \opc_in \opcode_switch [4:0] - connect \opcode_switch \opcode_in [10:1] -end -attribute \src "libresoc.v:83239.1-83954.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" -attribute \generator "nMigen" -module \dec31_dec_sub0 - attribute \src "libresoc.v:83592.3-83610.6" - wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:83668.3-83686.6" - wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83915.3-83933.6" - wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83934.3-83952.6" - wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:83573.3-83591.6" - wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:83649.3-83667.6" - wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:83820.3-83838.6" - wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:83497.3-83515.6" - wire width 12 $0\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:83839.3-83857.6" - wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:83858.3-83876.6" - wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83877.3-83895.6" - wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:83706.3-83724.6" - wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:83611.3-83629.6" - wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:83630.3-83648.6" - wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:83744.3-83762.6" - wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:83516.3-83534.6" - wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:83782.3-83800.6" - wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83896.3-83914.6" - wire width 2 $0\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:83554.3-83572.6" - wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:83725.3-83743.6" - wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:83801.3-83819.6" - wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:83763.3-83781.6" - wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:83687.3-83705.6" - wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:83535.3-83553.6" - wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:83240.7-83240.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:83592.3-83610.6" - wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:83668.3-83686.6" - wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83915.3-83933.6" - wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83934.3-83952.6" - wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:83573.3-83591.6" - wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:83649.3-83667.6" - wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:83820.3-83838.6" - wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:83497.3-83515.6" - wire width 12 $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:83839.3-83857.6" - wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:83858.3-83876.6" - wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83877.3-83895.6" - wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:83706.3-83724.6" - wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:83611.3-83629.6" - wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:83630.3-83648.6" - wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:83744.3-83762.6" - wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:83516.3-83534.6" - wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:83782.3-83800.6" - wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83896.3-83914.6" - wire width 2 $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:83554.3-83572.6" - wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:83725.3-83743.6" - wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:83801.3-83819.6" - wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:83763.3-83781.6" - wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:83687.3-83705.6" - wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:83535.3-83553.6" - wire width 2 $1\dec31_dec_sub0_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub0_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub0_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub0_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub0_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub0_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub0_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub0_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub0_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub0_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub0_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub0_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub0_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub0_upd - attribute \src "libresoc.v:83240.7-83240.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:83240.7-83240.20" - process $proc$libresoc.v:83240$3786 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:83497.3-83515.6" - process $proc$libresoc.v:83497$3762 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] - attribute \src "libresoc.v:83498.5-83498.29" - switch \initial - attribute \src "libresoc.v:83498.9-83498.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] - end - attribute \src "libresoc.v:83516.3-83534.6" - process $proc$libresoc.v:83516$3763 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:83517.5-83517.29" - switch \initial - attribute \src "libresoc.v:83517.9-83517.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] - end - attribute \src "libresoc.v:83535.3-83553.6" - process $proc$libresoc.v:83535$3764 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:83536.5-83536.29" - switch \initial - attribute \src "libresoc.v:83536.9-83536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub0_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] - end - attribute \src "libresoc.v:83554.3-83572.6" - process $proc$libresoc.v:83554$3765 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:83555.5-83555.29" - switch \initial - attribute \src "libresoc.v:83555.9-83555.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] - end - attribute \src "libresoc.v:83573.3-83591.6" - process $proc$libresoc.v:83573$3766 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:83574.5-83574.29" - switch \initial - attribute \src "libresoc.v:83574.9-83574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] - end - attribute \src "libresoc.v:83592.3-83610.6" - process $proc$libresoc.v:83592$3767 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:83593.5-83593.29" - switch \initial - attribute \src "libresoc.v:83593.9-83593.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 - case - assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] - end - attribute \src "libresoc.v:83611.3-83629.6" - process $proc$libresoc.v:83611$3768 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:83612.5-83612.29" - switch \initial - attribute \src "libresoc.v:83612.9-83612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] - end - attribute \src "libresoc.v:83630.3-83648.6" - process $proc$libresoc.v:83630$3769 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:83631.5-83631.29" - switch \initial - attribute \src "libresoc.v:83631.9-83631.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] - end - attribute \src "libresoc.v:83649.3-83667.6" - process $proc$libresoc.v:83649$3770 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:83650.5-83650.29" - switch \initial - attribute \src "libresoc.v:83650.9-83650.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] - end - attribute \src "libresoc.v:83668.3-83686.6" - process $proc$libresoc.v:83668$3771 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:83669.5-83669.29" - switch \initial - attribute \src "libresoc.v:83669.9-83669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_br[0:0] 1'0 - case - assign $1\dec31_dec_sub0_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] - end - attribute \src "libresoc.v:83687.3-83705.6" - process $proc$libresoc.v:83687$3772 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:83688.5-83688.29" - switch \initial - attribute \src "libresoc.v:83688.9-83688.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] - end - attribute \src "libresoc.v:83706.3-83724.6" - process $proc$libresoc.v:83706$3773 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:83707.5-83707.29" - switch \initial - attribute \src "libresoc.v:83707.9-83707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 - case - assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] - end - attribute \src "libresoc.v:83725.3-83743.6" - process $proc$libresoc.v:83725$3774 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:83726.5-83726.29" - switch \initial - attribute \src "libresoc.v:83726.9-83726.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] - end - attribute \src "libresoc.v:83744.3-83762.6" - process $proc$libresoc.v:83744$3775 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:83745.5-83745.29" - switch \initial - attribute \src "libresoc.v:83745.9-83745.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] - end - attribute \src "libresoc.v:83763.3-83781.6" - process $proc$libresoc.v:83763$3776 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:83764.5-83764.29" - switch \initial - attribute \src "libresoc.v:83764.9-83764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] - end - attribute \src "libresoc.v:83782.3-83800.6" - process $proc$libresoc.v:83782$3777 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:83783.5-83783.29" - switch \initial - attribute \src "libresoc.v:83783.9-83783.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub0_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] - end - attribute \src "libresoc.v:83801.3-83819.6" - process $proc$libresoc.v:83801$3778 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:83802.5-83802.29" - switch \initial - attribute \src "libresoc.v:83802.9-83802.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] - end - attribute \src "libresoc.v:83820.3-83838.6" - process $proc$libresoc.v:83820$3779 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:83821.5-83821.29" - switch \initial - attribute \src "libresoc.v:83821.9-83821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_form[4:0] 5'11000 - case - assign $1\dec31_dec_sub0_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] - end - attribute \src "libresoc.v:83839.3-83857.6" - process $proc$libresoc.v:83839$3780 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:83840.5-83840.29" - switch \initial - attribute \src "libresoc.v:83840.9-83840.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] - end - attribute \src "libresoc.v:83858.3-83876.6" - process $proc$libresoc.v:83858$3781 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:83859.5-83859.29" - switch \initial - attribute \src "libresoc.v:83859.9-83859.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] - end - attribute \src "libresoc.v:83877.3-83895.6" - process $proc$libresoc.v:83877$3782 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:83878.5-83878.29" - switch \initial - attribute \src "libresoc.v:83878.9-83878.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] - end - attribute \src "libresoc.v:83896.3-83914.6" - process $proc$libresoc.v:83896$3783 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] - attribute \src "libresoc.v:83897.5-83897.29" - switch \initial - attribute \src "libresoc.v:83897.9-83897.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] - end - attribute \src "libresoc.v:83915.3-83933.6" - process $proc$libresoc.v:83915$3784 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:83916.5-83916.29" - switch \initial - attribute \src "libresoc.v:83916.9-83916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 - case - assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] - end - attribute \src "libresoc.v:83934.3-83952.6" - process $proc$libresoc.v:83934$3785 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:83935.5-83935.29" - switch \initial - attribute \src "libresoc.v:83935.9-83935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:83958.1-85105.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" -attribute \generator "nMigen" -module \dec31_dec_sub10 - attribute \src "libresoc.v:84401.3-84437.6" - wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:84549.3-84585.6" - wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:85030.3-85066.6" - wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:85067.3-85103.6" - wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:84364.3-84400.6" - wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:84512.3-84548.6" - wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:84845.3-84881.6" - wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:84216.3-84252.6" - wire width 12 $0\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84882.3-84918.6" - wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84919.3-84955.6" - wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84956.3-84992.6" - wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:84623.3-84659.6" - wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:84438.3-84474.6" - wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:84475.3-84511.6" - wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:84697.3-84733.6" - wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:84253.3-84289.6" - wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:84771.3-84807.6" - wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84993.3-85029.6" - wire width 2 $0\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:84327.3-84363.6" - wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:84660.3-84696.6" - wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:84808.3-84844.6" - wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:84734.3-84770.6" - wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:84586.3-84622.6" - wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:84290.3-84326.6" - wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:83959.7-83959.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:84401.3-84437.6" - wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:84549.3-84585.6" - wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:85030.3-85066.6" - wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:85067.3-85103.6" - wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:84364.3-84400.6" - wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:84512.3-84548.6" - wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:84845.3-84881.6" - wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:84216.3-84252.6" - wire width 12 $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84882.3-84918.6" - wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84919.3-84955.6" - wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84956.3-84992.6" - wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:84623.3-84659.6" - wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:84438.3-84474.6" - wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:84475.3-84511.6" - wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:84697.3-84733.6" - wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:84253.3-84289.6" - wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:84771.3-84807.6" - wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84993.3-85029.6" - wire width 2 $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:84327.3-84363.6" - wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:84660.3-84696.6" - wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:84808.3-84844.6" - wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:84734.3-84770.6" - wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:84586.3-84622.6" - wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:84290.3-84326.6" - wire width 2 $1\dec31_dec_sub10_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub10_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub10_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub10_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub10_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub10_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub10_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub10_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub10_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub10_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub10_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub10_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub10_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub10_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub10_upd - attribute \src "libresoc.v:83959.7-83959.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:83959.7-83959.20" - process $proc$libresoc.v:83959$3811 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:84216.3-84252.6" - process $proc$libresoc.v:84216$3787 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] - attribute \src "libresoc.v:84217.5-84217.29" - switch \initial - attribute \src "libresoc.v:84217.9-84217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] - end - attribute \src "libresoc.v:84253.3-84289.6" - process $proc$libresoc.v:84253$3788 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:84254.5-84254.29" - switch \initial - attribute \src "libresoc.v:84254.9-84254.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] - end - attribute \src "libresoc.v:84290.3-84326.6" - process $proc$libresoc.v:84290$3789 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:84291.5-84291.29" - switch \initial - attribute \src "libresoc.v:84291.9-84291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub10_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] - end - attribute \src "libresoc.v:84327.3-84363.6" - process $proc$libresoc.v:84327$3790 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:84328.5-84328.29" - switch \initial - attribute \src "libresoc.v:84328.9-84328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] - end - attribute \src "libresoc.v:84364.3-84400.6" - process $proc$libresoc.v:84364$3791 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:84365.5-84365.29" - switch \initial - attribute \src "libresoc.v:84365.9-84365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 - case - assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] - end - attribute \src "libresoc.v:84401.3-84437.6" - process $proc$libresoc.v:84401$3792 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:84402.5-84402.29" - switch \initial - attribute \src "libresoc.v:84402.9-84402.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 - case - assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] - end - attribute \src "libresoc.v:84438.3-84474.6" - process $proc$libresoc.v:84438$3793 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:84439.5-84439.29" - switch \initial - attribute \src "libresoc.v:84439.9-84439.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] - end - attribute \src "libresoc.v:84475.3-84511.6" - process $proc$libresoc.v:84475$3794 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:84476.5-84476.29" - switch \initial - attribute \src "libresoc.v:84476.9-84476.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] - end - attribute \src "libresoc.v:84512.3-84548.6" - process $proc$libresoc.v:84512$3795 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:84513.5-84513.29" - switch \initial - attribute \src "libresoc.v:84513.9-84513.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] - end - attribute \src "libresoc.v:84549.3-84585.6" - process $proc$libresoc.v:84549$3796 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:84550.5-84550.29" - switch \initial - attribute \src "libresoc.v:84550.9-84550.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_br[0:0] 1'0 - case - assign $1\dec31_dec_sub10_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] - end - attribute \src "libresoc.v:84586.3-84622.6" - process $proc$libresoc.v:84586$3797 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:84587.5-84587.29" - switch \initial - attribute \src "libresoc.v:84587.9-84587.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] - end - attribute \src "libresoc.v:84623.3-84659.6" - process $proc$libresoc.v:84623$3798 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:84624.5-84624.29" - switch \initial - attribute \src "libresoc.v:84624.9-84624.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 - case - assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] - end - attribute \src "libresoc.v:84660.3-84696.6" - process $proc$libresoc.v:84660$3799 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:84661.5-84661.29" - switch \initial - attribute \src "libresoc.v:84661.9-84661.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] - end - attribute \src "libresoc.v:84697.3-84733.6" - process $proc$libresoc.v:84697$3800 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:84698.5-84698.29" - switch \initial - attribute \src "libresoc.v:84698.9-84698.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] - end - attribute \src "libresoc.v:84734.3-84770.6" - process $proc$libresoc.v:84734$3801 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:84735.5-84735.29" - switch \initial - attribute \src "libresoc.v:84735.9-84735.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] - end - attribute \src "libresoc.v:84771.3-84807.6" - process $proc$libresoc.v:84771$3802 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:84772.5-84772.29" - switch \initial - attribute \src "libresoc.v:84772.9-84772.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub10_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] - end - attribute \src "libresoc.v:84808.3-84844.6" - process $proc$libresoc.v:84808$3803 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:84809.5-84809.29" - switch \initial - attribute \src "libresoc.v:84809.9-84809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] - end - attribute \src "libresoc.v:84845.3-84881.6" - process $proc$libresoc.v:84845$3804 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:84846.5-84846.29" - switch \initial - attribute \src "libresoc.v:84846.9-84846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub10_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] - end - attribute \src "libresoc.v:84882.3-84918.6" - process $proc$libresoc.v:84882$3805 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:84883.5-84883.29" - switch \initial - attribute \src "libresoc.v:84883.9-84883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] - end - attribute \src "libresoc.v:84919.3-84955.6" - process $proc$libresoc.v:84919$3806 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:84920.5-84920.29" - switch \initial - attribute \src "libresoc.v:84920.9-84920.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] - end - attribute \src "libresoc.v:84956.3-84992.6" - process $proc$libresoc.v:84956$3807 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:84957.5-84957.29" - switch \initial - attribute \src "libresoc.v:84957.9-84957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] - end - attribute \src "libresoc.v:84993.3-85029.6" - process $proc$libresoc.v:84993$3808 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] - attribute \src "libresoc.v:84994.5-84994.29" - switch \initial - attribute \src "libresoc.v:84994.9-84994.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] - end - attribute \src "libresoc.v:85030.3-85066.6" - process $proc$libresoc.v:85030$3809 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:85031.5-85031.29" - switch \initial - attribute \src "libresoc.v:85031.9-85031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] - end - attribute \src "libresoc.v:85067.3-85103.6" - process $proc$libresoc.v:85067$3810 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:85068.5-85068.29" - switch \initial - attribute \src "libresoc.v:85068.9-85068.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:85109.1-86688.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" -attribute \generator "nMigen" -module \dec31_dec_sub11 - attribute \src "libresoc.v:85642.3-85696.6" - wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:85862.3-85916.6" - wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:86577.3-86631.6" - wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:86632.3-86686.6" - wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:85587.3-85641.6" - wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:85807.3-85861.6" - wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:86302.3-86356.6" - wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:85367.3-85421.6" - wire width 12 $0\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:86357.3-86411.6" - wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:86412.3-86466.6" - wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:86467.3-86521.6" - wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:85972.3-86026.6" - wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:85697.3-85751.6" - wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:85752.3-85806.6" - wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:86082.3-86136.6" - wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:85422.3-85476.6" - wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:86192.3-86246.6" - wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:86522.3-86576.6" - wire width 2 $0\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:85532.3-85586.6" - wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:86027.3-86081.6" - wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:86247.3-86301.6" - wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:86137.3-86191.6" - wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85917.3-85971.6" - wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:85477.3-85531.6" - wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:85110.7-85110.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:85642.3-85696.6" - wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:85862.3-85916.6" - wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:86577.3-86631.6" - wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:86632.3-86686.6" - wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:85587.3-85641.6" - wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:85807.3-85861.6" - wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:86302.3-86356.6" - wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:85367.3-85421.6" - wire width 12 $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:86357.3-86411.6" - wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:86412.3-86466.6" - wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:86467.3-86521.6" - wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:85972.3-86026.6" - wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:85697.3-85751.6" - wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:85752.3-85806.6" - wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:86082.3-86136.6" - wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:85422.3-85476.6" - wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:86192.3-86246.6" - wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:86522.3-86576.6" - wire width 2 $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:85532.3-85586.6" - wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:86027.3-86081.6" - wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:86247.3-86301.6" - wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:86137.3-86191.6" - wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:85917.3-85971.6" - wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:85477.3-85531.6" - wire width 2 $1\dec31_dec_sub11_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub11_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub11_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub11_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub11_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub11_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub11_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub11_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub11_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub11_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub11_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub11_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub11_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub11_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub11_upd - attribute \src "libresoc.v:85110.7-85110.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:85110.7-85110.20" - process $proc$libresoc.v:85110$3836 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:85367.3-85421.6" - process $proc$libresoc.v:85367$3812 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] - attribute \src "libresoc.v:85368.5-85368.29" - switch \initial - attribute \src "libresoc.v:85368.9-85368.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 - case - assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] - end - attribute \src "libresoc.v:85422.3-85476.6" - process $proc$libresoc.v:85422$3813 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:85423.5-85423.29" - switch \initial - attribute \src "libresoc.v:85423.9-85423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] - end - attribute \src "libresoc.v:85477.3-85531.6" - process $proc$libresoc.v:85477$3814 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:85478.5-85478.29" - switch \initial - attribute \src "libresoc.v:85478.9-85478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub11_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] - end - attribute \src "libresoc.v:85532.3-85586.6" - process $proc$libresoc.v:85532$3815 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:85533.5-85533.29" - switch \initial - attribute \src "libresoc.v:85533.9-85533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] - end - attribute \src "libresoc.v:85587.3-85641.6" - process $proc$libresoc.v:85587$3816 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:85588.5-85588.29" - switch \initial - attribute \src "libresoc.v:85588.9-85588.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] - end - attribute \src "libresoc.v:85642.3-85696.6" - process $proc$libresoc.v:85642$3817 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:85643.5-85643.29" - switch \initial - attribute \src "libresoc.v:85643.9-85643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 - case - assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] - end - attribute \src "libresoc.v:85697.3-85751.6" - process $proc$libresoc.v:85697$3818 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:85698.5-85698.29" - switch \initial - attribute \src "libresoc.v:85698.9-85698.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] - end - attribute \src "libresoc.v:85752.3-85806.6" - process $proc$libresoc.v:85752$3819 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:85753.5-85753.29" - switch \initial - attribute \src "libresoc.v:85753.9-85753.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] - end - attribute \src "libresoc.v:85807.3-85861.6" - process $proc$libresoc.v:85807$3820 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:85808.5-85808.29" - switch \initial - attribute \src "libresoc.v:85808.9-85808.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] - end - attribute \src "libresoc.v:85862.3-85916.6" - process $proc$libresoc.v:85862$3821 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:85863.5-85863.29" - switch \initial - attribute \src "libresoc.v:85863.9-85863.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_br[0:0] 1'0 - case - assign $1\dec31_dec_sub11_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] - end - attribute \src "libresoc.v:85917.3-85971.6" - process $proc$libresoc.v:85917$3822 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:85918.5-85918.29" - switch \initial - attribute \src "libresoc.v:85918.9-85918.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] - end - attribute \src "libresoc.v:85972.3-86026.6" - process $proc$libresoc.v:85972$3823 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:85973.5-85973.29" - switch \initial - attribute \src "libresoc.v:85973.9-85973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 - case - assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] - end - attribute \src "libresoc.v:86027.3-86081.6" - process $proc$libresoc.v:86027$3824 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:86028.5-86028.29" - switch \initial - attribute \src "libresoc.v:86028.9-86028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] - end - attribute \src "libresoc.v:86082.3-86136.6" - process $proc$libresoc.v:86082$3825 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:86083.5-86083.29" - switch \initial - attribute \src "libresoc.v:86083.9-86083.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] - end - attribute \src "libresoc.v:86137.3-86191.6" - process $proc$libresoc.v:86137$3826 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:86138.5-86138.29" - switch \initial - attribute \src "libresoc.v:86138.9-86138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub11_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] - end - attribute \src "libresoc.v:86192.3-86246.6" - process $proc$libresoc.v:86192$3827 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:86193.5-86193.29" - switch \initial - attribute \src "libresoc.v:86193.9-86193.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub11_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] - end - attribute \src "libresoc.v:86247.3-86301.6" - process $proc$libresoc.v:86247$3828 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:86248.5-86248.29" - switch \initial - attribute \src "libresoc.v:86248.9-86248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] - end - attribute \src "libresoc.v:86302.3-86356.6" - process $proc$libresoc.v:86302$3829 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:86303.5-86303.29" - switch \initial - attribute \src "libresoc.v:86303.9-86303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub11_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] - end - attribute \src "libresoc.v:86357.3-86411.6" - process $proc$libresoc.v:86357$3830 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:86358.5-86358.29" - switch \initial - attribute \src "libresoc.v:86358.9-86358.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] - end - attribute \src "libresoc.v:86412.3-86466.6" - process $proc$libresoc.v:86412$3831 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:86413.5-86413.29" - switch \initial - attribute \src "libresoc.v:86413.9-86413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] - end - attribute \src "libresoc.v:86467.3-86521.6" - process $proc$libresoc.v:86467$3832 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:86468.5-86468.29" - switch \initial - attribute \src "libresoc.v:86468.9-86468.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] - end - attribute \src "libresoc.v:86522.3-86576.6" - process $proc$libresoc.v:86522$3833 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] - attribute \src "libresoc.v:86523.5-86523.29" - switch \initial - attribute \src "libresoc.v:86523.9-86523.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] - end - attribute \src "libresoc.v:86577.3-86631.6" - process $proc$libresoc.v:86577$3834 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:86578.5-86578.29" - switch \initial - attribute \src "libresoc.v:86578.9-86578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] - end - attribute \src "libresoc.v:86632.3-86686.6" - process $proc$libresoc.v:86632$3835 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:86633.5-86633.29" - switch \initial - attribute \src "libresoc.v:86633.9-86633.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:86692.1-89423.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" -attribute \generator "nMigen" -module \dec31_dec_sub15 - attribute \src "libresoc.v:87465.3-87567.6" - wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87877.3-87979.6" - wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:89216.3-89318.6" - wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:89319.3-89421.6" - wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:87362.3-87464.6" - wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:87774.3-87876.6" - wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:88701.3-88803.6" - wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:86950.3-87052.6" - wire width 12 $0\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:88804.3-88906.6" - wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88907.3-89009.6" - wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:89010.3-89112.6" - wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:88083.3-88185.6" - wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:87568.3-87670.6" - wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:87671.3-87773.6" - wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:88289.3-88391.6" - wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:87053.3-87155.6" - wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:88495.3-88597.6" - wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:89113.3-89215.6" - wire width 2 $0\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:87259.3-87361.6" - wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:88186.3-88288.6" - wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:88598.3-88700.6" - wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:88392.3-88494.6" - wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:87980.3-88082.6" - wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:87156.3-87258.6" - wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:86693.7-86693.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:87465.3-87567.6" - wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87877.3-87979.6" - wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:89216.3-89318.6" - wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:89319.3-89421.6" - wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:87362.3-87464.6" - wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:87774.3-87876.6" - wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:88701.3-88803.6" - wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:86950.3-87052.6" - wire width 12 $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:88804.3-88906.6" - wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88907.3-89009.6" - wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:89010.3-89112.6" - wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:88083.3-88185.6" - wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:87568.3-87670.6" - wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:87671.3-87773.6" - wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:88289.3-88391.6" - wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:87053.3-87155.6" - wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:88495.3-88597.6" - wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:89113.3-89215.6" - wire width 2 $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:87259.3-87361.6" - wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:88186.3-88288.6" - wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:88598.3-88700.6" - wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:88392.3-88494.6" - wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:87980.3-88082.6" - wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:87156.3-87258.6" - wire width 2 $1\dec31_dec_sub15_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub15_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub15_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub15_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub15_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub15_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub15_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub15_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub15_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub15_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub15_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub15_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub15_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub15_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub15_upd - attribute \src "libresoc.v:86693.7-86693.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:86693.7-86693.20" - process $proc$libresoc.v:86693$3861 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:86950.3-87052.6" - process $proc$libresoc.v:86950$3837 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] - attribute \src "libresoc.v:86951.5-86951.29" - switch \initial - attribute \src "libresoc.v:86951.9-86951.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] - end - attribute \src "libresoc.v:87053.3-87155.6" - process $proc$libresoc.v:87053$3838 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:87054.5-87054.29" - switch \initial - attribute \src "libresoc.v:87054.9-87054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] - end - attribute \src "libresoc.v:87156.3-87258.6" - process $proc$libresoc.v:87156$3839 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:87157.5-87157.29" - switch \initial - attribute \src "libresoc.v:87157.9-87157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub15_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] - end - attribute \src "libresoc.v:87259.3-87361.6" - process $proc$libresoc.v:87259$3840 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:87260.5-87260.29" - switch \initial - attribute \src "libresoc.v:87260.9-87260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] - end - attribute \src "libresoc.v:87362.3-87464.6" - process $proc$libresoc.v:87362$3841 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:87363.5-87363.29" - switch \initial - attribute \src "libresoc.v:87363.9-87363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] - end - attribute \src "libresoc.v:87465.3-87567.6" - process $proc$libresoc.v:87465$3842 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:87466.5-87466.29" - switch \initial - attribute \src "libresoc.v:87466.9-87466.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 - case - assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] - end - attribute \src "libresoc.v:87568.3-87670.6" - process $proc$libresoc.v:87568$3843 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:87569.5-87569.29" - switch \initial - attribute \src "libresoc.v:87569.9-87569.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] - end - attribute \src "libresoc.v:87671.3-87773.6" - process $proc$libresoc.v:87671$3844 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:87672.5-87672.29" - switch \initial - attribute \src "libresoc.v:87672.9-87672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] - end - attribute \src "libresoc.v:87774.3-87876.6" - process $proc$libresoc.v:87774$3845 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:87775.5-87775.29" - switch \initial - attribute \src "libresoc.v:87775.9-87775.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] - end - attribute \src "libresoc.v:87877.3-87979.6" - process $proc$libresoc.v:87877$3846 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:87878.5-87878.29" - switch \initial - attribute \src "libresoc.v:87878.9-87878.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_br[0:0] 1'0 - case - assign $1\dec31_dec_sub15_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] - end - attribute \src "libresoc.v:87980.3-88082.6" - process $proc$libresoc.v:87980$3847 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:87981.5-87981.29" - switch \initial - attribute \src "libresoc.v:87981.9-87981.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] - end - attribute \src "libresoc.v:88083.3-88185.6" - process $proc$libresoc.v:88083$3848 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:88084.5-88084.29" - switch \initial - attribute \src "libresoc.v:88084.9-88084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 - case - assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] - end - attribute \src "libresoc.v:88186.3-88288.6" - process $proc$libresoc.v:88186$3849 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:88187.5-88187.29" - switch \initial - attribute \src "libresoc.v:88187.9-88187.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] - end - attribute \src "libresoc.v:88289.3-88391.6" - process $proc$libresoc.v:88289$3850 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:88290.5-88290.29" - switch \initial - attribute \src "libresoc.v:88290.9-88290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] - end - attribute \src "libresoc.v:88392.3-88494.6" - process $proc$libresoc.v:88392$3851 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:88393.5-88393.29" - switch \initial - attribute \src "libresoc.v:88393.9-88393.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub15_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] - end - attribute \src "libresoc.v:88495.3-88597.6" - process $proc$libresoc.v:88495$3852 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:88496.5-88496.29" - switch \initial - attribute \src "libresoc.v:88496.9-88496.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub15_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] - end - attribute \src "libresoc.v:88598.3-88700.6" - process $proc$libresoc.v:88598$3853 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:88599.5-88599.29" - switch \initial - attribute \src "libresoc.v:88599.9-88599.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] - end - attribute \src "libresoc.v:88701.3-88803.6" - process $proc$libresoc.v:88701$3854 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:88702.5-88702.29" - switch \initial - attribute \src "libresoc.v:88702.9-88702.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_form[4:0] 5'10010 - case - assign $1\dec31_dec_sub15_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] - end - attribute \src "libresoc.v:88804.3-88906.6" - process $proc$libresoc.v:88804$3855 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:88805.5-88805.29" - switch \initial - attribute \src "libresoc.v:88805.9-88805.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] - end - attribute \src "libresoc.v:88907.3-89009.6" - process $proc$libresoc.v:88907$3856 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:88908.5-88908.29" - switch \initial - attribute \src "libresoc.v:88908.9-88908.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] - end - attribute \src "libresoc.v:89010.3-89112.6" - process $proc$libresoc.v:89010$3857 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:89011.5-89011.29" - switch \initial - attribute \src "libresoc.v:89011.9-89011.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] - end - attribute \src "libresoc.v:89113.3-89215.6" - process $proc$libresoc.v:89113$3858 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] - attribute \src "libresoc.v:89114.5-89114.29" - switch \initial - attribute \src "libresoc.v:89114.9-89114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] - end - attribute \src "libresoc.v:89216.3-89318.6" - process $proc$libresoc.v:89216$3859 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:89217.5-89217.29" - switch \initial - attribute \src "libresoc.v:89217.9-89217.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 - case - assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] - end - attribute \src "libresoc.v:89319.3-89421.6" - process $proc$libresoc.v:89319$3860 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:89320.5-89320.29" - switch \initial - attribute \src "libresoc.v:89320.9-89320.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:89427.1-89926.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" -attribute \generator "nMigen" -module \dec31_dec_sub16 - attribute \src "libresoc.v:89735.3-89744.6" - wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:89775.3-89784.6" - wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89905.3-89914.6" - wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89915.3-89924.6" - wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:89725.3-89734.6" - wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:89765.3-89774.6" - wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:89855.3-89864.6" - wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:89685.3-89694.6" - wire width 12 $0\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:89865.3-89874.6" - wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:89875.3-89884.6" - wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89885.3-89894.6" - wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:89795.3-89804.6" - wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:89745.3-89754.6" - wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:89755.3-89764.6" - wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:89815.3-89824.6" - wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:89695.3-89704.6" - wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:89835.3-89844.6" - wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89895.3-89904.6" - wire width 2 $0\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:89715.3-89724.6" - wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:89805.3-89814.6" - wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:89845.3-89854.6" - wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:89825.3-89834.6" - wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:89785.3-89794.6" - wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:89705.3-89714.6" - wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:89428.7-89428.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:89735.3-89744.6" - wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:89775.3-89784.6" - wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89905.3-89914.6" - wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89915.3-89924.6" - wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:89725.3-89734.6" - wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:89765.3-89774.6" - wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:89855.3-89864.6" - wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:89685.3-89694.6" - wire width 12 $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:89865.3-89874.6" - wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:89875.3-89884.6" - wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89885.3-89894.6" - wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:89795.3-89804.6" - wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:89745.3-89754.6" - wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:89755.3-89764.6" - wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:89815.3-89824.6" - wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:89695.3-89704.6" - wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:89835.3-89844.6" - wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89895.3-89904.6" - wire width 2 $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:89715.3-89724.6" - wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:89805.3-89814.6" - wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:89845.3-89854.6" - wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:89825.3-89834.6" - wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:89785.3-89794.6" - wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:89705.3-89714.6" - wire width 2 $1\dec31_dec_sub16_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub16_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub16_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub16_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub16_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub16_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub16_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub16_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub16_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub16_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub16_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub16_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub16_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub16_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub16_upd - attribute \src "libresoc.v:89428.7-89428.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:89428.7-89428.20" - process $proc$libresoc.v:89428$3886 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:89685.3-89694.6" - process $proc$libresoc.v:89685$3862 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] - attribute \src "libresoc.v:89686.5-89686.29" - switch \initial - attribute \src "libresoc.v:89686.9-89686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 - case - assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] - end - attribute \src "libresoc.v:89695.3-89704.6" - process $proc$libresoc.v:89695$3863 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:89696.5-89696.29" - switch \initial - attribute \src "libresoc.v:89696.9-89696.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] - end - attribute \src "libresoc.v:89705.3-89714.6" - process $proc$libresoc.v:89705$3864 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:89706.5-89706.29" - switch \initial - attribute \src "libresoc.v:89706.9-89706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub16_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] - end - attribute \src "libresoc.v:89715.3-89724.6" - process $proc$libresoc.v:89715$3865 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:89716.5-89716.29" - switch \initial - attribute \src "libresoc.v:89716.9-89716.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] - end - attribute \src "libresoc.v:89725.3-89734.6" - process $proc$libresoc.v:89725$3866 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:89726.5-89726.29" - switch \initial - attribute \src "libresoc.v:89726.9-89726.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] - end - attribute \src "libresoc.v:89735.3-89744.6" - process $proc$libresoc.v:89735$3867 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:89736.5-89736.29" - switch \initial - attribute \src "libresoc.v:89736.9-89736.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 - case - assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] - end - attribute \src "libresoc.v:89745.3-89754.6" - process $proc$libresoc.v:89745$3868 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:89746.5-89746.29" - switch \initial - attribute \src "libresoc.v:89746.9-89746.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] - end - attribute \src "libresoc.v:89755.3-89764.6" - process $proc$libresoc.v:89755$3869 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:89756.5-89756.29" - switch \initial - attribute \src "libresoc.v:89756.9-89756.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] - end - attribute \src "libresoc.v:89765.3-89774.6" - process $proc$libresoc.v:89765$3870 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:89766.5-89766.29" - switch \initial - attribute \src "libresoc.v:89766.9-89766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] - end - attribute \src "libresoc.v:89775.3-89784.6" - process $proc$libresoc.v:89775$3871 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:89776.5-89776.29" - switch \initial - attribute \src "libresoc.v:89776.9-89776.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_br[0:0] 1'0 - case - assign $1\dec31_dec_sub16_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] - end - attribute \src "libresoc.v:89785.3-89794.6" - process $proc$libresoc.v:89785$3872 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:89786.5-89786.29" - switch \initial - attribute \src "libresoc.v:89786.9-89786.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] - end - attribute \src "libresoc.v:89795.3-89804.6" - process $proc$libresoc.v:89795$3873 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:89796.5-89796.29" - switch \initial - attribute \src "libresoc.v:89796.9-89796.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 - case - assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] - end - attribute \src "libresoc.v:89805.3-89814.6" - process $proc$libresoc.v:89805$3874 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:89806.5-89806.29" - switch \initial - attribute \src "libresoc.v:89806.9-89806.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] - end - attribute \src "libresoc.v:89815.3-89824.6" - process $proc$libresoc.v:89815$3875 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:89816.5-89816.29" - switch \initial - attribute \src "libresoc.v:89816.9-89816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] - end - attribute \src "libresoc.v:89825.3-89834.6" - process $proc$libresoc.v:89825$3876 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:89826.5-89826.29" - switch \initial - attribute \src "libresoc.v:89826.9-89826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] - end - attribute \src "libresoc.v:89835.3-89844.6" - process $proc$libresoc.v:89835$3877 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:89836.5-89836.29" - switch \initial - attribute \src "libresoc.v:89836.9-89836.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub16_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] - end - attribute \src "libresoc.v:89845.3-89854.6" - process $proc$libresoc.v:89845$3878 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:89846.5-89846.29" - switch \initial - attribute \src "libresoc.v:89846.9-89846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] - end - attribute \src "libresoc.v:89855.3-89864.6" - process $proc$libresoc.v:89855$3879 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:89856.5-89856.29" - switch \initial - attribute \src "libresoc.v:89856.9-89856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub16_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] - end - attribute \src "libresoc.v:89865.3-89874.6" - process $proc$libresoc.v:89865$3880 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:89866.5-89866.29" - switch \initial - attribute \src "libresoc.v:89866.9-89866.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] - end - attribute \src "libresoc.v:89875.3-89884.6" - process $proc$libresoc.v:89875$3881 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:89876.5-89876.29" - switch \initial - attribute \src "libresoc.v:89876.9-89876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] - end - attribute \src "libresoc.v:89885.3-89894.6" - process $proc$libresoc.v:89885$3882 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:89886.5-89886.29" - switch \initial - attribute \src "libresoc.v:89886.9-89886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] - end - attribute \src "libresoc.v:89895.3-89904.6" - process $proc$libresoc.v:89895$3883 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] - attribute \src "libresoc.v:89896.5-89896.29" - switch \initial - attribute \src "libresoc.v:89896.9-89896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] - end - attribute \src "libresoc.v:89905.3-89914.6" - process $proc$libresoc.v:89905$3884 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:89906.5-89906.29" - switch \initial - attribute \src "libresoc.v:89906.9-89906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 - case - assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] - end - attribute \src "libresoc.v:89915.3-89924.6" - process $proc$libresoc.v:89915$3885 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:89916.5-89916.29" - switch \initial - attribute \src "libresoc.v:89916.9-89916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 - case - assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:89930.1-90717.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" -attribute \generator "nMigen" -module \dec31_dec_sub18 - attribute \src "libresoc.v:90298.3-90319.6" - wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:90386.3-90407.6" - wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:90672.3-90693.6" - wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:90694.3-90715.6" - wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:90276.3-90297.6" - wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:90364.3-90385.6" - wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:90562.3-90583.6" - wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:90188.3-90209.6" - wire width 12 $0\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:90584.3-90605.6" - wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:90606.3-90627.6" - wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:90628.3-90649.6" - wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:90430.3-90451.6" - wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:90320.3-90341.6" - wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:90342.3-90363.6" - wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:90474.3-90495.6" - wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:90210.3-90231.6" - wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:90518.3-90539.6" - wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:90650.3-90671.6" - wire width 2 $0\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:90254.3-90275.6" - wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:90452.3-90473.6" - wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:90540.3-90561.6" - wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:90496.3-90517.6" - wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:90408.3-90429.6" - wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:90232.3-90253.6" - wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:89931.7-89931.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:90298.3-90319.6" - wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:90386.3-90407.6" - wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:90672.3-90693.6" - wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:90694.3-90715.6" - wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:90276.3-90297.6" - wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:90364.3-90385.6" - wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:90562.3-90583.6" - wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:90188.3-90209.6" - wire width 12 $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:90584.3-90605.6" - wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:90606.3-90627.6" - wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:90628.3-90649.6" - wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:90430.3-90451.6" - wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:90320.3-90341.6" - wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:90342.3-90363.6" - wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:90474.3-90495.6" - wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:90210.3-90231.6" - wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:90518.3-90539.6" - wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:90650.3-90671.6" - wire width 2 $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:90254.3-90275.6" - wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:90452.3-90473.6" - wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:90540.3-90561.6" - wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:90496.3-90517.6" - wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:90408.3-90429.6" - wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:90232.3-90253.6" - wire width 2 $1\dec31_dec_sub18_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub18_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub18_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub18_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub18_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub18_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub18_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub18_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub18_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub18_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub18_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub18_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub18_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub18_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub18_upd - attribute \src "libresoc.v:89931.7-89931.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:89931.7-89931.20" - process $proc$libresoc.v:89931$3911 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:90188.3-90209.6" - process $proc$libresoc.v:90188$3887 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] - attribute \src "libresoc.v:90189.5-90189.29" - switch \initial - attribute \src "libresoc.v:90189.9-90189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 - case - assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] - end - attribute \src "libresoc.v:90210.3-90231.6" - process $proc$libresoc.v:90210$3888 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:90211.5-90211.29" - switch \initial - attribute \src "libresoc.v:90211.9-90211.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] - end - attribute \src "libresoc.v:90232.3-90253.6" - process $proc$libresoc.v:90232$3889 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:90233.5-90233.29" - switch \initial - attribute \src "libresoc.v:90233.9-90233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub18_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] - end - attribute \src "libresoc.v:90254.3-90275.6" - process $proc$libresoc.v:90254$3890 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:90255.5-90255.29" - switch \initial - attribute \src "libresoc.v:90255.9-90255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] - end - attribute \src "libresoc.v:90276.3-90297.6" - process $proc$libresoc.v:90276$3891 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:90277.5-90277.29" - switch \initial - attribute \src "libresoc.v:90277.9-90277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] - end - attribute \src "libresoc.v:90298.3-90319.6" - process $proc$libresoc.v:90298$3892 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:90299.5-90299.29" - switch \initial - attribute \src "libresoc.v:90299.9-90299.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 - case - assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] - end - attribute \src "libresoc.v:90320.3-90341.6" - process $proc$libresoc.v:90320$3893 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:90321.5-90321.29" - switch \initial - attribute \src "libresoc.v:90321.9-90321.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] - end - attribute \src "libresoc.v:90342.3-90363.6" - process $proc$libresoc.v:90342$3894 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:90343.5-90343.29" - switch \initial - attribute \src "libresoc.v:90343.9-90343.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] - end - attribute \src "libresoc.v:90364.3-90385.6" - process $proc$libresoc.v:90364$3895 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:90365.5-90365.29" - switch \initial - attribute \src "libresoc.v:90365.9-90365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] - end - attribute \src "libresoc.v:90386.3-90407.6" - process $proc$libresoc.v:90386$3896 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:90387.5-90387.29" - switch \initial - attribute \src "libresoc.v:90387.9-90387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_br[0:0] 1'0 - case - assign $1\dec31_dec_sub18_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] - end - attribute \src "libresoc.v:90408.3-90429.6" - process $proc$libresoc.v:90408$3897 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:90409.5-90409.29" - switch \initial - attribute \src "libresoc.v:90409.9-90409.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] - end - attribute \src "libresoc.v:90430.3-90451.6" - process $proc$libresoc.v:90430$3898 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:90431.5-90431.29" - switch \initial - attribute \src "libresoc.v:90431.9-90431.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 - case - assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] - end - attribute \src "libresoc.v:90452.3-90473.6" - process $proc$libresoc.v:90452$3899 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:90453.5-90453.29" - switch \initial - attribute \src "libresoc.v:90453.9-90453.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] - end - attribute \src "libresoc.v:90474.3-90495.6" - process $proc$libresoc.v:90474$3900 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:90475.5-90475.29" - switch \initial - attribute \src "libresoc.v:90475.9-90475.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] - end - attribute \src "libresoc.v:90496.3-90517.6" - process $proc$libresoc.v:90496$3901 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:90497.5-90497.29" - switch \initial - attribute \src "libresoc.v:90497.9-90497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] - end - attribute \src "libresoc.v:90518.3-90539.6" - process $proc$libresoc.v:90518$3902 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:90519.5-90519.29" - switch \initial - attribute \src "libresoc.v:90519.9-90519.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub18_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] - end - attribute \src "libresoc.v:90540.3-90561.6" - process $proc$libresoc.v:90540$3903 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:90541.5-90541.29" - switch \initial - attribute \src "libresoc.v:90541.9-90541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] - end - attribute \src "libresoc.v:90562.3-90583.6" - process $proc$libresoc.v:90562$3904 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:90563.5-90563.29" - switch \initial - attribute \src "libresoc.v:90563.9-90563.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub18_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] - end - attribute \src "libresoc.v:90584.3-90605.6" - process $proc$libresoc.v:90584$3905 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:90585.5-90585.29" - switch \initial - attribute \src "libresoc.v:90585.9-90585.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] - end - attribute \src "libresoc.v:90606.3-90627.6" - process $proc$libresoc.v:90606$3906 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:90607.5-90607.29" - switch \initial - attribute \src "libresoc.v:90607.9-90607.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] - end - attribute \src "libresoc.v:90628.3-90649.6" - process $proc$libresoc.v:90628$3907 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:90629.5-90629.29" - switch \initial - attribute \src "libresoc.v:90629.9-90629.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] - end - attribute \src "libresoc.v:90650.3-90671.6" - process $proc$libresoc.v:90650$3908 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] - attribute \src "libresoc.v:90651.5-90651.29" - switch \initial - attribute \src "libresoc.v:90651.9-90651.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] - end - attribute \src "libresoc.v:90672.3-90693.6" - process $proc$libresoc.v:90672$3909 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:90673.5-90673.29" - switch \initial - attribute \src "libresoc.v:90673.9-90673.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] - end - attribute \src "libresoc.v:90694.3-90715.6" - process $proc$libresoc.v:90694$3910 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:90695.5-90695.29" - switch \initial - attribute \src "libresoc.v:90695.9-90695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:90721.1-91436.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" -attribute \generator "nMigen" -module \dec31_dec_sub19 - attribute \src "libresoc.v:91074.3-91092.6" - wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:91150.3-91168.6" - wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:91397.3-91415.6" - wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:91416.3-91434.6" - wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:91055.3-91073.6" - wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:91131.3-91149.6" - wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:91302.3-91320.6" - wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:90979.3-90997.6" - wire width 12 $0\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:91321.3-91339.6" - wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:91340.3-91358.6" - wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:91359.3-91377.6" - wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:91188.3-91206.6" - wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:91093.3-91111.6" - wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:91112.3-91130.6" - wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:91226.3-91244.6" - wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:90998.3-91016.6" - wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:91264.3-91282.6" - wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:91378.3-91396.6" - wire width 2 $0\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:91036.3-91054.6" - wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:91207.3-91225.6" - wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:91283.3-91301.6" - wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:91245.3-91263.6" - wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:91169.3-91187.6" - wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:91017.3-91035.6" - wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:90722.7-90722.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:91074.3-91092.6" - wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:91150.3-91168.6" - wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:91397.3-91415.6" - wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:91416.3-91434.6" - wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:91055.3-91073.6" - wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:91131.3-91149.6" - wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:91302.3-91320.6" - wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:90979.3-90997.6" - wire width 12 $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:91321.3-91339.6" - wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:91340.3-91358.6" - wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:91359.3-91377.6" - wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:91188.3-91206.6" - wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:91093.3-91111.6" - wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:91112.3-91130.6" - wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:91226.3-91244.6" - wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:90998.3-91016.6" - wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:91264.3-91282.6" - wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:91378.3-91396.6" - wire width 2 $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:91036.3-91054.6" - wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:91207.3-91225.6" - wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:91283.3-91301.6" - wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:91245.3-91263.6" - wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:91169.3-91187.6" - wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:91017.3-91035.6" - wire width 2 $1\dec31_dec_sub19_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub19_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub19_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub19_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub19_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub19_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub19_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub19_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub19_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub19_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub19_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub19_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub19_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub19_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub19_upd - attribute \src "libresoc.v:90722.7-90722.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:90722.7-90722.20" - process $proc$libresoc.v:90722$3936 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:90979.3-90997.6" - process $proc$libresoc.v:90979$3912 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] - attribute \src "libresoc.v:90980.5-90980.29" - switch \initial - attribute \src "libresoc.v:90980.9-90980.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 - case - assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] - end - attribute \src "libresoc.v:90998.3-91016.6" - process $proc$libresoc.v:90998$3913 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:90999.5-90999.29" - switch \initial - attribute \src "libresoc.v:90999.9-90999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] - end - attribute \src "libresoc.v:91017.3-91035.6" - process $proc$libresoc.v:91017$3914 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:91018.5-91018.29" - switch \initial - attribute \src "libresoc.v:91018.9-91018.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub19_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] - end - attribute \src "libresoc.v:91036.3-91054.6" - process $proc$libresoc.v:91036$3915 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:91037.5-91037.29" - switch \initial - attribute \src "libresoc.v:91037.9-91037.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] - end - attribute \src "libresoc.v:91055.3-91073.6" - process $proc$libresoc.v:91055$3916 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:91056.5-91056.29" - switch \initial - attribute \src "libresoc.v:91056.9-91056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] - end - attribute \src "libresoc.v:91074.3-91092.6" - process $proc$libresoc.v:91074$3917 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:91075.5-91075.29" - switch \initial - attribute \src "libresoc.v:91075.9-91075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 - case - assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] - end - attribute \src "libresoc.v:91093.3-91111.6" - process $proc$libresoc.v:91093$3918 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:91094.5-91094.29" - switch \initial - attribute \src "libresoc.v:91094.9-91094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] - end - attribute \src "libresoc.v:91112.3-91130.6" - process $proc$libresoc.v:91112$3919 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:91113.5-91113.29" - switch \initial - attribute \src "libresoc.v:91113.9-91113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] - end - attribute \src "libresoc.v:91131.3-91149.6" - process $proc$libresoc.v:91131$3920 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:91132.5-91132.29" - switch \initial - attribute \src "libresoc.v:91132.9-91132.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] - end - attribute \src "libresoc.v:91150.3-91168.6" - process $proc$libresoc.v:91150$3921 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:91151.5-91151.29" - switch \initial - attribute \src "libresoc.v:91151.9-91151.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_br[0:0] 1'0 - case - assign $1\dec31_dec_sub19_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] - end - attribute \src "libresoc.v:91169.3-91187.6" - process $proc$libresoc.v:91169$3922 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:91170.5-91170.29" - switch \initial - attribute \src "libresoc.v:91170.9-91170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] - end - attribute \src "libresoc.v:91188.3-91206.6" - process $proc$libresoc.v:91188$3923 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:91189.5-91189.29" - switch \initial - attribute \src "libresoc.v:91189.9-91189.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 - case - assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] - end - attribute \src "libresoc.v:91207.3-91225.6" - process $proc$libresoc.v:91207$3924 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:91208.5-91208.29" - switch \initial - attribute \src "libresoc.v:91208.9-91208.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] - end - attribute \src "libresoc.v:91226.3-91244.6" - process $proc$libresoc.v:91226$3925 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:91227.5-91227.29" - switch \initial - attribute \src "libresoc.v:91227.9-91227.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] - end - attribute \src "libresoc.v:91245.3-91263.6" - process $proc$libresoc.v:91245$3926 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:91246.5-91246.29" - switch \initial - attribute \src "libresoc.v:91246.9-91246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] - end - attribute \src "libresoc.v:91264.3-91282.6" - process $proc$libresoc.v:91264$3927 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:91265.5-91265.29" - switch \initial - attribute \src "libresoc.v:91265.9-91265.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub19_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] - end - attribute \src "libresoc.v:91283.3-91301.6" - process $proc$libresoc.v:91283$3928 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:91284.5-91284.29" - switch \initial - attribute \src "libresoc.v:91284.9-91284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] - end - attribute \src "libresoc.v:91302.3-91320.6" - process $proc$libresoc.v:91302$3929 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:91303.5-91303.29" - switch \initial - attribute \src "libresoc.v:91303.9-91303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_form[4:0] 5'01010 - case - assign $1\dec31_dec_sub19_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] - end - attribute \src "libresoc.v:91321.3-91339.6" - process $proc$libresoc.v:91321$3930 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:91322.5-91322.29" - switch \initial - attribute \src "libresoc.v:91322.9-91322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] - end - attribute \src "libresoc.v:91340.3-91358.6" - process $proc$libresoc.v:91340$3931 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:91341.5-91341.29" - switch \initial - attribute \src "libresoc.v:91341.9-91341.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] - end - attribute \src "libresoc.v:91359.3-91377.6" - process $proc$libresoc.v:91359$3932 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:91360.5-91360.29" - switch \initial - attribute \src "libresoc.v:91360.9-91360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] - end - attribute \src "libresoc.v:91378.3-91396.6" - process $proc$libresoc.v:91378$3933 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] - attribute \src "libresoc.v:91379.5-91379.29" - switch \initial - attribute \src "libresoc.v:91379.9-91379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 - case - assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] - end - attribute \src "libresoc.v:91397.3-91415.6" - process $proc$libresoc.v:91397$3934 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:91398.5-91398.29" - switch \initial - attribute \src "libresoc.v:91398.9-91398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] - end - attribute \src "libresoc.v:91416.3-91434.6" - process $proc$libresoc.v:91416$3935 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:91417.5-91417.29" - switch \initial - attribute \src "libresoc.v:91417.9-91417.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:91440.1-92299.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" -attribute \generator "nMigen" -module \dec31_dec_sub20 - attribute \src "libresoc.v:91823.3-91847.6" - wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91923.3-91947.6" - wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:92248.3-92272.6" - wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:92273.3-92297.6" - wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:91798.3-91822.6" - wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91898.3-91922.6" - wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:92123.3-92147.6" - wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:91698.3-91722.6" - wire width 12 $0\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:92148.3-92172.6" - wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:92173.3-92197.6" - wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:92198.3-92222.6" - wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:91973.3-91997.6" - wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:91848.3-91872.6" - wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:91873.3-91897.6" - wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:92023.3-92047.6" - wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:91723.3-91747.6" - wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:92073.3-92097.6" - wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:92223.3-92247.6" - wire width 2 $0\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:91773.3-91797.6" - wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91998.3-92022.6" - wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:92098.3-92122.6" - wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:92048.3-92072.6" - wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91948.3-91972.6" - wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:91748.3-91772.6" - wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:91441.7-91441.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:91823.3-91847.6" - wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91923.3-91947.6" - wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:92248.3-92272.6" - wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:92273.3-92297.6" - wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:91798.3-91822.6" - wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91898.3-91922.6" - wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:92123.3-92147.6" - wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:91698.3-91722.6" - wire width 12 $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:92148.3-92172.6" - wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:92173.3-92197.6" - wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:92198.3-92222.6" - wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:91973.3-91997.6" - wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:91848.3-91872.6" - wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:91873.3-91897.6" - wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:92023.3-92047.6" - wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:91723.3-91747.6" - wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:92073.3-92097.6" - wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:92223.3-92247.6" - wire width 2 $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:91773.3-91797.6" - wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91998.3-92022.6" - wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:92098.3-92122.6" - wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:92048.3-92072.6" - wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:91948.3-91972.6" - wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:91748.3-91772.6" - wire width 2 $1\dec31_dec_sub20_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub20_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub20_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub20_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub20_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub20_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub20_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub20_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub20_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub20_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub20_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub20_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub20_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub20_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub20_upd - attribute \src "libresoc.v:91441.7-91441.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:91441.7-91441.20" - process $proc$libresoc.v:91441$3961 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:91698.3-91722.6" - process $proc$libresoc.v:91698$3937 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] - attribute \src "libresoc.v:91699.5-91699.29" - switch \initial - attribute \src "libresoc.v:91699.9-91699.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] - end - attribute \src "libresoc.v:91723.3-91747.6" - process $proc$libresoc.v:91723$3938 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:91724.5-91724.29" - switch \initial - attribute \src "libresoc.v:91724.9-91724.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 - case - assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] - end - attribute \src "libresoc.v:91748.3-91772.6" - process $proc$libresoc.v:91748$3939 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:91749.5-91749.29" - switch \initial - attribute \src "libresoc.v:91749.9-91749.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub20_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] - end - attribute \src "libresoc.v:91773.3-91797.6" - process $proc$libresoc.v:91773$3940 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:91774.5-91774.29" - switch \initial - attribute \src "libresoc.v:91774.9-91774.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] - end - attribute \src "libresoc.v:91798.3-91822.6" - process $proc$libresoc.v:91798$3941 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:91799.5-91799.29" - switch \initial - attribute \src "libresoc.v:91799.9-91799.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] - end - attribute \src "libresoc.v:91823.3-91847.6" - process $proc$libresoc.v:91823$3942 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:91824.5-91824.29" - switch \initial - attribute \src "libresoc.v:91824.9-91824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 - case - assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] - end - attribute \src "libresoc.v:91848.3-91872.6" - process $proc$libresoc.v:91848$3943 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:91849.5-91849.29" - switch \initial - attribute \src "libresoc.v:91849.9-91849.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] - end - attribute \src "libresoc.v:91873.3-91897.6" - process $proc$libresoc.v:91873$3944 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:91874.5-91874.29" - switch \initial - attribute \src "libresoc.v:91874.9-91874.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] - end - attribute \src "libresoc.v:91898.3-91922.6" - process $proc$libresoc.v:91898$3945 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:91899.5-91899.29" - switch \initial - attribute \src "libresoc.v:91899.9-91899.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] - end - attribute \src "libresoc.v:91923.3-91947.6" - process $proc$libresoc.v:91923$3946 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:91924.5-91924.29" - switch \initial - attribute \src "libresoc.v:91924.9-91924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_br[0:0] 1'1 - case - assign $1\dec31_dec_sub20_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] - end - attribute \src "libresoc.v:91948.3-91972.6" - process $proc$libresoc.v:91948$3947 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:91949.5-91949.29" - switch \initial - attribute \src "libresoc.v:91949.9-91949.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] - end - attribute \src "libresoc.v:91973.3-91997.6" - process $proc$libresoc.v:91973$3948 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:91974.5-91974.29" - switch \initial - attribute \src "libresoc.v:91974.9-91974.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] - end - attribute \src "libresoc.v:91998.3-92022.6" - process $proc$libresoc.v:91998$3949 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:91999.5-91999.29" - switch \initial - attribute \src "libresoc.v:91999.9-91999.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] - end - attribute \src "libresoc.v:92023.3-92047.6" - process $proc$libresoc.v:92023$3950 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:92024.5-92024.29" - switch \initial - attribute \src "libresoc.v:92024.9-92024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] - end - attribute \src "libresoc.v:92048.3-92072.6" - process $proc$libresoc.v:92048$3951 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:92049.5-92049.29" - switch \initial - attribute \src "libresoc.v:92049.9-92049.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub20_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] - end - attribute \src "libresoc.v:92073.3-92097.6" - process $proc$libresoc.v:92073$3952 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:92074.5-92074.29" - switch \initial - attribute \src "libresoc.v:92074.9-92074.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub20_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] - end - attribute \src "libresoc.v:92098.3-92122.6" - process $proc$libresoc.v:92098$3953 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:92099.5-92099.29" - switch \initial - attribute \src "libresoc.v:92099.9-92099.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] - end - attribute \src "libresoc.v:92123.3-92147.6" - process $proc$libresoc.v:92123$3954 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:92124.5-92124.29" - switch \initial - attribute \src "libresoc.v:92124.9-92124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub20_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] - end - attribute \src "libresoc.v:92148.3-92172.6" - process $proc$libresoc.v:92148$3955 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:92149.5-92149.29" - switch \initial - attribute \src "libresoc.v:92149.9-92149.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] - end - attribute \src "libresoc.v:92173.3-92197.6" - process $proc$libresoc.v:92173$3956 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:92174.5-92174.29" - switch \initial - attribute \src "libresoc.v:92174.9-92174.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] - end - attribute \src "libresoc.v:92198.3-92222.6" - process $proc$libresoc.v:92198$3957 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:92199.5-92199.29" - switch \initial - attribute \src "libresoc.v:92199.9-92199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] - end - attribute \src "libresoc.v:92223.3-92247.6" - process $proc$libresoc.v:92223$3958 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] - attribute \src "libresoc.v:92224.5-92224.29" - switch \initial - attribute \src "libresoc.v:92224.9-92224.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] - end - attribute \src "libresoc.v:92248.3-92272.6" - process $proc$libresoc.v:92248$3959 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:92249.5-92249.29" - switch \initial - attribute \src "libresoc.v:92249.9-92249.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] - end - attribute \src "libresoc.v:92273.3-92297.6" - process $proc$libresoc.v:92273$3960 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:92274.5-92274.29" - switch \initial - attribute \src "libresoc.v:92274.9-92274.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:92303.1-93720.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" -attribute \generator "nMigen" -module \dec31_dec_sub21 - attribute \src "libresoc.v:93345.3-93375.6" - wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:92953.3-93001.6" - wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:93621.3-93669.6" - wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:93670.3-93718.6" - wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:92757.3-92805.6" - wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92904.3-92952.6" - wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:93376.3-93424.6" - wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:92561.3-92609.6" - wire width 12 $0\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:93425.3-93473.6" - wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:93474.3-93522.6" - wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:93523.3-93571.6" - wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:93100.3-93148.6" - wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:92806.3-92854.6" - wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:92855.3-92903.6" - wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:93149.3-93197.6" - wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:92610.3-92658.6" - wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:93247.3-93295.6" - wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:93572.3-93620.6" - wire width 2 $0\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:92708.3-92756.6" - wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:93051.3-93099.6" - wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:93296.3-93344.6" - wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:93198.3-93246.6" - wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:93002.3-93050.6" - wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:92659.3-92707.6" - wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:92304.7-92304.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:93345.3-93375.6" - wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:92953.3-93001.6" - wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:93621.3-93669.6" - wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:93670.3-93718.6" - wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:92757.3-92805.6" - wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92904.3-92952.6" - wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:93376.3-93424.6" - wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:92561.3-92609.6" - wire width 12 $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:93425.3-93473.6" - wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:93474.3-93522.6" - wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:93523.3-93571.6" - wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:93100.3-93148.6" - wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:92806.3-92854.6" - wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:92855.3-92903.6" - wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:93149.3-93197.6" - wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:92610.3-92658.6" - wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:93247.3-93295.6" - wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:93572.3-93620.6" - wire width 2 $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:92708.3-92756.6" - wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:93051.3-93099.6" - wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:93296.3-93344.6" - wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:93198.3-93246.6" - wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:93002.3-93050.6" - wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:92659.3-92707.6" - wire width 2 $1\dec31_dec_sub21_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub21_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub21_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub21_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub21_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub21_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub21_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub21_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub21_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub21_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub21_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub21_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub21_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub21_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub21_upd - attribute \src "libresoc.v:92304.7-92304.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:92304.7-92304.20" - process $proc$libresoc.v:92304$3986 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:92561.3-92609.6" - process $proc$libresoc.v:92561$3962 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] - attribute \src "libresoc.v:92562.5-92562.29" - switch \initial - attribute \src "libresoc.v:92562.9-92562.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] - end - attribute \src "libresoc.v:92610.3-92658.6" - process $proc$libresoc.v:92610$3963 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:92611.5-92611.29" - switch \initial - attribute \src "libresoc.v:92611.9-92611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 - case - assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] - end - attribute \src "libresoc.v:92659.3-92707.6" - process $proc$libresoc.v:92659$3964 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:92660.5-92660.29" - switch \initial - attribute \src "libresoc.v:92660.9-92660.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_upd[1:0] 2'10 - case - assign $1\dec31_dec_sub21_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] - end - attribute \src "libresoc.v:92708.3-92756.6" - process $proc$libresoc.v:92708$3965 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:92709.5-92709.29" - switch \initial - attribute \src "libresoc.v:92709.9-92709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] - end - attribute \src "libresoc.v:92757.3-92805.6" - process $proc$libresoc.v:92757$3966 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:92758.5-92758.29" - switch \initial - attribute \src "libresoc.v:92758.9-92758.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] - end - attribute \src "libresoc.v:92806.3-92854.6" - process $proc$libresoc.v:92806$3967 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:92807.5-92807.29" - switch \initial - attribute \src "libresoc.v:92807.9-92807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] - end - attribute \src "libresoc.v:92855.3-92903.6" - process $proc$libresoc.v:92855$3968 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:92856.5-92856.29" - switch \initial - attribute \src "libresoc.v:92856.9-92856.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] - end - attribute \src "libresoc.v:92904.3-92952.6" - process $proc$libresoc.v:92904$3969 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:92905.5-92905.29" - switch \initial - attribute \src "libresoc.v:92905.9-92905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] - end - attribute \src "libresoc.v:92953.3-93001.6" - process $proc$libresoc.v:92953$3970 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:92954.5-92954.29" - switch \initial - attribute \src "libresoc.v:92954.9-92954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_br[0:0] 1'0 - case - assign $1\dec31_dec_sub21_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] - end - attribute \src "libresoc.v:93002.3-93050.6" - process $proc$libresoc.v:93002$3971 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:93003.5-93003.29" - switch \initial - attribute \src "libresoc.v:93003.9-93003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] - end - attribute \src "libresoc.v:93051.3-93099.6" - process $proc$libresoc.v:93051$3972 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:93052.5-93052.29" - switch \initial - attribute \src "libresoc.v:93052.9-93052.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] - end - attribute \src "libresoc.v:93100.3-93148.6" - process $proc$libresoc.v:93100$3973 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:93101.5-93101.29" - switch \initial - attribute \src "libresoc.v:93101.9-93101.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] - end - attribute \src "libresoc.v:93149.3-93197.6" - process $proc$libresoc.v:93149$3974 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:93150.5-93150.29" - switch \initial - attribute \src "libresoc.v:93150.9-93150.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] - end - attribute \src "libresoc.v:93198.3-93246.6" - process $proc$libresoc.v:93198$3975 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:93199.5-93199.29" - switch \initial - attribute \src "libresoc.v:93199.9-93199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub21_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] - end - attribute \src "libresoc.v:93247.3-93295.6" - process $proc$libresoc.v:93247$3976 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:93248.5-93248.29" - switch \initial - attribute \src "libresoc.v:93248.9-93248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub21_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] - end - attribute \src "libresoc.v:93296.3-93344.6" - process $proc$libresoc.v:93296$3977 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:93297.5-93297.29" - switch \initial - attribute \src "libresoc.v:93297.9-93297.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] - end - attribute \src "libresoc.v:93345.3-93375.6" - process $proc$libresoc.v:93345$3978 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:93346.5-93346.29" - switch \initial - attribute \src "libresoc.v:93346.9-93346.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 - case - assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] - end - attribute \src "libresoc.v:93376.3-93424.6" - process $proc$libresoc.v:93376$3979 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:93377.5-93377.29" - switch \initial - attribute \src "libresoc.v:93377.9-93377.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub21_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] - end - attribute \src "libresoc.v:93425.3-93473.6" - process $proc$libresoc.v:93425$3980 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:93426.5-93426.29" - switch \initial - attribute \src "libresoc.v:93426.9-93426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] - end - attribute \src "libresoc.v:93474.3-93522.6" - process $proc$libresoc.v:93474$3981 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:93475.5-93475.29" - switch \initial - attribute \src "libresoc.v:93475.9-93475.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] - end - attribute \src "libresoc.v:93523.3-93571.6" - process $proc$libresoc.v:93523$3982 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:93524.5-93524.29" - switch \initial - attribute \src "libresoc.v:93524.9-93524.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] - end - attribute \src "libresoc.v:93572.3-93620.6" - process $proc$libresoc.v:93572$3983 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] - attribute \src "libresoc.v:93573.5-93573.29" - switch \initial - attribute \src "libresoc.v:93573.9-93573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] - end - attribute \src "libresoc.v:93621.3-93669.6" - process $proc$libresoc.v:93621$3984 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:93622.5-93622.29" - switch \initial - attribute \src "libresoc.v:93622.9-93622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] - end - attribute \src "libresoc.v:93670.3-93718.6" - process $proc$libresoc.v:93670$3985 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:93671.5-93671.29" - switch \initial - attribute \src "libresoc.v:93671.9-93671.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:93724.1-95303.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" -attribute \generator "nMigen" -module \dec31_dec_sub22 - attribute \src "libresoc.v:94257.3-94311.6" - wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:94477.3-94531.6" - wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:95192.3-95246.6" - wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:95247.3-95301.6" - wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:94202.3-94256.6" - wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:94422.3-94476.6" - wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94917.3-94971.6" - wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:93982.3-94036.6" - wire width 12 $0\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:94972.3-95026.6" - wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:95027.3-95081.6" - wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:95082.3-95136.6" - wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:94587.3-94641.6" - wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:94312.3-94366.6" - wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:94367.3-94421.6" - wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:94697.3-94751.6" - wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:94037.3-94091.6" - wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:94807.3-94861.6" - wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:95137.3-95191.6" - wire width 2 $0\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:94147.3-94201.6" - wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:94642.3-94696.6" - wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:94862.3-94916.6" - wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:94752.3-94806.6" - wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:94532.3-94586.6" - wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:94092.3-94146.6" - wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:93725.7-93725.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:94257.3-94311.6" - wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:94477.3-94531.6" - wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:95192.3-95246.6" - wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:95247.3-95301.6" - wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:94202.3-94256.6" - wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:94422.3-94476.6" - wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94917.3-94971.6" - wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:93982.3-94036.6" - wire width 12 $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:94972.3-95026.6" - wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:95027.3-95081.6" - wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:95082.3-95136.6" - wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:94587.3-94641.6" - wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:94312.3-94366.6" - wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:94367.3-94421.6" - wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:94697.3-94751.6" - wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:94037.3-94091.6" - wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:94807.3-94861.6" - wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:95137.3-95191.6" - wire width 2 $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:94147.3-94201.6" - wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:94642.3-94696.6" - wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:94862.3-94916.6" - wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:94752.3-94806.6" - wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:94532.3-94586.6" - wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:94092.3-94146.6" - wire width 2 $1\dec31_dec_sub22_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub22_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub22_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub22_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub22_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub22_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub22_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub22_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub22_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub22_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub22_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub22_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub22_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub22_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub22_upd - attribute \src "libresoc.v:93725.7-93725.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:93725.7-93725.20" - process $proc$libresoc.v:93725$4011 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:93982.3-94036.6" - process $proc$libresoc.v:93982$3987 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] - attribute \src "libresoc.v:93983.5-93983.29" - switch \initial - attribute \src "libresoc.v:93983.9-93983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] - end - attribute \src "libresoc.v:94037.3-94091.6" - process $proc$libresoc.v:94037$3988 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:94038.5-94038.29" - switch \initial - attribute \src "libresoc.v:94038.9-94038.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] - end - attribute \src "libresoc.v:94092.3-94146.6" - process $proc$libresoc.v:94092$3989 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:94093.5-94093.29" - switch \initial - attribute \src "libresoc.v:94093.9-94093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub22_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] - end - attribute \src "libresoc.v:94147.3-94201.6" - process $proc$libresoc.v:94147$3990 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:94148.5-94148.29" - switch \initial - attribute \src "libresoc.v:94148.9-94148.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] - end - attribute \src "libresoc.v:94202.3-94256.6" - process $proc$libresoc.v:94202$3991 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:94203.5-94203.29" - switch \initial - attribute \src "libresoc.v:94203.9-94203.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] - end - attribute \src "libresoc.v:94257.3-94311.6" - process $proc$libresoc.v:94257$3992 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:94258.5-94258.29" - switch \initial - attribute \src "libresoc.v:94258.9-94258.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 - case - assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] - end - attribute \src "libresoc.v:94312.3-94366.6" - process $proc$libresoc.v:94312$3993 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:94313.5-94313.29" - switch \initial - attribute \src "libresoc.v:94313.9-94313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] - end - attribute \src "libresoc.v:94367.3-94421.6" - process $proc$libresoc.v:94367$3994 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:94368.5-94368.29" - switch \initial - attribute \src "libresoc.v:94368.9-94368.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] - end - attribute \src "libresoc.v:94422.3-94476.6" - process $proc$libresoc.v:94422$3995 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:94423.5-94423.29" - switch \initial - attribute \src "libresoc.v:94423.9-94423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] - end - attribute \src "libresoc.v:94477.3-94531.6" - process $proc$libresoc.v:94477$3996 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:94478.5-94478.29" - switch \initial - attribute \src "libresoc.v:94478.9-94478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_br[0:0] 1'0 - case - assign $1\dec31_dec_sub22_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] - end - attribute \src "libresoc.v:94532.3-94586.6" - process $proc$libresoc.v:94532$3997 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:94533.5-94533.29" - switch \initial - attribute \src "libresoc.v:94533.9-94533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] - end - attribute \src "libresoc.v:94587.3-94641.6" - process $proc$libresoc.v:94587$3998 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:94588.5-94588.29" - switch \initial - attribute \src "libresoc.v:94588.9-94588.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 - case - assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] - end - attribute \src "libresoc.v:94642.3-94696.6" - process $proc$libresoc.v:94642$3999 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:94643.5-94643.29" - switch \initial - attribute \src "libresoc.v:94643.9-94643.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] - end - attribute \src "libresoc.v:94697.3-94751.6" - process $proc$libresoc.v:94697$4000 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:94698.5-94698.29" - switch \initial - attribute \src "libresoc.v:94698.9-94698.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] - end - attribute \src "libresoc.v:94752.3-94806.6" - process $proc$libresoc.v:94752$4001 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:94753.5-94753.29" - switch \initial - attribute \src "libresoc.v:94753.9-94753.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub22_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] - end - attribute \src "libresoc.v:94807.3-94861.6" - process $proc$libresoc.v:94807$4002 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:94808.5-94808.29" - switch \initial - attribute \src "libresoc.v:94808.9-94808.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub22_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] - end - attribute \src "libresoc.v:94862.3-94916.6" - process $proc$libresoc.v:94862$4003 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:94863.5-94863.29" - switch \initial - attribute \src "libresoc.v:94863.9-94863.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] - end - attribute \src "libresoc.v:94917.3-94971.6" - process $proc$libresoc.v:94917$4004 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:94918.5-94918.29" - switch \initial - attribute \src "libresoc.v:94918.9-94918.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub22_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] - end - attribute \src "libresoc.v:94972.3-95026.6" - process $proc$libresoc.v:94972$4005 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:94973.5-94973.29" - switch \initial - attribute \src "libresoc.v:94973.9-94973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] - end - attribute \src "libresoc.v:95027.3-95081.6" - process $proc$libresoc.v:95027$4006 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:95028.5-95028.29" - switch \initial - attribute \src "libresoc.v:95028.9-95028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] - end - attribute \src "libresoc.v:95082.3-95136.6" - process $proc$libresoc.v:95082$4007 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:95083.5-95083.29" - switch \initial - attribute \src "libresoc.v:95083.9-95083.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] - end - attribute \src "libresoc.v:95137.3-95191.6" - process $proc$libresoc.v:95137$4008 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] - attribute \src "libresoc.v:95138.5-95138.29" - switch \initial - attribute \src "libresoc.v:95138.9-95138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] - end - attribute \src "libresoc.v:95192.3-95246.6" - process $proc$libresoc.v:95192$4009 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:95193.5-95193.29" - switch \initial - attribute \src "libresoc.v:95193.9-95193.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] - end - attribute \src "libresoc.v:95247.3-95301.6" - process $proc$libresoc.v:95247$4010 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:95248.5-95248.29" - switch \initial - attribute \src "libresoc.v:95248.9-95248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10101 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:95307.1-96742.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" -attribute \generator "nMigen" -module \dec31_dec_sub23 - attribute \src "libresoc.v:95810.3-95858.6" - wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:96006.3-96054.6" - wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:96643.3-96691.6" - wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:96692.3-96740.6" - wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:95761.3-95809.6" - wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95957.3-96005.6" - wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:96398.3-96446.6" - wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:95565.3-95613.6" - wire width 12 $0\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:96447.3-96495.6" - wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:96496.3-96544.6" - wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:96545.3-96593.6" - wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:96104.3-96152.6" - wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:95859.3-95907.6" - wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95908.3-95956.6" - wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:96202.3-96250.6" - wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:95614.3-95662.6" - wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:96300.3-96348.6" - wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:96594.3-96642.6" - wire width 2 $0\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:95712.3-95760.6" - wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:96153.3-96201.6" - wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:96349.3-96397.6" - wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:96251.3-96299.6" - wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:96055.3-96103.6" - wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:95663.3-95711.6" - wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:95308.7-95308.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:95810.3-95858.6" - wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:96006.3-96054.6" - wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:96643.3-96691.6" - wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:96692.3-96740.6" - wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:95761.3-95809.6" - wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95957.3-96005.6" - wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:96398.3-96446.6" - wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:95565.3-95613.6" - wire width 12 $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:96447.3-96495.6" - wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:96496.3-96544.6" - wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:96545.3-96593.6" - wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:96104.3-96152.6" - wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:95859.3-95907.6" - wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95908.3-95956.6" - wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:96202.3-96250.6" - wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:95614.3-95662.6" - wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:96300.3-96348.6" - wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:96594.3-96642.6" - wire width 2 $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:95712.3-95760.6" - wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:96153.3-96201.6" - wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:96349.3-96397.6" - wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:96251.3-96299.6" - wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:96055.3-96103.6" - wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:95663.3-95711.6" - wire width 2 $1\dec31_dec_sub23_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub23_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub23_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub23_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub23_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub23_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub23_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub23_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub23_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub23_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub23_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub23_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub23_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub23_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub23_upd - attribute \src "libresoc.v:95308.7-95308.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:95308.7-95308.20" - process $proc$libresoc.v:95308$4036 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:95565.3-95613.6" - process $proc$libresoc.v:95565$4012 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] - attribute \src "libresoc.v:95566.5-95566.29" - switch \initial - attribute \src "libresoc.v:95566.9-95566.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 - case - assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] - end - attribute \src "libresoc.v:95614.3-95662.6" - process $proc$libresoc.v:95614$4013 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:95615.5-95615.29" - switch \initial - attribute \src "libresoc.v:95615.9-95615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 - case - assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] - end - attribute \src "libresoc.v:95663.3-95711.6" - process $proc$libresoc.v:95663$4014 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:95664.5-95664.29" - switch \initial - attribute \src "libresoc.v:95664.9-95664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub23_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] - end - attribute \src "libresoc.v:95712.3-95760.6" - process $proc$libresoc.v:95712$4015 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:95713.5-95713.29" - switch \initial - attribute \src "libresoc.v:95713.9-95713.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] - end - attribute \src "libresoc.v:95761.3-95809.6" - process $proc$libresoc.v:95761$4016 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:95762.5-95762.29" - switch \initial - attribute \src "libresoc.v:95762.9-95762.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] - end - attribute \src "libresoc.v:95810.3-95858.6" - process $proc$libresoc.v:95810$4017 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:95811.5-95811.29" - switch \initial - attribute \src "libresoc.v:95811.9-95811.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 - case - assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] - end - attribute \src "libresoc.v:95859.3-95907.6" - process $proc$libresoc.v:95859$4018 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:95860.5-95860.29" - switch \initial - attribute \src "libresoc.v:95860.9-95860.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] - end - attribute \src "libresoc.v:95908.3-95956.6" - process $proc$libresoc.v:95908$4019 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:95909.5-95909.29" - switch \initial - attribute \src "libresoc.v:95909.9-95909.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] - end - attribute \src "libresoc.v:95957.3-96005.6" - process $proc$libresoc.v:95957$4020 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:95958.5-95958.29" - switch \initial - attribute \src "libresoc.v:95958.9-95958.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] - end - attribute \src "libresoc.v:96006.3-96054.6" - process $proc$libresoc.v:96006$4021 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:96007.5-96007.29" - switch \initial - attribute \src "libresoc.v:96007.9-96007.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_br[0:0] 1'0 - case - assign $1\dec31_dec_sub23_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] - end - attribute \src "libresoc.v:96055.3-96103.6" - process $proc$libresoc.v:96055$4022 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:96056.5-96056.29" - switch \initial - attribute \src "libresoc.v:96056.9-96056.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] - end - attribute \src "libresoc.v:96104.3-96152.6" - process $proc$libresoc.v:96104$4023 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:96105.5-96105.29" - switch \initial - attribute \src "libresoc.v:96105.9-96105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 - case - assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] - end - attribute \src "libresoc.v:96153.3-96201.6" - process $proc$libresoc.v:96153$4024 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:96154.5-96154.29" - switch \initial - attribute \src "libresoc.v:96154.9-96154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] - end - attribute \src "libresoc.v:96202.3-96250.6" - process $proc$libresoc.v:96202$4025 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:96203.5-96203.29" - switch \initial - attribute \src "libresoc.v:96203.9-96203.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] - end - attribute \src "libresoc.v:96251.3-96299.6" - process $proc$libresoc.v:96251$4026 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:96252.5-96252.29" - switch \initial - attribute \src "libresoc.v:96252.9-96252.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub23_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] - end - attribute \src "libresoc.v:96300.3-96348.6" - process $proc$libresoc.v:96300$4027 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:96301.5-96301.29" - switch \initial - attribute \src "libresoc.v:96301.9-96301.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub23_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] - end - attribute \src "libresoc.v:96349.3-96397.6" - process $proc$libresoc.v:96349$4028 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:96350.5-96350.29" - switch \initial - attribute \src "libresoc.v:96350.9-96350.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] - end - attribute \src "libresoc.v:96398.3-96446.6" - process $proc$libresoc.v:96398$4029 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:96399.5-96399.29" - switch \initial - attribute \src "libresoc.v:96399.9-96399.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub23_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] - end - attribute \src "libresoc.v:96447.3-96495.6" - process $proc$libresoc.v:96447$4030 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:96448.5-96448.29" - switch \initial - attribute \src "libresoc.v:96448.9-96448.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 - case - assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] - end - attribute \src "libresoc.v:96496.3-96544.6" - process $proc$libresoc.v:96496$4031 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:96497.5-96497.29" - switch \initial - attribute \src "libresoc.v:96497.9-96497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] - end - attribute \src "libresoc.v:96545.3-96593.6" - process $proc$libresoc.v:96545$4032 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:96546.5-96546.29" - switch \initial - attribute \src "libresoc.v:96546.9-96546.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] - end - attribute \src "libresoc.v:96594.3-96642.6" - process $proc$libresoc.v:96594$4033 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] - attribute \src "libresoc.v:96595.5-96595.29" - switch \initial - attribute \src "libresoc.v:96595.9-96595.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] - end - attribute \src "libresoc.v:96643.3-96691.6" - process $proc$libresoc.v:96643$4034 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:96644.5-96644.29" - switch \initial - attribute \src "libresoc.v:96644.9-96644.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] - end - attribute \src "libresoc.v:96692.3-96740.6" - process $proc$libresoc.v:96692$4035 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:96693.5-96693.29" - switch \initial - attribute \src "libresoc.v:96693.9-96693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01010 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:96746.1-97461.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" -attribute \generator "nMigen" -module \dec31_dec_sub24 - attribute \src "libresoc.v:97099.3-97117.6" - wire width 8 $0\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:97175.3-97193.6" - wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:97422.3-97440.6" - wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:97441.3-97459.6" - wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:97080.3-97098.6" - wire width 2 $0\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:97156.3-97174.6" - wire $0\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:97327.3-97345.6" - wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:97004.3-97022.6" - wire width 12 $0\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:97346.3-97364.6" - wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:97365.3-97383.6" - wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:97384.3-97402.6" - wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:97213.3-97231.6" - wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:97118.3-97136.6" - wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:97137.3-97155.6" - wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:97251.3-97269.6" - wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:97023.3-97041.6" - wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:97289.3-97307.6" - wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:97403.3-97421.6" - wire width 2 $0\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:97061.3-97079.6" - wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:97232.3-97250.6" - wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:97308.3-97326.6" - wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:97270.3-97288.6" - wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:97194.3-97212.6" - wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:97042.3-97060.6" - wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:96747.7-96747.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:97099.3-97117.6" - wire width 8 $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:97175.3-97193.6" - wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:97422.3-97440.6" - wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:97441.3-97459.6" - wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:97080.3-97098.6" - wire width 2 $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:97156.3-97174.6" - wire $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:97327.3-97345.6" - wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:97004.3-97022.6" - wire width 12 $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:97346.3-97364.6" - wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:97365.3-97383.6" - wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:97384.3-97402.6" - wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:97213.3-97231.6" - wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:97118.3-97136.6" - wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:97137.3-97155.6" - wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:97251.3-97269.6" - wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:97023.3-97041.6" - wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:97289.3-97307.6" - wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:97403.3-97421.6" - wire width 2 $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:97061.3-97079.6" - wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:97232.3-97250.6" - wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:97308.3-97326.6" - wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:97270.3-97288.6" - wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:97194.3-97212.6" - wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:97042.3-97060.6" - wire width 2 $1\dec31_dec_sub24_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub24_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub24_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub24_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub24_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub24_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub24_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub24_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub24_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub24_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub24_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub24_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub24_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub24_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub24_upd - attribute \src "libresoc.v:96747.7-96747.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:96747.7-96747.20" - process $proc$libresoc.v:96747$4061 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:97004.3-97022.6" - process $proc$libresoc.v:97004$4037 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] - attribute \src "libresoc.v:97005.5-97005.29" - switch \initial - attribute \src "libresoc.v:97005.9-97005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] - end - attribute \src "libresoc.v:97023.3-97041.6" - process $proc$libresoc.v:97023$4038 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:97024.5-97024.29" - switch \initial - attribute \src "libresoc.v:97024.9-97024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] - end - attribute \src "libresoc.v:97042.3-97060.6" - process $proc$libresoc.v:97042$4039 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:97043.5-97043.29" - switch \initial - attribute \src "libresoc.v:97043.9-97043.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub24_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] - end - attribute \src "libresoc.v:97061.3-97079.6" - process $proc$libresoc.v:97061$4040 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:97062.5-97062.29" - switch \initial - attribute \src "libresoc.v:97062.9-97062.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] - end - attribute \src "libresoc.v:97080.3-97098.6" - process $proc$libresoc.v:97080$4041 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:97081.5-97081.29" - switch \initial - attribute \src "libresoc.v:97081.9-97081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] - end - attribute \src "libresoc.v:97099.3-97117.6" - process $proc$libresoc.v:97099$4042 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:97100.5-97100.29" - switch \initial - attribute \src "libresoc.v:97100.9-97100.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 - case - assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] - end - attribute \src "libresoc.v:97118.3-97136.6" - process $proc$libresoc.v:97118$4043 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:97119.5-97119.29" - switch \initial - attribute \src "libresoc.v:97119.9-97119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] - end - attribute \src "libresoc.v:97137.3-97155.6" - process $proc$libresoc.v:97137$4044 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:97138.5-97138.29" - switch \initial - attribute \src "libresoc.v:97138.9-97138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] - end - attribute \src "libresoc.v:97156.3-97174.6" - process $proc$libresoc.v:97156$4045 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:97157.5-97157.29" - switch \initial - attribute \src "libresoc.v:97157.9-97157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] - end - attribute \src "libresoc.v:97175.3-97193.6" - process $proc$libresoc.v:97175$4046 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:97176.5-97176.29" - switch \initial - attribute \src "libresoc.v:97176.9-97176.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_br[0:0] 1'0 - case - assign $1\dec31_dec_sub24_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] - end - attribute \src "libresoc.v:97194.3-97212.6" - process $proc$libresoc.v:97194$4047 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:97195.5-97195.29" - switch \initial - attribute \src "libresoc.v:97195.9-97195.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] - end - attribute \src "libresoc.v:97213.3-97231.6" - process $proc$libresoc.v:97213$4048 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:97214.5-97214.29" - switch \initial - attribute \src "libresoc.v:97214.9-97214.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] - end - attribute \src "libresoc.v:97232.3-97250.6" - process $proc$libresoc.v:97232$4049 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:97233.5-97233.29" - switch \initial - attribute \src "libresoc.v:97233.9-97233.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] - end - attribute \src "libresoc.v:97251.3-97269.6" - process $proc$libresoc.v:97251$4050 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:97252.5-97252.29" - switch \initial - attribute \src "libresoc.v:97252.9-97252.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] - end - attribute \src "libresoc.v:97270.3-97288.6" - process $proc$libresoc.v:97270$4051 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:97271.5-97271.29" - switch \initial - attribute \src "libresoc.v:97271.9-97271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] - end - attribute \src "libresoc.v:97289.3-97307.6" - process $proc$libresoc.v:97289$4052 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:97290.5-97290.29" - switch \initial - attribute \src "libresoc.v:97290.9-97290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub24_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] - end - attribute \src "libresoc.v:97308.3-97326.6" - process $proc$libresoc.v:97308$4053 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:97309.5-97309.29" - switch \initial - attribute \src "libresoc.v:97309.9-97309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] - end - attribute \src "libresoc.v:97327.3-97345.6" - process $proc$libresoc.v:97327$4054 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:97328.5-97328.29" - switch \initial - attribute \src "libresoc.v:97328.9-97328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub24_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] - end - attribute \src "libresoc.v:97346.3-97364.6" - process $proc$libresoc.v:97346$4055 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:97347.5-97347.29" - switch \initial - attribute \src "libresoc.v:97347.9-97347.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] - end - attribute \src "libresoc.v:97365.3-97383.6" - process $proc$libresoc.v:97365$4056 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:97366.5-97366.29" - switch \initial - attribute \src "libresoc.v:97366.9-97366.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] - end - attribute \src "libresoc.v:97384.3-97402.6" - process $proc$libresoc.v:97384$4057 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:97385.5-97385.29" - switch \initial - attribute \src "libresoc.v:97385.9-97385.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] - end - attribute \src "libresoc.v:97403.3-97421.6" - process $proc$libresoc.v:97403$4058 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] - attribute \src "libresoc.v:97404.5-97404.29" - switch \initial - attribute \src "libresoc.v:97404.9-97404.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] - end - attribute \src "libresoc.v:97422.3-97440.6" - process $proc$libresoc.v:97422$4059 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:97423.5-97423.29" - switch \initial - attribute \src "libresoc.v:97423.9-97423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] - end - attribute \src "libresoc.v:97441.3-97459.6" - process $proc$libresoc.v:97441$4060 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:97442.5-97442.29" - switch \initial - attribute \src "libresoc.v:97442.9-97442.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:97465.1-98972.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" -attribute \generator "nMigen" -module \dec31_dec_sub26 - attribute \src "libresoc.v:97983.3-98034.6" - wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:98191.3-98242.6" - wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:98867.3-98918.6" - wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98919.3-98970.6" - wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:97931.3-97982.6" - wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:98139.3-98190.6" - wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:98607.3-98658.6" - wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:97723.3-97774.6" - wire width 12 $0\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:98659.3-98710.6" - wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:98711.3-98762.6" - wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:98763.3-98814.6" - wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:98295.3-98346.6" - wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:98035.3-98086.6" - wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:98087.3-98138.6" - wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:98399.3-98450.6" - wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:97775.3-97826.6" - wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:98503.3-98554.6" - wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:98815.3-98866.6" - wire width 2 $0\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:97879.3-97930.6" - wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:98347.3-98398.6" - wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:98555.3-98606.6" - wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:98451.3-98502.6" - wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:98243.3-98294.6" - wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:97827.3-97878.6" - wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:97466.7-97466.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:97983.3-98034.6" - wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:98191.3-98242.6" - wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:98867.3-98918.6" - wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98919.3-98970.6" - wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:97931.3-97982.6" - wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:98139.3-98190.6" - wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:98607.3-98658.6" - wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:97723.3-97774.6" - wire width 12 $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:98659.3-98710.6" - wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:98711.3-98762.6" - wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:98763.3-98814.6" - wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:98295.3-98346.6" - wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:98035.3-98086.6" - wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:98087.3-98138.6" - wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:98399.3-98450.6" - wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:97775.3-97826.6" - wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:98503.3-98554.6" - wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:98815.3-98866.6" - wire width 2 $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:97879.3-97930.6" - wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:98347.3-98398.6" - wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:98555.3-98606.6" - wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:98451.3-98502.6" - wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:98243.3-98294.6" - wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:97827.3-97878.6" - wire width 2 $1\dec31_dec_sub26_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub26_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub26_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub26_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub26_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub26_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub26_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub26_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub26_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub26_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub26_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub26_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub26_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub26_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub26_upd - attribute \src "libresoc.v:97466.7-97466.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:97466.7-97466.20" - process $proc$libresoc.v:97466$4086 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:97723.3-97774.6" - process $proc$libresoc.v:97723$4062 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] - attribute \src "libresoc.v:97724.5-97724.29" - switch \initial - attribute \src "libresoc.v:97724.9-97724.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] - end - attribute \src "libresoc.v:97775.3-97826.6" - process $proc$libresoc.v:97775$4063 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:97776.5-97776.29" - switch \initial - attribute \src "libresoc.v:97776.9-97776.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] - end - attribute \src "libresoc.v:97827.3-97878.6" - process $proc$libresoc.v:97827$4064 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:97828.5-97828.29" - switch \initial - attribute \src "libresoc.v:97828.9-97828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub26_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] - end - attribute \src "libresoc.v:97879.3-97930.6" - process $proc$libresoc.v:97879$4065 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:97880.5-97880.29" - switch \initial - attribute \src "libresoc.v:97880.9-97880.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] - end - attribute \src "libresoc.v:97931.3-97982.6" - process $proc$libresoc.v:97931$4066 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:97932.5-97932.29" - switch \initial - attribute \src "libresoc.v:97932.9-97932.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] - end - attribute \src "libresoc.v:97983.3-98034.6" - process $proc$libresoc.v:97983$4067 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:97984.5-97984.29" - switch \initial - attribute \src "libresoc.v:97984.9-97984.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 - case - assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] - end - attribute \src "libresoc.v:98035.3-98086.6" - process $proc$libresoc.v:98035$4068 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:98036.5-98036.29" - switch \initial - attribute \src "libresoc.v:98036.9-98036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] - end - attribute \src "libresoc.v:98087.3-98138.6" - process $proc$libresoc.v:98087$4069 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:98088.5-98088.29" - switch \initial - attribute \src "libresoc.v:98088.9-98088.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] - end - attribute \src "libresoc.v:98139.3-98190.6" - process $proc$libresoc.v:98139$4070 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:98140.5-98140.29" - switch \initial - attribute \src "libresoc.v:98140.9-98140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] - end - attribute \src "libresoc.v:98191.3-98242.6" - process $proc$libresoc.v:98191$4071 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:98192.5-98192.29" - switch \initial - attribute \src "libresoc.v:98192.9-98192.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_br[0:0] 1'0 - case - assign $1\dec31_dec_sub26_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] - end - attribute \src "libresoc.v:98243.3-98294.6" - process $proc$libresoc.v:98243$4072 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:98244.5-98244.29" - switch \initial - attribute \src "libresoc.v:98244.9-98244.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] - end - attribute \src "libresoc.v:98295.3-98346.6" - process $proc$libresoc.v:98295$4073 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:98296.5-98296.29" - switch \initial - attribute \src "libresoc.v:98296.9-98296.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] - end - attribute \src "libresoc.v:98347.3-98398.6" - process $proc$libresoc.v:98347$4074 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:98348.5-98348.29" - switch \initial - attribute \src "libresoc.v:98348.9-98348.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] - end - attribute \src "libresoc.v:98399.3-98450.6" - process $proc$libresoc.v:98399$4075 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:98400.5-98400.29" - switch \initial - attribute \src "libresoc.v:98400.9-98400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] - end - attribute \src "libresoc.v:98451.3-98502.6" - process $proc$libresoc.v:98451$4076 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:98452.5-98452.29" - switch \initial - attribute \src "libresoc.v:98452.9-98452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub26_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] - end - attribute \src "libresoc.v:98503.3-98554.6" - process $proc$libresoc.v:98503$4077 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:98504.5-98504.29" - switch \initial - attribute \src "libresoc.v:98504.9-98504.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub26_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] - end - attribute \src "libresoc.v:98555.3-98606.6" - process $proc$libresoc.v:98555$4078 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:98556.5-98556.29" - switch \initial - attribute \src "libresoc.v:98556.9-98556.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] - end - attribute \src "libresoc.v:98607.3-98658.6" - process $proc$libresoc.v:98607$4079 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:98608.5-98608.29" - switch \initial - attribute \src "libresoc.v:98608.9-98608.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_form[4:0] 5'10000 - case - assign $1\dec31_dec_sub26_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] - end - attribute \src "libresoc.v:98659.3-98710.6" - process $proc$libresoc.v:98659$4080 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:98660.5-98660.29" - switch \initial - attribute \src "libresoc.v:98660.9-98660.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] - end - attribute \src "libresoc.v:98711.3-98762.6" - process $proc$libresoc.v:98711$4081 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:98712.5-98712.29" - switch \initial - attribute \src "libresoc.v:98712.9-98712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 - case - assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] - end - attribute \src "libresoc.v:98763.3-98814.6" - process $proc$libresoc.v:98763$4082 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:98764.5-98764.29" - switch \initial - attribute \src "libresoc.v:98764.9-98764.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] - end - attribute \src "libresoc.v:98815.3-98866.6" - process $proc$libresoc.v:98815$4083 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] - attribute \src "libresoc.v:98816.5-98816.29" - switch \initial - attribute \src "libresoc.v:98816.9-98816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] - end - attribute \src "libresoc.v:98867.3-98918.6" - process $proc$libresoc.v:98867$4084 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:98868.5-98868.29" - switch \initial - attribute \src "libresoc.v:98868.9-98868.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] - end - attribute \src "libresoc.v:98919.3-98970.6" - process $proc$libresoc.v:98919$4085 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:98920.5-98920.29" - switch \initial - attribute \src "libresoc.v:98920.9-98920.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01011 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:98976.1-99691.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" -attribute \generator "nMigen" -module \dec31_dec_sub27 - attribute \src "libresoc.v:99329.3-99347.6" - wire width 8 $0\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:99405.3-99423.6" - wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:99652.3-99670.6" - wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:99671.3-99689.6" - wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:99310.3-99328.6" - wire width 2 $0\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:99386.3-99404.6" - wire $0\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:99557.3-99575.6" - wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:99234.3-99252.6" - wire width 12 $0\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:99576.3-99594.6" - wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:99595.3-99613.6" - wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:99614.3-99632.6" - wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:99443.3-99461.6" - wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:99348.3-99366.6" - wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:99367.3-99385.6" - wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:99481.3-99499.6" - wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:99253.3-99271.6" - wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:99519.3-99537.6" - wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:99633.3-99651.6" - wire width 2 $0\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:99291.3-99309.6" - wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:99462.3-99480.6" - wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:99538.3-99556.6" - wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:99500.3-99518.6" - wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:99424.3-99442.6" - wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:99272.3-99290.6" - wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:98977.7-98977.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:99329.3-99347.6" - wire width 8 $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:99405.3-99423.6" - wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:99652.3-99670.6" - wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:99671.3-99689.6" - wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:99310.3-99328.6" - wire width 2 $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:99386.3-99404.6" - wire $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:99557.3-99575.6" - wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:99234.3-99252.6" - wire width 12 $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:99576.3-99594.6" - wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:99595.3-99613.6" - wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:99614.3-99632.6" - wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:99443.3-99461.6" - wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:99348.3-99366.6" - wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:99367.3-99385.6" - wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:99481.3-99499.6" - wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:99253.3-99271.6" - wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:99519.3-99537.6" - wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:99633.3-99651.6" - wire width 2 $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:99291.3-99309.6" - wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:99462.3-99480.6" - wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:99538.3-99556.6" - wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:99500.3-99518.6" - wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:99424.3-99442.6" - wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:99272.3-99290.6" - wire width 2 $1\dec31_dec_sub27_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub27_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub27_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub27_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub27_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub27_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub27_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub27_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub27_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub27_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub27_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub27_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub27_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub27_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub27_upd - attribute \src "libresoc.v:98977.7-98977.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:98977.7-98977.20" - process $proc$libresoc.v:98977$4111 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:99234.3-99252.6" - process $proc$libresoc.v:99234$4087 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] - attribute \src "libresoc.v:99235.5-99235.29" - switch \initial - attribute \src "libresoc.v:99235.9-99235.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 - case - assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] - end - attribute \src "libresoc.v:99253.3-99271.6" - process $proc$libresoc.v:99253$4088 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:99254.5-99254.29" - switch \initial - attribute \src "libresoc.v:99254.9-99254.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] - end - attribute \src "libresoc.v:99272.3-99290.6" - process $proc$libresoc.v:99272$4089 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:99273.5-99273.29" - switch \initial - attribute \src "libresoc.v:99273.9-99273.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub27_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] - end - attribute \src "libresoc.v:99291.3-99309.6" - process $proc$libresoc.v:99291$4090 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:99292.5-99292.29" - switch \initial - attribute \src "libresoc.v:99292.9-99292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] - end - attribute \src "libresoc.v:99310.3-99328.6" - process $proc$libresoc.v:99310$4091 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:99311.5-99311.29" - switch \initial - attribute \src "libresoc.v:99311.9-99311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] - end - attribute \src "libresoc.v:99329.3-99347.6" - process $proc$libresoc.v:99329$4092 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:99330.5-99330.29" - switch \initial - attribute \src "libresoc.v:99330.9-99330.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 - case - assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] - end - attribute \src "libresoc.v:99348.3-99366.6" - process $proc$libresoc.v:99348$4093 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:99349.5-99349.29" - switch \initial - attribute \src "libresoc.v:99349.9-99349.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] - end - attribute \src "libresoc.v:99367.3-99385.6" - process $proc$libresoc.v:99367$4094 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:99368.5-99368.29" - switch \initial - attribute \src "libresoc.v:99368.9-99368.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] - end - attribute \src "libresoc.v:99386.3-99404.6" - process $proc$libresoc.v:99386$4095 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:99387.5-99387.29" - switch \initial - attribute \src "libresoc.v:99387.9-99387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] - end - attribute \src "libresoc.v:99405.3-99423.6" - process $proc$libresoc.v:99405$4096 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:99406.5-99406.29" - switch \initial - attribute \src "libresoc.v:99406.9-99406.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_br[0:0] 1'0 - case - assign $1\dec31_dec_sub27_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] - end - attribute \src "libresoc.v:99424.3-99442.6" - process $proc$libresoc.v:99424$4097 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:99425.5-99425.29" - switch \initial - attribute \src "libresoc.v:99425.9-99425.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] - end - attribute \src "libresoc.v:99443.3-99461.6" - process $proc$libresoc.v:99443$4098 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:99444.5-99444.29" - switch \initial - attribute \src "libresoc.v:99444.9-99444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 - case - assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] - end - attribute \src "libresoc.v:99462.3-99480.6" - process $proc$libresoc.v:99462$4099 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:99463.5-99463.29" - switch \initial - attribute \src "libresoc.v:99463.9-99463.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] - end - attribute \src "libresoc.v:99481.3-99499.6" - process $proc$libresoc.v:99481$4100 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:99482.5-99482.29" - switch \initial - attribute \src "libresoc.v:99482.9-99482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] - end - attribute \src "libresoc.v:99500.3-99518.6" - process $proc$libresoc.v:99500$4101 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:99501.5-99501.29" - switch \initial - attribute \src "libresoc.v:99501.9-99501.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] - end - attribute \src "libresoc.v:99519.3-99537.6" - process $proc$libresoc.v:99519$4102 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:99520.5-99520.29" - switch \initial - attribute \src "libresoc.v:99520.9-99520.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub27_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] - end - attribute \src "libresoc.v:99538.3-99556.6" - process $proc$libresoc.v:99538$4103 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:99539.5-99539.29" - switch \initial - attribute \src "libresoc.v:99539.9-99539.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] - end - attribute \src "libresoc.v:99557.3-99575.6" - process $proc$libresoc.v:99557$4104 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:99558.5-99558.29" - switch \initial - attribute \src "libresoc.v:99558.9-99558.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'10000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub27_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] - end - attribute \src "libresoc.v:99576.3-99594.6" - process $proc$libresoc.v:99576$4105 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:99577.5-99577.29" - switch \initial - attribute \src "libresoc.v:99577.9-99577.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - case - assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] - end - attribute \src "libresoc.v:99595.3-99613.6" - process $proc$libresoc.v:99595$4106 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:99596.5-99596.29" - switch \initial - attribute \src "libresoc.v:99596.9-99596.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] - end - attribute \src "libresoc.v:99614.3-99632.6" - process $proc$libresoc.v:99614$4107 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:99615.5-99615.29" - switch \initial - attribute \src "libresoc.v:99615.9-99615.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] - end - attribute \src "libresoc.v:99633.3-99651.6" - process $proc$libresoc.v:99633$4108 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] - attribute \src "libresoc.v:99634.5-99634.29" - switch \initial - attribute \src "libresoc.v:99634.9-99634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] - end - attribute \src "libresoc.v:99652.3-99670.6" - process $proc$libresoc.v:99652$4109 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:99653.5-99653.29" - switch \initial - attribute \src "libresoc.v:99653.9-99653.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] - end - attribute \src "libresoc.v:99671.3-99689.6" - process $proc$libresoc.v:99671$4110 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:99672.5-99672.29" - switch \initial - attribute \src "libresoc.v:99672.9-99672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'11011 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11001 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:99695.1-100842.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" -attribute \generator "nMigen" -module \dec31_dec_sub28 - attribute \src "libresoc.v:100138.3-100174.6" - wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:100286.3-100322.6" - wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:100767.3-100803.6" - wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:100804.3-100840.6" - wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:100101.3-100137.6" - wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:100249.3-100285.6" - wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:100582.3-100618.6" - wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:99953.3-99989.6" - wire width 12 $0\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:100619.3-100655.6" - wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:100656.3-100692.6" - wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:100693.3-100729.6" - wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:100360.3-100396.6" - wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:100175.3-100211.6" - wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:100212.3-100248.6" - wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:100434.3-100470.6" - wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:99990.3-100026.6" - wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:100508.3-100544.6" - wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:100730.3-100766.6" - wire width 2 $0\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:100064.3-100100.6" - wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:100397.3-100433.6" - wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:100545.3-100581.6" - wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:100471.3-100507.6" - wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:100323.3-100359.6" - wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:100027.3-100063.6" - wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:99696.7-99696.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:100138.3-100174.6" - wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:100286.3-100322.6" - wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:100767.3-100803.6" - wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:100804.3-100840.6" - wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:100101.3-100137.6" - wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:100249.3-100285.6" - wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:100582.3-100618.6" - wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:99953.3-99989.6" - wire width 12 $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:100619.3-100655.6" - wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:100656.3-100692.6" - wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:100693.3-100729.6" - wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:100360.3-100396.6" - wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:100175.3-100211.6" - wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:100212.3-100248.6" - wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:100434.3-100470.6" - wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:99990.3-100026.6" - wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:100508.3-100544.6" - wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:100730.3-100766.6" - wire width 2 $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:100064.3-100100.6" - wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:100397.3-100433.6" - wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:100545.3-100581.6" - wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:100471.3-100507.6" - wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:100323.3-100359.6" - wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:100027.3-100063.6" - wire width 2 $1\dec31_dec_sub28_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub28_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub28_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub28_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub28_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub28_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub28_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub28_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub28_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub28_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub28_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub28_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub28_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub28_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub28_upd - attribute \src "libresoc.v:99696.7-99696.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:100027.3-100063.6" - process $proc$libresoc.v:100027$4114 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:100028.5-100028.29" - switch \initial - attribute \src "libresoc.v:100028.9-100028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub28_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] - end - attribute \src "libresoc.v:100064.3-100100.6" - process $proc$libresoc.v:100064$4115 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:100065.5-100065.29" - switch \initial - attribute \src "libresoc.v:100065.9-100065.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] - end - attribute \src "libresoc.v:100101.3-100137.6" - process $proc$libresoc.v:100101$4116 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:100102.5-100102.29" - switch \initial - attribute \src "libresoc.v:100102.9-100102.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] - end - attribute \src "libresoc.v:100138.3-100174.6" - process $proc$libresoc.v:100138$4117 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:100139.5-100139.29" - switch \initial - attribute \src "libresoc.v:100139.9-100139.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 - case - assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] - end - attribute \src "libresoc.v:100175.3-100211.6" - process $proc$libresoc.v:100175$4118 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:100176.5-100176.29" - switch \initial - attribute \src "libresoc.v:100176.9-100176.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] - end - attribute \src "libresoc.v:100212.3-100248.6" - process $proc$libresoc.v:100212$4119 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:100213.5-100213.29" - switch \initial - attribute \src "libresoc.v:100213.9-100213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] - end - attribute \src "libresoc.v:100249.3-100285.6" - process $proc$libresoc.v:100249$4120 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:100250.5-100250.29" - switch \initial - attribute \src "libresoc.v:100250.9-100250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] - end - attribute \src "libresoc.v:100286.3-100322.6" - process $proc$libresoc.v:100286$4121 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:100287.5-100287.29" - switch \initial - attribute \src "libresoc.v:100287.9-100287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_br[0:0] 1'0 - case - assign $1\dec31_dec_sub28_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] - end - attribute \src "libresoc.v:100323.3-100359.6" - process $proc$libresoc.v:100323$4122 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:100324.5-100324.29" - switch \initial - attribute \src "libresoc.v:100324.9-100324.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] - end - attribute \src "libresoc.v:100360.3-100396.6" - process $proc$libresoc.v:100360$4123 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:100361.5-100361.29" - switch \initial - attribute \src "libresoc.v:100361.9-100361.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 - case - assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] - end - attribute \src "libresoc.v:100397.3-100433.6" - process $proc$libresoc.v:100397$4124 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:100398.5-100398.29" - switch \initial - attribute \src "libresoc.v:100398.9-100398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] - end - attribute \src "libresoc.v:100434.3-100470.6" - process $proc$libresoc.v:100434$4125 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:100435.5-100435.29" - switch \initial - attribute \src "libresoc.v:100435.9-100435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] - end - attribute \src "libresoc.v:100471.3-100507.6" - process $proc$libresoc.v:100471$4126 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:100472.5-100472.29" - switch \initial - attribute \src "libresoc.v:100472.9-100472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] - end - attribute \src "libresoc.v:100508.3-100544.6" - process $proc$libresoc.v:100508$4127 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:100509.5-100509.29" - switch \initial - attribute \src "libresoc.v:100509.9-100509.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub28_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] - end - attribute \src "libresoc.v:100545.3-100581.6" - process $proc$libresoc.v:100545$4128 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:100546.5-100546.29" - switch \initial - attribute \src "libresoc.v:100546.9-100546.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] - end - attribute \src "libresoc.v:100582.3-100618.6" - process $proc$libresoc.v:100582$4129 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:100583.5-100583.29" - switch \initial - attribute \src "libresoc.v:100583.9-100583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub28_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] - end - attribute \src "libresoc.v:100619.3-100655.6" - process $proc$libresoc.v:100619$4130 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:100620.5-100620.29" - switch \initial - attribute \src "libresoc.v:100620.9-100620.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 - case - assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] - end - attribute \src "libresoc.v:100656.3-100692.6" - process $proc$libresoc.v:100656$4131 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:100657.5-100657.29" - switch \initial - attribute \src "libresoc.v:100657.9-100657.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] - end - attribute \src "libresoc.v:100693.3-100729.6" - process $proc$libresoc.v:100693$4132 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:100694.5-100694.29" - switch \initial - attribute \src "libresoc.v:100694.9-100694.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] - end - attribute \src "libresoc.v:100730.3-100766.6" - process $proc$libresoc.v:100730$4133 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] - attribute \src "libresoc.v:100731.5-100731.29" - switch \initial - attribute \src "libresoc.v:100731.9-100731.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] - end - attribute \src "libresoc.v:100767.3-100803.6" - process $proc$libresoc.v:100767$4134 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:100768.5-100768.29" - switch \initial - attribute \src "libresoc.v:100768.9-100768.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] - end - attribute \src "libresoc.v:100804.3-100840.6" - process $proc$libresoc.v:100804$4135 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:100805.5-100805.29" - switch \initial - attribute \src "libresoc.v:100805.9-100805.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] - end - attribute \src "libresoc.v:99696.7-99696.20" - process $proc$libresoc.v:99696$4136 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:99953.3-99989.6" - process $proc$libresoc.v:99953$4112 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] - attribute \src "libresoc.v:99954.5-99954.29" - switch \initial - attribute \src "libresoc.v:99954.9-99954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 - case - assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] - end - attribute \src "libresoc.v:99990.3-100026.6" - process $proc$libresoc.v:99990$4113 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:99991.5-99991.29" - switch \initial - attribute \src "libresoc.v:99991.9-99991.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:100846.1-101417.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" -attribute \generator "nMigen" -module \dec31_dec_sub4 - attribute \src "libresoc.v:101169.3-101181.6" - wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:101221.3-101233.6" - wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:101390.3-101402.6" - wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:101403.3-101415.6" - wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:101156.3-101168.6" - wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:101208.3-101220.6" - wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:101325.3-101337.6" - wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:101104.3-101116.6" - wire width 12 $0\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:101338.3-101350.6" - wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:101351.3-101363.6" - wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:101364.3-101376.6" - wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:101247.3-101259.6" - wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:101182.3-101194.6" - wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:101195.3-101207.6" - wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:101273.3-101285.6" - wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:101117.3-101129.6" - wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:101299.3-101311.6" - wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:101377.3-101389.6" - wire width 2 $0\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:101143.3-101155.6" - wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:101260.3-101272.6" - wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:101312.3-101324.6" - wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:101286.3-101298.6" - wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:101234.3-101246.6" - wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:101130.3-101142.6" - wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:100847.7-100847.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:101169.3-101181.6" - wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:101221.3-101233.6" - wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:101390.3-101402.6" - wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:101403.3-101415.6" - wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:101156.3-101168.6" - wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:101208.3-101220.6" - wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:101325.3-101337.6" - wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:101104.3-101116.6" - wire width 12 $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:101338.3-101350.6" - wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:101351.3-101363.6" - wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:101364.3-101376.6" - wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:101247.3-101259.6" - wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:101182.3-101194.6" - wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:101195.3-101207.6" - wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:101273.3-101285.6" - wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:101117.3-101129.6" - wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:101299.3-101311.6" - wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:101377.3-101389.6" - wire width 2 $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:101143.3-101155.6" - wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:101260.3-101272.6" - wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:101312.3-101324.6" - wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:101286.3-101298.6" - wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:101234.3-101246.6" - wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:101130.3-101142.6" - wire width 2 $1\dec31_dec_sub4_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub4_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub4_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub4_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub4_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub4_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub4_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub4_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub4_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub4_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub4_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub4_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub4_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub4_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub4_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub4_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub4_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub4_upd - attribute \src "libresoc.v:100847.7-100847.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:100847.7-100847.20" - process $proc$libresoc.v:100847$4161 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:101104.3-101116.6" - process $proc$libresoc.v:101104$4137 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] - attribute \src "libresoc.v:101105.5-101105.29" - switch \initial - attribute \src "libresoc.v:101105.9-101105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 - case - assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] - end - attribute \src "libresoc.v:101117.3-101129.6" - process $proc$libresoc.v:101117$4138 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:101118.5-101118.29" - switch \initial - attribute \src "libresoc.v:101118.9-101118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] - end - attribute \src "libresoc.v:101130.3-101142.6" - process $proc$libresoc.v:101130$4139 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:101131.5-101131.29" - switch \initial - attribute \src "libresoc.v:101131.9-101131.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub4_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] - end - attribute \src "libresoc.v:101143.3-101155.6" - process $proc$libresoc.v:101143$4140 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:101144.5-101144.29" - switch \initial - attribute \src "libresoc.v:101144.9-101144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] - end - attribute \src "libresoc.v:101156.3-101168.6" - process $proc$libresoc.v:101156$4141 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:101157.5-101157.29" - switch \initial - attribute \src "libresoc.v:101157.9-101157.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] - end - attribute \src "libresoc.v:101169.3-101181.6" - process $proc$libresoc.v:101169$4142 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:101170.5-101170.29" - switch \initial - attribute \src "libresoc.v:101170.9-101170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 - case - assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] - end - attribute \src "libresoc.v:101182.3-101194.6" - process $proc$libresoc.v:101182$4143 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:101183.5-101183.29" - switch \initial - attribute \src "libresoc.v:101183.9-101183.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] - end - attribute \src "libresoc.v:101195.3-101207.6" - process $proc$libresoc.v:101195$4144 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:101196.5-101196.29" - switch \initial - attribute \src "libresoc.v:101196.9-101196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] - end - attribute \src "libresoc.v:101208.3-101220.6" - process $proc$libresoc.v:101208$4145 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:101209.5-101209.29" - switch \initial - attribute \src "libresoc.v:101209.9-101209.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] - end - attribute \src "libresoc.v:101221.3-101233.6" - process $proc$libresoc.v:101221$4146 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:101222.5-101222.29" - switch \initial - attribute \src "libresoc.v:101222.9-101222.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_br[0:0] 1'0 - case - assign $1\dec31_dec_sub4_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] - end - attribute \src "libresoc.v:101234.3-101246.6" - process $proc$libresoc.v:101234$4147 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:101235.5-101235.29" - switch \initial - attribute \src "libresoc.v:101235.9-101235.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] - end - attribute \src "libresoc.v:101247.3-101259.6" - process $proc$libresoc.v:101247$4148 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:101248.5-101248.29" - switch \initial - attribute \src "libresoc.v:101248.9-101248.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 - case - assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] - end - attribute \src "libresoc.v:101260.3-101272.6" - process $proc$libresoc.v:101260$4149 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:101261.5-101261.29" - switch \initial - attribute \src "libresoc.v:101261.9-101261.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] - end - attribute \src "libresoc.v:101273.3-101285.6" - process $proc$libresoc.v:101273$4150 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:101274.5-101274.29" - switch \initial - attribute \src "libresoc.v:101274.9-101274.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 - case - assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] - end - attribute \src "libresoc.v:101286.3-101298.6" - process $proc$libresoc.v:101286$4151 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:101287.5-101287.29" - switch \initial - attribute \src "libresoc.v:101287.9-101287.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub4_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] - end - attribute \src "libresoc.v:101299.3-101311.6" - process $proc$libresoc.v:101299$4152 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:101300.5-101300.29" - switch \initial - attribute \src "libresoc.v:101300.9-101300.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub4_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] - end - attribute \src "libresoc.v:101312.3-101324.6" - process $proc$libresoc.v:101312$4153 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:101313.5-101313.29" - switch \initial - attribute \src "libresoc.v:101313.9-101313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 - case - assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] - end - attribute \src "libresoc.v:101325.3-101337.6" - process $proc$libresoc.v:101325$4154 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:101326.5-101326.29" - switch \initial - attribute \src "libresoc.v:101326.9-101326.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_form[4:0] 5'01000 - case - assign $1\dec31_dec_sub4_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] - end - attribute \src "libresoc.v:101338.3-101350.6" - process $proc$libresoc.v:101338$4155 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:101339.5-101339.29" - switch \initial - attribute \src "libresoc.v:101339.9-101339.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] - end - attribute \src "libresoc.v:101351.3-101363.6" - process $proc$libresoc.v:101351$4156 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:101352.5-101352.29" - switch \initial - attribute \src "libresoc.v:101352.9-101352.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] - end - attribute \src "libresoc.v:101364.3-101376.6" - process $proc$libresoc.v:101364$4157 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:101365.5-101365.29" - switch \initial - attribute \src "libresoc.v:101365.9-101365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] - end - attribute \src "libresoc.v:101377.3-101389.6" - process $proc$libresoc.v:101377$4158 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] - attribute \src "libresoc.v:101378.5-101378.29" - switch \initial - attribute \src "libresoc.v:101378.9-101378.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] - end - attribute \src "libresoc.v:101390.3-101402.6" - process $proc$libresoc.v:101390$4159 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:101391.5-101391.29" - switch \initial - attribute \src "libresoc.v:101391.9-101391.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] - end - attribute \src "libresoc.v:101403.3-101415.6" - process $proc$libresoc.v:101403$4160 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:101404.5-101404.29" - switch \initial - attribute \src "libresoc.v:101404.9-101404.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - case - assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:101421.1-102712.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" -attribute \generator "nMigen" -module \dec31_dec_sub8 - attribute \src "libresoc.v:101894.3-101936.6" - wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:102066.3-102108.6" - wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:102625.3-102667.6" - wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:102668.3-102710.6" - wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:101851.3-101893.6" - wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:102023.3-102065.6" - wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:102410.3-102452.6" - wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:101679.3-101721.6" - wire width 12 $0\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:102453.3-102495.6" - wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:102496.3-102538.6" - wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:102539.3-102581.6" - wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:102152.3-102194.6" - wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101937.3-101979.6" - wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101980.3-102022.6" - wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:102238.3-102280.6" - wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:101722.3-101764.6" - wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:102324.3-102366.6" - wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:102582.3-102624.6" - wire width 2 $0\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:101808.3-101850.6" - wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:102195.3-102237.6" - wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:102367.3-102409.6" - wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:102281.3-102323.6" - wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:102109.3-102151.6" - wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:101765.3-101807.6" - wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:101422.7-101422.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:101894.3-101936.6" - wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:102066.3-102108.6" - wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:102625.3-102667.6" - wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:102668.3-102710.6" - wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:101851.3-101893.6" - wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:102023.3-102065.6" - wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:102410.3-102452.6" - wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:101679.3-101721.6" - wire width 12 $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:102453.3-102495.6" - wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:102496.3-102538.6" - wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:102539.3-102581.6" - wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:102152.3-102194.6" - wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:101937.3-101979.6" - wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101980.3-102022.6" - wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:102238.3-102280.6" - wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:101722.3-101764.6" - wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:102324.3-102366.6" - wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:102582.3-102624.6" - wire width 2 $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:101808.3-101850.6" - wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:102195.3-102237.6" - wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:102367.3-102409.6" - wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:102281.3-102323.6" - wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:102109.3-102151.6" - wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:101765.3-101807.6" - wire width 2 $1\dec31_dec_sub8_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub8_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub8_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub8_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub8_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub8_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub8_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub8_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub8_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub8_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub8_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub8_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub8_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub8_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub8_upd - attribute \src "libresoc.v:101422.7-101422.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:101422.7-101422.20" - process $proc$libresoc.v:101422$4186 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:101679.3-101721.6" - process $proc$libresoc.v:101679$4162 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] - attribute \src "libresoc.v:101680.5-101680.29" - switch \initial - attribute \src "libresoc.v:101680.9-101680.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 - case - assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] - end - attribute \src "libresoc.v:101722.3-101764.6" - process $proc$libresoc.v:101722$4163 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:101723.5-101723.29" - switch \initial - attribute \src "libresoc.v:101723.9-101723.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] - end - attribute \src "libresoc.v:101765.3-101807.6" - process $proc$libresoc.v:101765$4164 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:101766.5-101766.29" - switch \initial - attribute \src "libresoc.v:101766.9-101766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub8_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] - end - attribute \src "libresoc.v:101808.3-101850.6" - process $proc$libresoc.v:101808$4165 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:101809.5-101809.29" - switch \initial - attribute \src "libresoc.v:101809.9-101809.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] - end - attribute \src "libresoc.v:101851.3-101893.6" - process $proc$libresoc.v:101851$4166 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:101852.5-101852.29" - switch \initial - attribute \src "libresoc.v:101852.9-101852.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 - case - assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] - end - attribute \src "libresoc.v:101894.3-101936.6" - process $proc$libresoc.v:101894$4167 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:101895.5-101895.29" - switch \initial - attribute \src "libresoc.v:101895.9-101895.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 - case - assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] - end - attribute \src "libresoc.v:101937.3-101979.6" - process $proc$libresoc.v:101937$4168 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:101938.5-101938.29" - switch \initial - attribute \src "libresoc.v:101938.9-101938.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 - case - assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] - end - attribute \src "libresoc.v:101980.3-102022.6" - process $proc$libresoc.v:101980$4169 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:101981.5-101981.29" - switch \initial - attribute \src "libresoc.v:101981.9-101981.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] - end - attribute \src "libresoc.v:102023.3-102065.6" - process $proc$libresoc.v:102023$4170 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:102024.5-102024.29" - switch \initial - attribute \src "libresoc.v:102024.9-102024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 - case - assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] - end - attribute \src "libresoc.v:102066.3-102108.6" - process $proc$libresoc.v:102066$4171 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:102067.5-102067.29" - switch \initial - attribute \src "libresoc.v:102067.9-102067.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_br[0:0] 1'0 - case - assign $1\dec31_dec_sub8_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] - end - attribute \src "libresoc.v:102109.3-102151.6" - process $proc$libresoc.v:102109$4172 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:102110.5-102110.29" - switch \initial - attribute \src "libresoc.v:102110.9-102110.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] - end - attribute \src "libresoc.v:102152.3-102194.6" - process $proc$libresoc.v:102152$4173 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:102153.5-102153.29" - switch \initial - attribute \src "libresoc.v:102153.9-102153.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 - case - assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] - end - attribute \src "libresoc.v:102195.3-102237.6" - process $proc$libresoc.v:102195$4174 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:102196.5-102196.29" - switch \initial - attribute \src "libresoc.v:102196.9-102196.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] - end - attribute \src "libresoc.v:102238.3-102280.6" - process $proc$libresoc.v:102238$4175 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:102239.5-102239.29" - switch \initial - attribute \src "libresoc.v:102239.9-102239.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] - end - attribute \src "libresoc.v:102281.3-102323.6" - process $proc$libresoc.v:102281$4176 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:102282.5-102282.29" - switch \initial - attribute \src "libresoc.v:102282.9-102282.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] - end - attribute \src "libresoc.v:102324.3-102366.6" - process $proc$libresoc.v:102324$4177 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:102325.5-102325.29" - switch \initial - attribute \src "libresoc.v:102325.9-102325.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub8_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] - end - attribute \src "libresoc.v:102367.3-102409.6" - process $proc$libresoc.v:102367$4178 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:102368.5-102368.29" - switch \initial - attribute \src "libresoc.v:102368.9-102368.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] - end - attribute \src "libresoc.v:102410.3-102452.6" - process $proc$libresoc.v:102410$4179 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:102411.5-102411.29" - switch \initial - attribute \src "libresoc.v:102411.9-102411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub8_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] - end - attribute \src "libresoc.v:102453.3-102495.6" - process $proc$libresoc.v:102453$4180 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:102454.5-102454.29" - switch \initial - attribute \src "libresoc.v:102454.9-102454.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] - end - attribute \src "libresoc.v:102496.3-102538.6" - process $proc$libresoc.v:102496$4181 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:102497.5-102497.29" - switch \initial - attribute \src "libresoc.v:102497.9-102497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - case - assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] - end - attribute \src "libresoc.v:102539.3-102581.6" - process $proc$libresoc.v:102539$4182 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:102540.5-102540.29" - switch \initial - attribute \src "libresoc.v:102540.9-102540.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] - end - attribute \src "libresoc.v:102582.3-102624.6" - process $proc$libresoc.v:102582$4183 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] - attribute \src "libresoc.v:102583.5-102583.29" - switch \initial - attribute \src "libresoc.v:102583.9-102583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] - end - attribute \src "libresoc.v:102625.3-102667.6" - process $proc$libresoc.v:102625$4184 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:102626.5-102626.29" - switch \initial - attribute \src "libresoc.v:102626.9-102626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] - end - attribute \src "libresoc.v:102668.3-102710.6" - process $proc$libresoc.v:102668$4185 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:102669.5-102669.29" - switch \initial - attribute \src "libresoc.v:102669.9-102669.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10011 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10001 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10100 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10110 - assign { } { } - assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:102716.1-104295.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" -attribute \generator "nMigen" -module \dec31_dec_sub9 - attribute \src "libresoc.v:103249.3-103303.6" - wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:103469.3-103523.6" - wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:104184.3-104238.6" - wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:104239.3-104293.6" - wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:103194.3-103248.6" - wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:103414.3-103468.6" - wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103909.3-103963.6" - wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:102974.3-103028.6" - wire width 12 $0\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:103964.3-104018.6" - wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:104019.3-104073.6" - wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:104074.3-104128.6" - wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:103579.3-103633.6" - wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:103304.3-103358.6" - wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:103359.3-103413.6" - wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:103689.3-103743.6" - wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:103029.3-103083.6" - wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:103799.3-103853.6" - wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:104129.3-104183.6" - wire width 2 $0\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:103139.3-103193.6" - wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:103634.3-103688.6" - wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:103854.3-103908.6" - wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:103744.3-103798.6" - wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:103524.3-103578.6" - wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:103084.3-103138.6" - wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:102717.7-102717.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:103249.3-103303.6" - wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:103469.3-103523.6" - wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:104184.3-104238.6" - wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:104239.3-104293.6" - wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:103194.3-103248.6" - wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:103414.3-103468.6" - wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103909.3-103963.6" - wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:102974.3-103028.6" - wire width 12 $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:103964.3-104018.6" - wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:104019.3-104073.6" - wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:104074.3-104128.6" - wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:103579.3-103633.6" - wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:103304.3-103358.6" - wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:103359.3-103413.6" - wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:103689.3-103743.6" - wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:103029.3-103083.6" - wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:103799.3-103853.6" - wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:104129.3-104183.6" - wire width 2 $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:103139.3-103193.6" - wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:103634.3-103688.6" - wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:103854.3-103908.6" - wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:103744.3-103798.6" - wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:103524.3-103578.6" - wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:103084.3-103138.6" - wire width 2 $1\dec31_dec_sub9_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec31_dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec31_dec_sub9_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec31_dec_sub9_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec31_dec_sub9_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec31_dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec31_dec_sub9_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec31_dec_sub9_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec31_dec_sub9_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec31_dec_sub9_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec31_dec_sub9_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec31_dec_sub9_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec31_dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec31_dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec31_dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec31_dec_sub9_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec31_dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec31_dec_sub9_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec31_dec_sub9_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec31_dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec31_dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec31_dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec31_dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec31_dec_sub9_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec31_dec_sub9_upd - attribute \src "libresoc.v:102717.7-102717.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 5 \opcode_switch - attribute \src "libresoc.v:102717.7-102717.20" - process $proc$libresoc.v:102717$4211 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:102974.3-103028.6" - process $proc$libresoc.v:102974$4187 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] - attribute \src "libresoc.v:102975.5-102975.29" - switch \initial - attribute \src "libresoc.v:102975.9-102975.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 - case - assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 - end - sync always - update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] - end - attribute \src "libresoc.v:103029.3-103083.6" - process $proc$libresoc.v:103029$4188 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:103030.5-103030.29" - switch \initial - attribute \src "libresoc.v:103030.9-103030.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - case - assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] - end - attribute \src "libresoc.v:103084.3-103138.6" - process $proc$libresoc.v:103084$4189 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:103085.5-103085.29" - switch \initial - attribute \src "libresoc.v:103085.9-103085.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - case - assign $1\dec31_dec_sub9_upd[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] - end - attribute \src "libresoc.v:103139.3-103193.6" - process $proc$libresoc.v:103139$4190 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:103140.5-103140.29" - switch \initial - attribute \src "libresoc.v:103140.9-103140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 - case - assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] - end - attribute \src "libresoc.v:103194.3-103248.6" - process $proc$libresoc.v:103194$4191 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:103195.5-103195.29" - switch \initial - attribute \src "libresoc.v:103195.9-103195.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - case - assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] - end - attribute \src "libresoc.v:103249.3-103303.6" - process $proc$libresoc.v:103249$4192 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:103250.5-103250.29" - switch \initial - attribute \src "libresoc.v:103250.9-103250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 - case - assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 - end - sync always - update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] - end - attribute \src "libresoc.v:103304.3-103358.6" - process $proc$libresoc.v:103304$4193 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:103305.5-103305.29" - switch \initial - attribute \src "libresoc.v:103305.9-103305.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] - end - attribute \src "libresoc.v:103359.3-103413.6" - process $proc$libresoc.v:103359$4194 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:103360.5-103360.29" - switch \initial - attribute \src "libresoc.v:103360.9-103360.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] - end - attribute \src "libresoc.v:103414.3-103468.6" - process $proc$libresoc.v:103414$4195 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:103415.5-103415.29" - switch \initial - attribute \src "libresoc.v:103415.9-103415.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - case - assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] - end - attribute \src "libresoc.v:103469.3-103523.6" - process $proc$libresoc.v:103469$4196 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:103470.5-103470.29" - switch \initial - attribute \src "libresoc.v:103470.9-103470.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_br[0:0] 1'0 - case - assign $1\dec31_dec_sub9_br[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] - end - attribute \src "libresoc.v:103524.3-103578.6" - process $proc$libresoc.v:103524$4197 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:103525.5-103525.29" - switch \initial - attribute \src "libresoc.v:103525.9-103525.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] - end - attribute \src "libresoc.v:103579.3-103633.6" - process $proc$libresoc.v:103579$4198 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:103580.5-103580.29" - switch \initial - attribute \src "libresoc.v:103580.9-103580.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 - case - assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 - end - sync always - update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] - end - attribute \src "libresoc.v:103634.3-103688.6" - process $proc$libresoc.v:103634$4199 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:103635.5-103635.29" - switch \initial - attribute \src "libresoc.v:103635.9-103635.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - case - assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] - end - attribute \src "libresoc.v:103689.3-103743.6" - process $proc$libresoc.v:103689$4200 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:103690.5-103690.29" - switch \initial - attribute \src "libresoc.v:103690.9-103690.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - case - assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] - end - attribute \src "libresoc.v:103744.3-103798.6" - process $proc$libresoc.v:103744$4201 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:103745.5-103745.29" - switch \initial - attribute \src "libresoc.v:103745.9-103745.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgn[0:0] 1'1 - case - assign $1\dec31_dec_sub9_sgn[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] - end - attribute \src "libresoc.v:103799.3-103853.6" - process $proc$libresoc.v:103799$4202 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:103800.5-103800.29" - switch \initial - attribute \src "libresoc.v:103800.9-103800.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - case - assign $1\dec31_dec_sub9_lk[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] - end - attribute \src "libresoc.v:103854.3-103908.6" - process $proc$libresoc.v:103854$4203 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:103855.5-103855.29" - switch \initial - attribute \src "libresoc.v:103855.9-103855.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - case - assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 - end - sync always - update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] - end - attribute \src "libresoc.v:103909.3-103963.6" - process $proc$libresoc.v:103909$4204 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:103910.5-103910.29" - switch \initial - attribute \src "libresoc.v:103910.9-103910.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'01000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_form[4:0] 5'10001 - case - assign $1\dec31_dec_sub9_form[4:0] 5'00000 - end - sync always - update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] - end - attribute \src "libresoc.v:103964.3-104018.6" - process $proc$libresoc.v:103964$4205 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:103965.5-103965.29" - switch \initial - attribute \src "libresoc.v:103965.9-103965.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 - case - assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] - end - attribute \src "libresoc.v:104019.3-104073.6" - process $proc$libresoc.v:104019$4206 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:104020.5-104020.29" - switch \initial - attribute \src "libresoc.v:104020.9-104020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 - case - assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 - end - sync always - update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] - end - attribute \src "libresoc.v:104074.3-104128.6" - process $proc$libresoc.v:104074$4207 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:104075.5-104075.29" - switch \initial - attribute \src "libresoc.v:104075.9-104075.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - case - assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] - end - attribute \src "libresoc.v:104129.3-104183.6" - process $proc$libresoc.v:104129$4208 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] - attribute \src "libresoc.v:104130.5-104130.29" - switch \initial - attribute \src "libresoc.v:104130.9-104130.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 - case - assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 - end - sync always - update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] - end - attribute \src "libresoc.v:104184.3-104238.6" - process $proc$libresoc.v:104184$4209 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:104185.5-104185.29" - switch \initial - attribute \src "libresoc.v:104185.9-104185.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - case - assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] - end - attribute \src "libresoc.v:104239.3-104293.6" - process $proc$libresoc.v:104239$4210 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:104240.5-104240.29" - switch \initial - attribute \src "libresoc.v:104240.9-104240.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'01100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11100 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11101 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11110 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'11111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'11000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10010 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10000 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'00111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 5'10111 - assign { } { } - assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 - case - assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 - end - sync always - update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] - end - connect \opcode_switch \opcode_in [10:6] -end -attribute \src "libresoc.v:104299.1-104942.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" -attribute \generator "nMigen" -module \dec58 - attribute \src "libresoc.v:104637.3-104652.6" - wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:104701.3-104716.6" - wire $0\dec58_br[0:0] - attribute \src "libresoc.v:104909.3-104924.6" - wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:104925.3-104940.6" - wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:104621.3-104636.6" - wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:104685.3-104700.6" - wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:104829.3-104844.6" - wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:104557.3-104572.6" - wire width 12 $0\dec58_function_unit[11:0] - attribute \src "libresoc.v:104845.3-104860.6" - wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:104861.3-104876.6" - wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104877.3-104892.6" - wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:104733.3-104748.6" - wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:104653.3-104668.6" - wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:104669.3-104684.6" - wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:104765.3-104780.6" - wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:104573.3-104588.6" - wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:104797.3-104812.6" - wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:104893.3-104908.6" - wire width 2 $0\dec58_out_sel[1:0] - attribute \src "libresoc.v:104605.3-104620.6" - wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:104749.3-104764.6" - wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:104813.3-104828.6" - wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:104781.3-104796.6" - wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:104717.3-104732.6" - wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:104589.3-104604.6" - wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:104300.7-104300.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:104637.3-104652.6" - wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:104701.3-104716.6" - wire $1\dec58_br[0:0] - attribute \src "libresoc.v:104909.3-104924.6" - wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:104925.3-104940.6" - wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:104621.3-104636.6" - wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:104685.3-104700.6" - wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:104829.3-104844.6" - wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:104557.3-104572.6" - wire width 12 $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:104845.3-104860.6" - wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:104861.3-104876.6" - wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104877.3-104892.6" - wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:104733.3-104748.6" - wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:104653.3-104668.6" - wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:104669.3-104684.6" - wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:104765.3-104780.6" - wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:104573.3-104588.6" - wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:104797.3-104812.6" - wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:104893.3-104908.6" - wire width 2 $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:104605.3-104620.6" - wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:104749.3-104764.6" - wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:104813.3-104828.6" - wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:104781.3-104796.6" - wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:104717.3-104732.6" - wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:104589.3-104604.6" - wire width 2 $1\dec58_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec58_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec58_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec58_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec58_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec58_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec58_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec58_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec58_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec58_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec58_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec58_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec58_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec58_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec58_upd - attribute \src "libresoc.v:104300.7-104300.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:104300.7-104300.20" - process $proc$libresoc.v:104300$4236 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:104557.3-104572.6" - process $proc$libresoc.v:104557$4212 - assign { } { } - assign { } { } - assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] - attribute \src "libresoc.v:104558.5-104558.29" - switch \initial - attribute \src "libresoc.v:104558.9-104558.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_function_unit[11:0] 12'000000000100 - case - assign $1\dec58_function_unit[11:0] 12'000000000000 - end - sync always - update \dec58_function_unit $0\dec58_function_unit[11:0] - end - attribute \src "libresoc.v:104573.3-104588.6" - process $proc$libresoc.v:104573$4213 - assign { } { } - assign { } { } - assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:104574.5-104574.29" - switch \initial - attribute \src "libresoc.v:104574.9-104574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_ldst_len[3:0] 4'0100 - case - assign $1\dec58_ldst_len[3:0] 4'0000 - end - sync always - update \dec58_ldst_len $0\dec58_ldst_len[3:0] - end - attribute \src "libresoc.v:104589.3-104604.6" - process $proc$libresoc.v:104589$4214 - assign { } { } - assign { } { } - assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:104590.5-104590.29" - switch \initial - attribute \src "libresoc.v:104590.9-104590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_upd[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_upd[1:0] 2'00 - case - assign $1\dec58_upd[1:0] 2'00 - end - sync always - update \dec58_upd $0\dec58_upd[1:0] - end - attribute \src "libresoc.v:104605.3-104620.6" - process $proc$libresoc.v:104605$4215 - assign { } { } - assign { } { } - assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:104606.5-104606.29" - switch \initial - attribute \src "libresoc.v:104606.9-104606.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rc_sel[1:0] 2'00 - case - assign $1\dec58_rc_sel[1:0] 2'00 - end - sync always - update \dec58_rc_sel $0\dec58_rc_sel[1:0] - end - attribute \src "libresoc.v:104621.3-104636.6" - process $proc$libresoc.v:104621$4216 - assign { } { } - assign { } { } - assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:104622.5-104622.29" - switch \initial - attribute \src "libresoc.v:104622.9-104622.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_in[1:0] 2'00 - case - assign $1\dec58_cry_in[1:0] 2'00 - end - sync always - update \dec58_cry_in $0\dec58_cry_in[1:0] - end - attribute \src "libresoc.v:104637.3-104652.6" - process $proc$libresoc.v:104637$4217 - assign { } { } - assign { } { } - assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:104638.5-104638.29" - switch \initial - attribute \src "libresoc.v:104638.9-104638.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01010101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_asmcode[7:0] 8'01100010 - case - assign $1\dec58_asmcode[7:0] 8'00000000 - end - sync always - update \dec58_asmcode $0\dec58_asmcode[7:0] - end - attribute \src "libresoc.v:104653.3-104668.6" - process $proc$libresoc.v:104653$4218 - assign { } { } - assign { } { } - assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:104654.5-104654.29" - switch \initial - attribute \src "libresoc.v:104654.9-104654.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_a[0:0] 1'0 - case - assign $1\dec58_inv_a[0:0] 1'0 - end - sync always - update \dec58_inv_a $0\dec58_inv_a[0:0] - end - attribute \src "libresoc.v:104669.3-104684.6" - process $proc$libresoc.v:104669$4219 - assign { } { } - assign { } { } - assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:104670.5-104670.29" - switch \initial - attribute \src "libresoc.v:104670.9-104670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_inv_out[0:0] 1'0 - case - assign $1\dec58_inv_out[0:0] 1'0 - end - sync always - update \dec58_inv_out $0\dec58_inv_out[0:0] - end - attribute \src "libresoc.v:104685.3-104700.6" - process $proc$libresoc.v:104685$4220 - assign { } { } - assign { } { } - assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:104686.5-104686.29" - switch \initial - attribute \src "libresoc.v:104686.9-104686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cry_out[0:0] 1'0 - case - assign $1\dec58_cry_out[0:0] 1'0 - end - sync always - update \dec58_cry_out $0\dec58_cry_out[0:0] - end - attribute \src "libresoc.v:104701.3-104716.6" - process $proc$libresoc.v:104701$4221 - assign { } { } - assign { } { } - assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:104702.5-104702.29" - switch \initial - attribute \src "libresoc.v:104702.9-104702.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_br[0:0] 1'0 - case - assign $1\dec58_br[0:0] 1'0 - end - sync always - update \dec58_br $0\dec58_br[0:0] - end - attribute \src "libresoc.v:104717.3-104732.6" - process $proc$libresoc.v:104717$4222 - assign { } { } - assign { } { } - assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:104718.5-104718.29" - switch \initial - attribute \src "libresoc.v:104718.9-104718.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn_ext[0:0] 1'1 - case - assign $1\dec58_sgn_ext[0:0] 1'0 - end - sync always - update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] - end - attribute \src "libresoc.v:104733.3-104748.6" - process $proc$libresoc.v:104733$4223 - assign { } { } - assign { } { } - assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:104734.5-104734.29" - switch \initial - attribute \src "libresoc.v:104734.9-104734.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_internal_op[6:0] 7'0100101 - case - assign $1\dec58_internal_op[6:0] 7'0000000 - end - sync always - update \dec58_internal_op $0\dec58_internal_op[6:0] - end - attribute \src "libresoc.v:104749.3-104764.6" - process $proc$libresoc.v:104749$4224 - assign { } { } - assign { } { } - assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:104750.5-104750.29" - switch \initial - attribute \src "libresoc.v:104750.9-104750.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_rsrv[0:0] 1'0 - case - assign $1\dec58_rsrv[0:0] 1'0 - end - sync always - update \dec58_rsrv $0\dec58_rsrv[0:0] - end - attribute \src "libresoc.v:104765.3-104780.6" - process $proc$libresoc.v:104765$4225 - assign { } { } - assign { } { } - assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:104766.5-104766.29" - switch \initial - attribute \src "libresoc.v:104766.9-104766.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_is_32b[0:0] 1'0 - case - assign $1\dec58_is_32b[0:0] 1'0 - end - sync always - update \dec58_is_32b $0\dec58_is_32b[0:0] - end - attribute \src "libresoc.v:104781.3-104796.6" - process $proc$libresoc.v:104781$4226 - assign { } { } - assign { } { } - assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:104782.5-104782.29" - switch \initial - attribute \src "libresoc.v:104782.9-104782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgn[0:0] 1'0 - case - assign $1\dec58_sgn[0:0] 1'0 - end - sync always - update \dec58_sgn $0\dec58_sgn[0:0] - end - attribute \src "libresoc.v:104797.3-104812.6" - process $proc$libresoc.v:104797$4227 - assign { } { } - assign { } { } - assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:104798.5-104798.29" - switch \initial - attribute \src "libresoc.v:104798.9-104798.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_lk[0:0] 1'0 - case - assign $1\dec58_lk[0:0] 1'0 - end - sync always - update \dec58_lk $0\dec58_lk[0:0] - end - attribute \src "libresoc.v:104813.3-104828.6" - process $proc$libresoc.v:104813$4228 - assign { } { } - assign { } { } - assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:104814.5-104814.29" - switch \initial - attribute \src "libresoc.v:104814.9-104814.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_sgl_pipe[0:0] 1'1 - case - assign $1\dec58_sgl_pipe[0:0] 1'0 - end - sync always - update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] - end - attribute \src "libresoc.v:104829.3-104844.6" - process $proc$libresoc.v:104829$4229 - assign { } { } - assign { } { } - assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:104830.5-104830.29" - switch \initial - attribute \src "libresoc.v:104830.9-104830.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_form[4:0] 5'00101 - case - assign $1\dec58_form[4:0] 5'00000 - end - sync always - update \dec58_form $0\dec58_form[4:0] - end - attribute \src "libresoc.v:104845.3-104860.6" - process $proc$libresoc.v:104845$4230 - assign { } { } - assign { } { } - assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:104846.5-104846.29" - switch \initial - attribute \src "libresoc.v:104846.9-104846.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in1_sel[2:0] 3'010 - case - assign $1\dec58_in1_sel[2:0] 3'000 - end - sync always - update \dec58_in1_sel $0\dec58_in1_sel[2:0] - end - attribute \src "libresoc.v:104861.3-104876.6" - process $proc$libresoc.v:104861$4231 - assign { } { } - assign { } { } - assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:104862.5-104862.29" - switch \initial - attribute \src "libresoc.v:104862.9-104862.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in2_sel[3:0] 4'1000 - case - assign $1\dec58_in2_sel[3:0] 4'0000 - end - sync always - update \dec58_in2_sel $0\dec58_in2_sel[3:0] - end - attribute \src "libresoc.v:104877.3-104892.6" - process $proc$libresoc.v:104877$4232 - assign { } { } - assign { } { } - assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:104878.5-104878.29" - switch \initial - attribute \src "libresoc.v:104878.9-104878.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_in3_sel[1:0] 2'00 - case - assign $1\dec58_in3_sel[1:0] 2'00 - end - sync always - update \dec58_in3_sel $0\dec58_in3_sel[1:0] - end - attribute \src "libresoc.v:104893.3-104908.6" - process $proc$libresoc.v:104893$4233 - assign { } { } - assign { } { } - assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] - attribute \src "libresoc.v:104894.5-104894.29" - switch \initial - attribute \src "libresoc.v:104894.9-104894.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_out_sel[1:0] 2'01 - case - assign $1\dec58_out_sel[1:0] 2'00 - end - sync always - update \dec58_out_sel $0\dec58_out_sel[1:0] - end - attribute \src "libresoc.v:104909.3-104924.6" - process $proc$libresoc.v:104909$4234 - assign { } { } - assign { } { } - assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:104910.5-104910.29" - switch \initial - attribute \src "libresoc.v:104910.9-104910.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_in[2:0] 3'000 - case - assign $1\dec58_cr_in[2:0] 3'000 - end - sync always - update \dec58_cr_in $0\dec58_cr_in[2:0] - end - attribute \src "libresoc.v:104925.3-104940.6" - process $proc$libresoc.v:104925$4235 - assign { } { } - assign { } { } - assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:104926.5-104926.29" - switch \initial - attribute \src "libresoc.v:104926.9-104926.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\dec58_cr_out[2:0] 3'000 - case - assign $1\dec58_cr_out[2:0] 3'000 - end - sync always - update \dec58_cr_out $0\dec58_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:104946.1-105517.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" -attribute \generator "nMigen" -module \dec62 - attribute \src "libresoc.v:105269.3-105281.6" - wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:105321.3-105333.6" - wire $0\dec62_br[0:0] - attribute \src "libresoc.v:105490.3-105502.6" - wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:105503.3-105515.6" - wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:105256.3-105268.6" - wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:105308.3-105320.6" - wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:105425.3-105437.6" - wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:105204.3-105216.6" - wire width 12 $0\dec62_function_unit[11:0] - attribute \src "libresoc.v:105438.3-105450.6" - wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:105451.3-105463.6" - wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:105464.3-105476.6" - wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:105347.3-105359.6" - wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:105282.3-105294.6" - wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:105295.3-105307.6" - wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:105373.3-105385.6" - wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:105217.3-105229.6" - wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:105399.3-105411.6" - wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:105477.3-105489.6" - wire width 2 $0\dec62_out_sel[1:0] - attribute \src "libresoc.v:105243.3-105255.6" - wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:105360.3-105372.6" - wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:105412.3-105424.6" - wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:105386.3-105398.6" - wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:105334.3-105346.6" - wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:105230.3-105242.6" - wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:104947.7-104947.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:105269.3-105281.6" - wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:105321.3-105333.6" - wire $1\dec62_br[0:0] - attribute \src "libresoc.v:105490.3-105502.6" - wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:105503.3-105515.6" - wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:105256.3-105268.6" - wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:105308.3-105320.6" - wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:105425.3-105437.6" - wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:105204.3-105216.6" - wire width 12 $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:105438.3-105450.6" - wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:105451.3-105463.6" - wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:105464.3-105476.6" - wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:105347.3-105359.6" - wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:105282.3-105294.6" - wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:105295.3-105307.6" - wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:105373.3-105385.6" - wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:105217.3-105229.6" - wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:105399.3-105411.6" - wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:105477.3-105489.6" - wire width 2 $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:105243.3-105255.6" - wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:105360.3-105372.6" - wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:105412.3-105424.6" - wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:105386.3-105398.6" - wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:105334.3-105346.6" - wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:105230.3-105242.6" - wire width 2 $1\dec62_upd[1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 8 output 4 \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 18 \dec62_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 9 \dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 10 \dec62_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 14 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 17 \dec62_cry_out - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 5 output 3 \dec62_form - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 output 1 \dec62_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 output 5 \dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 6 \dec62_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 7 \dec62_in3_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 output 2 \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 15 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 16 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 21 \dec62_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 output 11 \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 23 \dec62_lk - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 8 \dec62_out_sel - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 13 \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 20 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 24 \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 22 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire output 19 \dec62_sgn_ext - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 output 12 \dec62_upd - attribute \src "libresoc.v:104947.7-104947.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 input 25 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" - wire width 2 \opcode_switch - attribute \src "libresoc.v:104947.7-104947.20" - process $proc$libresoc.v:104947$4261 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:105204.3-105216.6" - process $proc$libresoc.v:105204$4237 - assign { } { } - assign { } { } - assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] - attribute \src "libresoc.v:105205.5-105205.29" - switch \initial - attribute \src "libresoc.v:105205.9-105205.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_function_unit[11:0] 12'000000000100 - case - assign $1\dec62_function_unit[11:0] 12'000000000000 - end - sync always - update \dec62_function_unit $0\dec62_function_unit[11:0] - end - attribute \src "libresoc.v:105217.3-105229.6" - process $proc$libresoc.v:105217$4238 - assign { } { } - assign { } { } - assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:105218.5-105218.29" - switch \initial - attribute \src "libresoc.v:105218.9-105218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_ldst_len[3:0] 4'1000 - case - assign $1\dec62_ldst_len[3:0] 4'0000 - end - sync always - update \dec62_ldst_len $0\dec62_ldst_len[3:0] - end - attribute \src "libresoc.v:105230.3-105242.6" - process $proc$libresoc.v:105230$4239 - assign { } { } - assign { } { } - assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:105231.5-105231.29" - switch \initial - attribute \src "libresoc.v:105231.9-105231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_upd[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_upd[1:0] 2'01 - case - assign $1\dec62_upd[1:0] 2'00 - end - sync always - update \dec62_upd $0\dec62_upd[1:0] - end - attribute \src "libresoc.v:105243.3-105255.6" - process $proc$libresoc.v:105243$4240 - assign { } { } - assign { } { } - assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:105244.5-105244.29" - switch \initial - attribute \src "libresoc.v:105244.9-105244.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rc_sel[1:0] 2'00 - case - assign $1\dec62_rc_sel[1:0] 2'00 - end - sync always - update \dec62_rc_sel $0\dec62_rc_sel[1:0] - end - attribute \src "libresoc.v:105256.3-105268.6" - process $proc$libresoc.v:105256$4241 - assign { } { } - assign { } { } - assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:105257.5-105257.29" - switch \initial - attribute \src "libresoc.v:105257.9-105257.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_in[1:0] 2'00 - case - assign $1\dec62_cry_in[1:0] 2'00 - end - sync always - update \dec62_cry_in $0\dec62_cry_in[1:0] - end - attribute \src "libresoc.v:105269.3-105281.6" - process $proc$libresoc.v:105269$4242 - assign { } { } - assign { } { } - assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:105270.5-105270.29" - switch \initial - attribute \src "libresoc.v:105270.9-105270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101100 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_asmcode[7:0] 8'10101111 - case - assign $1\dec62_asmcode[7:0] 8'00000000 - end - sync always - update \dec62_asmcode $0\dec62_asmcode[7:0] - end - attribute \src "libresoc.v:105282.3-105294.6" - process $proc$libresoc.v:105282$4243 - assign { } { } - assign { } { } - assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:105283.5-105283.29" - switch \initial - attribute \src "libresoc.v:105283.9-105283.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_a[0:0] 1'0 - case - assign $1\dec62_inv_a[0:0] 1'0 - end - sync always - update \dec62_inv_a $0\dec62_inv_a[0:0] - end - attribute \src "libresoc.v:105295.3-105307.6" - process $proc$libresoc.v:105295$4244 - assign { } { } - assign { } { } - assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:105296.5-105296.29" - switch \initial - attribute \src "libresoc.v:105296.9-105296.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_inv_out[0:0] 1'0 - case - assign $1\dec62_inv_out[0:0] 1'0 - end - sync always - update \dec62_inv_out $0\dec62_inv_out[0:0] - end - attribute \src "libresoc.v:105308.3-105320.6" - process $proc$libresoc.v:105308$4245 - assign { } { } - assign { } { } - assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:105309.5-105309.29" - switch \initial - attribute \src "libresoc.v:105309.9-105309.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cry_out[0:0] 1'0 - case - assign $1\dec62_cry_out[0:0] 1'0 - end - sync always - update \dec62_cry_out $0\dec62_cry_out[0:0] - end - attribute \src "libresoc.v:105321.3-105333.6" - process $proc$libresoc.v:105321$4246 - assign { } { } - assign { } { } - assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:105322.5-105322.29" - switch \initial - attribute \src "libresoc.v:105322.9-105322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_br[0:0] 1'0 - case - assign $1\dec62_br[0:0] 1'0 - end - sync always - update \dec62_br $0\dec62_br[0:0] - end - attribute \src "libresoc.v:105334.3-105346.6" - process $proc$libresoc.v:105334$4247 - assign { } { } - assign { } { } - assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:105335.5-105335.29" - switch \initial - attribute \src "libresoc.v:105335.9-105335.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn_ext[0:0] 1'0 - case - assign $1\dec62_sgn_ext[0:0] 1'0 - end - sync always - update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] - end - attribute \src "libresoc.v:105347.3-105359.6" - process $proc$libresoc.v:105347$4248 - assign { } { } - assign { } { } - assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:105348.5-105348.29" - switch \initial - attribute \src "libresoc.v:105348.9-105348.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_internal_op[6:0] 7'0100110 - case - assign $1\dec62_internal_op[6:0] 7'0000000 - end - sync always - update \dec62_internal_op $0\dec62_internal_op[6:0] - end - attribute \src "libresoc.v:105360.3-105372.6" - process $proc$libresoc.v:105360$4249 - assign { } { } - assign { } { } - assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:105361.5-105361.29" - switch \initial - attribute \src "libresoc.v:105361.9-105361.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_rsrv[0:0] 1'0 - case - assign $1\dec62_rsrv[0:0] 1'0 - end - sync always - update \dec62_rsrv $0\dec62_rsrv[0:0] - end - attribute \src "libresoc.v:105373.3-105385.6" - process $proc$libresoc.v:105373$4250 - assign { } { } - assign { } { } - assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:105374.5-105374.29" - switch \initial - attribute \src "libresoc.v:105374.9-105374.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_is_32b[0:0] 1'0 - case - assign $1\dec62_is_32b[0:0] 1'0 - end - sync always - update \dec62_is_32b $0\dec62_is_32b[0:0] - end - attribute \src "libresoc.v:105386.3-105398.6" - process $proc$libresoc.v:105386$4251 - assign { } { } - assign { } { } - assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:105387.5-105387.29" - switch \initial - attribute \src "libresoc.v:105387.9-105387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgn[0:0] 1'0 - case - assign $1\dec62_sgn[0:0] 1'0 - end - sync always - update \dec62_sgn $0\dec62_sgn[0:0] - end - attribute \src "libresoc.v:105399.3-105411.6" - process $proc$libresoc.v:105399$4252 - assign { } { } - assign { } { } - assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:105400.5-105400.29" - switch \initial - attribute \src "libresoc.v:105400.9-105400.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_lk[0:0] 1'0 - case - assign $1\dec62_lk[0:0] 1'0 - end - sync always - update \dec62_lk $0\dec62_lk[0:0] - end - attribute \src "libresoc.v:105412.3-105424.6" - process $proc$libresoc.v:105412$4253 - assign { } { } - assign { } { } - assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:105413.5-105413.29" - switch \initial - attribute \src "libresoc.v:105413.9-105413.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_sgl_pipe[0:0] 1'1 - case - assign $1\dec62_sgl_pipe[0:0] 1'0 - end - sync always - update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] - end - attribute \src "libresoc.v:105425.3-105437.6" - process $proc$libresoc.v:105425$4254 - assign { } { } - assign { } { } - assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:105426.5-105426.29" - switch \initial - attribute \src "libresoc.v:105426.9-105426.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_form[4:0] 5'00101 - case - assign $1\dec62_form[4:0] 5'00000 - end - sync always - update \dec62_form $0\dec62_form[4:0] - end - attribute \src "libresoc.v:105438.3-105450.6" - process $proc$libresoc.v:105438$4255 - assign { } { } - assign { } { } - assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:105439.5-105439.29" - switch \initial - attribute \src "libresoc.v:105439.9-105439.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in1_sel[2:0] 3'010 - case - assign $1\dec62_in1_sel[2:0] 3'000 - end - sync always - update \dec62_in1_sel $0\dec62_in1_sel[2:0] - end - attribute \src "libresoc.v:105451.3-105463.6" - process $proc$libresoc.v:105451$4256 - assign { } { } - assign { } { } - assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:105452.5-105452.29" - switch \initial - attribute \src "libresoc.v:105452.9-105452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in2_sel[3:0] 4'1000 - case - assign $1\dec62_in2_sel[3:0] 4'0000 - end - sync always - update \dec62_in2_sel $0\dec62_in2_sel[3:0] - end - attribute \src "libresoc.v:105464.3-105476.6" - process $proc$libresoc.v:105464$4257 - assign { } { } - assign { } { } - assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:105465.5-105465.29" - switch \initial - attribute \src "libresoc.v:105465.9-105465.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_in3_sel[1:0] 2'01 - case - assign $1\dec62_in3_sel[1:0] 2'00 - end - sync always - update \dec62_in3_sel $0\dec62_in3_sel[1:0] - end - attribute \src "libresoc.v:105477.3-105489.6" - process $proc$libresoc.v:105477$4258 - assign { } { } - assign { } { } - assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] - attribute \src "libresoc.v:105478.5-105478.29" - switch \initial - attribute \src "libresoc.v:105478.9-105478.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_out_sel[1:0] 2'00 - case - assign $1\dec62_out_sel[1:0] 2'00 - end - sync always - update \dec62_out_sel $0\dec62_out_sel[1:0] - end - attribute \src "libresoc.v:105490.3-105502.6" - process $proc$libresoc.v:105490$4259 - assign { } { } - assign { } { } - assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:105491.5-105491.29" - switch \initial - attribute \src "libresoc.v:105491.9-105491.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cr_in[2:0] 3'000 - case - assign $1\dec62_cr_in[2:0] 3'000 - end - sync always - update \dec62_cr_in $0\dec62_cr_in[2:0] - end - attribute \src "libresoc.v:105503.3-105515.6" - process $proc$libresoc.v:105503$4260 - assign { } { } - assign { } { } - assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:105504.5-105504.29" - switch \initial - attribute \src "libresoc.v:105504.9-105504.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\dec62_cr_out[2:0] 3'000 - case - assign $1\dec62_cr_out[2:0] 3'000 - end - sync always - update \dec62_cr_out $0\dec62_cr_out[2:0] - end - connect \opcode_switch \opcode_in [1:0] -end -attribute \src "libresoc.v:105521.1-106054.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" -attribute \generator "nMigen" -module \dec_ALU - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \ALU__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \ALU__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \ALU__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \ALU__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 14 \ALU__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \ALU__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \ALU__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \ALU__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \ALU__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \ALU__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \ALU__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \ALU__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \ALU__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \ALU__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \ALU__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \ALU__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \ALU__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_ALU_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_ALU_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_ALU_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_ALU_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_ALU_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:105938.7-105975.4" - cell \dec \dec - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC - connect \ALU_BD \dec_ALU_BD - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT - connect \ALU_DS \dec_ALU_DS - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_LI \dec_ALU_LI - connect \ALU_OE \dec_ALU_OE - connect \ALU_RA \dec_ALU_RA - connect \ALU_Rc \dec_ALU_Rc - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_cr_in \dec_ALU_cr_in - connect \ALU_cr_out \dec_ALU_cr_out - connect \ALU_cry_in \dec_ALU_cry_in - connect \ALU_cry_out \dec_ALU_cry_out - connect \ALU_function_unit \dec_ALU_function_unit - connect \ALU_in1_sel \dec_ALU_in1_sel - connect \ALU_in2_sel \dec_ALU_in2_sel - connect \ALU_internal_op \dec_ALU_internal_op - connect \ALU_inv_a \dec_ALU_inv_a - connect \ALU_inv_out \dec_ALU_inv_out - connect \ALU_is_32b \dec_ALU_is_32b - connect \ALU_ldst_len \dec_ALU_ldst_len - connect \ALU_rc_sel \dec_ALU_rc_sel - connect \ALU_sgn \dec_ALU_sgn - connect \ALU_sh \dec_ALU_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105976.10-105980.4" - cell \dec_ai \dec_ai - connect \ALU_RA \dec_ALU_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105981.10-105992.4" - cell \dec_bi \dec_bi - connect \ALU_BD \dec_ALU_BD - connect \ALU_DS \dec_ALU_DS - connect \ALU_LI \dec_ALU_LI - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_sh \dec_ALU_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:105993.13-106004.4" - cell \dec_cr_in \dec_cr_in - connect \ALU_BA \dec_ALU_BA - connect \ALU_BB \dec_ALU_BB - connect \ALU_BC \dec_ALU_BC - connect \ALU_BI \dec_ALU_BI - connect \ALU_BT \dec_ALU_BT - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106005.14-106014.4" - cell \dec_cr_out \dec_cr_out - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_internal_op \dec_ALU_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106015.10-106021.4" - cell \dec_oe \dec_oe - connect \ALU_OE \dec_ALU_OE - connect \ALU_internal_op \dec_ALU_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106022.10-106027.4" - cell \dec_rc \dec_rc - connect \ALU_Rc \dec_ALU_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \ALU__is_signed \dec_ALU_sgn - connect \ALU__is_32bit \dec_ALU_is_32b - connect \ALU__output_carry \dec_ALU_cry_out - connect \ALU__input_carry \dec_ALU_cry_in - connect \ALU__invert_out \dec_ALU_inv_out - connect \ALU__invert_in \dec_ALU_inv_a - connect \ALU__data_len \dec_ALU_ldst_len - connect \ALU__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \ALU__oe__ok \ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \ALU__rc__ok \ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \ALU__imm_data__ok \ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_ALU_in2_sel - connect \ALU__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_ALU_in1_sel - connect \ALU__fn_unit \dec_ALU_function_unit - connect \ALU__insn_type \dec_ALU_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_ALU_cr_out - connect \dec_cr_in_sel_in \dec_ALU_cr_in - connect \dec_oe_sel_in \dec_ALU_rc_sel - connect \dec_rc_sel_in \dec_ALU_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \ALU__insn \dec_opcode_in -end -attribute \src "libresoc.v:106058.1-106510.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" -attribute \generator "nMigen" -module \dec_BRANCH - attribute \src "libresoc.v:106484.3-106493.6" - wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:106059.7-106059.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:106484.3-106493.6" - wire $1\BRANCH__lk[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 3 \BRANCH__cia - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 5 \BRANCH__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \BRANCH__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \BRANCH__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 6 \BRANCH__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 4 \BRANCH__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \BRANCH__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 2 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 11 \core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_BRANCH_LK - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_BRANCH_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_BRANCH_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_BRANCH_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_BRANCH_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_BRANCH_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_BRANCH_lk - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:106059.7-106059.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 1 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:106409.13-106440.4" - cell \dec$147 \dec - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC - connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_DS \dec_BRANCH_DS - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_LI \dec_BRANCH_LI - connect \BRANCH_LK \dec_BRANCH_LK - connect \BRANCH_OE \dec_BRANCH_OE - connect \BRANCH_Rc \dec_BRANCH_Rc - connect \BRANCH_SH32 \dec_BRANCH_SH32 - connect \BRANCH_SI \dec_BRANCH_SI - connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_cr_in \dec_BRANCH_cr_in - connect \BRANCH_cr_out \dec_BRANCH_cr_out - connect \BRANCH_function_unit \dec_BRANCH_function_unit - connect \BRANCH_in2_sel \dec_BRANCH_in2_sel - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \BRANCH_is_32b \dec_BRANCH_is_32b - connect \BRANCH_lk \dec_BRANCH_lk - connect \BRANCH_rc_sel \dec_BRANCH_rc_sel - connect \BRANCH_sh \dec_BRANCH_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106441.16-106452.4" - cell \dec_bi$154 \dec_bi - connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_DS \dec_BRANCH_DS - connect \BRANCH_LI \dec_BRANCH_LI - connect \BRANCH_SH32 \dec_BRANCH_SH32 - connect \BRANCH_SI \dec_BRANCH_SI - connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_sh \dec_BRANCH_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106453.19-106464.4" - cell \dec_cr_in$150 \dec_cr_in - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BC \dec_BRANCH_BC - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106465.20-106473.4" - cell \dec_cr_out$152 \dec_cr_out - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106474.16-106478.4" - cell \dec_oe$149 \dec_oe - connect \BRANCH_OE \dec_BRANCH_OE - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:106479.16-106483.4" - cell \dec_rc$148 \dec_rc - connect \BRANCH_Rc \dec_BRANCH_Rc - connect \rc \dec_rc_rc - connect \sel_in \dec_rc_sel_in - end - attribute \src "libresoc.v:106059.7-106059.20" - process $proc$libresoc.v:106059$4263 - assign { } { } - assign $0\initial[0:0] 1'0 - sync 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 5 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:106793.13-106813.4" - cell \dec$140 \dec - connect \CR_BA \dec_CR_BA - connect \CR_BB \dec_CR_BB - connect \CR_BC \dec_CR_BC - connect \CR_BI \dec_CR_BI - connect \CR_BT \dec_CR_BT - connect \CR_FXM \dec_CR_FXM - connect \CR_OE \dec_CR_OE - connect \CR_Rc \dec_CR_Rc - connect \CR_cr_in \dec_CR_cr_in - connect \CR_cr_out \dec_CR_cr_out - connect \CR_function_unit \dec_CR_function_unit - connect \CR_internal_op \dec_CR_internal_op - connect \CR_rc_sel \dec_CR_rc_sel - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src 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"ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \DIV__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \DIV__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \DIV__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \DIV__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \DIV__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \DIV__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \DIV__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \DIV__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \DIV__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \DIV__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \DIV__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \DIV__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \DIV__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \DIV__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_DIV_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_DIV_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_DIV_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_DIV_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_DIV_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_DIV_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_DIV_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_DIV_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:107278.13-107315.4" - cell \dec$171 \dec - connect \DIV_BA \dec_DIV_BA - connect \DIV_BB \dec_DIV_BB - connect \DIV_BC \dec_DIV_BC - connect \DIV_BD \dec_DIV_BD - connect \DIV_BI \dec_DIV_BI - connect \DIV_BT \dec_DIV_BT - connect \DIV_DS \dec_DIV_DS - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_LI \dec_DIV_LI - connect \DIV_OE \dec_DIV_OE - connect \DIV_RA \dec_DIV_RA - connect \DIV_Rc \dec_DIV_Rc - connect \DIV_SH32 \dec_DIV_SH32 - connect \DIV_SI \dec_DIV_SI - connect \DIV_UI \dec_DIV_UI - connect \DIV_cr_in \dec_DIV_cr_in - connect \DIV_cr_out \dec_DIV_cr_out - connect \DIV_cry_in \dec_DIV_cry_in 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connect \DIV_BD \dec_DIV_BD - connect \DIV_DS \dec_DIV_DS - connect \DIV_LI \dec_DIV_LI - connect \DIV_SH32 \dec_DIV_SH32 - connect \DIV_SI \dec_DIV_SI - connect \DIV_UI \dec_DIV_UI - connect \DIV_sh \dec_DIV_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107333.19-107344.4" - cell \dec_cr_in$174 \dec_cr_in - connect \DIV_BA \dec_DIV_BA - connect \DIV_BB \dec_DIV_BB - connect \DIV_BC \dec_DIV_BC - connect \DIV_BI \dec_DIV_BI - connect \DIV_BT \dec_DIV_BT - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_internal_op \dec_DIV_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107345.20-107354.4" - cell \dec_cr_out$176 \dec_cr_out - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_internal_op \dec_DIV_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107355.16-107361.4" - cell \dec_oe$173 \dec_oe - connect \DIV_OE \dec_DIV_OE - connect \DIV_internal_op \dec_DIV_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107362.16-107367.4" - cell \dec_rc$172 \dec_rc - connect \DIV_Rc \dec_DIV_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \DIV__is_signed \dec_DIV_sgn - connect \DIV__is_32bit \dec_DIV_is_32b - connect \DIV__output_carry \dec_DIV_cry_out - connect \DIV__input_carry \dec_DIV_cry_in - connect \DIV__invert_out \dec_DIV_inv_out - connect \DIV__invert_in \dec_DIV_inv_a - connect \DIV__data_len \dec_DIV_ldst_len - connect \DIV__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_DIV_in2_sel - connect \DIV__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_DIV_in1_sel - connect \DIV__fn_unit \dec_DIV_function_unit - connect \DIV__insn_type \dec_DIV_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_DIV_cr_out - connect \dec_cr_in_sel_in \dec_DIV_cr_in - connect \dec_oe_sel_in \dec_DIV_rc_sel - connect \dec_rc_sel_in \dec_DIV_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \DIV__insn \dec_opcode_in -end -attribute \src "libresoc.v:107398.1-107921.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" -attribute \generator "nMigen" -module \dec_LDST - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LDST__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 13 \LDST__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \LDST__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LDST__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LDST__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \LDST__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LDST__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LDST__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \LDST__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 16 \LDST__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LDST__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LDST__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LDST__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LDST__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LDST__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LDST_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LDST_br - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LDST_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LDST_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_LDST_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LDST_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LDST_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LDST_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_LDST_sh - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 18 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:107809.13-107845.4" - cell \dec$196 \dec - connect \LDST_BA \dec_LDST_BA - connect \LDST_BB \dec_LDST_BB - connect \LDST_BC \dec_LDST_BC - connect \LDST_BD \dec_LDST_BD - connect \LDST_BI \dec_LDST_BI - connect \LDST_BT \dec_LDST_BT - connect \LDST_DS \dec_LDST_DS - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_LI \dec_LDST_LI - connect \LDST_OE \dec_LDST_OE - connect \LDST_RA \dec_LDST_RA - connect \LDST_Rc \dec_LDST_Rc - connect \LDST_SH32 \dec_LDST_SH32 - connect \LDST_SI \dec_LDST_SI - connect \LDST_UI \dec_LDST_UI - connect \LDST_br \dec_LDST_br - connect \LDST_cr_in \dec_LDST_cr_in - connect \LDST_cr_out \dec_LDST_cr_out - connect \LDST_function_unit \dec_LDST_function_unit - connect \LDST_in1_sel \dec_LDST_in1_sel - connect \LDST_in2_sel \dec_LDST_in2_sel - connect \LDST_internal_op \dec_LDST_internal_op - connect \LDST_is_32b \dec_LDST_is_32b - connect \LDST_ldst_len \dec_LDST_ldst_len - connect \LDST_rc_sel \dec_LDST_rc_sel - connect \LDST_sgn \dec_LDST_sgn - connect \LDST_sgn_ext \dec_LDST_sgn_ext - connect \LDST_sh \dec_LDST_sh - connect \LDST_upd \dec_LDST_upd - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107846.16-107850.4" - cell \dec_ai$203 \dec_ai - connect \LDST_RA \dec_LDST_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107851.16-107862.4" - cell \dec_bi$204 \dec_bi - connect \LDST_BD \dec_LDST_BD - connect \LDST_DS \dec_LDST_DS - connect \LDST_LI \dec_LDST_LI - connect \LDST_SH32 \dec_LDST_SH32 - connect \LDST_SI \dec_LDST_SI - connect \LDST_UI \dec_LDST_UI - connect \LDST_sh \dec_LDST_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107863.19-107874.4" - cell \dec_cr_in$199 \dec_cr_in - connect \LDST_BA \dec_LDST_BA - connect \LDST_BB \dec_LDST_BB - connect \LDST_BC \dec_LDST_BC - connect \LDST_BI \dec_LDST_BI - connect \LDST_BT \dec_LDST_BT - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_internal_op \dec_LDST_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107875.20-107883.4" - cell \dec_cr_out$201 \dec_cr_out - connect \LDST_FXM \dec_LDST_FXM - connect \LDST_internal_op \dec_LDST_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107884.16-107890.4" - cell \dec_oe$198 \dec_oe - connect \LDST_OE \dec_LDST_OE - connect \LDST_internal_op \dec_LDST_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:107891.16-107896.4" - cell \dec_rc$197 \dec_rc - connect \LDST_Rc \dec_LDST_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \LDST__ldst_mode \dec_LDST_upd - connect \LDST__sign_extend \dec_LDST_sgn_ext - connect \LDST__byte_reverse \dec_LDST_br - connect \LDST__is_signed \dec_LDST_sgn - connect \LDST__is_32bit \dec_LDST_is_32b - connect \LDST__data_len \dec_LDST_ldst_len - connect { \LDST__oe__ok \LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \LDST__rc__ok \LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \LDST__imm_data__ok \LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_LDST_in2_sel - connect \LDST__zero_a \dec_ai_immz_out - connect \dec_ai_sel_in \dec_LDST_in1_sel - connect \LDST__fn_unit \dec_LDST_function_unit - connect \LDST__insn_type \dec_LDST_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_LDST_cr_out - connect \dec_cr_in_sel_in \dec_LDST_cr_in - connect \dec_oe_sel_in \dec_LDST_rc_sel - connect \dec_rc_sel_in \dec_LDST_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \LDST__insn \dec_opcode_in -end -attribute \src "libresoc.v:107925.1-108458.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" -attribute \generator "nMigen" -module \dec_LOGICAL - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 18 \LOGICAL__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \LOGICAL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \LOGICAL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \LOGICAL__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \LOGICAL__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \LOGICAL__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \LOGICAL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \LOGICAL__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \LOGICAL__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \LOGICAL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \LOGICAL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \LOGICAL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \LOGICAL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \LOGICAL__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \LOGICAL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \LOGICAL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \LOGICAL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \LOGICAL__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LOGICAL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_LOGICAL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_LOGICAL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LOGICAL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LOGICAL_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_LOGICAL_function_unit - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_LOGICAL_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LOGICAL_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_is_32b - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_LOGICAL_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:152" - wire \dec_ai_immz_out - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 20 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:108342.13-108379.4" - cell \dec$155 \dec - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC - connect \LOGICAL_BD \dec_LOGICAL_BD - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT - connect \LOGICAL_DS \dec_LOGICAL_DS - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_LI \dec_LOGICAL_LI - connect \LOGICAL_OE \dec_LOGICAL_OE - connect \LOGICAL_RA \dec_LOGICAL_RA - connect \LOGICAL_Rc \dec_LOGICAL_Rc - connect \LOGICAL_SH32 \dec_LOGICAL_SH32 - connect \LOGICAL_SI \dec_LOGICAL_SI - connect \LOGICAL_UI \dec_LOGICAL_UI - connect \LOGICAL_cr_in \dec_LOGICAL_cr_in - connect \LOGICAL_cr_out \dec_LOGICAL_cr_out - connect \LOGICAL_cry_in \dec_LOGICAL_cry_in - connect \LOGICAL_cry_out \dec_LOGICAL_cry_out - connect \LOGICAL_function_unit \dec_LOGICAL_function_unit - connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel - connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \LOGICAL_inv_a \dec_LOGICAL_inv_a - connect \LOGICAL_inv_out \dec_LOGICAL_inv_out - connect \LOGICAL_is_32b \dec_LOGICAL_is_32b - connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len - connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel - connect \LOGICAL_sgn \dec_LOGICAL_sgn - connect \LOGICAL_sh \dec_LOGICAL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108380.16-108384.4" - cell \dec_ai$162 \dec_ai - connect \LOGICAL_RA \dec_LOGICAL_RA - connect \immz_out \dec_ai_immz_out - connect \sel_in \dec_ai_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108385.16-108396.4" - cell \dec_bi$163 \dec_bi - connect \LOGICAL_BD \dec_LOGICAL_BD - connect \LOGICAL_DS \dec_LOGICAL_DS - connect \LOGICAL_LI \dec_LOGICAL_LI - connect \LOGICAL_SH32 \dec_LOGICAL_SH32 - connect \LOGICAL_SI \dec_LOGICAL_SI - connect \LOGICAL_UI \dec_LOGICAL_UI - connect \LOGICAL_sh \dec_LOGICAL_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108397.19-108408.4" - cell \dec_cr_in$158 \dec_cr_in - connect \LOGICAL_BA \dec_LOGICAL_BA - connect \LOGICAL_BB \dec_LOGICAL_BB - connect \LOGICAL_BC \dec_LOGICAL_BC - connect \LOGICAL_BI \dec_LOGICAL_BI - connect \LOGICAL_BT \dec_LOGICAL_BT - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108409.20-108418.4" - cell \dec_cr_out$160 \dec_cr_out - connect \LOGICAL_FXM \dec_LOGICAL_FXM - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108419.16-108425.4" - cell \dec_oe$157 \dec_oe - connect \LOGICAL_OE \dec_LOGICAL_OE - connect \LOGICAL_internal_op \dec_LOGICAL_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108426.16-108431.4" - cell \dec_rc$156 \dec_rc - connect \LOGICAL_Rc \dec_LOGICAL_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \LOGICAL__is_signed \dec_LOGICAL_sgn - connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b - connect \LOGICAL__output_carry \dec_LOGICAL_cry_out - connect \LOGICAL__input_carry \dec_LOGICAL_cry_in - connect \LOGICAL__invert_out \dec_LOGICAL_inv_out - connect \LOGICAL__invert_in \dec_LOGICAL_inv_a - connect \LOGICAL__data_len \dec_LOGICAL_ldst_len - connect \LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_LOGICAL_in2_sel - connect \LOGICAL__zero_a \dec_ai_immz_out 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attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \MUL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \MUL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \MUL__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \MUL__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute 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"OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \MUL__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \MUL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \MUL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \MUL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \MUL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \MUL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \MUL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_MUL_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_MUL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_MUL_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_MUL_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_MUL_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_MUL_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 14 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:108823.13-108853.4" - cell \dec$180 \dec - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC - connect \MUL_BD \dec_MUL_BD - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT - connect \MUL_DS \dec_MUL_DS - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_LI \dec_MUL_LI - connect \MUL_OE \dec_MUL_OE - connect \MUL_Rc \dec_MUL_Rc - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_cr_in \dec_MUL_cr_in - connect \MUL_cr_out \dec_MUL_cr_out - connect \MUL_function_unit \dec_MUL_function_unit - connect \MUL_in2_sel \dec_MUL_in2_sel - connect \MUL_internal_op \dec_MUL_internal_op - connect \MUL_is_32b \dec_MUL_is_32b - connect \MUL_rc_sel \dec_MUL_rc_sel - connect \MUL_sgn \dec_MUL_sgn - connect \MUL_sh \dec_MUL_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108854.16-108865.4" - cell \dec_bi$187 \dec_bi - connect \MUL_BD \dec_MUL_BD - connect \MUL_DS \dec_MUL_DS - connect \MUL_LI \dec_MUL_LI - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_sh \dec_MUL_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108866.19-108877.4" - cell \dec_cr_in$183 \dec_cr_in - connect \MUL_BA \dec_MUL_BA - connect \MUL_BB \dec_MUL_BB - connect \MUL_BC \dec_MUL_BC - connect \MUL_BI \dec_MUL_BI - connect \MUL_BT \dec_MUL_BT - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108878.20-108887.4" - cell \dec_cr_out$185 \dec_cr_out - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_internal_op \dec_MUL_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108888.16-108894.4" - cell \dec_oe$182 \dec_oe - connect \MUL_OE \dec_MUL_OE - connect \MUL_internal_op \dec_MUL_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:108895.16-108900.4" - cell \dec_rc$181 \dec_rc - connect \MUL_Rc \dec_MUL_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \MUL__is_signed \dec_MUL_sgn - connect \MUL__is_32bit \dec_MUL_is_32b - connect \MUL__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_MUL_in2_sel - connect \MUL__fn_unit \dec_MUL_function_unit - connect \MUL__insn_type \dec_MUL_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_MUL_cr_out - connect \dec_cr_in_sel_in \dec_MUL_cr_in - connect \dec_oe_sel_in \dec_MUL_rc_sel - connect \dec_rc_sel_in \dec_MUL_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \MUL__insn \dec_opcode_in -end -attribute \src "libresoc.v:108924.1-109414.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" -attribute \generator "nMigen" -module \dec_SHIFT_ROT - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SHIFT_ROT__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \SHIFT_ROT__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SHIFT_ROT__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 12 \SHIFT_ROT__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \SHIFT_ROT__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 18 \SHIFT_ROT__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SHIFT_ROT__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \SHIFT_ROT__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \SHIFT_ROT__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \SHIFT_ROT__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \SHIFT_ROT__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \SHIFT_ROT__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \SHIFT_ROT__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \SHIFT_ROT__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 7 \SHIFT_ROT__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 6 \SHIFT_ROT__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \SHIFT_ROT__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 \dec_SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 \dec_SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 \dec_SHIFT_ROT_UI - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SHIFT_ROT_cr_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_cry_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_SHIFT_ROT_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 4 \dec_SHIFT_ROT_in2_sel - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \dec_SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_bi_imm_b_ok - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_cr_out_cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_oe_oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 19 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:109309.13-109342.4" - cell \dec$188 \dec - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out - connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a - connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109343.16-109354.4" - cell \dec_bi$195 \dec_bi - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \sel_in \dec_bi_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109355.19-109366.4" - cell \dec_cr_in$191 \dec_cr_in - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109367.20-109376.4" - cell \dec_cr_out$193 \dec_cr_out - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109377.16-109383.4" - cell \dec_oe$190 \dec_oe - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109384.16-109389.4" - cell \dec_rc$189 \dec_rc - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \sel_in \dec_rc_sel_in - end - connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a - connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] - connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] - connect \SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok - connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out - connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in - connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel - connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \SHIFT_ROT__insn \dec_opcode_in -end -attribute \src "libresoc.v:109418.1-109767.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" -attribute \generator "nMigen" -module \dec_SPR - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 3 \SPR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 4 \SPR__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SPR__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 5 \SPR__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 \dec_SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 \dec_SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire \dec_SPR_Rc - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SPR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 3 \dec_SPR_cr_out - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 12 \dec_SPR_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 \dec_SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" - wire \dec_SPR_is_32b - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 \dec_SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 \dec_XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 \dec_cr_in_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 \dec_cr_out_insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire \dec_cr_out_rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 \dec_cr_out_sel_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" - wire width 32 \dec_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec_rc_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" - wire width 32 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" - wire width 32 \insn_in$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 input 6 \raw_opcode_in - attribute \module_not_derived 1 - attribute \src "libresoc.v:109701.13-109722.4" - cell \dec$164 \dec - connect \SPR_BA \dec_SPR_BA - connect \SPR_BB \dec_SPR_BB - connect \SPR_BC \dec_SPR_BC - connect \SPR_BI \dec_SPR_BI - connect \SPR_BT \dec_SPR_BT - connect \SPR_FXM \dec_SPR_FXM - connect \SPR_OE \dec_SPR_OE - connect \SPR_Rc \dec_SPR_Rc - connect \SPR_cr_in \dec_SPR_cr_in - connect \SPR_cr_out \dec_SPR_cr_out - connect \SPR_function_unit \dec_SPR_function_unit - connect \SPR_internal_op \dec_SPR_internal_op - connect \SPR_is_32b \dec_SPR_is_32b - connect \SPR_rc_sel \dec_SPR_rc_sel - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \raw_opcode_in \raw_opcode_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109723.19-109734.4" - cell \dec_cr_in$167 \dec_cr_in - connect \SPR_BA \dec_SPR_BA - connect \SPR_BB \dec_SPR_BB - connect \SPR_BC \dec_SPR_BC - connect \SPR_BI \dec_SPR_BI - connect \SPR_BT \dec_SPR_BT - connect \SPR_FXM \dec_SPR_FXM - connect \SPR_internal_op \dec_SPR_internal_op - connect \X_BFA \dec_X_BFA - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109735.20-109743.4" - cell \dec_cr_out$169 \dec_cr_out - connect \SPR_FXM \dec_SPR_FXM - connect \SPR_internal_op \dec_SPR_internal_op - connect \XL_BT \dec_XL_BT - connect \X_BF \dec_X_BF - connect \insn_in \dec_cr_out_insn_in - connect \rc_in \dec_cr_out_rc_in - connect \sel_in \dec_cr_out_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109744.16-109748.4" - cell \dec_oe$166 \dec_oe - connect \SPR_OE \dec_SPR_OE - connect \SPR_internal_op \dec_SPR_internal_op - connect \sel_in \dec_oe_sel_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:109749.16-109753.4" - cell \dec_rc$165 \dec_rc - connect \SPR_Rc \dec_SPR_Rc - connect \rc \dec_rc_rc - connect \sel_in \dec_rc_sel_in - end - connect \SPR__is_32bit \dec_SPR_is_32b - connect \SPR__fn_unit \dec_SPR_function_unit - connect \SPR__insn_type \dec_SPR_internal_op - connect \dec_cr_out_rc_in \dec_rc_rc - connect \dec_cr_out_sel_in \dec_SPR_cr_out - connect \dec_cr_in_sel_in \dec_SPR_cr_in - connect \dec_oe_sel_in \dec_SPR_rc_sel - connect \dec_rc_sel_in \dec_SPR_rc_sel - connect \dec_cr_out_insn_in \dec_opcode_in - connect \dec_cr_in_insn_in \dec_opcode_in - connect \insn_in$1 \dec_opcode_in - connect \insn_in \dec_opcode_in - connect \SPR__insn \dec_opcode_in -end -attribute \src "libresoc.v:109771.1-110276.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" -attribute \generator "nMigen" -module \dec_a - attribute \src "libresoc.v:110205.3-110240.6" - wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:110205.3-110240.6" - wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:109772.7-109772.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:110173.3-110188.6" - wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:110189.3-110204.6" - wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:110241.3-110251.6" - wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:110263.3-110274.6" - wire width 10 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assign $2\fast_b[2:0] 3'000 - end - case - assign $1\fast_b[2:0] 3'000 - end - sync always - update \fast_b $0\fast_b[2:0] - end - attribute \src "libresoc.v:110617.3-110634.6" - process $proc$libresoc.v:110617$4313 - assign { } { } - assign { } { } - assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:110618.5-110618.29" - switch \initial - attribute \src "libresoc.v:110618.9-110618.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - switch { \XL_XO [5] \$7 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\fast_b_ok[0:0] 1'1 - case - assign $2\fast_b_ok[0:0] 1'0 - end - case - assign $1\fast_b_ok[0:0] 1'0 - end - sync always - update \fast_b_ok $0\fast_b_ok[0:0] - end - connect \$1 $eq$libresoc.v:110565$4306_Y - connect \$3 $not$libresoc.v:110566$4307_Y - connect \$5 $eq$libresoc.v:110567$4308_Y - connect \$7 $not$libresoc.v:110568$4309_Y -end -attribute \src "libresoc.v:110639.1-110892.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" -attribute \generator "nMigen" -module \dec_bi - attribute \src "libresoc.v:110866.3-110876.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:110877.3-110887.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:110728.3-110774.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:110775.3-110821.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:110640.7-110640.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:110855.3-110865.6" - wire width 26 $0\li[25:0] - attribute \src "libresoc.v:110822.3-110832.6" - wire width 16 $0\si[15:0] - attribute \src "libresoc.v:110833.3-110843.6" - wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:110844.3-110854.6" - wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:110866.3-110876.6" - wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:110877.3-110887.6" - wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:110728.3-110774.6" - wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:110775.3-110821.6" - wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:110855.3-110865.6" - wire width 26 $1\li[25:0] - attribute \src "libresoc.v:110822.3-110832.6" - wire width 16 $1\si[15:0] - attribute \src "libresoc.v:110833.3-110843.6" - wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:110844.3-110854.6" - wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:110718.17-110718.104" - wire width 64 $extend$libresoc.v:110718$4315_Y - attribute \src "libresoc.v:110719.18-110719.107" - wire width 64 $extend$libresoc.v:110719$4317_Y - attribute \src "libresoc.v:110722.17-110722.104" - wire width 64 $extend$libresoc.v:110722$4321_Y - attribute \src "libresoc.v:110726.17-110726.102" - wire width 64 $extend$libresoc.v:110726$4326_Y - attribute \src "libresoc.v:110718.17-110718.104" - wire width 64 $pos$libresoc.v:110718$4316_Y - attribute \src "libresoc.v:110719.18-110719.107" - wire width 64 $pos$libresoc.v:110719$4318_Y - attribute \src "libresoc.v:110722.17-110722.104" - wire width 64 $pos$libresoc.v:110722$4322_Y - attribute \src "libresoc.v:110726.17-110726.102" - wire width 64 $pos$libresoc.v:110726$4327_Y - attribute \src "libresoc.v:110720.18-110720.114" - wire width 47 $sshl$libresoc.v:110720$4319_Y - attribute \src "libresoc.v:110721.18-110721.113" - wire width 27 $sshl$libresoc.v:110721$4320_Y - attribute \src "libresoc.v:110723.18-110723.113" - wire width 17 $sshl$libresoc.v:110723$4323_Y - attribute \src "libresoc.v:110724.18-110724.113" - wire width 17 $sshl$libresoc.v:110724$4324_Y - attribute \src "libresoc.v:110725.17-110725.109" - wire width 47 $sshl$libresoc.v:110725$4325_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 8 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 9 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 input 7 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 3 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 4 \ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:110640.7-110640.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:110718$4315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \ALU_sh - connect \Y $extend$libresoc.v:110718$4315_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:110719$4317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:110719$4317_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:110722$4321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \ALU_UI - connect \Y $extend$libresoc.v:110722$4321_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:110726$4326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:110726$4326_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:110718$4316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110718$4315_Y - connect \Y $pos$libresoc.v:110718$4316_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:110719$4318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110719$4317_Y - connect \Y $pos$libresoc.v:110719$4318_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:110722$4322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110722$4321_Y - connect \Y $pos$libresoc.v:110722$4322_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:110726$4327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:110726$4326_Y - connect \Y $pos$libresoc.v:110726$4327_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:110720$4319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ALU_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:110720$4319_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:110721$4320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \ALU_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:110721$4320_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:110723$4323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \ALU_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:110723$4323_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:110724$4324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \ALU_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:110724$4324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:110725$4325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:110725$4325_Y - end - attribute \src "libresoc.v:110640.7-110640.20" - process $proc$libresoc.v:110640$4336 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:110728.3-110774.6" - process $proc$libresoc.v:110728$4328 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:110729.5-110729.29" - switch \initial - attribute \src "libresoc.v:110729.9-110729.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:110775.3-110821.6" - process $proc$libresoc.v:110775$4329 - assign { } { } - assign { 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} - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:111032.3-111078.6" - process $proc$libresoc.v:111032$4351 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111033.5-111033.29" - switch \initial - attribute \src "libresoc.v:111033.9-111033.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "libresoc.v:111079.3-111089.6" - process $proc$libresoc.v:111079$4352 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111080.5-111080.29" - switch \initial - attribute \src "libresoc.v:111080.9-111080.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" 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- connect \A $extend$libresoc.v:111232$4359_Y - connect \Y $pos$libresoc.v:111232$4360_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111233$4362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111233$4361_Y - connect \Y $pos$libresoc.v:111233$4362_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111236$4366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111236$4365_Y - connect \Y $pos$libresoc.v:111236$4366_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:111240$4371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111240$4370_Y - connect \Y $pos$libresoc.v:111240$4371_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:111234$4363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \LOGICAL_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111234$4363_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:111235$4364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LOGICAL_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:111235$4364_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:111237$4367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LOGICAL_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:111237$4367_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:111238$4368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LOGICAL_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:111238$4368_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:111239$4369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111239$4369_Y - end - attribute \src "libresoc.v:111154.7-111154.20" - process $proc$libresoc.v:111154$4380 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:111242.3-111288.6" - process $proc$libresoc.v:111242$4372 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111243.5-111243.29" - switch \initial - attribute \src "libresoc.v:111243.9-111243.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:111289.3-111335.6" - process $proc$libresoc.v:111289$4373 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111290.5-111290.29" - switch \initial - attribute \src "libresoc.v:111290.9-111290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "libresoc.v:111336.3-111346.6" - process $proc$libresoc.v:111336$4374 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111337.5-111337.29" - switch \initial - attribute \src "libresoc.v:111337.9-111337.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \LOGICAL_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "libresoc.v:111347.3-111357.6" - process $proc$libresoc.v:111347$4375 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111348.5-111348.29" - switch \initial - attribute \src "libresoc.v:111348.9-111348.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "libresoc.v:111358.3-111368.6" - process $proc$libresoc.v:111358$4376 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111359.5-111359.29" - switch \initial - attribute \src "libresoc.v:111359.9-111359.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \LOGICAL_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "libresoc.v:111369.3-111379.6" - process $proc$libresoc.v:111369$4377 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111370.5-111370.29" - switch \initial - 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64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "libresoc.v:111410.1-111663.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" -attribute \generator "nMigen" -module \dec_bi$179 - attribute \src "libresoc.v:111637.3-111647.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111648.3-111658.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111499.3-111545.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111546.3-111592.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:111411.7-111411.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:111626.3-111636.6" - wire width 26 $0\li[25:0] - attribute \src "libresoc.v:111593.3-111603.6" - wire width 16 $0\si[15:0] - attribute \src "libresoc.v:111604.3-111614.6" - wire width 32 $0\si_hi[31:0] - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - wire width 47 \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 8 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 9 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 input 7 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 3 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 4 \DIV_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:111411.7-111411.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111489$4381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \DIV_sh - connect \Y $extend$libresoc.v:111489$4381_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111490$4383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:111490$4383_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111493$4387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \DIV_UI - connect \Y $extend$libresoc.v:111493$4387_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:111497$4392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:111497$4392_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111489$4382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111489$4381_Y - connect \Y $pos$libresoc.v:111489$4382_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111490$4384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111490$4383_Y - connect \Y $pos$libresoc.v:111490$4384_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111493$4388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111493$4387_Y - connect \Y $pos$libresoc.v:111493$4388_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:111497$4393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111497$4392_Y - connect \Y $pos$libresoc.v:111497$4393_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:111491$4385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \DIV_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111491$4385_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:111492$4386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \DIV_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:111492$4386_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:111494$4389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DIV_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:111494$4389_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:111495$4390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DIV_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:111495$4390_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:111496$4391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111496$4391_Y - end - attribute \src "libresoc.v:111411.7-111411.20" - process $proc$libresoc.v:111411$4402 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:111499.3-111545.6" - process $proc$libresoc.v:111499$4394 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111500.5-111500.29" - switch \initial - attribute \src "libresoc.v:111500.9-111500.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:111546.3-111592.6" - process $proc$libresoc.v:111546$4395 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111547.5-111547.29" - switch \initial - attribute \src "libresoc.v:111547.9-111547.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "libresoc.v:111593.3-111603.6" - process $proc$libresoc.v:111593$4396 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111594.5-111594.29" - switch \initial - attribute \src "libresoc.v:111594.9-111594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \DIV_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "libresoc.v:111604.3-111614.6" - process $proc$libresoc.v:111604$4397 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111605.5-111605.29" - switch \initial - attribute \src "libresoc.v:111605.9-111605.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "libresoc.v:111615.3-111625.6" - process $proc$libresoc.v:111615$4398 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111616.5-111616.29" - switch \initial - attribute \src "libresoc.v:111616.9-111616.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \DIV_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "libresoc.v:111626.3-111636.6" - process $proc$libresoc.v:111626$4399 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111627.5-111627.29" - switch \initial - attribute \src "libresoc.v:111627.9-111627.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "libresoc.v:111637.3-111647.6" - process $proc$libresoc.v:111637$4400 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:111638.5-111638.29" - switch \initial - attribute \src "libresoc.v:111638.9-111638.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "libresoc.v:111648.3-111658.6" - process $proc$libresoc.v:111648$4401 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:111649.5-111649.29" - switch \initial - attribute \src "libresoc.v:111649.9-111649.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$libresoc.v:111489$4382_Y - connect \$11 $pos$libresoc.v:111490$4384_Y - connect \$14 $sshl$libresoc.v:111491$4385_Y - connect \$17 $sshl$libresoc.v:111492$4386_Y - connect \$1 $pos$libresoc.v:111493$4388_Y - connect \$20 $sshl$libresoc.v:111494$4389_Y - connect \$23 $sshl$libresoc.v:111495$4390_Y - connect \$4 $sshl$libresoc.v:111496$4391_Y - connect \$3 $pos$libresoc.v:111497$4393_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "libresoc.v:111667.1-111920.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" -attribute \generator "nMigen" -module \dec_bi$187 - attribute \src "libresoc.v:111894.3-111904.6" - wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:111905.3-111915.6" - wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:111756.3-111802.6" - wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:111803.3-111849.6" - wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:111668.7-111668.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:111883.3-111893.6" - wire width 26 $0\li[25:0] - attribute \src "libresoc.v:111850.3-111860.6" - wire width 16 $0\si[15:0] - attribute \src "libresoc.v:111861.3-111871.6" - wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:111872.3-111882.6" - wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:111894.3-111904.6" - wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:111905.3-111915.6" - wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:111756.3-111802.6" - wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:111803.3-111849.6" - wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111883.3-111893.6" - wire width 26 $1\li[25:0] - attribute \src "libresoc.v:111850.3-111860.6" - wire width 16 $1\si[15:0] - attribute \src "libresoc.v:111861.3-111871.6" - wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:111872.3-111882.6" - wire width 16 $1\ui[15:0] - attribute \src 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wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 8 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 9 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 input 7 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 3 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 4 \MUL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:111668.7-111668.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111746$4403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \MUL_sh - connect \Y $extend$libresoc.v:111746$4403_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111747$4405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:111747$4405_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:111750$4409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \MUL_UI - connect \Y $extend$libresoc.v:111750$4409_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:111754$4414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:111754$4414_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111746$4404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111746$4403_Y - connect \Y $pos$libresoc.v:111746$4404_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111747$4406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111747$4405_Y - connect \Y $pos$libresoc.v:111747$4406_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:111750$4410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111750$4409_Y - connect \Y $pos$libresoc.v:111750$4410_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:111754$4415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:111754$4414_Y - connect \Y $pos$libresoc.v:111754$4415_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:111748$4407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \MUL_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111748$4407_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:111749$4408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \MUL_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:111749$4408_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:111751$4411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \MUL_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:111751$4411_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:111752$4412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \MUL_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:111752$4412_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:111753$4413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:111753$4413_Y - end - attribute \src "libresoc.v:111668.7-111668.20" - process $proc$libresoc.v:111668$4424 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:111756.3-111802.6" - process $proc$libresoc.v:111756$4416 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:111757.5-111757.29" - switch \initial - attribute \src "libresoc.v:111757.9-111757.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:111803.3-111849.6" - process $proc$libresoc.v:111803$4417 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:111804.5-111804.29" - switch \initial - attribute \src "libresoc.v:111804.9-111804.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "libresoc.v:111850.3-111860.6" - process $proc$libresoc.v:111850$4418 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:111851.5-111851.29" - switch \initial - attribute \src "libresoc.v:111851.9-111851.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \MUL_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "libresoc.v:111861.3-111871.6" - process $proc$libresoc.v:111861$4419 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:111862.5-111862.29" - switch \initial - attribute \src "libresoc.v:111862.9-111862.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "libresoc.v:111872.3-111882.6" - process $proc$libresoc.v:111872$4420 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:111873.5-111873.29" - switch \initial - attribute \src "libresoc.v:111873.9-111873.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \MUL_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "libresoc.v:111883.3-111893.6" - process $proc$libresoc.v:111883$4421 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:111884.5-111884.29" - switch \initial - attribute \src "libresoc.v:111884.9-111884.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "libresoc.v:111894.3-111904.6" - process $proc$libresoc.v:111894$4422 - assign { } { } - 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - wire width 27 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - wire width 17 \$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - wire width 17 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 64 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 47 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:262" - wire width 64 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 64 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 8 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 14 input 9 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 24 input 7 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 3 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 16 input 4 \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \imm_b_ok - attribute \src "libresoc.v:111925.7-111925.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247" - wire width 26 \li - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219" - wire width 4 input 10 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:112003$4425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:112003$4425_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:112004$4427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:112004$4427_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:112007$4431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:112007$4431_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $extend$libresoc.v:112011$4436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A \$4 - connect \Y $extend$libresoc.v:112011$4436_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:112003$4426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112003$4425_Y - connect \Y $pos$libresoc.v:112003$4426_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:112004$4428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112004$4427_Y - connect \Y $pos$libresoc.v:112004$4428_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:112007$4432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112007$4431_Y - connect \Y $pos$libresoc.v:112007$4432_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $pos $pos$libresoc.v:112011$4437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:112011$4436_Y - connect \Y $pos$libresoc.v:112011$4437_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - cell $sshl $sshl$libresoc.v:112005$4429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \SHIFT_ROT_SI - connect \B 5'10000 - connect \Y $sshl$libresoc.v:112005$4429_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - cell $sshl $sshl$libresoc.v:112006$4430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \SHIFT_ROT_LI - connect \B 2'10 - connect \Y $sshl$libresoc.v:112006$4430_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - cell $sshl $sshl$libresoc.v:112008$4433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_BD - connect \B 2'10 - connect \Y $sshl$libresoc.v:112008$4433_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - cell $sshl $sshl$libresoc.v:112009$4434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_DS - connect \B 2'10 - connect \Y $sshl$libresoc.v:112009$4434_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - cell $sshl $sshl$libresoc.v:112010$4435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $sshl$libresoc.v:112010$4435_Y - end - attribute \src "libresoc.v:111925.7-111925.20" - process $proc$libresoc.v:111925$4446 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:112013.3-112059.6" - process $proc$libresoc.v:112013$4438 - assign { } { } - assign { } { } - assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:112014.5-112014.29" - switch \initial - attribute \src "libresoc.v:112014.9-112014.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b[63:0] \$1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd 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"libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b[63:0] \$3 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b[63:0] \$7 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b[63:0] \$9 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b[63:0] \$11 - case - assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \imm_b $0\imm_b[63:0] - end - attribute \src "libresoc.v:112317.3-112363.6" - process $proc$libresoc.v:112317$4461 - assign { } { } - assign { } { } - assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:112318.5-112318.29" - switch \initial - attribute \src "libresoc.v:112318.9-112318.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1001 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1010 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 4'1011 - assign { } { } - assign $1\imm_b_ok[0:0] 1'1 - case - assign $1\imm_b_ok[0:0] 1'0 - end - sync always - update \imm_b_ok $0\imm_b_ok[0:0] - end - attribute \src "libresoc.v:112364.3-112374.6" - process $proc$libresoc.v:112364$4462 - assign { } { } - assign { } { } - assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:112365.5-112365.29" - switch \initial - attribute \src "libresoc.v:112365.9-112365.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0011 - assign { } { } - assign $1\si[15:0] \LDST_SI - case - assign $1\si[15:0] 16'0000000000000000 - end - sync always - update \si $0\si[15:0] - end - attribute \src "libresoc.v:112375.3-112385.6" - process $proc$libresoc.v:112375$4463 - assign { } { } - assign { } { } - assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:112376.5-112376.29" - switch \initial - attribute \src "libresoc.v:112376.9-112376.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0101 - assign { } { } - assign $1\si_hi[31:0] \$13 [31:0] - case - assign $1\si_hi[31:0] 0 - end - sync always - update \si_hi $0\si_hi[31:0] - end - attribute \src "libresoc.v:112386.3-112396.6" - process $proc$libresoc.v:112386$4464 - assign { } { } - assign { } { } - assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:112387.5-112387.29" - switch \initial - attribute \src "libresoc.v:112387.9-112387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $1\ui[15:0] \LDST_UI - case - assign $1\ui[15:0] 16'0000000000000000 - end - sync always - update \ui $0\ui[15:0] - end - attribute \src "libresoc.v:112397.3-112407.6" - process $proc$libresoc.v:112397$4465 - assign { } { } - assign { } { } - assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:112398.5-112398.29" - switch \initial - attribute \src "libresoc.v:112398.9-112398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0110 - assign { } { } - assign $1\li[25:0] \$16 [25:0] - case - assign $1\li[25:0] 26'00000000000000000000000000 - end - sync always - update \li $0\li[25:0] - end - attribute \src "libresoc.v:112408.3-112418.6" - process $proc$libresoc.v:112408$4466 - assign { } { } - assign { } { } - assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:112409.5-112409.29" - switch \initial - attribute \src "libresoc.v:112409.9-112409.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'0111 - assign { } { } - assign $1\bd[15:0] \$19 [15:0] - case - assign $1\bd[15:0] 16'0000000000000000 - end - sync always - update \bd $0\bd[15:0] - end - attribute \src "libresoc.v:112419.3-112429.6" - process $proc$libresoc.v:112419$4467 - assign { } { } - assign { } { } - assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:112420.5-112420.29" - switch \initial - attribute \src "libresoc.v:112420.9-112420.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:227" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $1\ds[15:0] \$22 [15:0] - case - assign $1\ds[15:0] 16'0000000000000000 - end - sync always - update \ds $0\ds[15:0] - end - connect \$9 $pos$libresoc.v:112260$4448_Y - connect \$11 $pos$libresoc.v:112261$4450_Y - connect \$14 $sshl$libresoc.v:112262$4451_Y - connect \$17 $sshl$libresoc.v:112263$4452_Y - connect \$1 $pos$libresoc.v:112264$4454_Y - connect \$20 $sshl$libresoc.v:112265$4455_Y - connect \$23 $sshl$libresoc.v:112266$4456_Y - connect \$4 $sshl$libresoc.v:112267$4457_Y - connect \$3 $pos$libresoc.v:112268$4459_Y - connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 - connect \$13 \$14 - connect \$16 \$17 - connect \$19 \$20 - connect \$22 \$23 -end -attribute \src "libresoc.v:112438.1-112486.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" -attribute \generator "nMigen" -module \dec_c - attribute \src "libresoc.v:112439.7-112439.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:112456.3-112470.6" - wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:112471.3-112485.6" - wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:112456.3-112470.6" - wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:112471.3-112485.6" - wire $1\reg_c_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \RS - attribute \src "libresoc.v:112439.7-112439.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 1 \reg_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \reg_c_ok - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:112439.7-112439.20" - process $proc$libresoc.v:112439$4471 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:112456.3-112470.6" - process $proc$libresoc.v:112456$4469 - assign { } { } - assign { } { } - assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:112457.5-112457.29" - switch \initial - attribute \src "libresoc.v:112457.9-112457.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c[4:0] \RB - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c[4:0] \RS - case - assign $1\reg_c[4:0] 5'00000 - end - sync always - update \reg_c $0\reg_c[4:0] - end - attribute \src "libresoc.v:112471.3-112485.6" - process $proc$libresoc.v:112471$4470 - assign { } { } - assign { } { } - assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:112472.5-112472.29" - switch \initial - attribute \src "libresoc.v:112472.9-112472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_c_ok[0:0] 1'1 - case - assign $1\reg_c_ok[0:0] 1'0 - end - sync always - update \reg_c_ok $0\reg_c_ok[0:0] - end -end -attribute \src "libresoc.v:112490.1-112787.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in - attribute \src "libresoc.v:112681.3-112707.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:112708.3-112718.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112659.3-112669.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112719.3-112729.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112730.3-112740.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112632.3-112658.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112768.3-112786.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:112670.3-112680.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112491.7-112491.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:112741.3-112751.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:112752.3-112767.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:112681.3-112707.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112708.3-112718.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112659.3-112669.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112719.3-112729.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:112730.3-112740.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112632.3-112658.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112768.3-112786.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112670.3-112680.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112741.3-112751.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:112752.3-112767.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:112768.3-112786.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:112752.3-112767.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112625.17-112625.112" - wire $and$libresoc.v:112625$4473_Y - attribute \src "libresoc.v:112627.17-112627.112" - wire $and$libresoc.v:112627$4475_Y - attribute \src "libresoc.v:112624.17-112624.121" - wire $eq$libresoc.v:112624$4472_Y - attribute \src "libresoc.v:112626.17-112626.121" - wire $eq$libresoc.v:112626$4474_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \ALU_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute 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"OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 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"libresoc.v:112491.7-112491.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112625$4473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:112625$4473_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112627$4475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:112627$4475_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112624$4472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112624$4472_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112626$4474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112626$4474_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:112628.9-112631.4" - cell \ppick \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:112491.7-112491.20" - process $proc$libresoc.v:112491$4486 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:112632.3-112658.6" - process $proc$libresoc.v:112632$4476 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112633.5-112633.29" - switch \initial - attribute \src "libresoc.v:112633.9-112633.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:112659.3-112669.6" - process $proc$libresoc.v:112659$4477 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112660.5-112660.29" - switch \initial - attribute \src "libresoc.v:112660.9-112660.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:112670.3-112680.6" - process $proc$libresoc.v:112670$4478 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112671.5-112671.29" - switch \initial - attribute \src "libresoc.v:112671.9-112671.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:112681.3-112707.6" - process $proc$libresoc.v:112681$4479 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112682.5-112682.29" - switch \initial - attribute \src "libresoc.v:112682.9-112682.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \ALU_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:112624$4472_Y - connect \$3 $and$libresoc.v:112625$4473_Y - connect \$5 $eq$libresoc.v:112626$4474_Y - connect \$7 $and$libresoc.v:112627$4475_Y -end -attribute \src "libresoc.v:112791.1-113088.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$143 - attribute \src "libresoc.v:112982.3-113008.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113009.3-113019.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:112960.3-112970.6" - wire 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"libresoc.v:113031.3-113041.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:112933.3-112959.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113069.3-113087.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:112971.3-112981.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113042.3-113052.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:113053.3-113068.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113069.3-113087.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113053.3-113068.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:112926.17-112926.112" - wire $and$libresoc.v:112926$4488_Y - attribute \src "libresoc.v:112928.17-112928.112" - wire $and$libresoc.v:112928$4490_Y - attribute \src "libresoc.v:112925.17-112925.120" - wire $eq$libresoc.v:112925$4487_Y - attribute \src "libresoc.v:112927.17-112927.120" - wire $eq$libresoc.v:112927$4489_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \CR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:112792.7-112792.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112926$4488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:112926$4488_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:112928$4490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:112928$4490_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112925$4487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112925$4487_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:112927$4489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:112927$4489_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:112929.15-112932.4" - cell \ppick$144 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:112792.7-112792.20" - process $proc$libresoc.v:112792$4501 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:112933.3-112959.6" - process $proc$libresoc.v:112933$4491 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:112934.5-112934.29" - switch \initial - attribute \src "libresoc.v:112934.9-112934.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:112960.3-112970.6" - process $proc$libresoc.v:112960$4492 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:112961.5-112961.29" - switch \initial - attribute \src "libresoc.v:112961.9-112961.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:112971.3-112981.6" - process $proc$libresoc.v:112971$4493 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:112972.5-112972.29" - switch \initial - attribute \src "libresoc.v:112972.9-112972.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:112982.3-113008.6" - process $proc$libresoc.v:112982$4494 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:112983.5-112983.29" - switch \initial - attribute \src "libresoc.v:112983.9-112983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \CR_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:113009.3-113019.6" - process $proc$libresoc.v:113009$4495 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113010.5-113010.29" - switch \initial - attribute \src "libresoc.v:113010.9-113010.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:113020.3-113030.6" - process $proc$libresoc.v:113020$4496 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113021.5-113021.29" - switch \initial - attribute \src "libresoc.v:113021.9-113021.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:113031.3-113041.6" - process $proc$libresoc.v:113031$4497 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113032.5-113032.29" - switch \initial - attribute \src "libresoc.v:113032.9-113032.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:113042.3-113052.6" - process $proc$libresoc.v:113042$4498 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113043.5-113043.29" - switch \initial - attribute \src "libresoc.v:113043.9-113043.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:113053.3-113068.6" - process $proc$libresoc.v:113053$4499 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113054.5-113054.29" - switch \initial - attribute \src "libresoc.v:113054.9-113054.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \CR_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:113069.3-113087.6" - process $proc$libresoc.v:113069$4500 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113070.5-113070.29" - switch \initial - attribute \src "libresoc.v:113070.9-113070.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:112925$4487_Y - connect \$3 $and$libresoc.v:112926$4488_Y - connect \$5 $eq$libresoc.v:112927$4489_Y - connect \$7 $and$libresoc.v:112928$4490_Y -end -attribute \src "libresoc.v:113092.1-113389.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$150 - attribute \src "libresoc.v:113283.3-113309.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113310.3-113320.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113261.3-113271.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113321.3-113331.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113332.3-113342.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113234.3-113260.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113370.3-113388.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113272.3-113282.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113093.7-113093.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:113343.3-113353.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:113354.3-113369.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113283.3-113309.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113310.3-113320.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113261.3-113271.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113321.3-113331.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113332.3-113342.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113234.3-113260.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113370.3-113388.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113272.3-113282.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113343.3-113353.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:113354.3-113369.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113370.3-113388.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113354.3-113369.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113227.17-113227.112" - wire $and$libresoc.v:113227$4503_Y - attribute \src "libresoc.v:113229.17-113229.112" - wire $and$libresoc.v:113229$4505_Y - attribute \src "libresoc.v:113226.17-113226.124" - wire $eq$libresoc.v:113226$4502_Y - attribute \src "libresoc.v:113228.17-113228.124" - wire $eq$libresoc.v:113228$4504_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \BRANCH_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:113093.7-113093.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113227$4503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:113227$4503_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113229$4505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:113229$4505_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113226$4502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113226$4502_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113228$4504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113228$4504_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:113230.15-113233.4" - cell \ppick$151 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:113093.7-113093.20" - process $proc$libresoc.v:113093$4516 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:113234.3-113260.6" - process $proc$libresoc.v:113234$4506 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113235.5-113235.29" - switch \initial - attribute \src "libresoc.v:113235.9-113235.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:113261.3-113271.6" - process $proc$libresoc.v:113261$4507 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113262.5-113262.29" - switch \initial - attribute \src "libresoc.v:113262.9-113262.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:113272.3-113282.6" - process $proc$libresoc.v:113272$4508 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113273.5-113273.29" - switch \initial - attribute \src "libresoc.v:113273.9-113273.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:113283.3-113309.6" - process $proc$libresoc.v:113283$4509 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113284.5-113284.29" - switch \initial - attribute \src "libresoc.v:113284.9-113284.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:113310.3-113320.6" - process $proc$libresoc.v:113310$4510 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113311.5-113311.29" - switch \initial - attribute \src "libresoc.v:113311.9-113311.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:113321.3-113331.6" - process $proc$libresoc.v:113321$4511 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113322.5-113322.29" - switch \initial - attribute \src "libresoc.v:113322.9-113322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:113332.3-113342.6" - process $proc$libresoc.v:113332$4512 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113333.5-113333.29" - switch \initial - attribute \src "libresoc.v:113333.9-113333.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:113343.3-113353.6" - process $proc$libresoc.v:113343$4513 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113344.5-113344.29" - switch \initial - attribute \src "libresoc.v:113344.9-113344.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:113354.3-113369.6" - process $proc$libresoc.v:113354$4514 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113355.5-113355.29" - switch \initial - attribute \src "libresoc.v:113355.9-113355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \BRANCH_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:113370.3-113388.6" - process $proc$libresoc.v:113370$4515 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113371.5-113371.29" - switch \initial - attribute \src "libresoc.v:113371.9-113371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:113226$4502_Y - connect \$3 $and$libresoc.v:113227$4503_Y - connect \$5 $eq$libresoc.v:113228$4504_Y - connect \$7 $and$libresoc.v:113229$4505_Y -end -attribute \src "libresoc.v:113393.1-113690.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$158 - attribute \src "libresoc.v:113584.3-113610.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113611.3-113621.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113562.3-113572.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113622.3-113632.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113633.3-113643.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute 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$1\cr_fxm[7:0] - attribute \src "libresoc.v:113573.3-113583.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113644.3-113654.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:113655.3-113670.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113671.3-113689.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113655.3-113670.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113528.17-113528.112" - wire $and$libresoc.v:113528$4518_Y - attribute \src "libresoc.v:113530.17-113530.112" - wire $and$libresoc.v:113530$4520_Y - attribute \src "libresoc.v:113527.17-113527.125" - wire $eq$libresoc.v:113527$4517_Y - attribute \src "libresoc.v:113529.17-113529.125" - wire $eq$libresoc.v:113529$4519_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \LOGICAL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:113394.7-113394.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113528$4518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:113528$4518_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113530$4520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:113530$4520_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113527$4517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113527$4517_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113529$4519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113529$4519_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:113531.15-113534.4" - cell \ppick$159 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:113394.7-113394.20" - process $proc$libresoc.v:113394$4531 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:113535.3-113561.6" - process $proc$libresoc.v:113535$4521 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113536.5-113536.29" - switch \initial - attribute \src "libresoc.v:113536.9-113536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:113562.3-113572.6" - process $proc$libresoc.v:113562$4522 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113563.5-113563.29" - switch \initial - attribute \src "libresoc.v:113563.9-113563.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:113573.3-113583.6" - process $proc$libresoc.v:113573$4523 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113574.5-113574.29" - switch \initial - attribute \src "libresoc.v:113574.9-113574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:113584.3-113610.6" - process $proc$libresoc.v:113584$4524 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113585.5-113585.29" - switch \initial - attribute \src "libresoc.v:113585.9-113585.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:113611.3-113621.6" - process $proc$libresoc.v:113611$4525 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113612.5-113612.29" - switch \initial - attribute \src "libresoc.v:113612.9-113612.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:113622.3-113632.6" - process $proc$libresoc.v:113622$4526 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113623.5-113623.29" - switch \initial - attribute \src "libresoc.v:113623.9-113623.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:113633.3-113643.6" - process $proc$libresoc.v:113633$4527 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113634.5-113634.29" - switch \initial - attribute \src "libresoc.v:113634.9-113634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:113644.3-113654.6" - process $proc$libresoc.v:113644$4528 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113645.5-113645.29" - switch \initial - attribute \src "libresoc.v:113645.9-113645.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:113655.3-113670.6" - process $proc$libresoc.v:113655$4529 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113656.5-113656.29" - switch \initial - attribute \src "libresoc.v:113656.9-113656.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \LOGICAL_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:113671.3-113689.6" - process $proc$libresoc.v:113671$4530 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113672.5-113672.29" - switch \initial - attribute \src "libresoc.v:113672.9-113672.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:113527$4517_Y - connect \$3 $and$libresoc.v:113528$4518_Y - connect \$5 $eq$libresoc.v:113529$4519_Y - connect \$7 $and$libresoc.v:113530$4520_Y -end -attribute \src "libresoc.v:113694.1-113991.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$167 - attribute \src "libresoc.v:113885.3-113911.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:113912.3-113922.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113863.3-113873.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113923.3-113933.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113934.3-113944.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113836.3-113862.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113972.3-113990.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:113874.3-113884.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113695.7-113695.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:113945.3-113955.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:113956.3-113971.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:113885.3-113911.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113912.3-113922.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113863.3-113873.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113923.3-113933.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113934.3-113944.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113836.3-113862.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113972.3-113990.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:113874.3-113884.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113945.3-113955.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:113956.3-113971.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:113972.3-113990.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:113956.3-113971.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:113829.17-113829.112" - wire $and$libresoc.v:113829$4533_Y - attribute \src "libresoc.v:113831.17-113831.112" - wire $and$libresoc.v:113831$4535_Y - attribute \src "libresoc.v:113828.17-113828.121" - wire $eq$libresoc.v:113828$4532_Y - attribute \src "libresoc.v:113830.17-113830.121" - wire $eq$libresoc.v:113830$4534_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \SPR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:113695.7-113695.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113829$4533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:113829$4533_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:113831$4535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:113831$4535_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113828$4532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113828$4532_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:113830$4534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:113830$4534_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:113832.15-113835.4" - cell \ppick$168 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:113695.7-113695.20" - process $proc$libresoc.v:113695$4546 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:113836.3-113862.6" - process $proc$libresoc.v:113836$4536 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:113837.5-113837.29" - switch \initial - attribute \src "libresoc.v:113837.9-113837.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:113863.3-113873.6" - process $proc$libresoc.v:113863$4537 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:113864.5-113864.29" - switch \initial - attribute \src "libresoc.v:113864.9-113864.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:113874.3-113884.6" - process $proc$libresoc.v:113874$4538 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113875.5-113875.29" - switch \initial - attribute \src "libresoc.v:113875.9-113875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:113885.3-113911.6" - process $proc$libresoc.v:113885$4539 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:113886.5-113886.29" - switch \initial - attribute \src "libresoc.v:113886.9-113886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \SPR_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:113912.3-113922.6" - process $proc$libresoc.v:113912$4540 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:113913.5-113913.29" - switch \initial - attribute \src "libresoc.v:113913.9-113913.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:113923.3-113933.6" - process $proc$libresoc.v:113923$4541 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:113924.5-113924.29" - switch \initial - attribute \src "libresoc.v:113924.9-113924.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:113934.3-113944.6" - process $proc$libresoc.v:113934$4542 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:113935.5-113935.29" - switch \initial - attribute \src "libresoc.v:113935.9-113935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:113945.3-113955.6" - process $proc$libresoc.v:113945$4543 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:113946.5-113946.29" - switch \initial - attribute \src "libresoc.v:113946.9-113946.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:113956.3-113971.6" - process $proc$libresoc.v:113956$4544 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:113957.5-113957.29" - switch \initial - attribute \src "libresoc.v:113957.9-113957.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \SPR_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:113972.3-113990.6" - process $proc$libresoc.v:113972$4545 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:113973.5-113973.29" - switch \initial - attribute \src "libresoc.v:113973.9-113973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:113828$4532_Y - connect \$3 $and$libresoc.v:113829$4533_Y - connect \$5 $eq$libresoc.v:113830$4534_Y - connect \$7 $and$libresoc.v:113831$4535_Y -end -attribute \src "libresoc.v:113995.1-114292.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$174 - attribute \src "libresoc.v:114186.3-114212.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114213.3-114223.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114164.3-114174.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114224.3-114234.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114235.3-114245.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114137.3-114163.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114273.3-114291.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:114175.3-114185.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:113996.7-113996.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:114246.3-114256.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:114257.3-114272.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:114186.3-114212.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114213.3-114223.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114164.3-114174.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114224.3-114234.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114235.3-114245.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114137.3-114163.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114273.3-114291.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:114175.3-114185.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114246.3-114256.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:114257.3-114272.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:114273.3-114291.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:114257.3-114272.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:114130.17-114130.112" - wire $and$libresoc.v:114130$4548_Y - attribute \src "libresoc.v:114132.17-114132.112" - wire $and$libresoc.v:114132$4550_Y - attribute \src "libresoc.v:114129.17-114129.121" - wire $eq$libresoc.v:114129$4547_Y - attribute \src "libresoc.v:114131.17-114131.121" - wire $eq$libresoc.v:114131$4549_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \DIV_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:113996.7-113996.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114130$4548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:114130$4548_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114132$4550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:114132$4550_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114129$4547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114129$4547_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114131$4549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114131$4549_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:114133.15-114136.4" - cell \ppick$175 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:113996.7-113996.20" - process $proc$libresoc.v:113996$4561 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:114137.3-114163.6" - process $proc$libresoc.v:114137$4551 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114138.5-114138.29" - switch \initial - attribute \src "libresoc.v:114138.9-114138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:114164.3-114174.6" - process $proc$libresoc.v:114164$4552 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114165.5-114165.29" - switch \initial - attribute \src "libresoc.v:114165.9-114165.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:114175.3-114185.6" - process $proc$libresoc.v:114175$4553 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114176.5-114176.29" - switch \initial - attribute \src "libresoc.v:114176.9-114176.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:114186.3-114212.6" - process $proc$libresoc.v:114186$4554 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - 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process $proc$libresoc.v:114465$4567 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114466.5-114466.29" - switch \initial - attribute \src "libresoc.v:114466.9-114466.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:114476.3-114486.6" - process $proc$libresoc.v:114476$4568 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114477.5-114477.29" - switch \initial - attribute \src "libresoc.v:114477.9-114477.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:114487.3-114513.6" - process $proc$libresoc.v:114487$4569 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114488.5-114488.29" - switch \initial - attribute \src "libresoc.v:114488.9-114488.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \MUL_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:114514.3-114524.6" - process $proc$libresoc.v:114514$4570 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114515.5-114515.29" - switch \initial - attribute \src "libresoc.v:114515.9-114515.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:114525.3-114535.6" - process $proc$libresoc.v:114525$4571 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114526.5-114526.29" - switch \initial - attribute \src "libresoc.v:114526.9-114526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync always - update \cr_bitfield_o $0\cr_bitfield_o[2:0] - end - attribute \src "libresoc.v:114536.3-114546.6" - process $proc$libresoc.v:114536$4572 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114537.5-114537.29" - switch \initial - attribute \src "libresoc.v:114537.9-114537.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o_ok[0:0] 1'1 - case - assign $1\cr_bitfield_o_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] - end - attribute \src "libresoc.v:114547.3-114557.6" - process $proc$libresoc.v:114547$4573 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:114548.5-114548.29" - switch \initial - attribute \src "libresoc.v:114548.9-114548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:114558.3-114573.6" - process $proc$libresoc.v:114558$4574 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:114559.5-114559.29" - switch \initial - attribute \src "libresoc.v:114559.9-114559.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] \MUL_FXM - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:114574.3-114592.6" - process $proc$libresoc.v:114574$4575 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:114575.5-114575.29" - switch \initial - attribute \src "libresoc.v:114575.9-114575.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:114430$4562_Y - connect \$3 $and$libresoc.v:114431$4563_Y - connect \$5 $eq$libresoc.v:114432$4564_Y - connect \$7 $and$libresoc.v:114433$4565_Y -end -attribute \src "libresoc.v:114597.1-114894.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in" -attribute \generator "nMigen" -module \dec_cr_in$191 - attribute \src "libresoc.v:114788.3-114814.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:114815.3-114825.6" - wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114766.3-114776.6" - wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114826.3-114836.6" - wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114837.3-114847.6" - wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114739.3-114765.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114875.3-114893.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:114777.3-114787.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114598.7-114598.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:114848.3-114858.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:114859.3-114874.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:114788.3-114814.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114815.3-114825.6" - wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114766.3-114776.6" - wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114826.3-114836.6" - wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114837.3-114847.6" - wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:114739.3-114765.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114875.3-114893.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:114777.3-114787.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114848.3-114858.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:114859.3-114874.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:114875.3-114893.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:114859.3-114874.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:114732.17-114732.112" - wire $and$libresoc.v:114732$4578_Y - attribute \src "libresoc.v:114734.17-114734.112" - wire $and$libresoc.v:114734$4580_Y - attribute \src "libresoc.v:114731.17-114731.127" - wire $eq$libresoc.v:114731$4577_Y - attribute \src "libresoc.v:114733.17-114733.127" - wire $eq$libresoc.v:114733$4579_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 4 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 3 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 8 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 5 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 6 \SHIFT_ROT_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 2 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:114598.7-114598.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" - wire width 32 input 10 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114732$4578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \move_one - connect \Y $and$libresoc.v:114732$4578_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $and $and$libresoc.v:114734$4580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \move_one - connect \Y $and$libresoc.v:114734$4580_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114731$4577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114731$4577_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - cell $eq $eq$libresoc.v:114733$4579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $eq$libresoc.v:114733$4579_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:114735.15-114738.4" - cell \ppick$192 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:114598.7-114598.20" - process $proc$libresoc.v:114598$4591 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:114739.3-114765.6" - process $proc$libresoc.v:114739$4581 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:114740.5-114740.29" - switch \initial - attribute \src "libresoc.v:114740.9-114740.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:114766.3-114776.6" - process $proc$libresoc.v:114766$4582 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:114767.5-114767.29" - switch \initial - attribute \src "libresoc.v:114767.9-114767.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b_ok[0:0] 1'1 - case - assign $1\cr_bitfield_b_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] - end - attribute \src "libresoc.v:114777.3-114787.6" - process $proc$libresoc.v:114777$4583 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:114778.5-114778.29" - switch \initial - attribute \src "libresoc.v:114778.9-114778.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'110 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:114788.3-114814.6" - process $proc$libresoc.v:114788$4584 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:114789.5-114789.29" - switch \initial - attribute \src "libresoc.v:114789.9-114789.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BI [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BFA - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BA [4:2] - attribute \src "libresoc.v:0.0-0.0" - case 3'101 - assign { } { } - assign $1\cr_bitfield[2:0] \SHIFT_ROT_BC [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:114815.3-114825.6" - process $proc$libresoc.v:114815$4585 - assign { } { } - assign { } { } - assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:114816.5-114816.29" - switch \initial - attribute \src "libresoc.v:114816.9-114816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_b[2:0] \SHIFT_ROT_BB [4:2] - case - assign $1\cr_bitfield_b[2:0] 3'000 - end - sync always - update \cr_bitfield_b $0\cr_bitfield_b[2:0] - end - attribute \src "libresoc.v:114826.3-114836.6" - process $proc$libresoc.v:114826$4586 - assign { } { } - assign { } { } - assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:114827.5-114827.29" - switch \initial - attribute \src "libresoc.v:114827.9-114827.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_bitfield_o[2:0] \SHIFT_ROT_BT [4:2] - case - assign $1\cr_bitfield_o[2:0] 3'000 - end - sync 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"libresoc.v:115509.7-115509.20" - process $proc$libresoc.v:115509$4630 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:115632.3-115650.6" - process $proc$libresoc.v:115632$4624 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115633.5-115633.29" - switch \initial - attribute \src "libresoc.v:115633.9-115633.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:115651.3-115661.6" - process $proc$libresoc.v:115651$4625 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115652.5-115652.29" - switch \initial - attribute \src "libresoc.v:115652.9-115652.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:115662.3-115680.6" - process $proc$libresoc.v:115662$4626 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115663.5-115663.29" - switch \initial - attribute \src "libresoc.v:115663.9-115663.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:115681.3-115691.6" - process $proc$libresoc.v:115681$4627 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115682.5-115682.29" - switch \initial - attribute \src "libresoc.v:115682.9-115682.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign 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- assign { } { } - assign $3\ppick_i[7:0] \ALU_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:115713.3-115747.6" - process $proc$libresoc.v:115713$4629 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:115714.5-115714.29" - switch \initial - attribute \src "libresoc.v:115714.9-115714.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \ALU_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:115625$4622_Y - connect \$3 $eq$libresoc.v:115626$4623_Y -end -attribute \src "libresoc.v:115752.1-115991.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$145 - attribute \src "libresoc.v:115905.3-115923.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:115875.3-115893.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115956.3-115990.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:115894.3-115904.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115753.7-115753.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:115924.3-115934.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:115935.3-115955.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:115905.3-115923.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:115875.3-115893.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115956.3-115990.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:115894.3-115904.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:115924.3-115934.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:115935.3-115955.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:115956.3-115990.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:115935.3-115955.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:115956.3-115990.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:115935.3-115955.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:115956.3-115990.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:115868.17-115868.120" - wire $eq$libresoc.v:115868$4631_Y - attribute \src "libresoc.v:115869.17-115869.120" - wire $eq$libresoc.v:115869$4632_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 4 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\enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:115753.7-115753.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:115868$4631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115868$4631_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:115869$4632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:115869$4632_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:115870.15-115874.4" - cell \ppick$146 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:115753.7-115753.20" - process $proc$libresoc.v:115753$4639 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:115875.3-115893.6" - process $proc$libresoc.v:115875$4633 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:115876.5-115876.29" - switch \initial - attribute \src "libresoc.v:115876.9-115876.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:115894.3-115904.6" - process $proc$libresoc.v:115894$4634 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} - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:115924.3-115934.6" - process $proc$libresoc.v:115924$4636 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:115925.5-115925.29" - switch \initial - attribute \src "libresoc.v:115925.9-115925.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src 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attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:115996.7-115996.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116111$4640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116111$4640_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116112$4641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116112$4641_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116113.15-116117.4" - cell \ppick$153 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:115996.7-115996.20" - process $proc$libresoc.v:115996$4648 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:116118.3-116136.6" - process $proc$libresoc.v:116118$4642 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116119.5-116119.29" - switch \initial - attribute \src "libresoc.v:116119.9-116119.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:116137.3-116147.6" - process $proc$libresoc.v:116137$4643 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116138.5-116138.29" - switch \initial - attribute \src "libresoc.v:116138.9-116138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:116148.3-116166.6" - process $proc$libresoc.v:116148$4644 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116149.5-116149.29" - switch \initial - attribute \src "libresoc.v:116149.9-116149.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:116167.3-116177.6" - process $proc$libresoc.v:116167$4645 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116168.5-116168.29" - switch \initial - attribute \src "libresoc.v:116168.9-116168.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:116178.3-116198.6" - process $proc$libresoc.v:116178$4646 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116179.5-116179.29" - switch \initial - attribute \src "libresoc.v:116179.9-116179.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \BRANCH_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:116199.3-116233.6" - process $proc$libresoc.v:116199$4647 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116200.5-116200.29" - switch \initial - attribute \src "libresoc.v:116200.9-116200.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \BRANCH_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:116111$4640_Y - connect \$3 $eq$libresoc.v:116112$4641_Y -end -attribute \src "libresoc.v:116238.1-116478.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$160 - attribute \src "libresoc.v:116392.3-116410.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116362.3-116380.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116443.3-116477.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116381.3-116391.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116239.7-116239.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:116411.3-116421.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:116422.3-116442.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116392.3-116410.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116362.3-116380.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116443.3-116477.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116381.3-116391.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116411.3-116421.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:116422.3-116442.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116443.3-116477.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116422.3-116442.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116443.3-116477.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116422.3-116442.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116443.3-116477.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116355.17-116355.125" - wire $eq$libresoc.v:116355$4649_Y - attribute \src "libresoc.v:116356.17-116356.125" - wire $eq$libresoc.v:116356$4650_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 5 \LOGICAL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:116239.7-116239.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116355$4649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116355$4649_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116356$4650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116356$4650_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116357.15-116361.4" - cell \ppick$161 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:116239.7-116239.20" - process $proc$libresoc.v:116239$4657 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:116362.3-116380.6" - process $proc$libresoc.v:116362$4651 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116363.5-116363.29" - switch \initial - attribute \src "libresoc.v:116363.9-116363.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:116381.3-116391.6" - process $proc$libresoc.v:116381$4652 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116382.5-116382.29" - switch \initial - attribute \src "libresoc.v:116382.9-116382.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:116392.3-116410.6" - process $proc$libresoc.v:116392$4653 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116393.5-116393.29" - switch \initial - attribute \src "libresoc.v:116393.9-116393.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:116411.3-116421.6" - process $proc$libresoc.v:116411$4654 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116412.5-116412.29" - switch \initial - attribute \src "libresoc.v:116412.9-116412.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:116422.3-116442.6" - process $proc$libresoc.v:116422$4655 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116423.5-116423.29" - switch \initial - attribute \src "libresoc.v:116423.9-116423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \LOGICAL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:116443.3-116477.6" - process $proc$libresoc.v:116443$4656 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116444.5-116444.29" - switch \initial - attribute \src "libresoc.v:116444.9-116444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \LOGICAL_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:116355$4649_Y - connect \$3 $eq$libresoc.v:116356$4650_Y -end -attribute \src "libresoc.v:116482.1-116721.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$169 - attribute \src "libresoc.v:116635.3-116653.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:116605.3-116623.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116686.3-116720.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:116624.3-116634.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116483.7-116483.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:116654.3-116664.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:116665.3-116685.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:116635.3-116653.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116605.3-116623.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116686.3-116720.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:116624.3-116634.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116654.3-116664.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:116665.3-116685.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:116686.3-116720.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:116665.3-116685.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:116686.3-116720.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:116665.3-116685.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:116686.3-116720.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:116598.17-116598.121" - wire $eq$libresoc.v:116598$4658_Y - attribute \src "libresoc.v:116599.17-116599.121" - wire $eq$libresoc.v:116599$4659_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 4 \SPR_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116598$4658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116598$4658_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:116599$4659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116599$4659_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116600.15-116604.4" - cell \ppick$170 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:116483.7-116483.20" - process $proc$libresoc.v:116483$4666 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:116605.3-116623.6" - process $proc$libresoc.v:116605$4660 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116606.5-116606.29" - switch \initial - attribute \src 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attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:116635.3-116653.6" - process $proc$libresoc.v:116635$4662 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116636.5-116636.29" - switch \initial - attribute \src "libresoc.v:116636.9-116636.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:116654.3-116664.6" - process $proc$libresoc.v:116654$4663 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:116655.5-116655.29" - switch \initial - attribute \src "libresoc.v:116655.9-116655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:116665.3-116685.6" - process $proc$libresoc.v:116665$4664 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:116666.5-116666.29" - switch \initial - attribute \src "libresoc.v:116666.9-116666.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SPR_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:116686.3-116720.6" - process $proc$libresoc.v:116686$4665 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:116726.7-116726.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire 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$eq$libresoc.v:116843$4668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:116843$4668_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:116844.15-116848.4" - cell \ppick$177 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:116726.7-116726.20" - process $proc$libresoc.v:116726$4675 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:116849.3-116867.6" - process $proc$libresoc.v:116849$4669 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:116850.5-116850.29" - switch \initial - attribute \src "libresoc.v:116850.9-116850.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:116868.3-116878.6" - process $proc$libresoc.v:116868$4670 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:116869.5-116869.29" - switch \initial - attribute \src "libresoc.v:116869.9-116869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:116879.3-116897.6" - process $proc$libresoc.v:116879$4671 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:116880.5-116880.29" - switch \initial - attribute \src "libresoc.v:116880.9-116880.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src 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- attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \DIV_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:116930.3-116964.6" - process $proc$libresoc.v:116930$4674 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:116931.5-116931.29" - switch \initial - attribute \src "libresoc.v:116931.9-116931.17" - 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"libresoc.v:117086.17-117086.121" - wire $eq$libresoc.v:117086$4676_Y - attribute \src "libresoc.v:117087.17-117087.121" - wire $eq$libresoc.v:117087$4677_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 5 \MUL_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 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\enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:116970.7-116970.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117086$4676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117086$4676_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117087$4677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117087$4677_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:117088.15-117092.4" - cell \ppick$186 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:116970.7-116970.20" - process $proc$libresoc.v:116970$4684 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:117093.3-117111.6" - process $proc$libresoc.v:117093$4678 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117094.5-117094.29" - switch \initial - attribute \src "libresoc.v:117094.9-117094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:117112.3-117122.6" - process $proc$libresoc.v:117112$4679 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117113.5-117113.29" - switch \initial - attribute \src "libresoc.v:117113.9-117113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:117123.3-117141.6" - process $proc$libresoc.v:117123$4680 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117124.5-117124.29" - switch \initial - attribute \src "libresoc.v:117124.9-117124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:117142.3-117152.6" - process $proc$libresoc.v:117142$4681 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:117143.5-117143.29" - switch \initial - attribute \src "libresoc.v:117143.9-117143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:117153.3-117173.6" - process $proc$libresoc.v:117153$4682 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:117154.5-117154.29" - switch \initial - attribute \src "libresoc.v:117154.9-117154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \MUL_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:117174.3-117208.6" - process $proc$libresoc.v:117174$4683 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:117175.5-117175.29" - switch \initial - attribute \src "libresoc.v:117175.9-117175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \MUL_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:117086$4676_Y - connect \$3 $eq$libresoc.v:117087$4677_Y -end -attribute \src "libresoc.v:117213.1-117453.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$193 - attribute \src "libresoc.v:117367.3-117385.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:117337.3-117355.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117418.3-117452.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:117356.3-117366.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117214.7-117214.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:117386.3-117396.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:117397.3-117417.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:117367.3-117385.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117337.3-117355.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117418.3-117452.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:117356.3-117366.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117386.3-117396.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:117397.3-117417.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:117418.3-117452.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:117397.3-117417.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:117418.3-117452.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:117397.3-117417.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:117418.3-117452.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:117330.17-117330.127" - wire $eq$libresoc.v:117330$4685_Y - attribute \src "libresoc.v:117331.17-117331.127" - wire $eq$libresoc.v:117331$4686_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 5 \SHIFT_ROT_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:117214.7-117214.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 8 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117330$4685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117330$4685_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117331$4686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117331$4686_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:117332.15-117336.4" - cell \ppick$194 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:117214.7-117214.20" - process $proc$libresoc.v:117214$4693 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:117337.3-117355.6" - process $proc$libresoc.v:117337$4687 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117338.5-117338.29" - switch \initial - attribute \src "libresoc.v:117338.9-117338.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:117356.3-117366.6" - process $proc$libresoc.v:117356$4688 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117357.5-117357.29" - switch \initial - attribute \src "libresoc.v:117357.9-117357.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:117367.3-117385.6" - process $proc$libresoc.v:117367$4689 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117368.5-117368.29" - switch \initial - attribute \src "libresoc.v:117368.9-117368.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:117386.3-117396.6" - process $proc$libresoc.v:117386$4690 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:117387.5-117387.29" - switch \initial - attribute \src "libresoc.v:117387.9-117387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:117397.3-117417.6" - process $proc$libresoc.v:117397$4691 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:117398.5-117398.29" - switch \initial - attribute \src "libresoc.v:117398.9-117398.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \SHIFT_ROT_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:117418.3-117452.6" - process $proc$libresoc.v:117418$4692 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:117419.5-117419.29" - switch \initial - attribute \src "libresoc.v:117419.9-117419.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:117330$4685_Y - connect \$3 $eq$libresoc.v:117331$4686_Y -end -attribute \src "libresoc.v:117457.1-117696.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$201 - attribute \src "libresoc.v:117610.3-117628.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:117580.3-117598.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117661.3-117695.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:117599.3-117609.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117458.7-117458.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:117629.3-117639.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:117640.3-117660.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:117610.3-117628.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117580.3-117598.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117661.3-117695.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:117599.3-117609.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117629.3-117639.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:117640.3-117660.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:117661.3-117695.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:117640.3-117660.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:117661.3-117695.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:117640.3-117660.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:117661.3-117695.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:117573.17-117573.122" - wire $eq$libresoc.v:117573$4694_Y - attribute \src "libresoc.v:117574.17-117574.122" - wire $eq$libresoc.v:117574$4695_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 4 \LDST_FXM - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 3 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_fxm_ok - attribute \src "libresoc.v:117458.7-117458.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" - wire width 32 input 7 \insn_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" - wire \move_one - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" - wire input 2 \rc_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117573$4694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117573$4694_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - cell $eq $eq$libresoc.v:117574$4695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $eq$libresoc.v:117574$4695_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:117575.15-117579.4" - cell \ppick$202 \ppick - connect \en_o \ppick_en_o - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "libresoc.v:117458.7-117458.20" - process $proc$libresoc.v:117458$4702 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:117580.3-117598.6" - process $proc$libresoc.v:117580$4696 - assign { } { } - assign { } { } - assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117581.5-117581.29" - switch \initial - attribute \src "libresoc.v:117581.9-117581.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield_ok[0:0] \rc_in - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield_ok[0:0] 1'1 - case - assign $1\cr_bitfield_ok[0:0] 1'0 - end - sync always - update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] - end - attribute \src "libresoc.v:117599.3-117609.6" - process $proc$libresoc.v:117599$4697 - assign { } { } - assign { } { } - assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117600.5-117600.29" - switch \initial - attribute \src "libresoc.v:117600.9-117600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm_ok[0:0] 1'1 - case - assign $1\cr_fxm_ok[0:0] 1'0 - end - sync always - update \cr_fxm_ok $0\cr_fxm_ok[0:0] - end - attribute \src "libresoc.v:117610.3-117628.6" - process $proc$libresoc.v:117610$4698 - assign { } { } - assign { } { } - assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117611.5-117611.29" - switch \initial - attribute \src "libresoc.v:117611.9-117611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\cr_bitfield[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\cr_bitfield[2:0] \X_BF - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\cr_bitfield[2:0] \XL_BT [4:2] - case - assign $1\cr_bitfield[2:0] 3'000 - end - sync always - update \cr_bitfield $0\cr_bitfield[2:0] - end - attribute \src "libresoc.v:117629.3-117639.6" - process $proc$libresoc.v:117629$4699 - assign { } { } - assign { } { } - assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:117630.5-117630.29" - switch \initial - attribute \src "libresoc.v:117630.9-117630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\move_one[0:0] \insn_in [20] - case - assign $1\move_one[0:0] 1'0 - end - sync always - update \move_one $0\move_one[0:0] - end - attribute \src "libresoc.v:117640.3-117660.6" - process $proc$libresoc.v:117640$4700 - assign { } { } - assign { } { } - assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:117641.5-117641.29" - switch \initial - attribute \src "libresoc.v:117641.9-117641.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\ppick_i[7:0] $2\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ppick_i[7:0] $3\ppick_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ppick_i[7:0] \LDST_FXM - case - assign $3\ppick_i[7:0] 8'00000000 - end - case - assign $2\ppick_i[7:0] 8'00000000 - end - case - assign $1\ppick_i[7:0] 8'00000000 - end - sync always - update \ppick_i $0\ppick_i[7:0] - end - attribute \src "libresoc.v:117661.3-117695.6" - process $proc$libresoc.v:117661$4701 - assign { } { } - assign { } { } - assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:117662.5-117662.29" - switch \initial - attribute \src "libresoc.v:117662.9-117662.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" - switch \move_one - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - switch \ppick_en_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cr_fxm[7:0] \ppick_o - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\cr_fxm[7:0] 8'00000001 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\cr_fxm[7:0] \LDST_FXM - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_fxm[7:0] 8'11111111 - end - case - assign $1\cr_fxm[7:0] 8'00000000 - end - sync always - update \cr_fxm $0\cr_fxm[7:0] - end - connect \$1 $eq$libresoc.v:117573$4694_Y - connect \$3 $eq$libresoc.v:117574$4695_Y -end -attribute \src "libresoc.v:117700.1-117943.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" -attribute \generator "nMigen" -module \dec_cr_out$210 - attribute \src "libresoc.v:117857.3-117875.6" - wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:117827.3-117845.6" - wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117908.3-117942.6" - wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:117846.3-117856.6" - wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117701.7-117701.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:117876.3-117886.6" - wire $0\move_one[0:0] - attribute \src "libresoc.v:117887.3-117907.6" - wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:117857.3-117875.6" - wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:117827.3-117845.6" - wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:117908.3-117942.6" - wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:117846.3-117856.6" - wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:117876.3-117886.6" - wire $1\move_one[0:0] - attribute \src "libresoc.v:117887.3-117907.6" - wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:117908.3-117942.6" - wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:117887.3-117907.6" - wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:117908.3-117942.6" - wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:117887.3-117907.6" - wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:117908.3-117942.6" - wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:117820.17-117820.117" - wire $eq$libresoc.v:117820$4703_Y - attribute \src "libresoc.v:117821.17-117821.117" - wire $eq$libresoc.v:117821$4704_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" - wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 6 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 7 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 output 4 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:117701.7-117701.15" - wire \initial - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\reg_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\reg_o_ok[0:0] 1'1 - case - assign $1\reg_o_ok[0:0] 1'0 - end - sync always - update \reg_o_ok $0\reg_o_ok[0:0] - end - attribute \src "libresoc.v:118341.3-118351.6" - process $proc$libresoc.v:118341$4718 - assign { } { } - assign { } { } - assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:118342.5-118342.29" - switch \initial - attribute \src "libresoc.v:118342.9-118342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } - case - assign $1\spr[9:0] 10'0000000000 - end - sync always - update \spr $0\spr[9:0] - end - attribute \src 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update \spr_o_ok $0\spr_o_ok[0:0] - end - attribute \src "libresoc.v:118385.3-118423.6" - process $proc$libresoc.v:118385$4721 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $3\fast_o[2:0] - assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:118386.5-118386.29" - switch \initial - attribute \src "libresoc.v:118386.9-118386.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'11 - assign { } { } - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } - case - assign $2\fast_o[2:0] 3'000 - assign $2\fast_o_ok[0:0] 1'0 - end - case - assign $1\fast_o[2:0] 3'000 - assign $1\fast_o_ok[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0001000 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] $4\fast_o[2:0] - assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $4\fast_o[2:0] 3'000 - assign $4\fast_o_ok[0:0] 1'1 - case - assign $4\fast_o[2:0] $1\fast_o[2:0] - assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign { } { } - assign $3\fast_o[2:0] 3'011 - assign $3\fast_o_ok[0:0] 1'1 - case - assign $3\fast_o[2:0] $1\fast_o[2:0] - assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] - end - sync always - update \fast_o $0\fast_o[2:0] - update \fast_o_ok $0\fast_o_ok[0:0] - end - connect \$1 $eq$libresoc.v:118300$4712_Y - connect \$3 $eq$libresoc.v:118301$4713_Y - connect \$5 $eq$libresoc.v:118302$4714_Y - connect \$7 $not$libresoc.v:118303$4715_Y -end -attribute \src "libresoc.v:118428.1-118589.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" -attribute \generator "nMigen" -module \dec_o2 - attribute \src "libresoc.v:118549.3-118568.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:118569.3-118588.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:118429.7-118429.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:118535.3-118548.6" - wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:118535.3-118548.6" - wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:118549.3-118568.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:118569.3-118588.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:118535.3-118548.6" - wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:118535.3-118548.6" - wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:118549.3-118568.6" - wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:118569.3-118588.6" - wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:118533.17-118533.108" - wire $eq$libresoc.v:118533$4723_Y - attribute \src "libresoc.v:118534.17-118534.100" - wire width 6 $extend$libresoc.v:118534$4724_Y - attribute \src "libresoc.v:118534.17-118534.100" - wire width 6 $pos$libresoc.v:118534$4725_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 4 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 5 \fast_o_ok - attribute \src "libresoc.v:118429.7-118429.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 8 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" - wire input 1 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \reg_o_ok - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" - cell $eq $eq$libresoc.v:118533$4723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $eq$libresoc.v:118533$4723_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $extend$libresoc.v:118534$4724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \RA - connect \Y $extend$libresoc.v:118534$4724_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - cell $pos $pos$libresoc.v:118534$4725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $extend$libresoc.v:118534$4724_Y - connect \Y $pos$libresoc.v:118534$4725_Y - end - attribute \src "libresoc.v:118429.7-118429.20" - process $proc$libresoc.v:118429$4729 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:118535.3-118548.6" - process $proc$libresoc.v:118535$4726 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg_o[4:0] $1\reg_o[4:0] - assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:118536.5-118536.29" - switch \initial - attribute \src "libresoc.v:118536.9-118536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $1\reg_o[4:0] \$3 [4:0] - assign $1\reg_o_ok[0:0] 1'1 - case - assign $1\reg_o[4:0] 5'00000 - assign $1\reg_o_ok[0:0] 1'0 - end - sync always - update \reg_o $0\reg_o[4:0] - update \reg_o_ok $0\reg_o_ok[0:0] - end - attribute \src "libresoc.v:118549.3-118568.6" - process $proc$libresoc.v:118549$4727 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:118550.5-118550.29" - switch \initial - attribute \src "libresoc.v:118550.9-118550.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o[2:0] $2\fast_o[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o[2:0] 3'001 - case - assign $2\fast_o[2:0] 3'000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o[2:0] 3'100 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "libresoc.v:118569.3-118588.6" - process $proc$libresoc.v:118569$4728 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:118570.5-118570.29" - switch \initial - attribute \src "libresoc.v:118570.9-118570.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 , 7'0000110 , 7'0001000 - assign { } { } - assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" - switch \lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast_o_ok[0:0] 1'1 - case - assign $2\fast_o_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - connect \$1 $eq$libresoc.v:118533$4723_Y - connect \$3 $pos$libresoc.v:118534$4725_Y -end -attribute \src "libresoc.v:118593.1-118727.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" -attribute \generator "nMigen" -module \dec_oe - attribute \src "libresoc.v:118594.7-118594.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:118685.3-118705.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:118706.3-118726.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118685.3-118705.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:118706.3-118726.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118685.3-118705.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:118706.3-118726.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \ALU_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:118594.7-118594.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:118594.7-118594.20" - process $proc$libresoc.v:118594$4732 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:118685.3-118705.6" - process $proc$libresoc.v:118685$4730 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118686.5-118686.29" - switch \initial - attribute \src "libresoc.v:118686.9-118686.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \ALU_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \ALU_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:118706.3-118726.6" - process $proc$libresoc.v:118706$4731 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118707.5-118707.29" - switch \initial - attribute \src "libresoc.v:118707.9-118707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \ALU_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:118731.1-118863.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" -attribute \generator "nMigen" -module \dec_oe$142 - attribute \src "libresoc.v:118732.7-118732.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:118821.3-118841.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:118842.3-118862.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118821.3-118841.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:118842.3-118862.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118821.3-118841.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:118842.3-118862.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \CR_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:118732.7-118732.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:118732.7-118732.20" - process $proc$libresoc.v:118732$4735 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:118821.3-118841.6" - process $proc$libresoc.v:118821$4733 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118822.5-118822.29" - switch \initial - attribute \src "libresoc.v:118822.9-118822.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \CR_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \CR_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:118842.3-118862.6" - process $proc$libresoc.v:118842$4734 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118843.5-118843.29" - switch \initial - attribute \src "libresoc.v:118843.9-118843.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \CR_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:118867.1-118999.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" -attribute \generator "nMigen" -module \dec_oe$149 - attribute \src "libresoc.v:118868.7-118868.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:118957.3-118977.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:118978.3-118998.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:118957.3-118977.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:118978.3-118998.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:118957.3-118977.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:118978.3-118998.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \BRANCH_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:118868.7-118868.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:118868.7-118868.20" - process $proc$libresoc.v:118868$4738 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:118957.3-118977.6" - process $proc$libresoc.v:118957$4736 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:118958.5-118958.29" - switch \initial - attribute \src "libresoc.v:118958.9-118958.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \BRANCH_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \BRANCH_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:118978.3-118998.6" - process $proc$libresoc.v:118978$4737 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:118979.5-118979.29" - switch \initial - attribute \src "libresoc.v:118979.9-118979.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \BRANCH_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119003.1-119137.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" -attribute \generator "nMigen" -module \dec_oe$157 - attribute \src "libresoc.v:119004.7-119004.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119095.3-119115.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:119116.3-119136.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119095.3-119115.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:119116.3-119136.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119095.3-119115.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:119116.3-119136.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \LOGICAL_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:119004.7-119004.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119004.7-119004.20" - process $proc$libresoc.v:119004$4741 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119095.3-119115.6" - process $proc$libresoc.v:119095$4739 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119096.5-119096.29" - switch \initial - attribute \src "libresoc.v:119096.9-119096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \LOGICAL_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \LOGICAL_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:119116.3-119136.6" - process $proc$libresoc.v:119116$4740 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119117.5-119117.29" - switch \initial - attribute \src "libresoc.v:119117.9-119117.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \LOGICAL_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119141.1-119273.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" -attribute \generator "nMigen" -module \dec_oe$166 - attribute \src "libresoc.v:119142.7-119142.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119231.3-119251.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:119252.3-119272.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119231.3-119251.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:119252.3-119272.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119231.3-119251.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:119252.3-119272.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \SPR_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:119142.7-119142.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:119142.7-119142.20" - process $proc$libresoc.v:119142$4744 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119231.3-119251.6" - process $proc$libresoc.v:119231$4742 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119232.5-119232.29" - switch \initial - attribute \src "libresoc.v:119232.9-119232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \SPR_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \SPR_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:119252.3-119272.6" - process $proc$libresoc.v:119252$4743 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119253.5-119253.29" - switch \initial - attribute \src "libresoc.v:119253.9-119253.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \SPR_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119277.1-119411.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" -attribute \generator "nMigen" -module \dec_oe$173 - attribute \src "libresoc.v:119278.7-119278.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119369.3-119389.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:119390.3-119410.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119369.3-119389.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:119390.3-119410.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119369.3-119389.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:119390.3-119410.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \DIV_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:119278.7-119278.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119278.7-119278.20" - process $proc$libresoc.v:119278$4747 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119369.3-119389.6" - process $proc$libresoc.v:119369$4745 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119370.5-119370.29" - switch \initial - attribute \src "libresoc.v:119370.9-119370.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \DIV_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \DIV_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:119390.3-119410.6" - process $proc$libresoc.v:119390$4746 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119391.5-119391.29" - switch \initial - attribute \src "libresoc.v:119391.9-119391.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \DIV_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119415.1-119549.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" -attribute \generator "nMigen" -module \dec_oe$182 - attribute \src "libresoc.v:119416.7-119416.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119507.3-119527.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:119528.3-119548.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119507.3-119527.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:119528.3-119548.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119507.3-119527.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:119528.3-119548.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \MUL_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:119416.7-119416.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119416.7-119416.20" - process $proc$libresoc.v:119416$4750 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119507.3-119527.6" - process $proc$libresoc.v:119507$4748 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119508.5-119508.29" - switch \initial - attribute \src "libresoc.v:119508.9-119508.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \MUL_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \MUL_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:119528.3-119548.6" - process $proc$libresoc.v:119528$4749 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119529.5-119529.29" - switch \initial - attribute \src "libresoc.v:119529.9-119529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \MUL_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119553.1-119687.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" -attribute \generator "nMigen" -module \dec_oe$190 - attribute \src "libresoc.v:119554.7-119554.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119645.3-119665.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:119666.3-119686.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119645.3-119665.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:119666.3-119686.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119645.3-119665.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:119666.3-119686.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \SHIFT_ROT_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:119554.7-119554.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119554.7-119554.20" - process $proc$libresoc.v:119554$4753 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119645.3-119665.6" - process $proc$libresoc.v:119645$4751 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119646.5-119646.29" - switch \initial - attribute \src "libresoc.v:119646.9-119646.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \SHIFT_ROT_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \SHIFT_ROT_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:119666.3-119686.6" - process $proc$libresoc.v:119666$4752 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119667.5-119667.29" - switch \initial - attribute \src "libresoc.v:119667.9-119667.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \SHIFT_ROT_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119691.1-119825.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" -attribute \generator "nMigen" -module \dec_oe$198 - attribute \src "libresoc.v:119692.7-119692.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119783.3-119803.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:119804.3-119824.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119783.3-119803.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:119804.3-119824.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119783.3-119803.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:119804.3-119824.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \LDST_OE - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:119692.7-119692.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119692.7-119692.20" - process $proc$libresoc.v:119692$4756 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119783.3-119803.6" - process $proc$libresoc.v:119783$4754 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119784.5-119784.29" - switch \initial - attribute \src "libresoc.v:119784.9-119784.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \LDST_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \LDST_OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:119804.3-119824.6" - process $proc$libresoc.v:119804$4755 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119805.5-119805.29" - switch \initial - attribute \src "libresoc.v:119805.9-119805.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \LDST_internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119829.1-119963.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" -attribute \generator "nMigen" -module \dec_oe$207 - attribute \src "libresoc.v:119830.7-119830.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119921.3-119941.6" - wire $0\oe[0:0] - attribute \src "libresoc.v:119942.3-119962.6" - wire $0\oe_ok[0:0] - attribute \src "libresoc.v:119921.3-119941.6" - wire $1\oe[0:0] - attribute \src "libresoc.v:119942.3-119962.6" - wire $1\oe_ok[0:0] - attribute \src "libresoc.v:119921.3-119941.6" - wire $2\oe[0:0] - attribute \src "libresoc.v:119942.3-119962.6" - wire $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 4 \OE - attribute \src "libresoc.v:119830.7-119830.15" - wire \initial - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 3 \oe_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" - wire width 2 input 5 \sel_in - attribute \src "libresoc.v:119830.7-119830.20" - process $proc$libresoc.v:119830$4759 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119921.3-119941.6" - process $proc$libresoc.v:119921$4757 - assign { } { } - assign { } { } - assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:119922.5-119922.29" - switch \initial - attribute \src "libresoc.v:119922.9-119922.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe[0:0] $2\oe[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe[0:0] \OE - case - assign $2\oe[0:0] 1'0 - end - end - sync always - update \oe $0\oe[0:0] - end - attribute \src "libresoc.v:119942.3-119962.6" - process $proc$libresoc.v:119942$4758 - assign { } { } - assign { } { } - assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:119943.5-119943.29" - switch \initial - attribute \src "libresoc.v:119943.9-119943.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" - switch \internal_op - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 - assign $1\oe_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\oe_ok[0:0] $2\oe_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\oe_ok[0:0] 1'1 - case - assign $2\oe_ok[0:0] 1'0 - end - end - sync always - update \oe_ok $0\oe_ok[0:0] - end -end -attribute \src "libresoc.v:119967.1-120021.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" -attribute \generator "nMigen" -module \dec_rc - attribute \src "libresoc.v:119968.7-119968.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:119983.3-120001.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120002.3-120020.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:119983.3-120001.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120002.3-120020.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \ALU_Rc - attribute \src "libresoc.v:119968.7-119968.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:119968.7-119968.20" - process $proc$libresoc.v:119968$4762 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:119983.3-120001.6" - process $proc$libresoc.v:119983$4760 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:119984.5-119984.29" - switch \initial - attribute \src "libresoc.v:119984.9-119984.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \ALU_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120002.3-120020.6" - process $proc$libresoc.v:120002$4761 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120003.5-120003.29" - switch \initial - attribute \src "libresoc.v:120003.9-120003.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120025.1-120078.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" -attribute \generator "nMigen" -module \dec_rc$141 - attribute \src "libresoc.v:120026.7-120026.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120040.3-120058.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120059.3-120077.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120040.3-120058.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120059.3-120077.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \CR_Rc - attribute \src "libresoc.v:120026.7-120026.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:120026.7-120026.20" - process $proc$libresoc.v:120026$4765 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120040.3-120058.6" - process $proc$libresoc.v:120040$4763 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120041.5-120041.29" - switch \initial - attribute \src "libresoc.v:120041.9-120041.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \CR_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120059.3-120077.6" - process $proc$libresoc.v:120059$4764 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120060.5-120060.29" - switch \initial - attribute \src "libresoc.v:120060.9-120060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120082.1-120135.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" -attribute \generator "nMigen" -module \dec_rc$148 - attribute \src "libresoc.v:120083.7-120083.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120097.3-120115.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120116.3-120134.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120097.3-120115.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120116.3-120134.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \BRANCH_Rc - attribute \src "libresoc.v:120083.7-120083.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:120083.7-120083.20" - process $proc$libresoc.v:120083$4768 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120097.3-120115.6" - process $proc$libresoc.v:120097$4766 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120098.5-120098.29" - switch \initial - attribute \src "libresoc.v:120098.9-120098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \BRANCH_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120116.3-120134.6" - process $proc$libresoc.v:120116$4767 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120117.5-120117.29" - switch \initial - attribute \src "libresoc.v:120117.9-120117.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120139.1-120193.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" -attribute \generator "nMigen" -module \dec_rc$156 - attribute \src "libresoc.v:120140.7-120140.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120155.3-120173.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120174.3-120192.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120155.3-120173.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120174.3-120192.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:120140.7-120140.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120140.7-120140.20" - process $proc$libresoc.v:120140$4771 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120155.3-120173.6" - process $proc$libresoc.v:120155$4769 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120156.5-120156.29" - switch \initial - attribute \src "libresoc.v:120156.9-120156.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \LOGICAL_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120174.3-120192.6" - process $proc$libresoc.v:120174$4770 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120175.5-120175.29" - switch \initial - attribute \src "libresoc.v:120175.9-120175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120197.1-120250.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" -attribute \generator "nMigen" -module \dec_rc$165 - attribute \src "libresoc.v:120198.7-120198.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120212.3-120230.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120231.3-120249.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120212.3-120230.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120231.3-120249.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 2 \SPR_Rc - attribute \src "libresoc.v:120198.7-120198.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 3 \sel_in - attribute \src "libresoc.v:120198.7-120198.20" - process $proc$libresoc.v:120198$4774 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120212.3-120230.6" - process $proc$libresoc.v:120212$4772 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120213.5-120213.29" - switch \initial - attribute \src "libresoc.v:120213.9-120213.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \SPR_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120231.3-120249.6" - process $proc$libresoc.v:120231$4773 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120232.5-120232.29" - switch \initial - attribute \src "libresoc.v:120232.9-120232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120254.1-120308.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" -attribute \generator "nMigen" -module \dec_rc$172 - attribute \src "libresoc.v:120255.7-120255.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120270.3-120288.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120289.3-120307.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120270.3-120288.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120289.3-120307.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \DIV_Rc - attribute \src "libresoc.v:120255.7-120255.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120255.7-120255.20" - process $proc$libresoc.v:120255$4777 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120270.3-120288.6" - process $proc$libresoc.v:120270$4775 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120271.5-120271.29" - switch \initial - attribute \src "libresoc.v:120271.9-120271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \DIV_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120289.3-120307.6" - process $proc$libresoc.v:120289$4776 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120290.5-120290.29" - switch \initial - attribute \src "libresoc.v:120290.9-120290.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120312.1-120366.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" -attribute \generator "nMigen" -module \dec_rc$181 - attribute \src "libresoc.v:120313.7-120313.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120328.3-120346.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120347.3-120365.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120328.3-120346.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120347.3-120365.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \MUL_Rc - attribute \src "libresoc.v:120313.7-120313.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120313.7-120313.20" - process $proc$libresoc.v:120313$4780 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120328.3-120346.6" - process $proc$libresoc.v:120328$4778 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120329.5-120329.29" - switch \initial - attribute \src "libresoc.v:120329.9-120329.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \MUL_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120347.3-120365.6" - process $proc$libresoc.v:120347$4779 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120348.5-120348.29" - switch \initial - attribute \src "libresoc.v:120348.9-120348.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120370.1-120424.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" -attribute \generator "nMigen" -module \dec_rc$189 - attribute \src "libresoc.v:120371.7-120371.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120386.3-120404.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120405.3-120423.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120386.3-120404.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120405.3-120423.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:120371.7-120371.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120371.7-120371.20" - process $proc$libresoc.v:120371$4783 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120386.3-120404.6" - process $proc$libresoc.v:120386$4781 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120387.5-120387.29" - switch \initial - attribute \src "libresoc.v:120387.9-120387.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \SHIFT_ROT_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120405.3-120423.6" - process $proc$libresoc.v:120405$4782 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120406.5-120406.29" - switch \initial - attribute \src "libresoc.v:120406.9-120406.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120428.1-120482.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" -attribute \generator "nMigen" -module \dec_rc$197 - attribute \src "libresoc.v:120429.7-120429.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120444.3-120462.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120463.3-120481.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120444.3-120462.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120463.3-120481.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \LDST_Rc - attribute \src "libresoc.v:120429.7-120429.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120429.7-120429.20" - process $proc$libresoc.v:120429$4786 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120444.3-120462.6" - process $proc$libresoc.v:120444$4784 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120445.5-120445.29" - switch \initial - attribute \src "libresoc.v:120445.9-120445.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \LDST_Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120463.3-120481.6" - process $proc$libresoc.v:120463$4785 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120464.5-120464.29" - switch \initial - attribute \src "libresoc.v:120464.9-120464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120486.1-120540.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" -attribute \generator "nMigen" -module \dec_rc$206 - attribute \src "libresoc.v:120487.7-120487.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:120502.3-120520.6" - wire $0\rc[0:0] - attribute \src "libresoc.v:120521.3-120539.6" - wire $0\rc_ok[0:0] - attribute \src "libresoc.v:120502.3-120520.6" - wire $1\rc[0:0] - attribute \src "libresoc.v:120521.3-120539.6" - wire $1\rc_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" - wire input 3 \Rc - attribute \src "libresoc.v:120487.7-120487.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \rc_ok - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" - wire width 2 input 4 \sel_in - attribute \src "libresoc.v:120487.7-120487.20" - process $proc$libresoc.v:120487$4789 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120502.3-120520.6" - process $proc$libresoc.v:120502$4787 - assign { } { } - assign { } { } - assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:120503.5-120503.29" - switch \initial - attribute \src "libresoc.v:120503.9-120503.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc[0:0] \Rc - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc[0:0] 1'0 - case - assign $1\rc[0:0] 1'0 - end - sync always - update \rc $0\rc[0:0] - end - attribute \src "libresoc.v:120521.3-120539.6" - process $proc$libresoc.v:120521$4788 - assign { } { } - assign { } { } - assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:120522.5-120522.29" - switch \initial - attribute \src "libresoc.v:120522.9-120522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - switch \sel_in - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\rc_ok[0:0] 1'1 - case - assign $1\rc_ok[0:0] 1'0 - end - sync always - update \rc_ok $0\rc_ok[0:0] - end -end -attribute \src "libresoc.v:120544.1-121782.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" -attribute \generator "nMigen" -module \div0 - attribute \src "libresoc.v:121339.3-121340.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4929 - attribute \src "libresoc.v:121311.3-121312.75" - wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4930 - attribute \src "libresoc.v:121281.3-121282.73" - wire width 12 $0\alu_div0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4931 - attribute \src "libresoc.v:121283.3-121284.87" - wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4932 - attribute \src "libresoc.v:121285.3-121286.83" - wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4933 - attribute \src "libresoc.v:121299.3-121300.81" - wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4934 - attribute \src "libresoc.v:121313.3-121314.67" - wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4935 - attribute \src "libresoc.v:121279.3-121280.77" - wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__invert_in$next[0:0]$4936 - attribute \src "libresoc.v:121295.3-121296.77" - wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__invert_out$next[0:0]$4937 - attribute \src "libresoc.v:121301.3-121302.79" - wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4938 - attribute \src "libresoc.v:121307.3-121308.75" - wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__is_signed$next[0:0]$4939 - attribute \src "libresoc.v:121309.3-121310.77" - wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4940 - attribute \src "libresoc.v:121291.3-121292.71" - wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4941 - attribute \src "libresoc.v:121293.3-121294.71" - wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__output_carry$next[0:0]$4942 - attribute \src "libresoc.v:121305.3-121306.83" - wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4943 - attribute \src "libresoc.v:121289.3-121290.71" - wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4944 - attribute \src "libresoc.v:121287.3-121288.71" - wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4945 - attribute \src "libresoc.v:121303.3-121304.77" - wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $0\alu_div0_logical_op__zero_a$next[0:0]$4946 - attribute \src "libresoc.v:121297.3-121298.71" - wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:121337.3-121338.40" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:121692.3-121700.6" - wire $0\alu_l_r_alu$next[0:0]$5016 - attribute \src "libresoc.v:121253.3-121254.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:121683.3-121691.6" - wire $0\alui_l_r_alui$next[0:0]$5013 - attribute \src "libresoc.v:121255.3-121256.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:121565.3-121586.6" - wire width 64 $0\data_r0__o$next[63:0]$4972 - attribute \src "libresoc.v:121275.3-121276.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:121565.3-121586.6" - wire $0\data_r0__o_ok$next[0:0]$4973 - attribute \src "libresoc.v:121277.3-121278.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:121587.3-121608.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$4980 - attribute \src "libresoc.v:121271.3-121272.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:121587.3-121608.6" - wire $0\data_r1__cr_a_ok$next[0:0]$4981 - attribute \src "libresoc.v:121273.3-121274.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:121609.3-121630.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$4988 - attribute \src "libresoc.v:121267.3-121268.47" - wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:121609.3-121630.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$4989 - attribute \src "libresoc.v:121269.3-121270.53" - wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:121631.3-121652.6" - wire $0\data_r3__xer_so$next[0:0]$4996 - attribute \src "libresoc.v:121263.3-121264.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:121631.3-121652.6" - wire $0\data_r3__xer_so_ok$next[0:0]$4997 - attribute \src "libresoc.v:121265.3-121266.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:121701.3-121710.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:121711.3-121720.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:121721.3-121730.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:121731.3-121740.6" - wire $0\dest4_o[0:0] - attribute \src "libresoc.v:120545.7-120545.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:121481.3-121489.6" - wire $0\opc_l_r_opc$next[0:0]$4914 - attribute \src "libresoc.v:121323.3-121324.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:121472.3-121480.6" - wire $0\opc_l_s_opc$next[0:0]$4911 - attribute \src "libresoc.v:121325.3-121326.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:121741.3-121749.6" - wire width 4 $0\prev_wr_go$next[3:0]$5023 - attribute \src "libresoc.v:121335.3-121336.37" - wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:121426.3-121435.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:121517.3-121525.6" - wire width 4 $0\req_l_r_req$next[3:0]$4926 - attribute \src "libresoc.v:121315.3-121316.39" - wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:121508.3-121516.6" - wire width 4 $0\req_l_s_req$next[3:0]$4923 - attribute \src "libresoc.v:121317.3-121318.39" - wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:121445.3-121453.6" - wire $0\rok_l_r_rdok$next[0:0]$4902 - attribute \src "libresoc.v:121331.3-121332.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:121436.3-121444.6" - wire $0\rok_l_s_rdok$next[0:0]$4899 - attribute \src "libresoc.v:121333.3-121334.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:121463.3-121471.6" - wire $0\rst_l_r_rst$next[0:0]$4908 - attribute \src "libresoc.v:121327.3-121328.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:121454.3-121462.6" - wire $0\rst_l_s_rst$next[0:0]$4905 - attribute \src "libresoc.v:121329.3-121330.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:121499.3-121507.6" - wire width 3 $0\src_l_r_src$next[2:0]$4920 - attribute \src "libresoc.v:121319.3-121320.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:121490.3-121498.6" - wire width 3 $0\src_l_s_src$next[2:0]$4917 - attribute \src "libresoc.v:121321.3-121322.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:121653.3-121662.6" - wire width 64 $0\src_r0$next[63:0]$5004 - attribute \src "libresoc.v:121261.3-121262.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:121663.3-121672.6" - wire width 64 $0\src_r1$next[63:0]$5007 - attribute \src "libresoc.v:121259.3-121260.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:121673.3-121682.6" - wire $0\src_r2$next[0:0]$5010 - attribute \src "libresoc.v:121257.3-121258.29" - wire $0\src_r2[0:0] - attribute \src "libresoc.v:120675.7-120675.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4947 - attribute \src "libresoc.v:120685.13-120685.49" - wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 - attribute \src "libresoc.v:120702.14-120702.52" - wire width 12 $1\alu_div0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 - attribute \src "libresoc.v:120706.14-120706.72" - wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 - attribute \src "libresoc.v:120710.7-120710.47" - wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4951 - attribute \src "libresoc.v:120718.13-120718.52" - wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4952 - attribute \src "libresoc.v:120722.14-120722.47" - wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4953 - attribute \src "libresoc.v:120800.13-120800.51" - wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__invert_in$next[0:0]$4954 - attribute \src "libresoc.v:120804.7-120804.44" - wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__invert_out$next[0:0]$4955 - attribute \src "libresoc.v:120808.7-120808.45" - wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 - attribute \src "libresoc.v:120812.7-120812.43" - wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__is_signed$next[0:0]$4957 - attribute \src "libresoc.v:120816.7-120816.44" - wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 - attribute \src "libresoc.v:120820.7-120820.41" - wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 - attribute \src "libresoc.v:120824.7-120824.41" - wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__output_carry$next[0:0]$4960 - attribute \src "libresoc.v:120828.7-120828.47" - wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 - attribute \src "libresoc.v:120832.7-120832.41" - wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 - attribute \src "libresoc.v:120836.7-120836.41" - wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 - attribute \src "libresoc.v:120840.7-120840.44" - wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire $1\alu_div0_logical_op__zero_a$next[0:0]$4964 - attribute \src "libresoc.v:120844.7-120844.41" - wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:120870.7-120870.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:121692.3-121700.6" - wire $1\alu_l_r_alu$next[0:0]$5017 - attribute \src "libresoc.v:120878.7-120878.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:121683.3-121691.6" - wire $1\alui_l_r_alui$next[0:0]$5014 - attribute \src "libresoc.v:120890.7-120890.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:121565.3-121586.6" - wire width 64 $1\data_r0__o$next[63:0]$4974 - attribute \src "libresoc.v:120924.14-120924.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:121565.3-121586.6" - wire $1\data_r0__o_ok$next[0:0]$4975 - attribute \src "libresoc.v:120928.7-120928.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:121587.3-121608.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$4982 - attribute \src "libresoc.v:120932.13-120932.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:121587.3-121608.6" - wire $1\data_r1__cr_a_ok$next[0:0]$4983 - attribute \src "libresoc.v:120936.7-120936.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:121609.3-121630.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$4990 - attribute \src "libresoc.v:120940.13-120940.35" - wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:121609.3-121630.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$4991 - attribute \src "libresoc.v:120944.7-120944.32" - wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:121631.3-121652.6" - wire $1\data_r3__xer_so$next[0:0]$4998 - attribute \src "libresoc.v:120948.7-120948.29" - wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:121631.3-121652.6" - wire $1\data_r3__xer_so_ok$next[0:0]$4999 - attribute \src "libresoc.v:120952.7-120952.32" - wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:121701.3-121710.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:121711.3-121720.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:121721.3-121730.6" - wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:121731.3-121740.6" - wire $1\dest4_o[0:0] - attribute \src "libresoc.v:121481.3-121489.6" - wire $1\opc_l_r_opc$next[0:0]$4915 - attribute \src "libresoc.v:120972.7-120972.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:121472.3-121480.6" - wire $1\opc_l_s_opc$next[0:0]$4912 - attribute \src "libresoc.v:120976.7-120976.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:121741.3-121749.6" - wire width 4 $1\prev_wr_go$next[3:0]$5024 - attribute \src "libresoc.v:121107.13-121107.30" - wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:121426.3-121435.6" - wire $1\req_done[0:0] - attribute \src "libresoc.v:121517.3-121525.6" - wire width 4 $1\req_l_r_req$next[3:0]$4927 - attribute \src "libresoc.v:121115.13-121115.31" - wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:121508.3-121516.6" - wire width 4 $1\req_l_s_req$next[3:0]$4924 - attribute \src "libresoc.v:121119.13-121119.31" - wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:121445.3-121453.6" - wire $1\rok_l_r_rdok$next[0:0]$4903 - attribute \src "libresoc.v:121131.7-121131.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:121436.3-121444.6" - wire $1\rok_l_s_rdok$next[0:0]$4900 - attribute \src "libresoc.v:121135.7-121135.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:121463.3-121471.6" - wire $1\rst_l_r_rst$next[0:0]$4909 - attribute \src "libresoc.v:121139.7-121139.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:121454.3-121462.6" - wire $1\rst_l_s_rst$next[0:0]$4906 - attribute \src "libresoc.v:121143.7-121143.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:121499.3-121507.6" - wire width 3 $1\src_l_r_src$next[2:0]$4921 - attribute \src "libresoc.v:121157.13-121157.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:121490.3-121498.6" - wire width 3 $1\src_l_s_src$next[2:0]$4918 - attribute \src "libresoc.v:121161.13-121161.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:121653.3-121662.6" - wire width 64 $1\src_r0$next[63:0]$5005 - attribute \src "libresoc.v:121169.14-121169.43" - wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:121663.3-121672.6" - wire width 64 $1\src_r1$next[63:0]$5008 - attribute \src "libresoc.v:121173.14-121173.43" - wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:121673.3-121682.6" - wire $1\src_r2$next[0:0]$5011 - attribute \src "libresoc.v:121177.7-121177.20" - wire $1\src_r2[0:0] - attribute \src "libresoc.v:121526.3-121564.6" - wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 - attribute \src "libresoc.v:121526.3-121564.6" - wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4966 - attribute \src "libresoc.v:121526.3-121564.6" - wire $2\alu_div0_logical_op__oe__oe$next[0:0]$4967 - attribute \src "libresoc.v:121526.3-121564.6" - wire $2\alu_div0_logical_op__oe__ok$next[0:0]$4968 - attribute \src "libresoc.v:121526.3-121564.6" - wire $2\alu_div0_logical_op__rc__ok$next[0:0]$4969 - attribute \src "libresoc.v:121526.3-121564.6" - wire $2\alu_div0_logical_op__rc__rc$next[0:0]$4970 - attribute \src "libresoc.v:121565.3-121586.6" - wire width 64 $2\data_r0__o$next[63:0]$4976 - attribute \src "libresoc.v:121565.3-121586.6" - wire $2\data_r0__o_ok$next[0:0]$4977 - attribute \src "libresoc.v:121587.3-121608.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$4984 - attribute \src "libresoc.v:121587.3-121608.6" - wire $2\data_r1__cr_a_ok$next[0:0]$4985 - attribute \src "libresoc.v:121609.3-121630.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$4992 - attribute \src "libresoc.v:121609.3-121630.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$4993 - attribute \src "libresoc.v:121631.3-121652.6" - wire $2\data_r3__xer_so$next[0:0]$5000 - attribute \src "libresoc.v:121631.3-121652.6" - wire $2\data_r3__xer_so_ok$next[0:0]$5001 - attribute \src "libresoc.v:121565.3-121586.6" - wire $3\data_r0__o_ok$next[0:0]$4978 - attribute \src "libresoc.v:121587.3-121608.6" - wire $3\data_r1__cr_a_ok$next[0:0]$4986 - attribute \src "libresoc.v:121609.3-121630.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$4994 - attribute \src "libresoc.v:121631.3-121652.6" - wire $3\data_r3__xer_so_ok$next[0:0]$5002 - attribute \src "libresoc.v:121192.19-121192.133" - wire width 3 $and$libresoc.v:121192$4792_Y - attribute \src "libresoc.v:121194.19-121194.115" - wire width 3 $and$libresoc.v:121194$4794_Y - attribute \src "libresoc.v:121195.18-121195.110" - wire $and$libresoc.v:121195$4795_Y - attribute \src "libresoc.v:121196.19-121196.125" - wire $and$libresoc.v:121196$4796_Y - attribute \src "libresoc.v:121197.19-121197.125" - wire $and$libresoc.v:121197$4797_Y - attribute \src "libresoc.v:121198.19-121198.125" - wire $and$libresoc.v:121198$4798_Y - attribute \src "libresoc.v:121199.19-121199.125" - wire $and$libresoc.v:121199$4799_Y - attribute \src "libresoc.v:121200.19-121200.149" - wire width 4 $and$libresoc.v:121200$4800_Y - attribute \src "libresoc.v:121201.19-121201.121" - wire width 4 $and$libresoc.v:121201$4801_Y - attribute \src "libresoc.v:121202.19-121202.127" - wire $and$libresoc.v:121202$4802_Y - attribute \src "libresoc.v:121203.19-121203.127" - wire $and$libresoc.v:121203$4803_Y - attribute \src "libresoc.v:121204.19-121204.127" - wire $and$libresoc.v:121204$4804_Y - attribute \src "libresoc.v:121205.19-121205.127" - wire $and$libresoc.v:121205$4805_Y - attribute \src "libresoc.v:121207.18-121207.98" - wire $and$libresoc.v:121207$4807_Y - attribute \src "libresoc.v:121209.18-121209.100" - wire $and$libresoc.v:121209$4809_Y - attribute \src "libresoc.v:121210.18-121210.160" - wire width 4 $and$libresoc.v:121210$4810_Y - attribute \src "libresoc.v:121212.18-121212.119" - wire width 4 $and$libresoc.v:121212$4812_Y - attribute \src "libresoc.v:121215.17-121215.123" - wire $and$libresoc.v:121215$4815_Y - attribute \src "libresoc.v:121216.18-121216.116" - wire $and$libresoc.v:121216$4816_Y - attribute \src "libresoc.v:121221.18-121221.113" - wire $and$libresoc.v:121221$4821_Y - attribute \src "libresoc.v:121222.18-121222.125" - wire width 4 $and$libresoc.v:121222$4822_Y - attribute \src "libresoc.v:121224.18-121224.112" - wire $and$libresoc.v:121224$4824_Y - attribute \src "libresoc.v:121226.18-121226.126" - wire $and$libresoc.v:121226$4826_Y - attribute \src "libresoc.v:121227.18-121227.126" - wire $and$libresoc.v:121227$4827_Y - attribute \src "libresoc.v:121228.18-121228.117" - wire $and$libresoc.v:121228$4828_Y - attribute \src "libresoc.v:121234.18-121234.130" - wire $and$libresoc.v:121234$4834_Y - attribute \src "libresoc.v:121235.18-121235.124" - wire width 4 $and$libresoc.v:121235$4835_Y - attribute \src "libresoc.v:121237.18-121237.116" - wire $and$libresoc.v:121237$4837_Y - attribute \src "libresoc.v:121238.18-121238.119" - wire $and$libresoc.v:121238$4838_Y - attribute \src "libresoc.v:121239.18-121239.121" - wire $and$libresoc.v:121239$4839_Y - attribute \src "libresoc.v:121240.18-121240.121" - wire $and$libresoc.v:121240$4840_Y - attribute \src "libresoc.v:121250.18-121250.134" - wire $and$libresoc.v:121250$4850_Y - attribute \src "libresoc.v:121251.18-121251.132" - wire $and$libresoc.v:121251$4851_Y - attribute \src "libresoc.v:121252.18-121252.149" - wire width 3 $and$libresoc.v:121252$4852_Y - attribute \src "libresoc.v:121223.18-121223.113" - wire $eq$libresoc.v:121223$4823_Y - attribute \src "libresoc.v:121225.18-121225.119" - wire $eq$libresoc.v:121225$4825_Y - attribute \src "libresoc.v:121190.19-121190.130" - wire $not$libresoc.v:121190$4790_Y - attribute \src "libresoc.v:121191.19-121191.136" - wire $not$libresoc.v:121191$4791_Y - attribute \src "libresoc.v:121193.19-121193.115" - wire width 3 $not$libresoc.v:121193$4793_Y - attribute \src "libresoc.v:121206.18-121206.97" - wire $not$libresoc.v:121206$4806_Y - attribute \src "libresoc.v:121208.18-121208.99" - wire $not$libresoc.v:121208$4808_Y - attribute \src "libresoc.v:121211.18-121211.113" - wire width 4 $not$libresoc.v:121211$4811_Y - attribute \src "libresoc.v:121214.18-121214.106" - wire $not$libresoc.v:121214$4814_Y - attribute \src "libresoc.v:121220.18-121220.120" - wire $not$libresoc.v:121220$4820_Y - attribute \src "libresoc.v:121231.17-121231.113" - wire width 3 $not$libresoc.v:121231$4831_Y - attribute \src "libresoc.v:121219.18-121219.112" - wire $or$libresoc.v:121219$4819_Y - attribute \src "libresoc.v:121229.18-121229.122" - wire $or$libresoc.v:121229$4829_Y - attribute \src "libresoc.v:121230.18-121230.124" - wire $or$libresoc.v:121230$4830_Y - attribute \src "libresoc.v:121232.18-121232.168" - wire width 4 $or$libresoc.v:121232$4832_Y - attribute \src "libresoc.v:121233.18-121233.155" - wire width 3 $or$libresoc.v:121233$4833_Y - attribute \src "libresoc.v:121236.18-121236.120" - wire width 4 $or$libresoc.v:121236$4836_Y - attribute \src "libresoc.v:121242.17-121242.117" - wire width 3 $or$libresoc.v:121242$4842_Y - attribute \src "libresoc.v:121247.17-121247.104" - wire $reduce_and$libresoc.v:121247$4847_Y - attribute \src "libresoc.v:121213.18-121213.106" - wire $reduce_or$libresoc.v:121213$4813_Y - attribute \src "libresoc.v:121217.18-121217.113" - wire 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\A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:121252$4852_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:121223$4823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$42 - connect \B 1'0 - connect \Y $eq$libresoc.v:121223$4823_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:121225$4825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:121225$4825_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:121190$4790 - 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- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:121230$4830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:121230$4830_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:121232$4832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:121232$4832_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:121233$4833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i 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\$7 - connect \Y $reduce_and$libresoc.v:121247$4847_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:121213$4813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$libresoc.v:121213$4813_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:121217$4817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:121217$4817_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:121218$4818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:121218$4818_Y - end - attribute \src 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connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:121249$4849_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121341.12-121377.4" - cell \alu_div0 \alu_div0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_div0_cr_a - connect \cr_a_ok \cr_a_ok - connect \logical_op__data_len \alu_div0_logical_op__data_len - connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok - connect \logical_op__input_carry \alu_div0_logical_op__input_carry - connect \logical_op__insn \alu_div0_logical_op__insn - connect \logical_op__insn_type \alu_div0_logical_op__insn_type - connect \logical_op__invert_in \alu_div0_logical_op__invert_in - connect \logical_op__invert_out \alu_div0_logical_op__invert_out - connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit - connect \logical_op__is_signed \alu_div0_logical_op__is_signed - connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok - connect \logical_op__output_carry \alu_div0_logical_op__output_carry - connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok - connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc - connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 - connect \logical_op__zero_a \alu_div0_logical_op__zero_a - connect \n_ready_i \alu_div0_n_ready_i - connect \n_valid_o \alu_div0_n_valid_o - connect \o \alu_div0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_div0_p_ready_o - connect \p_valid_i \alu_div0_p_valid_i - connect \ra \alu_div0_ra - connect \rb \alu_div0_rb - connect \xer_ov \alu_div0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_div0_xer_so - connect \xer_so$1 \alu_div0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121378.14-121384.4" - cell \alu_l$90 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121385.15-121391.4" - cell \alui_l$89 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121392.14-121398.4" - cell \opc_l$85 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121399.14-121405.4" - cell \req_l$86 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121406.14-121412.4" - cell \rok_l$88 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121413.14-121418.4" - cell \rst_l$87 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:121419.14-121425.4" - cell \src_l$84 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:120545.7-120545.20" - process $proc$libresoc.v:120545$5025 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:120675.7-120675.24" - process $proc$libresoc.v:120675$5026 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:120685.13-120685.49" - process $proc$libresoc.v:120685$5027 - assign { } { } - assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:120702.14-120702.52" - process $proc$libresoc.v:120702$5028 - assign { } { } - assign $1\alu_div0_logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:120706.14-120706.72" - process $proc$libresoc.v:120706$5029 - assign { } { } - assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:120710.7-120710.47" - process $proc$libresoc.v:120710$5030 - assign { } { } - assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:120718.13-120718.52" - process $proc$libresoc.v:120718$5031 - assign { } { } - assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:120722.14-120722.47" - process $proc$libresoc.v:120722$5032 - assign { } { } - assign $1\alu_div0_logical_op__insn[31:0] 0 - sync always - sync init - update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:120800.13-120800.51" - process $proc$libresoc.v:120800$5033 - assign { } { } - assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:120804.7-120804.44" - process $proc$libresoc.v:120804$5034 - assign { } { } - assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:120808.7-120808.45" - process $proc$libresoc.v:120808$5035 - assign { } { } - assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:120812.7-120812.43" - process $proc$libresoc.v:120812$5036 - assign { } { } - assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:120816.7-120816.44" - process $proc$libresoc.v:120816$5037 - assign { } { } - assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:120820.7-120820.41" - process $proc$libresoc.v:120820$5038 - assign { } { } - assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:120824.7-120824.41" - process $proc$libresoc.v:120824$5039 - assign { } { } - assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:120828.7-120828.47" - process $proc$libresoc.v:120828$5040 - assign { } { } - assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:120832.7-120832.41" - process $proc$libresoc.v:120832$5041 - assign { } { } - assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:120836.7-120836.41" - process $proc$libresoc.v:120836$5042 - assign { } { } - assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:120840.7-120840.44" - process $proc$libresoc.v:120840$5043 - assign { } { } - assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:120844.7-120844.41" - process $proc$libresoc.v:120844$5044 - assign { } { } - assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:120870.7-120870.26" - process $proc$libresoc.v:120870$5045 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:120878.7-120878.25" - process $proc$libresoc.v:120878$5046 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:120890.7-120890.27" - process $proc$libresoc.v:120890$5047 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:120924.14-120924.47" - process $proc$libresoc.v:120924$5048 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:120928.7-120928.27" - process $proc$libresoc.v:120928$5049 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:120932.13-120932.33" - process $proc$libresoc.v:120932$5050 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:120936.7-120936.30" - process $proc$libresoc.v:120936$5051 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:120940.13-120940.35" - process $proc$libresoc.v:120940$5052 - assign { } { } - assign $1\data_r2__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] - end - attribute \src "libresoc.v:120944.7-120944.32" - process $proc$libresoc.v:120944$5053 - assign { } { } - assign $1\data_r2__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:120948.7-120948.29" - process $proc$libresoc.v:120948$5054 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:120952.7-120952.32" - process $proc$libresoc.v:120952$5055 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:120972.7-120972.25" - process $proc$libresoc.v:120972$5056 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:120976.7-120976.25" - process $proc$libresoc.v:120976$5057 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:121107.13-121107.30" - process $proc$libresoc.v:121107$5058 - assign { } { } - assign $1\prev_wr_go[3:0] 4'0000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[3:0] - end - attribute \src "libresoc.v:121115.13-121115.31" - process $proc$libresoc.v:121115$5059 - assign { } { } - assign $1\req_l_r_req[3:0] 4'1111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[3:0] - end - attribute \src "libresoc.v:121119.13-121119.31" - process $proc$libresoc.v:121119$5060 - assign { } { } - assign $1\req_l_s_req[3:0] 4'0000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[3:0] - end - attribute \src "libresoc.v:121131.7-121131.26" - process $proc$libresoc.v:121131$5061 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:121135.7-121135.26" - process $proc$libresoc.v:121135$5062 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:121139.7-121139.25" - process $proc$libresoc.v:121139$5063 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:121143.7-121143.25" - process $proc$libresoc.v:121143$5064 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:121157.13-121157.31" - process $proc$libresoc.v:121157$5065 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "libresoc.v:121161.13-121161.31" - process $proc$libresoc.v:121161$5066 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "libresoc.v:121169.14-121169.43" - process $proc$libresoc.v:121169$5067 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:121173.14-121173.43" - process $proc$libresoc.v:121173$5068 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:121177.7-121177.20" - process $proc$libresoc.v:121177$5069 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "libresoc.v:121253.3-121254.39" - process $proc$libresoc.v:121253$4853 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:121255.3-121256.43" - process $proc$libresoc.v:121255$4854 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:121257.3-121258.29" - process $proc$libresoc.v:121257$4855 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "libresoc.v:121259.3-121260.29" - process $proc$libresoc.v:121259$4856 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:121261.3-121262.29" - process $proc$libresoc.v:121261$4857 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:121263.3-121264.47" - process $proc$libresoc.v:121263$4858 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:121265.3-121266.53" - process $proc$libresoc.v:121265$4859 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:121267.3-121268.47" - process $proc$libresoc.v:121267$4860 - assign { } { } - assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next - sync posedge \coresync_clk - update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] - end - attribute \src "libresoc.v:121269.3-121270.53" - process $proc$libresoc.v:121269$4861 - assign { } { } - assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:121271.3-121272.43" - process $proc$libresoc.v:121271$4862 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:121273.3-121274.49" - process $proc$libresoc.v:121273$4863 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:121275.3-121276.37" - process $proc$libresoc.v:121275$4864 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:121277.3-121278.43" - process $proc$libresoc.v:121277$4865 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:121279.3-121280.77" - process $proc$libresoc.v:121279$4866 - assign { } { } - assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next - sync posedge \coresync_clk - update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:121281.3-121282.73" - process $proc$libresoc.v:121281$4867 - assign { } { } - assign $0\alu_div0_logical_op__fn_unit[11:0] \alu_div0_logical_op__fn_unit$next - sync posedge \coresync_clk - update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:121283.3-121284.87" - process $proc$libresoc.v:121283$4868 - assign { } { } - assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:121285.3-121286.83" - process $proc$libresoc.v:121285$4869 - assign { } { } - assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:121287.3-121288.71" - process $proc$libresoc.v:121287$4870 - assign { } { } - assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next - sync posedge \coresync_clk - update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:121289.3-121290.71" - process $proc$libresoc.v:121289$4871 - assign { } { } - assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:121291.3-121292.71" - process $proc$libresoc.v:121291$4872 - assign { } { } - assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next - sync posedge \coresync_clk - update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:121293.3-121294.71" - process $proc$libresoc.v:121293$4873 - assign { } { } - assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next - sync posedge \coresync_clk - update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:121295.3-121296.77" - process $proc$libresoc.v:121295$4874 - assign { } { } - assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next - sync posedge \coresync_clk - update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:121297.3-121298.71" - process $proc$libresoc.v:121297$4875 - assign { } { } - assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next - sync posedge \coresync_clk - update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:121299.3-121300.81" - process $proc$libresoc.v:121299$4876 - assign { } { } - assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next - sync posedge \coresync_clk - update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:121301.3-121302.79" - process $proc$libresoc.v:121301$4877 - assign { } { } - assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next - sync posedge \coresync_clk - update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:121303.3-121304.77" - process $proc$libresoc.v:121303$4878 - assign { } { } - assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next - sync posedge \coresync_clk - update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:121305.3-121306.83" - process $proc$libresoc.v:121305$4879 - assign { } { } - assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next - sync posedge \coresync_clk - update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:121307.3-121308.75" - process $proc$libresoc.v:121307$4880 - assign { } { } - assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next - sync posedge \coresync_clk - update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:121309.3-121310.77" - process $proc$libresoc.v:121309$4881 - assign { } { } - assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next - sync posedge \coresync_clk - update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:121311.3-121312.75" - process $proc$libresoc.v:121311$4882 - assign { } { } - assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next - sync posedge \coresync_clk - update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:121313.3-121314.67" - process $proc$libresoc.v:121313$4883 - assign { } { } - assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next - sync posedge \coresync_clk - update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:121315.3-121316.39" - process $proc$libresoc.v:121315$4884 - assign { } { } - assign $0\req_l_r_req[3:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[3:0] - end - attribute \src "libresoc.v:121317.3-121318.39" - process $proc$libresoc.v:121317$4885 - assign { } { } - assign $0\req_l_s_req[3:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[3:0] - end - attribute \src "libresoc.v:121319.3-121320.39" - process $proc$libresoc.v:121319$4886 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "libresoc.v:121321.3-121322.39" - process $proc$libresoc.v:121321$4887 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "libresoc.v:121323.3-121324.39" - process $proc$libresoc.v:121323$4888 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:121325.3-121326.39" - process $proc$libresoc.v:121325$4889 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:121327.3-121328.39" - process $proc$libresoc.v:121327$4890 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:121329.3-121330.39" - process $proc$libresoc.v:121329$4891 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:121331.3-121332.41" - process $proc$libresoc.v:121331$4892 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:121333.3-121334.41" - process $proc$libresoc.v:121333$4893 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:121335.3-121336.37" - process $proc$libresoc.v:121335$4894 - assign { } { } - assign $0\prev_wr_go[3:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[3:0] - end - attribute \src "libresoc.v:121337.3-121338.40" - process $proc$libresoc.v:121337$4895 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:121339.3-121340.25" - process $proc$libresoc.v:121339$4896 - assign { } { } - assign $0\all_rd_dly[0:0] \$10 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:121426.3-121435.6" - process $proc$libresoc.v:121426$4897 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:121427.5-121427.29" - switch \initial - attribute \src "libresoc.v:121427.9-121427.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$46 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:121436.3-121444.6" - process $proc$libresoc.v:121436$4898 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$4899 $1\rok_l_s_rdok$next[0:0]$4900 - attribute \src "libresoc.v:121437.5-121437.29" - switch \initial - attribute \src "libresoc.v:121437.9-121437.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$4900 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$4900 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4899 - end - attribute \src "libresoc.v:121445.3-121453.6" - process $proc$libresoc.v:121445$4901 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$4902 $1\rok_l_r_rdok$next[0:0]$4903 - attribute \src "libresoc.v:121446.5-121446.29" - switch \initial - attribute \src "libresoc.v:121446.9-121446.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$4903 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$4903 \$64 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4902 - end - attribute \src "libresoc.v:121454.3-121462.6" - process $proc$libresoc.v:121454$4904 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$4905 $1\rst_l_s_rst$next[0:0]$4906 - attribute \src "libresoc.v:121455.5-121455.29" - switch \initial - attribute \src "libresoc.v:121455.9-121455.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$4906 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$4906 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4905 - end - attribute \src "libresoc.v:121463.3-121471.6" - process $proc$libresoc.v:121463$4907 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$4908 $1\rst_l_r_rst$next[0:0]$4909 - attribute \src "libresoc.v:121464.5-121464.29" - switch \initial - attribute \src "libresoc.v:121464.9-121464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$4909 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$4909 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4908 - end - attribute \src "libresoc.v:121472.3-121480.6" - process $proc$libresoc.v:121472$4910 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$4911 $1\opc_l_s_opc$next[0:0]$4912 - attribute \src "libresoc.v:121473.5-121473.29" - switch \initial - attribute \src "libresoc.v:121473.9-121473.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$4912 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$4912 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4911 - end - attribute \src "libresoc.v:121481.3-121489.6" - process $proc$libresoc.v:121481$4913 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$4914 $1\opc_l_r_opc$next[0:0]$4915 - attribute \src "libresoc.v:121482.5-121482.29" - switch \initial - attribute \src "libresoc.v:121482.9-121482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$4915 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$4915 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4914 - end - attribute \src "libresoc.v:121490.3-121498.6" - process $proc$libresoc.v:121490$4916 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$4917 $1\src_l_s_src$next[2:0]$4918 - attribute \src "libresoc.v:121491.5-121491.29" - switch \initial - attribute \src "libresoc.v:121491.9-121491.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$4918 3'000 - case - assign $1\src_l_s_src$next[2:0]$4918 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4917 - end - attribute \src "libresoc.v:121499.3-121507.6" - process $proc$libresoc.v:121499$4919 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$4920 $1\src_l_r_src$next[2:0]$4921 - attribute \src "libresoc.v:121500.5-121500.29" - switch \initial - attribute \src "libresoc.v:121500.9-121500.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$4921 3'111 - case - assign $1\src_l_r_src$next[2:0]$4921 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4920 - end - attribute \src "libresoc.v:121508.3-121516.6" - process $proc$libresoc.v:121508$4922 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[3:0]$4923 $1\req_l_s_req$next[3:0]$4924 - attribute \src "libresoc.v:121509.5-121509.29" - switch \initial - attribute \src "libresoc.v:121509.9-121509.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[3:0]$4924 4'0000 - case - assign $1\req_l_s_req$next[3:0]$4924 \$66 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4923 - end - attribute \src "libresoc.v:121517.3-121525.6" - process $proc$libresoc.v:121517$4925 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[3:0]$4926 $1\req_l_r_req$next[3:0]$4927 - attribute \src "libresoc.v:121518.5-121518.29" - switch \initial - attribute \src "libresoc.v:121518.9-121518.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[3:0]$4927 4'1111 - case - assign $1\req_l_r_req$next[3:0]$4927 \$68 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4926 - end - attribute \src "libresoc.v:121526.3-121564.6" - process $proc$libresoc.v:121526$4928 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__data_len$next[3:0]$4929 $1\alu_div0_logical_op__data_len$next[3:0]$4947 - assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4930 $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__input_carry$next[1:0]$4933 $1\alu_div0_logical_op__input_carry$next[1:0]$4951 - assign $0\alu_div0_logical_op__insn$next[31:0]$4934 $1\alu_div0_logical_op__insn$next[31:0]$4952 - assign $0\alu_div0_logical_op__insn_type$next[6:0]$4935 $1\alu_div0_logical_op__insn_type$next[6:0]$4953 - assign $0\alu_div0_logical_op__invert_in$next[0:0]$4936 $1\alu_div0_logical_op__invert_in$next[0:0]$4954 - assign $0\alu_div0_logical_op__invert_out$next[0:0]$4937 $1\alu_div0_logical_op__invert_out$next[0:0]$4955 - assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4938 $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 - assign $0\alu_div0_logical_op__is_signed$next[0:0]$4939 $1\alu_div0_logical_op__is_signed$next[0:0]$4957 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__output_carry$next[0:0]$4942 $1\alu_div0_logical_op__output_carry$next[0:0]$4960 - assign { } { } - assign { } { } - assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4945 $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 - assign $0\alu_div0_logical_op__zero_a$next[0:0]$4946 $1\alu_div0_logical_op__zero_a$next[0:0]$4964 - assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4931 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 - assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4932 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4966 - assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4940 $2\alu_div0_logical_op__oe__oe$next[0:0]$4967 - assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4941 $2\alu_div0_logical_op__oe__ok$next[0:0]$4968 - assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4943 $2\alu_div0_logical_op__rc__ok$next[0:0]$4969 - assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4944 $2\alu_div0_logical_op__rc__rc$next[0:0]$4970 - attribute \src "libresoc.v:121527.5-121527.29" - switch \initial - attribute \src "libresoc.v:121527.9-121527.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_div0_logical_op__insn$next[31:0]$4952 $1\alu_div0_logical_op__data_len$next[3:0]$4947 $1\alu_div0_logical_op__is_signed$next[0:0]$4957 $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 $1\alu_div0_logical_op__output_carry$next[0:0]$4960 $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 $1\alu_div0_logical_op__invert_out$next[0:0]$4955 $1\alu_div0_logical_op__input_carry$next[1:0]$4951 $1\alu_div0_logical_op__zero_a$next[0:0]$4964 $1\alu_div0_logical_op__invert_in$next[0:0]$4954 $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 $1\alu_div0_logical_op__insn_type$next[6:0]$4953 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } - case - assign $1\alu_div0_logical_op__data_len$next[3:0]$4947 \alu_div0_logical_op__data_len - assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4948 \alu_div0_logical_op__fn_unit - assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 \alu_div0_logical_op__imm_data__data - assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 \alu_div0_logical_op__imm_data__ok - assign $1\alu_div0_logical_op__input_carry$next[1:0]$4951 \alu_div0_logical_op__input_carry - assign $1\alu_div0_logical_op__insn$next[31:0]$4952 \alu_div0_logical_op__insn - assign $1\alu_div0_logical_op__insn_type$next[6:0]$4953 \alu_div0_logical_op__insn_type - assign $1\alu_div0_logical_op__invert_in$next[0:0]$4954 \alu_div0_logical_op__invert_in - assign $1\alu_div0_logical_op__invert_out$next[0:0]$4955 \alu_div0_logical_op__invert_out - assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4956 \alu_div0_logical_op__is_32bit - assign $1\alu_div0_logical_op__is_signed$next[0:0]$4957 \alu_div0_logical_op__is_signed - assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 \alu_div0_logical_op__oe__oe - assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 \alu_div0_logical_op__oe__ok - assign $1\alu_div0_logical_op__output_carry$next[0:0]$4960 \alu_div0_logical_op__output_carry - assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 \alu_div0_logical_op__rc__ok - assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 \alu_div0_logical_op__rc__rc - assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4963 \alu_div0_logical_op__write_cr0 - assign $1\alu_div0_logical_op__zero_a$next[0:0]$4964 \alu_div0_logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4966 1'0 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4970 1'0 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4969 1'0 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4967 1'0 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4968 1'0 - case - assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4965 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4949 - assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4966 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4950 - assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4967 $1\alu_div0_logical_op__oe__oe$next[0:0]$4958 - assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4968 $1\alu_div0_logical_op__oe__ok$next[0:0]$4959 - assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4969 $1\alu_div0_logical_op__rc__ok$next[0:0]$4961 - assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4970 $1\alu_div0_logical_op__rc__rc$next[0:0]$4962 - end - sync always - update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4929 - update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4930 - update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4931 - update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4932 - update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4933 - update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4934 - update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4935 - update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4936 - update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4937 - update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4938 - update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4939 - update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4940 - update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4941 - update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4942 - update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4943 - update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4944 - update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4945 - update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4946 - end - attribute \src "libresoc.v:121565.3-121586.6" - process $proc$libresoc.v:121565$4971 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$4972 $2\data_r0__o$next[63:0]$4976 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$4973 $3\data_r0__o_ok$next[0:0]$4978 - attribute \src "libresoc.v:121566.5-121566.29" - switch \initial - attribute \src "libresoc.v:121566.9-121566.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$4975 $1\data_r0__o$next[63:0]$4974 } { \o_ok \alu_div0_o } - case - assign $1\data_r0__o$next[63:0]$4974 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$4975 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$4977 $2\data_r0__o$next[63:0]$4976 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$4976 $1\data_r0__o$next[63:0]$4974 - assign $2\data_r0__o_ok$next[0:0]$4977 $1\data_r0__o_ok$next[0:0]$4975 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$4978 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$4978 $2\data_r0__o_ok$next[0:0]$4977 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$4972 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4973 - end - attribute \src "libresoc.v:121587.3-121608.6" - process $proc$libresoc.v:121587$4979 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$4980 $2\data_r1__cr_a$next[3:0]$4984 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$4981 $3\data_r1__cr_a_ok$next[0:0]$4986 - attribute \src "libresoc.v:121588.5-121588.29" - switch \initial - attribute \src "libresoc.v:121588.9-121588.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$4983 $1\data_r1__cr_a$next[3:0]$4982 } { \cr_a_ok \alu_div0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$4982 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$4983 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$4985 $2\data_r1__cr_a$next[3:0]$4984 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$4984 $1\data_r1__cr_a$next[3:0]$4982 - assign $2\data_r1__cr_a_ok$next[0:0]$4985 $1\data_r1__cr_a_ok$next[0:0]$4983 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$4986 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$4986 $2\data_r1__cr_a_ok$next[0:0]$4985 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4980 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4981 - end - attribute \src "libresoc.v:121609.3-121630.6" - process $proc$libresoc.v:121609$4987 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$4988 $2\data_r2__xer_ov$next[1:0]$4992 - assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$4989 $3\data_r2__xer_ov_ok$next[0:0]$4994 - attribute \src "libresoc.v:121610.5-121610.29" - switch \initial - attribute \src "libresoc.v:121610.9-121610.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$4991 $1\data_r2__xer_ov$next[1:0]$4990 } { \xer_ov_ok \alu_div0_xer_ov } - case - assign $1\data_r2__xer_ov$next[1:0]$4990 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$4991 \data_r2__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$4993 $2\data_r2__xer_ov$next[1:0]$4992 } 3'000 - case - assign $2\data_r2__xer_ov$next[1:0]$4992 $1\data_r2__xer_ov$next[1:0]$4990 - assign $2\data_r2__xer_ov_ok$next[0:0]$4993 $1\data_r2__xer_ov_ok$next[0:0]$4991 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$4994 1'0 - case - assign $3\data_r2__xer_ov_ok$next[0:0]$4994 $2\data_r2__xer_ov_ok$next[0:0]$4993 - end - sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4988 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4989 - end - attribute \src "libresoc.v:121631.3-121652.6" - process $proc$libresoc.v:121631$4995 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_so$next[0:0]$4996 $2\data_r3__xer_so$next[0:0]$5000 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$4997 $3\data_r3__xer_so_ok$next[0:0]$5002 - attribute \src "libresoc.v:121632.5-121632.29" - switch \initial - attribute \src "libresoc.v:121632.9-121632.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$4999 $1\data_r3__xer_so$next[0:0]$4998 } { \xer_so_ok \alu_div0_xer_so } - case - assign $1\data_r3__xer_so$next[0:0]$4998 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$4999 \data_r3__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$5001 $2\data_r3__xer_so$next[0:0]$5000 } 2'00 - case - assign $2\data_r3__xer_so$next[0:0]$5000 $1\data_r3__xer_so$next[0:0]$4998 - assign $2\data_r3__xer_so_ok$next[0:0]$5001 $1\data_r3__xer_so_ok$next[0:0]$4999 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$5002 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$5002 $2\data_r3__xer_so_ok$next[0:0]$5001 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4996 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4997 - end - attribute \src "libresoc.v:121653.3-121662.6" - process $proc$libresoc.v:121653$5003 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$5004 $1\src_r0$next[63:0]$5005 - attribute \src "libresoc.v:121654.5-121654.29" - switch \initial - attribute \src "libresoc.v:121654.9-121654.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$5005 \src_or_imm - case - assign $1\src_r0$next[63:0]$5005 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$5004 - end - attribute \src "libresoc.v:121663.3-121672.6" - process $proc$libresoc.v:121663$5006 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$5007 $1\src_r1$next[63:0]$5008 - attribute \src "libresoc.v:121664.5-121664.29" - switch \initial - attribute \src "libresoc.v:121664.9-121664.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel$82 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$5008 \src_or_imm$85 - case - assign $1\src_r1$next[63:0]$5008 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$5007 - end - attribute \src "libresoc.v:121673.3-121682.6" - process $proc$libresoc.v:121673$5009 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$5010 $1\src_r2$next[0:0]$5011 - attribute \src "libresoc.v:121674.5-121674.29" - switch \initial - attribute \src "libresoc.v:121674.9-121674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$5011 \src3_i - case - assign $1\src_r2$next[0:0]$5011 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$5010 - end - attribute \src "libresoc.v:121683.3-121691.6" - process $proc$libresoc.v:121683$5012 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$5013 $1\alui_l_r_alui$next[0:0]$5014 - attribute \src "libresoc.v:121684.5-121684.29" - switch \initial - attribute \src "libresoc.v:121684.9-121684.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$5014 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$5014 \$94 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5013 - end - attribute \src "libresoc.v:121692.3-121700.6" - process $proc$libresoc.v:121692$5015 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$5016 $1\alu_l_r_alu$next[0:0]$5017 - attribute \src "libresoc.v:121693.5-121693.29" - switch \initial - attribute \src "libresoc.v:121693.9-121693.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$5017 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$5017 \$96 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5016 - end - attribute \src "libresoc.v:121701.3-121710.6" - process $proc$libresoc.v:121701$5018 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:121702.5-121702.29" - switch \initial - attribute \src "libresoc.v:121702.9-121702.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$122 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:121711.3-121720.6" - process $proc$libresoc.v:121711$5019 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:121712.5-121712.29" - switch \initial - attribute \src "libresoc.v:121712.9-121712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$124 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "libresoc.v:121721.3-121730.6" - process $proc$libresoc.v:121721$5020 - assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:121722.5-121722.29" - switch \initial - attribute \src "libresoc.v:121722.9-121722.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$126 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ov - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "libresoc.v:121731.3-121740.6" - process $proc$libresoc.v:121731$5021 - assign { } { } - assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:121732.5-121732.29" - switch \initial - attribute \src "libresoc.v:121732.9-121732.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$128 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "libresoc.v:121741.3-121749.6" - process $proc$libresoc.v:121741$5022 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[3:0]$5023 $1\prev_wr_go$next[3:0]$5024 - attribute \src "libresoc.v:121742.5-121742.29" - switch \initial - attribute \src "libresoc.v:121742.9-121742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[3:0]$5024 4'0000 - case - assign $1\prev_wr_go$next[3:0]$5024 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5023 - end - connect \$100 $not$libresoc.v:121190$4790_Y - connect \$102 $not$libresoc.v:121191$4791_Y - connect \$104 $and$libresoc.v:121192$4792_Y - connect \$106 $not$libresoc.v:121193$4793_Y - connect \$108 $and$libresoc.v:121194$4794_Y - connect \$10 $and$libresoc.v:121195$4795_Y - connect \$110 $and$libresoc.v:121196$4796_Y - connect \$112 $and$libresoc.v:121197$4797_Y - connect \$114 $and$libresoc.v:121198$4798_Y - connect \$116 $and$libresoc.v:121199$4799_Y - connect \$118 $and$libresoc.v:121200$4800_Y - connect \$120 $and$libresoc.v:121201$4801_Y - connect \$122 $and$libresoc.v:121202$4802_Y - connect \$124 $and$libresoc.v:121203$4803_Y - connect \$126 $and$libresoc.v:121204$4804_Y - connect \$128 $and$libresoc.v:121205$4805_Y - connect \$12 $not$libresoc.v:121206$4806_Y - connect \$14 $and$libresoc.v:121207$4807_Y - connect \$16 $not$libresoc.v:121208$4808_Y - connect \$18 $and$libresoc.v:121209$4809_Y - connect \$20 $and$libresoc.v:121210$4810_Y - connect \$24 $not$libresoc.v:121211$4811_Y - connect \$26 $and$libresoc.v:121212$4812_Y - connect \$23 $reduce_or$libresoc.v:121213$4813_Y - connect \$22 $not$libresoc.v:121214$4814_Y - connect \$2 $and$libresoc.v:121215$4815_Y - connect \$30 $and$libresoc.v:121216$4816_Y - connect \$32 $reduce_or$libresoc.v:121217$4817_Y - connect \$34 $reduce_or$libresoc.v:121218$4818_Y - connect \$36 $or$libresoc.v:121219$4819_Y - connect \$38 $not$libresoc.v:121220$4820_Y - connect \$40 $and$libresoc.v:121221$4821_Y - connect \$42 $and$libresoc.v:121222$4822_Y - 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\$86 $ternary$libresoc.v:121245$4845_Y - connect \$88 $ternary$libresoc.v:121246$4846_Y - connect \$4 $reduce_and$libresoc.v:121247$4847_Y - connect \$90 $ternary$libresoc.v:121248$4848_Y - connect \$92 $ternary$libresoc.v:121249$4849_Y - connect \$94 $and$libresoc.v:121250$4850_Y - connect \$96 $and$libresoc.v:121251$4851_Y - connect \$98 $and$libresoc.v:121252$4852_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$120 - connect \cu_rd__rel_o \$108 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_div0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_div0_p_valid_i \alui_l_q_alui - connect \alu_div0_xer_so$1 \$92 - connect \alu_div0_rb \$90 - connect \alu_div0_ra \$88 - connect \src_or_imm$85 \$86 - connect \src_sel$82 \$83 - connect \src_or_imm \$80 - connect \src_sel \$78 - connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } - connect \reset_r \$62 - connect \reset_w \$60 - connect \rst_r \$58 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 18 \trap_op__msr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 8 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 22 \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 7 \trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 21 \trap_op__traptype$8 - connect \fast2$14 \fast2 - connect \fast1$13 \fast1 - connect \rb$12 \rb - connect \ra$11 \ra - connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \muxid$1 \muxid -end -attribute \src "libresoc.v:122126.1-122297.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fast" -attribute \generator "nMigen" -module \fast - attribute \src "libresoc.v:122221.3-122227.6" - wire width 3 $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 - attribute \src "libresoc.v:122221.3-122227.6" - wire width 64 $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 - attribute \src "libresoc.v:122221.3-122227.6" - wire width 64 $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 - attribute \src "libresoc.v:122221.3-122227.6" - wire width 3 $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 - attribute \src "libresoc.v:122221.3-122227.6" - wire width 64 $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 - attribute \src "libresoc.v:122221.3-122227.6" - wire width 64 $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 - attribute \src "libresoc.v:122221.3-122227.6" - wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:122221.3-122227.6" - wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:122221.3-122227.6" - wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:122127.7-122127.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:122278.3-122287.6" - wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:122250.3-122258.6" - wire $0\ren_delay$10$next[0:0]$5110 - attribute \src "libresoc.v:122203.3-122204.43" - wire $0\ren_delay$10[0:0]$5093 - attribute \src "libresoc.v:122178.7-122178.28" - wire $0\ren_delay$10[0:0]$5130 - attribute \src "libresoc.v:122269.3-122277.6" - wire $0\ren_delay$11$next[0:0]$5114 - attribute \src "libresoc.v:122201.3-122202.43" - wire $0\ren_delay$11[0:0]$5091 - attribute \src "libresoc.v:122182.7-122182.28" - wire $0\ren_delay$11[0:0]$5132 - attribute \src "libresoc.v:122231.3-122239.6" - wire $0\ren_delay$next[0:0]$5106 - attribute \src "libresoc.v:122205.3-122206.35" - wire $0\ren_delay[0:0] - attribute \src "libresoc.v:122240.3-122249.6" - wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:122259.3-122268.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:122278.3-122287.6" - wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:122250.3-122258.6" - wire $1\ren_delay$10$next[0:0]$5111 - attribute \src "libresoc.v:122269.3-122277.6" - wire $1\ren_delay$11$next[0:0]$5115 - attribute \src "libresoc.v:122231.3-122239.6" - wire $1\ren_delay$next[0:0]$5107 - attribute \src "libresoc.v:122176.7-122176.23" - wire $1\ren_delay[0:0] - attribute \src "libresoc.v:122240.3-122249.6" - wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:122259.3-122268.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:122228.26-122228.32" - wire width 64 $memrd$\memory$libresoc.v:122228$5102_DATA - attribute \src "libresoc.v:122229.30-122229.36" - wire width 64 $memrd$\memory$libresoc.v:122229$5103_DATA - attribute \src "libresoc.v:122230.30-122230.36" - wire width 64 $memrd$\memory$libresoc.v:122230$5104_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:122225$5088_ADDR - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122225$5088_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122225$5088_EN - attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:122226$5089_ADDR - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122226$5089_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:122226$5089_EN - attribute \src "libresoc.v:122218.13-122218.16" - wire width 3 \_0_ - attribute \src "libresoc.v:122219.13-122219.16" - wire width 3 \_1_ - attribute \src "libresoc.v:122220.13-122220.16" - wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 15 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 14 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 16 \dest1__wen - attribute \src "libresoc.v:122127.7-122127.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 2 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 5 \issue__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 3 \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \issue__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 9 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 8 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 12 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 11 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \src2__ren - attribute \src "libresoc.v:122207.14-122207.20" - memory width 64 size 8 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5117 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5117 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 0 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5118 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5118 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 1 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5119 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5119 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 2 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5120 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5120 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 3 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5121 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5121 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 4 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5122 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5122 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 5 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5123 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5123 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 6 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5124 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5124 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 7 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:122228.26-122228.32" - cell $memrd $memrd$\memory$libresoc.v:122228$5102 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:122228$5102_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:122229.30-122229.36" - cell $memrd $memrd$\memory$libresoc.v:122229$5103 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_1_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:122229$5103_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:122230.30-122230.36" - cell $memrd $memrd$\memory$libresoc.v:122230$5104 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:122230$5104_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5125 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5125 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:122225$5088_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:122225$5088_DATA - connect \EN $memwr$\memory$libresoc.v:122225$5088_EN - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5126 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5126 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:122226$5089_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:122226$5089_DATA - connect \EN $memwr$\memory$libresoc.v:122226$5089_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5133 - sync always - sync init - end - attribute \src "libresoc.v:122127.7-122127.20" - process $proc$libresoc.v:122127$5127 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:122176.7-122176.23" - process $proc$libresoc.v:122176$5128 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] - end - attribute \src "libresoc.v:122178.7-122178.28" - process $proc$libresoc.v:122178$5129 - assign { } { } - assign $0\ren_delay$10[0:0]$5130 1'0 - sync always - sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5130 - end - attribute \src "libresoc.v:122182.7-122182.28" - process $proc$libresoc.v:122182$5131 - assign { } { } - assign $0\ren_delay$11[0:0]$5132 1'0 - sync always - sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5132 - end - attribute \src "libresoc.v:122201.3-122202.43" - process $proc$libresoc.v:122201$5090 - assign { } { } - assign $0\ren_delay$11[0:0]$5091 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5091 - end - attribute \src "libresoc.v:122203.3-122204.43" - process $proc$libresoc.v:122203$5092 - assign { } { } - assign $0\ren_delay$10[0:0]$5093 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5093 - end - attribute \src "libresoc.v:122205.3-122206.35" - process $proc$libresoc.v:122205$5094 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:122221.3-122227.6" - process $proc$libresoc.v:122221$5095 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 3'xxx - assign $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 3'xxx - assign $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[2:0] \src1__addr - assign $0\_1_[2:0] \src2__addr - assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:122225.5-122225.62" - switch \issue__wen - attribute \src "libresoc.v:122225.9-122225.19" - case 1'1 - assign $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 \issue__data_i - assign $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - attribute \src "libresoc.v:122226.5-122226.58" - switch \dest1__wen - attribute \src "libresoc.v:122226.9-122226.19" - case 1'1 - assign $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 \dest1__addr - assign $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[2:0] - update \_1_ $0\_1_[2:0] - update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:122225$5088_ADDR $0$memwr$\memory$libresoc.v:122225$5088_ADDR[2:0]$5096 - update $memwr$\memory$libresoc.v:122225$5088_DATA $0$memwr$\memory$libresoc.v:122225$5088_DATA[63:0]$5097 - update $memwr$\memory$libresoc.v:122225$5088_EN $0$memwr$\memory$libresoc.v:122225$5088_EN[63:0]$5098 - update $memwr$\memory$libresoc.v:122226$5089_ADDR $0$memwr$\memory$libresoc.v:122226$5089_ADDR[2:0]$5099 - update $memwr$\memory$libresoc.v:122226$5089_DATA $0$memwr$\memory$libresoc.v:122226$5089_DATA[63:0]$5100 - update $memwr$\memory$libresoc.v:122226$5089_EN $0$memwr$\memory$libresoc.v:122226$5089_EN[63:0]$5101 - end - attribute \src "libresoc.v:122231.3-122239.6" - process $proc$libresoc.v:122231$5105 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$5106 $1\ren_delay$next[0:0]$5107 - attribute \src "libresoc.v:122232.5-122232.29" - switch \initial - attribute \src "libresoc.v:122232.9-122232.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[0:0]$5107 1'0 - case - assign $1\ren_delay$next[0:0]$5107 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5106 - end - attribute \src "libresoc.v:122240.3-122249.6" - process $proc$libresoc.v:122240$5108 - assign { } { } - assign { } { } - assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:122241.5-122241.29" - switch \initial - attribute \src "libresoc.v:122241.9-122241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[63:0] \memory_r_data - case - assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src1__data_o $0\src1__data_o[63:0] - end - attribute \src "libresoc.v:122250.3-122258.6" - process $proc$libresoc.v:122250$5109 - assign { } { } - assign { } { } - assign $0\ren_delay$10$next[0:0]$5110 $1\ren_delay$10$next[0:0]$5111 - attribute \src "libresoc.v:122251.5-122251.29" - switch \initial - attribute \src "libresoc.v:122251.9-122251.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$10$next[0:0]$5111 1'0 - case - assign $1\ren_delay$10$next[0:0]$5111 \src2__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5110 - end - attribute \src "libresoc.v:122259.3-122268.6" - process $proc$libresoc.v:122259$5112 - assign { } { } - assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:122260.5-122260.29" - switch \initial - attribute \src "libresoc.v:122260.9-122260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$4 - case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src2__data_o $0\src2__data_o[63:0] - end - attribute \src "libresoc.v:122269.3-122277.6" - process $proc$libresoc.v:122269$5113 - assign { } { } - assign { } { } - assign $0\ren_delay$11$next[0:0]$5114 $1\ren_delay$11$next[0:0]$5115 - attribute \src "libresoc.v:122270.5-122270.29" - switch \initial - attribute \src "libresoc.v:122270.9-122270.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$11$next[0:0]$5115 1'0 - case - assign $1\ren_delay$11$next[0:0]$5115 \issue__ren - end - sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5114 - end - attribute \src "libresoc.v:122278.3-122287.6" - process $proc$libresoc.v:122278$5116 - assign { } { } - assign { } { } - assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:122279.5-122279.29" - switch \initial - attribute \src "libresoc.v:122279.9-122279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\issue__data_o[63:0] \memory_r_data$6 - case - assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \issue__data_o $0\issue__data_o[63:0] - end - connect \memory_r_data $memrd$\memory$libresoc.v:122228$5102_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:122229$5103_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:122230$5104_DATA - connect \memory_w_data$9 \issue__data_i - connect \memory_w_en$7 \issue__wen - connect \memory_w_addr$8 \issue__addr$1 - connect \memory_w_data \dest1__data_i - connect \memory_w_en \dest1__wen - connect \memory_w_addr \dest1__addr - connect \memory_r_addr$5 \issue__addr - connect \memory_r_addr$3 \src2__addr - connect \memory_r_addr \src1__addr -end -attribute \src "libresoc.v:122301.1-124221.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus" -attribute \generator "nMigen" -module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 257 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 258 \cr_a_ok$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 259 \cr_a_ok$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 260 \cr_a_ok$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 261 \cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 262 \cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 3 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 4 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 25 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 75 \cu_busy_o$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 82 \cu_busy_o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 103 \cu_busy_o$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 31 \cu_busy_o$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 118 \cu_busy_o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 138 \cu_busy_o$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 157 \cu_busy_o$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 42 \cu_busy_o$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 54 \cu_busy_o$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 24 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 30 \cu_issue_i$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 74 \cu_issue_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 81 \cu_issue_i$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 102 \cu_issue_i$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 117 \cu_issue_i$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 137 \cu_issue_i$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 156 \cu_issue_i$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 41 \cu_issue_i$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 53 \cu_issue_i$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 160 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 163 \cu_rd__go_i$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 166 \cu_rd__go_i$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 169 \cu_rd__go_i$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 172 \cu_rd__go_i$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 175 \cu_rd__go_i$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 178 \cu_rd__go_i$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 181 \cu_rd__go_i$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 184 \cu_rd__go_i$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 209 \cu_rd__go_i$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 159 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 162 \cu_rd__rel_o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 165 \cu_rd__rel_o$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 168 \cu_rd__rel_o$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 171 \cu_rd__rel_o$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 174 \cu_rd__rel_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 177 \cu_rd__rel_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 180 \cu_rd__rel_o$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 183 \cu_rd__rel_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 208 \cu_rd__rel_o$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 26 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 76 \cu_rdmaskn_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 83 \cu_rdmaskn_i$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 104 \cu_rdmaskn_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 119 \cu_rdmaskn_i$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 139 \cu_rdmaskn_i$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 158 \cu_rdmaskn_i$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 32 \cu_rdmaskn_i$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 43 \cu_rdmaskn_i$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 55 \cu_rdmaskn_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 5 \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 2 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 221 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 242 \cu_wr__go_i$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 244 \cu_wr__go_i$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 293 \cu_wr__go_i$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 224 \cu_wr__go_i$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 227 \cu_wr__go_i$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 230 \cu_wr__go_i$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 233 \cu_wr__go_i$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 236 \cu_wr__go_i$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 239 \cu_wr__go_i$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 220 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 243 \cu_wr__rel_o$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 292 \cu_wr__rel_o$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 223 \cu_wr__rel_o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 226 \cu_wr__rel_o$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 229 \cu_wr__rel_o$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 232 \cu_wr__rel_o$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 235 \cu_wr__rel_o$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 238 \cu_wr__rel_o$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 241 \cu_wr__rel_o$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 245 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 246 \dest1_o$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 247 \dest1_o$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 248 \dest1_o$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 249 \dest1_o$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 250 \dest1_o$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 251 \dest1_o$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 252 \dest1_o$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 298 \dest1_o$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 256 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 263 \dest2_o$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 265 \dest2_o$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 266 \dest2_o$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 267 \dest2_o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 268 \dest2_o$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 299 \dest2_o$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 301 \dest2_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 310 \dest2_o$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 264 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 272 \dest3_o$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 274 \dest3_o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 281 \dest3_o$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 282 \dest3_o$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 300 \dest3_o$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 302 \dest3_o$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 305 \dest3_o$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 279 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 288 \dest4_o$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 289 \dest4_o$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire output 290 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 295 \fast1_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 296 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 297 \fast2_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 255 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 output 315 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 316 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 325 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 311 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 314 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 317 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 318 \ldst_port0_exc_$signal$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 319 \ldst_port0_exc_$signal$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 320 \ldst_port0_exc_$signal$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 321 \ldst_port0_exc_$signal$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 322 \ldst_port0_exc_$signal$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 323 \ldst_port0_exc_$signal$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 324 \ldst_port0_exc_$signal$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 312 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 313 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 326 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 327 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 328 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 329 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 307 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 303 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 304 \nia_ok$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 253 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 219 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 222 \o_ok$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 225 \o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 228 \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 231 \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 234 \o_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 237 \o_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 240 \o_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 22 \oper_i_alu_alu0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_alu0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_alu0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \oper_i_alu_alu0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_alu0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 33 \oper_i_alu_branch0__cia - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute 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\oper_i_ldst_ldst0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 143 \oper_i_ldst_ldst0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 155 \oper_i_ldst_ldst0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 140 \oper_i_ldst_ldst0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 149 \oper_i_ldst_ldst0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 150 \oper_i_ldst_ldst0__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 154 \oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 147 \oper_i_ldst_ldst0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 148 \oper_i_ldst_ldst0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 146 \oper_i_ldst_ldst0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 145 \oper_i_ldst_ldst0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 153 \oper_i_ldst_ldst0__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 144 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 309 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 161 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 164 \src1_i$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 167 \src1_i$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 170 \src1_i$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 173 \src1_i$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 176 \src1_i$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 179 \src1_i$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 182 \src1_i$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 185 \src1_i$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 213 \src1_i$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 186 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 187 \src2_i$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 188 \src2_i$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 189 \src2_i$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 190 \src2_i$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 191 \src2_i$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 192 \src2_i$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 193 \src2_i$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 216 \src2_i$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 218 \src2_i$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 194 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 195 \src3_i$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 196 \src3_i$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 197 \src3_i$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 199 \src3_i$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 200 \src3_i$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 206 \src3_i$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 210 \src3_i$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 214 \src3_i$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 215 \src3_i$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 198 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 201 \src4_i$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 202 \src4_i$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 207 \src4_i$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 217 \src4_i$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 204 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 205 \src5_i$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 211 \src5_i$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 203 \src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 212 \src6_i$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 269 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 270 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 271 \xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 275 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 276 \xer_ov_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 277 \xer_ov_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 278 \xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 283 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 284 \xer_so_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 285 \xer_so_ok$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 286 \xer_so_ok$131 - attribute \module_not_derived 1 - attribute \src "libresoc.v:123853.8-123895.4" - cell \alu0 \alu0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok - connect \cu_busy_o \cu_busy_o - connect \cu_issue_i \cu_issue_i - connect \cu_rd__go_i \cu_rd__go_i - connect \cu_rd__rel_o \cu_rd__rel_o - connect \cu_rdmaskn_i \cu_rdmaskn_i - connect \cu_wr__go_i \cu_wr__go_i - connect \cu_wr__rel_o \cu_wr__rel_o - connect \dest1_o \dest1_o - connect \dest2_o \dest2_o$115 - connect \dest3_o \dest3_o$122 - connect \dest4_o \dest4_o - connect \dest5_o \dest5_o$132 - connect \o_ok \o_ok - connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data - connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok - connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn - connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok - connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok - connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a - connect \src1_i \src1_i - connect \src2_i \src2_i - connect \src3_i \src3_i$60 - connect \src4_i \src4_i$65 - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:123896.11-123923.4" - cell \branch0 \branch0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$5 - connect \cu_issue_i \cu_issue_i$4 - connect \cu_rd__go_i \cu_rd__go_i$70 - connect \cu_rd__rel_o \cu_rd__rel_o$69 - connect \cu_rdmaskn_i \cu_rdmaskn_i$6 - connect \cu_wr__go_i \cu_wr__go_i$137 - connect \cu_wr__rel_o \cu_wr__rel_o$136 - connect \dest1_o \dest1_o$141 - connect \dest2_o \dest2_o$144 - connect \dest3_o \dest3_o$147 - connect \fast1_ok \fast1_ok - connect \fast2_ok \fast2_ok - connect \nia_ok \nia_ok - connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data - connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok - connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit - connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk - connect \src1_i \src1_i$74 - connect \src2_i \src2_i$77 - connect \src3_i \src3_i$71 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:123924.7-123949.4" - cell \cr0 \cr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$110 - connect \cu_busy_o \cu_busy_o$2 - connect \cu_issue_i \cu_issue_i$1 - connect \cu_rd__go_i \cu_rd__go_i$29 - connect \cu_rd__rel_o \cu_rd__rel_o$28 - connect \cu_rdmaskn_i \cu_rdmaskn_i$3 - connect \cu_wr__go_i \cu_wr__go_i$82 - connect \cu_wr__rel_o \cu_wr__rel_o$81 - connect \dest1_o \dest1_o$103 - connect \dest2_o \dest2_o - connect \dest3_o \dest3_o - connect \full_cr_ok \full_cr_ok - connect \o_ok \o_ok$80 - connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn - connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type - connect \src1_i \src1_i$30 - connect \src2_i \src2_i$52 - connect \src3_i \src3_i$67 - connect \src4_i \src4_i$68 - connect \src5_i \src5_i$72 - connect \src6_i \src6_i$73 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:123950.8-123989.4" - cell \div0 \div0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$112 - connect \cu_busy_o \cu_busy_o$17 - connect \cu_issue_i \cu_issue_i$16 - connect \cu_rd__go_i \cu_rd__go_i$41 - connect \cu_rd__rel_o \cu_rd__rel_o$40 - connect \cu_rdmaskn_i \cu_rdmaskn_i$18 - connect \cu_wr__go_i \cu_wr__go_i$94 - connect \cu_wr__rel_o \cu_wr__rel_o$93 - connect \dest1_o \dest1_o$107 - connect \dest2_o \dest2_o$117 - connect \dest3_o \dest3_o$127 - connect \dest4_o \dest4_o$134 - connect \o_ok \o_ok$92 - connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len - connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data - connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok - connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn - connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok - connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok - connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a - connect \src1_i \src1_i$42 - connect \src2_i \src2_i$55 - connect \src3_i \src3_i$62 - connect \xer_ov_ok \xer_ov_ok$125 - connect \xer_so_ok \xer_so_ok$130 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:123990.9-124044.4" - cell \ldst0 \ldst0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_busy_o \cu_busy_o$26 - connect \cu_issue_i \cu_issue_i$25 - connect \cu_rd__go_i \cu_rd__go_i$50 - connect \cu_rd__rel_o \cu_rd__rel_o$49 - connect \cu_rdmaskn_i \cu_rdmaskn_i$27 - connect \cu_st__go_i \cu_st__go_i - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_wr__go_i \cu_wr__go_i$102 - connect \cu_wr__rel_o \cu_wr__rel_o$101 - connect \ea \ea - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 - connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 - connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 - connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 - connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 - connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 - connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \o \o - connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit - connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data - connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok - connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn - connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode - connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok - connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok - connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a - connect \src1_i \src1_i$51 - connect \src2_i \src2_i$58 - connect \src3_i \src3_i$59 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:124045.12-124080.4" - cell \logical0 \logical0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$111 - connect \cu_busy_o \cu_busy_o$11 - connect \cu_issue_i \cu_issue_i$10 - connect \cu_rd__go_i \cu_rd__go_i$35 - connect \cu_rd__rel_o \cu_rd__rel_o$34 - connect \cu_rdmaskn_i \cu_rdmaskn_i$12 - connect \cu_wr__go_i \cu_wr__go_i$88 - connect \cu_wr__rel_o \cu_wr__rel_o$87 - connect \dest1_o \dest1_o$105 - connect \dest2_o \dest2_o$116 - connect \o_ok \o_ok$86 - connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data - connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok - connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn - connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok - connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok - connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a - connect \src1_i \src1_i$36 - connect \src2_i \src2_i$54 - connect \src3_i \src3_i$61 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:124081.8-124114.4" - cell \mul0 \mul0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$113 - connect \cu_busy_o \cu_busy_o$20 - connect \cu_issue_i \cu_issue_i$19 - connect \cu_rd__go_i \cu_rd__go_i$44 - connect \cu_rd__rel_o \cu_rd__rel_o$43 - connect \cu_rdmaskn_i \cu_rdmaskn_i$21 - connect \cu_wr__go_i \cu_wr__go_i$97 - connect \cu_wr__rel_o \cu_wr__rel_o$96 - connect \dest1_o \dest1_o$108 - connect \dest2_o \dest2_o$118 - connect \dest3_o \dest3_o$128 - connect \dest4_o \dest4_o$135 - connect \o_ok \o_ok$95 - connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data - connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok - connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn - connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok - connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok - connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 - connect \src1_i \src1_i$45 - connect \src2_i \src2_i$56 - connect \src3_i \src3_i$63 - connect \xer_ov_ok \xer_ov_ok$126 - connect \xer_so_ok \xer_so_ok$131 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:124115.13-124153.4" - cell \shiftrot0 \shiftrot0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a_ok \cr_a_ok$114 - connect \cu_busy_o \cu_busy_o$23 - connect \cu_issue_i \cu_issue_i$22 - connect \cu_rd__go_i \cu_rd__go_i$47 - connect \cu_rd__rel_o \cu_rd__rel_o$46 - connect \cu_rdmaskn_i \cu_rdmaskn_i$24 - connect \cu_wr__go_i \cu_wr__go_i$100 - connect \cu_wr__rel_o \cu_wr__rel_o$99 - connect \dest1_o \dest1_o$109 - connect \dest2_o \dest2_o$119 - connect \dest3_o \dest3_o$123 - connect \o_ok \o_ok$98 - connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data - connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok - connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn - connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in - connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok - connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok - connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 - connect \src1_i \src1_i$48 - connect \src2_i \src2_i$57 - connect \src3_i \src3_i - connect \src4_i \src4_i$64 - connect \src5_i \src5_i - connect \xer_ca_ok \xer_ca_ok$121 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:124154.8-124186.4" - cell \spr0 \spr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$14 - connect \cu_issue_i \cu_issue_i$13 - connect \cu_rd__go_i \cu_rd__go_i$38 - connect \cu_rd__rel_o \cu_rd__rel_o$37 - connect \cu_rdmaskn_i \cu_rdmaskn_i$15 - connect \cu_wr__go_i \cu_wr__go_i$91 - connect \cu_wr__rel_o \cu_wr__rel_o$90 - connect \dest1_o \dest1_o$106 - connect \dest2_o \dest2_o$150 - connect \dest3_o \dest3_o$143 - connect \dest4_o \dest4_o$133 - connect \dest5_o \dest5_o - connect \dest6_o \dest6_o - connect \fast1_ok \fast1_ok$139 - connect \o_ok \o_ok$89 - connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit - connect \spr1_ok \spr1_ok - connect \src1_i \src1_i$39 - connect \src2_i \src2_i$79 - connect \src3_i \src3_i$76 - connect \src4_i \src4_i - connect \src5_i \src5_i$66 - connect \src6_i \src6_i - connect \xer_ca_ok \xer_ca_ok$120 - connect \xer_ov_ok \xer_ov_ok$124 - connect \xer_so_ok \xer_so_ok$129 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:124187.9-124220.4" - cell \trap0 \trap0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cu_busy_o \cu_busy_o$8 - connect \cu_issue_i \cu_issue_i$7 - connect \cu_rd__go_i \cu_rd__go_i$32 - connect \cu_rd__rel_o \cu_rd__rel_o$31 - connect \cu_rdmaskn_i \cu_rdmaskn_i$9 - connect \cu_wr__go_i \cu_wr__go_i$85 - connect \cu_wr__rel_o \cu_wr__rel_o$84 - connect \dest1_o \dest1_o$104 - connect \dest2_o \dest2_o$142 - connect \dest3_o \dest3_o$145 - connect \dest4_o \dest4_o$148 - connect \dest5_o \dest5_o$149 - connect \fast1_ok \fast1_ok$138 - connect \fast2_ok \fast2_ok$140 - connect \msr_ok \msr_ok - connect \nia_ok \nia_ok$146 - connect \o_ok \o_ok$83 - connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc - connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr - connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype - connect \src1_i \src1_i$33 - connect \src2_i \src2_i$53 - connect \src3_i \src3_i$75 - connect \src4_i \src4_i$78 - end -end -attribute \src "libresoc.v:124225.1-124283.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" -attribute \generator "nMigen" -module \idx_l - attribute \src "libresoc.v:124226.7-124226.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:124271.3-124279.6" - wire $0\q_int$next[0:0]$5144 - attribute \src "libresoc.v:124269.3-124270.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:124271.3-124279.6" - wire $1\q_int$next[0:0]$5145 - attribute \src "libresoc.v:124250.7-124250.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:124261.17-124261.96" - wire $and$libresoc.v:124261$5134_Y - attribute \src "libresoc.v:124266.17-124266.96" - wire $and$libresoc.v:124266$5139_Y - attribute \src "libresoc.v:124263.18-124263.95" - wire $not$libresoc.v:124263$5136_Y - attribute \src "libresoc.v:124265.17-124265.94" - wire $not$libresoc.v:124265$5138_Y - attribute \src "libresoc.v:124268.17-124268.94" - wire $not$libresoc.v:124268$5141_Y - attribute \src "libresoc.v:124262.18-124262.100" - wire $or$libresoc.v:124262$5135_Y - attribute \src "libresoc.v:124264.18-124264.101" - wire $or$libresoc.v:124264$5137_Y - attribute \src "libresoc.v:124267.17-124267.99" - wire $or$libresoc.v:124267$5140_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:124226.7-124226.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:124261$5134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:124261$5134_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:124266$5139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:124266$5139_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:124263$5136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \Y $not$libresoc.v:124263$5136_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:124265$5138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $not$libresoc.v:124265$5138_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:124268$5141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $not$libresoc.v:124268$5141_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:124262$5135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_idx_l - connect \Y $or$libresoc.v:124262$5135_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:124264$5137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \B \q_int - connect \Y $or$libresoc.v:124264$5137_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:124267$5140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_idx_l - connect \Y $or$libresoc.v:124267$5140_Y - end - attribute \src "libresoc.v:124226.7-124226.20" - process $proc$libresoc.v:124226$5146 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:124250.7-124250.19" - process $proc$libresoc.v:124250$5147 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:124269.3-124270.27" - process $proc$libresoc.v:124269$5142 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire \a_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 input 2 \a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire \a_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 15 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire output 5 \f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire \f_fetch_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 6 \f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" - wire \f_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire input 4 \f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 9 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 14 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 \ibus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 8 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire \ibus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 13 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 10 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 12 \ibus__sel - attribute \src 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\B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$11 - connect \Y $and$libresoc.v:124405$5150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124411$5156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$21 - connect \Y $and$libresoc.v:124411$5156_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124416$5161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$31 - connect \Y $and$libresoc.v:124416$5161_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124419$5164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$1 - connect \Y $and$libresoc.v:124419$5164_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:124422$5167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B \$41 - connect \Y $and$libresoc.v:124422$5167_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:124423$5168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:124423$5168_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:124425$5170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $and$libresoc.v:124425$5170_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124404$5149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:124404$5149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124407$5152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:124407$5152_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124408$5153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:124408$5153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124410$5155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:124410$5155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124413$5158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:124413$5158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124415$5160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:124415$5160_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124418$5163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:124418$5163_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:124421$5166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $not$libresoc.v:124421$5166_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:124424$5169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:124424$5169_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:124426$5171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $not$libresoc.v:124426$5171_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:124428$5173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $not$libresoc.v:124428$5173_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124403$5148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$5 - connect \B \$7 - connect \Y $or$libresoc.v:124403$5148_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124406$5151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:124406$5151_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124409$5154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \$17 - connect \Y $or$libresoc.v:124409$5154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124412$5157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:124412$5157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124414$5159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$25 - connect \B \$27 - connect \Y $or$libresoc.v:124414$5159_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124417$5162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:124417$5162_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124420$5165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$35 - connect \B \$37 - connect \Y $or$libresoc.v:124420$5165_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:124427$5172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $or$libresoc.v:124427$5172_Y - end - attribute \src "libresoc.v:124288.7-124288.20" - process $proc$libresoc.v:124288$5223 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:124352.14-124352.44" - process $proc$libresoc.v:124352$5224 - assign { } { } - assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \f_badaddr_o $1\f_badaddr_o[44:0] - end - attribute \src "libresoc.v:124359.7-124359.27" - process $proc$libresoc.v:124359$5225 - assign { } { } - assign $1\f_fetch_err_o[0:0] 1'0 - sync always - sync init - update \f_fetch_err_o $1\f_fetch_err_o[0:0] - end - attribute \src "libresoc.v:124373.14-124373.42" - process $proc$libresoc.v:124373$5226 - assign { } { } - assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus__adr $1\ibus__adr[44:0] - end - attribute \src "libresoc.v:124378.7-124378.23" - process $proc$libresoc.v:124378$5227 - assign { } { } - assign $1\ibus__cyc[0:0] 1'0 - sync always - sync init - update \ibus__cyc $1\ibus__cyc[0:0] - end - attribute \src "libresoc.v:124387.13-124387.30" - process $proc$libresoc.v:124387$5228 - assign { } { } - assign $1\ibus__sel[7:0] 8'00000000 - sync always - sync init - update \ibus__sel $1\ibus__sel[7:0] - end - attribute \src "libresoc.v:124392.7-124392.23" - process $proc$libresoc.v:124392$5229 - assign { } { } - assign $1\ibus__stb[0:0] 1'0 - sync always - sync init - update \ibus__stb $1\ibus__stb[0:0] - end - attribute \src "libresoc.v:124396.14-124396.47" - process $proc$libresoc.v:124396$5230 - assign { } { } - assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ibus_rdata $1\ibus_rdata[63:0] - end - attribute \src "libresoc.v:124429.3-124430.39" - process $proc$libresoc.v:124429$5174 - assign { } { } - assign $0\f_badaddr_o[44:0] \f_badaddr_o$next - sync posedge \clk - update \f_badaddr_o $0\f_badaddr_o[44:0] - end - attribute \src "libresoc.v:124431.3-124432.43" - process $proc$libresoc.v:124431$5175 - assign { } { } - assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next - sync posedge \clk - update \f_fetch_err_o $0\f_fetch_err_o[0:0] - end - attribute \src "libresoc.v:124433.3-124434.35" - process $proc$libresoc.v:124433$5176 - assign { } { } - assign $0\ibus__adr[44:0] \ibus__adr$next - sync posedge \clk - update \ibus__adr $0\ibus__adr[44:0] - end - attribute \src "libresoc.v:124435.3-124436.37" - process $proc$libresoc.v:124435$5177 - assign { } { } - assign $0\ibus_rdata[63:0] \ibus_rdata$next - sync posedge \clk - update \ibus_rdata $0\ibus_rdata[63:0] - end - attribute \src "libresoc.v:124437.3-124438.35" - process $proc$libresoc.v:124437$5178 - assign { } { } - assign $0\ibus__sel[7:0] \ibus__sel$next - sync posedge \clk - update \ibus__sel $0\ibus__sel[7:0] - end - attribute \src "libresoc.v:124439.3-124440.35" - process $proc$libresoc.v:124439$5179 - assign { } { } - assign $0\ibus__stb[0:0] \ibus__stb$next - sync posedge \clk - update \ibus__stb $0\ibus__stb[0:0] - end - attribute \src "libresoc.v:124441.3-124442.35" - process $proc$libresoc.v:124441$5180 - assign { } { } - assign $0\ibus__cyc[0:0] \ibus__cyc$next - sync posedge \clk - update \ibus__cyc $0\ibus__cyc[0:0] - end - attribute \src "libresoc.v:124443.3-124470.6" - process $proc$libresoc.v:124443$5181 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__cyc$next[0:0]$5182 $4\ibus__cyc$next[0:0]$5186 - attribute \src "libresoc.v:124444.5-124444.29" - switch \initial - attribute \src "libresoc.v:124444.9-124444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__cyc$next[0:0]$5183 $2\ibus__cyc$next[0:0]$5184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$3 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__cyc$next[0:0]$5184 $3\ibus__cyc$next[0:0]$5185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__cyc$next[0:0]$5185 1'0 - case - assign $3\ibus__cyc$next[0:0]$5185 \ibus__cyc - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__cyc$next[0:0]$5184 1'1 - case - assign $2\ibus__cyc$next[0:0]$5184 \ibus__cyc - end - case - assign $1\ibus__cyc$next[0:0]$5183 \ibus__cyc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus__cyc$next[0:0]$5186 1'0 - case - assign $4\ibus__cyc$next[0:0]$5186 $1\ibus__cyc$next[0:0]$5183 - end - sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5182 - end - attribute \src "libresoc.v:124471.3-124498.6" - process $proc$libresoc.v:124471$5187 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__stb$next[0:0]$5188 $4\ibus__stb$next[0:0]$5192 - attribute \src "libresoc.v:124472.5-124472.29" - switch \initial - attribute \src "libresoc.v:124472.9-124472.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__stb$next[0:0]$5189 $2\ibus__stb$next[0:0]$5190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$13 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__stb$next[0:0]$5190 $3\ibus__stb$next[0:0]$5191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__stb$next[0:0]$5191 1'0 - case - assign $3\ibus__stb$next[0:0]$5191 \ibus__stb - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__stb$next[0:0]$5190 1'1 - case - assign $2\ibus__stb$next[0:0]$5190 \ibus__stb - end - case - assign $1\ibus__stb$next[0:0]$5189 \ibus__stb - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus__stb$next[0:0]$5192 1'0 - case - assign $4\ibus__stb$next[0:0]$5192 $1\ibus__stb$next[0:0]$5189 - end - sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5188 - end - attribute \src "libresoc.v:124499.3-124526.6" - process $proc$libresoc.v:124499$5193 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__sel$next[7:0]$5194 $4\ibus__sel$next[7:0]$5198 - attribute \src "libresoc.v:124500.5-124500.29" - switch \initial - attribute \src "libresoc.v:124500.9-124500.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__sel$next[7:0]$5195 $2\ibus__sel$next[7:0]$5196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$23 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus__sel$next[7:0]$5196 $3\ibus__sel$next[7:0]$5197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__sel$next[7:0]$5197 8'00000000 - case - assign $3\ibus__sel$next[7:0]$5197 \ibus__sel - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__sel$next[7:0]$5196 8'11111111 - case - assign $2\ibus__sel$next[7:0]$5196 \ibus__sel - end - case - assign $1\ibus__sel$next[7:0]$5195 \ibus__sel - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus__sel$next[7:0]$5198 8'00000000 - case - assign $4\ibus__sel$next[7:0]$5198 $1\ibus__sel$next[7:0]$5195 - end - sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5194 - end - attribute \src "libresoc.v:124527.3-124551.6" - process $proc$libresoc.v:124527$5199 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus_rdata$next[63:0]$5200 $4\ibus_rdata$next[63:0]$5204 - attribute \src "libresoc.v:124528.5-124528.29" - switch \initial - attribute \src "libresoc.v:124528.9-124528.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus_rdata$next[63:0]$5201 $2\ibus_rdata$next[63:0]$5202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$33 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\ibus_rdata$next[63:0]$5202 $3\ibus_rdata$next[63:0]$5203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - switch \$39 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus_rdata$next[63:0]$5203 \ibus__dat_r - case - assign $3\ibus_rdata$next[63:0]$5203 \ibus_rdata - end - case - assign $2\ibus_rdata$next[63:0]$5202 \ibus_rdata - end - case - assign $1\ibus_rdata$next[63:0]$5201 \ibus_rdata - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ibus_rdata$next[63:0]$5204 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\ibus_rdata$next[63:0]$5204 $1\ibus_rdata$next[63:0]$5201 - end - sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5200 - end - attribute \src "libresoc.v:124552.3-124574.6" - process $proc$libresoc.v:124552$5205 - assign { } { } - assign { } { } - assign { } { } - assign $0\ibus__adr$next[44:0]$5206 $3\ibus__adr$next[44:0]$5209 - attribute \src "libresoc.v:124553.5-124553.29" - switch \initial - attribute \src "libresoc.v:124553.9-124553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ibus__adr$next[44:0]$5207 $2\ibus__adr$next[44:0]$5208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" - switch { \$43 \ibus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\ibus__adr$next[44:0]$5208 \ibus__adr - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\ibus__adr$next[44:0]$5208 \a_pc_i [47:3] - case - assign $2\ibus__adr$next[44:0]$5208 \ibus__adr - end - case - assign $1\ibus__adr$next[44:0]$5207 \ibus__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ibus__adr$next[44:0]$5209 45'000000000000000000000000000000000000000000000 - case - assign $3\ibus__adr$next[44:0]$5209 $1\ibus__adr$next[44:0]$5207 - end - sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5206 - end - attribute \src "libresoc.v:124575.3-124597.6" - process $proc$libresoc.v:124575$5210 - assign { } { } - assign { } { } - assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5211 $3\f_fetch_err_o$next[0:0]$5214 - attribute \src "libresoc.v:124576.5-124576.29" - switch \initial - attribute \src "libresoc.v:124576.9-124576.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" - switch \wb_icache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5212 $2\f_fetch_err_o$next[0:0]$5213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \$47 \$45 } - attribute \src "libresoc.v:0.0-0.0" - case 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\enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute 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attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 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attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute 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"OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:124671.7-124671.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 43 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 output 45 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 44 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:124953$5231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$libresoc.v:124953$5231_Y - end - attribute \src "libresoc.v:124671.7-124671.20" - process $proc$libresoc.v:124671$5236 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:124954.3-124965.6" - process $proc$libresoc.v:124954$5232 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:124955.5-124955.29" - switch \initial - attribute \src "libresoc.v:124955.9-124955.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" - switch \alu_op__invert_in - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$24 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] - end - attribute \src "libresoc.v:124966.3-124984.6" - process $proc$libresoc.v:124966$5233 - assign { } { } - assign { } { } - assign $0\xer_ca$23[1:0]$5234 $1\xer_ca$23[1:0]$5235 - attribute \src "libresoc.v:124967.5-124967.29" - switch \initial - attribute \src "libresoc.v:124967.9-124967.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" - switch \alu_op__input_carry - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\xer_ca$23[1:0]$5235 2'00 - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\xer_ca$23[1:0]$5235 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\xer_ca$23[1:0]$5235 \xer_ca - case - assign $1\xer_ca$23[1:0]$5235 2'00 - end - sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5234 - end - connect \$24 $not$libresoc.v:124953$5231_Y - connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \rb - connect \b \rb - connect \ra$20 \a -end -attribute \src "libresoc.v:124995.1-125317.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" -attribute \generator "nMigen" -module \input$113 - attribute \src "libresoc.v:125279.3-125290.6" - wire width 64 $0\a[63:0] - attribute \src "libresoc.v:124996.7-124996.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:125291.3-125309.6" - wire width 2 $0\xer_ca$23[1:0]$5240 - attribute \src "libresoc.v:125279.3-125290.6" - wire width 64 $1\a[63:0] - attribute \src "libresoc.v:125291.3-125309.6" - wire width 2 $1\xer_ca$23[1:0]$5241 - attribute \src "libresoc.v:125278.18-125278.100" - wire width 64 $not$libresoc.v:125278$5237_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - wire width 64 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:124996.7-124996.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 46 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 43 \rc$21 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \sr_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 34 \sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 17 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \sr_op__insn$18 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \sr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 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} { } - assign $1\xer_ca$23[1:0]$5241 2'11 - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\xer_ca$23[1:0]$5241 \xer_ca - case - assign $1\xer_ca$23[1:0]$5241 2'00 - end - sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5240 - end - connect \$24 $not$libresoc.v:125278$5237_Y - connect \rc$21 \rc - connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$20 \b - connect \b \rb - connect \ra$19 \a -end -attribute \src "libresoc.v:125321.1-125618.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" -attribute \generator "nMigen" -module \input$50 - attribute \src "libresoc.v:125600.3-125611.6" - wire width 64 $0\b[63:0] - attribute \src "libresoc.v:125322.7-125322.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:125600.3-125611.6" - wire width 64 $1\b[63:0] - attribute \src "libresoc.v:125599.18-125599.100" - wire width 64 $not$libresoc.v:125599$5243_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - wire width 64 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:125322.7-125322.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 43 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:125599$5243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rb - connect \Y $not$libresoc.v:125599$5243_Y - end - attribute \src "libresoc.v:125322.7-125322.20" - process $proc$libresoc.v:125322$5245 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:125600.3-125611.6" - process $proc$libresoc.v:125600$5244 - assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:125601.5-125601.29" - switch \initial - attribute \src "libresoc.v:125601.9-125601.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" - switch \logical_op__invert_in - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b[63:0] \$23 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\b[63:0] \rb - end - sync always - update \b $0\b[63:0] - end - connect \$23 $not$libresoc.v:125599$5243_Y - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \b - connect \ra$20 \a - connect \a \ra -end -attribute \src "libresoc.v:125622.1-125919.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" -attribute \generator "nMigen" -module \input$78 - attribute \src "libresoc.v:125901.3-125912.6" - wire width 64 $0\a[63:0] - attribute \src "libresoc.v:125623.7-125623.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:125901.3-125912.6" - wire width 64 $1\a[63:0] - attribute \src "libresoc.v:125900.18-125900.100" - wire width 64 $not$libresoc.v:125900$5246_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - wire width 64 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "libresoc.v:125623.7-125623.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 43 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:125900$5246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $not$libresoc.v:125900$5246_Y - end - attribute \src "libresoc.v:125623.7-125623.20" - process $proc$libresoc.v:125623$5248 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:125901.3-125912.6" - process $proc$libresoc.v:125901$5247 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:125902.5-125902.29" - switch \initial - attribute \src "libresoc.v:125902.9-125902.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" - switch \logical_op__invert_in - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$23 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] - end - connect \$23 $not$libresoc.v:125900$5246_Y - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$22 \xer_so - connect \rb$21 \rb - connect \b \rb - connect \ra$20 \a -end -attribute \src "libresoc.v:125923.1-126173.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" -attribute \generator "nMigen" -module \input$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 32 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 29 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 30 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 15 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 31 \xer_so$16 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$16 \xer_so - connect \rb$15 \rb - connect \b \rb - connect \ra$14 \a - connect \a \ra -end -attribute \src "libresoc.v:126177.1-126396.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.int" -attribute \generator "nMigen" -module \int - attribute \src "libresoc.v:126302.3-126308.6" - wire width 5 $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 - attribute \src "libresoc.v:126302.3-126308.6" - wire width 64 $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 - attribute \src "libresoc.v:126302.3-126308.6" - wire width 64 $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 - attribute \src "libresoc.v:126302.3-126308.6" - wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:126302.3-126308.6" - wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:126302.3-126308.6" - wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:126302.3-126308.6" - wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:126331.3-126340.6" - wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:126178.7-126178.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:126322.3-126330.6" - wire $0\ren_delay$10$next[0:0]$5301 - attribute \src "libresoc.v:126255.3-126256.43" - wire $0\ren_delay$10[0:0]$5283 - attribute \src "libresoc.v:126221.7-126221.28" - wire $0\ren_delay$10[0:0]$5349 - attribute \src "libresoc.v:126351.3-126359.6" - wire $0\ren_delay$8$next[0:0]$5306 - attribute \src "libresoc.v:126259.3-126260.41" - wire $0\ren_delay$8[0:0]$5287 - attribute \src "libresoc.v:126225.7-126225.27" - wire $0\ren_delay$8[0:0]$5351 - attribute \src "libresoc.v:126370.3-126378.6" - wire $0\ren_delay$9$next[0:0]$5310 - attribute \src "libresoc.v:126257.3-126258.41" - wire $0\ren_delay$9[0:0]$5285 - attribute \src "libresoc.v:126229.7-126229.27" - wire $0\ren_delay$9[0:0]$5353 - attribute \src "libresoc.v:126313.3-126321.6" - wire $0\ren_delay$next[0:0]$5298 - attribute \src "libresoc.v:126261.3-126262.35" - wire $0\ren_delay[0:0] - attribute \src "libresoc.v:126341.3-126350.6" - wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:126360.3-126369.6" - wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:126379.3-126388.6" - wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:126331.3-126340.6" - wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:126322.3-126330.6" - wire $1\ren_delay$10$next[0:0]$5302 - attribute \src "libresoc.v:126351.3-126359.6" - wire $1\ren_delay$8$next[0:0]$5307 - attribute \src "libresoc.v:126370.3-126378.6" - wire $1\ren_delay$9$next[0:0]$5311 - attribute \src "libresoc.v:126313.3-126321.6" - wire $1\ren_delay$next[0:0]$5299 - attribute \src "libresoc.v:126219.7-126219.23" - wire $1\ren_delay[0:0] - attribute \src "libresoc.v:126341.3-126350.6" - wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:126360.3-126369.6" - wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:126379.3-126388.6" - wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:126309.26-126309.32" - wire width 64 $memrd$\memory$libresoc.v:126309$5293_DATA - attribute \src "libresoc.v:126310.30-126310.36" - wire width 64 $memrd$\memory$libresoc.v:126310$5294_DATA - attribute \src "libresoc.v:126311.30-126311.36" - wire width 64 $memrd$\memory$libresoc.v:126311$5295_DATA - attribute \src "libresoc.v:126312.30-126312.36" - wire width 64 $memrd$\memory$libresoc.v:126312$5296_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:126307$5281_ADDR - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:126307$5281_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:126307$5281_EN - attribute \src "libresoc.v:126298.13-126298.16" - wire width 5 \_0_ - attribute \src "libresoc.v:126299.13-126299.16" - wire width 5 \_1_ - attribute \src "libresoc.v:126300.13-126300.16" - wire width 5 \_2_ - attribute \src "libresoc.v:126301.13-126301.16" - wire width 5 \_3_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 15 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 14 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 16 \dest1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 2 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 3 \dmi__ren - attribute \src "libresoc.v:126178.7-126178.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 5 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 6 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 7 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 9 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 8 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 12 \src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 11 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \src3__ren - attribute \src "libresoc.v:126263.14-126263.20" - memory width 64 size 32 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5313 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5313 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 0 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5314 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5314 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 1 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5315 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5315 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 2 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5316 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5316 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 3 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5317 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5317 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 4 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5318 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5318 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 5 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5319 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5319 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 6 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5320 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5320 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 7 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5321 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5321 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 8 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5322 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5322 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 9 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5323 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5323 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 10 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5324 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5324 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 11 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5325 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5325 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 12 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5326 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5326 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 13 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5327 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5327 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 14 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5328 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5328 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 15 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5329 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5329 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 16 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5330 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5330 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 17 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5331 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5331 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 18 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5332 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5332 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 19 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5333 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5333 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 20 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5334 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5334 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 21 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5335 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5335 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 22 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5336 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5336 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 23 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5337 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5337 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 24 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5338 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5338 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 25 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5339 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5339 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 26 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5340 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5340 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 27 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5341 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5341 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 28 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5342 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5342 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 29 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5343 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5343 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 30 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5344 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 5344 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 31 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:126309.26-126309.32" - cell $memrd $memrd$\memory$libresoc.v:126309$5293 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126309$5293_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:126310.30-126310.36" - cell $memrd $memrd$\memory$libresoc.v:126310$5294 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_1_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126310$5294_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:126311.30-126311.36" - cell $memrd $memrd$\memory$libresoc.v:126311$5295 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_2_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126311$5295_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:126312.30-126312.36" - cell $memrd $memrd$\memory$libresoc.v:126312$5296 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_3_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:126312$5296_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5345 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5345 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:126307$5281_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:126307$5281_DATA - connect \EN $memwr$\memory$libresoc.v:126307$5281_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5354 - sync always - sync init - end - attribute \src "libresoc.v:126178.7-126178.20" - process $proc$libresoc.v:126178$5346 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:126219.7-126219.23" - process $proc$libresoc.v:126219$5347 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] - end - attribute \src "libresoc.v:126221.7-126221.28" - process $proc$libresoc.v:126221$5348 - assign { } { } - assign $0\ren_delay$10[0:0]$5349 1'0 - sync always - sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5349 - end - attribute \src "libresoc.v:126225.7-126225.27" - process $proc$libresoc.v:126225$5350 - assign { } { } - assign $0\ren_delay$8[0:0]$5351 1'0 - sync always - sync init - update \ren_delay$8 $0\ren_delay$8[0:0]$5351 - end - attribute \src "libresoc.v:126229.7-126229.27" - process $proc$libresoc.v:126229$5352 - assign { } { } - assign $0\ren_delay$9[0:0]$5353 1'0 - sync always - sync init - update \ren_delay$9 $0\ren_delay$9[0:0]$5353 - end - attribute \src "libresoc.v:126255.3-126256.43" - process $proc$libresoc.v:126255$5282 - assign { } { } - assign $0\ren_delay$10[0:0]$5283 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5283 - end - attribute \src "libresoc.v:126257.3-126258.41" - process $proc$libresoc.v:126257$5284 - assign { } { } - assign $0\ren_delay$9[0:0]$5285 \ren_delay$9$next - sync posedge \coresync_clk - update \ren_delay$9 $0\ren_delay$9[0:0]$5285 - end - attribute \src "libresoc.v:126259.3-126260.41" - process $proc$libresoc.v:126259$5286 - assign { } { } - assign $0\ren_delay$8[0:0]$5287 \ren_delay$8$next - sync posedge \coresync_clk - update \ren_delay$8 $0\ren_delay$8[0:0]$5287 - end - attribute \src "libresoc.v:126261.3-126262.35" - process $proc$libresoc.v:126261$5288 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:126302.3-126308.6" - process $proc$libresoc.v:126302$5289 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 5'xxxxx - assign $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[4:0] \src1__addr - assign $0\_1_[4:0] \src2__addr - assign $0\_2_[4:0] \src3__addr - assign $0\_3_[4:0] \dmi__addr - attribute \src "libresoc.v:126307.5-126307.58" - switch \dest1__wen - attribute \src "libresoc.v:126307.9-126307.19" - case 1'1 - assign $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 \dest1__addr - assign $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[4:0] - update \_1_ $0\_1_[4:0] - update \_2_ $0\_2_[4:0] - update \_3_ $0\_3_[4:0] - update $memwr$\memory$libresoc.v:126307$5281_ADDR $0$memwr$\memory$libresoc.v:126307$5281_ADDR[4:0]$5290 - update $memwr$\memory$libresoc.v:126307$5281_DATA $0$memwr$\memory$libresoc.v:126307$5281_DATA[63:0]$5291 - update $memwr$\memory$libresoc.v:126307$5281_EN $0$memwr$\memory$libresoc.v:126307$5281_EN[63:0]$5292 - end - attribute \src "libresoc.v:126313.3-126321.6" - process $proc$libresoc.v:126313$5297 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$5298 $1\ren_delay$next[0:0]$5299 - attribute \src "libresoc.v:126314.5-126314.29" - switch \initial - attribute \src "libresoc.v:126314.9-126314.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$next[0:0]$5299 1'0 - case - assign $1\ren_delay$next[0:0]$5299 \src1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5298 - end - attribute \src "libresoc.v:126322.3-126330.6" - process $proc$libresoc.v:126322$5300 - assign { } { } - assign { } { } - assign $0\ren_delay$10$next[0:0]$5301 $1\ren_delay$10$next[0:0]$5302 - attribute \src "libresoc.v:126323.5-126323.29" - switch \initial - attribute \src "libresoc.v:126323.9-126323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$10$next[0:0]$5302 1'0 - case - assign $1\ren_delay$10$next[0:0]$5302 \dmi__ren - end - sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5301 - end - attribute \src "libresoc.v:126331.3-126340.6" - process $proc$libresoc.v:126331$5303 - assign { } { } - assign { } { } - assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:126332.5-126332.29" - switch \initial - attribute \src "libresoc.v:126332.9-126332.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$10 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi__data_o[63:0] \memory_r_data$7 - case - assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dmi__data_o $0\dmi__data_o[63:0] - end - attribute \src "libresoc.v:126341.3-126350.6" - process $proc$libresoc.v:126341$5304 - assign { } { } - assign { } { } - assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:126342.5-126342.29" - switch \initial - attribute \src "libresoc.v:126342.9-126342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src1__data_o[63:0] \memory_r_data - case - assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src1__data_o $0\src1__data_o[63:0] - end - attribute \src "libresoc.v:126351.3-126359.6" - process $proc$libresoc.v:126351$5305 - assign { } { } - assign { } { } - assign $0\ren_delay$8$next[0:0]$5306 $1\ren_delay$8$next[0:0]$5307 - attribute \src "libresoc.v:126352.5-126352.29" - switch \initial - attribute \src "libresoc.v:126352.9-126352.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$8$next[0:0]$5307 1'0 - case - assign $1\ren_delay$8$next[0:0]$5307 \src2__ren - end - sync always - update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5306 - end - attribute \src "libresoc.v:126360.3-126369.6" - process $proc$libresoc.v:126360$5308 - assign { } { } - assign { } { } - assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:126361.5-126361.29" - switch \initial - attribute \src "libresoc.v:126361.9-126361.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$8 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[63:0] \memory_r_data$3 - case - assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src2__data_o $0\src2__data_o[63:0] - end - attribute \src "libresoc.v:126370.3-126378.6" - process $proc$libresoc.v:126370$5309 - assign { } { } - assign { } { } - assign $0\ren_delay$9$next[0:0]$5310 $1\ren_delay$9$next[0:0]$5311 - attribute \src "libresoc.v:126371.5-126371.29" - switch \initial - attribute \src "libresoc.v:126371.9-126371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ren_delay$9$next[0:0]$5311 1'0 - case - assign $1\ren_delay$9$next[0:0]$5311 \src3__ren - end - sync always - update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5310 - end - attribute \src "libresoc.v:126379.3-126388.6" - process $proc$libresoc.v:126379$5312 - assign { } { } - assign { } { } - assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:126380.5-126380.29" - switch \initial - attribute \src "libresoc.v:126380.9-126380.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src3__data_o[63:0] \memory_r_data$5 - case - assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \src3__data_o $0\src3__data_o[63:0] - end - connect \memory_r_data $memrd$\memory$libresoc.v:126309$5293_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:126310$5294_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:126311$5295_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:126312$5296_DATA - connect \memory_w_data \dest1__data_i - connect \memory_w_en \dest1__wen - connect \memory_w_addr \dest1__addr - connect \memory_r_addr$6 \dmi__addr - connect \memory_r_addr$4 \src3__addr - connect \memory_r_addr$2 \src2__addr - connect \memory_r_addr \src1__addr -end -attribute \src "libresoc.v:126400.1-129114.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.jtag" -attribute \generator "nMigen" -module \jtag - attribute \src "libresoc.v:128546.3-128572.6" - wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:128194.3-128209.6" - wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:128707.3-128739.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$5765 - attribute \src "libresoc.v:128097.3-128098.41" - wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:128793.3-128819.6" - wire width 64 $0\dmi0__din$next[63:0]$5778 - attribute \src "libresoc.v:128093.3-128094.35" - wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:128396.3-128412.6" - wire $0\dmi0_addrsr__oe$next[0:0]$5702 - attribute \src "libresoc.v:128125.3-128126.47" - wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:128413.3-128433.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$5706 - attribute \src "libresoc.v:128123.3-128124.47" - wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:128378.3-128386.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$5696 - attribute \src "libresoc.v:128129.3-128130.63" - wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:128387.3-128395.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$5699 - attribute \src "libresoc.v:128127.3-128128.73" - wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128820.3-128840.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$5783 - attribute \src "libresoc.v:128091.3-128092.45" - wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:128452.3-128468.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$5717 - attribute \src "libresoc.v:128117.3-128118.47" - wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:128469.3-128489.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$5721 - attribute \src "libresoc.v:128115.3-128116.47" - wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:128434.3-128442.6" - wire $0\dmi0_datasr_update_core$next[0:0]$5711 - attribute \src "libresoc.v:128121.3-128122.63" - wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:128443.3-128451.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$5714 - attribute \src "libresoc.v:128119.3-128120.73" - wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128740.3-128792.6" - wire width 3 $0\fsm_state$503$next[2:0]$5771 - attribute \src "libresoc.v:128095.3-128096.45" - wire width 3 $0\fsm_state$503[2:0]$5617 - attribute \src "libresoc.v:127046.13-127046.35" - wire width 3 $0\fsm_state$503[2:0]$5817 - attribute \src "libresoc.v:128606.3-128658.6" - wire width 3 $0\fsm_state$next[2:0]$5748 - attribute \src "libresoc.v:128103.3-128104.35" - wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:126401.7-126401.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:128888.3-128908.6" - wire width 154 $0\io_bd$next[153:0]$5800 - attribute \src "libresoc.v:128155.3-128156.27" - wire width 154 $0\io_bd[153:0] - attribute \src "libresoc.v:128870.3-128887.6" - wire width 154 $0\io_sr$next[153:0]$5796 - attribute \src "libresoc.v:128157.3-128158.27" - wire width 154 $0\io_sr[153:0] - attribute \src "libresoc.v:128573.3-128605.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$5742 - attribute \src "libresoc.v:128105.3-128106.41" - wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:128659.3-128685.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$5755 - attribute \src "libresoc.v:128101.3-128102.45" - wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:128284.3-128300.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5672 - attribute \src "libresoc.v:128141.3-128142.53" - wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:128301.3-128321.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5676 - attribute \src "libresoc.v:128139.3-128140.53" - wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:128266.3-128274.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5666 - attribute \src "libresoc.v:128145.3-128146.69" - wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:128275.3-128283.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5669 - attribute \src "libresoc.v:128143.3-128144.79" - wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128686.3-128706.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$5760 - attribute \src "libresoc.v:128099.3-128100.51" - wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:128340.3-128356.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5687 - attribute \src "libresoc.v:128133.3-128134.53" - wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:128357.3-128377.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$5691 - attribute \src "libresoc.v:128131.3-128132.53" - wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:128322.3-128330.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$5681 - attribute \src "libresoc.v:128137.3-128138.69" - wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:128331.3-128339.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5684 - attribute \src "libresoc.v:128135.3-128136.79" - wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128228.3-128244.6" - wire $0\sr0__oe$next[0:0]$5657 - attribute \src "libresoc.v:128149.3-128150.31" - wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:128245.3-128265.6" - wire width 3 $0\sr0_reg$next[2:0]$5661 - attribute \src "libresoc.v:128147.3-128148.31" - wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:128210.3-128218.6" - wire $0\sr0_update_core$next[0:0]$5651 - attribute \src "libresoc.v:128153.3-128154.47" - wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:128219.3-128227.6" - wire $0\sr0_update_core_prev$next[0:0]$5654 - attribute \src "libresoc.v:128151.3-128152.57" - wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:128860.3-128869.6" - wire width 2 $0\sr5__i[1:0] - attribute \src "libresoc.v:128508.3-128524.6" - wire $0\sr5__oe$next[0:0]$5732 - attribute \src "libresoc.v:128109.3-128110.31" - wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:128525.3-128545.6" - wire width 2 $0\sr5_reg$next[1:0]$5736 - attribute \src "libresoc.v:128107.3-128108.31" - wire width 2 $0\sr5_reg[1:0] - attribute \src "libresoc.v:128490.3-128498.6" - wire $0\sr5_update_core$next[0:0]$5726 - attribute \src "libresoc.v:128113.3-128114.47" - wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:128499.3-128507.6" - wire $0\sr5_update_core_prev$next[0:0]$5729 - attribute \src "libresoc.v:128111.3-128112.57" - wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:128841.3-128859.6" - wire $0\wb_dcache_en$next[0:0]$5788 - attribute \src "libresoc.v:128089.3-128090.41" - wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:128841.3-128859.6" - wire $0\wb_icache_en$next[0:0]$5789 - attribute \src "libresoc.v:128087.3-128088.41" - wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:128546.3-128572.6" - wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:128194.3-128209.6" - wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:128707.3-128739.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$5766 - attribute \src "libresoc.v:126959.13-126959.32" - wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:128793.3-128819.6" - wire width 64 $1\dmi0__din$next[63:0]$5779 - attribute \src "libresoc.v:126964.14-126964.46" - wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:128396.3-128412.6" - wire $1\dmi0_addrsr__oe$next[0:0]$5703 - attribute \src "libresoc.v:126978.7-126978.29" - wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:128413.3-128433.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$5707 - attribute \src "libresoc.v:126986.13-126986.36" - wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:128378.3-128386.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$5697 - attribute \src "libresoc.v:126994.7-126994.37" - wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:128387.3-128395.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 - attribute \src "libresoc.v:126998.7-126998.42" - wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128820.3-128840.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$5784 - attribute \src "libresoc.v:127002.14-127002.51" - wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:128452.3-128468.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$5718 - attribute \src "libresoc.v:127008.13-127008.35" - wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:128469.3-128489.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$5722 - attribute \src "libresoc.v:127016.14-127016.52" - wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:128434.3-128442.6" - wire $1\dmi0_datasr_update_core$next[0:0]$5712 - attribute \src "libresoc.v:127024.7-127024.37" - wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:128443.3-128451.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$5715 - attribute \src "libresoc.v:127028.7-127028.42" - wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128740.3-128792.6" - wire width 3 $1\fsm_state$503$next[2:0]$5772 - attribute \src "libresoc.v:128606.3-128658.6" - wire width 3 $1\fsm_state$next[2:0]$5749 - attribute \src "libresoc.v:127044.13-127044.29" - wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:128888.3-128908.6" - wire width 154 $1\io_bd$next[153:0]$5801 - attribute \src "libresoc.v:127244.15-127244.67" - wire width 154 $1\io_bd[153:0] - attribute \src "libresoc.v:128870.3-128887.6" - wire width 154 $1\io_sr$next[153:0]$5797 - attribute \src "libresoc.v:127256.15-127256.67" - wire width 154 $1\io_sr[153:0] - attribute \src "libresoc.v:128573.3-128605.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$5743 - attribute \src "libresoc.v:127265.14-127265.41" - wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:128659.3-128685.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$5756 - attribute \src "libresoc.v:127274.14-127274.51" - wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:128284.3-128300.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5673 - attribute \src "libresoc.v:127288.7-127288.32" - wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:128301.3-128321.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5677 - attribute \src "libresoc.v:127296.14-127296.47" - wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:128266.3-128274.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5667 - attribute \src "libresoc.v:127304.7-127304.40" - wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:128275.3-128283.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 - attribute \src "libresoc.v:127308.7-127308.45" - wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:128686.3-128706.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$5761 - attribute \src "libresoc.v:127312.14-127312.54" - wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:128340.3-128356.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5688 - attribute \src "libresoc.v:127318.13-127318.38" - wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:128357.3-128377.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$5692 - attribute \src "libresoc.v:127326.14-127326.55" - wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:128322.3-128330.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$5682 - attribute \src "libresoc.v:127334.7-127334.40" - wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:128331.3-128339.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 - attribute \src "libresoc.v:127338.7-127338.45" - wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:128228.3-128244.6" - wire $1\sr0__oe$next[0:0]$5658 - attribute \src "libresoc.v:127768.7-127768.21" - wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:128245.3-128265.6" - wire width 3 $1\sr0_reg$next[2:0]$5662 - attribute \src "libresoc.v:127776.13-127776.27" - wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:128210.3-128218.6" - wire $1\sr0_update_core$next[0:0]$5652 - attribute \src "libresoc.v:127784.7-127784.29" - wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:128219.3-128227.6" - wire $1\sr0_update_core_prev$next[0:0]$5655 - attribute \src "libresoc.v:127788.7-127788.34" - wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:128860.3-128869.6" - wire width 2 $1\sr5__i[1:0] - attribute \src "libresoc.v:128508.3-128524.6" - wire $1\sr5__oe$next[0:0]$5733 - attribute \src "libresoc.v:127798.7-127798.21" - wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:128525.3-128545.6" - wire width 2 $1\sr5_reg$next[1:0]$5737 - attribute \src "libresoc.v:127806.13-127806.27" - wire width 2 $1\sr5_reg[1:0] - attribute \src "libresoc.v:128490.3-128498.6" - wire $1\sr5_update_core$next[0:0]$5727 - attribute \src "libresoc.v:127814.7-127814.29" - wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:128499.3-128507.6" - wire $1\sr5_update_core_prev$next[0:0]$5730 - attribute \src "libresoc.v:127818.7-127818.34" - wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:128841.3-128859.6" - wire $1\wb_dcache_en$next[0:0]$5790 - attribute \src "libresoc.v:127823.7-127823.26" - wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:128841.3-128859.6" - wire $1\wb_icache_en$next[0:0]$5791 - attribute \src "libresoc.v:127828.7-127828.26" - wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:128707.3-128739.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$5767 - attribute \src "libresoc.v:128793.3-128819.6" - wire width 64 $2\dmi0__din$next[63:0]$5780 - attribute \src "libresoc.v:128396.3-128412.6" - wire $2\dmi0_addrsr__oe$next[0:0]$5704 - attribute \src "libresoc.v:128413.3-128433.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$5708 - attribute \src "libresoc.v:128820.3-128840.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$5785 - attribute \src "libresoc.v:128452.3-128468.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$5719 - attribute \src "libresoc.v:128469.3-128489.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$5723 - attribute \src "libresoc.v:128740.3-128792.6" - wire width 3 $2\fsm_state$503$next[2:0]$5773 - attribute \src "libresoc.v:128606.3-128658.6" - wire width 3 $2\fsm_state$next[2:0]$5750 - attribute \src "libresoc.v:128888.3-128908.6" - wire width 154 $2\io_bd$next[153:0]$5802 - attribute \src "libresoc.v:128870.3-128887.6" - wire width 154 $2\io_sr$next[153:0]$5798 - attribute \src "libresoc.v:128573.3-128605.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$5744 - attribute \src "libresoc.v:128659.3-128685.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$5757 - attribute \src "libresoc.v:128284.3-128300.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$5674 - attribute \src "libresoc.v:128301.3-128321.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5678 - attribute \src "libresoc.v:128686.3-128706.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$5762 - attribute \src "libresoc.v:128340.3-128356.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5689 - attribute \src "libresoc.v:128357.3-128377.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$5693 - attribute \src "libresoc.v:128228.3-128244.6" - wire $2\sr0__oe$next[0:0]$5659 - attribute \src "libresoc.v:128245.3-128265.6" - wire width 3 $2\sr0_reg$next[2:0]$5663 - attribute \src "libresoc.v:128508.3-128524.6" - wire $2\sr5__oe$next[0:0]$5734 - attribute \src "libresoc.v:128525.3-128545.6" - wire width 2 $2\sr5_reg$next[1:0]$5738 - attribute \src "libresoc.v:128841.3-128859.6" - wire $2\wb_dcache_en$next[0:0]$5792 - attribute \src "libresoc.v:128841.3-128859.6" - wire $2\wb_icache_en$next[0:0]$5793 - attribute \src "libresoc.v:128707.3-128739.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$5768 - attribute \src "libresoc.v:128793.3-128819.6" - wire width 64 $3\dmi0__din$next[63:0]$5781 - attribute \src "libresoc.v:128413.3-128433.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$5709 - attribute \src "libresoc.v:128820.3-128840.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$5786 - attribute \src "libresoc.v:128469.3-128489.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$5724 - attribute \src "libresoc.v:128740.3-128792.6" - wire width 3 $3\fsm_state$503$next[2:0]$5774 - attribute \src "libresoc.v:128606.3-128658.6" - wire width 3 $3\fsm_state$next[2:0]$5751 - attribute \src "libresoc.v:128573.3-128605.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$5745 - attribute \src "libresoc.v:128659.3-128685.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$5758 - attribute \src "libresoc.v:128301.3-128321.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5679 - attribute \src "libresoc.v:128686.3-128706.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$5763 - attribute \src "libresoc.v:128357.3-128377.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$5694 - attribute \src "libresoc.v:128245.3-128265.6" - wire width 3 $3\sr0_reg$next[2:0]$5664 - attribute \src "libresoc.v:128525.3-128545.6" - wire width 2 $3\sr5_reg$next[1:0]$5739 - attribute \src "libresoc.v:128707.3-128739.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$5769 - attribute \src "libresoc.v:128740.3-128792.6" - wire width 3 $4\fsm_state$503$next[2:0]$5775 - attribute \src "libresoc.v:128606.3-128658.6" - wire width 3 $4\fsm_state$next[2:0]$5752 - attribute \src "libresoc.v:128573.3-128605.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$5746 - attribute \src "libresoc.v:128740.3-128792.6" - wire width 3 $5\fsm_state$503$next[2:0]$5776 - attribute \src "libresoc.v:128606.3-128658.6" - wire width 3 $5\fsm_state$next[2:0]$5753 - attribute \src "libresoc.v:128051.19-128051.112" - wire width 30 $add$libresoc.v:128051$5575_Y - attribute \src "libresoc.v:128053.19-128053.112" - wire width 30 $add$libresoc.v:128053$5577_Y - attribute \src "libresoc.v:128059.19-128059.112" - wire width 5 $add$libresoc.v:128059$5584_Y - attribute \src "libresoc.v:128060.19-128060.112" - wire width 5 $add$libresoc.v:128060$5585_Y - attribute \src "libresoc.v:127875.18-127875.112" - wire $and$libresoc.v:127875$5399_Y - attribute \src "libresoc.v:127942.18-127942.108" - wire $and$libresoc.v:127942$5466_Y - attribute \src "libresoc.v:127953.18-127953.110" - wire $and$libresoc.v:127953$5477_Y - attribute \src "libresoc.v:127981.19-127981.110" - wire $and$libresoc.v:127981$5505_Y - attribute \src "libresoc.v:127984.19-127984.114" - wire $and$libresoc.v:127984$5508_Y - attribute \src "libresoc.v:127987.19-127987.112" - wire $and$libresoc.v:127987$5511_Y - attribute \src "libresoc.v:127989.19-127989.113" - wire $and$libresoc.v:127989$5513_Y - attribute \src "libresoc.v:127991.19-127991.121" - wire $and$libresoc.v:127991$5515_Y - attribute \src "libresoc.v:127994.19-127994.114" - wire $and$libresoc.v:127994$5518_Y - attribute \src "libresoc.v:127996.19-127996.112" - wire $and$libresoc.v:127996$5520_Y - attribute \src "libresoc.v:128000.19-128000.113" - wire $and$libresoc.v:128000$5524_Y - attribute \src "libresoc.v:128002.19-128002.132" - wire $and$libresoc.v:128002$5526_Y - attribute \src "libresoc.v:128006.19-128006.114" - wire $and$libresoc.v:128006$5530_Y - attribute \src "libresoc.v:128008.19-128008.112" - wire $and$libresoc.v:128008$5532_Y - attribute \src "libresoc.v:128011.19-128011.113" - wire $and$libresoc.v:128011$5535_Y - attribute \src "libresoc.v:128013.19-128013.132" - wire $and$libresoc.v:128013$5537_Y - attribute \src "libresoc.v:128016.19-128016.114" - wire $and$libresoc.v:128016$5540_Y - attribute \src "libresoc.v:128018.19-128018.112" - wire $and$libresoc.v:128018$5542_Y - attribute \src "libresoc.v:128020.18-128020.108" - wire $and$libresoc.v:128020$5544_Y - attribute \src "libresoc.v:128021.19-128021.113" - wire $and$libresoc.v:128021$5545_Y - attribute \src "libresoc.v:128023.19-128023.129" - wire $and$libresoc.v:128023$5547_Y - attribute \src "libresoc.v:128027.19-128027.114" - wire $and$libresoc.v:128027$5551_Y - attribute \src "libresoc.v:128029.19-128029.112" - wire $and$libresoc.v:128029$5553_Y - attribute \src "libresoc.v:128031.18-128031.111" - wire $and$libresoc.v:128031$5555_Y - attribute \src "libresoc.v:128032.19-128032.113" - wire $and$libresoc.v:128032$5556_Y - attribute \src "libresoc.v:128034.19-128034.129" - wire $and$libresoc.v:128034$5558_Y - attribute \src "libresoc.v:128037.19-128037.114" - wire $and$libresoc.v:128037$5561_Y - attribute \src "libresoc.v:128039.19-128039.112" - wire $and$libresoc.v:128039$5563_Y - attribute \src "libresoc.v:128041.19-128041.113" - wire $and$libresoc.v:128041$5565_Y - attribute \src "libresoc.v:128044.19-128044.121" - wire $and$libresoc.v:128044$5568_Y - attribute \src "libresoc.v:128076.17-128076.106" - wire $and$libresoc.v:128076$5601_Y - attribute \src "libresoc.v:127831.17-127831.110" - wire $eq$libresoc.v:127831$5355_Y - attribute \src "libresoc.v:127842.18-127842.111" - wire $eq$libresoc.v:127842$5366_Y - attribute \src "libresoc.v:127853.18-127853.111" - wire $eq$libresoc.v:127853$5377_Y - attribute \src "libresoc.v:127886.17-127886.110" - wire $eq$libresoc.v:127886$5410_Y - attribute \src "libresoc.v:127887.18-127887.111" - wire $eq$libresoc.v:127887$5411_Y - attribute \src "libresoc.v:127898.18-127898.111" - wire $eq$libresoc.v:127898$5422_Y - attribute \src "libresoc.v:127920.18-127920.111" - wire $eq$libresoc.v:127920$5444_Y - attribute \src "libresoc.v:127964.18-127964.111" - wire $eq$libresoc.v:127964$5488_Y - attribute \src "libresoc.v:127975.18-127975.111" - wire $eq$libresoc.v:127975$5499_Y - attribute \src "libresoc.v:127976.19-127976.112" - wire $eq$libresoc.v:127976$5500_Y - attribute \src "libresoc.v:127977.19-127977.112" - wire $eq$libresoc.v:127977$5501_Y - attribute \src "libresoc.v:127979.19-127979.112" - wire $eq$libresoc.v:127979$5503_Y - attribute \src "libresoc.v:127982.19-127982.112" - wire $eq$libresoc.v:127982$5506_Y - attribute \src "libresoc.v:127992.19-127992.112" - wire $eq$libresoc.v:127992$5516_Y - attribute \src "libresoc.v:127997.17-127997.110" - wire $eq$libresoc.v:127997$5521_Y - attribute \src "libresoc.v:127998.18-127998.111" - wire $eq$libresoc.v:127998$5522_Y - attribute \src "libresoc.v:128003.19-128003.112" - wire $eq$libresoc.v:128003$5527_Y - attribute \src "libresoc.v:128004.19-128004.112" - wire $eq$libresoc.v:128004$5528_Y - attribute \src "libresoc.v:128014.19-128014.112" - wire $eq$libresoc.v:128014$5538_Y - attribute \src "libresoc.v:128024.19-128024.112" - wire $eq$libresoc.v:128024$5548_Y - attribute \src "libresoc.v:128025.19-128025.112" - wire $eq$libresoc.v:128025$5549_Y - attribute \src "libresoc.v:128035.19-128035.112" - wire $eq$libresoc.v:128035$5559_Y - attribute \src "libresoc.v:128042.18-128042.111" - wire $eq$libresoc.v:128042$5566_Y - attribute \src "libresoc.v:128045.19-128045.110" - wire $eq$libresoc.v:128045$5569_Y - attribute \src "libresoc.v:128047.19-128047.110" - wire $eq$libresoc.v:128047$5571_Y - attribute \src "libresoc.v:128048.19-128048.110" - wire $eq$libresoc.v:128048$5572_Y - attribute \src "libresoc.v:128050.19-128050.110" - wire $eq$libresoc.v:128050$5574_Y - attribute \src "libresoc.v:128052.18-128052.111" - wire $eq$libresoc.v:128052$5576_Y - attribute \src "libresoc.v:128055.19-128055.116" - wire $eq$libresoc.v:128055$5580_Y - attribute \src "libresoc.v:128056.19-128056.116" - wire $eq$libresoc.v:128056$5581_Y - attribute \src "libresoc.v:128058.19-128058.116" - wire $eq$libresoc.v:128058$5583_Y - attribute \src "libresoc.v:128054.19-128054.106" - wire width 8 $extend$libresoc.v:128054$5578_Y - attribute \src "libresoc.v:127983.19-127983.109" - wire $ne$libresoc.v:127983$5507_Y - attribute \src "libresoc.v:127985.19-127985.109" - wire $ne$libresoc.v:127985$5509_Y - attribute \src "libresoc.v:127988.19-127988.109" - wire $ne$libresoc.v:127988$5512_Y - attribute \src "libresoc.v:127993.19-127993.120" - wire $ne$libresoc.v:127993$5517_Y - attribute \src "libresoc.v:127995.19-127995.120" - wire $ne$libresoc.v:127995$5519_Y - attribute \src "libresoc.v:127999.19-127999.120" - wire $ne$libresoc.v:127999$5523_Y - attribute \src "libresoc.v:128005.19-128005.120" - wire $ne$libresoc.v:128005$5529_Y - attribute \src "libresoc.v:128007.19-128007.120" - wire $ne$libresoc.v:128007$5531_Y - attribute \src "libresoc.v:128010.19-128010.120" - wire $ne$libresoc.v:128010$5534_Y - attribute \src "libresoc.v:128015.19-128015.117" - wire $ne$libresoc.v:128015$5539_Y - attribute \src "libresoc.v:128017.19-128017.117" - wire $ne$libresoc.v:128017$5541_Y - attribute \src "libresoc.v:128019.19-128019.117" - wire $ne$libresoc.v:128019$5543_Y - attribute \src "libresoc.v:128026.19-128026.117" - wire $ne$libresoc.v:128026$5550_Y - attribute \src "libresoc.v:128028.19-128028.117" - wire $ne$libresoc.v:128028$5552_Y - attribute \src "libresoc.v:128030.19-128030.117" - wire $ne$libresoc.v:128030$5554_Y - attribute \src "libresoc.v:128036.19-128036.109" - wire $ne$libresoc.v:128036$5560_Y - attribute \src "libresoc.v:128038.19-128038.109" - wire $ne$libresoc.v:128038$5562_Y - attribute \src "libresoc.v:128040.19-128040.109" - wire $ne$libresoc.v:128040$5564_Y - attribute \src "libresoc.v:127990.19-127990.110" - wire $not$libresoc.v:127990$5514_Y - attribute \src "libresoc.v:128001.19-128001.121" - wire $not$libresoc.v:128001$5525_Y - attribute \src "libresoc.v:128012.19-128012.121" - wire $not$libresoc.v:128012$5536_Y - attribute \src "libresoc.v:128022.19-128022.118" - wire $not$libresoc.v:128022$5546_Y - attribute \src "libresoc.v:128033.19-128033.118" - wire $not$libresoc.v:128033$5557_Y - attribute \src "libresoc.v:128043.19-128043.110" - wire $not$libresoc.v:128043$5567_Y - attribute \src "libresoc.v:128046.19-128046.100" - wire $not$libresoc.v:128046$5570_Y - attribute \src "libresoc.v:127864.18-127864.104" - wire $or$libresoc.v:127864$5388_Y - attribute \src "libresoc.v:127909.18-127909.104" - wire $or$libresoc.v:127909$5433_Y - attribute \src "libresoc.v:127931.18-127931.104" - wire $or$libresoc.v:127931$5455_Y - attribute \src "libresoc.v:127978.19-127978.107" - wire $or$libresoc.v:127978$5502_Y - attribute \src "libresoc.v:127980.19-127980.107" - wire $or$libresoc.v:127980$5504_Y - attribute \src "libresoc.v:127986.18-127986.104" - wire $or$libresoc.v:127986$5510_Y - attribute \src "libresoc.v:128009.18-128009.104" - wire $or$libresoc.v:128009$5533_Y - attribute \src "libresoc.v:128049.19-128049.107" - wire $or$libresoc.v:128049$5573_Y - attribute \src "libresoc.v:128057.19-128057.107" - wire $or$libresoc.v:128057$5582_Y - attribute \src "libresoc.v:128065.17-128065.101" - wire $or$libresoc.v:128065$5590_Y - attribute \src "libresoc.v:128054.19-128054.106" - wire width 8 $pos$libresoc.v:128054$5579_Y - attribute \src "libresoc.v:127832.18-127832.133" - wire $ternary$libresoc.v:127832$5356_Y - attribute \src "libresoc.v:127833.19-127833.133" - wire $ternary$libresoc.v:127833$5357_Y - attribute \src "libresoc.v:127834.19-127834.134" - wire $ternary$libresoc.v:127834$5358_Y - attribute \src "libresoc.v:127835.19-127835.133" - wire $ternary$libresoc.v:127835$5359_Y - attribute \src "libresoc.v:127836.19-127836.132" - wire $ternary$libresoc.v:127836$5360_Y - attribute \src "libresoc.v:127837.19-127837.133" - wire $ternary$libresoc.v:127837$5361_Y - attribute \src "libresoc.v:127838.19-127838.133" - wire $ternary$libresoc.v:127838$5362_Y - attribute \src "libresoc.v:127839.19-127839.132" - wire $ternary$libresoc.v:127839$5363_Y - attribute \src "libresoc.v:127840.19-127840.133" - wire $ternary$libresoc.v:127840$5364_Y - attribute \src "libresoc.v:127841.19-127841.133" - wire $ternary$libresoc.v:127841$5365_Y - attribute \src "libresoc.v:127843.19-127843.132" - wire $ternary$libresoc.v:127843$5367_Y - attribute \src "libresoc.v:127844.19-127844.133" - wire $ternary$libresoc.v:127844$5368_Y - attribute \src "libresoc.v:127845.19-127845.133" - wire $ternary$libresoc.v:127845$5369_Y - attribute \src "libresoc.v:127846.19-127846.132" - wire $ternary$libresoc.v:127846$5370_Y - attribute \src "libresoc.v:127847.19-127847.133" - wire $ternary$libresoc.v:127847$5371_Y - attribute \src "libresoc.v:127848.19-127848.133" - wire $ternary$libresoc.v:127848$5372_Y - attribute \src "libresoc.v:127849.19-127849.132" - wire $ternary$libresoc.v:127849$5373_Y - attribute \src "libresoc.v:127850.19-127850.133" - wire $ternary$libresoc.v:127850$5374_Y - attribute \src "libresoc.v:127851.19-127851.133" - wire $ternary$libresoc.v:127851$5375_Y - attribute \src "libresoc.v:127852.19-127852.132" - wire $ternary$libresoc.v:127852$5376_Y - attribute \src "libresoc.v:127854.19-127854.133" - wire $ternary$libresoc.v:127854$5378_Y - attribute \src "libresoc.v:127855.19-127855.133" - wire $ternary$libresoc.v:127855$5379_Y - attribute \src "libresoc.v:127856.19-127856.132" - wire $ternary$libresoc.v:127856$5380_Y - attribute \src "libresoc.v:127857.19-127857.133" - wire $ternary$libresoc.v:127857$5381_Y - attribute \src "libresoc.v:127858.19-127858.133" - wire $ternary$libresoc.v:127858$5382_Y - attribute \src "libresoc.v:127859.19-127859.132" - wire $ternary$libresoc.v:127859$5383_Y - attribute \src "libresoc.v:127860.19-127860.133" - wire $ternary$libresoc.v:127860$5384_Y - attribute \src "libresoc.v:127861.19-127861.134" - wire $ternary$libresoc.v:127861$5385_Y - attribute \src "libresoc.v:127862.19-127862.135" - wire $ternary$libresoc.v:127862$5386_Y - attribute \src "libresoc.v:127863.19-127863.135" - wire $ternary$libresoc.v:127863$5387_Y - attribute \src "libresoc.v:127865.19-127865.136" - wire $ternary$libresoc.v:127865$5389_Y - attribute \src "libresoc.v:127866.19-127866.134" - wire $ternary$libresoc.v:127866$5390_Y - attribute \src "libresoc.v:127867.19-127867.135" - wire $ternary$libresoc.v:127867$5391_Y - attribute \src "libresoc.v:127868.19-127868.135" - wire $ternary$libresoc.v:127868$5392_Y - attribute \src "libresoc.v:127869.19-127869.136" - wire $ternary$libresoc.v:127869$5393_Y - attribute \src "libresoc.v:127870.19-127870.134" - wire $ternary$libresoc.v:127870$5394_Y - attribute \src "libresoc.v:127871.19-127871.133" - wire $ternary$libresoc.v:127871$5395_Y - attribute \src "libresoc.v:127872.19-127872.134" - wire $ternary$libresoc.v:127872$5396_Y - attribute \src "libresoc.v:127873.19-127873.133" - wire $ternary$libresoc.v:127873$5397_Y - attribute \src "libresoc.v:127874.19-127874.130" - wire $ternary$libresoc.v:127874$5398_Y - attribute \src "libresoc.v:127876.19-127876.130" - wire $ternary$libresoc.v:127876$5400_Y - attribute \src "libresoc.v:127877.19-127877.133" - wire $ternary$libresoc.v:127877$5401_Y - attribute \src "libresoc.v:127878.19-127878.132" - wire $ternary$libresoc.v:127878$5402_Y - attribute \src "libresoc.v:127879.19-127879.133" - wire $ternary$libresoc.v:127879$5403_Y - attribute \src "libresoc.v:127880.19-127880.132" - wire $ternary$libresoc.v:127880$5404_Y - attribute \src "libresoc.v:127881.19-127881.135" - wire $ternary$libresoc.v:127881$5405_Y - attribute \src "libresoc.v:127882.19-127882.134" - wire $ternary$libresoc.v:127882$5406_Y - attribute \src "libresoc.v:127883.19-127883.135" - wire $ternary$libresoc.v:127883$5407_Y - attribute \src "libresoc.v:127884.19-127884.135" - wire $ternary$libresoc.v:127884$5408_Y - attribute \src "libresoc.v:127885.19-127885.134" - wire $ternary$libresoc.v:127885$5409_Y - attribute \src "libresoc.v:127888.19-127888.135" - wire $ternary$libresoc.v:127888$5412_Y - attribute \src "libresoc.v:127889.19-127889.135" - wire $ternary$libresoc.v:127889$5413_Y - attribute \src "libresoc.v:127890.19-127890.134" - wire $ternary$libresoc.v:127890$5414_Y - attribute \src "libresoc.v:127891.19-127891.135" - wire $ternary$libresoc.v:127891$5415_Y - attribute \src "libresoc.v:127892.19-127892.135" - wire $ternary$libresoc.v:127892$5416_Y - attribute \src "libresoc.v:127893.19-127893.134" - wire $ternary$libresoc.v:127893$5417_Y - attribute \src "libresoc.v:127894.19-127894.135" - wire $ternary$libresoc.v:127894$5418_Y - attribute \src "libresoc.v:127895.19-127895.133" - wire $ternary$libresoc.v:127895$5419_Y - attribute \src "libresoc.v:127896.19-127896.134" - wire $ternary$libresoc.v:127896$5420_Y - attribute \src "libresoc.v:127897.19-127897.133" - wire $ternary$libresoc.v:127897$5421_Y - attribute \src "libresoc.v:127899.19-127899.134" - wire $ternary$libresoc.v:127899$5423_Y - attribute \src "libresoc.v:127900.19-127900.134" - wire $ternary$libresoc.v:127900$5424_Y - attribute \src "libresoc.v:127901.19-127901.133" - wire $ternary$libresoc.v:127901$5425_Y - attribute \src "libresoc.v:127902.19-127902.134" - wire $ternary$libresoc.v:127902$5426_Y - attribute \src "libresoc.v:127903.19-127903.134" - wire $ternary$libresoc.v:127903$5427_Y - attribute \src "libresoc.v:127904.19-127904.133" - wire $ternary$libresoc.v:127904$5428_Y - attribute \src "libresoc.v:127905.19-127905.134" - wire $ternary$libresoc.v:127905$5429_Y - attribute \src "libresoc.v:127906.19-127906.134" - wire $ternary$libresoc.v:127906$5430_Y - attribute \src "libresoc.v:127907.19-127907.133" - wire $ternary$libresoc.v:127907$5431_Y - attribute \src "libresoc.v:127908.19-127908.134" - wire $ternary$libresoc.v:127908$5432_Y - attribute \src "libresoc.v:127910.19-127910.134" - wire $ternary$libresoc.v:127910$5434_Y - attribute \src "libresoc.v:127911.19-127911.133" - wire $ternary$libresoc.v:127911$5435_Y - attribute \src "libresoc.v:127912.19-127912.134" - wire $ternary$libresoc.v:127912$5436_Y - attribute \src "libresoc.v:127913.19-127913.134" - wire $ternary$libresoc.v:127913$5437_Y - attribute \src "libresoc.v:127914.19-127914.133" - wire $ternary$libresoc.v:127914$5438_Y - attribute \src "libresoc.v:127915.19-127915.134" - wire $ternary$libresoc.v:127915$5439_Y - attribute \src "libresoc.v:127916.19-127916.135" - wire $ternary$libresoc.v:127916$5440_Y - attribute \src "libresoc.v:127917.19-127917.134" - wire $ternary$libresoc.v:127917$5441_Y - attribute \src "libresoc.v:127918.19-127918.135" - wire $ternary$libresoc.v:127918$5442_Y - attribute \src "libresoc.v:127919.19-127919.135" - wire $ternary$libresoc.v:127919$5443_Y - attribute \src "libresoc.v:127921.19-127921.134" - wire $ternary$libresoc.v:127921$5445_Y - attribute \src "libresoc.v:127922.19-127922.135" - wire $ternary$libresoc.v:127922$5446_Y - attribute \src "libresoc.v:127923.19-127923.133" - wire $ternary$libresoc.v:127923$5447_Y - attribute \src "libresoc.v:127924.19-127924.133" - wire $ternary$libresoc.v:127924$5448_Y - attribute \src "libresoc.v:127925.19-127925.133" - wire $ternary$libresoc.v:127925$5449_Y - attribute \src "libresoc.v:127926.19-127926.133" - wire $ternary$libresoc.v:127926$5450_Y - attribute \src "libresoc.v:127927.19-127927.133" - wire $ternary$libresoc.v:127927$5451_Y - attribute \src "libresoc.v:127928.19-127928.133" - wire $ternary$libresoc.v:127928$5452_Y - attribute \src "libresoc.v:127929.19-127929.133" - wire $ternary$libresoc.v:127929$5453_Y - attribute \src "libresoc.v:127930.19-127930.133" - wire $ternary$libresoc.v:127930$5454_Y - attribute \src "libresoc.v:127932.19-127932.133" - wire $ternary$libresoc.v:127932$5456_Y - attribute \src "libresoc.v:127933.19-127933.133" - wire $ternary$libresoc.v:127933$5457_Y - attribute \src "libresoc.v:127934.19-127934.134" - wire $ternary$libresoc.v:127934$5458_Y - attribute \src "libresoc.v:127935.19-127935.134" - wire $ternary$libresoc.v:127935$5459_Y - attribute \src "libresoc.v:127936.19-127936.135" - wire $ternary$libresoc.v:127936$5460_Y - attribute \src "libresoc.v:127937.19-127937.133" - wire $ternary$libresoc.v:127937$5461_Y - attribute \src "libresoc.v:127938.19-127938.135" - wire $ternary$libresoc.v:127938$5462_Y - attribute \src "libresoc.v:127939.19-127939.135" - wire $ternary$libresoc.v:127939$5463_Y - attribute \src "libresoc.v:127940.19-127940.134" - wire $ternary$libresoc.v:127940$5464_Y - attribute \src "libresoc.v:127941.19-127941.134" - wire $ternary$libresoc.v:127941$5465_Y - attribute \src "libresoc.v:127943.19-127943.134" - wire $ternary$libresoc.v:127943$5467_Y - attribute \src "libresoc.v:127944.19-127944.134" - wire $ternary$libresoc.v:127944$5468_Y - attribute \src "libresoc.v:127945.19-127945.134" - wire $ternary$libresoc.v:127945$5469_Y - attribute \src "libresoc.v:127946.19-127946.135" - wire $ternary$libresoc.v:127946$5470_Y - attribute \src "libresoc.v:127947.19-127947.134" - wire $ternary$libresoc.v:127947$5471_Y - attribute \src "libresoc.v:127948.19-127948.135" - wire $ternary$libresoc.v:127948$5472_Y - attribute \src "libresoc.v:127949.19-127949.135" - wire $ternary$libresoc.v:127949$5473_Y - attribute \src "libresoc.v:127950.19-127950.134" - wire $ternary$libresoc.v:127950$5474_Y - attribute \src "libresoc.v:127951.19-127951.135" - wire $ternary$libresoc.v:127951$5475_Y - attribute \src "libresoc.v:127952.19-127952.135" - wire $ternary$libresoc.v:127952$5476_Y - attribute \src "libresoc.v:127954.19-127954.134" - wire $ternary$libresoc.v:127954$5478_Y - attribute \src "libresoc.v:127955.19-127955.135" - wire $ternary$libresoc.v:127955$5479_Y - attribute \src "libresoc.v:127956.19-127956.136" - wire $ternary$libresoc.v:127956$5480_Y - attribute \src "libresoc.v:127957.19-127957.135" - wire $ternary$libresoc.v:127957$5481_Y - attribute \src "libresoc.v:127958.19-127958.136" - wire $ternary$libresoc.v:127958$5482_Y - attribute \src "libresoc.v:127959.19-127959.136" - wire $ternary$libresoc.v:127959$5483_Y - attribute \src "libresoc.v:127960.19-127960.135" - wire $ternary$libresoc.v:127960$5484_Y - attribute \src "libresoc.v:127961.19-127961.136" - wire $ternary$libresoc.v:127961$5485_Y - attribute \src "libresoc.v:127962.19-127962.136" - wire $ternary$libresoc.v:127962$5486_Y - attribute \src "libresoc.v:127963.19-127963.135" - wire $ternary$libresoc.v:127963$5487_Y - attribute \src "libresoc.v:127965.19-127965.136" - wire $ternary$libresoc.v:127965$5489_Y - attribute \src "libresoc.v:127966.19-127966.136" - wire $ternary$libresoc.v:127966$5490_Y - attribute \src "libresoc.v:127967.19-127967.135" - wire $ternary$libresoc.v:127967$5491_Y - attribute \src "libresoc.v:127968.19-127968.136" - wire $ternary$libresoc.v:127968$5492_Y - attribute \src "libresoc.v:127969.19-127969.136" - wire $ternary$libresoc.v:127969$5493_Y - attribute \src "libresoc.v:127970.19-127970.135" - wire $ternary$libresoc.v:127970$5494_Y - attribute \src "libresoc.v:127971.19-127971.136" - wire $ternary$libresoc.v:127971$5495_Y - attribute \src "libresoc.v:127972.19-127972.136" - wire $ternary$libresoc.v:127972$5496_Y - attribute \src "libresoc.v:127973.19-127973.135" - wire $ternary$libresoc.v:127973$5497_Y - attribute \src "libresoc.v:127974.19-127974.136" - wire $ternary$libresoc.v:127974$5498_Y - attribute \src "libresoc.v:128061.18-128061.130" - wire $ternary$libresoc.v:128061$5586_Y - attribute \src "libresoc.v:128062.18-128062.130" - wire $ternary$libresoc.v:128062$5587_Y - attribute \src "libresoc.v:128063.18-128063.130" - wire $ternary$libresoc.v:128063$5588_Y - attribute \src "libresoc.v:128064.18-128064.131" - wire $ternary$libresoc.v:128064$5589_Y - attribute \src "libresoc.v:128066.18-128066.130" - wire $ternary$libresoc.v:128066$5591_Y - attribute \src "libresoc.v:128067.18-128067.131" - wire $ternary$libresoc.v:128067$5592_Y - attribute \src "libresoc.v:128068.18-128068.131" - wire $ternary$libresoc.v:128068$5593_Y - attribute \src "libresoc.v:128069.18-128069.130" - wire $ternary$libresoc.v:128069$5594_Y - attribute \src "libresoc.v:128070.18-128070.131" - wire $ternary$libresoc.v:128070$5595_Y - attribute \src "libresoc.v:128071.18-128071.132" - wire $ternary$libresoc.v:128071$5596_Y - attribute \src "libresoc.v:128072.18-128072.132" - wire $ternary$libresoc.v:128072$5597_Y - attribute \src "libresoc.v:128073.18-128073.133" - wire $ternary$libresoc.v:128073$5598_Y - attribute \src "libresoc.v:128074.18-128074.133" - wire $ternary$libresoc.v:128074$5599_Y - attribute \src "libresoc.v:128075.18-128075.132" - wire $ternary$libresoc.v:128075$5600_Y - attribute \src "libresoc.v:128077.18-128077.133" - wire $ternary$libresoc.v:128077$5602_Y - attribute \src "libresoc.v:128078.18-128078.133" - wire $ternary$libresoc.v:128078$5603_Y - attribute \src "libresoc.v:128079.18-128079.132" - wire $ternary$libresoc.v:128079$5604_Y - attribute \src "libresoc.v:128080.18-128080.133" - wire $ternary$libresoc.v:128080$5605_Y - attribute \src "libresoc.v:128081.18-128081.133" - wire $ternary$libresoc.v:128081$5606_Y - attribute \src "libresoc.v:128082.18-128082.132" - wire $ternary$libresoc.v:128082$5607_Y - attribute \src "libresoc.v:128083.18-128083.133" - wire $ternary$libresoc.v:128083$5608_Y - attribute \src "libresoc.v:128084.18-128084.133" - wire $ternary$libresoc.v:128084$5609_Y - attribute \src "libresoc.v:128085.18-128085.132" - wire $ternary$libresoc.v:128085$5610_Y - attribute \src "libresoc.v:128086.18-128086.133" - wire $ternary$libresoc.v:128086$5611_Y - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$129 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$131 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$133 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$135 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$137 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$139 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$141 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$143 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$145 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$147 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$149 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$151 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$153 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$155 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$157 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$159 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$161 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$163 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$165 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$167 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$169 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$171 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$173 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$175 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$177 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$179 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$181 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$183 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$185 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$187 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$189 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$191 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$193 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$195 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$197 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$199 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$201 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$203 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$205 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$207 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$209 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$211 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$213 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$215 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$217 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$219 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$221 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$223 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$225 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$227 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$229 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$231 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$233 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$235 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$237 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$239 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$241 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$243 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$245 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$247 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$249 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$251 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$253 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$255 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$257 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$259 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$261 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$263 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$265 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$267 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$269 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$271 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$273 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$275 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$277 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$279 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$281 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$283 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$285 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$287 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$289 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$291 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$293 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$295 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$297 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$299 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$301 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$303 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$305 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$307 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$309 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$311 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$313 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$315 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$317 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$319 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$321 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$323 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$325 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$327 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$329 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$331 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$333 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$335 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$337 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$339 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$341 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$343 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$345 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$347 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$349 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$351 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$353 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$355 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$357 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$359 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$361 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$363 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$365 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$367 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$369 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$371 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$373 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$375 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$377 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$379 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$381 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$383 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$385 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$387 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$389 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$391 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$393 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$395 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$397 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$399 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$401 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$403 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$405 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$407 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$409 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$411 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$413 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$415 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$417 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$419 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$421 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$423 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$425 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$427 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$429 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$431 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$433 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$435 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$437 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$439 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$441 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$443 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$445 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$447 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$449 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$451 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$453 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$455 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$457 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$459 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$465 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$473 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$475 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$477 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$479 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$481 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$483 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$484 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$487 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$489 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$491 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - wire \$493 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$495 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$496 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$498 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$499 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 8 \$501 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$504 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$506 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$508 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - wire \$510 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$512 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$513 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$515 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$516 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 328 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 164 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 319 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 329 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" - wire \TAP_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" - wire \_fsm_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" - wire \_fsm_isdr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" - wire \_fsm_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" - wire \_fsm_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" - wire \_fsm_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" - wire \_idblock_TAP_id_tdo - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" - wire \_idblock_id_bypass - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" - wire \_idblock_select_id - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" - wire width 4 \_irblock_ir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" - wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 330 \clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire input 6 \dmi0__ack_o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 output 2 \dmi0__addr_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 \dmi0__addr_i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 output 5 \dmi0__din - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \dmi0__din$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 input 7 \dmi0__dout - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 3 \dmi0__req_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire output 4 \dmi0__we_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire width 8 \dmi0_addrsr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire width 8 \dmi0_addrsr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire \dmi0_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" - wire \dmi0_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \dmi0_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \dmi0_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 8 \dmi0_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 8 \dmi0_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \dmi0_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \dmi0_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 64 \dmi0_datasr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 2 \dmi0_datasr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" - wire width 2 \dmi0_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \dmi0_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire width 2 \dmi0_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \dmi0_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \dmi0_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \dmi0_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \dmi0_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \dmi0_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \dmi0_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 10 \eint_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \eint_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 11 \eint_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \eint_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 12 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - wire width 3 \fsm_state - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$503$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - wire width 3 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \gpio_e10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 21 \gpio_e10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 19 \gpio_e10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 23 \gpio_e11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \gpio_e11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \gpio_e11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \gpio_e12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 14 \gpio_e8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 15 \gpio_e8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 13 \gpio_e8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 17 \gpio_e9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 18 \gpio_e9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 16 \gpio_e9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_s0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_s0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_s0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_s1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_s1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_s1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_s2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_s2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_s2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_s3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_s3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_s3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_s4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_s4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s7__pad__oe - attribute \src "libresoc.v:126401.7-126401.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 154 \io_bd$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" - wire \io_bd2core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" - wire \io_bd2io - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" - wire \io_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" - wire \io_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 154 \io_sr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" - wire \io_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 326 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 320 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 \jtag_wb__adr$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 322 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 327 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 325 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 \jtag_wb__dat_w$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 321 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 323 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 324 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire width 29 \jtag_wb_addrsr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire width 29 \jtag_wb_addrsr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire \jtag_wb_addrsr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" - wire \jtag_wb_addrsr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \jtag_wb_addrsr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \jtag_wb_addrsr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 29 \jtag_wb_addrsr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 29 \jtag_wb_addrsr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \jtag_wb_addrsr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \jtag_wb_addrsr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_addrsr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_addrsr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_addrsr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_addrsr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__i$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 64 \jtag_wb_datasr__o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 2 \jtag_wb_datasr__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" - wire width 2 \jtag_wb_datasr__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \jtag_wb_datasr_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire width 2 \jtag_wb_datasr_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \jtag_wb_datasr_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 64 \jtag_wb_datasr_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \jtag_wb_datasr_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \jtag_wb_datasr_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_datasr_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \jtag_wb_datasr_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_datasr_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \jtag_wb_datasr_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \mspi0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \mspi0_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi0_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \mspi0_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \mspi0_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \negjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" - wire \negjtag_rst - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire \posjtag_clk - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" - wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 1 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_a_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_a_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_a_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_ba_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_ba_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_ba_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_ba_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_cas_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_cas_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_cke__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_cke__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_clock__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_clock__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire width 3 \sr0__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire width 3 \sr0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire \sr0__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" - wire \sr0__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \sr0_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \sr0_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 3 \sr0_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 3 \sr0_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \sr0_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \sr0_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr0_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr0_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr0_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr0_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__ie - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire width 2 \sr5__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" - wire \sr5__oe$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" - wire \sr5_capture - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" - wire \sr5_isir - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" - wire width 2 \sr5_reg$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" - wire \sr5_shift - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" - wire \sr5_update - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr5_update_core - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" - wire \sr5_update_core$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr5_update_core_prev - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" - wire \sr5_update_core_prev$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire output 8 \wb_dcache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire \wb_dcache_en$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire output 9 \wb_icache_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire \wb_icache_en$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:128051$5575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 29 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:128051$5575_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:128053$5577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 29 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 30 - connect \A \jtag_wb__adr - connect \B 1'1 - connect \Y $add$libresoc.v:128053$5577_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:128059$5584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0__addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:128059$5584_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:128060$5585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \dmi0__addr_i - connect \B 1'1 - connect \Y $add$libresoc.v:128060$5585_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:127875$5399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$15 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:127875$5399_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:127942$5466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$27 - connect \Y $and$libresoc.v:127942$5466_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:127953$5477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$29 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:127953$5477_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:127981$5505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$367 - connect \Y $and$libresoc.v:127981$5505_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127984$5508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$373 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:127984$5508_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127987$5511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$377 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:127987$5511_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:127989$5513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$381 - connect \B \_fsm_update - connect \Y $and$libresoc.v:127989$5513_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:127991$5515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_update_core_prev - connect \B \$385 - connect \Y $and$libresoc.v:127991$5515_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:127994$5518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$391 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:127994$5518_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:127996$5520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$395 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:127996$5520_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:128000$5524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$399 - connect \B \_fsm_update - connect \Y $and$libresoc.v:128000$5524_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:128002$5526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$403 - connect \Y $and$libresoc.v:128002$5526_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:128006$5530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$411 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:128006$5530_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:128008$5532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$415 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:128008$5532_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:128011$5535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$419 - connect \B \_fsm_update - connect \Y $and$libresoc.v:128011$5535_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:128013$5537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core_prev - connect \B \$423 - connect \Y $and$libresoc.v:128013$5537_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:128016$5540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$429 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:128016$5540_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:128018$5542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$433 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:128018$5542_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:128020$5544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$41 - connect \Y $and$libresoc.v:128020$5544_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:128021$5545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$437 - connect \B \_fsm_update - connect \Y $and$libresoc.v:128021$5545_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:128023$5547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core_prev - connect \B \$441 - connect \Y $and$libresoc.v:128023$5547_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:128027$5551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$449 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:128027$5551_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:128029$5553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$453 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:128029$5553_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:128031$5555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \_fsm_update - connect \Y $and$libresoc.v:128031$5555_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:128032$5556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$457 - connect \B \_fsm_update - connect \Y $and$libresoc.v:128032$5556_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:128034$5558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core_prev - connect \B \$461 - connect \Y $and$libresoc.v:128034$5558_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:128037$5561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$467 - connect \B \_fsm_capture - connect \Y $and$libresoc.v:128037$5561_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:128039$5563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$471 - connect \B \_fsm_shift - connect \Y $and$libresoc.v:128039$5563_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:128041$5565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$475 - connect \B \_fsm_update - connect \Y $and$libresoc.v:128041$5565_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:128044$5568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_update_core_prev - connect \B \$479 - connect \Y $and$libresoc.v:128044$5568_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:128076$5601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$5 - connect \Y $and$libresoc.v:128076$5601_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:127831$5355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:127831$5355_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127842$5366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:127842$5366_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127853$5377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:127853$5377_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:127886$5410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'1 - connect \Y $eq$libresoc.v:127886$5410_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127887$5411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:127887$5411_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127898$5422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:127898$5422_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:127920$5444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:127920$5444_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127964$5488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:127964$5488_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127975$5499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:127975$5499_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127976$5500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:127976$5500_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:127977$5501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:127977$5501_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:127979$5503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:127979$5503_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127982$5506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'100 - connect \Y $eq$libresoc.v:127982$5506_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:127992$5516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'101 - connect \Y $eq$libresoc.v:127992$5516_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:127997$5521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:127997$5521_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:127998$5522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:127998$5522_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:128003$5527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'110 - connect \Y $eq$libresoc.v:128003$5527_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:128004$5528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 3'111 - connect \Y $eq$libresoc.v:128004$5528_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:128014$5538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1000 - connect \Y $eq$libresoc.v:128014$5538_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:128024$5548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1001 - connect \Y $eq$libresoc.v:128024$5548_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:128025$5549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1010 - connect \Y $eq$libresoc.v:128025$5549_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:128035$5559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 4'1011 - connect \Y $eq$libresoc.v:128035$5559_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:128042$5566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:128042$5566_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:128045$5569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'0 - connect \Y $eq$libresoc.v:128045$5569_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:128047$5571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 1'1 - connect \Y $eq$libresoc.v:128047$5571_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:128048$5572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:128048$5572_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:128050$5574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state - connect \B 2'10 - connect \Y $eq$libresoc.v:128050$5574_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:128052$5576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:128052$5576_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:128055$5580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 1'1 - connect \Y $eq$libresoc.v:128055$5580_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:128056$5581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 2'10 - connect \Y $eq$libresoc.v:128056$5581_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:128058$5583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \fsm_state$503 - connect \B 2'10 - connect \Y $eq$libresoc.v:128058$5583_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:128054$5578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:128054$5578_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127983$5507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:127983$5507_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127985$5509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:127985$5509_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127988$5512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:127988$5512_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:127993$5517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:127993$5517_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:127995$5519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:127995$5519_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:127999$5523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:127999$5523_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:128005$5529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128005$5529_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:128007$5531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128007$5531_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:128010$5534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128010$5534_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:128015$5539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128015$5539_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:128017$5541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128017$5541_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:128019$5543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128019$5543_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:128026$5550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128026$5550_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:128028$5552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128028$5552_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:128030$5554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128030$5554_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:128036$5560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128036$5560_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:128038$5562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128038$5562_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:128040$5564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_isir - connect \B 1'0 - connect \Y $ne$libresoc.v:128040$5564_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:127990$5514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr0_update_core - connect \Y $not$libresoc.v:127990$5514_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:128001$5525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:128001$5525_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:128012$5536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:128012$5536_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:128022$5546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:128022$5546_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:128033$5557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:128033$5557_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:128043$5567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sr5_update_core - connect \Y $not$libresoc.v:128043$5567_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:128046$5570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$484 - connect \Y $not$libresoc.v:128046$5570_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127864$5388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$11 - connect \B \$13 - connect \Y $or$libresoc.v:127864$5388_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127909$5433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \$21 - connect \Y $or$libresoc.v:127909$5433_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:127931$5455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $or$libresoc.v:127931$5455_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127978$5502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $or$libresoc.v:127978$5502_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:127980$5504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$363 - connect \B \$365 - connect \Y $or$libresoc.v:127980$5504_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:127986$5510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$libresoc.v:127986$5510_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:128009$5533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$37 - connect \B \$39 - connect \Y $or$libresoc.v:128009$5533_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:128049$5573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$487 - connect \B \$489 - connect \Y $or$libresoc.v:128049$5573_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:128057$5582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$504 - connect \B \$506 - connect \Y $or$libresoc.v:128057$5582_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:128065$5590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$1 - connect \B \$3 - connect \Y $or$libresoc.v:128065$5590_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:128054$5579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:128054$5578_Y - connect \Y $pos$libresoc.v:128054$5579_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127832$5356 - parameter \WIDTH 1 - connect \A \gpio_e15__pad__i - connect \B \io_bd [24] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127832$5356_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127833$5357 - parameter \WIDTH 1 - connect \A \gpio_e15__core__o - connect \B \io_bd [25] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127833$5357_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127834$5358 - parameter \WIDTH 1 - connect \A \gpio_e15__core__oe - connect \B \io_bd [26] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127834$5358_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127835$5359 - parameter \WIDTH 1 - connect \A \gpio_s0__pad__i - connect \B \io_bd [27] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127835$5359_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127836$5360 - parameter \WIDTH 1 - connect \A \gpio_s0__core__o - connect \B \io_bd [28] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127836$5360_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127837$5361 - parameter \WIDTH 1 - connect \A \gpio_s0__core__oe - connect \B \io_bd [29] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127837$5361_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127838$5362 - parameter \WIDTH 1 - connect \A \gpio_s1__pad__i - connect \B \io_bd [30] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127838$5362_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127839$5363 - parameter \WIDTH 1 - connect \A \gpio_s1__core__o - connect \B \io_bd [31] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127839$5363_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127840$5364 - parameter \WIDTH 1 - connect \A \gpio_s1__core__oe - connect \B \io_bd [32] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127840$5364_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127841$5365 - parameter \WIDTH 1 - connect \A \gpio_s2__pad__i - connect \B \io_bd [33] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127841$5365_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127843$5367 - parameter \WIDTH 1 - connect \A \gpio_s2__core__o - connect \B \io_bd [34] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127843$5367_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127844$5368 - parameter \WIDTH 1 - connect \A \gpio_s2__core__oe - connect \B \io_bd [35] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127844$5368_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127845$5369 - parameter \WIDTH 1 - connect \A \gpio_s3__pad__i - connect \B \io_bd [36] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127845$5369_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127846$5370 - parameter \WIDTH 1 - connect \A \gpio_s3__core__o - connect \B \io_bd [37] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127846$5370_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127847$5371 - parameter \WIDTH 1 - connect \A \gpio_s3__core__oe - connect \B \io_bd [38] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127847$5371_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127848$5372 - parameter \WIDTH 1 - connect \A \gpio_s4__pad__i - connect \B \io_bd [39] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127848$5372_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127849$5373 - parameter \WIDTH 1 - connect \A \gpio_s4__core__o - connect \B \io_bd [40] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127849$5373_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127850$5374 - parameter \WIDTH 1 - connect \A \gpio_s4__core__oe - connect \B \io_bd [41] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127850$5374_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127851$5375 - parameter \WIDTH 1 - connect \A \gpio_s5__pad__i - connect \B \io_bd [42] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127851$5375_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127852$5376 - parameter \WIDTH 1 - connect \A \gpio_s5__core__o - connect \B \io_bd [43] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127852$5376_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127854$5378 - parameter \WIDTH 1 - connect \A \gpio_s5__core__oe - connect \B \io_bd [44] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127854$5378_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127855$5379 - parameter \WIDTH 1 - connect \A \gpio_s6__pad__i - connect \B \io_bd [45] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127855$5379_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127856$5380 - parameter \WIDTH 1 - connect \A \gpio_s6__core__o - connect \B \io_bd [46] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127856$5380_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127857$5381 - parameter \WIDTH 1 - connect \A \gpio_s6__core__oe - connect \B \io_bd [47] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127857$5381_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127858$5382 - parameter \WIDTH 1 - connect \A \gpio_s7__pad__i - connect \B \io_bd [48] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127858$5382_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127859$5383 - parameter \WIDTH 1 - connect \A \gpio_s7__core__o - connect \B \io_bd [49] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127859$5383_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127860$5384 - parameter \WIDTH 1 - connect \A \gpio_s7__core__oe - connect \B \io_bd [50] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127860$5384_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127861$5385 - parameter \WIDTH 1 - connect \A \mspi0_clk__core__o - connect \B \io_bd [51] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127861$5385_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127862$5386 - parameter \WIDTH 1 - connect \A \mspi0_cs_n__core__o - connect \B \io_bd [52] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127862$5386_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127863$5387 - parameter \WIDTH 1 - connect \A \mspi0_mosi__core__o - connect \B \io_bd [53] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127863$5387_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:127865$5389 - parameter \WIDTH 1 - connect \A \mspi0_miso__pad__i - connect \B \io_bd [54] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127865$5389_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127866$5390 - parameter \WIDTH 1 - connect \A \mspi1_clk__core__o - connect \B \io_bd [55] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127866$5390_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127867$5391 - parameter \WIDTH 1 - connect \A \mspi1_cs_n__core__o - connect \B \io_bd [56] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127867$5391_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127868$5392 - parameter \WIDTH 1 - connect \A \mspi1_mosi__core__o - connect \B \io_bd [57] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127868$5392_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:127869$5393 - parameter \WIDTH 1 - connect \A \mspi1_miso__pad__i - connect \B \io_bd [58] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127869$5393_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127870$5394 - parameter \WIDTH 1 - connect \A \mtwi_sda__pad__i - connect \B \io_bd [59] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127870$5394_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127871$5395 - parameter \WIDTH 1 - connect \A \mtwi_sda__core__o - connect \B \io_bd [60] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127871$5395_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127872$5396 - parameter \WIDTH 1 - connect \A \mtwi_sda__core__oe - connect \B \io_bd [61] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127872$5396_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127873$5397 - parameter \WIDTH 1 - connect \A \mtwi_scl__core__o - connect \B \io_bd [62] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127873$5397_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127874$5398 - parameter \WIDTH 1 - connect \A \pwm_0__core__o - connect \B \io_bd [63] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127874$5398_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127876$5400 - parameter \WIDTH 1 - connect \A \pwm_1__core__o - connect \B \io_bd [64] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127876$5400_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127877$5401 - parameter \WIDTH 1 - connect \A \sd0_cmd__pad__i - connect \B \io_bd [65] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127877$5401_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127878$5402 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__o - connect \B \io_bd [66] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127878$5402_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127879$5403 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__oe - connect \B \io_bd [67] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127879$5403_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127880$5404 - parameter \WIDTH 1 - connect \A \sd0_clk__core__o - connect \B \io_bd [68] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127880$5404_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127881$5405 - parameter \WIDTH 1 - connect \A \sd0_data0__pad__i - connect \B \io_bd [69] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127881$5405_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127882$5406 - parameter \WIDTH 1 - connect \A \sd0_data0__core__o - connect \B \io_bd [70] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127882$5406_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127883$5407 - parameter \WIDTH 1 - connect \A \sd0_data0__core__oe - connect \B \io_bd [71] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127883$5407_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127884$5408 - parameter \WIDTH 1 - connect \A \sd0_data1__pad__i - connect \B \io_bd [72] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127884$5408_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127885$5409 - parameter \WIDTH 1 - connect \A \sd0_data1__core__o - connect \B \io_bd [73] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127885$5409_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127888$5412 - parameter \WIDTH 1 - connect \A \sd0_data1__core__oe - connect \B \io_bd [74] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127888$5412_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127889$5413 - parameter \WIDTH 1 - connect \A \sd0_data2__pad__i - connect \B \io_bd [75] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127889$5413_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127890$5414 - parameter \WIDTH 1 - connect \A \sd0_data2__core__o - connect \B \io_bd [76] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127890$5414_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127891$5415 - parameter \WIDTH 1 - connect \A \sd0_data2__core__oe - connect \B \io_bd [77] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127891$5415_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127892$5416 - parameter \WIDTH 1 - connect \A \sd0_data3__pad__i - connect \B \io_bd [78] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127892$5416_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127893$5417 - parameter \WIDTH 1 - connect \A \sd0_data3__core__o - connect \B \io_bd [79] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127893$5417_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127894$5418 - parameter \WIDTH 1 - connect \A \sd0_data3__core__oe - connect \B \io_bd [80] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127894$5418_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127895$5419 - parameter \WIDTH 1 - connect \A \sdr_dm_0__core__o - connect \B \io_bd [81] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127895$5419_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127896$5420 - parameter \WIDTH 1 - connect \A \sdr_dq_0__pad__i - connect \B \io_bd [82] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127896$5420_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127897$5421 - parameter \WIDTH 1 - connect \A \sdr_dq_0__core__o - connect \B \io_bd [83] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127897$5421_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127899$5423 - parameter \WIDTH 1 - connect \A \sdr_dq_0__core__oe - connect \B \io_bd [84] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127899$5423_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127900$5424 - parameter \WIDTH 1 - connect \A \sdr_dq_1__pad__i - connect \B \io_bd [85] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127900$5424_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127901$5425 - parameter \WIDTH 1 - connect \A \sdr_dq_1__core__o - connect \B \io_bd [86] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127901$5425_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127902$5426 - parameter \WIDTH 1 - connect \A \sdr_dq_1__core__oe - connect \B \io_bd [87] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127902$5426_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127903$5427 - parameter \WIDTH 1 - connect \A \sdr_dq_2__pad__i - connect \B \io_bd [88] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127903$5427_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127904$5428 - parameter \WIDTH 1 - connect \A \sdr_dq_2__core__o - connect \B \io_bd [89] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127904$5428_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127905$5429 - parameter \WIDTH 1 - connect \A \sdr_dq_2__core__oe - connect \B \io_bd [90] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127905$5429_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127906$5430 - parameter \WIDTH 1 - connect \A \sdr_dq_3__pad__i - connect \B \io_bd [91] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127906$5430_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127907$5431 - parameter \WIDTH 1 - connect \A \sdr_dq_3__core__o - connect \B \io_bd [92] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127907$5431_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127908$5432 - parameter \WIDTH 1 - connect \A \sdr_dq_3__core__oe - connect \B \io_bd [93] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127908$5432_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127910$5434 - parameter \WIDTH 1 - connect \A \sdr_dq_4__pad__i - connect \B \io_bd [94] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127910$5434_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127911$5435 - parameter \WIDTH 1 - connect \A \sdr_dq_4__core__o - connect \B \io_bd [95] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127911$5435_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127912$5436 - parameter \WIDTH 1 - connect \A \sdr_dq_4__core__oe - connect \B \io_bd [96] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127912$5436_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127913$5437 - parameter \WIDTH 1 - connect \A \sdr_dq_5__pad__i - connect \B \io_bd [97] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127913$5437_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127914$5438 - parameter \WIDTH 1 - connect \A \sdr_dq_5__core__o - connect \B \io_bd [98] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127914$5438_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127915$5439 - parameter \WIDTH 1 - connect \A \sdr_dq_5__core__oe - connect \B \io_bd [99] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127915$5439_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127916$5440 - parameter \WIDTH 1 - connect \A \sdr_dq_6__pad__i - connect \B \io_bd [100] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127916$5440_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127917$5441 - parameter \WIDTH 1 - connect \A \sdr_dq_6__core__o - connect \B \io_bd [101] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127917$5441_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127918$5442 - parameter \WIDTH 1 - connect \A \sdr_dq_6__core__oe - connect \B \io_bd [102] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127918$5442_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127919$5443 - parameter \WIDTH 1 - connect \A \sdr_dq_7__pad__i - connect \B \io_bd [103] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127919$5443_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127921$5445 - parameter \WIDTH 1 - connect \A \sdr_dq_7__core__o - connect \B \io_bd [104] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127921$5445_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127922$5446 - parameter \WIDTH 1 - connect \A \sdr_dq_7__core__oe - connect \B \io_bd [105] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127922$5446_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127923$5447 - parameter \WIDTH 1 - connect \A \sdr_a_0__core__o - connect \B \io_bd [106] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127923$5447_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127924$5448 - parameter \WIDTH 1 - connect \A \sdr_a_1__core__o - connect \B \io_bd [107] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127924$5448_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127925$5449 - parameter \WIDTH 1 - connect \A \sdr_a_2__core__o - connect \B \io_bd [108] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127925$5449_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127926$5450 - parameter \WIDTH 1 - connect \A \sdr_a_3__core__o - connect \B \io_bd [109] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127926$5450_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127927$5451 - parameter \WIDTH 1 - connect \A \sdr_a_4__core__o - connect \B \io_bd [110] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127927$5451_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127928$5452 - parameter \WIDTH 1 - connect \A \sdr_a_5__core__o - connect \B \io_bd [111] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127928$5452_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127929$5453 - parameter \WIDTH 1 - connect \A \sdr_a_6__core__o - connect \B \io_bd [112] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127929$5453_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127930$5454 - parameter \WIDTH 1 - connect \A \sdr_a_7__core__o - connect \B \io_bd [113] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127930$5454_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127932$5456 - parameter \WIDTH 1 - connect \A \sdr_a_8__core__o - connect \B \io_bd [114] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127932$5456_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127933$5457 - parameter \WIDTH 1 - connect \A \sdr_a_9__core__o - connect \B \io_bd [115] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127933$5457_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127934$5458 - parameter \WIDTH 1 - connect \A \sdr_ba_0__core__o - connect \B \io_bd [116] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127934$5458_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127935$5459 - parameter \WIDTH 1 - connect \A \sdr_ba_1__core__o - connect \B \io_bd [117] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127935$5459_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127936$5460 - parameter \WIDTH 1 - connect \A \sdr_clock__core__o - connect \B \io_bd [118] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127936$5460_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127937$5461 - parameter \WIDTH 1 - connect \A \sdr_cke__core__o - connect \B \io_bd [119] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127937$5461_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127938$5462 - parameter \WIDTH 1 - connect \A \sdr_ras_n__core__o - connect \B \io_bd [120] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127938$5462_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127939$5463 - parameter \WIDTH 1 - connect \A \sdr_cas_n__core__o - connect \B \io_bd [121] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127939$5463_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127940$5464 - parameter \WIDTH 1 - connect \A \sdr_we_n__core__o - connect \B \io_bd [122] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127940$5464_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127941$5465 - parameter \WIDTH 1 - connect \A \sdr_cs_n__core__o - connect \B \io_bd [123] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127941$5465_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127943$5467 - parameter \WIDTH 1 - connect \A \sdr_a_10__core__o - connect \B \io_bd [124] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127943$5467_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127944$5468 - parameter \WIDTH 1 - connect \A \sdr_a_11__core__o - connect \B \io_bd [125] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127944$5468_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:127945$5469 - parameter \WIDTH 1 - connect \A \sdr_a_12__core__o - connect \B \io_bd [126] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127945$5469_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127946$5470 - parameter \WIDTH 1 - connect \A \sdr_dm_1__pad__i - connect \B \io_bd [127] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127946$5470_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127947$5471 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__o - connect \B \io_bd [128] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127947$5471_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127948$5472 - parameter \WIDTH 1 - connect \A \sdr_dm_1__core__oe - connect \B \io_bd [129] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127948$5472_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127949$5473 - parameter \WIDTH 1 - connect \A \sdr_dq_8__pad__i - connect \B \io_bd [130] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127949$5473_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127950$5474 - parameter \WIDTH 1 - connect \A \sdr_dq_8__core__o - connect \B \io_bd [131] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127950$5474_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127951$5475 - parameter \WIDTH 1 - connect \A \sdr_dq_8__core__oe - connect \B \io_bd [132] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127951$5475_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127952$5476 - parameter \WIDTH 1 - connect \A \sdr_dq_9__pad__i - connect \B \io_bd [133] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127952$5476_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127954$5478 - parameter \WIDTH 1 - connect \A \sdr_dq_9__core__o - connect \B \io_bd [134] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127954$5478_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127955$5479 - parameter \WIDTH 1 - connect \A \sdr_dq_9__core__oe - connect \B \io_bd [135] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127955$5479_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127956$5480 - parameter \WIDTH 1 - connect \A \sdr_dq_10__pad__i - connect \B \io_bd [136] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127956$5480_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127957$5481 - parameter \WIDTH 1 - connect \A \sdr_dq_10__core__o - connect \B \io_bd [137] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127957$5481_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127958$5482 - parameter \WIDTH 1 - connect \A \sdr_dq_10__core__oe - connect \B \io_bd [138] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127958$5482_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127959$5483 - parameter \WIDTH 1 - connect \A \sdr_dq_11__pad__i - connect \B \io_bd [139] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127959$5483_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127960$5484 - parameter \WIDTH 1 - connect \A \sdr_dq_11__core__o - connect \B \io_bd [140] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127960$5484_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127961$5485 - parameter \WIDTH 1 - connect \A \sdr_dq_11__core__oe - connect \B \io_bd [141] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127961$5485_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127962$5486 - parameter \WIDTH 1 - connect \A \sdr_dq_12__pad__i - connect \B \io_bd [142] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127962$5486_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127963$5487 - parameter \WIDTH 1 - connect \A \sdr_dq_12__core__o - connect \B \io_bd [143] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127963$5487_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127965$5489 - parameter \WIDTH 1 - connect \A \sdr_dq_12__core__oe - connect \B \io_bd [144] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127965$5489_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127966$5490 - parameter \WIDTH 1 - connect \A \sdr_dq_13__pad__i - connect \B \io_bd [145] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127966$5490_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127967$5491 - parameter \WIDTH 1 - connect \A \sdr_dq_13__core__o - connect \B \io_bd [146] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127967$5491_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127968$5492 - parameter \WIDTH 1 - connect \A \sdr_dq_13__core__oe - connect \B \io_bd [147] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127968$5492_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127969$5493 - parameter \WIDTH 1 - connect \A \sdr_dq_14__pad__i - connect \B \io_bd [148] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127969$5493_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127970$5494 - parameter \WIDTH 1 - connect \A \sdr_dq_14__core__o - connect \B \io_bd [149] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127970$5494_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127971$5495 - parameter \WIDTH 1 - connect \A \sdr_dq_14__core__oe - connect \B \io_bd [150] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127971$5495_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:127972$5496 - parameter \WIDTH 1 - connect \A \sdr_dq_15__pad__i - connect \B \io_bd [151] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:127972$5496_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:127973$5497 - parameter \WIDTH 1 - connect \A \sdr_dq_15__core__o - connect \B \io_bd [152] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127973$5497_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:127974$5498 - parameter \WIDTH 1 - connect \A \sdr_dq_15__core__oe - connect \B \io_bd [153] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:127974$5498_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:128061$5586 - parameter \WIDTH 1 - connect \A \eint_0__pad__i - connect \B \io_bd [0] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128061$5586_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:128062$5587 - parameter \WIDTH 1 - connect \A \eint_1__pad__i - connect \B \io_bd [1] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128062$5587_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:128063$5588 - parameter \WIDTH 1 - connect \A \eint_2__pad__i - connect \B \io_bd [2] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128063$5588_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:128064$5589 - parameter \WIDTH 1 - connect \A \gpio_e8__pad__i - connect \B \io_bd [3] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128064$5589_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:128066$5591 - parameter \WIDTH 1 - connect \A \gpio_e8__core__o - connect \B \io_bd [4] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128066$5591_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:128067$5592 - parameter \WIDTH 1 - connect \A \gpio_e8__core__oe - connect \B \io_bd [5] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128067$5592_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:128068$5593 - parameter \WIDTH 1 - connect \A \gpio_e9__pad__i - connect \B \io_bd [6] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128068$5593_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:128069$5594 - parameter \WIDTH 1 - connect \A \gpio_e9__core__o - connect \B \io_bd [7] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128069$5594_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:128070$5595 - parameter \WIDTH 1 - connect \A \gpio_e9__core__oe - connect \B \io_bd [8] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128070$5595_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:128071$5596 - parameter \WIDTH 1 - connect \A \gpio_e10__pad__i - connect \B \io_bd [9] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128071$5596_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:128072$5597 - parameter \WIDTH 1 - connect \A \gpio_e10__core__o - connect \B \io_bd [10] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128072$5597_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:128073$5598 - parameter \WIDTH 1 - connect \A \gpio_e10__core__oe - connect \B \io_bd [11] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128073$5598_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:128074$5599 - parameter \WIDTH 1 - connect \A \gpio_e11__pad__i - connect \B \io_bd [12] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128074$5599_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:128075$5600 - parameter \WIDTH 1 - connect \A \gpio_e11__core__o - connect \B \io_bd [13] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128075$5600_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:128077$5602 - parameter \WIDTH 1 - connect \A \gpio_e11__core__oe - connect \B \io_bd [14] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128077$5602_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:128078$5603 - parameter \WIDTH 1 - connect \A \gpio_e12__pad__i - connect \B \io_bd [15] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128078$5603_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:128079$5604 - parameter \WIDTH 1 - connect \A \gpio_e12__core__o - connect \B \io_bd [16] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128079$5604_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:128080$5605 - parameter \WIDTH 1 - connect \A \gpio_e12__core__oe - connect \B \io_bd [17] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128080$5605_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:128081$5606 - parameter \WIDTH 1 - connect \A \gpio_e13__pad__i - connect \B \io_bd [18] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128081$5606_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:128082$5607 - parameter \WIDTH 1 - connect \A \gpio_e13__core__o - connect \B \io_bd [19] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128082$5607_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:128083$5608 - parameter \WIDTH 1 - connect \A \gpio_e13__core__oe - connect \B \io_bd [20] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128083$5608_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:128084$5609 - parameter \WIDTH 1 - connect \A \gpio_e14__pad__i - connect \B \io_bd [21] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:128084$5609_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:128085$5610 - parameter \WIDTH 1 - connect \A \gpio_e14__core__o - connect \B \io_bd [22] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128085$5610_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:128086$5611 - parameter \WIDTH 1 - connect \A \gpio_e14__core__oe - connect \B \io_bd [23] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:128086$5611_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:128159.8-128171.4" - cell \_fsm \_fsm - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tms \TAP_bus__tms - connect \capture \_fsm_capture - connect \isdr \_fsm_isdr - connect \isir \_fsm_isir - connect \negjtag_clk \negjtag_clk - connect \negjtag_rst \negjtag_rst - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \update \_fsm_update - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:128172.12-128182.4" - cell \_idblock \_idblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_id_tdo \_idblock_TAP_id_tdo - connect \capture \_fsm_capture - connect \id_bypass \_idblock_id_bypass - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \select_id \_idblock_select_id - connect \shift \_fsm_shift - connect \update \_fsm_update - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:128183.12-128193.4" - cell \_irblock \_irblock - connect \TAP_bus__tdi \TAP_bus__tdi - connect \capture \_fsm_capture - connect \ir \_irblock_ir - connect \isir \_fsm_isir - connect \posjtag_clk \posjtag_clk - connect \posjtag_rst \posjtag_rst - connect \shift \_fsm_shift - connect \tdo \_irblock_tdo - connect \update \_fsm_update - end - attribute \src "libresoc.v:126401.7-126401.20" - process $proc$libresoc.v:126401$5803 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:126959.13-126959.32" - process $proc$libresoc.v:126959$5804 - assign { } { } - assign $1\dmi0__addr_i[3:0] 4'0000 - sync always - sync init - update \dmi0__addr_i $1\dmi0__addr_i[3:0] - end - attribute \src "libresoc.v:126964.14-126964.46" - process $proc$libresoc.v:126964$5805 - assign { } { } - assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0__din $1\dmi0__din[63:0] - end - attribute \src "libresoc.v:126978.7-126978.29" - process $proc$libresoc.v:126978$5806 - assign { } { } - assign $1\dmi0_addrsr__oe[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] - end - attribute \src "libresoc.v:126986.13-126986.36" - process $proc$libresoc.v:126986$5807 - assign { } { } - assign $1\dmi0_addrsr_reg[7:0] 8'00000000 - sync always - sync init - update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] - end - attribute \src "libresoc.v:126994.7-126994.37" - process $proc$libresoc.v:126994$5808 - assign { } { } - assign $1\dmi0_addrsr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:126998.7-126998.42" - process $proc$libresoc.v:126998$5809 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 - sync always - sync init - update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:127002.14-127002.51" - process $proc$libresoc.v:127002$5810 - assign { } { } - assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:127008.13-127008.35" - process $proc$libresoc.v:127008$5811 - assign { } { } - assign $1\dmi0_datasr__oe[1:0] 2'00 - sync always - sync init - update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] - end - attribute \src "libresoc.v:127016.14-127016.52" - process $proc$libresoc.v:127016$5812 - assign { } { } - assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] - end - attribute \src "libresoc.v:127024.7-127024.37" - process $proc$libresoc.v:127024$5813 - assign { } { } - assign $1\dmi0_datasr_update_core[0:0] 1'0 - sync always - sync init - update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] - end - attribute \src "libresoc.v:127028.7-127028.42" - process $proc$libresoc.v:127028$5814 - assign { } { } - assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 - sync always - sync init - update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:127044.13-127044.29" - process $proc$libresoc.v:127044$5815 - assign { } { } - assign $1\fsm_state[2:0] 3'000 - sync always - sync init - update \fsm_state $1\fsm_state[2:0] - end - attribute \src "libresoc.v:127046.13-127046.35" - process $proc$libresoc.v:127046$5816 - assign { } { } - assign $0\fsm_state$503[2:0]$5817 3'000 - sync always - sync init - update \fsm_state$503 $0\fsm_state$503[2:0]$5817 - end - attribute \src "libresoc.v:127244.15-127244.67" - process $proc$libresoc.v:127244$5818 - assign { } { } - assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \io_bd $1\io_bd[153:0] - end - attribute \src "libresoc.v:127256.15-127256.67" - process $proc$libresoc.v:127256$5819 - assign { } { } - assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \io_sr $1\io_sr[153:0] - end - attribute \src "libresoc.v:127265.14-127265.41" - process $proc$libresoc.v:127265$5820 - assign { } { } - assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 - sync always - sync init - update \jtag_wb__adr $1\jtag_wb__adr[28:0] - end - attribute \src "libresoc.v:127274.14-127274.51" - process $proc$libresoc.v:127274$5821 - assign { } { } - assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] - end - attribute \src "libresoc.v:127288.7-127288.32" - process $proc$libresoc.v:127288$5822 - assign { } { } - assign $1\jtag_wb_addrsr__oe[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] - end - attribute \src "libresoc.v:127296.14-127296.47" - process $proc$libresoc.v:127296$5823 - assign { } { } - assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 - sync always - sync init - update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] - end - attribute \src "libresoc.v:127304.7-127304.40" - process $proc$libresoc.v:127304$5824 - assign { } { } - assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:127308.7-127308.45" - process $proc$libresoc.v:127308$5825 - assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 - sync always - sync init - update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:127312.14-127312.54" - process $proc$libresoc.v:127312$5826 - assign { } { } - assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] - end - attribute \src "libresoc.v:127318.13-127318.38" - process $proc$libresoc.v:127318$5827 - assign { } { } - assign $1\jtag_wb_datasr__oe[1:0] 2'00 - sync always - sync init - update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] - end - attribute \src "libresoc.v:127326.14-127326.55" - process $proc$libresoc.v:127326$5828 - assign { } { } - assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] - end - attribute \src "libresoc.v:127334.7-127334.40" - process $proc$libresoc.v:127334$5829 - assign { } { } - assign $1\jtag_wb_datasr_update_core[0:0] 1'0 - sync always - sync init - update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] - end - attribute \src "libresoc.v:127338.7-127338.45" - process $proc$libresoc.v:127338$5830 - assign { } { } - assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 - sync always - sync init - update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:127768.7-127768.21" - process $proc$libresoc.v:127768$5831 - assign { } { } - assign $1\sr0__oe[0:0] 1'0 - sync always - sync init - update \sr0__oe $1\sr0__oe[0:0] - end - attribute \src "libresoc.v:127776.13-127776.27" - process $proc$libresoc.v:127776$5832 - assign { } { } - assign $1\sr0_reg[2:0] 3'000 - sync always - sync init - update \sr0_reg $1\sr0_reg[2:0] - end - attribute \src "libresoc.v:127784.7-127784.29" - process $proc$libresoc.v:127784$5833 - assign { } { } - assign $1\sr0_update_core[0:0] 1'0 - sync always - sync init - update \sr0_update_core $1\sr0_update_core[0:0] - end - attribute \src "libresoc.v:127788.7-127788.34" - process $proc$libresoc.v:127788$5834 - assign { } { } - assign $1\sr0_update_core_prev[0:0] 1'0 - sync always - sync init - update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] - end - attribute \src "libresoc.v:127798.7-127798.21" - process $proc$libresoc.v:127798$5835 - assign { } { } - assign $1\sr5__oe[0:0] 1'0 - sync always - sync init - update \sr5__oe $1\sr5__oe[0:0] - end - attribute \src "libresoc.v:127806.13-127806.27" - process $proc$libresoc.v:127806$5836 - assign { } { } - assign $1\sr5_reg[1:0] 2'00 - sync always - sync init - update \sr5_reg $1\sr5_reg[1:0] - end - attribute \src "libresoc.v:127814.7-127814.29" - process $proc$libresoc.v:127814$5837 - assign { } { } - assign $1\sr5_update_core[0:0] 1'0 - sync always - sync init - update \sr5_update_core $1\sr5_update_core[0:0] - end - attribute \src "libresoc.v:127818.7-127818.34" - process $proc$libresoc.v:127818$5838 - assign { } { } - assign $1\sr5_update_core_prev[0:0] 1'0 - sync always - sync init - update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] - end - attribute \src "libresoc.v:127823.7-127823.26" - process $proc$libresoc.v:127823$5839 - assign { } { } - assign $1\wb_dcache_en[0:0] 1'1 - sync always - sync init - update \wb_dcache_en $1\wb_dcache_en[0:0] - end - attribute \src "libresoc.v:127828.7-127828.26" - process $proc$libresoc.v:127828$5840 - assign { } { } - assign $1\wb_icache_en[0:0] 1'1 - sync always - sync init - update \wb_icache_en $1\wb_icache_en[0:0] - end - attribute \src "libresoc.v:128087.3-128088.41" - process $proc$libresoc.v:128087$5612 - assign { } { } - assign $0\wb_icache_en[0:0] \wb_icache_en$next - sync posedge \clk - update \wb_icache_en $0\wb_icache_en[0:0] - end - attribute \src "libresoc.v:128089.3-128090.41" - process $proc$libresoc.v:128089$5613 - assign { } { } - assign $0\wb_dcache_en[0:0] \wb_dcache_en$next - sync posedge \clk - update \wb_dcache_en $0\wb_dcache_en[0:0] - end - attribute \src "libresoc.v:128091.3-128092.45" - process $proc$libresoc.v:128091$5614 - assign { } { } - assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next - sync posedge \clk - update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] - end - attribute \src "libresoc.v:128093.3-128094.35" - process $proc$libresoc.v:128093$5615 - assign { } { } - assign $0\dmi0__din[63:0] \dmi0__din$next - sync posedge \clk - update \dmi0__din $0\dmi0__din[63:0] - end - attribute \src "libresoc.v:128095.3-128096.45" - process $proc$libresoc.v:128095$5616 - assign { } { } - assign $0\fsm_state$503[2:0]$5617 \fsm_state$503$next - sync posedge \clk - update \fsm_state$503 $0\fsm_state$503[2:0]$5617 - end - attribute \src "libresoc.v:128097.3-128098.41" - process $proc$libresoc.v:128097$5618 - assign { } { } - assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next - sync posedge \clk - update \dmi0__addr_i $0\dmi0__addr_i[3:0] - end - attribute \src "libresoc.v:128099.3-128100.51" - process $proc$libresoc.v:128099$5619 - assign { } { } - assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next - sync posedge \clk - update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] - end - attribute \src "libresoc.v:128101.3-128102.45" - process $proc$libresoc.v:128101$5620 - assign { } { } - assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next - sync posedge \clk - update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] - end - attribute \src "libresoc.v:128103.3-128104.35" - process $proc$libresoc.v:128103$5621 - assign { } { } - assign $0\fsm_state[2:0] \fsm_state$next - sync posedge \clk - update \fsm_state $0\fsm_state[2:0] - end - attribute \src "libresoc.v:128105.3-128106.41" - process $proc$libresoc.v:128105$5622 - assign { } { } - assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next - sync posedge \clk - update \jtag_wb__adr $0\jtag_wb__adr[28:0] - end - attribute \src "libresoc.v:128107.3-128108.31" - process $proc$libresoc.v:128107$5623 - assign { } { } - assign $0\sr5_reg[1:0] \sr5_reg$next - sync posedge \posjtag_clk - update \sr5_reg $0\sr5_reg[1:0] - end - attribute \src "libresoc.v:128109.3-128110.31" - process $proc$libresoc.v:128109$5624 - assign { } { } - assign $0\sr5__oe[0:0] \sr5__oe$next - sync posedge \clk - update \sr5__oe $0\sr5__oe[0:0] - end - attribute \src "libresoc.v:128111.3-128112.57" - process $proc$libresoc.v:128111$5625 - assign { } { } - assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next - sync posedge \clk - update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] - end - attribute \src "libresoc.v:128113.3-128114.47" - process $proc$libresoc.v:128113$5626 - assign { } { } - assign $0\sr5_update_core[0:0] \sr5_update_core$next - sync posedge \clk - update \sr5_update_core $0\sr5_update_core[0:0] - end - attribute \src "libresoc.v:128115.3-128116.47" - process $proc$libresoc.v:128115$5627 - assign { } { } - assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next - sync posedge \posjtag_clk - update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] - end - attribute \src "libresoc.v:128117.3-128118.47" - process $proc$libresoc.v:128117$5628 - assign { } { } - assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next - sync posedge \clk - update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] - end - attribute \src "libresoc.v:128119.3-128120.73" - process $proc$libresoc.v:128119$5629 - assign { } { } - assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next - sync posedge \clk - update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:128121.3-128122.63" - process $proc$libresoc.v:128121$5630 - assign { } { } - assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next - sync posedge \clk - update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] - end - attribute \src "libresoc.v:128123.3-128124.47" - process $proc$libresoc.v:128123$5631 - assign { } { } - assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next - sync posedge \posjtag_clk - update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] - end - attribute \src "libresoc.v:128125.3-128126.47" - process $proc$libresoc.v:128125$5632 - assign { } { } - assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next - sync posedge \clk - update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] - end - attribute \src "libresoc.v:128127.3-128128.73" - process $proc$libresoc.v:128127$5633 - assign { } { } - assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next - sync posedge \clk - update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:128129.3-128130.63" - process $proc$libresoc.v:128129$5634 - assign { } { } - assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next - sync posedge \clk - update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:128131.3-128132.53" - process $proc$libresoc.v:128131$5635 - assign { } { } - assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] - end - attribute \src "libresoc.v:128133.3-128134.53" - process $proc$libresoc.v:128133$5636 - assign { } { } - assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next - sync posedge \clk - update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] - end - attribute \src "libresoc.v:128135.3-128136.79" - process $proc$libresoc.v:128135$5637 - assign { } { } - assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next - sync posedge \clk - update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] - end - attribute \src "libresoc.v:128137.3-128138.69" - process $proc$libresoc.v:128137$5638 - assign { } { } - assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next - sync posedge \clk - update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] - end - attribute \src "libresoc.v:128139.3-128140.53" - process $proc$libresoc.v:128139$5639 - assign { } { } - assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next - sync posedge \posjtag_clk - update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] - end - attribute \src "libresoc.v:128141.3-128142.53" - process $proc$libresoc.v:128141$5640 - assign { } { } - assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next - sync posedge \clk - update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] - end - attribute \src "libresoc.v:128143.3-128144.79" - process $proc$libresoc.v:128143$5641 - assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next - sync posedge \clk - update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] - end - attribute \src "libresoc.v:128145.3-128146.69" - process $proc$libresoc.v:128145$5642 - assign { } { } - assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next - sync posedge \clk - update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] - end - attribute \src "libresoc.v:128147.3-128148.31" - process $proc$libresoc.v:128147$5643 - assign { } { } - assign $0\sr0_reg[2:0] \sr0_reg$next - sync posedge \posjtag_clk - update \sr0_reg $0\sr0_reg[2:0] - end - attribute \src "libresoc.v:128149.3-128150.31" - process $proc$libresoc.v:128149$5644 - assign { } { } - assign $0\sr0__oe[0:0] \sr0__oe$next - sync posedge \clk - update \sr0__oe $0\sr0__oe[0:0] - end - attribute \src "libresoc.v:128151.3-128152.57" - process $proc$libresoc.v:128151$5645 - assign { } { } - assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next - sync posedge \clk - update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] - end - attribute \src "libresoc.v:128153.3-128154.47" - process $proc$libresoc.v:128153$5646 - assign { } { } - assign $0\sr0_update_core[0:0] \sr0_update_core$next - sync posedge \clk - update \sr0_update_core $0\sr0_update_core[0:0] - end - attribute \src "libresoc.v:128155.3-128156.27" - process $proc$libresoc.v:128155$5647 - assign { } { } - assign $0\io_bd[153:0] \io_bd$next - sync negedge \negjtag_clk - update \io_bd $0\io_bd[153:0] - end - attribute \src "libresoc.v:128157.3-128158.27" - process $proc$libresoc.v:128157$5648 - assign { } { } - assign $0\io_sr[153:0] \io_sr$next - sync posedge \posjtag_clk - update \io_sr $0\io_sr[153:0] - end - attribute \src "libresoc.v:128194.3-128209.6" - process $proc$libresoc.v:128194$5649 - assign { } { } - assign { } { } - assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:128195.5-128195.29" - switch \initial - attribute \src "libresoc.v:128195.9-128195.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" - switch { \$369 \_idblock_select_id \_fsm_isir } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\TAP_tdo[0:0] \_irblock_tdo - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [153] - case - assign $1\TAP_tdo[0:0] 1'0 - end - sync always - update \TAP_tdo $0\TAP_tdo[0:0] - end - attribute \src "libresoc.v:128210.3-128218.6" - process $proc$libresoc.v:128210$5650 - assign { } { } - assign { } { } - assign $0\sr0_update_core$next[0:0]$5651 $1\sr0_update_core$next[0:0]$5652 - attribute \src "libresoc.v:128211.5-128211.29" - switch \initial - attribute \src "libresoc.v:128211.9-128211.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0_update_core$next[0:0]$5652 1'0 - case - assign $1\sr0_update_core$next[0:0]$5652 \sr0_update - end - sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5651 - end - attribute \src "libresoc.v:128219.3-128227.6" - process $proc$libresoc.v:128219$5653 - assign { } { } - assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5654 $1\sr0_update_core_prev$next[0:0]$5655 - attribute \src "libresoc.v:128220.5-128220.29" - switch \initial - attribute \src "libresoc.v:128220.9-128220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5655 1'0 - case - assign $1\sr0_update_core_prev$next[0:0]$5655 \sr0_update_core - end - sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5654 - end - attribute \src "libresoc.v:128228.3-128244.6" - process $proc$libresoc.v:128228$5656 - assign { } { } - assign { } { } - assign $0\sr0__oe$next[0:0]$5657 $2\sr0__oe$next[0:0]$5659 - attribute \src "libresoc.v:128229.5-128229.29" - switch \initial - attribute \src "libresoc.v:128229.9-128229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$387 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0__oe$next[0:0]$5658 \sr0_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\sr0__oe$next[0:0]$5658 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr0__oe$next[0:0]$5659 1'0 - case - assign $2\sr0__oe$next[0:0]$5659 $1\sr0__oe$next[0:0]$5658 - end - sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5657 - end - attribute \src "libresoc.v:128245.3-128265.6" - process $proc$libresoc.v:128245$5660 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr0_reg$next[2:0]$5661 $3\sr0_reg$next[2:0]$5664 - attribute \src "libresoc.v:128246.5-128246.29" - switch \initial - attribute \src "libresoc.v:128246.9-128246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \sr0_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr0_reg$next[2:0]$5662 { \TAP_bus__tdi \sr0_reg [2:1] } - case - assign $1\sr0_reg$next[2:0]$5662 \sr0_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \sr0_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr0_reg$next[2:0]$5663 \sr0__i - case - assign $2\sr0_reg$next[2:0]$5663 $1\sr0_reg$next[2:0]$5662 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\sr0_reg$next[2:0]$5664 3'000 - case - assign $3\sr0_reg$next[2:0]$5664 $2\sr0_reg$next[2:0]$5663 - end - sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5661 - end - attribute \src "libresoc.v:128266.3-128274.6" - process $proc$libresoc.v:128266$5665 - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5666 $1\jtag_wb_addrsr_update_core$next[0:0]$5667 - attribute \src "libresoc.v:128267.5-128267.29" - switch \initial - attribute \src "libresoc.v:128267.9-128267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5667 1'0 - case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5667 \jtag_wb_addrsr_update - end - sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5666 - end - attribute \src "libresoc.v:128275.3-128283.6" - process $proc$libresoc.v:128275$5668 - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5669 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 - attribute \src "libresoc.v:128276.5-128276.29" - switch \initial - attribute \src "libresoc.v:128276.9-128276.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 1'0 - case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5670 \jtag_wb_addrsr_update_core - end - sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5669 - end - attribute \src "libresoc.v:128284.3-128300.6" - process $proc$libresoc.v:128284$5671 - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5672 $2\jtag_wb_addrsr__oe$next[0:0]$5674 - attribute \src "libresoc.v:128285.5-128285.29" - switch \initial - attribute \src "libresoc.v:128285.9-128285.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$405 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5673 \jtag_wb_addrsr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5673 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$5674 1'0 - case - assign $2\jtag_wb_addrsr__oe$next[0:0]$5674 $1\jtag_wb_addrsr__oe$next[0:0]$5673 - end - sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5672 - end - attribute \src "libresoc.v:128301.3-128321.6" - process $proc$libresoc.v:128301$5675 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$5676 $3\jtag_wb_addrsr_reg$next[28:0]$5679 - attribute \src "libresoc.v:128302.5-128302.29" - switch \initial - attribute \src "libresoc.v:128302.9-128302.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \jtag_wb_addrsr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$5677 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } - case - assign $1\jtag_wb_addrsr_reg$next[28:0]$5677 \jtag_wb_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \jtag_wb_addrsr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$5678 \jtag_wb_addrsr__i - case - assign $2\jtag_wb_addrsr_reg$next[28:0]$5678 $1\jtag_wb_addrsr_reg$next[28:0]$5677 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$5679 29'00000000000000000000000000000 - case - assign $3\jtag_wb_addrsr_reg$next[28:0]$5679 $2\jtag_wb_addrsr_reg$next[28:0]$5678 - end - sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5676 - end - attribute \src "libresoc.v:128322.3-128330.6" - process $proc$libresoc.v:128322$5680 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$5681 $1\jtag_wb_datasr_update_core$next[0:0]$5682 - attribute \src "libresoc.v:128323.5-128323.29" - switch \initial - attribute \src "libresoc.v:128323.9-128323.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$5682 1'0 - case - assign $1\jtag_wb_datasr_update_core$next[0:0]$5682 \jtag_wb_datasr_update - end - sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5681 - end - attribute \src "libresoc.v:128331.3-128339.6" - process $proc$libresoc.v:128331$5683 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5684 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 - attribute \src "libresoc.v:128332.5-128332.29" - switch \initial - attribute \src "libresoc.v:128332.9-128332.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 1'0 - case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5685 \jtag_wb_datasr_update_core - end - sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5684 - end - attribute \src "libresoc.v:128340.3-128356.6" - process $proc$libresoc.v:128340$5686 - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$5687 $2\jtag_wb_datasr__oe$next[1:0]$5689 - attribute \src "libresoc.v:128341.5-128341.29" - switch \initial - attribute \src "libresoc.v:128341.9-128341.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$425 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5688 \jtag_wb_datasr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$5688 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$5689 2'00 - case - assign $2\jtag_wb_datasr__oe$next[1:0]$5689 $1\jtag_wb_datasr__oe$next[1:0]$5688 - end - sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5687 - end - attribute \src "libresoc.v:128357.3-128377.6" - process $proc$libresoc.v:128357$5690 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$5691 $3\jtag_wb_datasr_reg$next[63:0]$5694 - attribute \src "libresoc.v:128358.5-128358.29" - switch \initial - attribute \src "libresoc.v:128358.9-128358.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \jtag_wb_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$5692 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } - case - assign $1\jtag_wb_datasr_reg$next[63:0]$5692 \jtag_wb_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \jtag_wb_datasr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$5693 \jtag_wb_datasr__i - case - assign $2\jtag_wb_datasr_reg$next[63:0]$5693 $1\jtag_wb_datasr_reg$next[63:0]$5692 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$5694 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb_datasr_reg$next[63:0]$5694 $2\jtag_wb_datasr_reg$next[63:0]$5693 - end - sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$5691 - end - attribute \src "libresoc.v:128378.3-128386.6" - process $proc$libresoc.v:128378$5695 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$5696 $1\dmi0_addrsr_update_core$next[0:0]$5697 - attribute \src "libresoc.v:128379.5-128379.29" - switch \initial - attribute \src "libresoc.v:128379.9-128379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$5697 1'0 - case - assign $1\dmi0_addrsr_update_core$next[0:0]$5697 \dmi0_addrsr_update - end - sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$5696 - end - attribute \src "libresoc.v:128387.3-128395.6" - process $proc$libresoc.v:128387$5698 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$5699 $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 - attribute \src "libresoc.v:128388.5-128388.29" - switch \initial - attribute \src "libresoc.v:128388.9-128388.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 1'0 - case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$5700 \dmi0_addrsr_update_core - end - sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$5699 - end - attribute \src "libresoc.v:128396.3-128412.6" - process $proc$libresoc.v:128396$5701 - assign { } { } - assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$5702 $2\dmi0_addrsr__oe$next[0:0]$5704 - attribute \src "libresoc.v:128397.5-128397.29" - switch \initial - attribute \src "libresoc.v:128397.9-128397.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$443 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5703 \dmi0_addrsr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$5703 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$5704 1'0 - case - assign $2\dmi0_addrsr__oe$next[0:0]$5704 $1\dmi0_addrsr__oe$next[0:0]$5703 - end - sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$5702 - end - attribute \src "libresoc.v:128413.3-128433.6" - process $proc$libresoc.v:128413$5705 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$5706 $3\dmi0_addrsr_reg$next[7:0]$5709 - attribute \src "libresoc.v:128414.5-128414.29" - switch \initial - attribute \src "libresoc.v:128414.9-128414.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \dmi0_addrsr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$5707 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } - case - assign $1\dmi0_addrsr_reg$next[7:0]$5707 \dmi0_addrsr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \dmi0_addrsr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$5708 \dmi0_addrsr__i - case - assign $2\dmi0_addrsr_reg$next[7:0]$5708 $1\dmi0_addrsr_reg$next[7:0]$5707 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$5709 8'00000000 - case - assign $3\dmi0_addrsr_reg$next[7:0]$5709 $2\dmi0_addrsr_reg$next[7:0]$5708 - end - sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$5706 - end - attribute \src "libresoc.v:128434.3-128442.6" - process $proc$libresoc.v:128434$5710 - assign { } { } - assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$5711 $1\dmi0_datasr_update_core$next[0:0]$5712 - attribute \src "libresoc.v:128435.5-128435.29" - switch \initial - attribute \src "libresoc.v:128435.9-128435.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$5712 1'0 - case - assign $1\dmi0_datasr_update_core$next[0:0]$5712 \dmi0_datasr_update - end - sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$5711 - end - attribute \src "libresoc.v:128443.3-128451.6" - process $proc$libresoc.v:128443$5713 - assign { } { } - assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$5714 $1\dmi0_datasr_update_core_prev$next[0:0]$5715 - attribute \src "libresoc.v:128444.5-128444.29" - switch \initial - attribute \src "libresoc.v:128444.9-128444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5715 1'0 - case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$5715 \dmi0_datasr_update_core - end - sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$5714 - end - attribute \src "libresoc.v:128452.3-128468.6" - process $proc$libresoc.v:128452$5716 - assign { } { } - assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$5717 $2\dmi0_datasr__oe$next[1:0]$5719 - attribute \src "libresoc.v:128453.5-128453.29" - switch \initial - attribute \src "libresoc.v:128453.9-128453.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$463 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5718 \dmi0_datasr_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$5718 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$5719 2'00 - case - assign $2\dmi0_datasr__oe$next[1:0]$5719 $1\dmi0_datasr__oe$next[1:0]$5718 - end - sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$5717 - end - attribute \src "libresoc.v:128469.3-128489.6" - process $proc$libresoc.v:128469$5720 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$5721 $3\dmi0_datasr_reg$next[63:0]$5724 - attribute \src "libresoc.v:128470.5-128470.29" - switch \initial - attribute \src "libresoc.v:128470.9-128470.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \dmi0_datasr_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$5722 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } - case - assign $1\dmi0_datasr_reg$next[63:0]$5722 \dmi0_datasr_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \dmi0_datasr_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$5723 \dmi0_datasr__i - case - assign $2\dmi0_datasr_reg$next[63:0]$5723 $1\dmi0_datasr_reg$next[63:0]$5722 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$5724 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0_datasr_reg$next[63:0]$5724 $2\dmi0_datasr_reg$next[63:0]$5723 - end - sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$5721 - end - attribute \src "libresoc.v:128490.3-128498.6" - process $proc$libresoc.v:128490$5725 - assign { } { } - assign { } { } - assign $0\sr5_update_core$next[0:0]$5726 $1\sr5_update_core$next[0:0]$5727 - attribute \src "libresoc.v:128491.5-128491.29" - switch \initial - attribute \src "libresoc.v:128491.9-128491.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_update_core$next[0:0]$5727 1'0 - case - assign $1\sr5_update_core$next[0:0]$5727 \sr5_update - end - sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$5726 - end - attribute \src "libresoc.v:128499.3-128507.6" - process $proc$libresoc.v:128499$5728 - assign { } { } - assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$5729 $1\sr5_update_core_prev$next[0:0]$5730 - attribute \src "libresoc.v:128500.5-128500.29" - switch \initial - attribute \src "libresoc.v:128500.9-128500.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$5730 1'0 - case - assign $1\sr5_update_core_prev$next[0:0]$5730 \sr5_update_core - end - sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$5729 - end - attribute \src "libresoc.v:128508.3-128524.6" - process $proc$libresoc.v:128508$5731 - assign { } { } - assign { } { } - assign $0\sr5__oe$next[0:0]$5732 $2\sr5__oe$next[0:0]$5734 - attribute \src "libresoc.v:128509.5-128509.29" - switch \initial - attribute \src "libresoc.v:128509.9-128509.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$481 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5__oe$next[0:0]$5733 \sr5_isir - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\sr5__oe$next[0:0]$5733 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr5__oe$next[0:0]$5734 1'0 - case - assign $2\sr5__oe$next[0:0]$5734 $1\sr5__oe$next[0:0]$5733 - end - sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$5732 - end - attribute \src "libresoc.v:128525.3-128545.6" - process $proc$libresoc.v:128525$5735 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr5_reg$next[1:0]$5736 $3\sr5_reg$next[1:0]$5739 - attribute \src "libresoc.v:128526.5-128526.29" - switch \initial - attribute \src "libresoc.v:128526.9-128526.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" - switch \sr5_shift - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5_reg$next[1:0]$5737 { \TAP_bus__tdi \sr5_reg [1] } - case - assign $1\sr5_reg$next[1:0]$5737 \sr5_reg - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" - switch \sr5_capture - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\sr5_reg$next[1:0]$5738 \sr5__i - case - assign $2\sr5_reg$next[1:0]$5738 $1\sr5_reg$next[1:0]$5737 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\sr5_reg$next[1:0]$5739 2'00 - case - assign $3\sr5_reg$next[1:0]$5739 $2\sr5_reg$next[1:0]$5738 - end - sync always - update \sr5_reg$next $0\sr5_reg$next[1:0]$5736 - end - attribute \src "libresoc.v:128546.3-128572.6" - process $proc$libresoc.v:128546$5740 - assign { } { } - assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:128547.5-128547.29" - switch \initial - attribute \src "libresoc.v:128547.9-128547.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" - switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } - attribute \src "libresoc.v:0.0-0.0" - case 6'-----1 - assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'----1- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'---1-- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'--1--- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'-1---- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case 6'1----- - assign { } { } - assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\TAP_bus__tdo[0:0] \TAP_tdo - end - sync always - update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] - end - attribute \src "libresoc.v:128573.3-128605.6" - process $proc$libresoc.v:128573$5741 - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb__adr$next[28:0]$5742 $4\jtag_wb__adr$next[28:0]$5746 - attribute \src "libresoc.v:128574.5-128574.29" - switch \initial - attribute \src "libresoc.v:128574.9-128574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5743 $2\jtag_wb__adr$next[28:0]$5744 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5744 \jtag_wb_addrsr__o - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\jtag_wb__adr$next[28:0]$5744 \$495 [28:0] - case - assign $2\jtag_wb__adr$next[28:0]$5744 \jtag_wb__adr - end - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\jtag_wb__adr$next[28:0]$5743 $3\jtag_wb__adr$next[28:0]$5745 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb__adr$next[28:0]$5745 \$498 [28:0] - case - assign $3\jtag_wb__adr$next[28:0]$5745 \jtag_wb__adr - end - case - assign $1\jtag_wb__adr$next[28:0]$5743 \jtag_wb__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\jtag_wb__adr$next[28:0]$5746 29'00000000000000000000000000000 - case - assign $4\jtag_wb__adr$next[28:0]$5746 $1\jtag_wb__adr$next[28:0]$5743 - end - sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$5742 - end - attribute \src "libresoc.v:128606.3-128658.6" - process $proc$libresoc.v:128606$5747 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[2:0]$5748 $5\fsm_state$next[2:0]$5753 - attribute \src "libresoc.v:128607.5-128607.29" - switch \initial - attribute \src "libresoc.v:128607.9-128607.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$next[2:0]$5749 $2\fsm_state$next[2:0]$5750 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$next[2:0]$5750 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$next[2:0]$5750 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$next[2:0]$5750 3'010 - case - assign $2\fsm_state$next[2:0]$5750 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$next[2:0]$5749 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$next[2:0]$5749 $3\fsm_state$next[2:0]$5751 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$next[2:0]$5751 3'000 - case - assign $3\fsm_state$next[2:0]$5751 \fsm_state - end - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\fsm_state$next[2:0]$5749 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\fsm_state$next[2:0]$5749 $4\fsm_state$next[2:0]$5752 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[2:0]$5752 3'001 - case - assign $4\fsm_state$next[2:0]$5752 \fsm_state - end - case - assign $1\fsm_state$next[2:0]$5749 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$next[2:0]$5753 3'000 - case - assign $5\fsm_state$next[2:0]$5753 $1\fsm_state$next[2:0]$5749 - end - sync always - update \fsm_state$next $0\fsm_state$next[2:0]$5748 - end - attribute \src "libresoc.v:128659.3-128685.6" - process $proc$libresoc.v:128659$5754 - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$5755 $3\jtag_wb__dat_w$next[63:0]$5758 - attribute \src "libresoc.v:128660.5-128660.29" - switch \initial - attribute \src "libresoc.v:128660.9-128660.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$5756 $2\jtag_wb__dat_w$next[63:0]$5757 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" - switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb_datasr__o - case - assign $2\jtag_wb__dat_w$next[63:0]$5757 \jtag_wb__dat_w - end - case - assign $1\jtag_wb__dat_w$next[63:0]$5756 \jtag_wb__dat_w - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$5758 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb__dat_w$next[63:0]$5758 $1\jtag_wb__dat_w$next[63:0]$5756 - end - sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$5755 - end - attribute \src "libresoc.v:128686.3-128706.6" - process $proc$libresoc.v:128686$5759 - assign { } { } - assign { } { } - assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$5760 $3\jtag_wb_datasr__i$next[63:0]$5763 - attribute \src "libresoc.v:128687.5-128687.29" - switch \initial - attribute \src "libresoc.v:128687.9-128687.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$5761 $2\jtag_wb_datasr__i$next[63:0]$5762 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" - switch \jtag_wb__ack - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$5762 \jtag_wb__dat_r - case - assign $2\jtag_wb_datasr__i$next[63:0]$5762 \jtag_wb_datasr__i - end - case - assign $1\jtag_wb_datasr__i$next[63:0]$5761 \jtag_wb_datasr__i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$5763 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\jtag_wb_datasr__i$next[63:0]$5763 $1\jtag_wb_datasr__i$next[63:0]$5761 - end - sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$5760 - end - attribute \src "libresoc.v:128707.3-128739.6" - process $proc$libresoc.v:128707$5764 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0__addr_i$next[3:0]$5765 $4\dmi0__addr_i$next[3:0]$5769 - attribute \src "libresoc.v:128708.5-128708.29" - switch \initial - attribute \src "libresoc.v:128708.9-128708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\dmi0__addr_i$next[3:0]$5766 $2\dmi0__addr_i$next[3:0]$5767 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\dmi0__addr_i$next[3:0]$5767 \dmi0_addrsr__o [3:0] - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\dmi0__addr_i$next[3:0]$5767 \$512 [3:0] - case - assign $2\dmi0__addr_i$next[3:0]$5767 \dmi0__addr_i - end - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\dmi0__addr_i$next[3:0]$5766 $3\dmi0__addr_i$next[3:0]$5768 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0__addr_i$next[3:0]$5768 \$515 [3:0] - case - assign $3\dmi0__addr_i$next[3:0]$5768 \dmi0__addr_i - end - case - assign $1\dmi0__addr_i$next[3:0]$5766 \dmi0__addr_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\dmi0__addr_i$next[3:0]$5769 4'0000 - case - assign $4\dmi0__addr_i$next[3:0]$5769 $1\dmi0__addr_i$next[3:0]$5766 - end - sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$5765 - end - attribute \src "libresoc.v:128740.3-128792.6" - process $proc$libresoc.v:128740$5770 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$503$next[2:0]$5771 $5\fsm_state$503$next[2:0]$5776 - attribute \src "libresoc.v:128741.5-128741.29" - switch \initial - attribute \src "libresoc.v:128741.9-128741.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\fsm_state$503$next[2:0]$5772 $2\fsm_state$503$next[2:0]$5773 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\fsm_state$503$next[2:0]$5773 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\fsm_state$503$next[2:0]$5773 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\fsm_state$503$next[2:0]$5773 3'010 - case - assign $2\fsm_state$503$next[2:0]$5773 \fsm_state$503 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'001 - assign { } { } - assign $1\fsm_state$503$next[2:0]$5772 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\fsm_state$503$next[2:0]$5772 $3\fsm_state$503$next[2:0]$5774 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fsm_state$503$next[2:0]$5774 3'000 - case - assign $3\fsm_state$503$next[2:0]$5774 \fsm_state$503 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'010 - assign { } { } - assign $1\fsm_state$503$next[2:0]$5772 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 3'100 - assign { } { } - assign $1\fsm_state$503$next[2:0]$5772 $4\fsm_state$503$next[2:0]$5775 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$503$next[2:0]$5775 3'001 - case - assign $4\fsm_state$503$next[2:0]$5775 \fsm_state$503 - end - case - assign $1\fsm_state$503$next[2:0]$5772 \fsm_state$503 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fsm_state$503$next[2:0]$5776 3'000 - case - assign $5\fsm_state$503$next[2:0]$5776 $1\fsm_state$503$next[2:0]$5772 - end - sync always - update \fsm_state$503$next $0\fsm_state$503$next[2:0]$5771 - end - attribute \src "libresoc.v:128793.3-128819.6" - process $proc$libresoc.v:128793$5777 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0__din$next[63:0]$5778 $3\dmi0__din$next[63:0]$5781 - attribute \src "libresoc.v:128794.5-128794.29" - switch \initial - attribute \src "libresoc.v:128794.9-128794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 - attribute \src "libresoc.v:0.0-0.0" - case 3'000 - assign { } { } - assign $1\dmi0__din$next[63:0]$5779 $2\dmi0__din$next[63:0]$5780 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" - switch { \dmi0_datasr__oe \dmi0_addrsr__oe } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $2\dmi0__din$next[63:0]$5780 \dmi0__din - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $2\dmi0__din$next[63:0]$5780 \dmi0__din - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\dmi0__din$next[63:0]$5780 \dmi0_datasr__o - case - assign $2\dmi0__din$next[63:0]$5780 \dmi0__din - end - case - assign $1\dmi0__din$next[63:0]$5779 \dmi0__din - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0__din$next[63:0]$5781 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0__din$next[63:0]$5781 $1\dmi0__din$next[63:0]$5779 - end - sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$5778 - end - attribute \src "libresoc.v:128820.3-128840.6" - process $proc$libresoc.v:128820$5782 - assign { } { } - assign { } { } - assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$5783 $3\dmi0_datasr__i$next[63:0]$5786 - attribute \src "libresoc.v:128821.5-128821.29" - switch \initial - attribute \src "libresoc.v:128821.9-128821.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$503 - attribute \src "libresoc.v:0.0-0.0" - case 3'011 - assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$5784 $2\dmi0_datasr__i$next[63:0]$5785 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" - switch \dmi0__ack_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$5785 \dmi0__dout - case - assign $2\dmi0_datasr__i$next[63:0]$5785 \dmi0_datasr__i - end - case - assign $1\dmi0_datasr__i$next[63:0]$5784 \dmi0_datasr__i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$5786 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dmi0_datasr__i$next[63:0]$5786 $1\dmi0_datasr__i$next[63:0]$5784 - end - sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$5783 - end - attribute \src "libresoc.v:128841.3-128859.6" - process $proc$libresoc.v:128841$5787 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\wb_dcache_en$next[0:0]$5788 $2\wb_dcache_en$next[0:0]$5792 - assign $0\wb_icache_en$next[0:0]$5789 $2\wb_icache_en$next[0:0]$5793 - attribute \src "libresoc.v:128842.5-128842.29" - switch \initial - attribute \src "libresoc.v:128842.9-128842.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" - switch \sr5__oe - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\wb_dcache_en$next[0:0]$5790 $1\wb_icache_en$next[0:0]$5791 } \sr5__o - case - assign $1\wb_dcache_en$next[0:0]$5790 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$5791 \wb_icache_en - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $2\wb_icache_en$next[0:0]$5793 1'1 - assign $2\wb_dcache_en$next[0:0]$5792 1'1 - case - assign $2\wb_dcache_en$next[0:0]$5792 $1\wb_dcache_en$next[0:0]$5790 - assign $2\wb_icache_en$next[0:0]$5793 $1\wb_icache_en$next[0:0]$5791 - end - sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$5788 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$5789 - end - attribute \src "libresoc.v:128860.3-128869.6" - process $proc$libresoc.v:128860$5794 - assign { } { } - assign { } { } - assign $0\sr5__i[1:0] $1\sr5__i[1:0] - attribute \src "libresoc.v:128861.5-128861.29" - switch \initial - attribute \src "libresoc.v:128861.9-128861.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" - switch \sr5__ie - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } - case - assign $1\sr5__i[1:0] 2'00 - end - sync always - update \sr5__i $0\sr5__i[1:0] - end - attribute \src "libresoc.v:128870.3-128887.6" - process $proc$libresoc.v:128870$5795 - assign { } { } - assign { } { } - assign { } { } - assign $0\io_sr$next[153:0]$5796 $2\io_sr$next[153:0]$5798 - attribute \src "libresoc.v:128871.5-128871.29" - switch \initial - attribute \src "libresoc.v:128871.9-128871.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" - switch { \io_update \io_shift \io_capture } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\io_sr$next[153:0]$5797 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $1\io_sr$next[153:0]$5797 { \io_sr [152:0] \TAP_bus__tdi } - case - assign $1\io_sr$next[153:0]$5797 \io_sr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \posjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\io_sr$next[153:0]$5798 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_sr$next[153:0]$5798 $1\io_sr$next[153:0]$5797 - end - sync always - update \io_sr$next $0\io_sr$next[153:0]$5796 - end - attribute \src "libresoc.v:128888.3-128908.6" - process $proc$libresoc.v:128888$5799 - assign { } { } - assign { } { } - assign { } { } - assign $0\io_bd$next[153:0]$5800 $2\io_bd$next[153:0]$5802 - attribute \src "libresoc.v:128889.5-128889.29" - switch \initial - attribute \src "libresoc.v:128889.9-128889.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" - switch { \io_update \io_shift \io_capture } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign $1\io_bd$next[153:0]$5801 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign $1\io_bd$next[153:0]$5801 \io_bd - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $1\io_bd$next[153:0]$5801 \io_sr - case - assign $1\io_bd$next[153:0]$5801 \io_bd - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \negjtag_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\io_bd$next[153:0]$5802 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[153:0]$5802 $1\io_bd$next[153:0]$5801 - end - sync always - update \io_bd$next $0\io_bd$next[153:0]$5800 - end - connect \$9 $eq$libresoc.v:127831$5355_Y - connect \$99 $ternary$libresoc.v:127832$5356_Y - connect \$101 $ternary$libresoc.v:127833$5357_Y - connect \$103 $ternary$libresoc.v:127834$5358_Y - connect \$105 $ternary$libresoc.v:127835$5359_Y - connect \$107 $ternary$libresoc.v:127836$5360_Y - connect \$109 $ternary$libresoc.v:127837$5361_Y - connect \$111 $ternary$libresoc.v:127838$5362_Y - connect \$113 $ternary$libresoc.v:127839$5363_Y - connect \$115 $ternary$libresoc.v:127840$5364_Y - connect \$117 $ternary$libresoc.v:127841$5365_Y - connect \$11 $eq$libresoc.v:127842$5366_Y - connect \$119 $ternary$libresoc.v:127843$5367_Y - connect \$121 $ternary$libresoc.v:127844$5368_Y - connect \$123 $ternary$libresoc.v:127845$5369_Y - connect \$125 $ternary$libresoc.v:127846$5370_Y - connect \$127 $ternary$libresoc.v:127847$5371_Y - connect \$129 $ternary$libresoc.v:127848$5372_Y - connect \$131 $ternary$libresoc.v:127849$5373_Y - connect \$133 $ternary$libresoc.v:127850$5374_Y - connect \$135 $ternary$libresoc.v:127851$5375_Y - connect \$137 $ternary$libresoc.v:127852$5376_Y - connect \$13 $eq$libresoc.v:127853$5377_Y - connect \$139 $ternary$libresoc.v:127854$5378_Y - connect \$141 $ternary$libresoc.v:127855$5379_Y - connect \$143 $ternary$libresoc.v:127856$5380_Y - connect \$145 $ternary$libresoc.v:127857$5381_Y - connect \$147 $ternary$libresoc.v:127858$5382_Y - connect \$149 $ternary$libresoc.v:127859$5383_Y - connect \$151 $ternary$libresoc.v:127860$5384_Y - connect \$153 $ternary$libresoc.v:127861$5385_Y - connect \$155 $ternary$libresoc.v:127862$5386_Y - connect \$157 $ternary$libresoc.v:127863$5387_Y - connect \$15 $or$libresoc.v:127864$5388_Y - connect \$159 $ternary$libresoc.v:127865$5389_Y - connect \$161 $ternary$libresoc.v:127866$5390_Y - connect \$163 $ternary$libresoc.v:127867$5391_Y - connect \$165 $ternary$libresoc.v:127868$5392_Y - connect \$167 $ternary$libresoc.v:127869$5393_Y - connect \$169 $ternary$libresoc.v:127870$5394_Y - connect \$171 $ternary$libresoc.v:127871$5395_Y - connect \$173 $ternary$libresoc.v:127872$5396_Y - connect \$175 $ternary$libresoc.v:127873$5397_Y - connect \$177 $ternary$libresoc.v:127874$5398_Y - connect \$17 $and$libresoc.v:127875$5399_Y - connect \$179 $ternary$libresoc.v:127876$5400_Y - connect \$181 $ternary$libresoc.v:127877$5401_Y - connect \$183 $ternary$libresoc.v:127878$5402_Y - connect \$185 $ternary$libresoc.v:127879$5403_Y - connect \$187 $ternary$libresoc.v:127880$5404_Y - connect \$189 $ternary$libresoc.v:127881$5405_Y - connect \$191 $ternary$libresoc.v:127882$5406_Y - connect \$193 $ternary$libresoc.v:127883$5407_Y - connect \$195 $ternary$libresoc.v:127884$5408_Y - connect \$197 $ternary$libresoc.v:127885$5409_Y - connect \$1 $eq$libresoc.v:127886$5410_Y - connect \$19 $eq$libresoc.v:127887$5411_Y - connect \$199 $ternary$libresoc.v:127888$5412_Y - connect \$201 $ternary$libresoc.v:127889$5413_Y - connect \$203 $ternary$libresoc.v:127890$5414_Y - connect \$205 $ternary$libresoc.v:127891$5415_Y - connect \$207 $ternary$libresoc.v:127892$5416_Y - connect \$209 $ternary$libresoc.v:127893$5417_Y - connect \$211 $ternary$libresoc.v:127894$5418_Y - connect \$213 $ternary$libresoc.v:127895$5419_Y - connect \$215 $ternary$libresoc.v:127896$5420_Y - connect \$217 $ternary$libresoc.v:127897$5421_Y - connect \$21 $eq$libresoc.v:127898$5422_Y - connect \$219 $ternary$libresoc.v:127899$5423_Y - connect \$221 $ternary$libresoc.v:127900$5424_Y - connect \$223 $ternary$libresoc.v:127901$5425_Y - connect \$225 $ternary$libresoc.v:127902$5426_Y - connect \$227 $ternary$libresoc.v:127903$5427_Y - connect \$229 $ternary$libresoc.v:127904$5428_Y - connect \$231 $ternary$libresoc.v:127905$5429_Y - connect \$233 $ternary$libresoc.v:127906$5430_Y - connect \$235 $ternary$libresoc.v:127907$5431_Y - connect \$237 $ternary$libresoc.v:127908$5432_Y - connect \$23 $or$libresoc.v:127909$5433_Y - connect \$239 $ternary$libresoc.v:127910$5434_Y - connect \$241 $ternary$libresoc.v:127911$5435_Y - connect \$243 $ternary$libresoc.v:127912$5436_Y - connect \$245 $ternary$libresoc.v:127913$5437_Y - connect \$247 $ternary$libresoc.v:127914$5438_Y - connect \$249 $ternary$libresoc.v:127915$5439_Y - connect \$251 $ternary$libresoc.v:127916$5440_Y - connect \$253 $ternary$libresoc.v:127917$5441_Y - connect \$255 $ternary$libresoc.v:127918$5442_Y - connect \$257 $ternary$libresoc.v:127919$5443_Y - connect \$25 $eq$libresoc.v:127920$5444_Y - connect \$259 $ternary$libresoc.v:127921$5445_Y - connect \$261 $ternary$libresoc.v:127922$5446_Y - connect \$263 $ternary$libresoc.v:127923$5447_Y - connect \$265 $ternary$libresoc.v:127924$5448_Y - connect \$267 $ternary$libresoc.v:127925$5449_Y - connect \$269 $ternary$libresoc.v:127926$5450_Y - connect \$271 $ternary$libresoc.v:127927$5451_Y - connect \$273 $ternary$libresoc.v:127928$5452_Y - connect \$275 $ternary$libresoc.v:127929$5453_Y - connect \$277 $ternary$libresoc.v:127930$5454_Y - connect \$27 $or$libresoc.v:127931$5455_Y - connect \$279 $ternary$libresoc.v:127932$5456_Y - connect \$281 $ternary$libresoc.v:127933$5457_Y - connect \$283 $ternary$libresoc.v:127934$5458_Y - connect \$285 $ternary$libresoc.v:127935$5459_Y - connect \$287 $ternary$libresoc.v:127936$5460_Y - connect \$289 $ternary$libresoc.v:127937$5461_Y - connect \$291 $ternary$libresoc.v:127938$5462_Y - connect \$293 $ternary$libresoc.v:127939$5463_Y - connect \$295 $ternary$libresoc.v:127940$5464_Y - connect \$297 $ternary$libresoc.v:127941$5465_Y - connect \$29 $and$libresoc.v:127942$5466_Y - connect \$299 $ternary$libresoc.v:127943$5467_Y - connect \$301 $ternary$libresoc.v:127944$5468_Y - connect \$303 $ternary$libresoc.v:127945$5469_Y - connect \$305 $ternary$libresoc.v:127946$5470_Y - connect \$307 $ternary$libresoc.v:127947$5471_Y - connect \$309 $ternary$libresoc.v:127948$5472_Y - connect \$311 $ternary$libresoc.v:127949$5473_Y - connect \$313 $ternary$libresoc.v:127950$5474_Y - connect \$315 $ternary$libresoc.v:127951$5475_Y - connect \$317 $ternary$libresoc.v:127952$5476_Y - connect \$31 $and$libresoc.v:127953$5477_Y - connect \$319 $ternary$libresoc.v:127954$5478_Y - connect \$321 $ternary$libresoc.v:127955$5479_Y - connect \$323 $ternary$libresoc.v:127956$5480_Y - connect \$325 $ternary$libresoc.v:127957$5481_Y - connect \$327 $ternary$libresoc.v:127958$5482_Y - connect \$329 $ternary$libresoc.v:127959$5483_Y - connect \$331 $ternary$libresoc.v:127960$5484_Y - connect \$333 $ternary$libresoc.v:127961$5485_Y - connect \$335 $ternary$libresoc.v:127962$5486_Y - connect \$337 $ternary$libresoc.v:127963$5487_Y - connect \$33 $eq$libresoc.v:127964$5488_Y - connect \$339 $ternary$libresoc.v:127965$5489_Y - connect \$341 $ternary$libresoc.v:127966$5490_Y - connect \$343 $ternary$libresoc.v:127967$5491_Y - connect \$345 $ternary$libresoc.v:127968$5492_Y - connect \$347 $ternary$libresoc.v:127969$5493_Y - connect \$349 $ternary$libresoc.v:127970$5494_Y - connect \$351 $ternary$libresoc.v:127971$5495_Y - connect \$353 $ternary$libresoc.v:127972$5496_Y - connect \$355 $ternary$libresoc.v:127973$5497_Y - connect \$357 $ternary$libresoc.v:127974$5498_Y - connect \$35 $eq$libresoc.v:127975$5499_Y - connect \$359 $eq$libresoc.v:127976$5500_Y - connect \$361 $eq$libresoc.v:127977$5501_Y - connect \$363 $or$libresoc.v:127978$5502_Y - connect \$365 $eq$libresoc.v:127979$5503_Y - connect \$367 $or$libresoc.v:127980$5504_Y - connect \$369 $and$libresoc.v:127981$5505_Y - connect \$371 $eq$libresoc.v:127982$5506_Y - connect \$373 $ne$libresoc.v:127983$5507_Y - connect \$375 $and$libresoc.v:127984$5508_Y - connect \$377 $ne$libresoc.v:127985$5509_Y - connect \$37 $or$libresoc.v:127986$5510_Y - connect \$379 $and$libresoc.v:127987$5511_Y - connect \$381 $ne$libresoc.v:127988$5512_Y - connect \$383 $and$libresoc.v:127989$5513_Y - connect \$385 $not$libresoc.v:127990$5514_Y - connect \$387 $and$libresoc.v:127991$5515_Y - connect \$389 $eq$libresoc.v:127992$5516_Y - connect \$391 $ne$libresoc.v:127993$5517_Y - connect \$393 $and$libresoc.v:127994$5518_Y - connect \$395 $ne$libresoc.v:127995$5519_Y - connect \$397 $and$libresoc.v:127996$5520_Y - connect \$3 $eq$libresoc.v:127997$5521_Y - connect \$39 $eq$libresoc.v:127998$5522_Y - connect \$399 $ne$libresoc.v:127999$5523_Y - connect \$401 $and$libresoc.v:128000$5524_Y - connect \$403 $not$libresoc.v:128001$5525_Y - connect \$405 $and$libresoc.v:128002$5526_Y - connect \$407 $eq$libresoc.v:128003$5527_Y - connect \$409 $eq$libresoc.v:128004$5528_Y - connect \$411 $ne$libresoc.v:128005$5529_Y - connect \$413 $and$libresoc.v:128006$5530_Y - connect \$415 $ne$libresoc.v:128007$5531_Y - connect \$417 $and$libresoc.v:128008$5532_Y - connect \$41 $or$libresoc.v:128009$5533_Y - connect \$419 $ne$libresoc.v:128010$5534_Y - connect \$421 $and$libresoc.v:128011$5535_Y - connect \$423 $not$libresoc.v:128012$5536_Y - connect \$425 $and$libresoc.v:128013$5537_Y - connect \$427 $eq$libresoc.v:128014$5538_Y - connect \$429 $ne$libresoc.v:128015$5539_Y - connect \$431 $and$libresoc.v:128016$5540_Y - connect \$433 $ne$libresoc.v:128017$5541_Y - connect \$435 $and$libresoc.v:128018$5542_Y - connect \$437 $ne$libresoc.v:128019$5543_Y - connect \$43 $and$libresoc.v:128020$5544_Y - connect \$439 $and$libresoc.v:128021$5545_Y - connect \$441 $not$libresoc.v:128022$5546_Y - connect \$443 $and$libresoc.v:128023$5547_Y - connect \$445 $eq$libresoc.v:128024$5548_Y - connect \$447 $eq$libresoc.v:128025$5549_Y - connect \$449 $ne$libresoc.v:128026$5550_Y - connect \$451 $and$libresoc.v:128027$5551_Y - connect \$453 $ne$libresoc.v:128028$5552_Y - connect \$455 $and$libresoc.v:128029$5553_Y - connect \$457 $ne$libresoc.v:128030$5554_Y - connect \$45 $and$libresoc.v:128031$5555_Y - connect \$459 $and$libresoc.v:128032$5556_Y - connect \$461 $not$libresoc.v:128033$5557_Y - connect \$463 $and$libresoc.v:128034$5558_Y - connect \$465 $eq$libresoc.v:128035$5559_Y - connect \$467 $ne$libresoc.v:128036$5560_Y - connect \$469 $and$libresoc.v:128037$5561_Y - connect \$471 $ne$libresoc.v:128038$5562_Y - connect \$473 $and$libresoc.v:128039$5563_Y - connect \$475 $ne$libresoc.v:128040$5564_Y - connect \$477 $and$libresoc.v:128041$5565_Y - connect \$47 $eq$libresoc.v:128042$5566_Y - connect \$479 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$ternary$libresoc.v:128085$5610_Y - connect \$97 $ternary$libresoc.v:128086$5611_Y - connect \$495 \$496 - connect \$498 \$499 - connect \$512 \$513 - connect \$515 \$516 - connect \sr5__ie 1'0 - connect \sr0__i \sr0__o - connect \dmi0__we_i \$510 - connect \dmi0__req_i \$508 - connect \dmi0_addrsr__i \$501 - connect \jtag_wb__we \$493 - connect \jtag_wb__stb \$491 - connect \jtag_wb__cyc \$483 - connect \jtag_wb__sel 1'1 - connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \sr5_update \$477 - connect \sr5_shift \$473 - connect \sr5_capture \$469 - connect \sr5_isir \$465 - connect \sr5__o \sr5_reg - connect \dmi0_datasr_update \$459 - connect \dmi0_datasr_shift \$455 - connect \dmi0_datasr_capture \$451 - connect \dmi0_datasr_isir { \$447 \$445 } - connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$439 - connect \dmi0_addrsr_shift \$435 - connect \dmi0_addrsr_capture \$431 - connect \dmi0_addrsr_isir \$427 - connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$421 - connect \jtag_wb_datasr_shift \$417 - connect \jtag_wb_datasr_capture \$413 - connect \jtag_wb_datasr_isir { \$409 \$407 } - connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$401 - connect \jtag_wb_addrsr_shift \$397 - connect \jtag_wb_addrsr_capture \$393 - connect \jtag_wb_addrsr_isir \$389 - connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$383 - connect \sr0_shift \$379 - connect \sr0_capture \$375 - connect \sr0_isir \$371 - connect \sr0__o \sr0_reg - connect \sdr_dq_15__pad__oe \$357 - connect \sdr_dq_15__pad__o \$355 - connect \sdr_dq_15__core__i \$353 - connect \sdr_dq_14__pad__oe \$351 - connect \sdr_dq_14__pad__o \$349 - connect \sdr_dq_14__core__i \$347 - connect \sdr_dq_13__pad__oe \$345 - connect \sdr_dq_13__pad__o \$343 - connect \sdr_dq_13__core__i \$341 - connect \sdr_dq_12__pad__oe \$339 - connect \sdr_dq_12__pad__o \$337 - connect \sdr_dq_12__core__i \$335 - connect \sdr_dq_11__pad__oe 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\$275 - connect \sdr_a_5__pad__o \$273 - connect \sdr_a_4__pad__o \$271 - connect \sdr_a_3__pad__o \$269 - connect \sdr_a_2__pad__o \$267 - connect \sdr_a_1__pad__o \$265 - connect \sdr_a_0__pad__o \$263 - connect \sdr_dq_7__pad__oe \$261 - connect \sdr_dq_7__pad__o \$259 - connect \sdr_dq_7__core__i \$257 - connect \sdr_dq_6__pad__oe \$255 - connect \sdr_dq_6__pad__o \$253 - connect \sdr_dq_6__core__i \$251 - connect \sdr_dq_5__pad__oe \$249 - connect \sdr_dq_5__pad__o \$247 - connect \sdr_dq_5__core__i \$245 - connect \sdr_dq_4__pad__oe \$243 - connect \sdr_dq_4__pad__o \$241 - connect \sdr_dq_4__core__i \$239 - connect \sdr_dq_3__pad__oe \$237 - connect \sdr_dq_3__pad__o \$235 - connect \sdr_dq_3__core__i \$233 - connect \sdr_dq_2__pad__oe \$231 - connect \sdr_dq_2__pad__o \$229 - connect \sdr_dq_2__core__i \$227 - connect \sdr_dq_1__pad__oe \$225 - connect \sdr_dq_1__pad__o \$223 - connect \sdr_dq_1__core__i \$221 - connect \sdr_dq_0__pad__oe \$219 - connect \sdr_dq_0__pad__o \$217 - connect \sdr_dq_0__core__i \$215 - connect \sdr_dm_0__pad__o \$213 - connect \sd0_data3__pad__oe \$211 - connect \sd0_data3__pad__o \$209 - connect \sd0_data3__core__i \$207 - connect \sd0_data2__pad__oe \$205 - connect \sd0_data2__pad__o \$203 - connect \sd0_data2__core__i \$201 - connect \sd0_data1__pad__oe \$199 - connect \sd0_data1__pad__o \$197 - connect \sd0_data1__core__i \$195 - connect \sd0_data0__pad__oe \$193 - connect \sd0_data0__pad__o \$191 - connect \sd0_data0__core__i \$189 - connect \sd0_clk__pad__o \$187 - connect \sd0_cmd__pad__oe \$185 - connect \sd0_cmd__pad__o \$183 - connect \sd0_cmd__core__i \$181 - connect \pwm_1__pad__o \$179 - connect \pwm_0__pad__o \$177 - connect \mtwi_scl__pad__o \$175 - connect \mtwi_sda__pad__oe \$173 - connect \mtwi_sda__pad__o \$171 - connect \mtwi_sda__core__i \$169 - connect \mspi1_miso__core__i \$167 - connect \mspi1_mosi__pad__o \$165 - connect \mspi1_cs_n__pad__o \$163 - connect \mspi1_clk__pad__o \$161 - connect \mspi0_miso__core__i \$159 - connect \mspi0_mosi__pad__o \$157 - connect \mspi0_cs_n__pad__o \$155 - connect \mspi0_clk__pad__o \$153 - connect \gpio_s7__pad__oe \$151 - connect \gpio_s7__pad__o \$149 - connect \gpio_s7__core__i \$147 - connect \gpio_s6__pad__oe \$145 - connect \gpio_s6__pad__o \$143 - connect \gpio_s6__core__i \$141 - connect \gpio_s5__pad__oe \$139 - connect \gpio_s5__pad__o \$137 - connect \gpio_s5__core__i \$135 - connect \gpio_s4__pad__oe \$133 - connect \gpio_s4__pad__o \$131 - connect \gpio_s4__core__i \$129 - connect \gpio_s3__pad__oe \$127 - connect \gpio_s3__pad__o \$125 - connect \gpio_s3__core__i \$123 - connect \gpio_s2__pad__oe \$121 - connect \gpio_s2__pad__o \$119 - connect \gpio_s2__core__i \$117 - connect \gpio_s1__pad__oe \$115 - connect \gpio_s1__pad__o \$113 - connect \gpio_s1__core__i \$111 - connect \gpio_s0__pad__oe \$109 - connect \gpio_s0__pad__o \$107 - connect \gpio_s0__core__i \$105 - connect \gpio_e15__pad__oe \$103 - connect \gpio_e15__pad__o \$101 - connect \gpio_e15__core__i \$99 - connect \gpio_e14__pad__oe \$97 - connect \gpio_e14__pad__o \$95 - connect \gpio_e14__core__i \$93 - connect \gpio_e13__pad__oe \$91 - connect \gpio_e13__pad__o \$89 - connect \gpio_e13__core__i \$87 - connect \gpio_e12__pad__oe \$85 - connect \gpio_e12__pad__o \$83 - connect \gpio_e12__core__i \$81 - connect \gpio_e11__pad__oe \$79 - connect \gpio_e11__pad__o \$77 - connect \gpio_e11__core__i \$75 - connect \gpio_e10__pad__oe \$73 - connect \gpio_e10__pad__o \$71 - connect \gpio_e10__core__i \$69 - connect \gpio_e9__pad__oe \$67 - connect \gpio_e9__pad__o \$65 - connect \gpio_e9__core__i \$63 - connect \gpio_e8__pad__oe \$61 - connect \gpio_e8__pad__o \$59 - connect \gpio_e8__core__i \$57 - connect \eint_2__core__i \$55 - connect \eint_1__core__i \$53 - connect \eint_0__core__i \$51 - connect \io_bd2core \$49 - connect \io_bd2io \$47 - connect \io_update \$45 - connect \io_shift \$31 - connect \io_capture \$17 - connect \_idblock_id_bypass \$9 - connect \_idblock_select_id \$7 -end -attribute \src "libresoc.v:129118.1-129307.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0" -attribute \generator "nMigen" -module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 23 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 28 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 22 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 27 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 30 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 24 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 26 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 25 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 29 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 16 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 8 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 9 \ldst_port0_exc_$signal$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 10 \ldst_port0_exc_$signal$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 11 \ldst_port0_exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 12 \ldst_port0_exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 13 \ldst_port0_exc_$signal$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 14 \ldst_port0_exc_$signal$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 15 \ldst_port0_exc_$signal$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 17 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 18 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 48 \pimem_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pimem_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire \pimem_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire \pimem_ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 \pimem_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \pimem_ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire \pimem_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire \pimem_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pimem_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pimem_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \pimem_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \pimem_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" - wire width 64 \pimem_m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" - wire \pimem_m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 48 \pimem_x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" - wire \pimem_x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire \pimem_x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 8 \pimem_x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire width 64 \pimem_x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" - wire \pimem_x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" - wire \pimem_x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" - wire input 21 \wb_dcache_en - attribute \module_not_derived 1 - attribute \src "libresoc.v:129223.12-129257.4" - cell \l0$130 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len - connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 - connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal - connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 - connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 - connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 - connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 - connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 - connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129258.9-129280.4" - cell \lsmem \lsmem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \m_ld_data_o \pimem_m_ld_data_o - connect \m_valid_i \pimem_m_valid_i - connect \wb_dcache_en \wb_dcache_en - connect \x_addr_i \pimem_x_addr_i - connect \x_busy_o \pimem_x_busy_o - connect \x_ld_i \pimem_x_ld_i - connect \x_mask_i \pimem_x_mask_i - connect \x_st_data_i \pimem_x_st_data_i - connect \x_st_i \pimem_x_st_i - connect \x_valid_i \pimem_x_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129281.9-129305.4" - cell \pimem \pimem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \pimem_ldst_port0_data_len - connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal - connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i - connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok - connect \m_ld_data_o \pimem_m_ld_data_o - connect \m_valid_i \pimem_m_valid_i - connect \x_addr_i \pimem_x_addr_i - connect \x_busy_o \pimem_x_busy_o - connect \x_ld_i \pimem_x_ld_i - connect \x_mask_i \pimem_x_mask_i - connect \x_st_data_i \pimem_x_st_data_i - connect \x_st_i \pimem_x_st_i - connect \x_valid_i \pimem_x_valid_i - end - connect \pimem_ldst_port0_exc_$signal 1'0 -end -attribute \src "libresoc.v:129311.1-129719.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" -attribute \generator "nMigen" -module \l0$130 - attribute \src "libresoc.v:129574.3-129588.6" - wire $0\idx_l$23$next[0:0]$5880 - attribute \src "libresoc.v:129474.3-129475.35" - wire $0\idx_l$23[0:0]$5847 - attribute \src "libresoc.v:129332.7-129332.24" - wire $0\idx_l$23[0:0]$5902 - attribute \src "libresoc.v:129629.3-129638.6" - wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:129619.3-129628.6" - wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:129312.7-129312.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:129495.3-129504.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$5849 - attribute \src "libresoc.v:129505.3-129514.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$5852 - attribute \src "libresoc.v:129547.3-129556.6" - wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:129537.3-129546.6" - wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:129609.3-129618.6" - wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:129684.3-129693.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$5897 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$5864 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$5865 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$5866 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$5867 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$5868 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$5869 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$5870 - attribute \src "libresoc.v:129557.3-129573.6" - wire $0\ldst_port0_exc_$signal[0:0]$5863 - attribute \src "libresoc.v:129694.3-129703.6" - wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:129664.3-129673.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$5891 - attribute \src "libresoc.v:129674.3-129683.6" - wire $0\ldst_port0_is_st_i$9[0:0]$5894 - attribute \src "libresoc.v:129526.3-129536.6" - wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:129526.3-129536.6" - wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:129599.3-129608.6" - wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:129589.3-129598.6" - wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:129515.3-129525.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$5855 - attribute \src "libresoc.v:129515.3-129525.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$5856 - attribute \src "libresoc.v:129472.3-129473.36" - wire $0\reset_delay[0:0] - attribute \src "libresoc.v:129654.3-129663.6" - wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:129639.3-129653.6" - wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129574.3-129588.6" - wire $1\idx_l$23$next[0:0]$5881 - attribute \src "libresoc.v:129629.3-129638.6" - wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:129619.3-129628.6" - wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:129495.3-129504.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$5850 - attribute \src "libresoc.v:129505.3-129514.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$5853 - attribute \src "libresoc.v:129547.3-129556.6" - wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:129537.3-129546.6" - wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:129609.3-129618.6" - wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:129684.3-129693.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$5898 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$5872 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$5873 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$5874 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$5875 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$5876 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$5877 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$5878 - attribute \src "libresoc.v:129557.3-129573.6" - wire $1\ldst_port0_exc_$signal[0:0]$5871 - attribute \src "libresoc.v:129694.3-129703.6" - wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:129664.3-129673.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$5892 - attribute \src "libresoc.v:129674.3-129683.6" - wire $1\ldst_port0_is_st_i$9[0:0]$5895 - attribute \src "libresoc.v:129526.3-129536.6" - wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:129526.3-129536.6" - wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:129599.3-129608.6" - wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:129589.3-129598.6" - wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:129515.3-129525.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$5857 - attribute \src "libresoc.v:129515.3-129525.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$5858 - attribute \src "libresoc.v:129459.7-129459.25" - wire $1\reset_delay[0:0] - attribute \src "libresoc.v:129654.3-129663.6" - wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:129639.3-129653.6" - wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129574.3-129588.6" - wire $2\idx_l$23$next[0:0]$5882 - attribute \src "libresoc.v:129639.3-129653.6" - wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129470.18-129470.103" - wire $not$libresoc.v:129470$5843_Y - attribute \src "libresoc.v:129471.18-129471.118" - wire $not$libresoc.v:129471$5844_Y - attribute \src "libresoc.v:129468.18-129468.134" - wire $or$libresoc.v:129468$5841_Y - attribute \src "libresoc.v:129469.18-129469.120" - wire $ternary$libresoc.v:129469$5842_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire \$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" - wire width 96 \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" - wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \idx_l$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \idx_l$23$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \idx_l_q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \idx_l_r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \idx_l_s_idx_l - attribute \src "libresoc.v:129312.7-129312.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 48 output 25 \ldst_port0_addr_i$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \ldst_port0_addr_i_ok$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 16 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 27 \ldst_port0_addr_ok_o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 23 \ldst_port0_busy_o$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire \ldst_port0_cache_paradox - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - wire \ldst_port0_cache_paradox$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 24 \ldst_port0_data_len$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 8 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 9 \ldst_port0_exc_$signal$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 32 \ldst_port0_exc_$signal$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 10 \ldst_port0_exc_$signal$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 11 \ldst_port0_exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \ldst_port0_exc_$signal$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 12 \ldst_port0_exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 13 \ldst_port0_exc_$signal$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 14 \ldst_port0_exc_$signal$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire output 15 \ldst_port0_exc_$signal$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire \ldst_port0_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire \ldst_port0_go_die_i$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 21 \ldst_port0_is_ld_i$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 22 \ldst_port0_is_st_i$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 17 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 28 \ldst_port0_ld_data_o$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 18 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 29 \ldst_port0_ld_data_o_ok$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" - wire \ldst_port0_ldst_error - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" - wire \ldst_port0_ldst_error$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" - wire \ldst_port0_mmu_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" - wire \ldst_port0_mmu_done$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 31 \ldst_port0_st_data_i$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \ldst_port0_st_data_i_ok$17 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire \pick_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire \pick_n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire \pick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire \reset_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \reset_l_q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:129470$5843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pick_n - connect \Y $not$libresoc.v:129470$5843_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:129471$5844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:129471$5844_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:129468$5841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:129468$5841_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:129469$5842 - parameter \WIDTH 1 - connect \A \idx_l$23 - connect \B \pick_o - connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:129469$5842_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129476.9-129482.4" - cell \idx_l \idx_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_idx_l \idx_l_q_idx_l - connect \r_idx_l \idx_l_r_idx_l - connect \s_idx_l \idx_l_s_idx_l - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129483.8-129487.4" - cell \pick \pick - connect \i \pick_i - connect \n \pick_n - connect \o \pick_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:129488.17-129494.4" - cell \reset_l$131 \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_reset \reset_l_q_reset - connect \r_reset \reset_l_r_reset - connect \s_reset \reset_l_s_reset - end - attribute \src "libresoc.v:129312.7-129312.20" - process $proc$libresoc.v:129312$5900 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:129332.7-129332.24" - process $proc$libresoc.v:129332$5901 - assign { } { } - assign $0\idx_l$23[0:0]$5902 1'0 - sync always - sync init - update \idx_l$23 $0\idx_l$23[0:0]$5902 - end - attribute \src "libresoc.v:129459.7-129459.25" - process $proc$libresoc.v:129459$5903 - assign { } { } - assign $1\reset_delay[0:0] 1'0 - sync always - sync init - update \reset_delay $1\reset_delay[0:0] - end - attribute \src "libresoc.v:129472.3-129473.36" - process $proc$libresoc.v:129472$5845 - assign { } { } - assign $0\reset_delay[0:0] \reset_l_q_reset - sync posedge \coresync_clk - update \reset_delay $0\reset_delay[0:0] - end - attribute \src "libresoc.v:129474.3-129475.35" - process $proc$libresoc.v:129474$5846 - assign { } { } - assign $0\idx_l$23[0:0]$5847 \idx_l$23$next - sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$5847 - end - attribute \src "libresoc.v:129495.3-129504.6" - process $proc$libresoc.v:129495$5848 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$5849 $1\ldst_port0_addr_i$12[47:0]$5850 - attribute \src "libresoc.v:129496.5-129496.29" - switch \initial - attribute \src "libresoc.v:129496.9-129496.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$5850 \$32 [47:0] - case - assign $1\ldst_port0_addr_i$12[47:0]$5850 48'000000000000000000000000000000000000000000000000 - end - sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$5849 - end - attribute \src "libresoc.v:129505.3-129514.6" - process $proc$libresoc.v:129505$5851 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$5852 $1\ldst_port0_addr_i_ok$13[0:0]$5853 - attribute \src "libresoc.v:129506.5-129506.29" - switch \initial - attribute \src "libresoc.v:129506.9-129506.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$5853 \ldst_port0_addr_i_ok - case - assign $1\ldst_port0_addr_i_ok$13[0:0]$5853 1'0 - end - sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$5852 - end - attribute \src "libresoc.v:129515.3-129525.6" - process $proc$libresoc.v:129515$5854 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$5855 $1\ldst_port0_st_data_i$18[63:0]$5857 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$5856 $1\ldst_port0_st_data_i_ok$17[0:0]$5858 - attribute \src "libresoc.v:129516.5-129516.29" - switch \initial - attribute \src "libresoc.v:129516.9-129516.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$5858 $1\ldst_port0_st_data_i$18[63:0]$5857 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } - case - assign $1\ldst_port0_st_data_i$18[63:0]$5857 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$5858 1'0 - end - sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$5855 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$5856 - end - attribute \src "libresoc.v:129526.3-129536.6" - process $proc$libresoc.v:129526$5859 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:129527.5-129527.29" - switch \initial - attribute \src "libresoc.v:129527.9-129527.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } - case - assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 - end - sync always - update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] - update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] - end - attribute \src "libresoc.v:129537.3-129546.6" - process $proc$libresoc.v:129537$5860 - assign { } { } - assign { } { } - assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:129538.5-129538.29" - switch \initial - attribute \src "libresoc.v:129538.9-129538.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 - case - assign $1\ldst_port0_busy_o[0:0] 1'0 - end - sync always - update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] - end - attribute \src "libresoc.v:129547.3-129556.6" - process $proc$libresoc.v:129547$5861 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:129548.5-129548.29" - switch \initial - attribute \src "libresoc.v:129548.9-129548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 - case - assign $1\ldst_port0_addr_ok_o[0:0] 1'0 - end - sync always - update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] - end - attribute \src "libresoc.v:129557.3-129573.6" - process $proc$libresoc.v:129557$5862 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$5863 $1\ldst_port0_exc_$signal[0:0]$5871 - assign $0\ldst_port0_exc_$signal$1[0:0]$5864 $1\ldst_port0_exc_$signal$1[0:0]$5872 - assign $0\ldst_port0_exc_$signal$2[0:0]$5865 $1\ldst_port0_exc_$signal$2[0:0]$5873 - assign $0\ldst_port0_exc_$signal$3[0:0]$5866 $1\ldst_port0_exc_$signal$3[0:0]$5874 - assign $0\ldst_port0_exc_$signal$4[0:0]$5867 $1\ldst_port0_exc_$signal$4[0:0]$5875 - assign $0\ldst_port0_exc_$signal$5[0:0]$5868 $1\ldst_port0_exc_$signal$5[0:0]$5876 - assign $0\ldst_port0_exc_$signal$6[0:0]$5869 $1\ldst_port0_exc_$signal$6[0:0]$5877 - assign $0\ldst_port0_exc_$signal$7[0:0]$5870 $1\ldst_port0_exc_$signal$7[0:0]$5878 - attribute \src "libresoc.v:129558.5-129558.29" - switch \initial - attribute \src "libresoc.v:129558.9-129558.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$5878 $1\ldst_port0_exc_$signal$6[0:0]$5877 $1\ldst_port0_exc_$signal$5[0:0]$5876 $1\ldst_port0_exc_$signal$4[0:0]$5875 $1\ldst_port0_exc_$signal$3[0:0]$5874 $1\ldst_port0_exc_$signal$2[0:0]$5873 $1\ldst_port0_exc_$signal$1[0:0]$5872 $1\ldst_port0_exc_$signal[0:0]$5871 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } - case - assign $1\ldst_port0_exc_$signal[0:0]$5871 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$5872 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$5873 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$5874 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$5875 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$5876 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$5877 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$5878 1'0 - end - sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$5863 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$5864 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$5865 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$5866 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$5867 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$5868 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$5869 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$5870 - end - attribute \src "libresoc.v:129574.3-129588.6" - process $proc$libresoc.v:129574$5879 - assign { } { } - assign { } { } - assign { } { } - assign $0\idx_l$23$next[0:0]$5880 $2\idx_l$23$next[0:0]$5882 - attribute \src "libresoc.v:129575.5-129575.29" - switch \initial - attribute \src "libresoc.v:129575.9-129575.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\idx_l$23$next[0:0]$5881 \pick_o - case - assign $1\idx_l$23$next[0:0]$5881 \idx_l$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\idx_l$23$next[0:0]$5882 1'0 - case - assign $2\idx_l$23$next[0:0]$5882 $1\idx_l$23$next[0:0]$5881 - end - sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$5880 - end - attribute \src "libresoc.v:129589.3-129598.6" - process $proc$libresoc.v:129589$5883 - assign { } { } - assign { } { } - assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:129590.5-129590.29" - switch \initial - attribute \src "libresoc.v:129590.9-129590.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 - case - assign $1\ldst_port0_mmu_done[0:0] 1'0 - end - sync always - update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] - end - attribute \src "libresoc.v:129599.3-129608.6" - process $proc$libresoc.v:129599$5884 - assign { } { } - assign { } { } - assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:129600.5-129600.29" - switch \initial - attribute \src "libresoc.v:129600.9-129600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 - case - assign $1\ldst_port0_ldst_error[0:0] 1'0 - end - sync always - update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] - end - attribute \src "libresoc.v:129609.3-129618.6" - process $proc$libresoc.v:129609$5885 - assign { } { } - assign { } { } - assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:129610.5-129610.29" - switch \initial - attribute \src "libresoc.v:129610.9-129610.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 - case - assign $1\ldst_port0_cache_paradox[0:0] 1'0 - end - sync always - update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] - end - attribute \src "libresoc.v:129619.3-129628.6" - process $proc$libresoc.v:129619$5886 - assign { } { } - assign { } { } - assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:129620.5-129620.29" - switch \initial - attribute \src "libresoc.v:129620.9-129620.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - switch \$26 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\idx_l_s_idx_l[0:0] 1'1 - case - assign $1\idx_l_s_idx_l[0:0] 1'0 - end - sync always - update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] - end - attribute \src "libresoc.v:129629.3-129638.6" - process $proc$libresoc.v:129629$5887 - assign { } { } - assign { } { } - assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:129630.5-129630.29" - switch \initial - attribute \src "libresoc.v:129630.9-129630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\idx_l_r_idx_l[0:0] 1'1 - case - assign $1\idx_l_r_idx_l[0:0] 1'1 - end - sync always - update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] - end - attribute \src "libresoc.v:129639.3-129653.6" - process $proc$libresoc.v:129639$5888 - assign { } { } - assign { } { } - assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:129640.5-129640.29" - switch \initial - attribute \src "libresoc.v:129640.9-129640.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - switch \$28 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reset_l_s_reset[0:0] 1'1 - case - assign $2\reset_l_s_reset[0:0] 1'0 - end - case - assign $1\reset_l_s_reset[0:0] 1'0 - end - sync always - update \reset_l_s_reset $0\reset_l_s_reset[0:0] - end - attribute \src "libresoc.v:129654.3-129663.6" - process $proc$libresoc.v:129654$5889 - assign { } { } - assign { } { } - assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:129655.5-129655.29" - switch \initial - attribute \src "libresoc.v:129655.9-129655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_r_reset[0:0] 1'1 - case - assign $1\reset_l_r_reset[0:0] 1'0 - end - sync always - update \reset_l_r_reset $0\reset_l_r_reset[0:0] - end - attribute \src "libresoc.v:129664.3-129673.6" - process $proc$libresoc.v:129664$5890 - assign { } { } - assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$5891 $1\ldst_port0_is_ld_i$8[0:0]$5892 - attribute \src "libresoc.v:129665.5-129665.29" - switch \initial - attribute \src "libresoc.v:129665.9-129665.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$5892 \ldst_port0_is_ld_i - case - assign $1\ldst_port0_is_ld_i$8[0:0]$5892 1'0 - end - sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$5891 - end - attribute \src "libresoc.v:129674.3-129683.6" - process $proc$libresoc.v:129674$5893 - assign { } { } - assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$5894 $1\ldst_port0_is_st_i$9[0:0]$5895 - attribute \src "libresoc.v:129675.5-129675.29" - switch \initial - attribute \src "libresoc.v:129675.9-129675.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$5895 \ldst_port0_is_st_i - case - assign $1\ldst_port0_is_st_i$9[0:0]$5895 1'0 - end - sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$5894 - end - attribute \src "libresoc.v:129684.3-129693.6" - process $proc$libresoc.v:129684$5896 - assign { } { } - assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$5897 $1\ldst_port0_data_len$11[3:0]$5898 - attribute \src "libresoc.v:129685.5-129685.29" - switch \initial - attribute \src "libresoc.v:129685.9-129685.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$5898 \ldst_port0_data_len - case - assign $1\ldst_port0_data_len$11[3:0]$5898 4'0000 - end - sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$5897 - end - attribute \src "libresoc.v:129694.3-129703.6" - process $proc$libresoc.v:129694$5899 - assign { } { } - assign { } { } - assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:129695.5-129695.29" - switch \initial - attribute \src "libresoc.v:129695.9-129695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch \idx_l_q_idx_l - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 - case - assign $1\ldst_port0_go_die_i[0:0] 1'0 - end - sync always - update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] - end - connect \$20 $or$libresoc.v:129468$5841_Y - connect \$24 $ternary$libresoc.v:129469$5842_Y - connect \$26 $not$libresoc.v:129470$5843_Y - connect \$28 $not$libresoc.v:129471$5844_Y - connect \$22 \$24 - connect \$32 \ldst_port0_addr_i - connect \ldst_port0_go_die_i$30 1'0 - connect \ldst_port0_exc_$signal$33 1'0 - connect \ldst_port0_exc_$signal$34 1'0 - connect \ldst_port0_exc_$signal$35 1'0 - connect \ldst_port0_exc_$signal$36 1'0 - connect \ldst_port0_exc_$signal$37 1'0 - connect \ldst_port0_exc_$signal$38 1'0 - connect \ldst_port0_exc_$signal$39 1'0 - connect \ldst_port0_mmu_done$40 1'0 - connect \ldst_port0_ldst_error$41 1'0 - connect \ldst_port0_cache_paradox$42 1'0 - connect \reset_delay$next \reset_l_q_reset - connect \pick_i \$20 -end -attribute \src "libresoc.v:129723.1-129781.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" -attribute \generator "nMigen" -module \ld_active - attribute \src "libresoc.v:129724.7-129724.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:129769.3-129777.6" - wire $0\q_int$next[0:0]$5914 - attribute \src "libresoc.v:129767.3-129768.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:129769.3-129777.6" - wire $1\q_int$next[0:0]$5915 - attribute \src "libresoc.v:129746.7-129746.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:129759.17-129759.96" - wire $and$libresoc.v:129759$5904_Y - attribute \src "libresoc.v:129764.17-129764.96" - wire $and$libresoc.v:129764$5909_Y - attribute \src "libresoc.v:129761.18-129761.99" - wire $not$libresoc.v:129761$5906_Y - attribute \src "libresoc.v:129763.17-129763.98" - wire $not$libresoc.v:129763$5908_Y - attribute \src "libresoc.v:129766.17-129766.98" - wire $not$libresoc.v:129766$5911_Y - attribute \src "libresoc.v:129760.18-129760.104" - wire $or$libresoc.v:129760$5905_Y - attribute \src "libresoc.v:129762.18-129762.105" - wire $or$libresoc.v:129762$5907_Y - attribute \src "libresoc.v:129765.17-129765.103" - wire $or$libresoc.v:129765$5910_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:129724.7-129724.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 2 \r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:129759$5904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:129759$5904_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:129764$5909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:129764$5909_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:129761$5906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \Y $not$libresoc.v:129761$5906_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:129763$5908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $not$libresoc.v:129763$5908_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:129766$5911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $not$libresoc.v:129766$5911_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:129760$5905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_ld_active - connect \Y $or$libresoc.v:129760$5905_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:129762$5907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \B \q_int - connect \Y $or$libresoc.v:129762$5907_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:129765$5910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_ld_active - connect \Y $or$libresoc.v:129765$5910_Y - end - attribute \src "libresoc.v:129724.7-129724.20" - process $proc$libresoc.v:129724$5916 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:129746.7-129746.19" - process $proc$libresoc.v:129746$5917 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:129767.3-129768.27" - process $proc$libresoc.v:129767$5912 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:129769.3-129777.6" - process $proc$libresoc.v:129769$5913 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$5914 $1\q_int$next[0:0]$5915 - attribute \src "libresoc.v:129770.5-129770.29" - switch \initial - attribute \src "libresoc.v:129770.9-129770.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$5915 1'0 - case - assign $1\q_int$next[0:0]$5915 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$5914 - end - connect \$9 $and$libresoc.v:129759$5904_Y - connect \$11 $or$libresoc.v:129760$5905_Y - connect \$13 $not$libresoc.v:129761$5906_Y - connect \$15 $or$libresoc.v:129762$5907_Y - connect \$1 $not$libresoc.v:129763$5908_Y - connect \$3 $and$libresoc.v:129764$5909_Y - connect \$5 $or$libresoc.v:129765$5910_Y - connect \$7 $not$libresoc.v:129766$5911_Y - connect \qlq_ld_active \$15 - connect \qn_ld_active \$13 - connect \q_ld_active \$11 -end -attribute \src "libresoc.v:129785.1-131142.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" -attribute \generator "nMigen" -module \ldst0 - attribute \src "libresoc.v:130797.3-130805.6" - wire $0\adr_l_r_adr$next[0:0]$6060 - attribute \src "libresoc.v:130679.3-130680.39" - wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:130625.3-130626.21" - wire $0\alu_ok[0:0] - attribute \src "libresoc.v:130962.3-130971.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:130972.3-130981.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:130952.3-130961.6" - wire width 64 $0\ea_r$next[63:0]$6148 - attribute \src "libresoc.v:130627.3-130628.25" - wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:129786.7-129786.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:131027.3-131046.6" - wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:130991.3-131014.6" - wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:130894.3-130903.6" - wire width 64 $0\ldo_r$next[63:0]$6133 - attribute \src "libresoc.v:130635.3-130636.27" - wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:130623.3-130624.33" - wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:130982.3-130990.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6153 - attribute \src "libresoc.v:130621.3-130622.57" - wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:131071.3-131082.6" - wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:130842.3-130850.6" - wire $0\lsd_l_r_lsd$next[0:0]$6075 - attribute \src "libresoc.v:130669.3-130670.39" - wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:130770.3-130778.6" - wire $0\opc_l_r_opc$next[0:0]$6051 - attribute \src "libresoc.v:130685.3-130686.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130761.3-130769.6" - wire $0\opc_l_s_opc$next[0:0]$6048 - attribute \src "libresoc.v:130687.3-130688.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__byte_reverse$next[0:0]$6078 - attribute \src "libresoc.v:130661.3-130662.57" - wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6079 - attribute \src "libresoc.v:130659.3-130660.49" - wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 12 $0\oper_r__fn_unit$next[11:0]$6080 - attribute \src "libresoc.v:130639.3-130640.47" - wire width 12 $0\oper_r__fn_unit[11:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6081 - attribute \src "libresoc.v:130641.3-130642.61" - wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6082 - attribute \src "libresoc.v:130643.3-130644.57" - wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 32 $0\oper_r__insn$next[31:0]$6083 - attribute \src "libresoc.v:130667.3-130668.41" - wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6084 - attribute \src "libresoc.v:130637.3-130638.51" - wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__is_32bit$next[0:0]$6085 - attribute \src "libresoc.v:130655.3-130656.49" - wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__is_signed$next[0:0]$6086 - attribute \src "libresoc.v:130657.3-130658.51" - wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6087 - attribute \src "libresoc.v:130665.3-130666.51" - wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__oe__oe$next[0:0]$6088 - attribute \src "libresoc.v:130651.3-130652.45" - wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__oe__ok$next[0:0]$6089 - attribute \src "libresoc.v:130653.3-130654.45" - wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__rc__ok$next[0:0]$6090 - attribute \src "libresoc.v:130649.3-130650.45" - wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__rc__rc$next[0:0]$6091 - attribute \src "libresoc.v:130647.3-130648.45" - wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__sign_extend$next[0:0]$6092 - attribute \src "libresoc.v:130663.3-130664.55" - wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $0\oper_r__zero_a$next[0:0]$6093 - attribute \src "libresoc.v:130645.3-130646.45" - wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:130689.3-130690.28" - wire $0\p_st_go[0:0] - attribute \src "libresoc.v:131015.3-131026.6" - wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:130788.3-130796.6" - wire width 3 $0\src_l_r_src$next[2:0]$6057 - attribute \src "libresoc.v:130681.3-130682.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:130779.3-130787.6" - wire width 3 $0\src_l_s_src$next[2:0]$6054 - attribute \src "libresoc.v:130683.3-130684.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:130904.3-130919.6" - wire width 64 $0\src_r0$next[63:0]$6136 - attribute \src "libresoc.v:130633.3-130634.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:130920.3-130935.6" - wire width 64 $0\src_r1$next[63:0]$6140 - attribute \src "libresoc.v:130631.3-130632.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:130936.3-130951.6" - wire width 64 $0\src_r2$next[63:0]$6144 - attribute \src "libresoc.v:130629.3-130630.29" - wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:131047.3-131070.6" - wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:130833.3-130841.6" - wire $0\sto_l_r_sto$next[0:0]$6072 - attribute \src "libresoc.v:130671.3-130672.39" - wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:130824.3-130832.6" - wire $0\upd_l_r_upd$next[0:0]$6069 - attribute \src "libresoc.v:130673.3-130674.39" - wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:130815.3-130823.6" - wire $0\upd_l_s_upd$next[0:0]$6066 - attribute \src "libresoc.v:130675.3-130676.39" - wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:130806.3-130814.6" - wire $0\wri_l_r_wri$next[0:0]$6063 - attribute \src "libresoc.v:130677.3-130678.39" - wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:130797.3-130805.6" - wire $1\adr_l_r_adr$next[0:0]$6061 - attribute \src "libresoc.v:129982.7-129982.25" - wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:129996.7-129996.20" - wire $1\alu_ok[0:0] - attribute \src "libresoc.v:130962.3-130971.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:130972.3-130981.6" - wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:130952.3-130961.6" - wire width 64 $1\ea_r$next[63:0]$6149 - attribute \src "libresoc.v:130042.14-130042.41" - wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:131027.3-131046.6" - wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:130991.3-131014.6" - wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:130894.3-130903.6" - wire width 64 $1\ldo_r$next[63:0]$6134 - attribute \src "libresoc.v:130072.14-130072.42" - wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:130077.14-130077.62" - wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:130982.3-130990.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6154 - attribute \src "libresoc.v:130082.7-130082.34" - wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:131071.3-131082.6" - wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:130842.3-130850.6" - wire $1\lsd_l_r_lsd$next[0:0]$6076 - attribute \src "libresoc.v:130131.7-130131.25" - wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:130770.3-130778.6" - wire $1\opc_l_r_opc$next[0:0]$6052 - attribute \src "libresoc.v:130145.7-130145.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:130761.3-130769.6" - wire $1\opc_l_s_opc$next[0:0]$6049 - attribute \src "libresoc.v:130149.7-130149.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__byte_reverse$next[0:0]$6094 - attribute \src "libresoc.v:130277.7-130277.34" - wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6095 - attribute \src "libresoc.v:130281.13-130281.36" - wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 12 $1\oper_r__fn_unit$next[11:0]$6096 - attribute \src "libresoc.v:130298.14-130298.39" - wire width 12 $1\oper_r__fn_unit[11:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6097 - attribute \src "libresoc.v:130302.14-130302.59" - wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6098 - attribute \src "libresoc.v:130306.7-130306.34" - wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 32 $1\oper_r__insn$next[31:0]$6099 - attribute \src "libresoc.v:130310.14-130310.34" - wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6100 - attribute \src "libresoc.v:130388.13-130388.38" - wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__is_32bit$next[0:0]$6101 - attribute \src "libresoc.v:130392.7-130392.30" - wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__is_signed$next[0:0]$6102 - attribute \src "libresoc.v:130396.7-130396.31" - wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6103 - attribute \src "libresoc.v:130405.13-130405.37" - wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__oe__oe$next[0:0]$6104 - attribute \src "libresoc.v:130409.7-130409.28" - wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__oe__ok$next[0:0]$6105 - attribute \src "libresoc.v:130413.7-130413.28" - wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__rc__ok$next[0:0]$6106 - attribute \src "libresoc.v:130417.7-130417.28" - wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__rc__rc$next[0:0]$6107 - attribute \src "libresoc.v:130421.7-130421.28" - wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__sign_extend$next[0:0]$6108 - attribute \src "libresoc.v:130425.7-130425.33" - wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $1\oper_r__zero_a$next[0:0]$6109 - attribute \src "libresoc.v:130429.7-130429.28" - wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:130433.7-130433.21" - wire $1\p_st_go[0:0] - attribute \src "libresoc.v:131015.3-131026.6" - wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:130788.3-130796.6" - wire width 3 $1\src_l_r_src$next[2:0]$6058 - attribute \src "libresoc.v:130475.13-130475.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:130779.3-130787.6" - wire width 3 $1\src_l_s_src$next[2:0]$6055 - attribute \src "libresoc.v:130479.13-130479.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:130904.3-130919.6" - wire width 64 $1\src_r0$next[63:0]$6137 - attribute \src "libresoc.v:130483.14-130483.43" - wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:130920.3-130935.6" - wire width 64 $1\src_r1$next[63:0]$6141 - attribute \src "libresoc.v:130487.14-130487.43" - wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:130936.3-130951.6" - wire width 64 $1\src_r2$next[63:0]$6145 - attribute \src "libresoc.v:130491.14-130491.43" - wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:131047.3-131070.6" - wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:130833.3-130841.6" - wire $1\sto_l_r_sto$next[0:0]$6073 - attribute \src "libresoc.v:130501.7-130501.25" - wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:130824.3-130832.6" - wire $1\upd_l_r_upd$next[0:0]$6070 - attribute \src "libresoc.v:130511.7-130511.25" - wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:130815.3-130823.6" - wire $1\upd_l_s_upd$next[0:0]$6067 - attribute \src "libresoc.v:130515.7-130515.25" - wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:130806.3-130814.6" - wire $1\wri_l_r_wri$next[0:0]$6064 - attribute \src "libresoc.v:130525.7-130525.25" - wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:131027.3-131046.6" - wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:130991.3-131014.6" - wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__byte_reverse$next[0:0]$6110 - attribute \src "libresoc.v:130851.3-130893.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6111 - attribute \src "libresoc.v:130851.3-130893.6" - wire width 12 $2\oper_r__fn_unit$next[11:0]$6112 - attribute \src "libresoc.v:130851.3-130893.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6113 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6114 - attribute \src "libresoc.v:130851.3-130893.6" - wire width 32 $2\oper_r__insn$next[31:0]$6115 - attribute \src "libresoc.v:130851.3-130893.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6116 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__is_32bit$next[0:0]$6117 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__is_signed$next[0:0]$6118 - attribute \src "libresoc.v:130851.3-130893.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6119 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__oe__oe$next[0:0]$6120 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__oe__ok$next[0:0]$6121 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__rc__ok$next[0:0]$6122 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__rc__rc$next[0:0]$6123 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__sign_extend$next[0:0]$6124 - attribute \src "libresoc.v:130851.3-130893.6" - wire $2\oper_r__zero_a$next[0:0]$6125 - attribute \src "libresoc.v:130904.3-130919.6" - wire width 64 $2\src_r0$next[63:0]$6138 - attribute \src "libresoc.v:130920.3-130935.6" - wire width 64 $2\src_r1$next[63:0]$6142 - attribute \src "libresoc.v:130936.3-130951.6" - wire width 64 $2\src_r2$next[63:0]$6146 - attribute \src "libresoc.v:131047.3-131070.6" - wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:130851.3-130893.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6126 - attribute \src "libresoc.v:130851.3-130893.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6127 - attribute \src "libresoc.v:130851.3-130893.6" - wire $3\oper_r__oe__oe$next[0:0]$6128 - attribute \src "libresoc.v:130851.3-130893.6" - wire $3\oper_r__oe__ok$next[0:0]$6129 - attribute \src "libresoc.v:130851.3-130893.6" - wire $3\oper_r__rc__ok$next[0:0]$6130 - attribute \src "libresoc.v:130851.3-130893.6" - wire $3\oper_r__rc__rc$next[0:0]$6131 - attribute \src "libresoc.v:130607.18-130607.124" - wire width 65 $add$libresoc.v:130607$5998_Y - attribute \src "libresoc.v:130530.19-130530.118" - wire $and$libresoc.v:130530$5918_Y - attribute \src "libresoc.v:130531.19-130531.125" - wire $and$libresoc.v:130531$5919_Y - attribute \src "libresoc.v:130532.19-130532.120" - wire $and$libresoc.v:130532$5920_Y - attribute \src "libresoc.v:130533.19-130533.125" - wire $and$libresoc.v:130533$5921_Y - attribute \src "libresoc.v:130534.19-130534.118" - wire $and$libresoc.v:130534$5922_Y - attribute \src "libresoc.v:130536.19-130536.119" - wire $and$libresoc.v:130536$5924_Y - attribute \src "libresoc.v:130537.19-130537.123" - wire $and$libresoc.v:130537$5925_Y - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 3 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 4 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 23 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 22 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 26 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 25 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 24 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire input 5 \cu_st__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire output 2 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 31 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 30 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 33 \ea - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \exc_$signal$185 - attribute \src "libresoc.v:129786.7-129786.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" - wire \ld_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" - wire \ld_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" - wire width 64 \ldd_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" - wire width 64 \ldd_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" - wire width 64 \lddata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 output 38 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 96 \ldst_port0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 39 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \ldst_port0_addr_i_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire input 48 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire input 34 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 37 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 40 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 41 \ldst_port0_exc_$signal$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 42 \ldst_port0_exc_$signal$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 43 \ldst_port0_exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 44 \ldst_port0_exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 45 \ldst_port0_exc_$signal$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 46 \ldst_port0_exc_$signal$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 47 \ldst_port0_exc_$signal$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire output 35 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire output 36 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 49 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 50 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 51 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 52 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" - wire \load_mem_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \lod_l_qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \lod_l_r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \lod_l_s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \lsd_l_q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \lsd_l_r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \lsd_l_r_lsd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \lsd_l_s_lsd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 32 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" - wire \op_is_ld - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" - wire \op_is_st - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \oper_i_ldst_ldst0__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \oper_i_ldst_ldst0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 7 \oper_i_ldst_ldst0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \oper_i_ldst_ldst0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_ldst_ldst0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 21 \oper_i_ldst_ldst0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \oper_i_ldst_ldst0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_ldst_ldst0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_ldst_ldst0__is_signed - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 20 \oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_ldst_ldst0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_ldst_ldst0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \oper_i_ldst_ldst0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_ldst_ldst0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \oper_i_ldst_ldst0__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__byte_reverse$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \oper_r__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \oper_r__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:130571$5960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 96 - parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:130571$5959_Y - connect \Y $pos$libresoc.v:130571$5960_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130573$5963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:130573$5962_Y - connect \Y $pos$libresoc.v:130573$5963_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130574$5964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:130574$5964_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130576$5966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:130576$5966_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130578$5969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:130578$5968_Y - connect \Y $pos$libresoc.v:130578$5969_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130579$5970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:130579$5970_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $pos$libresoc.v:130580$5971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:130580$5971_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:130603$5994 - parameter \WIDTH 64 - connect \A \ldo_r - connect \B \ldd_o - connect \S \ld_ok - connect \Y $ternary$libresoc.v:130603$5994_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:130604$5995 - parameter \WIDTH 64 - connect \A \ea_r - connect \B \alu_o - connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:130604$5995_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:130605$5996 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:130605$5996_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:130606$5997 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \oper_r__imm_data__data - connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:130606$5997_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130691.9-130697.4" - cell \adr_l \adr_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_adr \adr_l_q_adr - connect \r_adr \adr_l_r_adr - connect \s_adr \adr_l_s_adr - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130698.15-130704.4" - cell \alu_l$128 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130705.9-130711.4" - cell \lod_l \lod_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \qn_lod \lod_l_qn_lod - connect \r_lod \lod_l_r_lod - connect \s_lod \lod_l_s_lod - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130712.9-130718.4" - cell \lsd_l \lsd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_lsd \lsd_l_q_lsd - connect \r_lsd \lsd_l_r_lsd - connect \s_lsd \lsd_l_s_lsd - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130719.15-130725.4" - cell \opc_l$126 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130726.15-130732.4" - cell \rst_l$129 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rst \rst_l_q_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130733.15-130739.4" - cell \src_l$127 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130740.9-130746.4" - cell \sto_l \sto_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_sto \sto_l_q_sto - connect \r_sto \sto_l_r_sto - connect \s_sto \sto_l_s_sto - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130747.9-130753.4" - cell \upd_l \upd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_upd \upd_l_q_upd - connect \r_upd \upd_l_r_upd - connect \s_upd \upd_l_s_upd - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:130754.9-130760.4" - cell \wri_l \wri_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_wri \wri_l_q_wri - connect \r_wri \wri_l_r_wri - connect \s_wri \wri_l_s_wri - end - attribute \src "libresoc.v:129786.7-129786.20" - process $proc$libresoc.v:129786$6160 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:129982.7-129982.25" - process $proc$libresoc.v:129982$6161 - assign { } { } - assign $1\adr_l_r_adr[0:0] 1'1 - sync always - sync init - update \adr_l_r_adr $1\adr_l_r_adr[0:0] - end - attribute \src "libresoc.v:129996.7-129996.20" - process $proc$libresoc.v:129996$6162 - assign { } { } - assign $1\alu_ok[0:0] 1'0 - sync always - sync init - update \alu_ok $1\alu_ok[0:0] - end - attribute \src "libresoc.v:130042.14-130042.41" - process $proc$libresoc.v:130042$6163 - assign { } { } - assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ea_r $1\ea_r[63:0] - end - attribute \src "libresoc.v:130072.14-130072.42" - process $proc$libresoc.v:130072$6164 - assign { } { } - assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ldo_r $1\ldo_r[63:0] - end - attribute \src "libresoc.v:130077.14-130077.62" - process $proc$libresoc.v:130077$6165 - assign { } { } - assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] - end - attribute \src "libresoc.v:130082.7-130082.34" - process $proc$libresoc.v:130082$6166 - assign { } { } - assign $1\ldst_port0_addr_i_ok[0:0] 1'0 - sync always - sync init - update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] - end - attribute \src "libresoc.v:130131.7-130131.25" - process $proc$libresoc.v:130131$6167 - assign { } { } - assign $1\lsd_l_r_lsd[0:0] 1'1 - sync always - sync init - update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] - end - attribute \src "libresoc.v:130145.7-130145.25" - process $proc$libresoc.v:130145$6168 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:130149.7-130149.25" - process $proc$libresoc.v:130149$6169 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:130277.7-130277.34" - process $proc$libresoc.v:130277$6170 - assign { } { } - assign $1\oper_r__byte_reverse[0:0] 1'0 - sync always - sync init - update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] - end - attribute \src "libresoc.v:130281.13-130281.36" - process $proc$libresoc.v:130281$6171 - assign { } { } - assign $1\oper_r__data_len[3:0] 4'0000 - sync always - sync init - update \oper_r__data_len $1\oper_r__data_len[3:0] - end - attribute \src "libresoc.v:130298.14-130298.39" - process $proc$libresoc.v:130298$6172 - assign { } { } - assign $1\oper_r__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \oper_r__fn_unit $1\oper_r__fn_unit[11:0] - end - attribute \src "libresoc.v:130302.14-130302.59" - process $proc$libresoc.v:130302$6173 - assign { } { } - assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] - end - attribute \src "libresoc.v:130306.7-130306.34" - process $proc$libresoc.v:130306$6174 - assign { } { } - assign $1\oper_r__imm_data__ok[0:0] 1'0 - sync always - sync init - update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] - end - attribute \src "libresoc.v:130310.14-130310.34" - process $proc$libresoc.v:130310$6175 - assign { } { } - assign $1\oper_r__insn[31:0] 0 - sync always - sync init - update \oper_r__insn $1\oper_r__insn[31:0] - end - attribute \src "libresoc.v:130388.13-130388.38" - process $proc$libresoc.v:130388$6176 - assign { } { } - assign $1\oper_r__insn_type[6:0] 7'0000000 - sync always - sync init - update \oper_r__insn_type $1\oper_r__insn_type[6:0] - end - attribute \src "libresoc.v:130392.7-130392.30" - process $proc$libresoc.v:130392$6177 - assign { } { } - assign $1\oper_r__is_32bit[0:0] 1'0 - sync always - sync init - update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] - end - attribute \src "libresoc.v:130396.7-130396.31" - process $proc$libresoc.v:130396$6178 - assign { } { } - assign $1\oper_r__is_signed[0:0] 1'0 - sync always - sync init - update \oper_r__is_signed $1\oper_r__is_signed[0:0] - end - attribute \src "libresoc.v:130405.13-130405.37" - process $proc$libresoc.v:130405$6179 - assign { } { } - assign $1\oper_r__ldst_mode[1:0] 2'00 - sync always - sync init - update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] - end - attribute \src "libresoc.v:130409.7-130409.28" - process $proc$libresoc.v:130409$6180 - assign { } { } - assign $1\oper_r__oe__oe[0:0] 1'0 - sync always - sync init - update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] - end - attribute \src "libresoc.v:130413.7-130413.28" - process $proc$libresoc.v:130413$6181 - assign { } { } - assign $1\oper_r__oe__ok[0:0] 1'0 - sync always - sync init - update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] - end - attribute \src "libresoc.v:130417.7-130417.28" - process $proc$libresoc.v:130417$6182 - assign { } { } - assign $1\oper_r__rc__ok[0:0] 1'0 - sync always - sync init - update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] - end - attribute \src "libresoc.v:130421.7-130421.28" - process $proc$libresoc.v:130421$6183 - assign { } { } - assign $1\oper_r__rc__rc[0:0] 1'0 - sync always - sync init - update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] - end - attribute \src "libresoc.v:130425.7-130425.33" - process $proc$libresoc.v:130425$6184 - assign { } { } - assign $1\oper_r__sign_extend[0:0] 1'0 - sync always - sync init - update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] - end - attribute \src "libresoc.v:130429.7-130429.28" - process $proc$libresoc.v:130429$6185 - assign { } { } - assign $1\oper_r__zero_a[0:0] 1'0 - sync always - sync init - update \oper_r__zero_a $1\oper_r__zero_a[0:0] - end - attribute \src "libresoc.v:130433.7-130433.21" - process $proc$libresoc.v:130433$6186 - assign { } { } - assign $1\p_st_go[0:0] 1'0 - sync always - sync init - update \p_st_go $1\p_st_go[0:0] - end - attribute \src "libresoc.v:130475.13-130475.31" - process $proc$libresoc.v:130475$6187 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "libresoc.v:130479.13-130479.31" - process $proc$libresoc.v:130479$6188 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "libresoc.v:130483.14-130483.43" - process $proc$libresoc.v:130483$6189 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:130487.14-130487.43" - process $proc$libresoc.v:130487$6190 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:130491.14-130491.43" - process $proc$libresoc.v:130491$6191 - assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r2 $1\src_r2[63:0] - end - attribute \src "libresoc.v:130501.7-130501.25" - process $proc$libresoc.v:130501$6192 - assign { } { } - assign $1\sto_l_r_sto[0:0] 1'1 - sync always - sync init - update \sto_l_r_sto $1\sto_l_r_sto[0:0] - end - attribute \src "libresoc.v:130511.7-130511.25" - process $proc$libresoc.v:130511$6193 - assign { } { } - assign $1\upd_l_r_upd[0:0] 1'1 - sync always - sync init - update \upd_l_r_upd $1\upd_l_r_upd[0:0] - end - attribute \src "libresoc.v:130515.7-130515.25" - process $proc$libresoc.v:130515$6194 - assign { } { } - assign $1\upd_l_s_upd[0:0] 1'0 - sync always - sync init - update \upd_l_s_upd $1\upd_l_s_upd[0:0] - end - attribute \src "libresoc.v:130525.7-130525.25" - process $proc$libresoc.v:130525$6195 - assign { } { } - assign $1\wri_l_r_wri[0:0] 1'1 - sync always - sync init - update \wri_l_r_wri $1\wri_l_r_wri[0:0] - end - attribute \src "libresoc.v:130621.3-130622.57" - process $proc$libresoc.v:130621$6012 - assign { } { } - assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next - sync posedge \coresync_clk - update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] - end - attribute \src "libresoc.v:130623.3-130624.33" - process $proc$libresoc.v:130623$6013 - assign { } { } - assign $0\ldst_port0_addr_i[95:0] \$175 - sync posedge \coresync_clk - update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] - end - attribute \src "libresoc.v:130625.3-130626.21" - process $proc$libresoc.v:130625$6014 - assign { } { } - assign $0\alu_ok[0:0] \$96 - sync posedge \coresync_clk - update \alu_ok $0\alu_ok[0:0] - end - attribute \src "libresoc.v:130627.3-130628.25" - process $proc$libresoc.v:130627$6015 - assign { } { } - assign $0\ea_r[63:0] \ea_r$next - sync posedge \coresync_clk - update \ea_r $0\ea_r[63:0] - end - attribute \src "libresoc.v:130629.3-130630.29" - process $proc$libresoc.v:130629$6016 - assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] - end - attribute \src "libresoc.v:130631.3-130632.29" - process $proc$libresoc.v:130631$6017 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:130633.3-130634.29" - process $proc$libresoc.v:130633$6018 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:130635.3-130636.27" - process $proc$libresoc.v:130635$6019 - assign { } { } - assign $0\ldo_r[63:0] \ldo_r$next - sync posedge \coresync_clk - update \ldo_r $0\ldo_r[63:0] - end - attribute \src "libresoc.v:130637.3-130638.51" - process $proc$libresoc.v:130637$6020 - assign { } { } - assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next - sync posedge \coresync_clk - update \oper_r__insn_type $0\oper_r__insn_type[6:0] - end - attribute \src "libresoc.v:130639.3-130640.47" - process $proc$libresoc.v:130639$6021 - assign { } { } - assign $0\oper_r__fn_unit[11:0] \oper_r__fn_unit$next - sync posedge \coresync_clk - update \oper_r__fn_unit $0\oper_r__fn_unit[11:0] - end - attribute \src "libresoc.v:130641.3-130642.61" - process $proc$libresoc.v:130641$6022 - assign { } { } - assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next - sync posedge \coresync_clk - update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] - end - attribute \src "libresoc.v:130643.3-130644.57" - process $proc$libresoc.v:130643$6023 - assign { } { } - assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next - sync posedge \coresync_clk - update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] - end - attribute \src "libresoc.v:130645.3-130646.45" - process $proc$libresoc.v:130645$6024 - assign { } { } - assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next - sync posedge \coresync_clk - update \oper_r__zero_a $0\oper_r__zero_a[0:0] - end - attribute \src "libresoc.v:130647.3-130648.45" - process $proc$libresoc.v:130647$6025 - assign { } { } - assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next - sync posedge \coresync_clk - update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] - end - attribute \src "libresoc.v:130649.3-130650.45" - process $proc$libresoc.v:130649$6026 - assign { } { } - assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next - sync posedge \coresync_clk - update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] - end - attribute \src "libresoc.v:130651.3-130652.45" - process $proc$libresoc.v:130651$6027 - assign { } { } - assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next - sync posedge \coresync_clk - update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] - end - attribute \src "libresoc.v:130653.3-130654.45" - process $proc$libresoc.v:130653$6028 - assign { } { } - assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next - sync posedge \coresync_clk - update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] - end - attribute \src "libresoc.v:130655.3-130656.49" - process $proc$libresoc.v:130655$6029 - assign { } { } - assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next - sync posedge \coresync_clk - update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] - end - attribute \src "libresoc.v:130657.3-130658.51" - process $proc$libresoc.v:130657$6030 - assign { } { } - assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next - sync posedge \coresync_clk - update \oper_r__is_signed $0\oper_r__is_signed[0:0] - end - attribute \src "libresoc.v:130659.3-130660.49" - process $proc$libresoc.v:130659$6031 - assign { } { } - assign $0\oper_r__data_len[3:0] \oper_r__data_len$next - sync posedge \coresync_clk - update \oper_r__data_len $0\oper_r__data_len[3:0] - end - attribute \src "libresoc.v:130661.3-130662.57" - process $proc$libresoc.v:130661$6032 - assign { } { } - assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next - sync posedge \coresync_clk - update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] - end - attribute \src "libresoc.v:130663.3-130664.55" - process $proc$libresoc.v:130663$6033 - assign { } { } - assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next - sync posedge \coresync_clk - update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] - end - attribute \src "libresoc.v:130665.3-130666.51" - process $proc$libresoc.v:130665$6034 - assign { } { } - assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next - sync posedge \coresync_clk - update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] - end - attribute \src "libresoc.v:130667.3-130668.41" - process $proc$libresoc.v:130667$6035 - assign { } { } - assign $0\oper_r__insn[31:0] \oper_r__insn$next - sync posedge \coresync_clk - update \oper_r__insn $0\oper_r__insn[31:0] - end - attribute \src "libresoc.v:130669.3-130670.39" - process $proc$libresoc.v:130669$6036 - assign { } { } - assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next - sync posedge \coresync_clk - update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] - end - attribute \src "libresoc.v:130671.3-130672.39" - process $proc$libresoc.v:130671$6037 - assign { } { } - assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next - sync posedge \coresync_clk - update \sto_l_r_sto $0\sto_l_r_sto[0:0] - end - attribute \src "libresoc.v:130673.3-130674.39" - process $proc$libresoc.v:130673$6038 - assign { } { } - assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next - sync posedge \coresync_clk - update \upd_l_r_upd $0\upd_l_r_upd[0:0] - end - attribute \src "libresoc.v:130675.3-130676.39" - process $proc$libresoc.v:130675$6039 - assign { } { } - assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next - sync posedge \coresync_clk - update \upd_l_s_upd $0\upd_l_s_upd[0:0] - end - attribute \src "libresoc.v:130677.3-130678.39" - process $proc$libresoc.v:130677$6040 - assign { } { } - assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next - sync posedge \coresync_clk - update \wri_l_r_wri $0\wri_l_r_wri[0:0] - end - attribute \src "libresoc.v:130679.3-130680.39" - process $proc$libresoc.v:130679$6041 - assign { } { } - assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next - sync posedge \coresync_clk - update \adr_l_r_adr $0\adr_l_r_adr[0:0] - end - attribute \src "libresoc.v:130681.3-130682.39" - process $proc$libresoc.v:130681$6042 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "libresoc.v:130683.3-130684.39" - process $proc$libresoc.v:130683$6043 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "libresoc.v:130685.3-130686.39" - process $proc$libresoc.v:130685$6044 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:130687.3-130688.39" - process $proc$libresoc.v:130687$6045 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:130689.3-130690.28" - process $proc$libresoc.v:130689$6046 - assign { } { } - assign $0\p_st_go[0:0] \cu_st__go_i - sync posedge \coresync_clk - update \p_st_go $0\p_st_go[0:0] - end - attribute \src "libresoc.v:130761.3-130769.6" - process $proc$libresoc.v:130761$6047 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6048 $1\opc_l_s_opc$next[0:0]$6049 - attribute \src "libresoc.v:130762.5-130762.29" - switch \initial - attribute \src "libresoc.v:130762.9-130762.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6049 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$6049 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6048 - end - attribute \src "libresoc.v:130770.3-130778.6" - process $proc$libresoc.v:130770$6050 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6051 $1\opc_l_r_opc$next[0:0]$6052 - attribute \src "libresoc.v:130771.5-130771.29" - switch \initial - attribute \src "libresoc.v:130771.9-130771.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6052 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$6052 \reset_o - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6051 - end - attribute \src "libresoc.v:130779.3-130787.6" - process $proc$libresoc.v:130779$6053 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$6054 $1\src_l_s_src$next[2:0]$6055 - attribute \src "libresoc.v:130780.5-130780.29" - switch \initial - attribute \src "libresoc.v:130780.9-130780.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$6055 3'000 - case - assign $1\src_l_s_src$next[2:0]$6055 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6054 - end - attribute \src "libresoc.v:130788.3-130796.6" - process $proc$libresoc.v:130788$6056 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$6057 $1\src_l_r_src$next[2:0]$6058 - attribute \src "libresoc.v:130789.5-130789.29" - switch \initial - attribute \src "libresoc.v:130789.9-130789.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$6058 3'111 - case - assign $1\src_l_r_src$next[2:0]$6058 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6057 - end - attribute \src "libresoc.v:130797.3-130805.6" - process $proc$libresoc.v:130797$6059 - assign { } { } - assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6060 $1\adr_l_r_adr$next[0:0]$6061 - attribute \src "libresoc.v:130798.5-130798.29" - switch \initial - attribute \src "libresoc.v:130798.9-130798.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6061 1'1 - case - assign $1\adr_l_r_adr$next[0:0]$6061 \reset_a - end - sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6060 - end - attribute \src "libresoc.v:130806.3-130814.6" - process $proc$libresoc.v:130806$6062 - assign { } { } - assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6063 $1\wri_l_r_wri$next[0:0]$6064 - attribute \src "libresoc.v:130807.5-130807.29" - switch \initial - attribute \src "libresoc.v:130807.9-130807.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6064 1'1 - case - assign $1\wri_l_r_wri$next[0:0]$6064 \$38 [0] - end - sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6063 - end - attribute \src "libresoc.v:130815.3-130823.6" - process $proc$libresoc.v:130815$6065 - assign { } { } - assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6066 $1\upd_l_s_upd$next[0:0]$6067 - attribute \src "libresoc.v:130816.5-130816.29" - switch \initial - attribute \src "libresoc.v:130816.9-130816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6067 1'0 - case - assign $1\upd_l_s_upd$next[0:0]$6067 \reset_i - end - sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6066 - end - attribute \src "libresoc.v:130824.3-130832.6" - process $proc$libresoc.v:130824$6068 - assign { } { } - assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6069 $1\upd_l_r_upd$next[0:0]$6070 - attribute \src "libresoc.v:130825.5-130825.29" - switch \initial - attribute \src "libresoc.v:130825.9-130825.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6070 1'1 - case - assign $1\upd_l_r_upd$next[0:0]$6070 \reset_u - end - sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6069 - end - attribute \src "libresoc.v:130833.3-130841.6" - process $proc$libresoc.v:130833$6071 - assign { } { } - assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6072 $1\sto_l_r_sto$next[0:0]$6073 - attribute \src "libresoc.v:130834.5-130834.29" - switch \initial - attribute \src "libresoc.v:130834.9-130834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6073 1'1 - case - assign $1\sto_l_r_sto$next[0:0]$6073 \$59 - end - sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6072 - end - attribute \src "libresoc.v:130842.3-130850.6" - process $proc$libresoc.v:130842$6074 - assign { } { } - assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6075 $1\lsd_l_r_lsd$next[0:0]$6076 - attribute \src "libresoc.v:130843.5-130843.29" - switch \initial - attribute \src "libresoc.v:130843.9-130843.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6076 1'1 - case - assign $1\lsd_l_r_lsd$next[0:0]$6076 \$63 - end - sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6075 - end - attribute \src "libresoc.v:130851.3-130893.6" - process $proc$libresoc.v:130851$6077 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6078 $2\oper_r__byte_reverse$next[0:0]$6110 - assign $0\oper_r__data_len$next[3:0]$6079 $2\oper_r__data_len$next[3:0]$6111 - assign $0\oper_r__fn_unit$next[11:0]$6080 $2\oper_r__fn_unit$next[11:0]$6112 - assign { } { } - assign { } { } - assign $0\oper_r__insn$next[31:0]$6083 $2\oper_r__insn$next[31:0]$6115 - assign $0\oper_r__insn_type$next[6:0]$6084 $2\oper_r__insn_type$next[6:0]$6116 - assign $0\oper_r__is_32bit$next[0:0]$6085 $2\oper_r__is_32bit$next[0:0]$6117 - assign $0\oper_r__is_signed$next[0:0]$6086 $2\oper_r__is_signed$next[0:0]$6118 - assign $0\oper_r__ldst_mode$next[1:0]$6087 $2\oper_r__ldst_mode$next[1:0]$6119 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6092 $2\oper_r__sign_extend$next[0:0]$6124 - assign $0\oper_r__zero_a$next[0:0]$6093 $2\oper_r__zero_a$next[0:0]$6125 - assign $0\oper_r__imm_data__data$next[63:0]$6081 $3\oper_r__imm_data__data$next[63:0]$6126 - assign $0\oper_r__imm_data__ok$next[0:0]$6082 $3\oper_r__imm_data__ok$next[0:0]$6127 - assign $0\oper_r__oe__oe$next[0:0]$6088 $3\oper_r__oe__oe$next[0:0]$6128 - assign $0\oper_r__oe__ok$next[0:0]$6089 $3\oper_r__oe__ok$next[0:0]$6129 - assign $0\oper_r__rc__ok$next[0:0]$6090 $3\oper_r__rc__ok$next[0:0]$6130 - assign $0\oper_r__rc__rc$next[0:0]$6091 $3\oper_r__rc__rc$next[0:0]$6131 - attribute \src "libresoc.v:130852.5-130852.29" - switch \initial - attribute \src "libresoc.v:130852.9-130852.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\oper_r__insn$next[31:0]$6099 $1\oper_r__ldst_mode$next[1:0]$6103 $1\oper_r__sign_extend$next[0:0]$6108 $1\oper_r__byte_reverse$next[0:0]$6094 $1\oper_r__data_len$next[3:0]$6095 $1\oper_r__is_signed$next[0:0]$6102 $1\oper_r__is_32bit$next[0:0]$6101 $1\oper_r__oe__ok$next[0:0]$6105 $1\oper_r__oe__oe$next[0:0]$6104 $1\oper_r__rc__ok$next[0:0]$6106 $1\oper_r__rc__rc$next[0:0]$6107 $1\oper_r__zero_a$next[0:0]$6109 $1\oper_r__imm_data__ok$next[0:0]$6098 $1\oper_r__imm_data__data$next[63:0]$6097 $1\oper_r__fn_unit$next[11:0]$6096 $1\oper_r__insn_type$next[6:0]$6100 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } - case - assign $1\oper_r__byte_reverse$next[0:0]$6094 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6095 \oper_r__data_len - assign $1\oper_r__fn_unit$next[11:0]$6096 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6097 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6098 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6099 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6100 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6101 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6102 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6103 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6104 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6105 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6106 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6107 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6108 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6109 \oper_r__zero_a - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" - switch \cu_done_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\oper_r__insn$next[31:0]$6115 $2\oper_r__ldst_mode$next[1:0]$6119 $2\oper_r__sign_extend$next[0:0]$6124 $2\oper_r__byte_reverse$next[0:0]$6110 $2\oper_r__data_len$next[3:0]$6111 $2\oper_r__is_signed$next[0:0]$6118 $2\oper_r__is_32bit$next[0:0]$6117 $2\oper_r__oe__ok$next[0:0]$6121 $2\oper_r__oe__oe$next[0:0]$6120 $2\oper_r__rc__ok$next[0:0]$6122 $2\oper_r__rc__rc$next[0:0]$6123 $2\oper_r__zero_a$next[0:0]$6125 $2\oper_r__imm_data__ok$next[0:0]$6114 $2\oper_r__imm_data__data$next[63:0]$6113 $2\oper_r__fn_unit$next[11:0]$6112 $2\oper_r__insn_type$next[6:0]$6116 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\oper_r__byte_reverse$next[0:0]$6110 $1\oper_r__byte_reverse$next[0:0]$6094 - assign $2\oper_r__data_len$next[3:0]$6111 $1\oper_r__data_len$next[3:0]$6095 - assign $2\oper_r__fn_unit$next[11:0]$6112 $1\oper_r__fn_unit$next[11:0]$6096 - assign $2\oper_r__imm_data__data$next[63:0]$6113 $1\oper_r__imm_data__data$next[63:0]$6097 - assign $2\oper_r__imm_data__ok$next[0:0]$6114 $1\oper_r__imm_data__ok$next[0:0]$6098 - assign $2\oper_r__insn$next[31:0]$6115 $1\oper_r__insn$next[31:0]$6099 - assign $2\oper_r__insn_type$next[6:0]$6116 $1\oper_r__insn_type$next[6:0]$6100 - assign $2\oper_r__is_32bit$next[0:0]$6117 $1\oper_r__is_32bit$next[0:0]$6101 - assign $2\oper_r__is_signed$next[0:0]$6118 $1\oper_r__is_signed$next[0:0]$6102 - assign $2\oper_r__ldst_mode$next[1:0]$6119 $1\oper_r__ldst_mode$next[1:0]$6103 - assign $2\oper_r__oe__oe$next[0:0]$6120 $1\oper_r__oe__oe$next[0:0]$6104 - assign $2\oper_r__oe__ok$next[0:0]$6121 $1\oper_r__oe__ok$next[0:0]$6105 - assign $2\oper_r__rc__ok$next[0:0]$6122 $1\oper_r__rc__ok$next[0:0]$6106 - assign $2\oper_r__rc__rc$next[0:0]$6123 $1\oper_r__rc__rc$next[0:0]$6107 - assign $2\oper_r__sign_extend$next[0:0]$6124 $1\oper_r__sign_extend$next[0:0]$6108 - assign $2\oper_r__zero_a$next[0:0]$6125 $1\oper_r__zero_a$next[0:0]$6109 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6126 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6127 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6131 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6130 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6128 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6129 1'0 - case - assign $3\oper_r__imm_data__data$next[63:0]$6126 $2\oper_r__imm_data__data$next[63:0]$6113 - assign $3\oper_r__imm_data__ok$next[0:0]$6127 $2\oper_r__imm_data__ok$next[0:0]$6114 - assign $3\oper_r__oe__oe$next[0:0]$6128 $2\oper_r__oe__oe$next[0:0]$6120 - assign $3\oper_r__oe__ok$next[0:0]$6129 $2\oper_r__oe__ok$next[0:0]$6121 - assign $3\oper_r__rc__ok$next[0:0]$6130 $2\oper_r__rc__ok$next[0:0]$6122 - assign $3\oper_r__rc__rc$next[0:0]$6131 $2\oper_r__rc__rc$next[0:0]$6123 - end - sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6078 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6079 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$6080 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6081 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6082 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6083 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6084 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6085 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6086 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6087 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6088 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6089 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6090 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6091 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6092 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6093 - end - attribute \src "libresoc.v:130894.3-130903.6" - process $proc$libresoc.v:130894$6132 - assign { } { } - assign { } { } - assign $0\ldo_r$next[63:0]$6133 $1\ldo_r$next[63:0]$6134 - attribute \src "libresoc.v:130895.5-130895.29" - switch \initial - attribute \src "libresoc.v:130895.9-130895.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \ld_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldo_r$next[63:0]$6134 \ldd_o - case - assign $1\ldo_r$next[63:0]$6134 \ldo_r - end - sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6133 - end - attribute \src "libresoc.v:130904.3-130919.6" - process $proc$libresoc.v:130904$6135 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$6136 $2\src_r0$next[63:0]$6138 - attribute \src "libresoc.v:130905.5-130905.29" - switch \initial - attribute \src "libresoc.v:130905.9-130905.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" - switch \cu_rd__go_i [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$6137 \src1_i - case - assign $1\src_r0$next[63:0]$6137 \src_r0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src_r0$next[63:0]$6138 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\src_r0$next[63:0]$6138 $1\src_r0$next[63:0]$6137 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$6136 - end - attribute \src "libresoc.v:130920.3-130935.6" - process $proc$libresoc.v:130920$6139 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$6140 $2\src_r1$next[63:0]$6142 - attribute \src "libresoc.v:130921.5-130921.29" - switch \initial - attribute \src "libresoc.v:130921.9-130921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" - switch \cu_rd__go_i [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$6141 \src2_i - case - assign $1\src_r1$next[63:0]$6141 \src_r1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src_r1$next[63:0]$6142 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\src_r1$next[63:0]$6142 $1\src_r1$next[63:0]$6141 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$6140 - end - attribute \src "libresoc.v:130936.3-130951.6" - process $proc$libresoc.v:130936$6143 - assign { } { } - assign { } { } - assign { } { } - assign $0\src_r2$next[63:0]$6144 $2\src_r2$next[63:0]$6146 - attribute \src "libresoc.v:130937.5-130937.29" - switch \initial - attribute \src "libresoc.v:130937.9-130937.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" - switch \cu_rd__go_i [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[63:0]$6145 \src3_i - case - assign $1\src_r2$next[63:0]$6145 \src_r2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src_r2$next[63:0]$6146 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\src_r2$next[63:0]$6146 $1\src_r2$next[63:0]$6145 - end - sync always - update \src_r2$next $0\src_r2$next[63:0]$6144 - end - attribute \src "libresoc.v:130952.3-130961.6" - process $proc$libresoc.v:130952$6147 - assign { } { } - assign { } { } - assign $0\ea_r$next[63:0]$6148 $1\ea_r$next[63:0]$6149 - attribute \src "libresoc.v:130953.5-130953.29" - switch \initial - attribute \src "libresoc.v:130953.9-130953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \alu_l_q_alu - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ea_r$next[63:0]$6149 \alu_o - case - assign $1\ea_r$next[63:0]$6149 \ea_r - end - sync always - update \ea_r$next $0\ea_r$next[63:0]$6148 - end - attribute \src "libresoc.v:130962.3-130971.6" - process $proc$libresoc.v:130962$6150 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:130963.5-130963.29" - switch \initial - attribute \src "libresoc.v:130963.9-130963.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" - switch \cu_wr__go_i [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \ldd_r - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:130972.3-130981.6" - process $proc$libresoc.v:130972$6151 - assign { } { } - assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:130973.5-130973.29" - switch \initial - attribute \src "libresoc.v:130973.9-130973.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - switch \$164 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[63:0] \addr_r - case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest2_o $0\dest2_o[63:0] - end - attribute \src "libresoc.v:130982.3-130990.6" - process $proc$libresoc.v:130982$6152 - assign { } { } - assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6153 $1\ldst_port0_addr_i_ok$next[0:0]$6154 - attribute \src "libresoc.v:130983.5-130983.29" - switch \initial - attribute \src "libresoc.v:130983.9-130983.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6154 1'0 - case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6154 \$177 - end - sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6153 - end - attribute \src "libresoc.v:130991.3-131014.6" - process $proc$libresoc.v:130991$6155 - assign { } { } - assign { } { } - assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:130992.5-130992.29" - switch \initial - attribute \src "libresoc.v:130992.9-130992.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" - switch \oper_r__byte_reverse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\lddata_r[63:0] $2\lddata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" - switch \oper_r__data_len - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $2\lddata_r[63:0] \$186 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $2\lddata_r[63:0] \$188 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $2\lddata_r[63:0] \$190 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } - case - assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \lddata_r $0\lddata_r[63:0] - end - attribute \src "libresoc.v:131015.3-131026.6" - process $proc$libresoc.v:131015$6156 - assign { } { } - assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:131016.5-131016.29" - switch \initial - attribute \src "libresoc.v:131016.9-131016.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" - switch \oper_r__byte_reverse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\revnorev[63:0] \lddata_r - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\revnorev[63:0] \ldst_port0_ld_data_o - end - sync always - update \revnorev $0\revnorev[63:0] - end - attribute \src "libresoc.v:131027.3-131046.6" - process $proc$libresoc.v:131027$6157 - assign { } { } - assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:131028.5-131028.29" - switch \initial - attribute \src "libresoc.v:131028.9-131028.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" - switch \oper_r__sign_extend - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldd_o[63:0] $2\ldd_o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - switch \$192 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ldd_o[63:0] \revnorev - end - sync always - update \ldd_o $0\ldd_o[63:0] - end - attribute \src "libresoc.v:131047.3-131070.6" - process $proc$libresoc.v:131047$6158 - assign { } { } - assign { } { } - assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:131048.5-131048.29" - switch \initial - attribute \src "libresoc.v:131048.9-131048.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" - switch \oper_r__byte_reverse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\stdata_r[63:0] $2\stdata_r[63:0] - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" - switch \oper_r__data_len - attribute \src "libresoc.v:0.0-0.0" - case 4'0001 - assign { } { } - assign $2\stdata_r[63:0] \$194 - attribute \src "libresoc.v:0.0-0.0" - case 4'0010 - assign { } { } - assign $2\stdata_r[63:0] \$196 - attribute \src "libresoc.v:0.0-0.0" - case 4'0100 - assign { } { } - assign $2\stdata_r[63:0] \$198 - attribute \src "libresoc.v:0.0-0.0" - case 4'1000 - assign { } { } - assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } - case - assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \stdata_r $0\stdata_r[63:0] - end - attribute \src "libresoc.v:131071.3-131082.6" - process $proc$libresoc.v:131071$6159 - assign { } { } - assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:131072.5-131072.29" - switch \initial - attribute \src "libresoc.v:131072.9-131072.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" - switch \oper_r__byte_reverse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_st_data_i[63:0] \stdata_r - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ldst_port0_st_data_i[63:0] \src_r2 - end - sync always - update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] - end - connect \$100 $and$libresoc.v:130530$5918_Y - connect \$102 $and$libresoc.v:130531$5919_Y - connect \$104 $and$libresoc.v:130532$5920_Y - connect \$106 $and$libresoc.v:130533$5921_Y - connect \$108 $and$libresoc.v:130534$5922_Y - connect \$10 $or$libresoc.v:130535$5923_Y - connect \$110 $and$libresoc.v:130536$5924_Y - connect \$112 $and$libresoc.v:130537$5925_Y - connect \$114 $and$libresoc.v:130538$5926_Y - connect \$116 $and$libresoc.v:130539$5927_Y - connect \$118 $and$libresoc.v:130540$5928_Y - connect \$120 $and$libresoc.v:130541$5929_Y - connect \$122 $and$libresoc.v:130542$5930_Y - connect \$124 $and$libresoc.v:130543$5931_Y - connect \$126 $eq$libresoc.v:130544$5932_Y - connect \$128 $and$libresoc.v:130545$5933_Y - connect \$12 $or$libresoc.v:130546$5934_Y - connect \$130 $and$libresoc.v:130547$5935_Y - connect \$132 $and$libresoc.v:130548$5936_Y - connect \$134 $or$libresoc.v:130549$5937_Y - connect \$136 $or$libresoc.v:130550$5938_Y - connect \$138 $or$libresoc.v:130551$5939_Y - connect \$140 $and$libresoc.v:130552$5940_Y - connect \$142 $and$libresoc.v:130553$5941_Y - connect \$145 $or$libresoc.v:130554$5942_Y - connect \$147 $or$libresoc.v:130555$5943_Y - connect \$144 $not$libresoc.v:130556$5944_Y - connect \$14 $or$libresoc.v:130557$5945_Y - connect \$150 $and$libresoc.v:130558$5946_Y - connect \$152 $or$libresoc.v:130559$5947_Y - connect \$154 $and$libresoc.v:130560$5948_Y - connect \$156 $not$libresoc.v:130561$5949_Y - connect \$158 $or$libresoc.v:130562$5950_Y - connect \$160 $and$libresoc.v:130563$5951_Y - connect \$162 $eq$libresoc.v:130564$5952_Y - connect \$164 $and$libresoc.v:130565$5953_Y - connect \$167 $eq$libresoc.v:130566$5954_Y - connect \$16 $or$libresoc.v:130567$5955_Y - connect \$169 $and$libresoc.v:130568$5956_Y - connect \$171 $and$libresoc.v:130569$5957_Y - connect \$173 $and$libresoc.v:130570$5958_Y - connect \$175 $pos$libresoc.v:130571$5960_Y - connect \$177 $and$libresoc.v:130572$5961_Y - connect \$186 $pos$libresoc.v:130573$5963_Y - connect \$188 $pos$libresoc.v:130574$5964_Y - connect \$18 $or$libresoc.v:130575$5965_Y - connect \$190 $pos$libresoc.v:130576$5966_Y - connect \$192 $eq$libresoc.v:130577$5967_Y - connect \$194 $pos$libresoc.v:130578$5969_Y - connect \$196 $pos$libresoc.v:130579$5970_Y - connect \$198 $pos$libresoc.v:130580$5971_Y - connect \$20 $or$libresoc.v:130581$5972_Y - connect \$22 $eq$libresoc.v:130582$5973_Y - connect \$24 $eq$libresoc.v:130583$5974_Y - connect \$26 $and$libresoc.v:130584$5975_Y - connect \$28 $and$libresoc.v:130585$5976_Y - connect \$30 $not$libresoc.v:130586$5977_Y - connect \$32 $and$libresoc.v:130587$5978_Y - connect \$34 $not$libresoc.v:130588$5979_Y - connect \$36 $and$libresoc.v:130589$5980_Y - connect \$39 $not$libresoc.v:130590$5981_Y - connect \$41 $eq$libresoc.v:130591$5982_Y - connect \$43 $and$libresoc.v:130592$5983_Y - connect \$45 $or$libresoc.v:130593$5984_Y - connect \$47 $not$libresoc.v:130594$5985_Y - connect \$49 $eq$libresoc.v:130595$5986_Y - connect \$51 $and$libresoc.v:130596$5987_Y - connect \$53 $or$libresoc.v:130597$5988_Y - connect \$55 $or$libresoc.v:130598$5989_Y - connect \$57 $and$libresoc.v:130599$5990_Y - connect \$59 $or$libresoc.v:130600$5991_Y - connect \$61 $or$libresoc.v:130601$5992_Y - connect \$63 $or$libresoc.v:130602$5993_Y - connect \$65 $ternary$libresoc.v:130603$5994_Y - connect \$67 $ternary$libresoc.v:130604$5995_Y - connect \$69 $ternary$libresoc.v:130605$5996_Y - connect \$71 $ternary$libresoc.v:130606$5997_Y - connect \$74 $add$libresoc.v:130607$5998_Y - connect \$76 $and$libresoc.v:130608$5999_Y - connect \$78 $not$libresoc.v:130609$6000_Y - connect \$80 $and$libresoc.v:130610$6001_Y - connect \$82 $not$libresoc.v:130611$6002_Y - connect \$84 $and$libresoc.v:130612$6003_Y - connect \$86 $and$libresoc.v:130613$6004_Y - connect \$88 $and$libresoc.v:130614$6005_Y - connect \$8 $or$libresoc.v:130615$6006_Y - connect \$90 $or$libresoc.v:130616$6007_Y - connect \$93 $or$libresoc.v:130617$6008_Y - connect \$92 $not$libresoc.v:130618$6009_Y - connect \$96 $and$libresoc.v:130619$6010_Y - connect \$98 $not$libresoc.v:130620$6011_Y - connect \$38 \$55 - connect \$73 \$74 - connect \$166 \$169 - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \ldst_port0_st_data_i_ok \cu_st__go_i - connect \ld_ok \ldst_port0_ld_data_o_ok - connect \addr_ok \ldst_port0_addr_ok_o - connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } - connect \ldst_port0_addr_i$next \$175 - connect \ldst_port0_data_len \oper_r__data_len - connect \ldst_port0_is_st_i \$173 - connect \ldst_port0_is_ld_i \$171 - connect \cu_wrmask_o \$169 [1:0] - connect \ea \dest2_o - connect \o \dest1_o - connect \cu_done_o \$160 - connect \wr_reset \$154 - connect \wr_any \$138 - connect \cu_wr__rel_o [1] \$132 - connect \cu_wr__rel_o [0] \$122 - connect \cu_st__rel_o \$112 - connect \cu_ad__rel_o \$104 - connect \rd_done \$100 - connect \alu_valid \$96 - connect \rda_any \$90 - connect \cu_rd__rel_o [2] \$88 - connect \cu_rd__rel_o [1:0] \$84 [1:0] - connect \cu_busy_o \opc_l_q_opc - connect \alu_ok$next \alu_valid - connect \alu_o \$74 [63:0] - connect \src2_or_imm \$71 - connect \src1_or_z \$69 - connect \addr_r \$67 - connect \ldd_r \$65 - connect \rst_l_r_rst \cu_issue_i - connect \rst_l_s_rst \addr_ok - connect \lsd_l_s_lsd \cu_issue_i - connect \sto_l_s_sto \$57 - connect \wri_l_s_wri \cu_issue_i - connect \lod_l_r_lod \ld_ok - connect \lod_l_s_lod \reset_i - connect \adr_l_s_adr \reset_i - connect \alu_l_r_alu \$36 - connect \alu_l_s_alu \reset_i - connect \st_o \op_is_st - connect \ld_o \op_is_ld - connect \stwd_mem_o \$28 - connect \load_mem_o \$26 - connect \op_is_ld \$24 - connect \op_is_st \$22 - connect \p_st_go$next \cu_st__go_i - connect \reset_a \$20 - connect \reset_r \$18 - connect \reset_s \$16 - connect \reset_u \$14 - connect \reset_w \$12 - connect \reset_o \$10 - connect \reset_i \$8 -end -attribute \src "libresoc.v:131146.1-131733.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" -attribute \generator "nMigen" -module \left_mask - attribute \src "libresoc.v:131147.7-131147.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:131345.3-131732.6" - wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:131345.3-131732.6" - wire $10\mask[9:9] - attribute \src "libresoc.v:131345.3-131732.6" - wire $11\mask[10:10] - attribute \src "libresoc.v:131345.3-131732.6" - wire $12\mask[11:11] - attribute \src "libresoc.v:131345.3-131732.6" - wire $13\mask[12:12] - attribute \src "libresoc.v:131345.3-131732.6" - wire $14\mask[13:13] - attribute \src "libresoc.v:131345.3-131732.6" - wire $15\mask[14:14] - attribute \src "libresoc.v:131345.3-131732.6" - wire $16\mask[15:15] - attribute \src "libresoc.v:131345.3-131732.6" - wire $17\mask[16:16] - attribute \src "libresoc.v:131345.3-131732.6" - wire $18\mask[17:17] - attribute \src "libresoc.v:131345.3-131732.6" - wire $19\mask[18:18] - attribute \src "libresoc.v:131345.3-131732.6" - wire $1\mask[0:0] - attribute \src "libresoc.v:131345.3-131732.6" - wire $20\mask[19:19] - attribute \src "libresoc.v:131345.3-131732.6" - wire $21\mask[20:20] - attribute \src "libresoc.v:131345.3-131732.6" - wire $22\mask[21:21] - attribute \src "libresoc.v:131345.3-131732.6" - wire $23\mask[22:22] - attribute \src "libresoc.v:131345.3-131732.6" - wire $24\mask[23:23] - attribute \src "libresoc.v:131345.3-131732.6" - wire $25\mask[24:24] - attribute \src "libresoc.v:131345.3-131732.6" - wire $26\mask[25:25] - attribute \src "libresoc.v:131345.3-131732.6" - wire $27\mask[26:26] - attribute \src "libresoc.v:131345.3-131732.6" - wire $28\mask[27:27] - attribute \src "libresoc.v:131345.3-131732.6" - wire $29\mask[28:28] - attribute \src "libresoc.v:131345.3-131732.6" - wire $2\mask[1:1] - attribute \src "libresoc.v:131345.3-131732.6" - wire $30\mask[29:29] - attribute \src "libresoc.v:131345.3-131732.6" - wire $31\mask[30:30] - attribute \src "libresoc.v:131345.3-131732.6" - wire $32\mask[31:31] - attribute \src "libresoc.v:131345.3-131732.6" - wire $33\mask[32:32] - attribute \src "libresoc.v:131345.3-131732.6" - wire $34\mask[33:33] - attribute \src "libresoc.v:131345.3-131732.6" - wire $35\mask[34:34] - attribute \src "libresoc.v:131345.3-131732.6" - wire $36\mask[35:35] - attribute \src "libresoc.v:131345.3-131732.6" - wire $37\mask[36:36] - attribute \src "libresoc.v:131345.3-131732.6" - wire $38\mask[37:37] - attribute \src "libresoc.v:131345.3-131732.6" - wire $39\mask[38:38] - attribute \src "libresoc.v:131345.3-131732.6" - wire $3\mask[2:2] - attribute \src "libresoc.v:131345.3-131732.6" - wire $40\mask[39:39] - attribute \src "libresoc.v:131345.3-131732.6" - wire $41\mask[40:40] - attribute \src "libresoc.v:131345.3-131732.6" - wire $42\mask[41:41] - attribute \src "libresoc.v:131345.3-131732.6" - wire $43\mask[42:42] - attribute \src "libresoc.v:131345.3-131732.6" - wire $44\mask[43:43] - attribute \src "libresoc.v:131345.3-131732.6" - wire $45\mask[44:44] - attribute \src "libresoc.v:131345.3-131732.6" - wire $46\mask[45:45] - attribute \src "libresoc.v:131345.3-131732.6" - wire $47\mask[46:46] - attribute \src "libresoc.v:131345.3-131732.6" - wire $48\mask[47:47] - attribute \src "libresoc.v:131345.3-131732.6" - wire $49\mask[48:48] - attribute \src "libresoc.v:131345.3-131732.6" - wire $4\mask[3:3] - attribute \src "libresoc.v:131345.3-131732.6" - wire $50\mask[49:49] - attribute \src "libresoc.v:131345.3-131732.6" - wire $51\mask[50:50] - attribute \src "libresoc.v:131345.3-131732.6" - wire $52\mask[51:51] - attribute \src "libresoc.v:131345.3-131732.6" - wire $53\mask[52:52] - attribute \src "libresoc.v:131345.3-131732.6" - wire $54\mask[53:53] - attribute \src "libresoc.v:131345.3-131732.6" - wire $55\mask[54:54] - attribute \src "libresoc.v:131345.3-131732.6" - wire $56\mask[55:55] - attribute \src "libresoc.v:131345.3-131732.6" - wire $57\mask[56:56] - attribute \src "libresoc.v:131345.3-131732.6" - wire $58\mask[57:57] - attribute \src "libresoc.v:131345.3-131732.6" - wire $59\mask[58:58] - attribute \src "libresoc.v:131345.3-131732.6" - wire $5\mask[4:4] - attribute \src "libresoc.v:131345.3-131732.6" - wire $60\mask[59:59] - attribute \src "libresoc.v:131345.3-131732.6" - wire $61\mask[60:60] - attribute \src "libresoc.v:131345.3-131732.6" - wire $62\mask[61:61] - attribute \src "libresoc.v:131345.3-131732.6" - wire $63\mask[62:62] - attribute \src "libresoc.v:131345.3-131732.6" - wire $64\mask[63:63] - attribute \src "libresoc.v:131345.3-131732.6" - wire $6\mask[5:5] - attribute \src "libresoc.v:131345.3-131732.6" - wire $7\mask[6:6] - attribute \src "libresoc.v:131345.3-131732.6" - wire $8\mask[7:7] - attribute \src "libresoc.v:131345.3-131732.6" - wire $9\mask[8:8] - attribute \src "libresoc.v:131281.17-131281.96" - wire $gt$libresoc.v:131281$6196_Y - attribute \src "libresoc.v:131282.18-131282.98" - wire $gt$libresoc.v:131282$6197_Y - attribute \src "libresoc.v:131283.19-131283.99" - wire $gt$libresoc.v:131283$6198_Y - attribute \src "libresoc.v:131284.19-131284.99" - wire $gt$libresoc.v:131284$6199_Y - attribute \src "libresoc.v:131285.19-131285.99" - wire $gt$libresoc.v:131285$6200_Y - attribute \src "libresoc.v:131286.19-131286.99" - wire $gt$libresoc.v:131286$6201_Y - attribute \src "libresoc.v:131287.19-131287.99" - wire $gt$libresoc.v:131287$6202_Y - attribute \src "libresoc.v:131288.19-131288.99" - wire $gt$libresoc.v:131288$6203_Y - attribute \src "libresoc.v:131289.19-131289.99" - wire $gt$libresoc.v:131289$6204_Y - attribute \src "libresoc.v:131290.19-131290.99" - wire $gt$libresoc.v:131290$6205_Y - attribute \src "libresoc.v:131291.19-131291.99" - wire $gt$libresoc.v:131291$6206_Y - attribute \src "libresoc.v:131292.18-131292.97" - wire $gt$libresoc.v:131292$6207_Y - attribute \src "libresoc.v:131293.19-131293.99" - wire $gt$libresoc.v:131293$6208_Y - attribute \src "libresoc.v:131294.19-131294.99" - wire $gt$libresoc.v:131294$6209_Y - attribute \src "libresoc.v:131295.19-131295.99" - wire $gt$libresoc.v:131295$6210_Y - attribute \src "libresoc.v:131296.19-131296.99" - wire $gt$libresoc.v:131296$6211_Y - attribute \src "libresoc.v:131297.19-131297.99" - wire $gt$libresoc.v:131297$6212_Y - attribute \src "libresoc.v:131298.18-131298.97" - wire $gt$libresoc.v:131298$6213_Y - attribute \src "libresoc.v:131299.18-131299.97" - wire $gt$libresoc.v:131299$6214_Y - attribute \src "libresoc.v:131300.18-131300.97" - wire $gt$libresoc.v:131300$6215_Y - attribute \src "libresoc.v:131301.17-131301.96" - wire $gt$libresoc.v:131301$6216_Y - attribute \src "libresoc.v:131302.18-131302.97" - wire $gt$libresoc.v:131302$6217_Y - attribute \src "libresoc.v:131303.18-131303.97" - wire $gt$libresoc.v:131303$6218_Y - attribute \src "libresoc.v:131304.18-131304.97" - wire $gt$libresoc.v:131304$6219_Y - attribute \src "libresoc.v:131305.18-131305.97" - wire $gt$libresoc.v:131305$6220_Y - attribute \src "libresoc.v:131306.18-131306.97" - wire $gt$libresoc.v:131306$6221_Y - attribute \src "libresoc.v:131307.18-131307.97" - wire $gt$libresoc.v:131307$6222_Y - attribute \src "libresoc.v:131308.18-131308.97" - wire $gt$libresoc.v:131308$6223_Y - attribute \src "libresoc.v:131309.18-131309.98" - wire $gt$libresoc.v:131309$6224_Y - attribute \src "libresoc.v:131310.18-131310.98" - wire $gt$libresoc.v:131310$6225_Y - attribute \src "libresoc.v:131311.18-131311.98" - wire $gt$libresoc.v:131311$6226_Y - attribute \src "libresoc.v:131312.17-131312.96" - wire $gt$libresoc.v:131312$6227_Y - attribute \src "libresoc.v:131313.18-131313.98" - wire $gt$libresoc.v:131313$6228_Y - attribute \src "libresoc.v:131314.18-131314.98" - wire $gt$libresoc.v:131314$6229_Y - attribute \src "libresoc.v:131315.18-131315.98" - wire $gt$libresoc.v:131315$6230_Y - attribute \src "libresoc.v:131316.18-131316.98" - wire $gt$libresoc.v:131316$6231_Y - attribute \src "libresoc.v:131317.18-131317.98" - wire $gt$libresoc.v:131317$6232_Y - attribute \src "libresoc.v:131318.18-131318.98" - wire $gt$libresoc.v:131318$6233_Y - attribute \src "libresoc.v:131319.18-131319.98" - wire $gt$libresoc.v:131319$6234_Y - attribute \src "libresoc.v:131320.18-131320.98" - wire $gt$libresoc.v:131320$6235_Y - attribute \src "libresoc.v:131321.18-131321.98" - wire $gt$libresoc.v:131321$6236_Y - attribute \src "libresoc.v:131322.18-131322.98" - wire $gt$libresoc.v:131322$6237_Y - attribute \src "libresoc.v:131323.17-131323.96" - wire $gt$libresoc.v:131323$6238_Y - attribute \src "libresoc.v:131324.18-131324.98" - wire $gt$libresoc.v:131324$6239_Y - attribute \src "libresoc.v:131325.18-131325.98" - wire $gt$libresoc.v:131325$6240_Y - attribute \src "libresoc.v:131326.18-131326.98" - wire $gt$libresoc.v:131326$6241_Y - attribute \src "libresoc.v:131327.18-131327.98" - wire $gt$libresoc.v:131327$6242_Y - attribute \src "libresoc.v:131328.18-131328.98" - wire $gt$libresoc.v:131328$6243_Y - attribute \src "libresoc.v:131329.18-131329.98" - wire $gt$libresoc.v:131329$6244_Y - attribute \src "libresoc.v:131330.18-131330.98" - wire $gt$libresoc.v:131330$6245_Y - attribute \src "libresoc.v:131331.18-131331.98" - wire $gt$libresoc.v:131331$6246_Y - attribute \src "libresoc.v:131332.18-131332.98" - wire $gt$libresoc.v:131332$6247_Y - attribute \src "libresoc.v:131333.18-131333.98" - wire $gt$libresoc.v:131333$6248_Y - attribute \src "libresoc.v:131334.17-131334.96" - wire $gt$libresoc.v:131334$6249_Y - attribute \src "libresoc.v:131335.18-131335.98" - wire $gt$libresoc.v:131335$6250_Y - attribute \src "libresoc.v:131336.18-131336.98" - wire $gt$libresoc.v:131336$6251_Y - attribute \src "libresoc.v:131337.18-131337.98" - wire $gt$libresoc.v:131337$6252_Y - attribute \src "libresoc.v:131338.18-131338.98" - wire $gt$libresoc.v:131338$6253_Y - attribute \src "libresoc.v:131339.18-131339.98" - wire $gt$libresoc.v:131339$6254_Y - attribute \src "libresoc.v:131340.18-131340.98" - wire $gt$libresoc.v:131340$6255_Y - attribute \src "libresoc.v:131341.18-131341.98" - wire $gt$libresoc.v:131341$6256_Y - attribute \src "libresoc.v:131342.18-131342.98" - wire $gt$libresoc.v:131342$6257_Y - attribute \src "libresoc.v:131343.18-131343.98" - wire $gt$libresoc.v:131343$6258_Y - attribute \src "libresoc.v:131344.18-131344.98" - wire $gt$libresoc.v:131344$6259_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$99 - attribute \src "libresoc.v:131147.7-131147.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" - wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" - wire width 7 input 2 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131281$6196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'100 - connect \Y $gt$libresoc.v:131281$6196_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131282$6197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110001 - connect \Y $gt$libresoc.v:131282$6197_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131283$6198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110010 - connect \Y $gt$libresoc.v:131283$6198_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131284$6199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110011 - connect \Y $gt$libresoc.v:131284$6199_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131285$6200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110100 - connect \Y $gt$libresoc.v:131285$6200_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131286$6201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110101 - connect \Y $gt$libresoc.v:131286$6201_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131287$6202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110110 - connect \Y $gt$libresoc.v:131287$6202_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131288$6203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110111 - connect \Y $gt$libresoc.v:131288$6203_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131289$6204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111000 - connect \Y $gt$libresoc.v:131289$6204_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131290$6205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111001 - connect \Y $gt$libresoc.v:131290$6205_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131291$6206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111010 - connect \Y $gt$libresoc.v:131291$6206_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131292$6207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'101 - connect \Y $gt$libresoc.v:131292$6207_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131293$6208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111011 - connect \Y $gt$libresoc.v:131293$6208_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131294$6209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111100 - connect \Y $gt$libresoc.v:131294$6209_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131295$6210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111101 - connect \Y $gt$libresoc.v:131295$6210_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131296$6211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111110 - connect \Y $gt$libresoc.v:131296$6211_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131297$6212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111111 - connect \Y $gt$libresoc.v:131297$6212_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131298$6213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'110 - connect \Y $gt$libresoc.v:131298$6213_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131299$6214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'111 - connect \Y $gt$libresoc.v:131299$6214_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131300$6215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1000 - connect \Y $gt$libresoc.v:131300$6215_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131301$6216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'0 - connect \Y $gt$libresoc.v:131301$6216_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131302$6217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1001 - connect \Y $gt$libresoc.v:131302$6217_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131303$6218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1010 - connect \Y $gt$libresoc.v:131303$6218_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131304$6219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1011 - connect \Y $gt$libresoc.v:131304$6219_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131305$6220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1100 - connect \Y $gt$libresoc.v:131305$6220_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131306$6221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1101 - connect \Y $gt$libresoc.v:131306$6221_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131307$6222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1110 - connect \Y $gt$libresoc.v:131307$6222_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131308$6223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1111 - connect \Y $gt$libresoc.v:131308$6223_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131309$6224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10000 - connect \Y $gt$libresoc.v:131309$6224_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131310$6225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10001 - connect \Y $gt$libresoc.v:131310$6225_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131311$6226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10010 - connect \Y $gt$libresoc.v:131311$6226_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131312$6227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'1 - connect \Y $gt$libresoc.v:131312$6227_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131313$6228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10011 - connect \Y $gt$libresoc.v:131313$6228_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131314$6229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10100 - connect \Y $gt$libresoc.v:131314$6229_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131315$6230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10101 - connect \Y $gt$libresoc.v:131315$6230_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131316$6231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10110 - connect \Y $gt$libresoc.v:131316$6231_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131317$6232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10111 - connect \Y $gt$libresoc.v:131317$6232_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131318$6233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11000 - connect \Y $gt$libresoc.v:131318$6233_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131319$6234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11001 - connect \Y $gt$libresoc.v:131319$6234_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131320$6235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11010 - connect \Y $gt$libresoc.v:131320$6235_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131321$6236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11011 - connect \Y $gt$libresoc.v:131321$6236_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131322$6237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11100 - connect \Y $gt$libresoc.v:131322$6237_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131323$6238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'10 - connect \Y $gt$libresoc.v:131323$6238_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131324$6239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11101 - connect \Y $gt$libresoc.v:131324$6239_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131325$6240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11110 - connect \Y $gt$libresoc.v:131325$6240_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131326$6241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11111 - connect \Y $gt$libresoc.v:131326$6241_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131327$6242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100000 - connect \Y $gt$libresoc.v:131327$6242_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131328$6243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100001 - connect \Y $gt$libresoc.v:131328$6243_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131329$6244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100010 - connect \Y $gt$libresoc.v:131329$6244_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131330$6245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100011 - connect \Y $gt$libresoc.v:131330$6245_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131331$6246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100100 - connect \Y $gt$libresoc.v:131331$6246_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131332$6247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100101 - connect \Y $gt$libresoc.v:131332$6247_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131333$6248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100110 - connect \Y $gt$libresoc.v:131333$6248_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131334$6249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'11 - connect \Y $gt$libresoc.v:131334$6249_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131335$6250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100111 - connect \Y $gt$libresoc.v:131335$6250_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131336$6251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101000 - connect \Y $gt$libresoc.v:131336$6251_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131337$6252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101001 - connect \Y $gt$libresoc.v:131337$6252_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131338$6253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101010 - connect \Y $gt$libresoc.v:131338$6253_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131339$6254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101011 - connect \Y $gt$libresoc.v:131339$6254_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131340$6255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101100 - connect \Y $gt$libresoc.v:131340$6255_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131341$6256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101101 - connect \Y $gt$libresoc.v:131341$6256_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131342$6257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101110 - connect \Y $gt$libresoc.v:131342$6257_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131343$6258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101111 - connect \Y $gt$libresoc.v:131343$6258_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:131344$6259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110000 - connect \Y $gt$libresoc.v:131344$6259_Y - end - attribute \src "libresoc.v:131147.7-131147.20" - process $proc$libresoc.v:131147$6261 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:131345.3-131732.6" - process $proc$libresoc.v:131345$6260 - assign { } { } - assign { } { } - assign $0\mask[63:0] [0] $1\mask[0:0] - assign $0\mask[63:0] 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assign $0\mask[63:0] [25] $26\mask[25:25] - assign $0\mask[63:0] [26] $27\mask[26:26] - assign $0\mask[63:0] [27] $28\mask[27:27] - assign $0\mask[63:0] [28] $29\mask[28:28] - assign $0\mask[63:0] [29] $30\mask[29:29] - assign $0\mask[63:0] [30] $31\mask[30:30] - assign $0\mask[63:0] [31] $32\mask[31:31] - assign $0\mask[63:0] [32] $33\mask[32:32] - assign $0\mask[63:0] [33] $34\mask[33:33] - assign $0\mask[63:0] [34] $35\mask[34:34] - assign $0\mask[63:0] [35] $36\mask[35:35] - assign $0\mask[63:0] [36] $37\mask[36:36] - assign $0\mask[63:0] [37] $38\mask[37:37] - assign $0\mask[63:0] [38] $39\mask[38:38] - assign $0\mask[63:0] [39] $40\mask[39:39] - assign $0\mask[63:0] [40] $41\mask[40:40] - assign $0\mask[63:0] [41] $42\mask[41:41] - assign $0\mask[63:0] [42] $43\mask[42:42] - assign $0\mask[63:0] [43] $44\mask[43:43] - assign $0\mask[63:0] [44] $45\mask[44:44] - assign $0\mask[63:0] [45] $46\mask[45:45] - assign $0\mask[63:0] [46] $47\mask[46:46] - assign $0\mask[63:0] [47] $48\mask[47:47] - assign $0\mask[63:0] [48] $49\mask[48:48] - assign $0\mask[63:0] [49] $50\mask[49:49] - assign $0\mask[63:0] [50] $51\mask[50:50] - assign $0\mask[63:0] [51] $52\mask[51:51] - assign $0\mask[63:0] [52] $53\mask[52:52] - assign $0\mask[63:0] [53] $54\mask[53:53] - assign $0\mask[63:0] [54] $55\mask[54:54] - assign $0\mask[63:0] [55] $56\mask[55:55] - assign $0\mask[63:0] [56] $57\mask[56:56] - assign $0\mask[63:0] [57] $58\mask[57:57] - assign $0\mask[63:0] [58] $59\mask[58:58] - assign $0\mask[63:0] [59] $60\mask[59:59] - assign $0\mask[63:0] [60] $61\mask[60:60] - assign $0\mask[63:0] [61] $62\mask[61:61] - assign $0\mask[63:0] [62] $63\mask[62:62] - assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:131346.5-131346.29" - switch \initial - attribute \src "libresoc.v:131346.9-131346.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\mask[0:0] 1'1 - case - assign $1\mask[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mask[1:1] 1'1 - case - assign $2\mask[1:1] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$5 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\mask[2:2] 1'1 - case - assign $3\mask[2:2] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\mask[3:3] 1'1 - case - assign $4\mask[3:3] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\mask[4:4] 1'1 - case - assign $5\mask[4:4] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\mask[5:5] 1'1 - case - assign $6\mask[5:5] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\mask[6:6] 1'1 - case - assign $7\mask[6:6] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\mask[7:7] 1'1 - case - assign $8\mask[7:7] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\mask[8:8] 1'1 - case - assign $9\mask[8:8] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\mask[9:9] 1'1 - case - assign $10\mask[9:9] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $11\mask[10:10] 1'1 - case - assign $11\mask[10:10] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $12\mask[11:11] 1'1 - case - assign $12\mask[11:11] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$25 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $13\mask[12:12] 1'1 - case - assign $13\mask[12:12] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $14\mask[13:13] 1'1 - case - assign $14\mask[13:13] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$29 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\mask[14:14] 1'1 - case - assign $15\mask[14:14] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$31 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $16\mask[15:15] 1'1 - case - assign $16\mask[15:15] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $17\mask[16:16] 1'1 - case - assign $17\mask[16:16] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$35 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $18\mask[17:17] 1'1 - case - assign $18\mask[17:17] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$37 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $19\mask[18:18] 1'1 - case - assign $19\mask[18:18] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$39 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $20\mask[19:19] 1'1 - case - assign $20\mask[19:19] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$41 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $21\mask[20:20] 1'1 - case - assign $21\mask[20:20] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$43 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $22\mask[21:21] 1'1 - case - assign $22\mask[21:21] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$45 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $23\mask[22:22] 1'1 - case - assign $23\mask[22:22] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$47 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $24\mask[23:23] 1'1 - case - assign $24\mask[23:23] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$49 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $25\mask[24:24] 1'1 - case - assign $25\mask[24:24] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$51 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $26\mask[25:25] 1'1 - case - assign $26\mask[25:25] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$53 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $27\mask[26:26] 1'1 - case - assign $27\mask[26:26] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $28\mask[27:27] 1'1 - case - assign $28\mask[27:27] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$57 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $29\mask[28:28] 1'1 - case - assign $29\mask[28:28] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$59 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $30\mask[29:29] 1'1 - case - assign $30\mask[29:29] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$61 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $31\mask[30:30] 1'1 - case - assign $31\mask[30:30] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $32\mask[31:31] 1'1 - case - assign $32\mask[31:31] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$65 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $33\mask[32:32] 1'1 - case - assign $33\mask[32:32] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$67 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $34\mask[33:33] 1'1 - case - assign $34\mask[33:33] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $35\mask[34:34] 1'1 - case - assign $35\mask[34:34] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $36\mask[35:35] 1'1 - case - assign $36\mask[35:35] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$73 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $37\mask[36:36] 1'1 - case - assign $37\mask[36:36] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$75 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $38\mask[37:37] 1'1 - case - assign $38\mask[37:37] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $39\mask[38:38] 1'1 - case - assign $39\mask[38:38] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$79 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $40\mask[39:39] 1'1 - case - assign $40\mask[39:39] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $41\mask[40:40] 1'1 - case - assign $41\mask[40:40] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$83 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $42\mask[41:41] 1'1 - case - assign $42\mask[41:41] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $43\mask[42:42] 1'1 - case - assign $43\mask[42:42] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $44\mask[43:43] 1'1 - case - assign $44\mask[43:43] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$89 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $45\mask[44:44] 1'1 - case - assign $45\mask[44:44] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$91 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $46\mask[45:45] 1'1 - case - assign $46\mask[45:45] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $47\mask[46:46] 1'1 - case - assign $47\mask[46:46] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $48\mask[47:47] 1'1 - case - assign $48\mask[47:47] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$97 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $49\mask[48:48] 1'1 - case - assign $49\mask[48:48] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$99 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $50\mask[49:49] 1'1 - case - assign $50\mask[49:49] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $51\mask[50:50] 1'1 - case - assign $51\mask[50:50] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $52\mask[51:51] 1'1 - case - assign $52\mask[51:51] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$105 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $53\mask[52:52] 1'1 - case - assign $53\mask[52:52] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$107 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $54\mask[53:53] 1'1 - case - assign $54\mask[53:53] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$109 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $55\mask[54:54] 1'1 - case - assign $55\mask[54:54] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$111 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $56\mask[55:55] 1'1 - case - assign $56\mask[55:55] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $57\mask[56:56] 1'1 - case - assign $57\mask[56:56] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $58\mask[57:57] 1'1 - case - assign $58\mask[57:57] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$117 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $59\mask[58:58] 1'1 - case - assign $59\mask[58:58] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$119 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $60\mask[59:59] 1'1 - case - assign $60\mask[59:59] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$121 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $61\mask[60:60] 1'1 - case - assign $61\mask[60:60] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$123 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $62\mask[61:61] 1'1 - case - assign $62\mask[61:61] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$125 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $63\mask[62:62] 1'1 - case - assign $63\mask[62:62] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$127 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $64\mask[63:63] 1'1 - case - assign $64\mask[63:63] 1'0 - end - sync always - update \mask $0\mask[63:0] - end - connect \$9 $gt$libresoc.v:131281$6196_Y - connect \$99 $gt$libresoc.v:131282$6197_Y - connect \$101 $gt$libresoc.v:131283$6198_Y - connect \$103 $gt$libresoc.v:131284$6199_Y - connect \$105 $gt$libresoc.v:131285$6200_Y - connect \$107 $gt$libresoc.v:131286$6201_Y - connect \$109 $gt$libresoc.v:131287$6202_Y - connect \$111 $gt$libresoc.v:131288$6203_Y - connect \$113 $gt$libresoc.v:131289$6204_Y - connect \$115 $gt$libresoc.v:131290$6205_Y - connect \$117 $gt$libresoc.v:131291$6206_Y - connect \$11 $gt$libresoc.v:131292$6207_Y - connect \$119 $gt$libresoc.v:131293$6208_Y - connect \$121 $gt$libresoc.v:131294$6209_Y - connect \$123 $gt$libresoc.v:131295$6210_Y - connect \$125 $gt$libresoc.v:131296$6211_Y - connect \$127 $gt$libresoc.v:131297$6212_Y - connect \$13 $gt$libresoc.v:131298$6213_Y - connect \$15 $gt$libresoc.v:131299$6214_Y - connect \$17 $gt$libresoc.v:131300$6215_Y - connect \$1 $gt$libresoc.v:131301$6216_Y - connect \$19 $gt$libresoc.v:131302$6217_Y - connect \$21 $gt$libresoc.v:131303$6218_Y - connect \$23 $gt$libresoc.v:131304$6219_Y - connect \$25 $gt$libresoc.v:131305$6220_Y - connect \$27 $gt$libresoc.v:131306$6221_Y - connect \$29 $gt$libresoc.v:131307$6222_Y - connect \$31 $gt$libresoc.v:131308$6223_Y - connect \$33 $gt$libresoc.v:131309$6224_Y - connect \$35 $gt$libresoc.v:131310$6225_Y - connect \$37 $gt$libresoc.v:131311$6226_Y - connect \$3 $gt$libresoc.v:131312$6227_Y - connect \$39 $gt$libresoc.v:131313$6228_Y - connect \$41 $gt$libresoc.v:131314$6229_Y - connect \$43 $gt$libresoc.v:131315$6230_Y - connect \$45 $gt$libresoc.v:131316$6231_Y - connect \$47 $gt$libresoc.v:131317$6232_Y - connect \$49 $gt$libresoc.v:131318$6233_Y - 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$gt$libresoc.v:131341$6256_Y - connect \$93 $gt$libresoc.v:131342$6257_Y - connect \$95 $gt$libresoc.v:131343$6258_Y - connect \$97 $gt$libresoc.v:131344$6259_Y -end -attribute \src "libresoc.v:131737.1-131766.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" -attribute \generator "nMigen" -module \lenexp - attribute \src "libresoc.v:131761.17-131761.101" - wire width 64 $extend$libresoc.v:131761$6265_Y - attribute \src "libresoc.v:131761.17-131761.101" - wire width 64 $pos$libresoc.v:131761$6266_Y - attribute \src "libresoc.v:131758.17-131758.111" - wire width 20 $sshl$libresoc.v:131758$6262_Y - attribute \src "libresoc.v:131760.17-131760.113" - wire width 32 $sshl$libresoc.v:131760$6264_Y - attribute \src "libresoc.v:131759.17-131759.107" - wire width 21 $sub$libresoc.v:131759$6263_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 20 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 \$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 64 \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 32 \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 input 1 \addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" - wire width 17 \binlen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 input 4 \len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 output 2 \lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 output 3 \rexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:131761$6265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \$7 - connect \Y $extend$libresoc.v:131761$6265_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:131761$6266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:131761$6265_Y - connect \Y $pos$libresoc.v:131761$6266_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:131758$6262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 20 - connect \A 5'00001 - connect \B \len_i - connect \Y $sshl$libresoc.v:131758$6262_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:131760$6264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 17 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 32 - connect \A \binlen - connect \B \addr_i - connect \Y $sshl$libresoc.v:131760$6264_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:131759$6263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 21 - connect \A \$2 - connect \B 1'1 - connect \Y $sub$libresoc.v:131759$6263_Y - end - connect \$2 $sshl$libresoc.v:131758$6262_Y - connect \$4 $sub$libresoc.v:131759$6263_Y - connect \$7 $sshl$libresoc.v:131760$6264_Y - connect \$6 $pos$libresoc.v:131761$6266_Y - connect \$1 \$4 - connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } - connect \lexp_o \$6 - connect \binlen \$4 [16:0] -end -attribute \src "libresoc.v:131770.1-131828.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" 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$or$libresoc.v:131809$6270_Y - attribute \src "libresoc.v:131812.17-131812.97" - wire $or$libresoc.v:131812$6273_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst 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$and$libresoc.v:131806$6267_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:131811$6272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:131811$6272_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:131808$6269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \Y $not$libresoc.v:131808$6269_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:131810$6271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $not$libresoc.v:131810$6271_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:131813$6274 - parameter \A_SIGNED 0 - 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"/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$6278 1'0 - case - assign $1\q_int$next[0:0]$6278 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$6277 - end - connect \$9 $and$libresoc.v:131806$6267_Y - connect \$11 $or$libresoc.v:131807$6268_Y - connect \$13 $not$libresoc.v:131808$6269_Y - connect \$15 $or$libresoc.v:131809$6270_Y - connect \$1 $not$libresoc.v:131810$6271_Y - connect \$3 $and$libresoc.v:131811$6272_Y - connect \$5 $or$libresoc.v:131812$6273_Y - connect \$7 $not$libresoc.v:131813$6274_Y - connect \qlq_lod \$15 - connect \qn_lod \$13 - connect \q_lod \$11 -end -attribute \src "libresoc.v:131832.1-132946.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" -attribute \generator "nMigen" -module \logical0 - attribute \src "libresoc.v:132571.3-132572.24" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:132569.3-132570.44" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:132876.3-132884.6" - wire $0\alu_l_r_alu$next[0:0]$6481 - attribute \src "libresoc.v:132493.3-132494.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6410 - attribute \src "libresoc.v:132543.3-132544.83" - wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$6411 - attribute \src "libresoc.v:132513.3-132514.81" - wire width 12 $0\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6412 - attribute \src "libresoc.v:132515.3-132516.95" - wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6413 - attribute \src "libresoc.v:132517.3-132518.91" - wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6414 - attribute \src "libresoc.v:132531.3-132532.89" - wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6415 - attribute \src "libresoc.v:132545.3-132546.75" - wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6416 - attribute \src "libresoc.v:132511.3-132512.85" - wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6417 - attribute \src "libresoc.v:132527.3-132528.85" - wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6418 - attribute \src "libresoc.v:132533.3-132534.87" - wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6419 - attribute \src "libresoc.v:132539.3-132540.83" - wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6420 - attribute \src "libresoc.v:132541.3-132542.85" - wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6421 - attribute \src "libresoc.v:132523.3-132524.79" - wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6422 - attribute \src "libresoc.v:132525.3-132526.79" - wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6423 - attribute \src "libresoc.v:132537.3-132538.91" - wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6424 - attribute \src "libresoc.v:132521.3-132522.79" - wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6425 - attribute \src "libresoc.v:132519.3-132520.79" - wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6426 - attribute \src "libresoc.v:132535.3-132536.85" - wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6427 - attribute \src "libresoc.v:132529.3-132530.79" - wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:132867.3-132875.6" - wire $0\alui_l_r_alui$next[0:0]$6478 - attribute \src "libresoc.v:132495.3-132496.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132793.3-132814.6" - wire width 64 $0\data_r0__o$next[63:0]$6453 - attribute \src "libresoc.v:132507.3-132508.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:132793.3-132814.6" - wire $0\data_r0__o_ok$next[0:0]$6454 - attribute \src "libresoc.v:132509.3-132510.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132815.3-132836.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6461 - attribute \src "libresoc.v:132503.3-132504.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132815.3-132836.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6462 - attribute \src "libresoc.v:132505.3-132506.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132885.3-132894.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:132895.3-132904.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:131833.7-131833.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:132709.3-132717.6" - wire $0\opc_l_r_opc$next[0:0]$6395 - attribute \src "libresoc.v:132555.3-132556.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132700.3-132708.6" - wire $0\opc_l_s_opc$next[0:0]$6392 - attribute \src "libresoc.v:132557.3-132558.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132905.3-132913.6" - wire width 2 $0\prev_wr_go$next[1:0]$6486 - attribute \src "libresoc.v:132567.3-132568.37" - wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:132654.3-132663.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:132745.3-132753.6" - wire width 2 $0\req_l_r_req$next[1:0]$6407 - attribute \src "libresoc.v:132547.3-132548.39" - wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:132736.3-132744.6" - wire width 2 $0\req_l_s_req$next[1:0]$6404 - attribute \src "libresoc.v:132549.3-132550.39" - wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:132673.3-132681.6" - wire $0\rok_l_r_rdok$next[0:0]$6383 - attribute \src "libresoc.v:132563.3-132564.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132664.3-132672.6" - wire $0\rok_l_s_rdok$next[0:0]$6380 - attribute \src "libresoc.v:132565.3-132566.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132691.3-132699.6" - wire $0\rst_l_r_rst$next[0:0]$6389 - attribute \src "libresoc.v:132559.3-132560.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132682.3-132690.6" - wire $0\rst_l_s_rst$next[0:0]$6386 - attribute \src "libresoc.v:132561.3-132562.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132727.3-132735.6" - wire width 3 $0\src_l_r_src$next[2:0]$6401 - attribute \src "libresoc.v:132551.3-132552.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:132718.3-132726.6" - wire width 3 $0\src_l_s_src$next[2:0]$6398 - attribute \src "libresoc.v:132553.3-132554.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:132837.3-132846.6" - wire width 64 $0\src_r0$next[63:0]$6469 - attribute \src "libresoc.v:132501.3-132502.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:132847.3-132856.6" - wire width 64 $0\src_r1$next[63:0]$6472 - attribute \src "libresoc.v:132499.3-132500.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:132857.3-132866.6" - wire $0\src_r2$next[0:0]$6475 - attribute \src "libresoc.v:132497.3-132498.29" - wire $0\src_r2[0:0] - attribute \src "libresoc.v:131951.7-131951.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:131961.7-131961.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:132876.3-132884.6" - wire $1\alu_l_r_alu$next[0:0]$6482 - attribute \src "libresoc.v:131969.7-131969.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6428 - attribute \src "libresoc.v:131977.13-131977.53" - wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 - attribute \src "libresoc.v:131994.14-131994.56" - wire width 12 $1\alu_logical0_logical_op__fn_unit[11:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 - attribute \src "libresoc.v:131998.14-131998.76" - wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 - attribute \src "libresoc.v:132002.7-132002.51" - wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 - attribute \src "libresoc.v:132010.13-132010.56" - wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6433 - attribute \src "libresoc.v:132014.14-132014.51" - wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 - attribute \src "libresoc.v:132092.13-132092.55" - wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 - attribute \src "libresoc.v:132096.7-132096.48" - wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 - attribute \src "libresoc.v:132100.7-132100.49" - wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 - attribute \src "libresoc.v:132104.7-132104.47" - wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 - attribute \src "libresoc.v:132108.7-132108.48" - wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 - attribute \src "libresoc.v:132112.7-132112.45" - wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 - attribute \src "libresoc.v:132116.7-132116.45" - wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 - attribute \src "libresoc.v:132120.7-132120.51" - wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 - attribute \src "libresoc.v:132124.7-132124.45" - wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 - attribute \src "libresoc.v:132128.7-132128.45" - wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 - attribute \src "libresoc.v:132132.7-132132.48" - wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132754.3-132792.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 - attribute \src "libresoc.v:132136.7-132136.45" - wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:132867.3-132875.6" - wire $1\alui_l_r_alui$next[0:0]$6479 - attribute \src "libresoc.v:132162.7-132162.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132793.3-132814.6" - wire width 64 $1\data_r0__o$next[63:0]$6455 - attribute \src "libresoc.v:132196.14-132196.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:132793.3-132814.6" - wire $1\data_r0__o_ok$next[0:0]$6456 - attribute \src "libresoc.v:132200.7-132200.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132815.3-132836.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6463 - attribute \src "libresoc.v:132204.13-132204.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132815.3-132836.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6464 - attribute \src "libresoc.v:132208.7-132208.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132885.3-132894.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:132895.3-132904.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:132709.3-132717.6" - wire $1\opc_l_r_opc$next[0:0]$6396 - attribute \src "libresoc.v:132222.7-132222.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132700.3-132708.6" - wire $1\opc_l_s_opc$next[0:0]$6393 - attribute \src "libresoc.v:132226.7-132226.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132905.3-132913.6" - wire width 2 $1\prev_wr_go$next[1:0]$6487 - attribute \src "libresoc.v:132357.13-132357.30" - wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:132654.3-132663.6" - wire $1\req_done[0:0] - attribute \src "libresoc.v:132745.3-132753.6" - wire width 2 $1\req_l_r_req$next[1:0]$6408 - attribute \src "libresoc.v:132365.13-132365.31" - wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:132736.3-132744.6" - wire width 2 $1\req_l_s_req$next[1:0]$6405 - attribute \src "libresoc.v:132369.13-132369.31" - wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:132673.3-132681.6" - wire $1\rok_l_r_rdok$next[0:0]$6384 - attribute \src "libresoc.v:132381.7-132381.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132664.3-132672.6" - wire $1\rok_l_s_rdok$next[0:0]$6381 - attribute \src "libresoc.v:132385.7-132385.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132691.3-132699.6" - wire $1\rst_l_r_rst$next[0:0]$6390 - attribute \src "libresoc.v:132389.7-132389.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132682.3-132690.6" - wire $1\rst_l_s_rst$next[0:0]$6387 - attribute \src "libresoc.v:132393.7-132393.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132727.3-132735.6" - wire width 3 $1\src_l_r_src$next[2:0]$6402 - attribute \src "libresoc.v:132407.13-132407.31" - wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:132718.3-132726.6" - wire width 3 $1\src_l_s_src$next[2:0]$6399 - attribute \src "libresoc.v:132411.13-132411.31" - wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:132837.3-132846.6" - wire width 64 $1\src_r0$next[63:0]$6470 - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_logical0_logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_logical0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_logical0_logical_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute 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\enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_logical0_logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_logical0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_logical0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_logical0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_logical0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_logical0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_logical0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 2 \alu_pulsem - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 21 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 20 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 24 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 23 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 22 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 30 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 29 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 31 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:131833.7-131833.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 18 \oper_i_alu_logical0__data_len - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_logical0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_logical0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_logical0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 12 \oper_i_alu_logical0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \oper_i_alu_logical0__insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_logical0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_logical0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_logical0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_logical0__is_32bit - attribute \src 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parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:132476$6321_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:132477$6322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$4 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:132477$6322_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:132483$6328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$6 - connect \Y $reduce_and$libresoc.v:132483$6328_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:132454$6299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \$25 - connect \Y $reduce_or$libresoc.v:132454$6299_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132457$6302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:132457$6302_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132458$6303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:132458$6303_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132480$6325 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132480$6325_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132481$6326 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132481$6326_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132482$6327 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132482$6327_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132484$6329 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_logical0_logical_op__imm_data__data - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132484$6329_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:132485$6330 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:132485$6330_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:132486$6331 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$80 - connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:132486$6331_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:132487$6332 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:132487$6332_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132573.14-132579.4" - cell \alu_l$61 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132580.16-132612.4" - cell \alu_logical0 \alu_logical0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_logical0_cr_a - connect \cr_a_ok \cr_a_ok - connect \logical_op__data_len \alu_logical0_logical_op__data_len - connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok - connect \logical_op__input_carry \alu_logical0_logical_op__input_carry - connect \logical_op__insn \alu_logical0_logical_op__insn - connect \logical_op__insn_type \alu_logical0_logical_op__insn_type - connect \logical_op__invert_in \alu_logical0_logical_op__invert_in - connect \logical_op__invert_out \alu_logical0_logical_op__invert_out - connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit - connect \logical_op__is_signed \alu_logical0_logical_op__is_signed - connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok - connect \logical_op__output_carry \alu_logical0_logical_op__output_carry - connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok - connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc - connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 - connect \logical_op__zero_a \alu_logical0_logical_op__zero_a - connect \n_ready_i \alu_logical0_n_ready_i - connect \n_valid_o \alu_logical0_n_valid_o - connect \o \alu_logical0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_logical0_p_ready_o - connect \p_valid_i \alu_logical0_p_valid_i - connect \ra \alu_logical0_ra - connect \rb \alu_logical0_rb - connect \xer_so \alu_logical0_xer_so - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132613.15-132619.4" - cell \alui_l$60 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132620.14-132626.4" - cell \opc_l$56 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132627.14-132633.4" - cell \req_l$57 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132634.14-132640.4" - cell \rok_l$59 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132641.14-132646.4" - cell \rst_l$58 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:132647.14-132653.4" - cell \src_l$55 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:131833.7-131833.20" - process $proc$libresoc.v:131833$6488 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:131951.7-131951.24" - process $proc$libresoc.v:131951$6489 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:131961.7-131961.26" - process $proc$libresoc.v:131961$6490 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:131969.7-131969.25" - process $proc$libresoc.v:131969$6491 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:131977.13-131977.53" - process $proc$libresoc.v:131977$6492 - assign { } { } - assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:131994.14-131994.56" - process $proc$libresoc.v:131994$6493 - assign { } { } - assign $1\alu_logical0_logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:131998.14-131998.76" - process $proc$libresoc.v:131998$6494 - assign { } { } - assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:132002.7-132002.51" - process $proc$libresoc.v:132002$6495 - assign { } { } - assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:132010.13-132010.56" - process $proc$libresoc.v:132010$6496 - assign { } { } - assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:132014.14-132014.51" - process $proc$libresoc.v:132014$6497 - assign { } { } - assign $1\alu_logical0_logical_op__insn[31:0] 0 - sync always - sync init - update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:132092.13-132092.55" - process $proc$libresoc.v:132092$6498 - assign { } { } - assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:132096.7-132096.48" - process $proc$libresoc.v:132096$6499 - assign { } { } - assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:132100.7-132100.49" - process $proc$libresoc.v:132100$6500 - assign { } { } - assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:132104.7-132104.47" - process $proc$libresoc.v:132104$6501 - assign { } { } - assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:132108.7-132108.48" - process $proc$libresoc.v:132108$6502 - assign { } { } - assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:132112.7-132112.45" - process $proc$libresoc.v:132112$6503 - assign { } { } - assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:132116.7-132116.45" - process $proc$libresoc.v:132116$6504 - assign { } { } - assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:132120.7-132120.51" - process $proc$libresoc.v:132120$6505 - assign { } { } - assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:132124.7-132124.45" - process $proc$libresoc.v:132124$6506 - assign { } { } - assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:132128.7-132128.45" - process $proc$libresoc.v:132128$6507 - assign { } { } - assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:132132.7-132132.48" - process $proc$libresoc.v:132132$6508 - assign { } { } - assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:132136.7-132136.45" - process $proc$libresoc.v:132136$6509 - assign { } { } - assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:132162.7-132162.27" - process $proc$libresoc.v:132162$6510 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:132196.14-132196.47" - process $proc$libresoc.v:132196$6511 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:132200.7-132200.27" - process $proc$libresoc.v:132200$6512 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:132204.13-132204.33" - process $proc$libresoc.v:132204$6513 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:132208.7-132208.30" - process $proc$libresoc.v:132208$6514 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:132222.7-132222.25" - process $proc$libresoc.v:132222$6515 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:132226.7-132226.25" - process $proc$libresoc.v:132226$6516 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:132357.13-132357.30" - process $proc$libresoc.v:132357$6517 - assign { } { } - assign $1\prev_wr_go[1:0] 2'00 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[1:0] - end - attribute \src "libresoc.v:132365.13-132365.31" - process $proc$libresoc.v:132365$6518 - assign { } { } - assign $1\req_l_r_req[1:0] 2'11 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[1:0] - end - attribute \src "libresoc.v:132369.13-132369.31" - process $proc$libresoc.v:132369$6519 - assign { } { } - assign $1\req_l_s_req[1:0] 2'00 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[1:0] - end - attribute \src "libresoc.v:132381.7-132381.26" - process $proc$libresoc.v:132381$6520 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:132385.7-132385.26" - process $proc$libresoc.v:132385$6521 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:132389.7-132389.25" - process $proc$libresoc.v:132389$6522 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:132393.7-132393.25" - process $proc$libresoc.v:132393$6523 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:132407.13-132407.31" - process $proc$libresoc.v:132407$6524 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "libresoc.v:132411.13-132411.31" - process $proc$libresoc.v:132411$6525 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "libresoc.v:132419.14-132419.43" - process $proc$libresoc.v:132419$6526 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:132423.14-132423.43" - process $proc$libresoc.v:132423$6527 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:132427.7-132427.20" - process $proc$libresoc.v:132427$6528 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "libresoc.v:132493.3-132494.39" - process $proc$libresoc.v:132493$6338 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:132495.3-132496.43" - process $proc$libresoc.v:132495$6339 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:132497.3-132498.29" - process $proc$libresoc.v:132497$6340 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "libresoc.v:132499.3-132500.29" - process $proc$libresoc.v:132499$6341 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:132501.3-132502.29" - process $proc$libresoc.v:132501$6342 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:132503.3-132504.43" - process $proc$libresoc.v:132503$6343 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:132505.3-132506.49" - process $proc$libresoc.v:132505$6344 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:132507.3-132508.37" - process $proc$libresoc.v:132507$6345 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:132509.3-132510.43" - process $proc$libresoc.v:132509$6346 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:132511.3-132512.85" - process $proc$libresoc.v:132511$6347 - assign { } { } - assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:132513.3-132514.81" - process $proc$libresoc.v:132513$6348 - assign { } { } - assign $0\alu_logical0_logical_op__fn_unit[11:0] \alu_logical0_logical_op__fn_unit$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:132515.3-132516.95" - process $proc$libresoc.v:132515$6349 - assign { } { } - assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:132517.3-132518.91" - process $proc$libresoc.v:132517$6350 - assign { } { } - assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:132519.3-132520.79" - process $proc$libresoc.v:132519$6351 - assign { } { } - assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:132521.3-132522.79" - process $proc$libresoc.v:132521$6352 - assign { } { } - assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:132523.3-132524.79" - process $proc$libresoc.v:132523$6353 - assign { } { } - assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:132525.3-132526.79" - process $proc$libresoc.v:132525$6354 - assign { } { } - assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:132527.3-132528.85" - process $proc$libresoc.v:132527$6355 - assign { } { } - assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:132529.3-132530.79" - process $proc$libresoc.v:132529$6356 - assign { } { } - assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:132531.3-132532.89" - process $proc$libresoc.v:132531$6357 - assign { } { } - assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:132533.3-132534.87" - process $proc$libresoc.v:132533$6358 - assign { } { } - assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:132535.3-132536.85" - process $proc$libresoc.v:132535$6359 - assign { } { } - assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:132537.3-132538.91" - process $proc$libresoc.v:132537$6360 - assign { } { } - assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:132539.3-132540.83" - process $proc$libresoc.v:132539$6361 - assign { } { } - assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:132541.3-132542.85" - process $proc$libresoc.v:132541$6362 - assign { } { } - assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:132543.3-132544.83" - process $proc$libresoc.v:132543$6363 - assign { } { } - assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] - end - attribute \src "libresoc.v:132545.3-132546.75" - process $proc$libresoc.v:132545$6364 - assign { } { } - assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next - sync posedge \coresync_clk - update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] - end - attribute \src "libresoc.v:132547.3-132548.39" - process $proc$libresoc.v:132547$6365 - assign { } { } - assign $0\req_l_r_req[1:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[1:0] - end - attribute \src "libresoc.v:132549.3-132550.39" - process $proc$libresoc.v:132549$6366 - assign { } { } - assign $0\req_l_s_req[1:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[1:0] - end - attribute \src "libresoc.v:132551.3-132552.39" - process $proc$libresoc.v:132551$6367 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "libresoc.v:132553.3-132554.39" - process $proc$libresoc.v:132553$6368 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "libresoc.v:132555.3-132556.39" - process $proc$libresoc.v:132555$6369 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:132557.3-132558.39" - process $proc$libresoc.v:132557$6370 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:132559.3-132560.39" - process $proc$libresoc.v:132559$6371 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:132561.3-132562.39" - process $proc$libresoc.v:132561$6372 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:132563.3-132564.41" - process $proc$libresoc.v:132563$6373 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:132565.3-132566.41" - process $proc$libresoc.v:132565$6374 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:132567.3-132568.37" - process $proc$libresoc.v:132567$6375 - assign { } { } - assign $0\prev_wr_go[1:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[1:0] - end - attribute \src "libresoc.v:132569.3-132570.44" - process $proc$libresoc.v:132569$6376 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:132571.3-132572.24" - process $proc$libresoc.v:132571$6377 - assign { } { } - assign $0\all_rd_dly[0:0] \$9 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:132654.3-132663.6" - process $proc$libresoc.v:132654$6378 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:132655.5-132655.29" - switch \initial - attribute \src "libresoc.v:132655.9-132655.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$53 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$45 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:132664.3-132672.6" - process $proc$libresoc.v:132664$6379 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6380 $1\rok_l_s_rdok$next[0:0]$6381 - attribute \src "libresoc.v:132665.5-132665.29" - switch \initial - attribute \src "libresoc.v:132665.9-132665.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6381 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$6381 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6380 - end - attribute \src "libresoc.v:132673.3-132681.6" - process $proc$libresoc.v:132673$6382 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6383 $1\rok_l_r_rdok$next[0:0]$6384 - attribute \src "libresoc.v:132674.5-132674.29" - switch \initial - attribute \src "libresoc.v:132674.9-132674.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6384 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$6384 \$63 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6383 - end - attribute \src "libresoc.v:132682.3-132690.6" - process $proc$libresoc.v:132682$6385 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6386 $1\rst_l_s_rst$next[0:0]$6387 - attribute \src "libresoc.v:132683.5-132683.29" - switch \initial - attribute \src "libresoc.v:132683.9-132683.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6387 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$6387 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6386 - end - attribute \src "libresoc.v:132691.3-132699.6" - process $proc$libresoc.v:132691$6388 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6389 $1\rst_l_r_rst$next[0:0]$6390 - attribute \src "libresoc.v:132692.5-132692.29" - switch \initial - attribute \src "libresoc.v:132692.9-132692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6390 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$6390 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6389 - end - attribute \src "libresoc.v:132700.3-132708.6" - process $proc$libresoc.v:132700$6391 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6392 $1\opc_l_s_opc$next[0:0]$6393 - attribute \src "libresoc.v:132701.5-132701.29" - switch \initial - attribute \src "libresoc.v:132701.9-132701.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6393 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$6393 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6392 - end - attribute \src "libresoc.v:132709.3-132717.6" - process $proc$libresoc.v:132709$6394 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6395 $1\opc_l_r_opc$next[0:0]$6396 - attribute \src "libresoc.v:132710.5-132710.29" - switch \initial - attribute \src "libresoc.v:132710.9-132710.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6396 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$6396 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6395 - end - attribute \src "libresoc.v:132718.3-132726.6" - process $proc$libresoc.v:132718$6397 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$6398 $1\src_l_s_src$next[2:0]$6399 - attribute \src "libresoc.v:132719.5-132719.29" - switch \initial - attribute \src "libresoc.v:132719.9-132719.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$6399 3'000 - case - assign $1\src_l_s_src$next[2:0]$6399 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6398 - end - attribute \src "libresoc.v:132727.3-132735.6" - process $proc$libresoc.v:132727$6400 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$6401 $1\src_l_r_src$next[2:0]$6402 - attribute \src "libresoc.v:132728.5-132728.29" - switch \initial - attribute \src "libresoc.v:132728.9-132728.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$6402 3'111 - case - assign $1\src_l_r_src$next[2:0]$6402 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6401 - end - attribute \src "libresoc.v:132736.3-132744.6" - process $proc$libresoc.v:132736$6403 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[1:0]$6404 $1\req_l_s_req$next[1:0]$6405 - attribute \src "libresoc.v:132737.5-132737.29" - switch \initial - attribute \src "libresoc.v:132737.9-132737.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[1:0]$6405 2'00 - case - assign $1\req_l_s_req$next[1:0]$6405 \$65 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6404 - end - attribute \src "libresoc.v:132745.3-132753.6" - process $proc$libresoc.v:132745$6406 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[1:0]$6407 $1\req_l_r_req$next[1:0]$6408 - attribute \src "libresoc.v:132746.5-132746.29" - switch \initial - attribute \src "libresoc.v:132746.9-132746.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[1:0]$6408 2'11 - case - assign $1\req_l_r_req$next[1:0]$6408 \$67 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6407 - end - attribute \src "libresoc.v:132754.3-132792.6" - process $proc$libresoc.v:132754$6409 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6410 $1\alu_logical0_logical_op__data_len$next[3:0]$6428 - assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$6411 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6414 $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6415 $1\alu_logical0_logical_op__insn$next[31:0]$6433 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6416 $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6417 $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6418 $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6419 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6420 $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6423 $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 - assign { } { } - assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6426 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6427 $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6412 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6446 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6413 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6447 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6421 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6448 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6422 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6449 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6424 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6450 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6425 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6451 - attribute \src "libresoc.v:132755.5-132755.29" - switch \initial - attribute \src "libresoc.v:132755.9-132755.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6433 $1\alu_logical0_logical_op__data_len$next[3:0]$6428 $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } - case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6428 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$6429 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6432 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6433 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6434 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6435 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6436 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6437 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6438 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6441 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6444 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6445 \alu_logical0_logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6446 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6447 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6451 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6450 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6448 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6449 1'0 - case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6446 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6430 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6447 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6431 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6448 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6439 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6449 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6440 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6450 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6442 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6451 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6443 - end - sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6410 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$6411 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6412 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6413 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6414 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6415 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6416 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6417 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6418 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6419 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6420 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6421 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6422 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6423 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6424 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6425 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6426 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6427 - end - attribute \src "libresoc.v:132793.3-132814.6" - process $proc$libresoc.v:132793$6452 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$6453 $2\data_r0__o$next[63:0]$6457 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6454 $3\data_r0__o_ok$next[0:0]$6459 - attribute \src "libresoc.v:132794.5-132794.29" - switch \initial - attribute \src "libresoc.v:132794.9-132794.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6456 $1\data_r0__o$next[63:0]$6455 } { \o_ok \alu_logical0_o } - case - assign $1\data_r0__o$next[63:0]$6455 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6456 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6458 $2\data_r0__o$next[63:0]$6457 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$6457 $1\data_r0__o$next[63:0]$6455 - assign $2\data_r0__o_ok$next[0:0]$6458 $1\data_r0__o_ok$next[0:0]$6456 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6459 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$6459 $2\data_r0__o_ok$next[0:0]$6458 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6453 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6454 - end - attribute \src "libresoc.v:132815.3-132836.6" - process $proc$libresoc.v:132815$6460 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6461 $2\data_r1__cr_a$next[3:0]$6465 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6462 $3\data_r1__cr_a_ok$next[0:0]$6467 - attribute \src "libresoc.v:132816.5-132816.29" - switch \initial - attribute \src "libresoc.v:132816.9-132816.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6464 $1\data_r1__cr_a$next[3:0]$6463 } { \cr_a_ok \alu_logical0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$6463 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6464 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6466 $2\data_r1__cr_a$next[3:0]$6465 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$6465 $1\data_r1__cr_a$next[3:0]$6463 - assign $2\data_r1__cr_a_ok$next[0:0]$6466 $1\data_r1__cr_a_ok$next[0:0]$6464 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6467 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$6467 $2\data_r1__cr_a_ok$next[0:0]$6466 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6461 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6462 - end - attribute \src "libresoc.v:132837.3-132846.6" - process $proc$libresoc.v:132837$6468 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$6469 $1\src_r0$next[63:0]$6470 - attribute \src "libresoc.v:132838.5-132838.29" - switch \initial - attribute \src "libresoc.v:132838.9-132838.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$6470 \src_or_imm - case - assign $1\src_r0$next[63:0]$6470 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$6469 - end - attribute \src "libresoc.v:132847.3-132856.6" - process $proc$libresoc.v:132847$6471 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$6472 $1\src_r1$next[63:0]$6473 - attribute \src "libresoc.v:132848.5-132848.29" - switch \initial - attribute \src "libresoc.v:132848.9-132848.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$6473 \src_or_imm$80 - case - assign $1\src_r1$next[63:0]$6473 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$6472 - end - attribute \src "libresoc.v:132857.3-132866.6" - process $proc$libresoc.v:132857$6474 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$6475 $1\src_r2$next[0:0]$6476 - attribute \src "libresoc.v:132858.5-132858.29" - switch \initial - attribute \src "libresoc.v:132858.9-132858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$6476 \src3_i - case - assign $1\src_r2$next[0:0]$6476 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$6475 - end - attribute \src "libresoc.v:132867.3-132875.6" - process $proc$libresoc.v:132867$6477 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6478 $1\alui_l_r_alui$next[0:0]$6479 - attribute \src "libresoc.v:132868.5-132868.29" - switch \initial - attribute \src "libresoc.v:132868.9-132868.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6479 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$6479 \$89 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6478 - end - attribute \src "libresoc.v:132876.3-132884.6" - process $proc$libresoc.v:132876$6480 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6481 $1\alu_l_r_alu$next[0:0]$6482 - attribute \src "libresoc.v:132877.5-132877.29" - switch \initial - attribute \src "libresoc.v:132877.9-132877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6482 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$6482 \$91 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6481 - end - attribute \src "libresoc.v:132885.3-132894.6" - process $proc$libresoc.v:132885$6483 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:132886.5-132886.29" - switch \initial - attribute \src "libresoc.v:132886.9-132886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$113 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:132895.3-132904.6" - process $proc$libresoc.v:132895$6484 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:132896.5-132896.29" - switch \initial - attribute \src "libresoc.v:132896.9-132896.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "libresoc.v:132905.3-132913.6" - process $proc$libresoc.v:132905$6485 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[1:0]$6486 $1\prev_wr_go$next[1:0]$6487 - attribute \src "libresoc.v:132906.5-132906.29" - switch \initial - attribute \src "libresoc.v:132906.9-132906.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\prev_wr_go$next[1:0]$6487 2'00 - case - assign $1\prev_wr_go$next[1:0]$6487 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6486 - end - connect \$9 $and$libresoc.v:132436$6281_Y - connect \$99 $and$libresoc.v:132437$6282_Y - connect \$101 $not$libresoc.v:132438$6283_Y - connect \$103 $and$libresoc.v:132439$6284_Y - connect \$105 $and$libresoc.v:132440$6285_Y - connect \$107 $and$libresoc.v:132441$6286_Y - connect \$109 $and$libresoc.v:132442$6287_Y - connect \$111 $and$libresoc.v:132443$6288_Y - connect \$113 $and$libresoc.v:132444$6289_Y - connect \$115 $and$libresoc.v:132445$6290_Y - connect \$11 $not$libresoc.v:132446$6291_Y - connect \$13 $and$libresoc.v:132447$6292_Y - connect \$15 $not$libresoc.v:132448$6293_Y - connect \$17 $and$libresoc.v:132449$6294_Y - connect \$1 $and$libresoc.v:132450$6295_Y - connect \$19 $and$libresoc.v:132451$6296_Y - connect \$23 $not$libresoc.v:132452$6297_Y - connect \$25 $and$libresoc.v:132453$6298_Y - connect \$22 $reduce_or$libresoc.v:132454$6299_Y - connect \$21 $not$libresoc.v:132455$6300_Y - connect \$29 $and$libresoc.v:132456$6301_Y - connect \$31 $reduce_or$libresoc.v:132457$6302_Y - connect \$33 $reduce_or$libresoc.v:132458$6303_Y - connect \$35 $or$libresoc.v:132459$6304_Y - connect \$37 $not$libresoc.v:132460$6305_Y - connect \$39 $and$libresoc.v:132461$6306_Y - connect \$41 $and$libresoc.v:132462$6307_Y - connect \$43 $eq$libresoc.v:132463$6308_Y - connect \$45 $and$libresoc.v:132464$6309_Y - connect \$47 $eq$libresoc.v:132465$6310_Y - connect \$4 $not$libresoc.v:132466$6311_Y - connect \$49 $and$libresoc.v:132467$6312_Y - connect \$51 $and$libresoc.v:132468$6313_Y - connect \$53 $and$libresoc.v:132469$6314_Y - connect \$55 $or$libresoc.v:132470$6315_Y - connect \$57 $or$libresoc.v:132471$6316_Y - connect \$59 $or$libresoc.v:132472$6317_Y - connect \$61 $or$libresoc.v:132473$6318_Y - connect \$63 $and$libresoc.v:132474$6319_Y - connect \$65 $and$libresoc.v:132475$6320_Y - connect \$67 $or$libresoc.v:132476$6321_Y - connect \$6 $or$libresoc.v:132477$6322_Y - connect \$69 $and$libresoc.v:132478$6323_Y - connect \$71 $and$libresoc.v:132479$6324_Y - connect \$73 $ternary$libresoc.v:132480$6325_Y - connect \$75 $ternary$libresoc.v:132481$6326_Y - connect \$78 $ternary$libresoc.v:132482$6327_Y - connect \$3 $reduce_and$libresoc.v:132483$6328_Y - connect \$81 $ternary$libresoc.v:132484$6329_Y - connect \$83 $ternary$libresoc.v:132485$6330_Y - connect \$85 $ternary$libresoc.v:132486$6331_Y - connect \$87 $ternary$libresoc.v:132487$6332_Y - connect \$89 $and$libresoc.v:132488$6333_Y - connect \$91 $and$libresoc.v:132489$6334_Y - connect \$93 $and$libresoc.v:132490$6335_Y - connect \$95 $not$libresoc.v:132491$6336_Y - connect \$97 $not$libresoc.v:132492$6337_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$111 - connect \cu_rd__rel_o \$103 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_logical0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_logical0_p_valid_i \alui_l_q_alui - connect \alu_logical0_xer_so \$87 - connect \alu_logical0_rb \$85 - connect \alu_logical0_ra \$83 - connect \src_or_imm$80 \$81 - connect \src_sel$77 \$78 - connect \src_or_imm \$75 - connect \src_sel \$73 - connect \cu_wrmask_o { \$71 \$69 } - connect \reset_r \$61 - connect \reset_w \$59 - connect \rst_r \$57 - connect \reset \$55 - connect \wr_any \$35 - connect \cu_done_o \$29 - connect \alu_pulsem { \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$17 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_logical0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$13 - connect \all_rd_dly$next \all_rd - connect \all_rd \$9 -end -attribute \src "libresoc.v:132950.1-134320.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" -attribute \generator "nMigen" -module \logical_pipe1 - attribute \src "libresoc.v:134259.3-134277.6" - wire width 4 $0\cr_a$next[3:0]$6613 - attribute \src "libresoc.v:134019.3-134020.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:134259.3-134277.6" - wire $0\cr_a_ok$next[0:0]$6614 - attribute \src "libresoc.v:134021.3-134022.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:132951.7-132951.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6564 - attribute \src "libresoc.v:134059.3-134060.57" - wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$6565 - attribute \src "libresoc.v:134029.3-134030.55" - wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6566 - attribute \src "libresoc.v:134031.3-134032.69" - wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6567 - attribute \src "libresoc.v:134033.3-134034.65" - wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6568 - attribute \src "libresoc.v:134047.3-134048.63" - wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire width 32 $0\logical_op__insn$next[31:0]$6569 - attribute \src "libresoc.v:134061.3-134062.49" - wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6570 - attribute \src "libresoc.v:134027.3-134028.59" - wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__invert_in$next[0:0]$6571 - attribute \src "libresoc.v:134043.3-134044.59" - wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__invert_out$next[0:0]$6572 - attribute \src "libresoc.v:134049.3-134050.61" - wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__is_32bit$next[0:0]$6573 - attribute \src "libresoc.v:134055.3-134056.57" - wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__is_signed$next[0:0]$6574 - attribute \src "libresoc.v:134057.3-134058.59" - wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__oe__oe$next[0:0]$6575 - attribute \src "libresoc.v:134039.3-134040.53" - wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__oe__ok$next[0:0]$6576 - attribute \src "libresoc.v:134041.3-134042.53" - wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__output_carry$next[0:0]$6577 - attribute \src "libresoc.v:134053.3-134054.65" - wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__rc__ok$next[0:0]$6578 - attribute \src "libresoc.v:134037.3-134038.53" - wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__rc__rc$next[0:0]$6579 - attribute \src "libresoc.v:134035.3-134036.53" - wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__write_cr0$next[0:0]$6580 - attribute \src "libresoc.v:134051.3-134052.59" - wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:134198.3-134239.6" - wire $0\logical_op__zero_a$next[0:0]$6581 - attribute \src "libresoc.v:134045.3-134046.53" - wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:134185.3-134197.6" - wire width 2 $0\muxid$next[1:0]$6561 - attribute \src "libresoc.v:134063.3-134064.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:134240.3-134258.6" - wire width 64 $0\o$next[63:0]$6607 - attribute \src "libresoc.v:134023.3-134024.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:134240.3-134258.6" - wire $0\o_ok$next[0:0]$6608 - attribute \src "libresoc.v:134025.3-134026.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:134167.3-134184.6" - wire $0\r_busy$next[0:0]$6557 - attribute \src "libresoc.v:134065.3-134066.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:134278.3-134296.6" - wire $0\xer_so$next[0:0]$6619 - attribute \src "libresoc.v:134015.3-134016.29" - wire $0\xer_so[0:0] - attribute \src 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$2\logical_op__imm_data__data$next[63:0]$6600 - attribute \src "libresoc.v:134198.3-134239.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6601 - attribute \src "libresoc.v:134198.3-134239.6" - wire $2\logical_op__oe__oe$next[0:0]$6602 - attribute \src "libresoc.v:134198.3-134239.6" - wire $2\logical_op__oe__ok$next[0:0]$6603 - attribute \src "libresoc.v:134198.3-134239.6" - wire $2\logical_op__rc__ok$next[0:0]$6604 - attribute \src "libresoc.v:134198.3-134239.6" - wire $2\logical_op__rc__rc$next[0:0]$6605 - attribute \src "libresoc.v:134240.3-134258.6" - wire $2\o_ok$next[0:0]$6611 - attribute \src "libresoc.v:134167.3-134184.6" - wire $2\r_busy$next[0:0]$6559 - attribute \src "libresoc.v:134278.3-134296.6" - wire $2\xer_so_ok$next[0:0]$6623 - attribute \src "libresoc.v:134014.18-134014.118" - wire $and$libresoc.v:134014$6529_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$64 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 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"OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 38 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 37 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 36 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_logical_op__data_len$60 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_logical_op__fn_unit$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_logical_op__imm_data__data$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__imm_data__ok$47 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_logical_op__input_carry$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_logical_op__insn$61 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_logical_op__insn_type$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_in$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__invert_out$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_32bit$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__is_signed$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__oe$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__oe__ok$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__output_carry$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__rc__rc$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__write_cr0$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_logical_op__zero_a$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_so$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 30 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 50 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 51 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 52 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:134014$6529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$63 - connect \B \p_ready_o - connect \Y $and$libresoc.v:134014$6529_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:134067.14-134112.4" - cell \input$50 \input - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__data_len$18 \input_logical_op__data_len$38 - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \input_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 - connect \logical_op__insn \input_logical_op__insn - connect \logical_op__insn$19 \input_logical_op__insn$39 - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 - connect \logical_op__invert_in \input_logical_op__invert_in - connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 - connect \logical_op__oe__ok \input_logical_op__oe__ok - connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 - connect \logical_op__rc__ok \input_logical_op__rc__ok - connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$21 - connect \ra \input_ra - connect \ra$20 \input_ra$40 - connect \rb \input_rb - connect \rb$21 \input_rb$41 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$42 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:134113.13-134158.4" - cell \main$51 \main - connect \logical_op__data_len \main_logical_op__data_len - connect \logical_op__data_len$18 \main_logical_op__data_len$60 - connect \logical_op__fn_unit \main_logical_op__fn_unit - connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 - connect \logical_op__imm_data__data \main_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 - connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 - connect \logical_op__input_carry \main_logical_op__input_carry - connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 - connect \logical_op__insn \main_logical_op__insn - connect \logical_op__insn$19 \main_logical_op__insn$61 - connect \logical_op__insn_type \main_logical_op__insn_type - connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 - connect \logical_op__invert_in \main_logical_op__invert_in - connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 - connect \logical_op__invert_out \main_logical_op__invert_out - connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 - connect \logical_op__is_32bit \main_logical_op__is_32bit - connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 - connect \logical_op__is_signed \main_logical_op__is_signed - connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 - connect \logical_op__oe__oe \main_logical_op__oe__oe - connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 - connect \logical_op__oe__ok \main_logical_op__oe__ok - connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 - connect \logical_op__output_carry \main_logical_op__output_carry - connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 - connect \logical_op__rc__ok \main_logical_op__rc__ok - connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 - connect \logical_op__rc__rc \main_logical_op__rc__rc - connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 - connect \logical_op__write_cr0 \main_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 - connect \logical_op__zero_a \main_logical_op__zero_a - connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$43 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_so \main_xer_so - connect \xer_so$20 \main_xer_so$62 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:134159.10-134162.4" - cell \n$49 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:134163.10-134166.4" - cell \p$48 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:132951.7-132951.20" - process $proc$libresoc.v:132951$6624 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:132960.13-132960.24" - process $proc$libresoc.v:132960$6625 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:132969.7-132969.21" - process $proc$libresoc.v:132969$6626 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:133248.13-133248.40" - process $proc$libresoc.v:133248$6627 - assign { } { } - assign $1\logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \logical_op__data_len $1\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:133270.14-133270.43" - process $proc$libresoc.v:133270$6628 - assign { } { } - assign $1\logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:133305.14-133305.63" - process $proc$libresoc.v:133305$6629 - assign { } { } - assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:133314.7-133314.38" - process $proc$libresoc.v:133314$6630 - assign { } { } - assign $1\logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:133327.13-133327.43" - process $proc$libresoc.v:133327$6631 - assign { } { } - assign $1\logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \logical_op__input_carry $1\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:133344.14-133344.38" - process $proc$libresoc.v:133344$6632 - assign { } { } - assign $1\logical_op__insn[31:0] 0 - sync always - sync init - update \logical_op__insn $1\logical_op__insn[31:0] - end - attribute \src "libresoc.v:133427.13-133427.42" - process $proc$libresoc.v:133427$6633 - assign { } { } - assign $1\logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \logical_op__insn_type $1\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:133584.7-133584.35" - process $proc$libresoc.v:133584$6634 - assign { } { } - assign $1\logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \logical_op__invert_in $1\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:133593.7-133593.36" - process $proc$libresoc.v:133593$6635 - assign { } { } - assign $1\logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \logical_op__invert_out $1\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:133602.7-133602.34" - process $proc$libresoc.v:133602$6636 - assign { } { } - assign $1\logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:133611.7-133611.35" - process $proc$libresoc.v:133611$6637 - assign { } { } - assign $1\logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \logical_op__is_signed $1\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:133620.7-133620.32" - process $proc$libresoc.v:133620$6638 - assign { } { } - assign $1\logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:133629.7-133629.32" - process $proc$libresoc.v:133629$6639 - assign { } { } - assign $1\logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:133638.7-133638.38" - process $proc$libresoc.v:133638$6640 - assign { } { } - assign $1\logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \logical_op__output_carry $1\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:133647.7-133647.32" - process $proc$libresoc.v:133647$6641 - assign { } { } - assign $1\logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:133656.7-133656.32" - process $proc$libresoc.v:133656$6642 - assign { } { } - assign $1\logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:133665.7-133665.35" - process $proc$libresoc.v:133665$6643 - assign { } { } - assign $1\logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:133674.7-133674.32" - process $proc$libresoc.v:133674$6644 - assign { } { } - assign $1\logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \logical_op__zero_a $1\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:133953.13-133953.25" - process $proc$libresoc.v:133953$6645 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:133968.14-133968.38" - process $proc$libresoc.v:133968$6646 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:133975.7-133975.18" - process $proc$libresoc.v:133975$6647 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:133989.7-133989.20" - process $proc$libresoc.v:133989$6648 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:133998.7-133998.20" - process $proc$libresoc.v:133998$6649 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:134007.7-134007.23" - process $proc$libresoc.v:134007$6650 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:134015.3-134016.29" - process $proc$libresoc.v:134015$6530 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:134017.3-134018.35" - process $proc$libresoc.v:134017$6531 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:134019.3-134020.25" - process $proc$libresoc.v:134019$6532 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:134021.3-134022.31" - process $proc$libresoc.v:134021$6533 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:134023.3-134024.19" - process $proc$libresoc.v:134023$6534 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:134025.3-134026.25" - process $proc$libresoc.v:134025$6535 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:134027.3-134028.59" - process $proc$libresoc.v:134027$6536 - assign { } { } - assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next - sync posedge \coresync_clk - update \logical_op__insn_type $0\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:134029.3-134030.55" - process $proc$libresoc.v:134029$6537 - assign { } { } - assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next - sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:134031.3-134032.69" - process $proc$libresoc.v:134031$6538 - assign { } { } - assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next - sync posedge \coresync_clk - update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:134033.3-134034.65" - process $proc$libresoc.v:134033$6539 - assign { } { } - assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:134035.3-134036.53" - process $proc$libresoc.v:134035$6540 - assign { } { } - assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next - sync posedge \coresync_clk - update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:134037.3-134038.53" - process $proc$libresoc.v:134037$6541 - assign { } { } - assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next - sync posedge \coresync_clk - update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:134039.3-134040.53" - process $proc$libresoc.v:134039$6542 - assign { } { } - assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next - sync posedge \coresync_clk - update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:134041.3-134042.53" - process $proc$libresoc.v:134041$6543 - assign { } { } - assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next - sync posedge \coresync_clk - update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:134043.3-134044.59" - process $proc$libresoc.v:134043$6544 - assign { } { } - assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next - sync posedge \coresync_clk - update \logical_op__invert_in $0\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:134045.3-134046.53" - process $proc$libresoc.v:134045$6545 - assign { } { } - assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next - sync posedge \coresync_clk - update \logical_op__zero_a $0\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:134047.3-134048.63" - process $proc$libresoc.v:134047$6546 - assign { } { } - assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next - sync posedge \coresync_clk - update \logical_op__input_carry $0\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:134049.3-134050.61" - process $proc$libresoc.v:134049$6547 - assign { } { } - assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next - sync posedge \coresync_clk - update \logical_op__invert_out $0\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:134051.3-134052.59" - process $proc$libresoc.v:134051$6548 - assign { } { } - assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next - sync posedge \coresync_clk - update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:134053.3-134054.65" - process $proc$libresoc.v:134053$6549 - assign { } { } - assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next - sync posedge \coresync_clk - update \logical_op__output_carry $0\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:134055.3-134056.57" - process $proc$libresoc.v:134055$6550 - assign { } { } - assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next - sync posedge \coresync_clk - update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:134057.3-134058.59" - process $proc$libresoc.v:134057$6551 - assign { } { } - assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next - sync posedge \coresync_clk - update \logical_op__is_signed $0\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:134059.3-134060.57" - process $proc$libresoc.v:134059$6552 - assign { } { } - assign $0\logical_op__data_len[3:0] \logical_op__data_len$next - sync posedge \coresync_clk - update \logical_op__data_len $0\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:134061.3-134062.49" - process $proc$libresoc.v:134061$6553 - assign { } { } - assign $0\logical_op__insn[31:0] \logical_op__insn$next - sync posedge \coresync_clk - update \logical_op__insn $0\logical_op__insn[31:0] - end - attribute \src "libresoc.v:134063.3-134064.27" - process $proc$libresoc.v:134063$6554 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:134065.3-134066.29" - process $proc$libresoc.v:134065$6555 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:134167.3-134184.6" - process $proc$libresoc.v:134167$6556 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$6557 $2\r_busy$next[0:0]$6559 - attribute \src "libresoc.v:134168.5-134168.29" - switch \initial - attribute \src "libresoc.v:134168.9-134168.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$6558 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$6558 1'0 - case - assign $1\r_busy$next[0:0]$6558 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$6559 1'0 - case - assign $2\r_busy$next[0:0]$6559 $1\r_busy$next[0:0]$6558 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$6557 - end - attribute \src "libresoc.v:134185.3-134197.6" - process $proc$libresoc.v:134185$6560 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$6561 $1\muxid$next[1:0]$6562 - attribute \src "libresoc.v:134186.5-134186.29" - switch \initial - attribute \src "libresoc.v:134186.9-134186.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$6562 \muxid$66 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$6562 \muxid$66 - case - assign $1\muxid$next[1:0]$6562 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$6561 - end - attribute \src "libresoc.v:134198.3-134239.6" - process $proc$libresoc.v:134198$6563 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$next[3:0]$6564 $1\logical_op__data_len$next[3:0]$6582 - assign $0\logical_op__fn_unit$next[11:0]$6565 $1\logical_op__fn_unit$next[11:0]$6583 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6568 $1\logical_op__input_carry$next[1:0]$6586 - assign $0\logical_op__insn$next[31:0]$6569 $1\logical_op__insn$next[31:0]$6587 - assign $0\logical_op__insn_type$next[6:0]$6570 $1\logical_op__insn_type$next[6:0]$6588 - assign $0\logical_op__invert_in$next[0:0]$6571 $1\logical_op__invert_in$next[0:0]$6589 - assign $0\logical_op__invert_out$next[0:0]$6572 $1\logical_op__invert_out$next[0:0]$6590 - assign $0\logical_op__is_32bit$next[0:0]$6573 $1\logical_op__is_32bit$next[0:0]$6591 - assign $0\logical_op__is_signed$next[0:0]$6574 $1\logical_op__is_signed$next[0:0]$6592 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6577 $1\logical_op__output_carry$next[0:0]$6595 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6580 $1\logical_op__write_cr0$next[0:0]$6598 - assign $0\logical_op__zero_a$next[0:0]$6581 $1\logical_op__zero_a$next[0:0]$6599 - assign $0\logical_op__imm_data__data$next[63:0]$6566 $2\logical_op__imm_data__data$next[63:0]$6600 - assign $0\logical_op__imm_data__ok$next[0:0]$6567 $2\logical_op__imm_data__ok$next[0:0]$6601 - assign $0\logical_op__oe__oe$next[0:0]$6575 $2\logical_op__oe__oe$next[0:0]$6602 - assign $0\logical_op__oe__ok$next[0:0]$6576 $2\logical_op__oe__ok$next[0:0]$6603 - assign $0\logical_op__rc__ok$next[0:0]$6578 $2\logical_op__rc__ok$next[0:0]$6604 - assign $0\logical_op__rc__rc$next[0:0]$6579 $2\logical_op__rc__rc$next[0:0]$6605 - attribute \src "libresoc.v:134199.5-134199.29" - switch \initial - attribute \src "libresoc.v:134199.9-134199.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$6587 $1\logical_op__data_len$next[3:0]$6582 $1\logical_op__is_signed$next[0:0]$6592 $1\logical_op__is_32bit$next[0:0]$6591 $1\logical_op__output_carry$next[0:0]$6595 $1\logical_op__write_cr0$next[0:0]$6598 $1\logical_op__invert_out$next[0:0]$6590 $1\logical_op__input_carry$next[1:0]$6586 $1\logical_op__zero_a$next[0:0]$6599 $1\logical_op__invert_in$next[0:0]$6589 $1\logical_op__oe__ok$next[0:0]$6594 $1\logical_op__oe__oe$next[0:0]$6593 $1\logical_op__rc__ok$next[0:0]$6596 $1\logical_op__rc__rc$next[0:0]$6597 $1\logical_op__imm_data__ok$next[0:0]$6585 $1\logical_op__imm_data__data$next[63:0]$6584 $1\logical_op__fn_unit$next[11:0]$6583 $1\logical_op__insn_type$next[6:0]$6588 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$next[31:0]$6587 $1\logical_op__data_len$next[3:0]$6582 $1\logical_op__is_signed$next[0:0]$6592 $1\logical_op__is_32bit$next[0:0]$6591 $1\logical_op__output_carry$next[0:0]$6595 $1\logical_op__write_cr0$next[0:0]$6598 $1\logical_op__invert_out$next[0:0]$6590 $1\logical_op__input_carry$next[1:0]$6586 $1\logical_op__zero_a$next[0:0]$6599 $1\logical_op__invert_in$next[0:0]$6589 $1\logical_op__oe__ok$next[0:0]$6594 $1\logical_op__oe__oe$next[0:0]$6593 $1\logical_op__rc__ok$next[0:0]$6596 $1\logical_op__rc__rc$next[0:0]$6597 $1\logical_op__imm_data__ok$next[0:0]$6585 $1\logical_op__imm_data__data$next[63:0]$6584 $1\logical_op__fn_unit$next[11:0]$6583 $1\logical_op__insn_type$next[6:0]$6588 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } - case - assign $1\logical_op__data_len$next[3:0]$6582 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$6583 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6584 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6585 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6586 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6587 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6588 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6589 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6590 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6591 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6592 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6593 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6594 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6595 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6596 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6597 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6598 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6599 \logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6600 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6601 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6605 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6604 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6602 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6603 1'0 - case - assign $2\logical_op__imm_data__data$next[63:0]$6600 $1\logical_op__imm_data__data$next[63:0]$6584 - assign $2\logical_op__imm_data__ok$next[0:0]$6601 $1\logical_op__imm_data__ok$next[0:0]$6585 - assign $2\logical_op__oe__oe$next[0:0]$6602 $1\logical_op__oe__oe$next[0:0]$6593 - assign $2\logical_op__oe__ok$next[0:0]$6603 $1\logical_op__oe__ok$next[0:0]$6594 - assign $2\logical_op__rc__ok$next[0:0]$6604 $1\logical_op__rc__ok$next[0:0]$6596 - assign $2\logical_op__rc__rc$next[0:0]$6605 $1\logical_op__rc__rc$next[0:0]$6597 - end - sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6564 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$6565 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6566 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6567 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6568 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6569 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6570 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6571 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6572 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6573 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6574 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6575 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6576 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6577 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6578 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6579 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6580 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6581 - end - attribute \src "libresoc.v:134240.3-134258.6" - process $proc$libresoc.v:134240$6606 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$6607 $1\o$next[63:0]$6609 - assign { } { } - assign $0\o_ok$next[0:0]$6608 $2\o_ok$next[0:0]$6611 - attribute \src "libresoc.v:134241.5-134241.29" - switch \initial - attribute \src "libresoc.v:134241.9-134241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$6610 $1\o$next[63:0]$6609 } { \o_ok$86 \o$85 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$6610 $1\o$next[63:0]$6609 } { \o_ok$86 \o$85 } - case - assign $1\o$next[63:0]$6609 \o - assign $1\o_ok$next[0:0]$6610 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$6611 1'0 - case - assign $2\o_ok$next[0:0]$6611 $1\o_ok$next[0:0]$6610 - end - sync always - update \o$next $0\o$next[63:0]$6607 - update \o_ok$next $0\o_ok$next[0:0]$6608 - end - attribute \src "libresoc.v:134259.3-134277.6" - process $proc$libresoc.v:134259$6612 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$6613 $1\cr_a$next[3:0]$6615 - assign { } { } - assign $0\cr_a_ok$next[0:0]$6614 $2\cr_a_ok$next[0:0]$6617 - attribute \src "libresoc.v:134260.5-134260.29" - switch \initial - attribute \src "libresoc.v:134260.9-134260.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$6616 $1\cr_a$next[3:0]$6615 } { \cr_a_ok$88 \cr_a$87 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$6616 $1\cr_a$next[3:0]$6615 } { \cr_a_ok$88 \cr_a$87 } - case - assign $1\cr_a$next[3:0]$6615 \cr_a - assign $1\cr_a_ok$next[0:0]$6616 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$6617 1'0 - case - assign $2\cr_a_ok$next[0:0]$6617 $1\cr_a_ok$next[0:0]$6616 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$6613 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6614 - end - attribute \src "libresoc.v:134278.3-134296.6" - process $proc$libresoc.v:134278$6618 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$6619 $1\xer_so$next[0:0]$6621 - assign { } { } - assign $0\xer_so_ok$next[0:0]$6620 $2\xer_so_ok$next[0:0]$6623 - attribute \src "libresoc.v:134279.5-134279.29" - switch \initial - attribute \src "libresoc.v:134279.9-134279.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$6622 $1\xer_so$next[0:0]$6621 } { \xer_so_ok$92 \xer_so$91 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$6622 $1\xer_so$next[0:0]$6621 } { \xer_so_ok$92 \xer_so$91 } - case - assign $1\xer_so$next[0:0]$6621 \xer_so - assign $1\xer_so_ok$next[0:0]$6622 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$6623 1'0 - case - assign $2\xer_so_ok$next[0:0]$6623 $1\xer_so_ok$next[0:0]$6622 - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$6619 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6620 - end - connect \$64 $and$libresoc.v:134014$6529_Y - connect \cr_a$89 4'0000 - connect \cr_a_ok$90 1'0 - connect \xer_so_ok$93 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } - connect { \cr_a_ok$88 \cr_a$87 } 5'00000 - connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } - connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } - connect \muxid$66 \main_muxid$43 - connect \p_valid_i_p_ready_o \$64 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$63 \p_valid_i - connect \main_xer_so \input_xer_so$42 - connect \main_rb \input_rb$41 - connect \main_ra \input_ra$40 - connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } - connect \main_muxid \input_muxid$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:134324.1-135342.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" -attribute \generator "nMigen" -module \logical_pipe2 - attribute \src "libresoc.v:135309.3-135327.6" - wire width 4 $0\cr_a$22$next[3:0]$6756 - attribute \src "libresoc.v:135113.3-135114.33" - wire width 4 $0\cr_a$22[3:0]$6653 - attribute \src "libresoc.v:134336.13-134336.29" - wire width 4 $0\cr_a$22[3:0]$6763 - attribute \src "libresoc.v:135309.3-135327.6" - wire $0\cr_a_ok$23$next[0:0]$6757 - attribute \src "libresoc.v:135115.3-135116.39" - wire $0\cr_a_ok$23[0:0]$6655 - attribute \src "libresoc.v:134345.7-134345.26" - wire $0\cr_a_ok$23[0:0]$6765 - attribute \src "libresoc.v:134325.7-134325.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:135248.3-135289.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$6707 - attribute \src "libresoc.v:135153.3-135154.65" - wire width 4 $0\logical_op__data_len$18[3:0]$6693 - attribute \src "libresoc.v:134356.13-134356.45" - wire width 4 $0\logical_op__data_len$18[3:0]$6767 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6708 - attribute \src "libresoc.v:135123.3-135124.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$6663 - attribute \src "libresoc.v:134391.14-134391.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$6769 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6709 - attribute \src "libresoc.v:135125.3-135126.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6665 - attribute \src "libresoc.v:134413.14-134413.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6771 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$6710 - attribute \src "libresoc.v:135127.3-135128.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6667 - attribute \src "libresoc.v:134422.7-134422.42" - wire $0\logical_op__imm_data__ok$5[0:0]$6773 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$6711 - attribute \src "libresoc.v:135141.3-135142.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$6681 - attribute \src "libresoc.v:134439.13-134439.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$6775 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$6712 - attribute \src "libresoc.v:135155.3-135156.57" - wire width 32 $0\logical_op__insn$19[31:0]$6695 - attribute \src "libresoc.v:134452.14-134452.43" - wire width 32 $0\logical_op__insn$19[31:0]$6777 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$6713 - attribute \src "libresoc.v:135121.3-135122.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6661 - attribute \src "libresoc.v:134609.13-134609.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$6779 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__invert_in$10$next[0:0]$6714 - attribute \src "libresoc.v:135137.3-135138.67" - wire $0\logical_op__invert_in$10[0:0]$6677 - attribute \src "libresoc.v:134692.7-134692.40" - wire $0\logical_op__invert_in$10[0:0]$6781 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__invert_out$13$next[0:0]$6715 - attribute \src "libresoc.v:135143.3-135144.69" - wire $0\logical_op__invert_out$13[0:0]$6683 - attribute \src "libresoc.v:134701.7-134701.41" - wire $0\logical_op__invert_out$13[0:0]$6783 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__is_32bit$16$next[0:0]$6716 - attribute \src "libresoc.v:135149.3-135150.65" - wire $0\logical_op__is_32bit$16[0:0]$6689 - attribute \src "libresoc.v:134710.7-134710.39" - wire $0\logical_op__is_32bit$16[0:0]$6785 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__is_signed$17$next[0:0]$6717 - attribute \src "libresoc.v:135151.3-135152.67" - wire $0\logical_op__is_signed$17[0:0]$6691 - attribute \src "libresoc.v:134719.7-134719.40" - wire $0\logical_op__is_signed$17[0:0]$6787 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__oe__oe$8$next[0:0]$6718 - attribute \src "libresoc.v:135133.3-135134.59" - wire $0\logical_op__oe__oe$8[0:0]$6673 - attribute \src "libresoc.v:134730.7-134730.36" - wire $0\logical_op__oe__oe$8[0:0]$6789 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__oe__ok$9$next[0:0]$6719 - attribute \src "libresoc.v:135135.3-135136.59" - wire $0\logical_op__oe__ok$9[0:0]$6675 - attribute \src "libresoc.v:134739.7-134739.36" - wire $0\logical_op__oe__ok$9[0:0]$6791 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__output_carry$15$next[0:0]$6720 - attribute \src "libresoc.v:135147.3-135148.73" - wire $0\logical_op__output_carry$15[0:0]$6687 - attribute \src "libresoc.v:134746.7-134746.43" - wire $0\logical_op__output_carry$15[0:0]$6793 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__rc__ok$7$next[0:0]$6721 - attribute \src "libresoc.v:135131.3-135132.59" - wire $0\logical_op__rc__ok$7[0:0]$6671 - attribute \src "libresoc.v:134757.7-134757.36" - wire $0\logical_op__rc__ok$7[0:0]$6795 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__rc__rc$6$next[0:0]$6722 - attribute \src "libresoc.v:135129.3-135130.59" - wire $0\logical_op__rc__rc$6[0:0]$6669 - attribute \src "libresoc.v:134766.7-134766.36" - wire $0\logical_op__rc__rc$6[0:0]$6797 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__write_cr0$14$next[0:0]$6723 - attribute \src "libresoc.v:135145.3-135146.67" - wire $0\logical_op__write_cr0$14[0:0]$6685 - attribute \src "libresoc.v:134773.7-134773.40" - wire $0\logical_op__write_cr0$14[0:0]$6799 - attribute \src "libresoc.v:135248.3-135289.6" - wire $0\logical_op__zero_a$11$next[0:0]$6724 - attribute \src "libresoc.v:135139.3-135140.61" - wire $0\logical_op__zero_a$11[0:0]$6679 - attribute \src "libresoc.v:134782.7-134782.37" - wire $0\logical_op__zero_a$11[0:0]$6801 - attribute \src "libresoc.v:135235.3-135247.6" - wire width 2 $0\muxid$1$next[1:0]$6704 - attribute \src "libresoc.v:135157.3-135158.33" - wire width 2 $0\muxid$1[1:0]$6697 - attribute \src "libresoc.v:134791.13-134791.29" - wire width 2 $0\muxid$1[1:0]$6803 - attribute \src "libresoc.v:135290.3-135308.6" - wire width 64 $0\o$20$next[63:0]$6750 - attribute \src "libresoc.v:135117.3-135118.27" - wire width 64 $0\o$20[63:0]$6657 - attribute \src "libresoc.v:134806.14-134806.43" - wire width 64 $0\o$20[63:0]$6805 - attribute \src "libresoc.v:135290.3-135308.6" - wire $0\o_ok$21$next[0:0]$6751 - attribute \src "libresoc.v:135119.3-135120.33" - wire $0\o_ok$21[0:0]$6659 - attribute \src "libresoc.v:134815.7-134815.23" - wire $0\o_ok$21[0:0]$6807 - attribute \src "libresoc.v:135217.3-135234.6" - wire $0\r_busy$next[0:0]$6700 - attribute \src "libresoc.v:135159.3-135160.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:135309.3-135327.6" - wire width 4 $1\cr_a$22$next[3:0]$6758 - attribute \src "libresoc.v:135309.3-135327.6" - wire $1\cr_a_ok$23$next[0:0]$6759 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$6725 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6726 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6727 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$6728 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$6729 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$6730 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$6731 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__invert_in$10$next[0:0]$6732 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__invert_out$13$next[0:0]$6733 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__is_32bit$16$next[0:0]$6734 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__is_signed$17$next[0:0]$6735 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__oe__oe$8$next[0:0]$6736 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__oe__ok$9$next[0:0]$6737 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__output_carry$15$next[0:0]$6738 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__rc__ok$7$next[0:0]$6739 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__rc__rc$6$next[0:0]$6740 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__write_cr0$14$next[0:0]$6741 - attribute \src "libresoc.v:135248.3-135289.6" - wire $1\logical_op__zero_a$11$next[0:0]$6742 - attribute \src "libresoc.v:135235.3-135247.6" - wire width 2 $1\muxid$1$next[1:0]$6705 - attribute \src "libresoc.v:135290.3-135308.6" - wire width 64 $1\o$20$next[63:0]$6752 - attribute \src "libresoc.v:135290.3-135308.6" - wire $1\o_ok$21$next[0:0]$6753 - attribute \src "libresoc.v:135217.3-135234.6" - wire $1\r_busy$next[0:0]$6701 - attribute \src "libresoc.v:135103.7-135103.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:135309.3-135327.6" - wire $2\cr_a_ok$23$next[0:0]$6760 - attribute \src "libresoc.v:135248.3-135289.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6743 - attribute \src "libresoc.v:135248.3-135289.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$6744 - attribute \src "libresoc.v:135248.3-135289.6" - wire $2\logical_op__oe__oe$8$next[0:0]$6745 - attribute \src "libresoc.v:135248.3-135289.6" - wire $2\logical_op__oe__ok$9$next[0:0]$6746 - attribute \src "libresoc.v:135248.3-135289.6" - wire $2\logical_op__rc__ok$7$next[0:0]$6747 - attribute \src "libresoc.v:135248.3-135289.6" - wire $2\logical_op__rc__rc$6$next[0:0]$6748 - attribute \src "libresoc.v:135290.3-135308.6" - wire $2\o_ok$21$next[0:0]$6754 - attribute \src "libresoc.v:135217.3-135234.6" - wire $2\r_busy$next[0:0]$6702 - attribute \src "libresoc.v:135112.18-135112.118" - wire $and$libresoc.v:135112$6651_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 52 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 53 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$73 - attribute \src "libresoc.v:134325.7-134325.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 48 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$68 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 33 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 34 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$55 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 42 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 49 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$69 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 32 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 31 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 30 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 29 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 50 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 51 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_logical_op__data_len$41 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_logical_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_logical_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__imm_data__ok$28 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_logical_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_logical_op__insn$42 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_logical_op__insn_type$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__invert_out$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 27 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 28 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:135112$6651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$48 - connect \B \p_ready_o - connect \Y $and$libresoc.v:135112$6651_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135161.10-135164.4" - cell \n$53 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135165.15-135212.4" - cell \output$54 \output - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$45 - connect \cr_a_ok \output_cr_a_ok - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__data_len$18 \output_logical_op__data_len$41 - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 - connect \logical_op__imm_data__data \output_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 - connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 - connect \logical_op__insn \output_logical_op__insn - connect \logical_op__insn$19 \output_logical_op__insn$42 - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 - connect \logical_op__invert_in \output_logical_op__invert_in - connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 - connect \logical_op__oe__ok \output_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 - connect \logical_op__rc__ok \output_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$24 - connect \o \output_o - connect \o$20 \output_o$43 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$44 - connect \xer_so \output_xer_so - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:135213.10-135216.4" - cell \p$52 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:134325.7-134325.20" - process $proc$libresoc.v:134325$6761 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:134336.13-134336.29" - process $proc$libresoc.v:134336$6762 - assign { } { } - assign $0\cr_a$22[3:0]$6763 4'0000 - sync always - sync init - update \cr_a$22 $0\cr_a$22[3:0]$6763 - end - attribute \src "libresoc.v:134345.7-134345.26" - process $proc$libresoc.v:134345$6764 - assign { } { } - assign $0\cr_a_ok$23[0:0]$6765 1'0 - sync always - sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6765 - end - attribute \src "libresoc.v:134356.13-134356.45" - process $proc$libresoc.v:134356$6766 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$6767 4'0000 - sync always - sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6767 - end - attribute \src "libresoc.v:134391.14-134391.47" - process $proc$libresoc.v:134391$6768 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$6769 12'000000000000 - sync always - sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6769 - end - attribute \src "libresoc.v:134413.14-134413.67" - process $proc$libresoc.v:134413$6770 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6771 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6771 - end - attribute \src "libresoc.v:134422.7-134422.42" - process $proc$libresoc.v:134422$6772 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6773 1'0 - sync always - sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6773 - end - attribute \src "libresoc.v:134439.13-134439.48" - process $proc$libresoc.v:134439$6774 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6775 2'00 - sync always - sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6775 - end - attribute \src "libresoc.v:134452.14-134452.43" - process $proc$libresoc.v:134452$6776 - assign { } { } - assign $0\logical_op__insn$19[31:0]$6777 0 - sync always - sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6777 - end - attribute \src "libresoc.v:134609.13-134609.46" - process $proc$libresoc.v:134609$6778 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6779 7'0000000 - sync always - sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6779 - end - attribute \src "libresoc.v:134692.7-134692.40" - process $proc$libresoc.v:134692$6780 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6781 1'0 - sync always - sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6781 - end - attribute \src "libresoc.v:134701.7-134701.41" - process $proc$libresoc.v:134701$6782 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6783 1'0 - sync always - sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6783 - end - attribute \src "libresoc.v:134710.7-134710.39" - process $proc$libresoc.v:134710$6784 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6785 1'0 - sync always - sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6785 - end - attribute \src "libresoc.v:134719.7-134719.40" - process $proc$libresoc.v:134719$6786 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6787 1'0 - sync always - sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6787 - end - attribute \src "libresoc.v:134730.7-134730.36" - process $proc$libresoc.v:134730$6788 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6789 1'0 - sync always - sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6789 - end - attribute \src "libresoc.v:134739.7-134739.36" - process $proc$libresoc.v:134739$6790 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6791 1'0 - sync always - sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6791 - end - attribute \src "libresoc.v:134746.7-134746.43" - process $proc$libresoc.v:134746$6792 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6793 1'0 - sync always - sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6793 - end - attribute \src "libresoc.v:134757.7-134757.36" - process $proc$libresoc.v:134757$6794 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6795 1'0 - sync always - sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6795 - end - attribute \src "libresoc.v:134766.7-134766.36" - process $proc$libresoc.v:134766$6796 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6797 1'0 - sync always - sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6797 - end - attribute \src "libresoc.v:134773.7-134773.40" - process $proc$libresoc.v:134773$6798 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6799 1'0 - sync always - sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6799 - end - attribute \src "libresoc.v:134782.7-134782.37" - process $proc$libresoc.v:134782$6800 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6801 1'0 - sync always - sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6801 - end - attribute \src "libresoc.v:134791.13-134791.29" - process $proc$libresoc.v:134791$6802 - assign { } { } - assign $0\muxid$1[1:0]$6803 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$6803 - end - attribute \src "libresoc.v:134806.14-134806.43" - process $proc$libresoc.v:134806$6804 - assign { } { } - assign $0\o$20[63:0]$6805 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$20 $0\o$20[63:0]$6805 - end - attribute \src "libresoc.v:134815.7-134815.23" - process $proc$libresoc.v:134815$6806 - assign { } { } - assign $0\o_ok$21[0:0]$6807 1'0 - sync always - sync init - update \o_ok$21 $0\o_ok$21[0:0]$6807 - end - attribute \src "libresoc.v:135103.7-135103.20" - process $proc$libresoc.v:135103$6808 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:135113.3-135114.33" - process $proc$libresoc.v:135113$6652 - assign { } { } - assign $0\cr_a$22[3:0]$6653 \cr_a$22$next - sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6653 - end - attribute \src "libresoc.v:135115.3-135116.39" - process $proc$libresoc.v:135115$6654 - assign { } { } - assign $0\cr_a_ok$23[0:0]$6655 \cr_a_ok$23$next - sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6655 - end - attribute \src "libresoc.v:135117.3-135118.27" - process $proc$libresoc.v:135117$6656 - assign { } { } - assign $0\o$20[63:0]$6657 \o$20$next - sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6657 - end - attribute \src "libresoc.v:135119.3-135120.33" - process $proc$libresoc.v:135119$6658 - assign { } { } - assign $0\o_ok$21[0:0]$6659 \o_ok$21$next - sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6659 - end - attribute \src "libresoc.v:135121.3-135122.65" - process $proc$libresoc.v:135121$6660 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6661 \logical_op__insn_type$2$next - sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6661 - end - attribute \src "libresoc.v:135123.3-135124.61" - process $proc$libresoc.v:135123$6662 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$6663 \logical_op__fn_unit$3$next - sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6663 - end - attribute \src "libresoc.v:135125.3-135126.75" - process $proc$libresoc.v:135125$6664 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6665 \logical_op__imm_data__data$4$next - sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6665 - end - attribute \src "libresoc.v:135127.3-135128.71" - process $proc$libresoc.v:135127$6666 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6667 \logical_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6667 - end - attribute \src "libresoc.v:135129.3-135130.59" - process $proc$libresoc.v:135129$6668 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6669 \logical_op__rc__rc$6$next - sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6669 - end - attribute \src "libresoc.v:135131.3-135132.59" - process $proc$libresoc.v:135131$6670 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$6671 \logical_op__rc__ok$7$next - sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6671 - end - attribute \src "libresoc.v:135133.3-135134.59" - process $proc$libresoc.v:135133$6672 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$6673 \logical_op__oe__oe$8$next - sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6673 - end - attribute \src "libresoc.v:135135.3-135136.59" - process $proc$libresoc.v:135135$6674 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$6675 \logical_op__oe__ok$9$next - sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6675 - end - attribute \src "libresoc.v:135137.3-135138.67" - process $proc$libresoc.v:135137$6676 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$6677 \logical_op__invert_in$10$next - sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6677 - end - attribute \src "libresoc.v:135139.3-135140.61" - process $proc$libresoc.v:135139$6678 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$6679 \logical_op__zero_a$11$next - sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6679 - end - attribute \src "libresoc.v:135141.3-135142.71" - process $proc$libresoc.v:135141$6680 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$6681 \logical_op__input_carry$12$next - sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6681 - end - attribute \src "libresoc.v:135143.3-135144.69" - process $proc$libresoc.v:135143$6682 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$6683 \logical_op__invert_out$13$next - sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6683 - end - attribute \src "libresoc.v:135145.3-135146.67" - process $proc$libresoc.v:135145$6684 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$6685 \logical_op__write_cr0$14$next - sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6685 - end - attribute \src "libresoc.v:135147.3-135148.73" - process $proc$libresoc.v:135147$6686 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$6687 \logical_op__output_carry$15$next - sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6687 - end - attribute \src "libresoc.v:135149.3-135150.65" - process $proc$libresoc.v:135149$6688 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$6689 \logical_op__is_32bit$16$next - sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6689 - end - attribute \src "libresoc.v:135151.3-135152.67" - process $proc$libresoc.v:135151$6690 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$6691 \logical_op__is_signed$17$next - sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6691 - end - attribute \src "libresoc.v:135153.3-135154.65" - process $proc$libresoc.v:135153$6692 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$6693 \logical_op__data_len$18$next - sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6693 - end - attribute \src "libresoc.v:135155.3-135156.57" - process $proc$libresoc.v:135155$6694 - assign { } { } - assign $0\logical_op__insn$19[31:0]$6695 \logical_op__insn$19$next - sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6695 - end - attribute \src "libresoc.v:135157.3-135158.33" - process $proc$libresoc.v:135157$6696 - assign { } { } - assign $0\muxid$1[1:0]$6697 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$6697 - end - attribute \src "libresoc.v:135159.3-135160.29" - process $proc$libresoc.v:135159$6698 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:135217.3-135234.6" - process $proc$libresoc.v:135217$6699 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$6700 $2\r_busy$next[0:0]$6702 - attribute \src "libresoc.v:135218.5-135218.29" - switch \initial - attribute \src "libresoc.v:135218.9-135218.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$6701 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$6701 1'0 - case - assign $1\r_busy$next[0:0]$6701 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$6702 1'0 - case - assign $2\r_busy$next[0:0]$6702 $1\r_busy$next[0:0]$6701 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$6700 - end - attribute \src "libresoc.v:135235.3-135247.6" - process $proc$libresoc.v:135235$6703 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$6704 $1\muxid$1$next[1:0]$6705 - attribute \src "libresoc.v:135236.5-135236.29" - switch \initial - attribute \src "libresoc.v:135236.9-135236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$6705 \muxid$51 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$6705 \muxid$51 - case - assign $1\muxid$1$next[1:0]$6705 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$6704 - end - attribute \src "libresoc.v:135248.3-135289.6" - process $proc$libresoc.v:135248$6706 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$6707 $1\logical_op__data_len$18$next[3:0]$6725 - assign $0\logical_op__fn_unit$3$next[11:0]$6708 $1\logical_op__fn_unit$3$next[11:0]$6726 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$6711 $1\logical_op__input_carry$12$next[1:0]$6729 - assign $0\logical_op__insn$19$next[31:0]$6712 $1\logical_op__insn$19$next[31:0]$6730 - assign $0\logical_op__insn_type$2$next[6:0]$6713 $1\logical_op__insn_type$2$next[6:0]$6731 - assign $0\logical_op__invert_in$10$next[0:0]$6714 $1\logical_op__invert_in$10$next[0:0]$6732 - assign $0\logical_op__invert_out$13$next[0:0]$6715 $1\logical_op__invert_out$13$next[0:0]$6733 - assign $0\logical_op__is_32bit$16$next[0:0]$6716 $1\logical_op__is_32bit$16$next[0:0]$6734 - assign $0\logical_op__is_signed$17$next[0:0]$6717 $1\logical_op__is_signed$17$next[0:0]$6735 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$6720 $1\logical_op__output_carry$15$next[0:0]$6738 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$6723 $1\logical_op__write_cr0$14$next[0:0]$6741 - assign $0\logical_op__zero_a$11$next[0:0]$6724 $1\logical_op__zero_a$11$next[0:0]$6742 - assign $0\logical_op__imm_data__data$4$next[63:0]$6709 $2\logical_op__imm_data__data$4$next[63:0]$6743 - assign $0\logical_op__imm_data__ok$5$next[0:0]$6710 $2\logical_op__imm_data__ok$5$next[0:0]$6744 - assign $0\logical_op__oe__oe$8$next[0:0]$6718 $2\logical_op__oe__oe$8$next[0:0]$6745 - assign $0\logical_op__oe__ok$9$next[0:0]$6719 $2\logical_op__oe__ok$9$next[0:0]$6746 - assign $0\logical_op__rc__ok$7$next[0:0]$6721 $2\logical_op__rc__ok$7$next[0:0]$6747 - assign $0\logical_op__rc__rc$6$next[0:0]$6722 $2\logical_op__rc__rc$6$next[0:0]$6748 - attribute \src "libresoc.v:135249.5-135249.29" - switch \initial - attribute \src "libresoc.v:135249.9-135249.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6730 $1\logical_op__data_len$18$next[3:0]$6725 $1\logical_op__is_signed$17$next[0:0]$6735 $1\logical_op__is_32bit$16$next[0:0]$6734 $1\logical_op__output_carry$15$next[0:0]$6738 $1\logical_op__write_cr0$14$next[0:0]$6741 $1\logical_op__invert_out$13$next[0:0]$6733 $1\logical_op__input_carry$12$next[1:0]$6729 $1\logical_op__zero_a$11$next[0:0]$6742 $1\logical_op__invert_in$10$next[0:0]$6732 $1\logical_op__oe__ok$9$next[0:0]$6737 $1\logical_op__oe__oe$8$next[0:0]$6736 $1\logical_op__rc__ok$7$next[0:0]$6739 $1\logical_op__rc__rc$6$next[0:0]$6740 $1\logical_op__imm_data__ok$5$next[0:0]$6728 $1\logical_op__imm_data__data$4$next[63:0]$6727 $1\logical_op__fn_unit$3$next[11:0]$6726 $1\logical_op__insn_type$2$next[6:0]$6731 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$6730 $1\logical_op__data_len$18$next[3:0]$6725 $1\logical_op__is_signed$17$next[0:0]$6735 $1\logical_op__is_32bit$16$next[0:0]$6734 $1\logical_op__output_carry$15$next[0:0]$6738 $1\logical_op__write_cr0$14$next[0:0]$6741 $1\logical_op__invert_out$13$next[0:0]$6733 $1\logical_op__input_carry$12$next[1:0]$6729 $1\logical_op__zero_a$11$next[0:0]$6742 $1\logical_op__invert_in$10$next[0:0]$6732 $1\logical_op__oe__ok$9$next[0:0]$6737 $1\logical_op__oe__oe$8$next[0:0]$6736 $1\logical_op__rc__ok$7$next[0:0]$6739 $1\logical_op__rc__rc$6$next[0:0]$6740 $1\logical_op__imm_data__ok$5$next[0:0]$6728 $1\logical_op__imm_data__data$4$next[63:0]$6727 $1\logical_op__fn_unit$3$next[11:0]$6726 $1\logical_op__insn_type$2$next[6:0]$6731 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } - case - assign $1\logical_op__data_len$18$next[3:0]$6725 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$6726 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$6727 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$6728 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$6729 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$6730 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$6731 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$6732 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$6733 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$6734 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$6735 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$6736 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$6737 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$6738 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$6739 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$6740 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$6741 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$6742 \logical_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$6743 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6744 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$6748 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$6747 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$6745 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$6746 1'0 - case - assign $2\logical_op__imm_data__data$4$next[63:0]$6743 $1\logical_op__imm_data__data$4$next[63:0]$6727 - assign $2\logical_op__imm_data__ok$5$next[0:0]$6744 $1\logical_op__imm_data__ok$5$next[0:0]$6728 - assign $2\logical_op__oe__oe$8$next[0:0]$6745 $1\logical_op__oe__oe$8$next[0:0]$6736 - assign $2\logical_op__oe__ok$9$next[0:0]$6746 $1\logical_op__oe__ok$9$next[0:0]$6737 - assign $2\logical_op__rc__ok$7$next[0:0]$6747 $1\logical_op__rc__ok$7$next[0:0]$6739 - assign $2\logical_op__rc__rc$6$next[0:0]$6748 $1\logical_op__rc__rc$6$next[0:0]$6740 - end - sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6707 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6708 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6709 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6710 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6711 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6712 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6713 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6714 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6715 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6716 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6717 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6718 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6719 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6720 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6721 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6722 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6723 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6724 - end - attribute \src "libresoc.v:135290.3-135308.6" - process $proc$libresoc.v:135290$6749 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$6750 $1\o$20$next[63:0]$6752 - assign { } { } - assign $0\o_ok$21$next[0:0]$6751 $2\o_ok$21$next[0:0]$6754 - attribute \src "libresoc.v:135291.5-135291.29" - switch \initial - attribute \src "libresoc.v:135291.9-135291.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$6753 $1\o$20$next[63:0]$6752 } { \o_ok$71 \o$70 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$21$next[0:0]$6753 $1\o$20$next[63:0]$6752 } { \o_ok$71 \o$70 } - case - assign $1\o$20$next[63:0]$6752 \o$20 - assign $1\o_ok$21$next[0:0]$6753 \o_ok$21 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$21$next[0:0]$6754 1'0 - case - assign $2\o_ok$21$next[0:0]$6754 $1\o_ok$21$next[0:0]$6753 - end - sync always - update \o$20$next $0\o$20$next[63:0]$6750 - update \o_ok$21$next $0\o_ok$21$next[0:0]$6751 - end - attribute \src "libresoc.v:135309.3-135327.6" - process $proc$libresoc.v:135309$6755 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$6756 $1\cr_a$22$next[3:0]$6758 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$6757 $2\cr_a_ok$23$next[0:0]$6760 - attribute \src "libresoc.v:135310.5-135310.29" - switch \initial - attribute \src "libresoc.v:135310.9-135310.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6759 $1\cr_a$22$next[3:0]$6758 } { \cr_a_ok$73 \cr_a$72 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$6759 $1\cr_a$22$next[3:0]$6758 } { \cr_a_ok$73 \cr_a$72 } - case - assign $1\cr_a$22$next[3:0]$6758 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$6759 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$23$next[0:0]$6760 1'0 - case - assign $2\cr_a_ok$23$next[0:0]$6760 $1\cr_a_ok$23$next[0:0]$6759 - end - sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$6756 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6757 - end - connect \$49 $and$libresoc.v:135112$6651_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } - connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } - connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } - connect \muxid$51 \output_muxid$24 - connect \p_valid_i_p_ready_o \$49 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$48 \p_valid_i - connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \output_muxid \muxid -end -attribute \src "ls180.v:4.1-10571.10" -attribute \cells_not_processed 1 -module \ls180 - attribute \src "ls180.v:10056.1-10066.4" - wire width 7 $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 - attribute \src "ls180.v:10056.1-10066.4" - wire width 7 $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 - attribute \src "ls180.v:10056.1-10066.4" - wire width 7 $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 - attribute \src "ls180.v:10056.1-10066.4" - wire width 7 $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 - attribute \src "ls180.v:10056.1-10066.4" - wire width 32 $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 - attribute \src "ls180.v:10076.1-10080.4" - wire width 3 $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 - attribute \src "ls180.v:10076.1-10080.4" - wire width 25 $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 - attribute \src "ls180.v:10076.1-10080.4" - wire width 25 $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 - attribute \src "ls180.v:10090.1-10094.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 - attribute \src "ls180.v:10090.1-10094.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 - attribute \src "ls180.v:10090.1-10094.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 - attribute \src "ls180.v:10104.1-10108.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 - attribute \src "ls180.v:10104.1-10108.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 - attribute \src "ls180.v:10104.1-10108.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 - attribute \src "ls180.v:10118.1-10122.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 - attribute \src "ls180.v:10118.1-10122.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 - attribute \src "ls180.v:10118.1-10122.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 - attribute \src "ls180.v:10133.1-10137.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 - attribute \src "ls180.v:10133.1-10137.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 - attribute \src "ls180.v:10133.1-10137.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 - attribute \src "ls180.v:10150.1-10154.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 - attribute \src "ls180.v:10150.1-10154.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 - attribute \src "ls180.v:10150.1-10154.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 - attribute \src "ls180.v:10166.1-10170.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 - attribute \src "ls180.v:10166.1-10170.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 - attribute \src "ls180.v:10166.1-10170.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 - attribute \src "ls180.v:10180.1-10184.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 - attribute \src "ls180.v:10180.1-10184.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 - attribute \src "ls180.v:10180.1-10184.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 - attribute \src "ls180.v:3223.1-3316.4" - wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3380.1-3473.4" - wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3537.1-3630.4" - wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3694.1-3787.4" - wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6517.1-6533.4" - wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6738.1-6754.4" - wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6755.1-6771.4" - wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6823.1-6830.4" - wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6831.1-6838.4" - wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6839.1-6846.4" - wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6847.1-6854.4" - wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6855.1-6862.4" - wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6863.1-6870.4" - wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6871.1-6878.4" - wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6879.1-6886.4" - wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6534.1-6550.4" - wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6887.1-6894.4" - wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6895.1-6902.4" - wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:6903.1-6910.4" - wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:6911.1-6918.4" - wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:6919.1-6938.4" - wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:6939.1-6958.4" - wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:6959.1-6978.4" - wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:6979.1-6998.4" - wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:6999.1-7018.4" - wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7019.1-7038.4" - wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6551.1-6567.4" - wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7039.1-7058.4" - wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7059.1-7078.4" - wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6568.1-6584.4" - wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6585.1-6601.4" - wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6602.1-6618.4" - wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6670.1-6686.4" - wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6687.1-6703.4" - wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6704.1-6720.4" - wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6721.1-6737.4" - wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6619.1-6635.4" - wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6636.1-6652.4" - wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6653.1-6669.4" - wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6772.1-6788.4" - wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6789.1-6805.4" - wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6806.1-6822.4" - wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5757.1-5768.4" - wire $0\builder_error[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5646.1-5682.4" - wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5646.1-5682.4" - wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5646.1-5682.4" - wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5646.1-5682.4" - wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5646.1-5682.4" - wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5646.1-5682.4" - wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5646.1-5682.4" - wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:5646.1-5682.4" - wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1879.5-1879.44" - wire $0\builder_libresocsim_wishbone_err[0:0] - attribute \src "ls180.v:1768.5-1768.27" - wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1769.5-1769.27" - wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1770.5-1770.27" - wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1771.5-1771.27" - wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5646.1-5682.4" - wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3129.1-3159.4" - wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5456.1-5495.4" - wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5553.1-5589.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4698.1-4770.4" - wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4543.1-4636.4" - wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4433.1-4509.4" - wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4670.1-4697.4" - wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4399.1-4432.4" - wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5757.1-5768.4" - wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5757.1-5768.4" - wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5707.1-5714.4" - wire width 5 $0\builder_slave_sel[4:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\builder_slave_sel_r[4:0] - attribute \src "ls180.v:4230.1-4278.4" - wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4289.1-4337.4" - wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7198.1-7226.4" - wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7227.1-7255.4" - wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7079.1-7095.4" - wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7096.1-7112.4" - wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7113.1-7129.4" - wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7130.1-7146.4" - wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7147.1-7163.4" - wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7164.1-7180.4" - wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7181.1-7197.4" - wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:154.11-154.24" - wire width 3 $0\eint_1[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 36 $0\main_dummy[35:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_gpio_oe_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_gpio_out_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_gpio_out_storage[15:0] - attribute \src "ls180.v:7313.1-7331.4" - wire width 16 $0\main_gpio_status[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7352.1-7354.4" - wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1556.11-1556.41" - wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1555.11-1555.41" - wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:5515.1-5552.4" - wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1647.11-1647.41" - wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1646.11-1646.41" - wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1639.12-1639.45" - wire width 32 $0\main_interface1_bus_dat_w[31:0] - attribute \src "ls180.v:5515.1-5552.4" - wire width 4 $0\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:2787.1-2833.4" - wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:169.11-169.69" - wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] - attribute \src "ls180.v:168.11-168.69" - wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:2775.1-2785.4" - wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2787.1-2833.4" - wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:2847.1-2893.4" - wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:184.11-184.69" - wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] - attribute \src "ls180.v:183.11-183.69" - wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:2835.1-2845.4" - wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2847.1-2893.4" - wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:2907.1-2953.4" - wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:199.11-199.69" - wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] - attribute \src "ls180.v:198.11-198.69" - wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:2895.1-2905.4" - wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:2907.1-2953.4" - wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:127.12-127.74" - wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:135.5-135.69" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:131.5-131.72" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:143.12-143.78" - wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - attribute \src "ls180.v:141.5-141.74" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] - attribute \src "ls180.v:159.5-159.74" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] - attribute \src "ls180.v:2847.1-2893.4" - wire $0\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:75.5-75.46" - wire $0\main_libresocsim_libresoc_dbus_err[0:0] - attribute \src "ls180.v:2787.1-2833.4" - wire $0\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:86.5-86.46" - wire $0\main_libresocsim_libresoc_ibus_err[0:0] - attribute \src "ls180.v:2768.1-2773.4" - wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:2907.1-2953.4" - wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:117.5-117.49" - wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:215.5-215.40" - wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:2956.1-2962.4" - wire width 4 $0\main_libresocsim_we[3:0] - attribute \src "ls180.v:2968.1-2973.4" - wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4040.1-4086.4" - wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4028.1-4038.4" - wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4040.1-4086.4" - wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1580.5-1580.41" - wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5423.1-5430.4" - wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5456.1-5495.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5456.1-5495.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:5456.1-5495.4" - wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5456.1-5495.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5456.1-5495.4" - wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5456.1-5495.4" - wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5456.1-5495.4" - wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1389.5-1389.34" - wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5111.1-5118.4" - wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5167.1-5174.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5121.1-5128.4" - wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5177.1-5184.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5131.1-5138.4" - wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5187.1-5194.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5141.1-5148.4" - wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5197.1-5204.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5156.1-5163.4" - wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1495.5-1495.50" - wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5150.1-5155.4" - wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5103.1-5108.4" - wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5023.1-5102.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:4985.1-4992.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:4995.1-5002.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5005.1-5012.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5015.1-5022.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1452.5-1452.51" - wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5023.1-5102.4" - wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5023.1-5102.4" - wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:4963.1-4970.4" - wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:5601.1-5617.4" - wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:5515.1-5552.4" - wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5553.1-5589.4" - wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5553.1-5589.4" - wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5553.1-5589.4" - wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5553.1-5589.4" - wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5553.1-5589.4" - wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5553.1-5589.4" - wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1660.5-1660.45" - wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5515.1-5552.4" - wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:5515.1-5552.4" - wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1716.5-1716.41" - wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5631.1-5638.4" - wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4369.1-4397.4" - wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1181.5-1181.53" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1182.5-1182.52" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1162.5-1162.46" - wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4543.1-4636.4" - wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1135.5-1135.49" - wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1136.5-1136.48" - wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1137.5-1137.55" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1139.5-1139.57" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1140.5-1140.58" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1142.11-1142.64" - wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1143.5-1143.59" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1148.11-1148.57" - wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1149.5-1149.52" - wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4543.1-4636.4" - wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4543.1-4636.4" - wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4543.1-4636.4" - wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4433.1-4509.4" - wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4433.1-4509.4" - wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4433.1-4509.4" - wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4433.1-4509.4" - wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4433.1-4509.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4433.1-4509.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1125.11-1125.57" - wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1126.5-1126.52" - wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4433.1-4509.4" - wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4804.1-4905.4" - wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1337.5-1337.55" - wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1338.5-1338.54" - wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1318.5-1318.48" - wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1289.5-1289.50" - wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1290.5-1290.49" - wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1291.5-1291.56" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1293.5-1293.58" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1294.5-1294.59" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1296.11-1296.65" - wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1297.5-1297.60" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1300.5-1300.51" - wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1301.5-1301.52" - wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1302.11-1302.58" - wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1303.5-1303.53" - wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1310.5-1310.41" - wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4804.1-4905.4" - wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4804.1-4905.4" - wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4804.1-4905.4" - wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4698.1-4770.4" - wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4698.1-4770.4" - wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1259.5-1259.54" - wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1260.5-1260.53" - wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1240.5-1240.47" - wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4670.1-4697.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4670.1-4697.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4670.1-4697.4" - wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4670.1-4697.4" - wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1227.5-1227.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1228.5-1228.49" - wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1229.5-1229.56" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1230.5-1230.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1231.5-1231.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1232.5-1232.59" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1233.11-1233.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1234.11-1234.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1235.5-1235.60" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1225.5-1225.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4698.1-4770.4" - wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1214.5-1214.51" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1215.5-1215.52" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4698.1-4770.4" - wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4698.1-4770.4" - wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4698.1-4770.4" - wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5205.1-5395.4" - wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4698.1-4770.4" - wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4698.1-4770.4" - wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4670.1-4697.4" - wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4399.1-4432.4" - wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4399.1-4432.4" - wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1107.5-1107.40" - wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4399.1-4432.4" - wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4399.1-4432.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4399.1-4432.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4399.1-4432.4" - wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4399.1-4432.4" - wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3185.1-3192.4" - wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:447.5-447.64" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:430.5-430.67" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:431.5-431.66" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3207.1-3214.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3174.1-3181.4" - wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3872.1-3880.4" - wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3223.1-3316.4" - wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:489.32-489.76" - wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:487.32-487.75" - wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3342.1-3349.4" - wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:529.5-529.64" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:512.5-512.67" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:513.5-513.66" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3364.1-3371.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3331.1-3338.4" - wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3881.1-3889.4" - wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3380.1-3473.4" - wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:571.32-571.76" - wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:569.32-569.75" - wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3499.1-3506.4" - wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:611.5-611.64" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:594.5-594.67" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:595.5-595.66" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3521.1-3528.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3488.1-3495.4" - wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3890.1-3898.4" - wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3537.1-3630.4" - wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:653.32-653.76" - wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:651.32-651.75" - wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3656.1-3663.4" - wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:693.5-693.64" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:676.5-676.67" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:677.5-677.66" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3678.1-3685.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3645.1-3652.4" - wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3899.1-3907.4" - wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3694.1-3787.4" - wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:735.32-735.76" - wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:733.32-733.75" - wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3821.1-3826.4" - wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3827.1-3832.4" - wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3833.1-3838.4" - wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:743.5-743.43" - wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3807.1-3813.4" - wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:741.5-741.48" - wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:740.5-740.43" - wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:738.5-738.44" - wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:739.5-739.45" - wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3854.1-3859.4" - wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3860.1-3865.4" - wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3866.1-3871.4" - wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3840.1-3846.4" - wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3912.1-3984.4" - wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3129.1-3159.4" - wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:391.5-391.42" - wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:392.5-392.43" - wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3129.1-3159.4" - wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:327.5-327.38" - wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:376.5-376.35" - wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4008.1-4021.4" - wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4008.1-4021.4" - wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:277.5-277.36" - wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3070.1-3086.4" - wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3070.1-3086.4" - wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3070.1-3086.4" - wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3070.1-3086.4" - wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3012.1-3066.4" - wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:774.12-774.36" - wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:775.11-775.35" - wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3129.1-3159.4" - wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3012.1-3066.4" - wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3012.1-3066.4" - wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:777.5-777.31" - wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:778.5-778.31" - wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3912.1-3984.4" - wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:782.32-782.63" - wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:780.32-780.63" - wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4230.1-4278.4" - wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4230.1-4278.4" - wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4230.1-4278.4" - wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4230.1-4278.4" - wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4230.1-4278.4" - wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4230.1-4278.4" - wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4230.1-4278.4" - wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4230.1-4278.4" - wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:998.12-998.47" - wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6282.1-6287.4" - wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4289.1-4337.4" - wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6328.1-6333.4" - wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:4148.1-4152.4" - wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4137.1-4141.4" - wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:853.5-853.38" - wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:854.5-854.37" - wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:980.5-980.27" - wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4142.1-4147.4" - wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:962.5-962.37" - wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4200.1-4207.4" - wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4131.1-4136.4" - wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:925.5-925.37" - wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:908.5-908.40" - wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:909.5-909.39" - wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4170.1-4177.4" - wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4040.1-4086.4" - wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:821.5-821.29" - wire $0\main_wb_sdram_err[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10056.1-10066.4" - wire width 7 $0\memadr[6:0] - attribute \src "ls180.v:10076.1-10080.4" - wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10090.1-10094.4" - wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10104.1-10108.4" - wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10118.1-10122.4" - wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10133.1-10137.4" - wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10139.1-10142.4" - wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10150.1-10154.4" - wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10156.1-10159.4" - wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10166.1-10170.4" - wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10180.1-10184.4" - wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7428.1-10052.4" - wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7356.1-7426.4" - wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7356.1-7426.4" - wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7356.1-7426.4" - wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7428.1-10052.4" - wire $0\uart_tx[0:0] - attribute \src "ls180.v:1747.11-1747.49" - wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1746.11-1746.44" - wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1749.11-1749.49" - wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1748.11-1748.44" - wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1751.11-1751.49" - wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1750.11-1750.44" - wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1753.11-1753.49" - wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1752.11-1752.44" - wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2598.5-2598.41" - wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2611.5-2611.42" - wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2612.5-2612.42" - wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2616.12-2616.50" - wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2617.5-2617.42" - wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2618.5-2618.42" - wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2619.12-2619.50" - wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2620.5-2620.42" - wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2621.5-2621.42" - wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2622.12-2622.50" - wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2623.5-2623.42" - wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2599.12-2599.49" - wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2624.5-2624.42" - wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2625.12-2625.50" - wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2626.5-2626.42" - wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2627.5-2627.42" - wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2628.12-2628.50" - wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2629.12-2629.50" - wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] - attribute \src "ls180.v:2630.11-2630.48" - wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] - attribute \src "ls180.v:2631.5-2631.42" - wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2632.5-2632.42" - wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2633.5-2633.42" - wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2600.11-2600.47" - wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2634.11-2634.48" - wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2635.11-2635.48" - wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2601.5-2601.41" - wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2602.5-2602.41" - wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2603.5-2603.41" - wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2607.5-2607.41" - wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2608.12-2608.49" - wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2609.11-2609.47" - wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2610.5-2610.41" - wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2604.5-2604.39" - wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2605.5-2605.39" - wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2606.5-2606.39" - wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2613.5-2613.39" - wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2614.5-2614.39" - wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2615.5-2615.39" - wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1733.5-1733.41" - wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1732.5-1732.36" - wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1737.5-1737.41" - wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1736.5-1736.36" - wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1741.5-1741.41" - wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1740.5-1740.36" - wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1778.5-1778.40" - wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1777.5-1777.35" - wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1898.12-1898.39" - wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1895.5-1895.25" - wire $1\builder_error[0:0] - attribute \src "ls180.v:1892.11-1892.31" - wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1902.11-1902.51" - wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2404.11-2404.52" - wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2437.11-2437.52" - wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2478.11-2478.52" - wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2543.11-2543.52" - wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2568.11-2568.52" - wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1943.11-1943.51" - wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1972.11-1972.51" - wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1985.11-1985.51" - wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2026.11-2026.51" - wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2067.11-2067.51" - wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2132.11-2132.51" - wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2265.11-2265.51" - wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2346.11-2346.51" - wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2363.11-2363.51" - wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1865.12-1865.43" - wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2594.12-2594.55" - wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2595.5-2595.50" - wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1867.11-1867.43" - wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2592.11-2592.55" - wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2593.5-2593.52" - wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1866.5-1866.34" - wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2596.5-2596.46" - wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2597.5-2597.49" - wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1875.5-1875.44" - wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1871.12-1871.54" - wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1755.11-1755.48" - wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1754.11-1754.43" - wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2701.32-2701.66" - wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2702.32-2702.66" - wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2721.32-2721.67" - wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2722.32-2722.67" - wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2723.32-2723.67" - wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2724.32-2724.67" - wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2725.32-2725.67" - wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2726.32-2726.67" - wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2727.32-2727.67" - wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2728.32-2728.67" - wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2729.32-2729.67" - wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2730.32-2730.67" - wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2731.32-2731.67" - wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2732.32-2732.67" - wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2733.32-2733.67" - wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2734.32-2734.67" - wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2703.32-2703.66" - wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2704.32-2704.66" - wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2705.32-2705.66" - wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2706.32-2706.66" - wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2707.32-2707.66" - wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2708.32-2708.66" - wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2709.32-2709.66" - wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2710.32-2710.66" - wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2711.32-2711.66" - wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2712.32-2712.66" - wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2713.32-2713.66" - wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2714.32-2714.66" - wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2715.32-2715.66" - wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2716.32-2716.66" - wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2717.32-2717.66" - wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2718.32-2718.66" - wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2719.32-2719.66" - wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2720.32-2720.66" - wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1773.5-1773.43" - wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1774.5-1774.43" - wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1775.5-1775.43" - wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1776.5-1776.43" - wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1772.5-1772.42" - wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2591.11-2591.36" - wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1745.11-1745.46" - wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1744.11-1744.41" - wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1854.11-1854.51" - wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1853.11-1853.46" - wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1822.5-1822.57" - wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1821.5-1821.52" - wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1834.11-1834.47" - wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1833.11-1833.42" - wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1858.5-1858.49" - wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1857.5-1857.44" - wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1862.11-1862.65" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1861.11-1861.60" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1810.11-1810.46" - wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1809.11-1809.41" - wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1798.11-1798.52" - wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1797.11-1797.47" - wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1794.11-1794.52" - wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1793.11-1793.47" - wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1806.5-1806.46" - wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1805.5-1805.41" - wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1814.11-1814.53" - wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1813.11-1813.48" - wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1790.5-1790.46" - wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1789.5-1789.41" - wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1886.5-1886.30" - wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1882.12-1882.40" - wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1893.11-1893.35" - wire width 5 $1\builder_slave_sel[4:0] - attribute \src "ls180.v:1894.11-1894.37" - wire width 5 $1\builder_slave_sel_r[4:0] - attribute \src "ls180.v:1782.11-1782.47" - wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1781.11-1781.42" - wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1786.11-1786.47" - wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1785.11-1785.42" - wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2590.11-2590.31" - wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2643.5-2643.39" - wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2644.5-2644.39" - wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2636.11-2636.47" - wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2637.12-2637.49" - wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2638.5-2638.41" - wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2639.5-2639.41" - wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2640.5-2640.41" - wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2641.5-2641.41" - wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2642.5-2642.41" - wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:834.5-834.29" - wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:831.5-831.34" - wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1779.5-1779.55" - wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1780.5-1780.58" - wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:833.12-833.40" - wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:830.5-830.31" - wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:265.12-265.38" - wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:266.5-266.36" - wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1065.12-1065.30" - wire width 36 $1\main_dummy[35:0] - attribute \src "ls180.v:982.5-982.27" - wire $1\main_gpio_oe_re[0:0] - attribute \src "ls180.v:981.12-981.40" - wire width 16 $1\main_gpio_oe_storage[15:0] - attribute \src "ls180.v:986.5-986.28" - wire $1\main_gpio_out_re[0:0] - attribute \src "ls180.v:985.12-985.41" - wire width 16 $1\main_gpio_out_storage[15:0] - attribute \src "ls180.v:983.12-983.36" - wire width 16 $1\main_gpio_status[15:0] - attribute \src "ls180.v:1090.5-1090.23" - wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1089.11-1089.34" - wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:250.5-250.24" - wire $1\main_int_rst[0:0] - attribute \src "ls180.v:1638.12-1638.43" - wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1642.5-1642.35" - wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1641.11-1641.41" - wire width 4 $1\main_interface1_bus_sel[3:0] - attribute \src "ls180.v:1643.5-1643.35" - wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1645.5-1645.34" - wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:62.12-62.47" - wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:172.5-172.47" - wire $1\main_libresocsim_converter0_counter[0:0] - attribute \src "ls180.v:1734.5-1734.69" - wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1735.5-1735.72" - wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:174.12-174.53" - wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] - attribute \src "ls180.v:171.5-171.44" - wire $1\main_libresocsim_converter0_skip[0:0] - attribute \src "ls180.v:187.5-187.47" - wire $1\main_libresocsim_converter1_counter[0:0] - attribute \src "ls180.v:1738.5-1738.69" - wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1739.5-1739.72" - wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:189.12-189.53" - wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] - attribute \src "ls180.v:186.5-186.44" - wire $1\main_libresocsim_converter1_skip[0:0] - attribute \src "ls180.v:202.5-202.47" - wire $1\main_libresocsim_converter2_counter[0:0] - attribute \src "ls180.v:1742.5-1742.69" - wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1743.5-1743.72" - wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:204.12-204.53" - wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] - attribute \src "ls180.v:201.5-201.44" - wire $1\main_libresocsim_converter2_skip[0:0] - attribute \src "ls180.v:225.5-225.34" - wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:224.5-224.39" - wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:245.5-245.44" - wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:244.5-244.49" - wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:160.12-160.71" - wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] - attribute \src "ls180.v:164.5-164.63" - wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - attribute \src "ls180.v:161.12-161.73" - wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - attribute \src "ls180.v:163.11-163.69" - wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] - attribute \src "ls180.v:165.5-165.63" - wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] - attribute \src "ls180.v:167.5-167.62" - wire $1\main_libresocsim_interface0_converted_interface_we[0:0] - attribute \src "ls180.v:175.12-175.71" - wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] - attribute \src "ls180.v:179.5-179.63" - wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - attribute \src "ls180.v:176.12-176.73" - wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - attribute \src "ls180.v:178.11-178.69" - wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] - attribute \src "ls180.v:180.5-180.63" - wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] - attribute \src "ls180.v:182.5-182.62" - wire $1\main_libresocsim_interface1_converted_interface_we[0:0] - attribute \src "ls180.v:190.12-190.71" - wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] - attribute \src "ls180.v:194.5-194.63" - wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - attribute \src "ls180.v:191.12-191.73" - wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - attribute \src "ls180.v:193.11-193.69" - wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] - attribute \src "ls180.v:195.5-195.63" - wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] - attribute \src "ls180.v:197.5-197.62" - wire $1\main_libresocsim_interface2_converted_interface_we[0:0] - attribute \src "ls180.v:71.5-71.46" - wire $1\main_libresocsim_libresoc_dbus_ack[0:0] - attribute \src "ls180.v:82.5-82.46" - wire $1\main_libresocsim_libresoc_ibus_ack[0:0] - attribute \src "ls180.v:64.12-64.55" - wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:115.5-115.49" - wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - attribute \src "ls180.v:221.5-221.36" - wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:220.12-220.49" - wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:211.5-211.40" - wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:223.5-223.38" - wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:222.12-222.51" - wire width 32 $1\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:55.5-55.37" - wire $1\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:54.5-54.42" - wire $1\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:57.5-57.39" - wire $1\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:56.12-56.60" - wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:227.5-227.44" - wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:226.5-226.49" - wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:246.12-246.42" - wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:228.12-228.49" - wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:218.11-218.37" - wire width 4 $1\main_libresocsim_we[3:0] - attribute \src "ls180.v:234.5-234.39" - wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:235.5-235.45" - wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:232.5-232.41" - wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:822.12-822.40" - wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:826.5-826.32" - wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:823.12-823.42" - wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:825.11-825.38" - wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:827.5-827.32" - wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:829.5-829.31" - wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1069.12-1069.37" - wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1071.5-1071.31" - wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1070.5-1070.36" - wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1075.5-1075.31" - wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1074.12-1074.44" - wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1073.5-1073.30" - wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1072.12-1072.43" - wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1079.12-1079.37" - wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1081.5-1081.31" - wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1080.5-1080.36" - wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1085.5-1085.31" - wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1084.12-1084.44" - wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1083.5-1083.30" - wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1082.12-1082.43" - wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:267.11-267.32" - wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1607.11-1607.50" - wire width 2 $1\main_sdblock2mem_converter_demux[1:0] - attribute \src "ls180.v:1603.5-1603.51" - wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1604.5-1604.50" - wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1605.12-1605.66" - wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] - attribute \src "ls180.v:1606.11-1606.77" - wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - attribute \src "ls180.v:1609.5-1609.49" - wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1582.11-1582.47" - wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1579.11-1579.45" - wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1581.11-1581.47" - wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1583.11-1583.50" - wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1617.12-1617.62" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1618.12-1618.60" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - attribute \src "ls180.v:1615.5-1615.45" - wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1625.5-1625.54" - wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1624.12-1624.67" - wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1629.5-1629.56" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1628.5-1628.61" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1627.5-1627.56" - wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1626.12-1626.69" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1633.5-1633.54" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1632.5-1632.59" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1635.12-1635.61" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1855.12-1855.87" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1856.5-1856.82" - wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1620.5-1620.57" - wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1630.5-1630.53" - wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1399.5-1399.38" - wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1398.12-1398.51" - wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1397.5-1397.39" - wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1396.11-1396.51" - wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1383.5-1383.39" - wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1382.12-1382.52" - wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1385.5-1385.38" - wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1384.12-1384.51" - wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1538.11-1538.39" - wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1839.11-1839.62" - wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1840.5-1840.59" - wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1539.5-1539.32" - wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1835.5-1835.55" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1836.5-1836.58" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1540.5-1540.33" - wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1843.5-1843.56" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1844.5-1844.59" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1390.13-1390.53" - wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1851.13-1851.76" - wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1852.5-1852.69" - wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1541.5-1541.35" - wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1845.5-1845.58" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1846.5-1846.61" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1499.11-1499.47" - wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1505.5-1505.46" - wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1504.12-1504.54" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1500.12-1500.58" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1512.5-1512.46" - wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1511.12-1511.54" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1507.12-1507.58" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1519.5-1519.46" - wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1518.12-1518.54" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1514.12-1514.58" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1526.5-1526.46" - wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1525.12-1525.54" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1521.12-1521.58" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1528.12-1528.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1529.12-1529.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1530.12-1530.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1531.12-1531.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1533.12-1533.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1534.12-1534.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1535.12-1535.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1536.12-1536.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1490.5-1490.48" - wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1491.5-1491.47" - wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1492.11-1492.61" - wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1489.5-1489.48" - wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1488.5-1488.48" - wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1493.5-1493.50" - wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1498.11-1498.47" - wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1532.5-1532.43" - wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1455.11-1455.48" - wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1831.11-1831.87" - wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1832.5-1832.84" - wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1460.12-1460.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1456.12-1456.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1467.12-1467.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1463.12-1463.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1474.12-1474.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1470.12-1470.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1481.12-1481.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1477.12-1477.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1484.12-1484.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1823.12-1823.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1824.5-1824.88" - wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1485.12-1485.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1825.12-1825.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1826.5-1826.88" - wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1486.12-1486.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1827.12-1827.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1828.5-1828.88" - wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1487.12-1487.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1829.12-1829.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1830.5-1830.88" - wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1446.5-1446.49" - wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1453.5-1453.50" - wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1454.11-1454.64" - wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1451.5-1451.51" - wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1450.5-1450.51" - wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1442.11-1442.47" - wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1400.11-1400.51" - wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1543.12-1543.42" - wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1841.12-1841.65" - wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1842.5-1842.60" - wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1544.5-1544.33" - wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1837.5-1837.56" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1838.5-1838.59" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1545.5-1545.34" - wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1847.5-1847.57" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1848.5-1848.60" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1546.5-1546.36" - wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1849.5-1849.59" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1850.5-1850.62" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1691.11-1691.48" - wire width 2 $1\main_sdmem2block_converter_mux[1:0] - attribute \src "ls180.v:1689.11-1689.64" - wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1665.5-1665.40" - wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1664.12-1664.53" - wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1663.12-1663.45" - wire width 32 $1\main_sdmem2block_dma_data[31:0] - attribute \src "ls180.v:1859.12-1859.75" - wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - attribute \src "ls180.v:1860.5-1860.70" - wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1670.5-1670.44" - wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1669.5-1669.42" - wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1668.5-1668.47" - wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1667.5-1667.42" - wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1666.12-1666.55" - wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1673.5-1673.40" - wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1672.5-1672.45" - wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1677.12-1677.47" - wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1863.12-1863.87" - wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1864.5-1864.82" - wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1656.5-1656.42" - wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1657.12-1657.61" - wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1655.5-1655.43" - wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1654.5-1654.43" - wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1661.5-1661.44" - wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1662.12-1662.60" - wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] - attribute \src "ls180.v:1658.5-1658.45" - wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1718.11-1718.47" - wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1715.11-1715.45" - wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1717.11-1717.47" - wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1719.11-1719.50" - wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1099.5-1099.35" - wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1102.5-1102.35" - wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1103.5-1103.36" - wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1101.11-1101.41" - wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1097.5-1097.33" - wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1096.11-1096.46" - wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1205.5-1205.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1206.5-1206.48" - wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1207.11-1207.62" - wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1203.5-1203.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1190.11-1190.54" - wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1186.5-1186.55" - wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1187.5-1187.54" - wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1188.11-1188.68" - wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1189.11-1189.81" - wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1192.5-1192.53" - wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1208.5-1208.38" - wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1803.5-1803.66" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1804.5-1804.69" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1178.5-1178.36" - wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1173.5-1173.53" - wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1160.11-1160.39" - wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1799.11-1799.67" - wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1800.5-1800.64" - wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1145.5-1145.48" - wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1146.5-1146.50" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1147.5-1147.51" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1152.5-1152.37" - wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1153.11-1153.53" - wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1151.5-1151.38" - wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1150.5-1150.38" - wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1156.5-1156.39" - wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1157.11-1157.53" - wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1158.11-1158.55" - wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1155.5-1155.40" - wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1154.5-1154.40" - wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1159.12-1159.48" - wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1801.12-1801.71" - wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1802.5-1802.66" - wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1132.11-1132.39" - wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1795.11-1795.66" - wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1796.5-1796.63" - wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1131.5-1131.32" - wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1122.5-1122.48" - wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1123.5-1123.50" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1124.5-1124.51" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1129.5-1129.37" - wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1130.11-1130.51" - wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1128.5-1128.38" - wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1127.5-1127.38" - wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1316.11-1316.41" - wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1815.11-1815.70" - wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1816.5-1816.66" - wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1361.5-1361.51" - wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1362.5-1362.50" - wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1363.11-1363.64" - wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1359.5-1359.51" - wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1346.5-1346.50" - wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1342.5-1342.57" - wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1343.5-1343.56" - wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1344.11-1344.70" - wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1345.11-1345.83" - wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1348.5-1348.55" - wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1364.5-1364.40" - wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1819.5-1819.69" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1820.5-1820.72" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1334.5-1334.38" - wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1329.5-1329.55" - wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1299.5-1299.49" - wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1306.5-1306.38" - wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1307.11-1307.61" - wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1305.5-1305.39" - wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1304.5-1304.39" - wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1311.5-1311.40" - wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1312.11-1312.54" - wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1313.11-1313.56" - wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1309.5-1309.41" - wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1308.5-1308.41" - wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1314.5-1314.33" - wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1315.12-1315.49" - wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1817.12-1817.73" - wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1818.5-1818.68" - wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1224.11-1224.40" - wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1811.11-1811.61" - wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1812.5-1812.58" - wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1283.5-1283.50" - wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1284.5-1284.49" - wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1285.11-1285.63" - wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1281.5-1281.50" - wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1268.11-1268.55" - wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1264.5-1264.56" - wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1265.5-1265.55" - wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1266.11-1266.69" - wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1267.11-1267.82" - wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1270.5-1270.54" - wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1286.5-1286.39" - wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1807.5-1807.66" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1808.5-1808.69" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1256.5-1256.37" - wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1251.5-1251.54" - wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1238.5-1238.34" - wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1213.5-1213.49" - wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1216.11-1216.58" - wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1217.5-1217.53" - wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1220.5-1220.39" - wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1221.5-1221.38" - wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1222.11-1222.52" - wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1219.5-1219.39" - wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1218.5-1218.39" - wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1236.5-1236.34" - wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1223.5-1223.33" - wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1237.5-1237.34" - wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1117.11-1117.39" - wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1791.11-1791.66" - wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1792.5-1792.63" - wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1112.5-1112.48" - wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1113.5-1113.50" - wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1114.5-1114.51" - wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1115.11-1115.57" - wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1116.5-1116.52" - wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1366.5-1366.35" - wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1369.11-1369.42" - wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:329.5-329.33" - wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:328.12-328.46" - wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:331.5-331.34" - wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:330.11-330.45" - wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:427.5-427.50" - wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:449.11-449.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:446.11-446.68" - wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:448.11-448.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:450.11-450.73" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:473.5-473.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:474.5-474.58" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:476.12-476.74" - wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:475.5-475.64" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:471.5-471.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:419.12-419.57" - wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:421.5-421.51" - wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:424.5-424.54" - wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:425.5-425.55" - wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:426.5-426.56" - wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:422.5-422.51" - wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:423.5-423.50" - wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:418.5-418.45" - wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:417.5-417.45" - wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:416.5-416.47" - wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:414.5-414.51" - wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:413.5-413.51" - wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:477.12-477.47" - wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:481.5-481.45" - wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:482.5-482.54" - wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:480.5-480.44" - wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:478.5-478.46" - wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:485.11-485.55" - wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:484.32-484.76" - wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:509.5-509.50" - wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:531.11-531.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:528.11-528.68" - wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:530.11-530.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:532.11-532.73" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:555.5-555.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:556.5-556.58" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:558.12-558.74" - wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:557.5-557.64" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:553.5-553.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:501.12-501.57" - wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:503.5-503.51" - wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:506.5-506.54" - wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:507.5-507.55" - wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:508.5-508.56" - wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:504.5-504.51" - wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:505.5-505.50" - wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:500.5-500.45" - wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:499.5-499.45" - wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:498.5-498.47" - wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:496.5-496.51" - wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:495.5-495.51" - wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:559.12-559.47" - wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:563.5-563.45" - wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:564.5-564.54" - wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:562.5-562.44" - wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:560.5-560.46" - wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:567.11-567.55" - wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:566.32-566.76" - wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:591.5-591.50" - wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:613.11-613.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:610.11-610.68" - wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:612.11-612.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:614.11-614.73" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:637.5-637.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:638.5-638.58" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:640.12-640.74" - wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:639.5-639.64" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:635.5-635.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:583.12-583.57" - wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:585.5-585.51" - wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:588.5-588.54" - wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:589.5-589.55" - wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:590.5-590.56" - wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:586.5-586.51" - wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:587.5-587.50" - wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:582.5-582.45" - wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:581.5-581.45" - wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:580.5-580.47" - wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:578.5-578.51" - wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:577.5-577.51" - wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:641.12-641.47" - wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:645.5-645.45" - wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:646.5-646.54" - wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:644.5-644.44" - wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:642.5-642.46" - wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:649.11-649.55" - wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:648.32-648.76" - wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:673.5-673.50" - wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:695.11-695.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:692.11-692.68" - wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:694.11-694.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:696.11-696.73" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:719.5-719.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:720.5-720.58" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:722.12-722.74" - wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:721.5-721.64" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:717.5-717.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:665.12-665.57" - wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:667.5-667.51" - wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:670.5-670.54" - wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:671.5-671.55" - wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:672.5-672.56" - wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:668.5-668.51" - wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:669.5-669.50" - wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:664.5-664.45" - wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:663.5-663.45" - wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:662.5-662.47" - wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:660.5-660.51" - wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:659.5-659.51" - wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:723.12-723.47" - wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:727.5-727.45" - wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:728.5-728.54" - wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:726.5-726.44" - wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:724.5-724.46" - wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:731.11-731.55" - wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:730.32-730.76" - wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:746.5-746.49" - wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:747.5-747.49" - wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:748.5-748.48" - wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:754.11-754.45" - wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:752.11-752.46" - wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:764.5-764.49" - wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:765.5-765.49" - wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:766.5-766.48" - wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:761.5-761.43" - wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:772.11-772.45" - wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:770.11-770.46" - wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:759.5-759.48" - wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:756.5-756.44" - wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:757.5-757.45" - wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:385.5-385.31" - wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:386.12-386.44" - wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:387.11-387.43" - wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:388.5-388.38" - wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:389.5-389.38" - wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:390.5-390.37" - wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:384.5-384.32" - wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:383.5-383.32" - wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:323.5-323.33" - wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:322.11-322.44" - wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:367.12-367.45" - wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:368.11-368.40" - wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:369.5-369.35" - wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:370.5-370.34" - wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:371.5-371.35" - wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:380.5-380.39" - wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:372.5-372.34" - wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:378.5-378.39" - wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:791.5-791.26" - wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:794.5-794.26" - wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:364.12-364.46" - wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:365.11-365.47" - wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:270.5-270.36" - wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:271.5-271.35" - wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:272.5-272.36" - wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:282.12-282.45" - wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:283.5-283.43" - wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:273.5-273.35" - wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:309.5-309.38" - wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:300.12-300.48" - wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:301.11-301.43" - wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:302.5-302.38" - wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:306.5-306.36" - wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:303.5-303.37" - wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:307.5-307.36" - wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:304.5-304.38" - wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:313.5-313.42" - wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:308.5-308.40" - wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:305.5-305.37" - wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:310.12-310.47" - wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:311.5-311.42" - wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:312.11-312.50" - wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:401.5-401.38" - wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:400.5-400.38" - wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:321.5-321.25" - wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:407.5-407.38" - wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:406.11-406.46" - wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:405.5-405.38" - wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:402.5-402.39" - wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:298.12-298.46" - wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:299.5-299.44" - wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:334.12-334.37" - wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:776.11-776.40" - wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:320.11-320.36" - wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:785.5-785.36" - wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:784.32-784.63" - wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:793.11-793.34" - wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:796.11-796.34" - wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:398.11-398.44" - wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:788.11-788.42" - wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:787.32-787.63" - wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:333.5-333.32" - wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:332.12-332.45" - wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:1001.12-1001.44" - wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1002.5-1002.31" - wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1006.11-1006.42" - wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1007.5-1007.31" - wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1063.5-1063.30" - wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1062.12-1062.45" - wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1011.5-1011.36" - wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1012.5-1012.31" - wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1013.5-1013.36" - wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1014.5-1014.31" - wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1015.5-1015.39" - wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1016.5-1016.38" - wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1017.11-1017.40" - wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1783.11-1783.62" - wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1784.5-1784.59" - wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1018.5-1018.39" - wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1019.5-1019.39" - wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:992.5-992.32" - wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1020.12-1020.48" - wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1023.11-1023.44" - wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1024.11-1024.43" - wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1025.11-1025.44" - wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:993.5-993.31" - wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:995.11-995.38" - wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:999.5-999.33" - wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1056.12-1056.47" - wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1051.5-1051.37" - wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1038.5-1038.37" - wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1037.12-1037.50" - wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1053.11-1053.38" - wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1787.11-1787.60" - wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1788.5-1788.57" - wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1052.5-1052.36" - wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1048.5-1048.32" - wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1047.5-1047.37" - wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1028.5-1028.32" - wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1029.5-1029.30" - wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1050.5-1050.38" - wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1049.5-1049.43" - wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1031.11-1031.37" - wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1061.11-1061.42" - wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1055.5-1055.37" - wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1059.11-1059.42" - wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1054.5-1054.37" - wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1043.5-1043.34" - wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1060.11-1060.41" - wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1042.11-1042.45" - wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1035.5-1035.33" - wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:889.11-889.50" - wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:891.5-891.37" - wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:885.11-885.49" - wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:890.11-890.48" - wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:857.12-857.54" - wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:847.12-847.54" - wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:840.5-840.28" - wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:861.11-861.43" - wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:862.5-862.33" - wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:859.5-859.30" - wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:860.11-860.38" - wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:842.5-842.36" - wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:855.11-855.51" - wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:851.5-851.38" - wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:839.12-839.47" - wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:849.11-849.43" - wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:850.5-850.33" - wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:848.11-848.38" - wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:856.5-856.39" - wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:846.5-846.39" - wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:880.5-880.30" - wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:964.11-964.43" - wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:961.11-961.42" - wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:963.11-963.43" - wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:954.5-954.38" - wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:965.11-965.46" - wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:881.5-881.36" - wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:878.5-878.32" - wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:875.5-875.30" - wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:927.11-927.43" - wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:924.11-924.42" - wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:926.11-926.43" - wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:917.5-917.38" - wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:928.11-928.46" - wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:876.5-876.36" - wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:873.5-873.32" - wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:817.5-817.29" - wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:835.5-835.31" - wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2816.68-2816.110" - wire $add$ls180.v:2816$22_Y - attribute \src "ls180.v:2876.68-2876.110" - wire $add$ls180.v:2876$33_Y - attribute \src "ls180.v:2936.68-2936.110" - wire $add$ls180.v:2936$44_Y - attribute \src "ls180.v:4069.54-4069.83" - wire $add$ls180.v:4069$537_Y - attribute \src "ls180.v:4169.36-4169.89" - wire width 5 $add$ls180.v:4169$583_Y - attribute \src "ls180.v:4199.36-4199.89" - wire width 5 $add$ls180.v:4199$594_Y - attribute \src "ls180.v:4254.54-4254.83" - wire width 3 $add$ls180.v:4254$607_Y - attribute \src "ls180.v:4313.52-4313.79" - wire width 3 $add$ls180.v:4313$615_Y - attribute \src "ls180.v:4417.58-4417.86" - wire width 8 $add$ls180.v:4417$643_Y - attribute \src "ls180.v:4474.58-4474.86" - wire width 8 $add$ls180.v:4474$646_Y - attribute \src "ls180.v:4491.58-4491.86" - wire width 8 $add$ls180.v:4491$648_Y - attribute \src "ls180.v:4584.59-4584.87" - wire width 8 $add$ls180.v:4584$665_Y - attribute \src "ls180.v:4609.59-4609.87" - wire width 8 $add$ls180.v:4609$668_Y - attribute \src "ls180.v:4731.53-4731.82" - wire width 8 $add$ls180.v:4731$685_Y - attribute \src "ls180.v:4842.65-4842.114" - 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$xor$ls180.v:4953$800_Y - attribute \src "ls180.v:4953.205-4953.277" - wire $xor$ls180.v:4953$801_Y - attribute \src "ls180.v:4953.164-4953.278" - wire $xor$ls180.v:4953$802_Y - attribute \src "ls180.v:4954.360-4954.432" - wire $xor$ls180.v:4954$803_Y - attribute \src "ls180.v:4954.205-4954.277" - wire $xor$ls180.v:4954$804_Y - attribute \src "ls180.v:4954.164-4954.278" - wire $xor$ls180.v:4954$805_Y - attribute \src "ls180.v:4955.360-4955.432" - wire $xor$ls180.v:4955$806_Y - attribute \src "ls180.v:4955.205-4955.277" - wire $xor$ls180.v:4955$807_Y - attribute \src "ls180.v:4955.164-4955.278" - wire $xor$ls180.v:4955$808_Y - attribute \src "ls180.v:4956.360-4956.432" - wire $xor$ls180.v:4956$809_Y - attribute \src "ls180.v:4956.205-4956.277" - wire $xor$ls180.v:4956$810_Y - attribute \src "ls180.v:4956.164-4956.278" - wire $xor$ls180.v:4956$811_Y - attribute \src "ls180.v:4957.360-4957.432" - wire $xor$ls180.v:4957$812_Y - attribute \src "ls180.v:4957.205-4957.277" - wire $xor$ls180.v:4957$813_Y - attribute \src "ls180.v:4957.164-4957.278" - wire $xor$ls180.v:4957$814_Y - attribute \src "ls180.v:4958.360-4958.432" - wire $xor$ls180.v:4958$815_Y - attribute \src "ls180.v:4958.205-4958.277" - wire $xor$ls180.v:4958$816_Y - attribute \src "ls180.v:4958.164-4958.278" - wire $xor$ls180.v:4958$817_Y - attribute \src "ls180.v:4959.360-4959.432" - wire $xor$ls180.v:4959$818_Y - attribute \src "ls180.v:4959.205-4959.277" - wire $xor$ls180.v:4959$819_Y - attribute \src "ls180.v:4959.164-4959.278" - wire $xor$ls180.v:4959$820_Y - attribute \src "ls180.v:4960.360-4960.432" - wire $xor$ls180.v:4960$821_Y - attribute \src "ls180.v:4960.205-4960.277" - wire $xor$ls180.v:4960$822_Y - attribute \src "ls180.v:4960.164-4960.278" - wire $xor$ls180.v:4960$823_Y - attribute \src "ls180.v:4961.360-4961.432" - wire $xor$ls180.v:4961$824_Y - attribute \src "ls180.v:4961.205-4961.277" - wire $xor$ls180.v:4961$825_Y - attribute \src "ls180.v:4961.164-4961.278" - wire $xor$ls180.v:4961$826_Y - attribute \src "ls180.v:4962.360-4962.432" - wire $xor$ls180.v:4962$827_Y - attribute \src "ls180.v:4962.205-4962.277" - wire $xor$ls180.v:4962$828_Y - attribute \src "ls180.v:4962.164-4962.278" - wire $xor$ls180.v:4962$829_Y - attribute \src "ls180.v:4983.899-4983.983" - wire $xor$ls180.v:4983$843_Y - attribute \src "ls180.v:4983.634-4983.718" - wire $xor$ls180.v:4983$844_Y - attribute \src "ls180.v:4983.588-4983.719" - wire $xor$ls180.v:4983$845_Y - attribute \src "ls180.v:4983.234-4983.318" - wire $xor$ls180.v:4983$846_Y - attribute \src "ls180.v:4983.187-4983.319" - wire $xor$ls180.v:4983$847_Y - attribute \src "ls180.v:4984.899-4984.983" - wire $xor$ls180.v:4984$848_Y - attribute \src "ls180.v:4984.634-4984.718" - wire $xor$ls180.v:4984$849_Y - attribute \src "ls180.v:4984.588-4984.719" - wire $xor$ls180.v:4984$850_Y - attribute \src "ls180.v:4984.234-4984.318" - wire $xor$ls180.v:4984$851_Y - attribute \src "ls180.v:4984.187-4984.319" - wire $xor$ls180.v:4984$852_Y - attribute \src "ls180.v:4993.899-4993.983" - wire $xor$ls180.v:4993$854_Y - attribute \src "ls180.v:4993.634-4993.718" - wire $xor$ls180.v:4993$855_Y - attribute \src "ls180.v:4993.588-4993.719" - wire $xor$ls180.v:4993$856_Y - attribute \src "ls180.v:4993.234-4993.318" - wire $xor$ls180.v:4993$857_Y - attribute \src "ls180.v:4993.187-4993.319" - wire $xor$ls180.v:4993$858_Y - attribute \src "ls180.v:4994.899-4994.983" - wire $xor$ls180.v:4994$859_Y - attribute \src "ls180.v:4994.634-4994.718" - wire $xor$ls180.v:4994$860_Y - attribute \src "ls180.v:4994.588-4994.719" - wire $xor$ls180.v:4994$861_Y - attribute \src "ls180.v:4994.234-4994.318" - wire $xor$ls180.v:4994$862_Y - attribute \src "ls180.v:4994.187-4994.319" - wire $xor$ls180.v:4994$863_Y - attribute \src "ls180.v:5003.899-5003.983" - wire $xor$ls180.v:5003$865_Y - attribute \src "ls180.v:5003.634-5003.718" - wire $xor$ls180.v:5003$866_Y - attribute \src "ls180.v:5003.588-5003.719" - wire $xor$ls180.v:5003$867_Y - attribute \src "ls180.v:5003.234-5003.318" - wire $xor$ls180.v:5003$868_Y - attribute \src "ls180.v:5003.187-5003.319" - wire $xor$ls180.v:5003$869_Y - attribute \src "ls180.v:5004.899-5004.983" - wire $xor$ls180.v:5004$870_Y - attribute \src "ls180.v:5004.634-5004.718" - wire $xor$ls180.v:5004$871_Y - attribute \src "ls180.v:5004.588-5004.719" - wire $xor$ls180.v:5004$872_Y - attribute \src "ls180.v:5004.234-5004.318" - wire $xor$ls180.v:5004$873_Y - attribute \src "ls180.v:5004.187-5004.319" - wire $xor$ls180.v:5004$874_Y - attribute \src "ls180.v:5013.899-5013.983" - wire $xor$ls180.v:5013$876_Y - attribute \src "ls180.v:5013.634-5013.718" - wire $xor$ls180.v:5013$877_Y - attribute \src "ls180.v:5013.588-5013.719" - wire $xor$ls180.v:5013$878_Y - attribute \src "ls180.v:5013.234-5013.318" - wire $xor$ls180.v:5013$879_Y - attribute \src "ls180.v:5013.187-5013.319" - wire $xor$ls180.v:5013$880_Y - attribute \src "ls180.v:5014.899-5014.983" - wire $xor$ls180.v:5014$881_Y - attribute \src "ls180.v:5014.634-5014.718" - wire $xor$ls180.v:5014$882_Y - attribute \src "ls180.v:5014.588-5014.719" - wire $xor$ls180.v:5014$883_Y - attribute \src "ls180.v:5014.234-5014.318" - wire $xor$ls180.v:5014$884_Y - attribute \src "ls180.v:5014.187-5014.319" - wire $xor$ls180.v:5014$885_Y - attribute \src "ls180.v:5165.879-5165.961" - wire $xor$ls180.v:5165$918_Y - attribute \src "ls180.v:5165.620-5165.702" - wire $xor$ls180.v:5165$919_Y - attribute \src "ls180.v:5165.575-5165.703" - wire $xor$ls180.v:5165$920_Y - attribute \src "ls180.v:5165.229-5165.311" - wire $xor$ls180.v:5165$921_Y - attribute \src "ls180.v:5165.183-5165.312" - wire $xor$ls180.v:5165$922_Y - attribute \src "ls180.v:5166.879-5166.961" - wire $xor$ls180.v:5166$923_Y - attribute \src "ls180.v:5166.620-5166.702" - wire $xor$ls180.v:5166$924_Y - attribute \src "ls180.v:5166.575-5166.703" - wire $xor$ls180.v:5166$925_Y - attribute \src "ls180.v:5166.229-5166.311" - wire $xor$ls180.v:5166$926_Y - attribute \src "ls180.v:5166.183-5166.312" - wire $xor$ls180.v:5166$927_Y - attribute \src "ls180.v:5175.879-5175.961" - wire $xor$ls180.v:5175$929_Y - attribute \src "ls180.v:5175.620-5175.702" - wire $xor$ls180.v:5175$930_Y - attribute \src "ls180.v:5175.575-5175.703" - wire $xor$ls180.v:5175$931_Y - attribute \src "ls180.v:5175.229-5175.311" - wire $xor$ls180.v:5175$932_Y - attribute \src "ls180.v:5175.183-5175.312" - wire $xor$ls180.v:5175$933_Y - attribute \src "ls180.v:5176.879-5176.961" - wire $xor$ls180.v:5176$934_Y - attribute \src "ls180.v:5176.620-5176.702" - wire $xor$ls180.v:5176$935_Y - attribute \src "ls180.v:5176.575-5176.703" - wire $xor$ls180.v:5176$936_Y - attribute \src "ls180.v:5176.229-5176.311" - wire $xor$ls180.v:5176$937_Y - attribute \src "ls180.v:5176.183-5176.312" - wire $xor$ls180.v:5176$938_Y - attribute \src "ls180.v:5185.879-5185.961" - wire $xor$ls180.v:5185$940_Y - attribute \src "ls180.v:5185.620-5185.702" - wire $xor$ls180.v:5185$941_Y - attribute \src "ls180.v:5185.575-5185.703" - wire $xor$ls180.v:5185$942_Y - attribute \src "ls180.v:5185.229-5185.311" - wire $xor$ls180.v:5185$943_Y - attribute \src "ls180.v:5185.183-5185.312" - wire $xor$ls180.v:5185$944_Y - attribute \src "ls180.v:5186.879-5186.961" - wire $xor$ls180.v:5186$945_Y - attribute \src "ls180.v:5186.620-5186.702" - wire $xor$ls180.v:5186$946_Y - attribute \src "ls180.v:5186.575-5186.703" - wire $xor$ls180.v:5186$947_Y - attribute \src "ls180.v:5186.229-5186.311" - wire $xor$ls180.v:5186$948_Y - attribute \src "ls180.v:5186.183-5186.312" - wire $xor$ls180.v:5186$949_Y - attribute \src "ls180.v:5195.879-5195.961" - wire $xor$ls180.v:5195$951_Y - attribute \src "ls180.v:5195.620-5195.702" - wire $xor$ls180.v:5195$952_Y - attribute \src "ls180.v:5195.575-5195.703" - wire $xor$ls180.v:5195$953_Y - attribute \src "ls180.v:5195.229-5195.311" - wire $xor$ls180.v:5195$954_Y - attribute \src "ls180.v:5195.183-5195.312" - wire $xor$ls180.v:5195$955_Y - attribute \src "ls180.v:5196.879-5196.961" - wire $xor$ls180.v:5196$956_Y - attribute \src "ls180.v:5196.620-5196.702" - wire $xor$ls180.v:5196$957_Y - attribute \src "ls180.v:5196.575-5196.703" - wire $xor$ls180.v:5196$958_Y - attribute \src "ls180.v:5196.229-5196.311" - wire $xor$ls180.v:5196$959_Y - attribute \src "ls180.v:5196.183-5196.312" - wire $xor$ls180.v:5196$960_Y - attribute \src "ls180.v:1747.11-1747.42" - wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1746.11-1746.37" - wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1749.11-1749.42" - wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1748.11-1748.37" - wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1751.11-1751.42" - wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1750.11-1750.37" - wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1753.11-1753.42" - wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1752.11-1752.37" - wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2598.5-2598.34" - wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2599.12-2599.41" - wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2611.5-2611.35" - wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2612.5-2612.35" - wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2616.12-2616.42" - wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2617.5-2617.35" - wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2618.5-2618.35" - wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2619.12-2619.42" - wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2620.5-2620.35" - wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2621.5-2621.35" - wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2622.12-2622.42" - wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2623.5-2623.35" - wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2600.11-2600.40" - wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2624.5-2624.35" - wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2625.12-2625.42" - wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2626.5-2626.35" - wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2627.5-2627.35" - wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2628.12-2628.42" - wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2629.12-2629.42" - wire width 32 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2630.11-2630.41" - wire width 4 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2631.5-2631.35" - wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2632.5-2632.35" - wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2633.5-2633.35" - wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2601.5-2601.34" - wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2634.11-2634.41" - wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2635.11-2635.41" - wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2602.5-2602.34" - wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2603.5-2603.34" - wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2607.5-2607.34" - wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2608.12-2608.41" - wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2609.11-2609.40" - wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2610.5-2610.34" - wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2604.5-2604.32" - wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2605.5-2605.32" - wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2606.5-2606.32" - wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2613.5-2613.32" - wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2614.5-2614.32" - wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2615.5-2615.32" - wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1733.5-1733.34" - wire \builder_converter0_next_state - attribute \src "ls180.v:1732.5-1732.29" - wire \builder_converter0_state - attribute \src "ls180.v:1737.5-1737.34" - wire \builder_converter1_next_state - attribute \src "ls180.v:1736.5-1736.29" - wire \builder_converter1_state - attribute \src "ls180.v:1741.5-1741.34" - wire \builder_converter2_next_state - attribute \src "ls180.v:1740.5-1740.29" - wire \builder_converter2_state - attribute \src "ls180.v:1778.5-1778.33" - wire \builder_converter_next_state - attribute \src "ls180.v:1777.5-1777.28" - wire \builder_converter_state - attribute \src "ls180.v:1898.12-1898.25" - wire width 20 \builder_count - attribute \src "ls180.v:2586.13-2586.41" - wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2589.12-2589.42" - wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2588.12-2588.42" - wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2587.6-2587.33" - wire \builder_csr_interconnect_we - attribute \src "ls180.v:1936.12-1936.42" - wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1935.6-1935.37" - wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1938.12-1938.42" - wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1937.6-1937.37" - wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1932.12-1932.42" - wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1931.6-1931.37" - wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1934.12-1934.42" - wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1933.6-1933.37" - wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1928.12-1928.42" - wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1927.6-1927.37" - wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1930.12-1930.42" - wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1929.6-1929.37" - wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1924.12-1924.42" - wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1923.6-1923.37" - wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1926.12-1926.42" - wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1925.6-1925.37" - wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1904.6-1904.31" - wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1903.6-1903.32" - wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1906.6-1906.31" - wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1905.6-1905.32" - wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1920.12-1920.39" - wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1919.6-1919.34" - wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1922.12-1922.39" - wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1921.6-1921.34" - wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1916.12-1916.39" - wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1915.6-1915.34" - wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1918.12-1918.39" - wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1917.6-1917.34" - wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1912.12-1912.39" - wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1911.6-1911.34" - wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1914.12-1914.39" - wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1913.6-1913.34" - wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1908.12-1908.39" - wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1907.6-1907.34" - wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1910.12-1910.39" - wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1909.6-1909.34" - wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1939.6-1939.26" - wire \builder_csrbank0_sel - attribute \src "ls180.v:2410.12-2410.40" - wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2409.6-2409.35" - wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2412.12-2412.40" - wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2411.6-2411.35" - wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2406.12-2406.40" - wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2405.6-2405.35" - wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2408.12-2408.40" - wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2407.6-2407.35" - wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2426.6-2426.29" - wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2425.6-2425.30" - wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2428.6-2428.29" - wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2427.6-2427.30" - wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2430.6-2430.35" - wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2429.6-2429.36" - wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2432.6-2432.35" - wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2431.6-2431.36" - wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2422.12-2422.36" - wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2421.6-2421.31" - wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2424.12-2424.36" - wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2423.6-2423.31" - wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2418.12-2418.37" - wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2417.6-2417.32" - wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2420.12-2420.37" - wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2419.6-2419.32" - wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2433.6-2433.27" - wire \builder_csrbank10_sel - attribute \src "ls180.v:2414.6-2414.32" - wire \builder_csrbank10_status_r - attribute \src "ls180.v:2413.6-2413.33" - wire \builder_csrbank10_status_re - attribute \src "ls180.v:2416.6-2416.32" - wire \builder_csrbank10_status_w - attribute \src "ls180.v:2415.6-2415.33" - wire \builder_csrbank10_status_we - attribute \src "ls180.v:2471.12-2471.44" - wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2470.6-2470.39" - wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2473.12-2473.44" - wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2472.6-2472.39" - wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2467.12-2467.44" - wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2466.6-2466.39" - wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2469.12-2469.44" - wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2468.6-2468.39" - wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2443.12-2443.40" - wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2442.6-2442.35" - wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2445.12-2445.40" - wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2444.6-2444.35" - wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2439.12-2439.40" - wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2438.6-2438.35" - wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2441.12-2441.40" - wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2440.6-2440.35" - wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2459.6-2459.29" - wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2458.6-2458.30" - wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2461.6-2461.29" - wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2460.6-2460.30" - wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2463.6-2463.35" - wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2462.6-2462.36" - wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2465.6-2465.35" - wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2464.6-2464.36" - wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2455.12-2455.36" - wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2454.6-2454.31" - wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2457.12-2457.36" - wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2456.6-2456.31" - wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2451.12-2451.37" - wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2450.6-2450.32" - wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2453.12-2453.37" - wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2452.6-2452.32" - wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2474.6-2474.27" - wire \builder_csrbank11_sel - attribute \src "ls180.v:2447.6-2447.32" - wire \builder_csrbank11_status_r - attribute \src "ls180.v:2446.6-2446.33" - wire \builder_csrbank11_status_re - attribute \src "ls180.v:2449.6-2449.32" - wire \builder_csrbank11_status_w - attribute \src "ls180.v:2448.6-2448.33" - wire \builder_csrbank11_status_we - attribute \src "ls180.v:2512.6-2512.29" - wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2511.6-2511.30" - wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2514.6-2514.29" - wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2513.6-2513.30" - wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2536.6-2536.36" - wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2535.6-2535.37" - wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2538.6-2538.36" - wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2537.6-2537.37" - wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2492.12-2492.37" - wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2491.6-2491.32" - wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2494.12-2494.37" - wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2493.6-2493.32" - wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2488.12-2488.37" - wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2487.6-2487.32" - wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2490.12-2490.37" - wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2489.6-2489.32" - wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2484.12-2484.37" - wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2483.6-2483.32" - wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2486.12-2486.37" - wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2485.6-2485.32" - wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2480.12-2480.37" - wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2479.6-2479.32" - wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2482.12-2482.37" - wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2481.6-2481.32" - wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2508.12-2508.39" - wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2507.6-2507.34" - wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2510.12-2510.39" - wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2509.6-2509.34" - wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2504.12-2504.39" - wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2503.6-2503.34" - wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2506.12-2506.39" - wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2505.6-2505.34" - wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2500.12-2500.39" - wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2499.6-2499.34" - wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2502.12-2502.39" - wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2501.6-2501.34" - wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2496.12-2496.39" - wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2495.6-2495.34" - wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2498.12-2498.39" - wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2497.6-2497.34" - wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2539.6-2539.27" - wire \builder_csrbank12_sel - attribute \src "ls180.v:2516.6-2516.39" - wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2515.6-2515.40" - wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2518.6-2518.39" - wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2517.6-2517.40" - wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2532.12-2532.38" - wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2531.6-2531.33" - wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2534.12-2534.38" - wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2533.6-2533.33" - wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2528.12-2528.38" - wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2527.6-2527.33" - wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2530.12-2530.38" - wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2529.6-2529.33" - wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2524.12-2524.38" - wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2523.6-2523.33" - wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2526.12-2526.38" - wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2525.6-2525.33" - wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2520.12-2520.38" - wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2519.6-2519.33" - wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2522.12-2522.38" - wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2521.6-2521.33" - wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2553.12-2553.42" - wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2552.6-2552.37" - wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2555.12-2555.42" - wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2554.6-2554.37" - wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2549.6-2549.33" - wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2548.6-2548.34" - wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2551.6-2551.33" - wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2550.6-2550.34" - wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2561.6-2561.32" - wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2560.6-2560.33" - wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2563.6-2563.32" - wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2562.6-2562.33" - wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2564.6-2564.27" - wire \builder_csrbank13_sel - attribute \src "ls180.v:2557.6-2557.33" - wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2556.6-2556.34" - wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2559.6-2559.33" - wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2558.6-2558.34" - wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2545.6-2545.32" - wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2544.6-2544.33" - wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2547.6-2547.32" - wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2546.6-2546.33" - wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2585.6-2585.27" - wire \builder_csrbank14_sel - attribute \src "ls180.v:2582.12-2582.44" - wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2581.6-2581.39" - wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2584.12-2584.44" - wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2583.6-2583.39" - wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2578.12-2578.44" - wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2577.6-2577.39" - wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2580.12-2580.44" - wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2579.6-2579.39" - wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2574.12-2574.44" - wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2573.6-2573.39" - wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2576.12-2576.44" - wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2575.6-2575.39" - wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2570.12-2570.44" - wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2569.6-2569.39" - wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2572.12-2572.44" - wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2571.6-2571.39" - wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:1957.12-1957.34" - wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1956.6-1956.29" - wire \builder_csrbank1_in0_re - attribute \src "ls180.v:1959.12-1959.34" - wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:1958.6-1958.29" - wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1953.12-1953.34" - wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1952.6-1952.29" - wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1955.12-1955.34" - wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1954.6-1954.29" - wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1949.12-1949.34" - wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1948.6-1948.29" - wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1951.12-1951.34" - wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1950.6-1950.29" - wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1945.12-1945.34" - wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1944.6-1944.29" - wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1947.12-1947.34" - wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1946.6-1946.29" - wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:1965.12-1965.35" - wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:1964.6-1964.30" - wire \builder_csrbank1_out0_re - attribute \src "ls180.v:1967.12-1967.35" - wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:1966.6-1966.30" - wire \builder_csrbank1_out0_we - attribute \src "ls180.v:1961.12-1961.35" - wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:1960.6-1960.30" - wire \builder_csrbank1_out1_re - attribute \src "ls180.v:1963.12-1963.35" - wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:1962.6-1962.30" - wire \builder_csrbank1_out1_we - attribute \src "ls180.v:1968.6-1968.26" - wire \builder_csrbank1_sel - attribute \src "ls180.v:1978.6-1978.26" - wire \builder_csrbank2_r_r - attribute \src "ls180.v:1977.6-1977.27" - wire \builder_csrbank2_r_re - attribute \src "ls180.v:1980.6-1980.26" - wire \builder_csrbank2_r_w - attribute \src "ls180.v:1979.6-1979.27" - wire \builder_csrbank2_r_we - attribute \src "ls180.v:1981.6-1981.26" - wire \builder_csrbank2_sel - attribute \src "ls180.v:1974.12-1974.33" - wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:1973.6-1973.28" - wire \builder_csrbank2_w0_re - attribute \src "ls180.v:1976.12-1976.33" - wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:1975.6-1975.28" - wire \builder_csrbank2_w0_we - attribute \src "ls180.v:1987.6-1987.32" - wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:1986.6-1986.33" - wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:1989.6-1989.32" - wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:1988.6-1988.33" - wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2019.12-2019.38" - wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2018.6-2018.33" - wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2021.12-2021.38" - wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2020.6-2020.33" - wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2015.12-2015.38" - wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2014.6-2014.33" - wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2017.12-2017.38" - wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2016.6-2016.33" - wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2011.12-2011.38" - wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2010.6-2010.33" - wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2013.12-2013.38" - wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2012.6-2012.33" - wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2007.12-2007.38" - wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2006.6-2006.33" - wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2009.12-2009.38" - wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2008.6-2008.33" - wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2022.6-2022.26" - wire \builder_csrbank3_sel - attribute \src "ls180.v:2003.12-2003.37" - wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2002.6-2002.32" - wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2005.12-2005.37" - wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2004.6-2004.32" - wire \builder_csrbank3_width0_we - attribute \src "ls180.v:1999.12-1999.37" - wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:1998.6-1998.32" - wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2001.12-2001.37" - wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2000.6-2000.32" - wire \builder_csrbank3_width1_we - attribute \src "ls180.v:1995.12-1995.37" - wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:1994.6-1994.32" - wire \builder_csrbank3_width2_re - attribute \src "ls180.v:1997.12-1997.37" - wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:1996.6-1996.32" - wire \builder_csrbank3_width2_we - attribute \src "ls180.v:1991.12-1991.37" - wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:1990.6-1990.32" - wire \builder_csrbank3_width3_re - attribute \src "ls180.v:1993.12-1993.37" - wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:1992.6-1992.32" - wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2028.6-2028.32" - wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2027.6-2027.33" - wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2030.6-2030.32" - wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2029.6-2029.33" - wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2060.12-2060.38" - wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2059.6-2059.33" - wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2062.12-2062.38" - wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2061.6-2061.33" - wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2056.12-2056.38" - wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2055.6-2055.33" - wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2058.12-2058.38" - wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2057.6-2057.33" - wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2052.12-2052.38" - wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2051.6-2051.33" - wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2054.12-2054.38" - wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2053.6-2053.33" - wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2048.12-2048.38" - wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2047.6-2047.33" - wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2050.12-2050.38" - wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2049.6-2049.33" - wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2063.6-2063.26" - wire \builder_csrbank4_sel - attribute \src "ls180.v:2044.12-2044.37" - wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2043.6-2043.32" - wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2046.12-2046.37" - wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2045.6-2045.32" - wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2040.12-2040.37" - wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2039.6-2039.32" - wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2042.12-2042.37" - wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2041.6-2041.32" - wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2036.12-2036.37" - wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2035.6-2035.32" - wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2038.12-2038.37" - wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2037.6-2037.32" - wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2032.12-2032.37" - wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2031.6-2031.32" - wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2034.12-2034.37" - wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2033.6-2033.32" - wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2097.12-2097.40" - wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2096.6-2096.35" - wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2099.12-2099.40" - wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2098.6-2098.35" - wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2093.12-2093.40" - wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2092.6-2092.35" - wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2095.12-2095.40" - wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2094.6-2094.35" - wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2089.12-2089.40" - wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2088.6-2088.35" - wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2091.12-2091.40" - wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2090.6-2090.35" - wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2085.12-2085.40" - wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2084.6-2084.35" - wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2087.12-2087.40" - wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2086.6-2086.35" - wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2081.12-2081.40" - wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2080.6-2080.35" - wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2083.12-2083.40" - wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2082.6-2082.35" - wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2077.12-2077.40" - wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2076.6-2076.35" - wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2079.12-2079.40" - wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2078.6-2078.35" - wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2073.12-2073.40" - wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2072.6-2072.35" - wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2075.12-2075.40" - wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2074.6-2074.35" - wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2069.12-2069.40" - wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2068.6-2068.35" - wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2071.12-2071.40" - wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2070.6-2070.35" - wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2121.6-2121.33" - wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2120.6-2120.34" - wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2123.6-2123.33" - wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2122.6-2122.34" - wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2117.6-2117.36" - wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2116.6-2116.37" - wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2119.6-2119.36" - wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2118.6-2118.37" - wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2113.12-2113.42" - wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2112.6-2112.37" - wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2115.12-2115.42" - wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2114.6-2114.37" - wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2109.12-2109.42" - wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2108.6-2108.37" - wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2111.12-2111.42" - wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2110.6-2110.37" - wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2105.12-2105.42" - wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2104.6-2104.37" - wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2107.12-2107.42" - wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2106.6-2106.37" - wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2101.12-2101.42" - wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2100.6-2100.37" - wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2103.12-2103.42" - wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2102.6-2102.37" - wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2125.6-2125.34" - wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2124.6-2124.35" - wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2127.6-2127.34" - wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2126.6-2126.35" - wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2128.6-2128.26" - wire \builder_csrbank5_sel - attribute \src "ls180.v:2258.12-2258.43" - wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2257.6-2257.38" - wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2260.12-2260.43" - wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2259.6-2259.38" - wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2254.12-2254.43" - wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2253.6-2253.38" - wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2256.12-2256.43" - wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2255.6-2255.38" - wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2250.12-2250.43" - wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2249.6-2249.38" - wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2252.12-2252.43" - wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2251.6-2251.38" - wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2246.12-2246.43" - wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2245.6-2245.38" - wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2248.12-2248.43" - wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2247.6-2247.38" - wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2242.12-2242.44" - wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2241.6-2241.39" - wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2244.12-2244.44" - wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2243.6-2243.39" - wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2238.12-2238.44" - wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2237.6-2237.39" - wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2240.12-2240.44" - wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2239.6-2239.39" - wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2146.12-2146.44" - wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2145.6-2145.39" - wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2148.12-2148.44" - wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2147.6-2147.39" - wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2142.12-2142.44" - wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2141.6-2141.39" - wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2144.12-2144.44" - wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2143.6-2143.39" - wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2138.12-2138.44" - wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2137.6-2137.39" - wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2140.12-2140.44" - wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2139.6-2139.39" - wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2134.12-2134.44" - wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2133.6-2133.39" - wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2136.12-2136.44" - wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2135.6-2135.39" - wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2162.12-2162.43" - wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2161.6-2161.38" - wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2164.12-2164.43" - wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2163.6-2163.38" - wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2158.12-2158.43" - wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2157.6-2157.38" - wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2160.12-2160.43" - wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2159.6-2159.38" - wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2154.12-2154.43" - wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2153.6-2153.38" - wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2156.12-2156.43" - wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2155.6-2155.38" - wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2150.12-2150.43" - wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2149.6-2149.38" - wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2152.12-2152.43" - wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2151.6-2151.38" - wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2230.12-2230.40" - wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2229.6-2229.35" - wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2232.12-2232.40" - wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2231.6-2231.35" - wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2226.12-2226.44" - wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2225.6-2225.39" - wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2228.12-2228.44" - wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2227.6-2227.39" - wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2186.12-2186.45" - wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2185.6-2185.40" - wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2188.12-2188.45" - wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2187.6-2187.40" - wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2182.12-2182.45" - wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2181.6-2181.40" - wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2184.12-2184.45" - wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2183.6-2183.40" - wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2178.12-2178.45" - wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2177.6-2177.40" - wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2180.12-2180.45" - wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2179.6-2179.40" - wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2174.12-2174.45" - wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2173.6-2173.40" - wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2176.12-2176.45" - wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2175.6-2175.40" - wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2170.12-2170.45" - wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2169.6-2169.40" - wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2172.12-2172.45" - wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2171.6-2171.40" - wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2166.12-2166.45" - wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2165.6-2165.40" - wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2168.12-2168.45" - wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2167.6-2167.40" - wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2222.12-2222.44" - wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2221.6-2221.39" - wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2224.12-2224.44" - wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2223.6-2223.39" - wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2218.12-2218.44" - wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2217.6-2217.39" - wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2220.12-2220.44" - wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2219.6-2219.39" - wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2214.12-2214.44" - wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2213.6-2213.39" - wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2216.12-2216.44" - wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2215.6-2215.39" - wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2210.12-2210.44" - wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2209.6-2209.39" - wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2212.12-2212.44" - wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2211.6-2211.39" - wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2206.12-2206.44" - wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2205.6-2205.39" - wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2208.12-2208.44" - wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2207.6-2207.39" - wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2202.12-2202.44" - wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2201.6-2201.39" - wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2204.12-2204.44" - wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2203.6-2203.39" - wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2198.12-2198.44" - wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2197.6-2197.39" - wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2200.12-2200.44" - wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2199.6-2199.39" - wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2194.12-2194.44" - wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2193.6-2193.39" - wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2196.12-2196.44" - wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2195.6-2195.39" - wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2190.12-2190.44" - wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2189.6-2189.39" - wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2192.12-2192.44" - wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2191.6-2191.39" - wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2234.12-2234.41" - wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2233.6-2233.36" - wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2236.12-2236.41" - wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2235.6-2235.36" - wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2261.6-2261.26" - wire \builder_csrbank6_sel - attribute \src "ls180.v:2295.12-2295.40" - wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2294.6-2294.35" - wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2297.12-2297.40" - wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2296.6-2296.35" - wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2291.12-2291.40" - wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2290.6-2290.35" - wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2293.12-2293.40" - wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2292.6-2292.35" - wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2287.12-2287.40" - wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2286.6-2286.35" - wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2289.12-2289.40" - wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2288.6-2288.35" - wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2283.12-2283.40" - wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2282.6-2282.35" - wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2285.12-2285.40" - wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2284.6-2284.35" - wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2279.12-2279.40" - wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2278.6-2278.35" - wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2281.12-2281.40" - wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2280.6-2280.35" - wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2275.12-2275.40" - wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2274.6-2274.35" - wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2277.12-2277.40" - wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2276.6-2276.35" - wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2271.12-2271.40" - wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2270.6-2270.35" - wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2273.12-2273.40" - wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2272.6-2272.35" - wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2267.12-2267.40" - wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2266.6-2266.35" - wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2269.12-2269.40" - wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2268.6-2268.35" - wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2319.6-2319.33" - wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2318.6-2318.34" - wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2321.6-2321.33" - wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2320.6-2320.34" - wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2315.6-2315.36" - wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2314.6-2314.37" - wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2317.6-2317.36" - wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2316.6-2316.37" - wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2311.12-2311.42" - wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2310.6-2310.37" - wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2313.12-2313.42" - wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2312.6-2312.37" - wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2307.12-2307.42" - wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2306.6-2306.37" - wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2309.12-2309.42" - wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2308.6-2308.37" - wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2303.12-2303.42" - wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2302.6-2302.37" - wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2305.12-2305.42" - wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2304.6-2304.37" - wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2299.12-2299.42" - wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2298.6-2298.37" - wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2301.12-2301.42" - wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2300.6-2300.37" - wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2323.6-2323.34" - wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2322.6-2322.35" - wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2325.6-2325.34" - wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2324.6-2324.35" - wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2339.12-2339.42" - wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2338.6-2338.37" - wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2341.12-2341.42" - wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2340.6-2340.37" - wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2335.12-2335.42" - wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2334.6-2334.37" - wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2337.12-2337.42" - wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2336.6-2336.37" - wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2331.12-2331.42" - wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2330.6-2330.37" - wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2333.12-2333.42" - wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2332.6-2332.37" - wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2327.12-2327.42" - wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2326.6-2326.37" - wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2329.12-2329.42" - wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2328.6-2328.37" - wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2342.6-2342.26" - wire \builder_csrbank7_sel - attribute \src "ls180.v:2348.6-2348.36" - wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2347.6-2347.37" - wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2350.6-2350.36" - wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2349.6-2349.37" - wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2356.12-2356.47" - wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2355.6-2355.42" - wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2358.12-2358.47" - wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2357.6-2357.42" - wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2352.6-2352.41" - wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2351.6-2351.42" - wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2354.6-2354.41" - wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2353.6-2353.42" - wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2359.6-2359.26" - wire \builder_csrbank8_sel - attribute \src "ls180.v:2365.12-2365.44" - wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2364.6-2364.39" - wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2367.12-2367.44" - wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2366.6-2366.39" - wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2377.12-2377.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2376.6-2376.43" - wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2379.12-2379.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2378.6-2378.43" - wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2373.12-2373.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2372.6-2372.43" - wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2375.12-2375.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2374.6-2374.43" - wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2381.12-2381.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2380.6-2380.44" - wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2383.12-2383.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2382.6-2382.44" - wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2369.12-2369.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2368.6-2368.43" - wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2371.12-2371.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2370.6-2370.43" - wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2397.12-2397.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2396.6-2396.42" - wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2399.12-2399.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2398.6-2398.42" - wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2393.12-2393.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2392.6-2392.42" - wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2395.12-2395.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2394.6-2394.42" - wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2389.12-2389.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2388.6-2388.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2391.12-2391.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2390.6-2390.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2385.12-2385.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2384.6-2384.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2387.12-2387.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2386.6-2386.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2400.6-2400.26" - wire \builder_csrbank9_sel - attribute \src "ls180.v:1897.6-1897.18" - wire \builder_done - attribute \src "ls180.v:1895.5-1895.18" - wire \builder_error - attribute \src "ls180.v:1892.11-1892.24" - wire width 3 \builder_grant - attribute \src "ls180.v:1899.13-1899.44" - wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1902.11-1902.44" - wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1901.12-1901.45" - wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1900.6-1900.36" - wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2401.13-2401.45" - wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2404.11-2404.45" - wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2403.12-2403.46" - wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2402.6-2402.37" - wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2434.13-2434.45" - wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2437.11-2437.45" - wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2436.12-2436.46" - wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2435.6-2435.37" - wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2475.13-2475.45" - wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2478.11-2478.45" - wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2477.12-2477.46" - wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2476.6-2476.37" - wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2540.13-2540.45" - wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2543.11-2543.45" - wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2542.12-2542.46" - wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2541.6-2541.37" - wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2565.13-2565.45" - wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2568.11-2568.45" - wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2567.12-2567.46" - wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2566.6-2566.37" - wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:1940.13-1940.44" - wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1943.11-1943.44" - wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1942.12-1942.45" - wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1941.6-1941.36" - wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:1969.13-1969.44" - wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:1972.11-1972.44" - wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:1971.12-1971.45" - wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:1970.6-1970.36" - wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:1982.13-1982.44" - wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:1985.11-1985.44" - wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:1984.12-1984.45" - wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:1983.6-1983.36" - wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2023.13-2023.44" - wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2026.11-2026.44" - wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2025.12-2025.45" - wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2024.6-2024.36" - wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2064.13-2064.44" - wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2067.11-2067.44" - wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2066.12-2066.45" - wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2065.6-2065.36" - wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2129.13-2129.44" - wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2132.11-2132.44" - wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2131.12-2131.45" - wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2130.6-2130.36" - wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2262.13-2262.44" - wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2265.11-2265.44" - wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2264.12-2264.45" - wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2263.6-2263.36" - wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2343.13-2343.44" - wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2346.11-2346.44" - wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2345.12-2345.45" - wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2344.6-2344.36" - wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2360.13-2360.44" - wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2363.11-2363.44" - wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2362.12-2362.45" - wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2361.6-2361.36" - wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1865.12-1865.35" - wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2594.12-2594.47" - wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2595.5-2595.43" - wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1868.12-1868.37" - wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1867.11-1867.36" - wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2592.11-2592.48" - wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2593.5-2593.45" - wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1866.5-1866.27" - wire \builder_libresocsim_we - attribute \src "ls180.v:2596.5-2596.39" - wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2597.5-2597.42" - wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1875.5-1875.37" - wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1869.13-1869.45" - wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1878.12-1878.44" - wire width 2 \builder_libresocsim_wishbone_bte - attribute \src "ls180.v:1877.12-1877.44" - wire width 3 \builder_libresocsim_wishbone_cti - attribute \src "ls180.v:1873.6-1873.38" - wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1871.12-1871.46" - wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1870.13-1870.47" - wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1879.5-1879.37" - wire \builder_libresocsim_wishbone_err - attribute \src "ls180.v:1872.12-1872.44" - wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1874.6-1874.38" - wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1876.6-1876.37" - wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1768.5-1768.20" - wire \builder_locked0 - attribute \src "ls180.v:1769.5-1769.20" - wire \builder_locked1 - attribute \src "ls180.v:1770.5-1770.20" - wire \builder_locked2 - attribute \src "ls180.v:1771.5-1771.20" - wire \builder_locked3 - attribute \src "ls180.v:1755.11-1755.41" - wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1754.11-1754.36" - wire width 3 \builder_multiplexer_state - attribute \no_retiming "true" - attribute \src "ls180.v:2701.32-2701.59" - wire \builder_multiregimpl0_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2702.32-2702.59" - wire \builder_multiregimpl0_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2721.32-2721.60" - wire \builder_multiregimpl10_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2722.32-2722.60" - wire \builder_multiregimpl10_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2723.32-2723.60" - wire \builder_multiregimpl11_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2724.32-2724.60" - wire \builder_multiregimpl11_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2725.32-2725.60" - wire \builder_multiregimpl12_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2726.32-2726.60" - wire \builder_multiregimpl12_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2727.32-2727.60" - wire \builder_multiregimpl13_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2728.32-2728.60" - wire \builder_multiregimpl13_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2729.32-2729.60" - wire \builder_multiregimpl14_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2730.32-2730.60" - wire \builder_multiregimpl14_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2731.32-2731.60" - wire \builder_multiregimpl15_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2732.32-2732.60" - wire \builder_multiregimpl15_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2733.32-2733.60" - wire \builder_multiregimpl16_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2734.32-2734.60" - wire \builder_multiregimpl16_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2703.32-2703.59" - wire \builder_multiregimpl1_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2704.32-2704.59" - wire \builder_multiregimpl1_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2705.32-2705.59" - wire \builder_multiregimpl2_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2706.32-2706.59" - wire \builder_multiregimpl2_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2707.32-2707.59" - wire \builder_multiregimpl3_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2708.32-2708.59" - wire \builder_multiregimpl3_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2709.32-2709.59" - wire \builder_multiregimpl4_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2710.32-2710.59" - wire \builder_multiregimpl4_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2711.32-2711.59" - wire \builder_multiregimpl5_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2712.32-2712.59" - wire \builder_multiregimpl5_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2713.32-2713.59" - wire \builder_multiregimpl6_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2714.32-2714.59" - wire \builder_multiregimpl6_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2715.32-2715.59" - wire \builder_multiregimpl7_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2716.32-2716.59" - wire \builder_multiregimpl7_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2717.32-2717.59" - wire \builder_multiregimpl8_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2718.32-2718.59" - wire \builder_multiregimpl8_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2719.32-2719.59" - wire \builder_multiregimpl9_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2720.32-2720.59" - wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1773.5-1773.36" - wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1774.5-1774.36" - wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1775.5-1775.36" - wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1776.5-1776.36" - wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1772.5-1772.35" - wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2591.11-2591.29" - wire width 2 \builder_next_state - attribute \src "ls180.v:1745.11-1745.39" - wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1744.11-1744.34" - wire width 2 \builder_refresher_state - attribute \src "ls180.v:1891.12-1891.27" - wire width 5 \builder_request - attribute \src "ls180.v:1758.6-1758.28" - wire \builder_roundrobin0_ce - attribute \src "ls180.v:1757.6-1757.31" - wire \builder_roundrobin0_grant - attribute \src "ls180.v:1756.6-1756.33" - wire \builder_roundrobin0_request - attribute \src "ls180.v:1761.6-1761.28" - wire \builder_roundrobin1_ce - attribute \src "ls180.v:1760.6-1760.31" - wire \builder_roundrobin1_grant - attribute \src "ls180.v:1759.6-1759.33" - wire \builder_roundrobin1_request - attribute \src "ls180.v:1764.6-1764.28" - wire \builder_roundrobin2_ce - attribute \src "ls180.v:1763.6-1763.31" - wire \builder_roundrobin2_grant - attribute \src "ls180.v:1762.6-1762.33" - wire \builder_roundrobin2_request - attribute \src "ls180.v:1767.6-1767.28" - wire \builder_roundrobin3_ce - attribute \src "ls180.v:1766.6-1766.31" - wire \builder_roundrobin3_grant - attribute \src "ls180.v:1765.6-1765.33" - wire \builder_roundrobin3_request - attribute \src "ls180.v:1854.11-1854.44" - wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1853.11-1853.39" - wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1822.5-1822.50" - wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1821.5-1821.45" - wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1834.11-1834.40" - wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1833.11-1833.35" - wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1858.5-1858.42" - wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1857.5-1857.37" - wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1862.11-1862.58" - wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1861.11-1861.53" - wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1810.11-1810.39" - wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1809.11-1809.34" - wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1798.11-1798.45" - wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1797.11-1797.40" - wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1794.11-1794.45" - wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1793.11-1793.40" - wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1806.5-1806.39" - wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1805.5-1805.34" - wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1814.11-1814.46" - wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1813.11-1813.41" - wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1790.5-1790.39" - wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1789.5-1789.34" - wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1886.5-1886.23" - wire \builder_shared_ack - attribute \src "ls180.v:1880.13-1880.31" - wire width 30 \builder_shared_adr - attribute \src "ls180.v:1889.12-1889.30" - wire width 2 \builder_shared_bte - attribute \src "ls180.v:1888.12-1888.30" - wire width 3 \builder_shared_cti - attribute \src "ls180.v:1884.6-1884.24" - wire \builder_shared_cyc - attribute \src "ls180.v:1882.12-1882.32" - wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1881.13-1881.33" - wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1890.6-1890.24" - wire \builder_shared_err - attribute \src "ls180.v:1883.12-1883.30" - wire width 4 \builder_shared_sel - attribute \src "ls180.v:1885.6-1885.24" - wire \builder_shared_stb - attribute \src "ls180.v:1887.6-1887.23" - wire \builder_shared_we - attribute \src "ls180.v:1893.11-1893.28" - wire width 5 \builder_slave_sel - attribute \src "ls180.v:1894.11-1894.30" - wire width 5 \builder_slave_sel_r - attribute \src "ls180.v:1782.11-1782.40" - wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1781.11-1781.35" - wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1786.11-1786.40" - wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1785.11-1785.35" - wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2590.11-2590.24" - wire width 2 \builder_state - attribute \src "ls180.v:2643.5-2643.32" - wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2644.5-2644.32" - wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2636.11-2636.40" - wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2637.12-2637.41" - wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2638.5-2638.34" - wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2639.5-2639.34" - wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2640.5-2640.34" - wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2641.5-2641.34" - wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2642.5-2642.34" - wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1896.6-1896.18" - wire \builder_wait - attribute \src "ls180.v:37.20-37.24" - wire width 3 output 33 \eint - attribute \src "ls180.v:154.11-154.17" - wire width 3 \eint_1 - attribute \src "ls180.v:5.21-5.27" - wire width 16 output 1 \gpio_i - attribute \src "ls180.v:6.21-6.27" - wire width 16 output 2 \gpio_o - attribute \src "ls180.v:7.21-7.28" - wire width 16 output 3 \gpio_oe - attribute \src "ls180.v:17.14-17.21" - wire output 13 \i2c_scl - attribute \src "ls180.v:18.14-18.23" - wire output 14 \i2c_sda_i - attribute \src "ls180.v:19.14-19.23" - wire output 15 \i2c_sda_o - attribute \src "ls180.v:20.14-20.24" - wire output 16 \i2c_sda_oe - attribute \src "ls180.v:48.13-48.21" - wire input 44 \jtag_tck - attribute \src "ls180.v:49.13-49.21" - wire input 45 \jtag_tdi - attribute \src "ls180.v:50.14-50.22" - wire output 46 \jtag_tdo - attribute \src "ls180.v:47.13-47.21" - wire input 43 \jtag_tms - attribute \src "ls180.v:836.6-836.18" - wire \main_ack_cmd - attribute \src "ls180.v:838.6-838.20" - wire \main_ack_rdata - attribute \src "ls180.v:837.6-837.20" - wire \main_ack_wdata - attribute \src "ls180.v:834.5-834.22" - wire \main_cmd_consumed - attribute \src "ls180.v:831.5-831.27" - wire \main_converter_counter - attribute \src "ls180.v:1779.5-1779.48" - wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1780.5-1780.51" - wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:833.12-833.32" - wire width 32 \main_converter_dat_r - attribute \src "ls180.v:832.6-832.26" - wire \main_converter_reset - attribute \src "ls180.v:830.5-830.24" - wire \main_converter_skip - attribute \src "ls180.v:260.6-260.23" - wire \main_dfi_p0_act_n - attribute \src "ls180.v:251.13-251.32" - wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:252.12-252.28" - wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:253.6-253.23" - wire \main_dfi_p0_cas_n - attribute \src "ls180.v:257.6-257.21" - wire \main_dfi_p0_cke - attribute \src "ls180.v:254.6-254.22" - wire \main_dfi_p0_cs_n - attribute \src "ls180.v:258.6-258.21" - wire \main_dfi_p0_odt - attribute \src "ls180.v:255.6-255.23" - wire \main_dfi_p0_ras_n - attribute \src "ls180.v:265.12-265.30" - wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:264.6-264.27" - wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:266.5-266.29" - wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:259.6-259.25" - wire \main_dfi_p0_reset_n - attribute \src "ls180.v:256.6-256.22" - wire \main_dfi_p0_we_n - attribute \src "ls180.v:261.13-261.31" - wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:262.6-262.27" - wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:263.12-263.35" - wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1065.12-1065.22" - wire width 36 \main_dummy - attribute \src "ls180.v:982.5-982.20" - wire \main_gpio_oe_re - attribute \src "ls180.v:981.12-981.32" - wire width 16 \main_gpio_oe_storage - attribute \src "ls180.v:986.5-986.21" - wire \main_gpio_out_re - attribute \src "ls180.v:985.12-985.33" - wire width 16 \main_gpio_out_storage - attribute \src "ls180.v:987.13-987.29" - wire width 16 \main_gpio_pads_i - attribute \src "ls180.v:988.13-988.29" - wire width 16 \main_gpio_pads_o - attribute \src "ls180.v:989.13-989.30" - wire width 16 \main_gpio_pads_oe - attribute \src "ls180.v:983.12-983.28" - wire width 16 \main_gpio_status - attribute \src "ls180.v:984.6-984.18" - wire \main_gpio_we - attribute \src "ls180.v:1087.6-1087.17" - wire \main_i2c_oe - attribute \src "ls180.v:1090.5-1090.16" - wire \main_i2c_re - attribute \src "ls180.v:1086.6-1086.18" - wire \main_i2c_scl - attribute \src "ls180.v:1088.6-1088.19" - wire \main_i2c_sda0 - attribute \src "ls180.v:1091.6-1091.19" - wire \main_i2c_sda1 - attribute \src "ls180.v:1092.6-1092.21" - wire \main_i2c_status - attribute \src "ls180.v:1089.11-1089.27" - wire width 3 \main_i2c_storage - attribute \src "ls180.v:1093.6-1093.17" - wire \main_i2c_we - attribute \src "ls180.v:250.5-250.17" - wire \main_int_rst - attribute \src "ls180.v:1553.6-1553.29" - wire \main_interface0_bus_ack - attribute \src "ls180.v:1547.13-1547.36" - wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1556.11-1556.34" - wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1555.11-1555.34" - wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1551.6-1551.29" - wire \main_interface0_bus_cyc - attribute \src "ls180.v:1549.13-1549.38" - wire width 32 \main_interface0_bus_dat_r - attribute \src "ls180.v:1548.13-1548.38" - wire width 32 \main_interface0_bus_dat_w - attribute \src "ls180.v:1557.6-1557.29" - wire \main_interface0_bus_err - attribute \src "ls180.v:1550.12-1550.35" - wire width 4 \main_interface0_bus_sel - attribute \src "ls180.v:1552.6-1552.29" - wire \main_interface0_bus_stb - attribute \src "ls180.v:1554.6-1554.28" - wire \main_interface0_bus_we - attribute \src "ls180.v:1644.6-1644.29" - wire \main_interface1_bus_ack - attribute \src "ls180.v:1638.12-1638.35" - wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1647.11-1647.34" - wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1646.11-1646.34" - wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1642.5-1642.28" - wire \main_interface1_bus_cyc - attribute \src "ls180.v:1640.13-1640.38" - wire width 32 \main_interface1_bus_dat_r - attribute \src "ls180.v:1639.12-1639.37" - wire width 32 \main_interface1_bus_dat_w - attribute \src "ls180.v:1648.6-1648.29" - wire \main_interface1_bus_err - attribute \src "ls180.v:1641.11-1641.34" - wire width 4 \main_interface1_bus_sel - attribute \src "ls180.v:1643.5-1643.28" - wire \main_interface1_bus_stb - attribute \src "ls180.v:1645.5-1645.27" - wire \main_interface1_bus_we - attribute \src "ls180.v:216.12-216.32" - wire width 7 \main_libresocsim_adr - attribute \src "ls180.v:61.6-61.32" - wire \main_libresocsim_bus_error - attribute \src "ls180.v:62.12-62.39" - wire width 32 \main_libresocsim_bus_errors - attribute \src "ls180.v:58.13-58.47" - wire width 32 \main_libresocsim_bus_errors_status - attribute \src "ls180.v:59.6-59.36" - wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:172.5-172.40" - wire \main_libresocsim_converter0_counter - attribute \src "ls180.v:1734.5-1734.62" - wire \main_libresocsim_converter0_counter_converter0_next_value - attribute \src "ls180.v:1735.5-1735.65" - wire \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:174.12-174.45" - wire width 64 \main_libresocsim_converter0_dat_r - attribute \src "ls180.v:173.6-173.39" - wire \main_libresocsim_converter0_reset - attribute \src "ls180.v:171.5-171.37" - wire \main_libresocsim_converter0_skip - attribute \src "ls180.v:187.5-187.40" - wire \main_libresocsim_converter1_counter - attribute \src "ls180.v:1738.5-1738.62" - wire \main_libresocsim_converter1_counter_converter1_next_value - attribute \src "ls180.v:1739.5-1739.65" - wire \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:189.12-189.45" - wire width 64 \main_libresocsim_converter1_dat_r - attribute \src "ls180.v:188.6-188.39" - wire \main_libresocsim_converter1_reset - attribute \src "ls180.v:186.5-186.37" - wire \main_libresocsim_converter1_skip - attribute \src "ls180.v:202.5-202.40" - wire \main_libresocsim_converter2_counter - attribute \src "ls180.v:1742.5-1742.62" - wire \main_libresocsim_converter2_counter_converter2_next_value - attribute \src "ls180.v:1743.5-1743.65" - wire \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:204.12-204.45" - wire width 64 \main_libresocsim_converter2_dat_r - attribute \src "ls180.v:203.6-203.39" - wire \main_libresocsim_converter2_reset - attribute \src "ls180.v:201.5-201.37" - wire \main_libresocsim_converter2_skip - attribute \src "ls180.v:217.13-217.35" - wire width 32 \main_libresocsim_dat_r - attribute \src "ls180.v:219.13-219.35" - wire width 32 \main_libresocsim_dat_w - attribute \src "ls180.v:225.5-225.27" - wire \main_libresocsim_en_re - attribute \src "ls180.v:224.5-224.32" - wire \main_libresocsim_en_storage - attribute \src "ls180.v:241.6-241.45" - wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:240.6-240.46" - wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:243.6-243.45" - wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:242.6-242.46" - wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:245.5-245.37" - wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:237.6-237.44" - wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:236.6-236.45" - wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:239.6-239.44" - wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:238.6-238.45" - wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:244.5-244.42" - wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:166.6-166.57" - wire \main_libresocsim_interface0_converted_interface_ack - attribute \src "ls180.v:160.12-160.63" - wire width 30 \main_libresocsim_interface0_converted_interface_adr - attribute \src "ls180.v:169.11-169.62" - wire width 2 \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:168.11-168.62" - wire width 3 \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:164.5-164.56" - wire \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:162.13-162.66" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_r - attribute \src "ls180.v:161.12-161.65" - wire width 32 \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:170.6-170.57" - wire \main_libresocsim_interface0_converted_interface_err - attribute \src "ls180.v:163.11-163.62" - wire width 4 \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:165.5-165.56" - wire \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:167.5-167.55" - wire \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:181.6-181.57" - wire \main_libresocsim_interface1_converted_interface_ack - attribute \src "ls180.v:175.12-175.63" - wire width 30 \main_libresocsim_interface1_converted_interface_adr - attribute \src "ls180.v:184.11-184.62" - wire width 2 \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:183.11-183.62" - wire width 3 \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:179.5-179.56" - wire \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:177.13-177.66" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_r - attribute \src "ls180.v:176.12-176.65" - wire width 32 \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:185.6-185.57" - wire \main_libresocsim_interface1_converted_interface_err - attribute \src "ls180.v:178.11-178.62" - wire width 4 \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:180.5-180.56" - wire \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:182.5-182.55" - wire \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:196.6-196.57" - wire \main_libresocsim_interface2_converted_interface_ack - attribute \src "ls180.v:190.12-190.63" - wire width 30 \main_libresocsim_interface2_converted_interface_adr - attribute \src "ls180.v:199.11-199.62" - wire width 2 \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:198.11-198.62" - wire width 3 \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:194.5-194.56" - wire \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:192.13-192.66" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_r - attribute \src "ls180.v:191.12-191.65" - wire width 32 \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:200.6-200.57" - wire \main_libresocsim_interface2_converted_interface_err - attribute \src "ls180.v:193.11-193.62" - wire width 4 \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:195.5-195.56" - wire \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:197.5-197.55" - wire \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:230.6-230.26" - wire \main_libresocsim_irq - attribute \src "ls180.v:122.6-122.32" - wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:123.6-123.32" - wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:124.13-124.39" - wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:126.12-126.45" - wire width 3 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:127.12-127.66" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:128.13-128.67" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:129.13-129.68" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:134.6-134.61" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:135.5-135.62" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:136.6-136.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:137.6-137.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:130.6-130.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:131.5-131.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:132.6-132.66" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:133.6-133.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:142.13-142.68" - wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:151.12-151.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:148.6-148.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:150.6-150.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:149.6-149.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:152.12-152.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:143.12-143.70" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:144.13-144.71" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:145.6-145.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:147.6-147.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:146.6-146.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:138.6-138.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:140.6-140.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:141.5-141.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:139.6-139.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:156.6-156.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:158.6-158.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:159.5-159.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:157.6-157.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - attribute \src "ls180.v:71.5-71.39" - wire \main_libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:65.13-65.47" - wire width 29 \main_libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:74.12-74.46" - wire width 2 \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:73.12-73.46" - wire width 3 \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:69.6-69.40" - wire \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:67.13-67.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:66.13-66.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:75.5-75.39" - wire \main_libresocsim_libresoc_dbus_err - attribute \src "ls180.v:68.12-68.46" - wire width 8 \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:70.6-70.40" - wire \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:72.6-72.39" - wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:82.5-82.39" - wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:76.13-76.47" - wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:85.12-85.46" - wire width 2 \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:84.12-84.46" - wire width 3 \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:80.6-80.40" - wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:78.13-78.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:77.13-77.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:86.5-86.39" - wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:79.12-79.46" - wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:81.6-81.40" - wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:83.6-83.39" - wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:64.12-64.47" - wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:118.6-118.40" - wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:120.6-120.40" - wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:121.6-121.40" - wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:119.6-119.40" - wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:115.5-115.42" - wire \main_libresocsim_libresoc_jtag_wb_ack - attribute \src "ls180.v:109.13-109.50" - wire width 29 \main_libresocsim_libresoc_jtag_wb_adr - attribute \src "ls180.v:113.6-113.43" - wire \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:111.13-111.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r - attribute \src "ls180.v:110.13-110.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:117.5-117.42" - wire \main_libresocsim_libresoc_jtag_wb_err - attribute \src "ls180.v:112.12-112.49" - wire width 8 \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:114.6-114.43" - wire \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:116.6-116.42" - wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:125.6-125.40" - wire \main_libresocsim_libresoc_pll_48_o - attribute \src "ls180.v:63.6-63.37" - wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:93.6-93.44" - wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:87.13-87.51" - wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:96.12-96.50" - wire width 2 \main_libresocsim_libresoc_xics_icp_bte - attribute \src "ls180.v:95.12-95.50" - wire width 3 \main_libresocsim_libresoc_xics_icp_cti - attribute \src "ls180.v:91.6-91.44" - wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:89.13-89.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:88.13-88.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:97.6-97.44" - wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:90.12-90.50" - wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:92.6-92.44" - wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:94.6-94.43" - wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:104.6-104.44" - wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:98.13-98.51" - wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:107.12-107.50" - wire width 2 \main_libresocsim_libresoc_xics_ics_bte - attribute \src "ls180.v:106.12-106.50" - wire width 3 \main_libresocsim_libresoc_xics_ics_cti - attribute \src "ls180.v:102.6-102.44" - wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:100.13-100.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:99.13-99.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:108.6-108.44" - wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:101.12-101.50" - wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:103.6-103.44" - wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:105.6-105.43" - wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:221.5-221.29" - wire \main_libresocsim_load_re - attribute \src "ls180.v:220.12-220.41" - wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:211.5-211.33" - wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:205.13-205.41" - wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:214.12-214.40" - wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:213.12-213.40" - wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:209.6-209.34" - wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:207.13-207.43" - wire width 32 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:206.13-206.43" - wire width 32 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:215.5-215.33" - wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:208.12-208.40" - wire width 4 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:210.6-210.34" - wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:212.6-212.33" - wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:223.5-223.31" - wire \main_libresocsim_reload_re - attribute \src "ls180.v:222.12-222.43" - wire width 32 \main_libresocsim_reload_storage - attribute \src "ls180.v:60.6-60.28" - wire \main_libresocsim_reset - attribute \src "ls180.v:55.5-55.30" - wire \main_libresocsim_reset_re - attribute \src "ls180.v:54.5-54.35" - wire \main_libresocsim_reset_storage - attribute \src "ls180.v:57.5-57.32" - wire \main_libresocsim_scratch_re - attribute \src "ls180.v:56.12-56.44" - wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:227.5-227.37" - wire \main_libresocsim_update_value_re - attribute \src "ls180.v:226.5-226.42" - wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:246.12-246.34" - wire width 32 \main_libresocsim_value - attribute \src "ls180.v:228.12-228.41" - wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:229.6-229.31" - wire \main_libresocsim_value_we - attribute \src "ls180.v:218.11-218.30" - wire width 4 \main_libresocsim_we - attribute \src "ls180.v:234.5-234.32" - wire \main_libresocsim_zero_clear - attribute \src "ls180.v:235.5-235.38" - wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:232.5-232.34" - wire \main_libresocsim_zero_pending - attribute \src "ls180.v:231.6-231.34" - wire \main_libresocsim_zero_status - attribute \src "ls180.v:233.6-233.35" - wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:828.6-828.26" - wire \main_litedram_wb_ack - attribute \src "ls180.v:822.12-822.32" - wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:826.5-826.25" - wire \main_litedram_wb_cyc - attribute \src "ls180.v:824.13-824.35" - wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:823.12-823.34" - wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:825.11-825.31" - wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:827.5-827.25" - wire \main_litedram_wb_stb - attribute \src "ls180.v:829.5-829.24" - wire \main_litedram_wb_we - attribute \src "ls180.v:1064.13-1064.20" - wire width 36 \main_nc - attribute \src "ls180.v:801.6-801.24" - wire \main_port_cmd_last - attribute \src "ls180.v:803.13-803.39" - wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:802.6-802.30" - wire \main_port_cmd_payload_we - attribute \src "ls180.v:800.6-800.25" - wire \main_port_cmd_ready - attribute \src "ls180.v:799.6-799.25" - wire \main_port_cmd_valid - attribute \src "ls180.v:798.6-798.21" - wire \main_port_flush - attribute \src "ls180.v:810.13-810.41" - wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:809.6-809.27" - wire \main_port_rdata_ready - attribute \src "ls180.v:808.6-808.27" - wire \main_port_rdata_valid - attribute \src "ls180.v:806.13-806.41" - wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:807.12-807.38" - wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:805.6-805.27" - wire \main_port_wdata_ready - attribute \src "ls180.v:804.6-804.27" - wire \main_port_wdata_valid - attribute \src "ls180.v:1069.12-1069.29" - wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1066.6-1066.22" - wire \main_pwm0_enable - attribute \src "ls180.v:1071.5-1071.24" - wire \main_pwm0_enable_re - attribute \src "ls180.v:1070.5-1070.29" - wire \main_pwm0_enable_storage - attribute \src "ls180.v:1068.13-1068.29" - wire width 32 \main_pwm0_period - attribute \src "ls180.v:1075.5-1075.24" - wire \main_pwm0_period_re - attribute \src "ls180.v:1074.12-1074.36" - wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1067.13-1067.28" - wire width 32 \main_pwm0_width - attribute \src "ls180.v:1073.5-1073.23" - wire \main_pwm0_width_re - attribute \src "ls180.v:1072.12-1072.35" - wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1079.12-1079.29" - wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1076.6-1076.22" - wire \main_pwm1_enable - attribute \src "ls180.v:1081.5-1081.24" - wire \main_pwm1_enable_re - attribute \src "ls180.v:1080.5-1080.29" - wire \main_pwm1_enable_storage - attribute \src "ls180.v:1078.13-1078.29" - wire width 32 \main_pwm1_period - attribute \src "ls180.v:1085.5-1085.24" - wire \main_pwm1_period_re - attribute \src "ls180.v:1084.12-1084.36" - wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1077.13-1077.28" - wire width 32 \main_pwm1_width - attribute \src "ls180.v:1083.5-1083.23" - wire \main_pwm1_width_re - attribute \src "ls180.v:1082.12-1082.35" - wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:267.11-267.25" - wire width 3 \main_rddata_en - attribute \src "ls180.v:1607.11-1607.43" - wire width 2 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1608.6-1608.42" - wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1598.6-1598.43" - wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1599.6-1599.42" - wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1600.12-1600.56" - wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1597.6-1597.43" - wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1596.6-1596.43" - wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1603.5-1603.44" - wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1604.5-1604.43" - wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1605.12-1605.58" - wire width 32 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1606.11-1606.70" - wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1602.6-1602.45" - wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1601.6-1601.45" - wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1609.5-1609.42" - wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1582.11-1582.40" - wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1587.6-1587.35" - wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1591.6-1591.41" - wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1592.6-1592.40" - wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1590.12-1590.54" - wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1594.6-1594.42" - wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1595.6-1595.41" - wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1593.12-1593.55" - wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1579.11-1579.38" - wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1581.11-1581.40" - wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1588.12-1588.44" - wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1589.12-1589.46" - wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1580.5-1580.34" - wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1565.6-1565.38" - wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1566.6-1566.37" - wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1567.12-1567.51" - wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1564.6-1564.38" - wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1563.6-1563.38" - wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1570.6-1570.40" - wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1571.6-1571.39" - wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1572.12-1572.53" - wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1569.6-1569.40" - wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1568.6-1568.40" - wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1577.12-1577.46" - wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1578.12-1578.47" - wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1575.6-1575.39" - wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1576.6-1576.45" - wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1573.6-1573.39" - wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1574.6-1574.45" - wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1583.11-1583.43" - wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1584.12-1584.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1586.12-1586.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1585.6-1585.37" - wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1560.6-1560.38" - wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1561.6-1561.37" - wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1617.12-1617.54" - wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1562.12-1562.52" - wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1618.12-1618.52" - wire width 32 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1559.6-1559.39" - wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1616.6-1616.39" - wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1558.6-1558.39" - wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1615.5-1615.38" - wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1612.6-1612.42" - wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1613.6-1613.41" - wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1614.13-1614.56" - wire width 32 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1611.6-1611.42" - wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1610.6-1610.42" - wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1634.13-1634.52" - wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1625.5-1625.47" - wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1624.12-1624.59" - wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1629.5-1629.49" - wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1628.5-1628.54" - wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1636.13-1636.54" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1627.5-1627.49" - wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1626.12-1626.61" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1633.5-1633.47" - wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1632.5-1632.52" - wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1635.12-1635.53" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1855.12-1855.79" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1856.5-1856.75" - wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1637.6-1637.46" - wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1621.6-1621.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1622.6-1622.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1623.13-1623.65" - wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1620.5-1620.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1619.6-1619.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1630.5-1630.46" - wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1631.6-1631.43" - wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1399.5-1399.31" - wire \main_sdcore_block_count_re - attribute \src "ls180.v:1398.12-1398.43" - wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1397.5-1397.32" - wire \main_sdcore_block_length_re - attribute \src "ls180.v:1396.11-1396.43" - wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1383.5-1383.32" - wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1382.12-1382.44" - wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1385.5-1385.31" - wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1384.12-1384.43" - wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1538.11-1538.32" - wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1839.11-1839.55" - wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1840.5-1840.52" - wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1539.5-1539.25" - wire \main_sdcore_cmd_done - attribute \src "ls180.v:1835.5-1835.48" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1836.5-1836.51" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1540.5-1540.26" - wire \main_sdcore_cmd_error - attribute \src "ls180.v:1843.5-1843.49" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1844.5-1844.52" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1392.12-1392.40" - wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1393.6-1393.30" - wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1390.13-1390.44" - wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1851.13-1851.67" - wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1852.5-1852.62" - wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1391.6-1391.33" - wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1387.6-1387.28" - wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1386.6-1386.29" - wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1389.5-1389.27" - wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1388.6-1388.29" - wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1541.5-1541.28" - wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1845.5-1845.51" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1846.5-1846.54" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1537.12-1537.32" - wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1499.11-1499.40" - wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1505.5-1505.39" - wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1504.12-1504.46" - wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1500.12-1500.50" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1501.13-1501.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1502.13-1502.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1506.6-1506.43" - wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1503.12-1503.46" - wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1512.5-1512.39" - wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1511.12-1511.46" - wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1507.12-1507.50" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1508.13-1508.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1509.13-1509.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1513.6-1513.43" - wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1510.12-1510.46" - wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1519.5-1519.39" - wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1518.12-1518.46" - wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1514.12-1514.50" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1515.13-1515.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1516.13-1516.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1520.6-1520.43" - wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1517.12-1517.46" - wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1526.5-1526.39" - wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1525.12-1525.46" - wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1521.12-1521.50" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1522.13-1522.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1523.13-1523.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1527.6-1527.43" - wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1524.12-1524.46" - wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1528.12-1528.45" - wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1529.12-1529.45" - wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1530.12-1530.45" - wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1531.12-1531.45" - wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1533.12-1533.43" - wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1534.12-1534.43" - wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1535.12-1535.43" - wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1536.12-1536.43" - wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1490.5-1490.41" - wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1491.5-1491.40" - wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1492.11-1492.54" - wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1489.5-1489.41" - wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1488.5-1488.41" - wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1495.5-1495.43" - wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1496.6-1496.43" - wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1497.12-1497.57" - wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1494.6-1494.44" - wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1493.5-1493.43" - wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1498.11-1498.40" - wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1532.5-1532.36" - wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1455.11-1455.41" - wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1831.11-1831.80" - wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1832.5-1832.77" - wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1461.6-1461.41" - wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1460.12-1460.47" - wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1456.12-1456.51" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1457.13-1457.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1458.13-1458.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1462.6-1462.44" - wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1459.12-1459.47" - wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1468.6-1468.41" - wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1467.12-1467.47" - wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1463.12-1463.51" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1464.13-1464.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1465.13-1465.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1469.6-1469.44" - wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1466.12-1466.47" - wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1475.6-1475.41" - wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1474.12-1474.47" - wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1470.12-1470.51" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1471.13-1471.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1472.13-1472.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1476.6-1476.44" - wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1473.12-1473.47" - wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1482.6-1482.41" - wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1481.12-1481.47" - wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1477.12-1477.51" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1478.13-1478.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1479.13-1479.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1483.6-1483.44" - wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1480.12-1480.47" - wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1484.12-1484.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1823.12-1823.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1824.5-1824.81" - wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1485.12-1485.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1825.12-1825.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1826.5-1826.81" - wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1486.12-1486.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1827.12-1827.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1828.5-1828.81" - wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1487.12-1487.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1829.12-1829.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1830.5-1830.81" - wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1447.6-1447.43" - wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1448.6-1448.42" - wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1449.12-1449.56" - wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1446.5-1446.42" - wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1445.6-1445.43" - wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1452.5-1452.44" - wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1453.5-1453.43" - wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1454.11-1454.57" - wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1451.5-1451.44" - wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1450.5-1450.44" - wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1443.6-1443.35" - wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1442.11-1442.40" - wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1400.11-1400.44" - wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1401.12-1401.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1410.12-1410.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1411.12-1411.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1412.12-1412.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1413.12-1413.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1414.12-1414.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1415.12-1415.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1416.12-1416.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1417.12-1417.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1418.12-1418.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1419.12-1419.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1402.12-1402.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1420.12-1420.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1421.12-1421.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1422.12-1422.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1423.12-1423.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1424.12-1424.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1425.12-1425.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1426.12-1426.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1427.12-1427.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1428.12-1428.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1429.12-1429.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1403.12-1403.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1430.12-1430.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1431.12-1431.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1432.12-1432.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1433.12-1433.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1434.12-1434.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1435.12-1435.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1436.12-1436.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1437.12-1437.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1438.12-1438.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1439.12-1439.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1404.12-1404.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1440.12-1440.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1405.12-1405.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1406.12-1406.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1407.12-1407.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1408.12-1408.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1409.12-1409.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1444.6-1444.38" - wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1441.13-1441.42" - wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1543.12-1543.34" - wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1841.12-1841.57" - wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1842.5-1842.53" - wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1544.5-1544.26" - wire \main_sdcore_data_done - attribute \src "ls180.v:1837.5-1837.49" - wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1838.5-1838.52" - wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1545.5-1545.27" - wire \main_sdcore_data_error - attribute \src "ls180.v:1847.5-1847.50" - wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1848.5-1848.53" - wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1394.12-1394.41" - wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1395.6-1395.31" - wire \main_sdcore_data_event_we - attribute \src "ls180.v:1546.5-1546.29" - wire \main_sdcore_data_timeout - attribute \src "ls180.v:1849.5-1849.52" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1850.5-1850.55" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1542.12-1542.33" - wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1374.6-1374.33" - wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1375.6-1375.32" - wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1376.12-1376.46" - wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1373.6-1373.33" - wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1372.6-1372.33" - wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1379.6-1379.37" - wire \main_sdcore_source_source_first - attribute \src "ls180.v:1380.6-1380.36" - wire \main_sdcore_source_source_last - attribute \src "ls180.v:1381.12-1381.50" - wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1378.6-1378.37" - wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1377.6-1377.37" - wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1692.6-1692.38" - wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1693.6-1693.37" - wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1691.11-1691.41" - wire width 2 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1682.6-1682.43" - wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1683.6-1683.42" - wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1684.13-1684.57" - wire width 32 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1681.6-1681.43" - wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1680.6-1680.43" - wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1687.6-1687.45" - wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1688.6-1688.44" - wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1689.11-1689.57" - wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1690.6-1690.65" - wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1686.6-1686.45" - wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1685.6-1685.45" - wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1676.13-1676.38" - wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1665.5-1665.33" - wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1664.12-1664.45" - wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1663.12-1663.37" - wire width 32 \main_sdmem2block_dma_data - attribute \src "ls180.v:1859.12-1859.67" - wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1860.5-1860.63" - wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1670.5-1670.37" - wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1671.6-1671.34" - wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1669.5-1669.35" - wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1668.5-1668.40" - wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1678.13-1678.40" - wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1667.5-1667.35" - wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1666.12-1666.47" - wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1673.5-1673.33" - wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1672.5-1672.38" - wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1677.12-1677.39" - wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1863.12-1863.79" - wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1864.5-1864.75" - wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1674.13-1674.47" - wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1675.6-1675.36" - wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1679.6-1679.32" - wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1656.5-1656.35" - wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1657.12-1657.53" - wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1655.5-1655.36" - wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1654.5-1654.36" - wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1660.5-1660.38" - wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1661.5-1661.37" - wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1662.12-1662.52" - wire width 32 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1659.6-1659.39" - wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1658.5-1658.38" - wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1718.11-1718.40" - wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1723.6-1723.35" - wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1727.6-1727.41" - wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1728.6-1728.40" - wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1726.12-1726.54" - wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1730.6-1730.42" - wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1731.6-1731.41" - wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1729.12-1729.55" - wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1715.11-1715.38" - wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1717.11-1717.40" - wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1724.12-1724.44" - wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1725.12-1725.46" - wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1716.5-1716.34" - wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1701.6-1701.38" - wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1702.6-1702.37" - wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1703.12-1703.51" - wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1700.6-1700.38" - wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1699.6-1699.38" - wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1706.6-1706.40" - wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1707.6-1707.39" - wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1708.12-1708.53" - wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1705.6-1705.40" - wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1704.6-1704.40" - wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1713.12-1713.46" - wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1714.12-1714.47" - wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1711.6-1711.39" - wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1712.6-1712.45" - wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1709.6-1709.39" - wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1710.6-1710.45" - wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1719.11-1719.43" - wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1720.12-1720.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1722.12-1722.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1721.6-1721.37" - wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1651.6-1651.43" - wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1696.6-1696.43" - wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1652.6-1652.42" - wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1697.6-1697.42" - wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1653.12-1653.56" - wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1698.12-1698.56" - wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1650.6-1650.43" - wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1695.6-1695.43" - wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1649.6-1649.43" - wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1694.6-1694.43" - wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1100.6-1100.27" - wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1099.5-1099.28" - wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1102.5-1102.28" - wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1103.5-1103.29" - wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1101.11-1101.34" - wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1097.5-1097.26" - wire \main_sdphy_clocker_re - attribute \src "ls180.v:1098.6-1098.29" - wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1096.11-1096.37" - wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1200.6-1200.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1201.6-1201.40" - wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1202.12-1202.54" - wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1199.6-1199.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1198.6-1198.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1205.5-1205.42" - wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1206.5-1206.41" - wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1207.11-1207.55" - wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1204.6-1204.43" - wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1203.5-1203.42" - wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1190.11-1190.47" - wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1191.6-1191.46" - wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1181.5-1181.46" - wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1182.5-1182.45" - wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1183.6-1183.54" - wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1180.6-1180.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1179.6-1179.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1186.5-1186.48" - wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1187.5-1187.47" - wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1188.11-1188.61" - wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1189.11-1189.74" - wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1185.6-1185.49" - wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1184.6-1184.49" - wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1192.5-1192.46" - wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1163.6-1163.40" - wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1164.6-1164.39" - wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1165.6-1165.46" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1166.6-1166.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1167.6-1167.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1168.6-1168.49" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1169.12-1169.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1170.12-1170.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1171.6-1171.50" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1162.5-1162.39" - wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1161.6-1161.40" - wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1208.5-1208.31" - wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1803.5-1803.59" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1804.5-1804.62" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1178.5-1178.29" - wire \main_sdphy_cmdr_cmdr_run - attribute \src "ls180.v:1174.6-1174.47" - wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1195.6-1195.47" - wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1175.6-1175.46" - wire \main_sdphy_cmdr_cmdr_source_source_last0 - attribute \src "ls180.v:1196.6-1196.46" - wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1176.12-1176.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1197.12-1197.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1173.5-1173.46" - wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1194.6-1194.47" - wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1172.6-1172.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1193.6-1193.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1177.6-1177.32" - wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1160.11-1160.32" - wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1799.11-1799.60" - wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1800.5-1800.57" - wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1135.5-1135.42" - wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1136.5-1136.41" - wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1137.5-1137.48" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1138.6-1138.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1139.5-1139.50" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1140.5-1140.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1141.12-1141.58" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1142.11-1142.57" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1143.5-1143.52" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1134.6-1134.43" - wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1133.6-1133.43" - wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1145.5-1145.41" - wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1146.5-1146.43" - wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1147.5-1147.44" - wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1148.11-1148.50" - wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1149.5-1149.45" - wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1144.6-1144.36" - wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1152.5-1152.30" - wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1153.11-1153.46" - wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1151.5-1151.31" - wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1150.5-1150.31" - wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1156.5-1156.32" - wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1157.11-1157.46" - wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1158.11-1158.48" - wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1155.5-1155.33" - wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1154.5-1154.33" - wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1159.12-1159.35" - wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1801.12-1801.63" - wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1802.5-1802.59" - wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1132.11-1132.32" - wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1795.11-1795.59" - wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1796.5-1796.56" - wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1131.5-1131.25" - wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1119.6-1119.43" - wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1120.12-1120.50" - wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1118.6-1118.35" - wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1122.5-1122.41" - wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1123.5-1123.43" - wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1124.5-1124.44" - wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1125.11-1125.50" - wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1126.5-1126.45" - wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1121.6-1121.36" - wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1129.5-1129.30" - wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1130.11-1130.44" - wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1128.5-1128.31" - wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1127.5-1127.31" - wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1316.11-1316.33" - wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1815.11-1815.62" - wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1816.5-1816.59" - wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1356.6-1356.43" - wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1357.6-1357.42" - wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1358.12-1358.56" - wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1355.6-1355.43" - wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1354.6-1354.43" - wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1361.5-1361.44" - wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1362.5-1362.43" - wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1363.11-1363.57" - wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1360.6-1360.45" - wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1359.5-1359.44" - wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1346.5-1346.43" - wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1347.6-1347.48" - wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1337.5-1337.48" - wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1338.5-1338.47" - wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1339.12-1339.62" - wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1336.6-1336.49" - wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1335.6-1335.49" - wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1342.5-1342.50" - wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1343.5-1343.49" - wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1344.11-1344.63" - wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1345.11-1345.76" - wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1341.6-1341.51" - wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1340.6-1340.51" - wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1348.5-1348.48" - wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1319.6-1319.42" - wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1320.6-1320.41" - wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1321.6-1321.48" - wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1322.6-1322.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1323.6-1323.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1324.6-1324.51" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1325.12-1325.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1326.12-1326.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1327.6-1327.52" - wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1318.5-1318.41" - wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1317.6-1317.42" - wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1364.5-1364.33" - wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1819.5-1819.62" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1820.5-1820.65" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1334.5-1334.31" - wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1330.6-1330.49" - wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1351.6-1351.49" - wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1331.6-1331.48" - wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1352.6-1352.48" - wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1332.12-1332.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1353.12-1353.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1329.5-1329.48" - wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1350.6-1350.49" - wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1328.6-1328.49" - wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1349.6-1349.49" - wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1333.6-1333.34" - wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1289.5-1289.43" - wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1290.5-1290.42" - wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1291.5-1291.49" - wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1292.6-1292.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1293.5-1293.51" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1294.5-1294.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1295.12-1295.59" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1296.11-1296.58" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1297.5-1297.53" - wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1288.6-1288.44" - wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1287.6-1287.44" - wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1299.5-1299.42" - wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1300.5-1300.44" - wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1301.5-1301.45" - wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1302.11-1302.51" - wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1303.5-1303.46" - wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1298.6-1298.37" - wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1306.5-1306.31" - wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1307.11-1307.53" - wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1305.5-1305.32" - wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1304.5-1304.32" - wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1310.5-1310.34" - wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1311.5-1311.33" - wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1312.11-1312.47" - wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1313.11-1313.49" - wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1309.5-1309.34" - wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1308.5-1308.34" - wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1314.5-1314.26" - wire \main_sdphy_datar_stop - attribute \src "ls180.v:1315.12-1315.36" - wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1817.12-1817.65" - wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1818.5-1818.61" - wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1224.11-1224.33" - wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1811.11-1811.54" - wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1812.5-1812.51" - wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1278.6-1278.42" - wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1279.6-1279.41" - wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1280.12-1280.55" - wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1277.6-1277.42" - wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1276.6-1276.42" - wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1283.5-1283.43" - wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1284.5-1284.42" - wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1285.11-1285.56" - wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1282.6-1282.44" - wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1281.5-1281.43" - wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1268.11-1268.48" - wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1269.6-1269.47" - wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1259.5-1259.47" - wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1260.5-1260.46" - wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1261.6-1261.55" - wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1258.6-1258.48" - wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1257.6-1257.48" - wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1264.5-1264.49" - wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1265.5-1265.48" - wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1266.11-1266.62" - wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1267.11-1267.75" - wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1263.6-1263.50" - wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1262.6-1262.50" - wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1270.5-1270.47" - wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1241.6-1241.41" - wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1242.6-1242.40" - wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1243.6-1243.47" - wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1244.6-1244.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1245.6-1245.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1246.6-1246.50" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1247.12-1247.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1248.12-1248.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1249.6-1249.51" - wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1240.5-1240.40" - wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1239.6-1239.41" - wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1286.5-1286.32" - wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1807.5-1807.59" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1808.5-1808.62" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1256.5-1256.30" - wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1252.6-1252.48" - wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1273.6-1273.48" - wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1253.6-1253.47" - wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1274.6-1274.47" - wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1254.12-1254.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1275.12-1275.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1251.5-1251.47" - wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1272.6-1272.48" - wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1250.6-1250.48" - wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1271.6-1271.48" - wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1255.6-1255.33" - wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1238.5-1238.27" - wire \main_sdphy_dataw_error - attribute \src "ls180.v:1227.5-1227.43" - wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1228.5-1228.42" - wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1229.5-1229.49" - wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1230.5-1230.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1231.5-1231.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1232.5-1232.52" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1233.11-1233.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1234.11-1234.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1235.5-1235.53" - wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1226.6-1226.44" - wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1225.5-1225.43" - wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1210.6-1210.44" - wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1211.12-1211.51" - wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1209.6-1209.36" - wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1213.5-1213.42" - wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1214.5-1214.44" - wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1215.5-1215.45" - wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1216.11-1216.51" - wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1217.5-1217.46" - wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1212.6-1212.37" - wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1220.5-1220.32" - wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1221.5-1221.31" - wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1222.11-1222.45" - wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1219.5-1219.32" - wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1218.5-1218.32" - wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1236.5-1236.27" - wire \main_sdphy_dataw_start - attribute \src "ls180.v:1223.5-1223.26" - wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1237.5-1237.27" - wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1117.11-1117.32" - wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1791.11-1791.59" - wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1792.5-1792.56" - wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1105.6-1105.34" - wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1104.6-1104.35" - wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1107.5-1107.33" - wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1106.6-1106.35" - wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1109.6-1109.43" - wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1110.12-1110.50" - wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1108.6-1108.35" - wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1112.5-1112.41" - wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1113.5-1113.43" - wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1114.5-1114.44" - wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1115.11-1115.50" - wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1116.5-1116.45" - wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1111.6-1111.36" - wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1365.6-1365.27" - wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1366.5-1366.28" - wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1367.6-1367.29" - wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1368.6-1368.30" - wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1369.11-1369.35" - wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1370.12-1370.36" - wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1371.6-1371.31" - wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1094.6-1094.23" - wire \main_sdphy_status - attribute \src "ls180.v:1095.6-1095.19" - wire \main_sdphy_we - attribute \src "ls180.v:329.5-329.26" - wire \main_sdram_address_re - attribute \src "ls180.v:328.12-328.38" - wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:331.5-331.27" - wire \main_sdram_baddress_re - attribute \src "ls180.v:330.11-330.38" - wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:427.5-427.43" - wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:449.11-449.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:454.6-454.58" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:459.6-459.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:460.6-460.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:458.13-458.78" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:457.6-457.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:463.6-463.65" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:464.6-464.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:462.13-462.79" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:461.6-461.70" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:446.11-446.61" - wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:448.11-448.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:455.12-455.67" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:456.13-456.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:447.5-447.57" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:430.5-430.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:431.5-431.59" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:433.13-433.75" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:432.6-432.66" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:429.6-429.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:428.6-428.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:436.6-436.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:437.6-437.62" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:439.13-439.77" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:438.6-438.68" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:435.6-435.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:434.6-434.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:444.13-444.71" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:445.13-445.72" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:442.6-442.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:443.6-443.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:440.6-440.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:441.6-441.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:450.11-450.66" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:451.13-451.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:453.13-453.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:452.6-452.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:467.6-467.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:468.6-468.50" - wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:470.13-470.65" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:469.6-469.56" - wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:466.6-466.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:465.6-465.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:473.5-473.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:474.5-474.51" - wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:476.12-476.66" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:475.5-475.57" - wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:472.6-472.53" - wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:471.5-471.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:419.12-419.49" - wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:420.12-420.50" - wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:421.5-421.44" - wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:424.5-424.47" - wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:425.5-425.48" - wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:426.5-426.49" - wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:422.5-422.44" - wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:423.5-423.43" - wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:418.5-418.38" - wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:417.5-417.38" - wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:416.5-416.40" - wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:415.6-415.41" - wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:411.13-411.45" - wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:412.6-412.38" - wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:414.5-414.44" - wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:409.6-409.39" - wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:408.6-408.39" - wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:413.5-413.44" - wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:410.6-410.36" - wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:477.12-477.39" - wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:481.5-481.38" - wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:482.5-482.47" - wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:479.6-479.37" - wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:480.5-480.37" - wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:478.5-478.39" - wire \main_sdram_bankmachine0_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:489.32-489.69" - wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:488.6-488.43" - wire \main_sdram_bankmachine0_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:487.32-487.68" - wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:486.6-486.42" - wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:485.11-485.48" - wire width 3 \main_sdram_bankmachine0_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:484.32-484.69" - wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:483.6-483.43" - wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:509.5-509.43" - wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:531.11-531.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:536.6-536.58" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:541.6-541.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:542.6-542.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:540.13-540.78" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:539.6-539.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:545.6-545.65" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:546.6-546.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:544.13-544.79" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:543.6-543.70" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:528.11-528.61" - wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:530.11-530.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:537.12-537.67" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:538.13-538.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:529.5-529.57" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:512.5-512.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:513.5-513.59" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:515.13-515.75" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:514.6-514.66" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:511.6-511.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:510.6-510.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:518.6-518.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:519.6-519.62" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:521.13-521.77" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:520.6-520.68" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:517.6-517.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:516.6-516.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:526.13-526.71" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:527.13-527.72" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:524.6-524.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:525.6-525.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:522.6-522.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:523.6-523.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:532.11-532.66" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:533.13-533.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:535.13-535.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:534.6-534.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:549.6-549.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:550.6-550.50" - wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:552.13-552.65" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:551.6-551.56" - wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:548.6-548.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:547.6-547.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:555.5-555.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:556.5-556.51" - wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:558.12-558.66" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:557.5-557.57" - wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:554.6-554.53" - wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:553.5-553.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:501.12-501.49" - wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:502.12-502.50" - wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:503.5-503.44" - wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:506.5-506.47" - wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:507.5-507.48" - wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:508.5-508.49" - wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:504.5-504.44" - wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:505.5-505.43" - wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:500.5-500.38" - wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:499.5-499.38" - wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:498.5-498.40" - wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:497.6-497.41" - wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:493.13-493.45" - wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:494.6-494.38" - wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:496.5-496.44" - wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:491.6-491.39" - wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:490.6-490.39" - wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:495.5-495.44" - wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:492.6-492.36" - wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:559.12-559.39" - wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:563.5-563.38" - wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:564.5-564.47" - wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:561.6-561.37" - wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:562.5-562.37" - wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:560.5-560.39" - wire \main_sdram_bankmachine1_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:571.32-571.69" - wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:570.6-570.43" - wire \main_sdram_bankmachine1_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:569.32-569.68" - wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:568.6-568.42" - wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:567.11-567.48" - wire width 3 \main_sdram_bankmachine1_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:566.32-566.69" - wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:565.6-565.43" - wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:591.5-591.43" - wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:613.11-613.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:618.6-618.58" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:623.6-623.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:624.6-624.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:622.13-622.78" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:621.6-621.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:627.6-627.65" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:628.6-628.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:626.13-626.79" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:625.6-625.70" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:610.11-610.61" - wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:612.11-612.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:619.12-619.67" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:620.13-620.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:611.5-611.57" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:594.5-594.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:595.5-595.59" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:597.13-597.75" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:596.6-596.66" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:593.6-593.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:592.6-592.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:600.6-600.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:601.6-601.62" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:603.13-603.77" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:602.6-602.68" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:599.6-599.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:598.6-598.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:608.13-608.71" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:609.13-609.72" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:606.6-606.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:607.6-607.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:604.6-604.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:605.6-605.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:614.11-614.66" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:615.13-615.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:617.13-617.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:616.6-616.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:631.6-631.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:632.6-632.50" - wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:634.13-634.65" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:633.6-633.56" - wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:630.6-630.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:629.6-629.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:637.5-637.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:638.5-638.51" - wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:640.12-640.66" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:639.5-639.57" - wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:636.6-636.53" - wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:635.5-635.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:583.12-583.49" - wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:584.12-584.50" - wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:585.5-585.44" - wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:588.5-588.47" - wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:589.5-589.48" - wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:590.5-590.49" - wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:586.5-586.44" - wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:587.5-587.43" - wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:582.5-582.38" - wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:581.5-581.38" - wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:580.5-580.40" - wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:579.6-579.41" - wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:575.13-575.45" - wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:576.6-576.38" - wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:578.5-578.44" - wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:573.6-573.39" - wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:572.6-572.39" - wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:577.5-577.44" - wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:574.6-574.36" - wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:641.12-641.39" - wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:645.5-645.38" - wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:646.5-646.47" - wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:643.6-643.37" - wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:644.5-644.37" - wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:642.5-642.39" - wire \main_sdram_bankmachine2_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:653.32-653.69" - wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:652.6-652.43" - wire \main_sdram_bankmachine2_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:651.32-651.68" - wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:650.6-650.42" - wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:649.11-649.48" - wire width 3 \main_sdram_bankmachine2_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:648.32-648.69" - wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:647.6-647.43" - wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:673.5-673.43" - wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:695.11-695.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:700.6-700.58" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:705.6-705.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:706.6-706.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:704.13-704.78" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:703.6-703.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:709.6-709.65" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:710.6-710.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:708.13-708.79" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:707.6-707.70" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:692.11-692.61" - wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:694.11-694.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:701.12-701.67" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:702.13-702.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:693.5-693.57" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:676.5-676.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:677.5-677.59" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:679.13-679.75" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:678.6-678.66" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:675.6-675.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:674.6-674.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:682.6-682.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:683.6-683.62" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:685.13-685.77" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:684.6-684.68" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:681.6-681.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:680.6-680.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:690.13-690.71" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:691.13-691.72" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:688.6-688.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:689.6-689.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:686.6-686.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:687.6-687.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:696.11-696.66" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:697.13-697.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:699.13-699.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:698.6-698.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:713.6-713.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:714.6-714.50" - wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:716.13-716.65" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:715.6-715.56" - wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:712.6-712.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:711.6-711.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:719.5-719.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:720.5-720.51" - wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:722.12-722.66" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:721.5-721.57" - wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:718.6-718.53" - wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:717.5-717.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:665.12-665.49" - wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:666.12-666.50" - wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:667.5-667.44" - wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:670.5-670.47" - wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:671.5-671.48" - wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:672.5-672.49" - wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:668.5-668.44" - wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:669.5-669.43" - wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:664.5-664.38" - wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:663.5-663.38" - wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:662.5-662.40" - wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:661.6-661.41" - wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:657.13-657.45" - wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:658.6-658.38" - wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:660.5-660.44" - wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:655.6-655.39" - wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:654.6-654.39" - wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:659.5-659.44" - wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:656.6-656.36" - wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:723.12-723.39" - wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:727.5-727.38" - wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:728.5-728.47" - wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:725.6-725.37" - wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:726.5-726.37" - wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:724.5-724.39" - wire \main_sdram_bankmachine3_row_opened - attribute \no_retiming "true" - attribute \src "ls180.v:735.32-735.69" - wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:734.6-734.43" - wire \main_sdram_bankmachine3_trascon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:733.32-733.68" - wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:732.6-732.42" - wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:731.11-731.48" - wire width 3 \main_sdram_bankmachine3_twtpcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:730.32-730.69" - wire \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:729.6-729.43" - wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:737.6-737.28" - wire \main_sdram_cas_allowed - attribute \src "ls180.v:755.6-755.30" - wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:744.13-744.48" - wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:745.12-745.48" - wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:746.5-746.42" - wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:749.6-749.46" - wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:750.6-750.47" - wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:751.6-751.48" - wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:747.5-747.42" - wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:748.5-748.41" - wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:743.5-743.36" - wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:742.6-742.37" - wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:754.11-754.38" - wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:753.12-753.41" - wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:752.11-752.39" - wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:741.5-741.41" - wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:740.5-740.36" - wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:738.5-738.37" - wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:739.5-739.38" - wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:773.6-773.30" - wire \main_sdram_choose_req_ce - attribute \src "ls180.v:762.13-762.48" - wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:763.12-763.48" - wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:764.5-764.42" - wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:767.6-767.46" - wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:768.6-768.47" - wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:769.6-769.48" - wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:765.5-765.42" - wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:766.5-766.41" - wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:761.5-761.36" - wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:760.6-760.37" - wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:772.11-772.38" - wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:771.12-771.41" - wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:770.11-770.39" - wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:759.5-759.41" - wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:758.6-758.37" - wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:756.5-756.37" - wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:757.5-757.38" - wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:317.6-317.20" - wire \main_sdram_cke - attribute \src "ls180.v:385.5-385.24" - wire \main_sdram_cmd_last - attribute \src "ls180.v:386.12-386.36" - wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:387.11-387.36" - wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:388.5-388.31" - wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:391.5-391.35" - wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:392.5-392.36" - wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:389.5-389.31" - wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:390.5-390.30" - wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:384.5-384.25" - wire \main_sdram_cmd_ready - attribute \src "ls180.v:383.5-383.25" - wire \main_sdram_cmd_valid - attribute \src "ls180.v:325.6-325.32" - wire \main_sdram_command_issue_r - attribute \src "ls180.v:324.6-324.33" - wire \main_sdram_command_issue_re - attribute \src "ls180.v:327.5-327.31" - wire \main_sdram_command_issue_w - attribute \src "ls180.v:326.6-326.33" - wire \main_sdram_command_issue_we - attribute \src "ls180.v:323.5-323.26" - wire \main_sdram_command_re - attribute \src "ls180.v:322.11-322.37" - wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:376.5-376.28" - wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:367.12-367.37" - wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:368.11-368.33" - wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:369.5-369.28" - wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:373.6-373.27" - wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:370.5-370.27" - wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:374.6-374.27" - wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:371.5-371.28" - wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:381.13-381.37" - wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:380.5-380.32" - wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:382.6-382.36" - wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:375.6-375.31" - wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:372.5-372.27" - wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:377.13-377.37" - wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:378.5-378.32" - wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:379.12-379.41" - wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:791.5-791.19" - wire \main_sdram_en0 - attribute \src "ls180.v:794.5-794.19" - wire \main_sdram_en1 - attribute \src "ls180.v:797.6-797.30" - wire \main_sdram_go_to_refresh - attribute \src "ls180.v:339.13-339.44" - wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:340.6-340.37" - wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:342.6-342.44" - wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:337.6-337.38" - wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:336.6-336.38" - wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:341.6-341.44" - wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:338.6-338.35" - wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:346.13-346.44" - wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:347.6-347.37" - wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:349.6-349.44" - wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:344.6-344.38" - wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:343.6-343.38" - wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:348.6-348.44" - wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:345.6-345.35" - wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:353.13-353.44" - wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:354.6-354.37" - wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:356.6-356.44" - wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:351.6-351.38" - wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:350.6-350.38" - wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:355.6-355.44" - wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:352.6-352.35" - wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:360.13-360.44" - wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:361.6-361.37" - wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:363.6-363.44" - wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:358.6-358.38" - wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:357.6-357.38" - wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:362.6-362.44" - wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:359.6-359.35" - wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:366.13-366.39" - wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:364.12-364.38" - wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:365.11-365.40" - wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:277.5-277.29" - wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:268.13-268.39" - wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:269.12-269.35" - wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:270.5-270.29" - wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:274.6-274.28" - wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:271.5-271.28" - wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:275.6-275.28" - wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:272.5-272.29" - wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:282.12-282.37" - wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:281.6-281.34" - wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:283.5-283.36" - wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:276.6-276.32" - wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:273.5-273.28" - wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:278.13-278.38" - wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:279.6-279.34" - wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:280.12-280.42" - wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:309.5-309.31" - wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:300.12-300.40" - wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:301.11-301.36" - wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:302.5-302.31" - wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:306.5-306.29" - wire \main_sdram_master_p0_cke - attribute \src "ls180.v:303.5-303.30" - wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:307.5-307.29" - wire \main_sdram_master_p0_odt - attribute \src "ls180.v:304.5-304.31" - wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:314.13-314.40" - wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:313.5-313.35" - wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:315.6-315.39" - wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:308.5-308.33" - wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:305.5-305.30" - wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:310.12-310.39" - wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:311.5-311.35" - wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:312.11-312.43" - wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:792.6-792.26" - wire \main_sdram_max_time0 - attribute \src "ls180.v:795.6-795.26" - wire \main_sdram_max_time1 - attribute \src "ls180.v:774.12-774.28" - wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:775.11-775.28" - wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:318.6-318.20" - wire \main_sdram_odt - attribute \src "ls180.v:401.5-401.31" - wire \main_sdram_postponer_count - attribute \src "ls180.v:399.6-399.32" - wire \main_sdram_postponer_req_i - attribute \src "ls180.v:400.5-400.31" - wire \main_sdram_postponer_req_o - attribute \src "ls180.v:736.6-736.28" - wire \main_sdram_ras_allowed - attribute \src "ls180.v:321.5-321.18" - wire \main_sdram_re - attribute \src "ls180.v:789.6-789.31" - wire \main_sdram_read_available - attribute \src "ls180.v:319.6-319.24" - wire \main_sdram_reset_n - attribute \src "ls180.v:316.6-316.20" - wire \main_sdram_sel - attribute \src "ls180.v:407.5-407.31" - wire \main_sdram_sequencer_count - attribute \src "ls180.v:406.11-406.39" - wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:403.6-403.32" - wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:405.5-405.31" - wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:402.5-402.32" - wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:404.6-404.33" - wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:293.6-293.31" - wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:284.13-284.40" - wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:285.12-285.36" - wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:286.6-286.31" - wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:290.6-290.29" - wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:287.6-287.30" - wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:291.6-291.29" - wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:288.6-288.31" - wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:298.12-298.38" - wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:297.6-297.35" - wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:299.5-299.37" - wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:292.6-292.33" - wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:289.6-289.30" - wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:294.13-294.39" - wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:295.6-295.35" - wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:296.12-296.43" - wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:334.12-334.29" - wire width 16 \main_sdram_status - attribute \src "ls180.v:777.5-777.24" - wire \main_sdram_steerer0 - attribute \src "ls180.v:778.5-778.24" - wire \main_sdram_steerer1 - attribute \src "ls180.v:776.11-776.33" - wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:320.11-320.29" - wire width 4 \main_sdram_storage - attribute \src "ls180.v:785.5-785.29" - wire \main_sdram_tccdcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:784.32-784.56" - wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:783.6-783.30" - wire \main_sdram_tccdcon_valid - attribute \no_retiming "true" - attribute \src "ls180.v:782.32-782.56" - wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:781.6-781.30" - wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:793.11-793.27" - wire width 5 \main_sdram_time0 - attribute \src "ls180.v:796.11-796.27" - wire width 4 \main_sdram_time1 - attribute \src "ls180.v:396.12-396.35" - wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:398.11-398.34" - wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:395.6-395.28" - wire \main_sdram_timer_done0 - attribute \src "ls180.v:397.6-397.28" - wire \main_sdram_timer_done1 - attribute \src "ls180.v:394.6-394.27" - wire \main_sdram_timer_wait - attribute \no_retiming "true" - attribute \src "ls180.v:780.32-780.56" - wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:779.6-779.30" - wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:788.11-788.35" - wire width 3 \main_sdram_twtrcon_count - attribute \no_retiming "true" - attribute \src "ls180.v:787.32-787.56" - wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:786.6-786.30" - wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:393.6-393.30" - wire \main_sdram_wants_refresh - attribute \src "ls180.v:335.6-335.19" - wire \main_sdram_we - attribute \src "ls180.v:333.5-333.25" - wire \main_sdram_wrdata_re - attribute \src "ls180.v:332.12-332.37" - wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:790.6-790.32" - wire \main_sdram_write_available - attribute \src "ls180.v:990.6-990.27" - wire \main_spimaster0_start - attribute \src "ls180.v:1000.12-1000.35" - wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1001.12-1001.36" - wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1002.5-1002.24" - wire \main_spimaster12_re - attribute \src "ls180.v:1003.6-1003.27" - wire \main_spimaster13_done - attribute \src "ls180.v:1004.6-1004.29" - wire \main_spimaster14_status - attribute \src "ls180.v:1005.6-1005.25" - wire \main_spimaster15_we - attribute \src "ls180.v:1006.11-1006.35" - wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1007.5-1007.24" - wire \main_spimaster17_re - attribute \src "ls180.v:1008.12-1008.35" - wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1009.6-1009.25" - wire \main_spimaster19_we - attribute \src "ls180.v:991.12-991.34" - wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1063.5-1063.23" - wire \main_spimaster1_re - attribute \src "ls180.v:1062.12-1062.35" - wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1010.6-1010.26" - wire \main_spimaster20_sel - attribute \src "ls180.v:1011.5-1011.29" - wire \main_spimaster21_storage - attribute \src "ls180.v:1012.5-1012.24" - wire \main_spimaster22_re - attribute \src "ls180.v:1013.5-1013.29" - wire \main_spimaster23_storage - attribute \src "ls180.v:1014.5-1014.24" - wire \main_spimaster24_re - attribute \src "ls180.v:1015.5-1015.32" - wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1016.5-1016.31" - wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1017.11-1017.33" - wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1783.11-1783.55" - wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1784.5-1784.52" - wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1018.5-1018.32" - wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1019.5-1019.32" - wire \main_spimaster29_miso_latch - attribute \src "ls180.v:992.5-992.25" - wire \main_spimaster2_done - attribute \src "ls180.v:1020.12-1020.40" - wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1021.6-1021.31" - wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1022.6-1022.31" - wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1023.11-1023.37" - wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1024.11-1024.36" - wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1025.11-1025.37" - wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:993.5-993.24" - wire \main_spimaster3_irq - attribute \src "ls180.v:994.12-994.32" - wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:995.11-995.31" - wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:996.6-996.24" - wire \main_spimaster6_cs - attribute \src "ls180.v:997.6-997.30" - wire \main_spimaster7_loopback - attribute \src "ls180.v:998.12-998.39" - wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:999.5-999.26" - wire \main_spimaster9_start - attribute \src "ls180.v:1034.13-1034.40" - wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1056.12-1056.39" - wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1051.5-1051.30" - wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1058.6-1058.29" - wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1057.6-1057.29" - wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1038.5-1038.30" - wire \main_spisdcard_control_re - attribute \src "ls180.v:1037.12-1037.42" - wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1053.11-1053.31" - wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1787.11-1787.53" - wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1788.5-1788.50" - wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1032.6-1032.23" - wire \main_spisdcard_cs - attribute \src "ls180.v:1052.5-1052.29" - wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1048.5-1048.25" - wire \main_spisdcard_cs_re - attribute \src "ls180.v:1047.5-1047.30" - wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1028.5-1028.25" - wire \main_spisdcard_done0 - attribute \src "ls180.v:1039.6-1039.26" - wire \main_spisdcard_done1 - attribute \src "ls180.v:1029.5-1029.23" - wire \main_spisdcard_irq - attribute \src "ls180.v:1027.12-1027.34" - wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1036.12-1036.34" - wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1033.6-1033.29" - wire \main_spisdcard_loopback - attribute \src "ls180.v:1050.5-1050.31" - wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1049.5-1049.36" - wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1031.11-1031.30" - wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1061.11-1061.35" - wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1055.5-1055.30" - wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1044.12-1044.38" - wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1045.6-1045.28" - wire \main_spisdcard_miso_we - attribute \src "ls180.v:1030.12-1030.31" - wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1059.11-1059.35" - wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1054.5-1054.30" - wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1043.5-1043.27" - wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1060.11-1060.34" - wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1042.11-1042.38" - wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1046.6-1046.24" - wire \main_spisdcard_sel - attribute \src "ls180.v:1026.6-1026.27" - wire \main_spisdcard_start0 - attribute \src "ls180.v:1035.5-1035.26" - wire \main_spisdcard_start1 - attribute \src "ls180.v:1040.6-1040.34" - wire \main_spisdcard_status_status - attribute \src "ls180.v:1041.6-1041.30" - wire \main_spisdcard_status_we - attribute \src "ls180.v:887.12-887.44" - wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:886.6-886.39" - wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:889.11-889.43" - wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:888.6-888.39" - wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:891.5-891.30" - wire \main_uart_eventmanager_re - attribute \src "ls180.v:883.12-883.43" - wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:882.6-882.38" - wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:885.11-885.42" - wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:884.6-884.38" - wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:890.11-890.41" - wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:871.6-871.19" - wire \main_uart_irq - attribute \src "ls180.v:857.12-857.46" - wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:847.12-847.46" - wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:840.5-840.21" - wire \main_uart_phy_re - attribute \src "ls180.v:858.6-858.22" - wire \main_uart_phy_rx - attribute \src "ls180.v:861.11-861.36" - wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:862.5-862.26" - wire \main_uart_phy_rx_busy - attribute \src "ls180.v:859.5-859.23" - wire \main_uart_phy_rx_r - attribute \src "ls180.v:860.11-860.31" - wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:843.6-843.30" - wire \main_uart_phy_sink_first - attribute \src "ls180.v:844.6-844.29" - wire \main_uart_phy_sink_last - attribute \src "ls180.v:845.12-845.43" - wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:842.5-842.29" - wire \main_uart_phy_sink_ready - attribute \src "ls180.v:841.6-841.30" - wire \main_uart_phy_sink_valid - attribute \src "ls180.v:853.5-853.31" - wire \main_uart_phy_source_first - attribute \src "ls180.v:854.5-854.30" - wire \main_uart_phy_source_last - attribute \src "ls180.v:855.11-855.44" - wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:852.6-852.32" - wire \main_uart_phy_source_ready - attribute \src "ls180.v:851.5-851.31" - wire \main_uart_phy_source_valid - attribute \src "ls180.v:839.12-839.33" - wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:849.11-849.36" - wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:850.5-850.26" - wire \main_uart_phy_tx_busy - attribute \src "ls180.v:848.11-848.31" - wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:856.5-856.32" - wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:846.5-846.32" - wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:980.5-980.20" - wire \main_uart_reset - attribute \src "ls180.v:880.5-880.23" - wire \main_uart_rx_clear - attribute \src "ls180.v:964.11-964.36" - wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:969.6-969.31" - wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:975.6-975.37" - wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:976.6-976.36" - wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:974.12-974.50" - wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:978.6-978.38" - wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:979.6-979.37" - wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:977.12-977.51" - wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:961.11-961.35" - wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:973.12-973.36" - wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:963.11-963.36" - wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:970.12-970.40" - wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:971.12-971.42" - wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:972.6-972.33" - wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:953.6-953.26" - wire \main_uart_rx_fifo_re - attribute \src "ls180.v:954.5-954.31" - wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:962.5-962.30" - wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:945.6-945.34" - wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:946.6-946.33" - wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:947.12-947.47" - wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:944.6-944.34" - wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:943.6-943.34" - wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:950.6-950.36" - wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:951.6-951.35" - wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:952.12-952.49" - wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:949.6-949.36" - wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:948.6-948.36" - wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:959.12-959.42" - wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:960.12-960.43" - wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:957.6-957.35" - wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:958.6-958.41" - wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:955.6-955.35" - wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:956.6-956.41" - wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:965.11-965.39" - wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:966.12-966.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:968.12-968.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:967.6-967.33" - wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:881.5-881.29" - wire \main_uart_rx_old_trigger - attribute \src "ls180.v:878.5-878.25" - wire \main_uart_rx_pending - attribute \src "ls180.v:877.6-877.25" - wire \main_uart_rx_status - attribute \src "ls180.v:879.6-879.26" - wire \main_uart_rx_trigger - attribute \src "ls180.v:869.6-869.30" - wire \main_uart_rxempty_status - attribute \src "ls180.v:870.6-870.26" - wire \main_uart_rxempty_we - attribute \src "ls180.v:894.6-894.29" - wire \main_uart_rxfull_status - attribute \src "ls180.v:895.6-895.25" - wire \main_uart_rxfull_we - attribute \src "ls180.v:864.12-864.28" - wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:863.6-863.23" - wire \main_uart_rxtx_re - attribute \src "ls180.v:866.12-866.28" - wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:865.6-865.23" - wire \main_uart_rxtx_we - attribute \src "ls180.v:875.5-875.23" - wire \main_uart_tx_clear - attribute \src "ls180.v:927.11-927.36" - wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:932.6-932.31" - wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:938.6-938.37" - wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:939.6-939.36" - wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:937.12-937.50" - wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:941.6-941.38" - wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:942.6-942.37" - wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:940.12-940.51" - wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:924.11-924.35" - wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:936.12-936.36" - wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:926.11-926.36" - wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:933.12-933.40" - wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:934.12-934.42" - wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:935.6-935.33" - wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:916.6-916.26" - wire \main_uart_tx_fifo_re - attribute \src "ls180.v:917.5-917.31" - wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:925.5-925.30" - wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:908.5-908.33" - wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:909.5-909.32" - wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:910.12-910.47" - wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:907.6-907.34" - wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:906.6-906.34" - wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:913.6-913.36" - wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:914.6-914.35" - wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:915.12-915.49" - wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:912.6-912.36" - wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:911.6-911.36" - wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:922.12-922.42" - wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:923.12-923.43" - wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:920.6-920.35" - wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:921.6-921.41" - wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:918.6-918.35" - wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:919.6-919.41" - wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:928.11-928.39" - wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:929.12-929.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:931.12-931.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:930.6-930.33" - wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:876.5-876.29" - wire \main_uart_tx_old_trigger - attribute \src "ls180.v:873.5-873.25" - wire \main_uart_tx_pending - attribute \src "ls180.v:872.6-872.25" - wire \main_uart_tx_status - attribute \src "ls180.v:874.6-874.26" - wire \main_uart_tx_trigger - attribute \src "ls180.v:892.6-892.30" - wire \main_uart_txempty_status - attribute \src "ls180.v:893.6-893.26" - wire \main_uart_txempty_we - attribute \src "ls180.v:867.6-867.29" - wire \main_uart_txfull_status - attribute \src "ls180.v:868.6-868.25" - wire \main_uart_txfull_we - attribute \src "ls180.v:898.6-898.31" - wire \main_uart_uart_sink_first - attribute \src "ls180.v:899.6-899.30" - wire \main_uart_uart_sink_last - attribute \src "ls180.v:900.12-900.44" - wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:897.6-897.31" - wire \main_uart_uart_sink_ready - attribute \src "ls180.v:896.6-896.31" - wire \main_uart_uart_sink_valid - attribute \src "ls180.v:903.6-903.33" - wire \main_uart_uart_source_first - attribute \src "ls180.v:904.6-904.32" - wire \main_uart_uart_source_last - attribute \src "ls180.v:905.12-905.46" - wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:902.6-902.33" - wire \main_uart_uart_source_ready - attribute \src "ls180.v:901.6-901.33" - wire \main_uart_uart_source_valid - attribute \src "ls180.v:817.5-817.22" - wire \main_wb_sdram_ack - attribute \src "ls180.v:811.13-811.30" - wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:820.12-820.29" - wire width 2 \main_wb_sdram_bte - attribute \src "ls180.v:819.12-819.29" - wire width 3 \main_wb_sdram_cti - attribute \src "ls180.v:815.6-815.23" - wire \main_wb_sdram_cyc - attribute \src "ls180.v:813.13-813.32" - wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:812.13-812.32" - wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:821.5-821.22" - wire \main_wb_sdram_err - attribute \src "ls180.v:814.12-814.29" - wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:816.6-816.23" - wire \main_wb_sdram_stb - attribute \src "ls180.v:818.6-818.22" - wire \main_wb_sdram_we - attribute \src "ls180.v:835.5-835.24" - wire \main_wdata_consumed - attribute \src "ls180.v:10055.11-10055.17" - wire width 7 \memadr - attribute \src "ls180.v:10075.12-10075.18" - wire width 25 \memdat - attribute \src "ls180.v:10089.12-10089.20" - wire width 25 \memdat_1 - attribute \src "ls180.v:10103.12-10103.20" - wire width 25 \memdat_2 - attribute \src "ls180.v:10117.12-10117.20" - wire width 25 \memdat_3 - attribute \src "ls180.v:10131.11-10131.19" - wire width 10 \memdat_4 - attribute \src "ls180.v:10132.11-10132.19" - wire width 10 \memdat_5 - attribute \src "ls180.v:10148.11-10148.19" - wire width 10 \memdat_6 - attribute \src "ls180.v:10149.11-10149.19" - wire width 10 \memdat_7 - attribute \src "ls180.v:10165.11-10165.19" - wire width 10 \memdat_8 - attribute \src "ls180.v:10179.11-10179.19" - wire width 10 \memdat_9 - attribute \src "ls180.v:51.20-51.22" - wire width 36 input 47 \nc - attribute \src "ls180.v:249.6-249.13" - wire \por_clk - attribute \src "ls180.v:38.19-38.22" - wire width 2 output 34 \pwm - attribute \src "ls180.v:155.12-155.17" - wire width 2 \pwm_1 - attribute \src "ls180.v:10.13-10.23" - wire output 6 \sdcard_clk - attribute \src "ls180.v:11.14-11.26" - wire output 7 \sdcard_cmd_i - attribute \src "ls180.v:12.13-12.25" - wire output 8 \sdcard_cmd_o - attribute \src "ls180.v:13.13-13.26" - wire output 9 \sdcard_cmd_oe - attribute \src "ls180.v:14.19-14.32" - wire width 4 input 10 \sdcard_data_i - attribute \src "ls180.v:15.19-15.32" - wire width 4 output 11 \sdcard_data_o - attribute \src "ls180.v:16.13-16.27" - wire output 12 \sdcard_data_oe - attribute \src "ls180.v:25.20-25.27" - wire width 13 output 21 \sdram_a - attribute \src "ls180.v:34.19-34.27" - wire width 2 output 30 \sdram_ba - attribute \src "ls180.v:31.13-31.24" - wire output 27 \sdram_cas_n - attribute \src "ls180.v:33.13-33.22" - wire output 29 \sdram_cke - attribute \src "ls180.v:36.13-36.24" - wire output 32 \sdram_clock - attribute \src "ls180.v:153.6-153.19" - wire \sdram_clock_1 - attribute \src "ls180.v:32.13-32.23" - wire output 28 \sdram_cs_n - attribute \src "ls180.v:35.19-35.27" - wire width 2 output 31 \sdram_dm - attribute \src "ls180.v:26.21-26.31" - wire width 16 output 22 \sdram_dq_i - attribute \src "ls180.v:27.20-27.30" - wire width 16 output 23 \sdram_dq_o - attribute \src "ls180.v:28.13-28.24" - wire output 24 \sdram_dq_oe - attribute \src "ls180.v:30.13-30.24" - wire output 26 \sdram_ras_n - attribute \src "ls180.v:29.13-29.23" - wire output 25 \sdram_we_n - attribute \src "ls180.v:2645.6-2645.15" - wire \sdrio_clk - attribute \src "ls180.v:2646.6-2646.17" - wire \sdrio_clk_1 - attribute \src "ls180.v:2655.6-2655.18" - wire \sdrio_clk_10 - attribute \src "ls180.v:2656.6-2656.18" - wire \sdrio_clk_11 - attribute \src "ls180.v:2657.6-2657.18" - wire \sdrio_clk_12 - attribute \src "ls180.v:2658.6-2658.18" - wire \sdrio_clk_13 - attribute \src "ls180.v:2659.6-2659.18" - wire \sdrio_clk_14 - attribute \src "ls180.v:2660.6-2660.18" - wire \sdrio_clk_15 - attribute \src "ls180.v:2661.6-2661.18" - wire \sdrio_clk_16 - attribute \src "ls180.v:2662.6-2662.18" - wire \sdrio_clk_17 - attribute \src "ls180.v:2663.6-2663.18" - wire \sdrio_clk_18 - attribute \src "ls180.v:2664.6-2664.18" - wire \sdrio_clk_19 - attribute \src "ls180.v:2647.6-2647.17" - wire \sdrio_clk_2 - attribute \src "ls180.v:2665.6-2665.18" - wire \sdrio_clk_20 - attribute \src "ls180.v:2666.6-2666.18" - wire \sdrio_clk_21 - attribute \src "ls180.v:2667.6-2667.18" - wire \sdrio_clk_22 - attribute \src "ls180.v:2668.6-2668.18" - wire \sdrio_clk_23 - attribute \src "ls180.v:2669.6-2669.18" - wire \sdrio_clk_24 - attribute \src "ls180.v:2670.6-2670.18" - wire \sdrio_clk_25 - attribute \src "ls180.v:2671.6-2671.18" - wire \sdrio_clk_26 - attribute \src "ls180.v:2672.6-2672.18" - wire \sdrio_clk_27 - attribute \src "ls180.v:2673.6-2673.18" - wire \sdrio_clk_28 - attribute \src "ls180.v:2674.6-2674.18" - wire \sdrio_clk_29 - attribute \src "ls180.v:2648.6-2648.17" - wire \sdrio_clk_3 - attribute \src "ls180.v:2675.6-2675.18" - wire \sdrio_clk_30 - attribute \src "ls180.v:2676.6-2676.18" - wire \sdrio_clk_31 - attribute \src "ls180.v:2677.6-2677.18" - wire \sdrio_clk_32 - attribute \src "ls180.v:2678.6-2678.18" - wire \sdrio_clk_33 - attribute \src "ls180.v:2679.6-2679.18" - wire \sdrio_clk_34 - attribute \src "ls180.v:2680.6-2680.18" - wire \sdrio_clk_35 - attribute \src "ls180.v:2681.6-2681.18" - wire \sdrio_clk_36 - attribute \src "ls180.v:2682.6-2682.18" - wire \sdrio_clk_37 - attribute \src "ls180.v:2683.6-2683.18" - wire \sdrio_clk_38 - attribute \src "ls180.v:2684.6-2684.18" - wire \sdrio_clk_39 - attribute \src "ls180.v:2649.6-2649.17" - wire \sdrio_clk_4 - attribute \src "ls180.v:2685.6-2685.18" - wire \sdrio_clk_40 - attribute \src "ls180.v:2686.6-2686.18" - wire \sdrio_clk_41 - attribute \src "ls180.v:2687.6-2687.18" - wire \sdrio_clk_42 - attribute \src "ls180.v:2688.6-2688.18" - wire \sdrio_clk_43 - attribute \src "ls180.v:2689.6-2689.18" - wire \sdrio_clk_44 - attribute \src "ls180.v:2690.6-2690.18" - wire \sdrio_clk_45 - attribute \src "ls180.v:2691.6-2691.18" - wire \sdrio_clk_46 - attribute \src "ls180.v:2692.6-2692.18" - wire \sdrio_clk_47 - attribute \src "ls180.v:2693.6-2693.18" - wire \sdrio_clk_48 - attribute \src "ls180.v:2694.6-2694.18" - wire \sdrio_clk_49 - attribute \src "ls180.v:2650.6-2650.17" - wire \sdrio_clk_5 - attribute \src "ls180.v:2695.6-2695.18" - wire \sdrio_clk_50 - attribute \src "ls180.v:2696.6-2696.18" - wire \sdrio_clk_51 - attribute \src "ls180.v:2697.6-2697.18" - wire \sdrio_clk_52 - attribute \src "ls180.v:2698.6-2698.18" - wire \sdrio_clk_53 - attribute \src "ls180.v:2699.6-2699.18" - wire \sdrio_clk_54 - attribute \src "ls180.v:2700.6-2700.18" - wire \sdrio_clk_55 - attribute \src "ls180.v:2735.6-2735.18" - wire \sdrio_clk_56 - attribute \src "ls180.v:2736.6-2736.18" - wire \sdrio_clk_57 - attribute \src "ls180.v:2737.6-2737.18" - wire \sdrio_clk_58 - attribute \src "ls180.v:2738.6-2738.18" - wire \sdrio_clk_59 - attribute \src "ls180.v:2651.6-2651.17" - wire \sdrio_clk_6 - attribute \src "ls180.v:2739.6-2739.18" - wire \sdrio_clk_60 - attribute \src "ls180.v:2740.6-2740.18" - wire \sdrio_clk_61 - attribute \src "ls180.v:2741.6-2741.18" - wire \sdrio_clk_62 - attribute \src "ls180.v:2742.6-2742.18" - wire \sdrio_clk_63 - attribute \src "ls180.v:2743.6-2743.18" - wire \sdrio_clk_64 - attribute \src "ls180.v:2744.6-2744.18" - wire \sdrio_clk_65 - attribute \src "ls180.v:2745.6-2745.18" - wire \sdrio_clk_66 - attribute \src "ls180.v:2746.6-2746.18" - wire \sdrio_clk_67 - attribute \src "ls180.v:2747.6-2747.18" - wire \sdrio_clk_68 - attribute \src "ls180.v:2652.6-2652.17" - wire \sdrio_clk_7 - attribute \src "ls180.v:2653.6-2653.17" - wire \sdrio_clk_8 - attribute \src "ls180.v:2654.6-2654.17" - wire \sdrio_clk_9 - attribute \src "ls180.v:21.13-21.26" - wire output 17 \spimaster_clk - attribute \src "ls180.v:23.13-23.27" - wire output 19 \spimaster_cs_n - attribute \src "ls180.v:24.14-24.28" - wire output 20 \spimaster_miso - attribute \src "ls180.v:22.13-22.27" - wire output 18 \spimaster_mosi - attribute \src "ls180.v:39.13-39.26" - wire output 35 \spisdcard_clk - attribute \src "ls180.v:41.13-41.27" - wire output 37 \spisdcard_cs_n - attribute \src "ls180.v:42.14-42.28" - wire output 38 \spisdcard_miso - attribute \src "ls180.v:40.13-40.27" - wire output 36 \spisdcard_mosi - attribute \src "ls180.v:43.13-43.20" - wire input 39 \sys_clk - attribute \src "ls180.v:247.6-247.15" - wire \sys_clk_1 - attribute \src "ls180.v:45.19-45.31" - wire width 3 input 41 \sys_clksel_i - attribute \src "ls180.v:46.14-46.26" - wire output 42 \sys_pll_48_o - attribute \src "ls180.v:44.13-44.20" - wire input 40 \sys_rst - attribute \src "ls180.v:248.6-248.15" - wire \sys_rst_1 - attribute \src "ls180.v:9.13-9.20" - wire input 5 \uart_rx - attribute \src "ls180.v:8.13-8.20" - wire output 4 \uart_tx - attribute \src "ls180.v:10054.12-10054.15" - memory width 32 size 128 \mem - attribute \src "ls180.v:10074.12-10074.19" - memory width 25 size 8 \storage - attribute \src "ls180.v:10088.12-10088.21" - memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10102.12-10102.21" - memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10116.12-10116.21" - memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10130.11-10130.20" - memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10147.11-10147.20" - memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10164.11-10164.20" - memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10178.11-10178.20" - memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2816.68-2816.110" - cell $add $add$ls180.v:2816$22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter - connect \B 1'1 - connect \Y $add$ls180.v:2816$22_Y - end - attribute \src "ls180.v:2876.68-2876.110" - cell $add $add$ls180.v:2876$33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter - connect \B 1'1 - connect \Y $add$ls180.v:2876$33_Y - end - attribute \src "ls180.v:2936.68-2936.110" - cell $add $add$ls180.v:2936$44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter - connect \B 1'1 - connect \Y $add$ls180.v:2936$44_Y - end - attribute \src "ls180.v:4069.54-4069.83" - cell $add $add$ls180.v:4069$537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $add$ls180.v:4069$537_Y - end - attribute \src "ls180.v:4169.36-4169.89" - cell $add $add$ls180.v:4169$583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4169$583_Y - end - attribute \src "ls180.v:4199.36-4199.89" - cell $add $add$ls180.v:4199$594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4199$594_Y - end - attribute \src "ls180.v:4254.54-4254.83" - cell $add $add$ls180.v:4254$607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster27_count - connect \B 1'1 - connect \Y $add$ls180.v:4254$607_Y - end - attribute \src "ls180.v:4313.52-4313.79" - cell $add $add$ls180.v:4313$615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_count - connect \B 1'1 - connect \Y $add$ls180.v:4313$615_Y - end - attribute \src "ls180.v:4417.58-4417.86" - cell $add $add$ls180.v:4417$643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_init_count - connect \B 1'1 - connect \Y $add$ls180.v:4417$643_Y - end - attribute \src "ls180.v:4474.58-4474.86" - cell $add $add$ls180.v:4474$646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4474$646_Y - end - attribute \src "ls180.v:4491.58-4491.86" - cell $add $add$ls180.v:4491$648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4491$648_Y - end - attribute \src "ls180.v:4584.59-4584.87" - cell $add $add$ls180.v:4584$665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4584$665_Y - end - attribute \src "ls180.v:4609.59-4609.87" - cell $add $add$ls180.v:4609$668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4609$668_Y - end - attribute \src "ls180.v:4731.53-4731.82" - cell $add $add$ls180.v:4731$685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $add$ls180.v:4731$685_Y - end - attribute \src "ls180.v:4842.65-4842.114" - cell $add $add$ls180.v:4842$699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_sink_payload_block_length - connect \B 4'1000 - connect \Y $add$ls180.v:4842$699_Y - end - attribute \src "ls180.v:4847.62-4847.91" - cell $add $add$ls180.v:4847$702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4847$702_Y - end - attribute \src "ls180.v:4873.61-4873.90" - cell $add $add$ls180.v:4873$705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4873$705_Y - end - attribute \src "ls180.v:5077.80-5077.117" - cell $add $add$ls180.v:5077$890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 1'1 - connect \Y $add$ls180.v:5077$890_Y - end - attribute \src "ls180.v:5271.54-5271.82" - cell $add $add$ls180.v:5271$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_cmd_count - connect \B 1'1 - connect \Y $add$ls180.v:5271$965_Y - end - attribute \src "ls180.v:5323.55-5323.84" - cell $add $add$ls180.v:5323$975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5323$975_Y - end - attribute \src "ls180.v:5349.57-5349.86" - cell $add $add$ls180.v:5349$983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5349$983_Y - end - attribute \src "ls180.v:5470.51-5470.134" - cell $add $add$ls180.v:5470$999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_base - connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5470$999_Y - end - attribute \src "ls180.v:5473.77-5473.125" - cell $add $add$ls180.v:5473$1001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B 1'1 - connect \Y $add$ls180.v:5473$1001_Y - end - attribute \src "ls180.v:5566.50-5566.105" - cell $add $add$ls180.v:5566$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_base - connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5566$1010_Y - end - attribute \src "ls180.v:5568.77-5568.111" - cell $add $add$ls180.v:5568$1011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_offset - connect \B 1'1 - connect \Y $add$ls180.v:5568$1011_Y - end - attribute \src "ls180.v:7500.36-7500.70" - cell $add $add$ls180.v:7500$2415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_bus_errors - connect \B 1'1 - connect \Y $add$ls180.v:7500$2415_Y - end - attribute \src "ls180.v:7585.37-7585.72" - cell $add $add$ls180.v:7585$2436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_sequencer_counter - connect \B 1'1 - connect \Y $add$ls180.v:7585$2436_Y - end - attribute \src "ls180.v:7602.60-7602.119" - cell $add $add$ls180.v:7602$2440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7602$2440_Y - end - attribute \src "ls180.v:7605.60-7605.119" - cell $add $add$ls180.v:7605$2441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7605$2441_Y - end - attribute \src "ls180.v:7609.59-7609.116" - cell $add $add$ls180.v:7609$2446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7609$2446_Y - end - attribute \src "ls180.v:7648.60-7648.119" - cell $add $add$ls180.v:7648$2456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7648$2456_Y - end - attribute \src "ls180.v:7651.60-7651.119" - cell $add $add$ls180.v:7651$2457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7651$2457_Y - end - attribute \src "ls180.v:7655.59-7655.116" - cell $add $add$ls180.v:7655$2462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7655$2462_Y - end - attribute \src "ls180.v:7694.60-7694.119" - cell $add $add$ls180.v:7694$2472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7694$2472_Y - end - attribute \src "ls180.v:7697.60-7697.119" - cell $add $add$ls180.v:7697$2473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7697$2473_Y - end - attribute \src "ls180.v:7701.59-7701.116" - cell $add $add$ls180.v:7701$2478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7701$2478_Y - end - attribute \src "ls180.v:7740.60-7740.119" - cell $add $add$ls180.v:7740$2488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $add$ls180.v:7740$2488_Y - end - attribute \src "ls180.v:7743.60-7743.119" - cell $add $add$ls180.v:7743$2489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \B 1'1 - connect \Y $add$ls180.v:7743$2489_Y - end - attribute \src "ls180.v:7747.59-7747.116" - cell $add $add$ls180.v:7747$2494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $add$ls180.v:7747$2494_Y - end - attribute \src "ls180.v:7977.34-7977.66" - cell $add $add$ls180.v:7977$2548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_phy_tx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:7977$2548_Y - end - attribute \src "ls180.v:7993.73-7993.131" - cell $add $add$ls180.v:7993$2551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_tx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:7993$2551_Y - end - attribute \src "ls180.v:8006.34-8006.66" - cell $add $add$ls180.v:8006$2555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'1 - connect \Y $add$ls180.v:8006$2555_Y - end - attribute \src "ls180.v:8025.73-8025.131" - cell $add $add$ls180.v:8025$2558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_rx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8025$2558_Y - end - attribute \src "ls180.v:8051.33-8051.65" - cell $add $add$ls180.v:8051$2566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8051$2566_Y - end - attribute \src "ls180.v:8054.33-8054.65" - cell $add $add$ls180.v:8054$2567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8054$2567_Y - end - attribute \src "ls180.v:8058.33-8058.64" - cell $add $add$ls180.v:8058$2572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:8058$2572_Y - end - attribute \src "ls180.v:8073.33-8073.65" - cell $add $add$ls180.v:8073$2577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8073$2577_Y - end - attribute \src "ls180.v:8076.33-8076.65" - cell $add $add$ls180.v:8076$2578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8076$2578_Y - end - attribute \src "ls180.v:8080.33-8080.64" - cell $add $add$ls180.v:8080$2583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $add$ls180.v:8080$2583_Y - end - attribute \src "ls180.v:8101.35-8101.70" - cell $add $add$ls180.v:8101$2585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster30_clk_divider - connect \B 1'1 - connect \Y $add$ls180.v:8101$2585_Y - end - attribute \src "ls180.v:8136.34-8136.68" - cell $add $add$ls180.v:8136$2590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8136$2590_Y - end - attribute \src "ls180.v:8172.25-8172.49" - cell $add $add$ls180.v:8172$2595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_counter - connect \B 1'1 - connect \Y $add$ls180.v:8172$2595_Y - end - attribute \src "ls180.v:8186.25-8186.49" - cell $add $add$ls180.v:8186$2599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_counter - connect \B 1'1 - connect \Y $add$ls180.v:8186$2599_Y - end - attribute \src "ls180.v:8200.31-8200.61" - cell $add $add$ls180.v:8200$2604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 9 - connect \A \main_sdphy_clocker_clks - connect \B 1'1 - connect \Y $add$ls180.v:8200$2604_Y - end - attribute \src "ls180.v:8223.45-8223.88" - cell $add $add$ls180.v:8223$2608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8223$2608_Y - end - attribute \src "ls180.v:8269.71-8269.114" - cell $add $add$ls180.v:8269$2614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8269$2614_Y - end - attribute \src "ls180.v:8304.46-8304.90" - cell $add $add$ls180.v:8304$2620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8304$2620_Y - end - attribute \src "ls180.v:8350.72-8350.116" - cell $add $add$ls180.v:8350$2626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8350$2626_Y - end - attribute \src "ls180.v:8383.47-8383.92" - cell $add $add$ls180.v:8383$2632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8383$2632_Y - end - attribute \src "ls180.v:8411.73-8411.118" - cell $add $add$ls180.v:8411$2638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8411$2638_Y - end - attribute \src "ls180.v:8523.39-8523.75" - cell $add $add$ls180.v:8523$2651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 1'1 - connect \Y $add$ls180.v:8523$2651_Y - end - attribute \src "ls180.v:8584.37-8584.73" - cell $add $add$ls180.v:8584$2655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8584$2655_Y - end - attribute \src "ls180.v:8587.37-8587.73" - cell $add $add$ls180.v:8587$2656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8587$2656_Y - end - attribute \src "ls180.v:8591.36-8591.70" - cell $add $add$ls180.v:8591$2661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8591$2661_Y - end - attribute \src "ls180.v:8606.41-8606.80" - cell $add $add$ls180.v:8606$2665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8606$2665_Y - end - attribute \src "ls180.v:8640.67-8640.106" - cell $add $add$ls180.v:8640$2671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8640$2671_Y - end - attribute \src "ls180.v:8666.39-8666.76" - cell $add $add$ls180.v:8666$2673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdmem2block_converter_mux - connect \B 1'1 - connect \Y $add$ls180.v:8666$2673_Y - end - attribute \src "ls180.v:8670.37-8670.73" - cell $add $add$ls180.v:8670$2677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8670$2677_Y - end - attribute \src "ls180.v:8673.37-8673.73" - cell $add $add$ls180.v:8673$2678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8673$2678_Y - end - attribute \src "ls180.v:8677.36-8677.70" - cell $add $add$ls180.v:8677$2683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8677$2683_Y - end - attribute \src "ls180.v:2810.9-2810.80" - cell $and $and$ls180.v:2810$17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2810$17_Y - end - attribute \src "ls180.v:2828.9-2828.80" - cell $and $and$ls180.v:2828$24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_stb - connect \B \main_libresocsim_libresoc_ibus_cyc - connect \Y $and$ls180.v:2828$24_Y - end - attribute \src "ls180.v:2870.9-2870.80" - cell $and $and$ls180.v:2870$28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2870$28_Y - end - attribute \src "ls180.v:2888.9-2888.80" - cell $and $and$ls180.v:2888$35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_stb - connect \B \main_libresocsim_libresoc_dbus_cyc - connect \Y $and$ls180.v:2888$35_Y - end - attribute \src "ls180.v:2930.9-2930.86" - cell $and $and$ls180.v:2930$39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2930$39_Y - end - attribute \src "ls180.v:2948.9-2948.86" - cell $and $and$ls180.v:2948$46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_stb - connect \B \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $and$ls180.v:2948$46_Y - end - attribute \src "ls180.v:2958.31-2958.90" - cell $and $and$ls180.v:2958$48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2958$48_Y - end - attribute \src "ls180.v:2958.30-2958.121" - cell $and $and$ls180.v:2958$49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2958$48_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2958$49_Y - end - attribute \src "ls180.v:2958.29-2958.156" - cell $and $and$ls180.v:2958$50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2958$49_Y - connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:2958$50_Y - end - attribute \src "ls180.v:2959.31-2959.90" - cell $and $and$ls180.v:2959$51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2959$51_Y - end - attribute \src "ls180.v:2959.30-2959.121" - cell $and $and$ls180.v:2959$52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2959$51_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2959$52_Y - end - attribute \src "ls180.v:2959.29-2959.156" - cell $and $and$ls180.v:2959$53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2959$52_Y - connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:2959$53_Y - end - attribute \src "ls180.v:2960.31-2960.90" - cell $and $and$ls180.v:2960$54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2960$54_Y - end - attribute \src "ls180.v:2960.30-2960.121" - cell $and $and$ls180.v:2960$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2960$54_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2960$55_Y - end - attribute \src "ls180.v:2960.29-2960.156" - cell $and $and$ls180.v:2960$56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2960$55_Y - connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:2960$56_Y - end - attribute \src "ls180.v:2961.31-2961.90" - cell $and $and$ls180.v:2961$57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2961$57_Y - end - attribute \src "ls180.v:2961.30-2961.121" - cell $and $and$ls180.v:2961$58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2961$57_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2961$58_Y - end - attribute \src "ls180.v:2961.29-2961.156" - cell $and $and$ls180.v:2961$59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2961$58_Y - connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:2961$59_Y - end - attribute \src "ls180.v:2970.7-2970.89" - cell $and $and$ls180.v:2970$62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_re - connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:2970$62_Y - end - attribute \src "ls180.v:2975.32-2975.111" - cell $and $and$ls180.v:2975$63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_w - connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:2975$63_Y - end - attribute \src "ls180.v:3089.40-3089.99" - cell $and $and$ls180.v:3089$70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3089$70_Y - end - attribute \src "ls180.v:3090.40-3090.99" - cell $and $and$ls180.v:3090$71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3090$71_Y - end - attribute \src "ls180.v:3128.38-3128.103" - cell $and $and$ls180.v:3128$77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3128$76_Y - connect \Y $and$ls180.v:3128$77_Y - end - attribute \src "ls180.v:3182.50-3182.119" - cell $and $and$ls180.v:3182$85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3182$85_Y - end - attribute \src "ls180.v:3182.49-3182.167" - cell $and $and$ls180.v:3182$86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3182$85_Y - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3182$86_Y - end - attribute \src "ls180.v:3183.49-3183.118" - cell $and $and$ls180.v:3183$87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3183$87_Y - end - attribute \src "ls180.v:3183.48-3183.154" - cell $and $and$ls180.v:3183$88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3183$87_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3183$88_Y - end - attribute \src "ls180.v:3184.50-3184.119" - cell $and $and$ls180.v:3184$89 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3184$89_Y - end - attribute \src "ls180.v:3184.49-3184.155" - cell $and $and$ls180.v:3184$90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3184$89_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3184$90_Y - end - attribute \src "ls180.v:3187.7-3187.114" - cell $and $and$ls180.v:3187$92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3187$92_Y - end - attribute \src "ls180.v:3216.66-3216.246" - cell $and $and$ls180.v:3216$98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3216$97_Y - connect \Y $and$ls180.v:3216$98_Y - end - attribute \src "ls180.v:3217.64-3217.187" - cell $and $and$ls180.v:3217$99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3217$99_Y - end - attribute \src "ls180.v:3241.9-3241.86" - cell $and $and$ls180.v:3241$105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3241$105_Y - end - attribute \src "ls180.v:3253.9-3253.86" - cell $and $and$ls180.v:3253$106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3253$106_Y - end - attribute \src "ls180.v:3303.13-3303.87" - cell $and $and$ls180.v:3303$108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_ready - connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3303$108_Y - end - attribute \src "ls180.v:3339.50-3339.119" - cell $and $and$ls180.v:3339$115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3339$115_Y - end - attribute \src "ls180.v:3339.49-3339.167" - cell $and $and$ls180.v:3339$116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3339$115_Y - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3339$116_Y - end - attribute \src "ls180.v:3340.49-3340.118" - cell $and $and$ls180.v:3340$117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3340$117_Y - end - attribute \src "ls180.v:3340.48-3340.154" - cell $and $and$ls180.v:3340$118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3340$117_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3340$118_Y - end - attribute \src "ls180.v:3341.50-3341.119" - cell $and $and$ls180.v:3341$119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3341$119_Y - end - attribute \src "ls180.v:3341.49-3341.155" - cell $and $and$ls180.v:3341$120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3341$119_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3341$120_Y - end - attribute \src "ls180.v:3344.7-3344.114" - cell $and $and$ls180.v:3344$122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3344$122_Y - end - attribute \src "ls180.v:3373.66-3373.246" - cell $and $and$ls180.v:3373$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3373$127_Y - connect \Y $and$ls180.v:3373$128_Y - end - attribute \src "ls180.v:3374.64-3374.187" - cell $and $and$ls180.v:3374$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3374$129_Y - end - attribute \src "ls180.v:3398.9-3398.86" - cell $and $and$ls180.v:3398$135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3398$135_Y - end - attribute \src "ls180.v:3410.9-3410.86" - cell $and $and$ls180.v:3410$136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3410$136_Y - end - attribute \src "ls180.v:3460.13-3460.87" - cell $and $and$ls180.v:3460$138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_ready - connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3460$138_Y - end - attribute \src "ls180.v:3496.50-3496.119" - cell $and $and$ls180.v:3496$145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3496$145_Y - end - attribute \src "ls180.v:3496.49-3496.167" - cell $and $and$ls180.v:3496$146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3496$145_Y - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3496$146_Y - end - attribute \src "ls180.v:3497.49-3497.118" - cell $and $and$ls180.v:3497$147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3497$147_Y - end - attribute \src "ls180.v:3497.48-3497.154" - cell $and $and$ls180.v:3497$148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3497$147_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3497$148_Y - end - attribute \src "ls180.v:3498.50-3498.119" - cell $and $and$ls180.v:3498$149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3498$149_Y - end - attribute \src "ls180.v:3498.49-3498.155" - cell $and $and$ls180.v:3498$150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3498$149_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3498$150_Y - end - attribute \src "ls180.v:3501.7-3501.114" - cell $and $and$ls180.v:3501$152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3501$152_Y - end - attribute \src "ls180.v:3530.66-3530.246" - cell $and $and$ls180.v:3530$158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3530$157_Y - connect \Y $and$ls180.v:3530$158_Y - end - attribute \src "ls180.v:3531.64-3531.187" - cell $and $and$ls180.v:3531$159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3531$159_Y - end - attribute \src "ls180.v:3555.9-3555.86" - cell $and $and$ls180.v:3555$165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3555$165_Y - end - attribute \src "ls180.v:3567.9-3567.86" - cell $and $and$ls180.v:3567$166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3567$166_Y - end - attribute \src "ls180.v:3617.13-3617.87" - cell $and $and$ls180.v:3617$168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_ready - connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3617$168_Y - end - attribute \src "ls180.v:3653.50-3653.119" - cell $and $and$ls180.v:3653$175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3653$175_Y - end - attribute \src "ls180.v:3653.49-3653.167" - cell $and $and$ls180.v:3653$176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3653$175_Y - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3653$176_Y - end - attribute \src "ls180.v:3654.49-3654.118" - cell $and $and$ls180.v:3654$177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3654$177_Y - end - attribute \src "ls180.v:3654.48-3654.154" - cell $and $and$ls180.v:3654$178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3654$177_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3654$178_Y - end - attribute \src "ls180.v:3655.50-3655.119" - cell $and $and$ls180.v:3655$179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3655$179_Y - end - attribute \src "ls180.v:3655.49-3655.155" - cell $and $and$ls180.v:3655$180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3655$179_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3655$180_Y - end - attribute \src "ls180.v:3658.7-3658.114" - cell $and $and$ls180.v:3658$182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3658$182_Y - end - attribute \src "ls180.v:3687.66-3687.246" - cell $and $and$ls180.v:3687$188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3687$187_Y - connect \Y $and$ls180.v:3687$188_Y - end - attribute \src "ls180.v:3688.64-3688.187" - cell $and $and$ls180.v:3688$189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3688$189_Y - end - attribute \src "ls180.v:3712.9-3712.86" - cell $and $and$ls180.v:3712$195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3712$195_Y - end - attribute \src "ls180.v:3724.9-3724.86" - cell $and $and$ls180.v:3724$196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3724$196_Y - end - attribute \src "ls180.v:3774.13-3774.87" - cell $and $and$ls180.v:3774$198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_ready - connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3774$198_Y - end - attribute \src "ls180.v:3789.37-3789.102" - cell $and $and$ls180.v:3789$199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3789$199_Y - end - attribute \src "ls180.v:3789.108-3789.188" - cell $and $and$ls180.v:3789$201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3789$200_Y - connect \Y $and$ls180.v:3789$201_Y - end - attribute \src "ls180.v:3789.107-3789.231" - cell $and $and$ls180.v:3789$203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3789$201_Y - connect \B $not$ls180.v:3789$202_Y - connect \Y $and$ls180.v:3789$203_Y - end - attribute \src "ls180.v:3789.36-3789.232" - cell $and $and$ls180.v:3789$204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3789$199_Y - connect \B $and$ls180.v:3789$203_Y - connect \Y $and$ls180.v:3789$204_Y - end - attribute \src "ls180.v:3790.37-3790.102" - cell $and $and$ls180.v:3790$205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3790$205_Y - end - attribute \src "ls180.v:3790.108-3790.188" - cell $and $and$ls180.v:3790$207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3790$206_Y - connect \Y $and$ls180.v:3790$207_Y - end - attribute \src "ls180.v:3790.107-3790.231" - cell $and $and$ls180.v:3790$209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3790$207_Y - connect \B $not$ls180.v:3790$208_Y - connect \Y $and$ls180.v:3790$209_Y - end - attribute \src "ls180.v:3790.36-3790.232" - cell $and $and$ls180.v:3790$210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3790$205_Y - connect \B $and$ls180.v:3790$209_Y - connect \Y $and$ls180.v:3790$210_Y - end - attribute \src "ls180.v:3791.34-3791.85" - cell $and $and$ls180.v:3791$211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_trrdcon_ready - connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3791$211_Y - end - attribute \src "ls180.v:3792.37-3792.102" - cell $and $and$ls180.v:3792$212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3792$212_Y - end - attribute \src "ls180.v:3792.36-3792.194" - cell $and $and$ls180.v:3792$214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3792$212_Y - connect \B $or$ls180.v:3792$213_Y - connect \Y $and$ls180.v:3792$214_Y - end - attribute \src "ls180.v:3794.37-3794.102" - cell $and $and$ls180.v:3794$215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3794$215_Y - end - attribute \src "ls180.v:3794.36-3794.148" - cell $and $and$ls180.v:3794$216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3794$215_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3794$216_Y - end - attribute \src "ls180.v:3795.40-3795.119" - cell $and $and$ls180.v:3795$217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3795$217_Y - end - attribute \src "ls180.v:3795.124-3795.203" - cell $and $and$ls180.v:3795$218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3795$218_Y - end - attribute \src "ls180.v:3795.209-3795.288" - cell $and $and$ls180.v:3795$220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3795$220_Y - end - attribute \src "ls180.v:3795.294-3795.373" - cell $and $and$ls180.v:3795$222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3795$222_Y - end - attribute \src "ls180.v:3796.41-3796.121" - cell $and $and$ls180.v:3796$224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3796$224_Y - end - attribute \src "ls180.v:3796.126-3796.206" - cell $and $and$ls180.v:3796$225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3796$225_Y - end - attribute \src "ls180.v:3796.212-3796.292" - cell $and $and$ls180.v:3796$227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3796$227_Y - end - attribute \src "ls180.v:3796.298-3796.378" - cell $and $and$ls180.v:3796$229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3796$229_Y - end - attribute \src "ls180.v:3803.38-3803.111" - cell $and $and$ls180.v:3803$233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_gnt - connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3803$233_Y - end - attribute \src "ls180.v:3803.37-3803.150" - cell $and $and$ls180.v:3803$234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3803$233_Y - connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3803$234_Y - end - attribute \src "ls180.v:3803.36-3803.189" - cell $and $and$ls180.v:3803$235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3803$234_Y - connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3803$235_Y - end - attribute \src "ls180.v:3809.77-3809.153" - cell $and $and$ls180.v:3809$238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3809$238_Y - end - attribute \src "ls180.v:3809.162-3809.246" - cell $and $and$ls180.v:3809$240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3809$239_Y - connect \Y $and$ls180.v:3809$240_Y - end - attribute \src "ls180.v:3809.161-3809.291" - cell $and $and$ls180.v:3809$242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$240_Y - connect \B $not$ls180.v:3809$241_Y - connect \Y $and$ls180.v:3809$242_Y - end - attribute \src "ls180.v:3809.76-3809.333" - cell $and $and$ls180.v:3809$245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$238_Y - connect \B $or$ls180.v:3809$244_Y - connect \Y $and$ls180.v:3809$245_Y - end - attribute \src "ls180.v:3809.338-3809.505" - cell $and $and$ls180.v:3809$248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3809$246_Y - connect \B $eq$ls180.v:3809$247_Y - connect \Y $and$ls180.v:3809$248_Y - end - attribute \src "ls180.v:3809.38-3809.507" - cell $and $and$ls180.v:3809$250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3809$249_Y - connect \Y $and$ls180.v:3809$250_Y - end - attribute \src "ls180.v:3810.77-3810.153" - cell $and $and$ls180.v:3810$251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3810$251_Y - end - attribute \src "ls180.v:3810.162-3810.246" - cell $and $and$ls180.v:3810$253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3810$252_Y - connect \Y $and$ls180.v:3810$253_Y - end - attribute \src "ls180.v:3810.161-3810.291" - cell $and $and$ls180.v:3810$255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$253_Y - connect \B $not$ls180.v:3810$254_Y - connect \Y $and$ls180.v:3810$255_Y - end - attribute \src "ls180.v:3810.76-3810.333" - cell $and $and$ls180.v:3810$258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$251_Y - connect \B $or$ls180.v:3810$257_Y - connect \Y $and$ls180.v:3810$258_Y - end - attribute \src "ls180.v:3810.338-3810.505" - cell $and $and$ls180.v:3810$261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3810$259_Y - connect \B $eq$ls180.v:3810$260_Y - connect \Y $and$ls180.v:3810$261_Y - end - attribute \src "ls180.v:3810.38-3810.507" - cell $and $and$ls180.v:3810$263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3810$262_Y - connect \Y $and$ls180.v:3810$263_Y - end - attribute \src "ls180.v:3811.77-3811.153" - cell $and $and$ls180.v:3811$264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3811$264_Y - end - attribute \src "ls180.v:3811.162-3811.246" - cell $and $and$ls180.v:3811$266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3811$265_Y - connect \Y $and$ls180.v:3811$266_Y - end - attribute \src "ls180.v:3811.161-3811.291" - cell $and $and$ls180.v:3811$268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$266_Y - connect \B $not$ls180.v:3811$267_Y - connect \Y $and$ls180.v:3811$268_Y - end - attribute \src "ls180.v:3811.76-3811.333" - cell $and $and$ls180.v:3811$271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$264_Y - connect \B $or$ls180.v:3811$270_Y - connect \Y $and$ls180.v:3811$271_Y - end - attribute \src "ls180.v:3811.338-3811.505" - cell $and $and$ls180.v:3811$274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3811$272_Y - connect \B $eq$ls180.v:3811$273_Y - connect \Y $and$ls180.v:3811$274_Y - end - attribute \src "ls180.v:3811.38-3811.507" - cell $and $and$ls180.v:3811$276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3811$275_Y - connect \Y $and$ls180.v:3811$276_Y - end - attribute \src "ls180.v:3812.77-3812.153" - cell $and $and$ls180.v:3812$277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3812$277_Y - end - attribute \src "ls180.v:3812.162-3812.246" - cell $and $and$ls180.v:3812$279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3812$278_Y - connect \Y $and$ls180.v:3812$279_Y - end - attribute \src "ls180.v:3812.161-3812.291" - cell $and $and$ls180.v:3812$281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3812$279_Y - connect \B $not$ls180.v:3812$280_Y - connect \Y $and$ls180.v:3812$281_Y - end - attribute \src "ls180.v:3812.76-3812.333" - cell $and $and$ls180.v:3812$284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3812$277_Y - connect \B $or$ls180.v:3812$283_Y - connect \Y $and$ls180.v:3812$284_Y - end - attribute \src "ls180.v:3812.338-3812.505" - cell $and $and$ls180.v:3812$287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3812$285_Y - connect \B $eq$ls180.v:3812$286_Y - connect \Y $and$ls180.v:3812$287_Y - end - attribute \src "ls180.v:3812.38-3812.507" - cell $and $and$ls180.v:3812$289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3812$288_Y - connect \Y $and$ls180.v:3812$289_Y - end - attribute \src "ls180.v:3842.77-3842.153" - cell $and $and$ls180.v:3842$296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3842$296_Y - end - attribute \src "ls180.v:3842.162-3842.246" - cell $and $and$ls180.v:3842$298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3842$297_Y - connect \Y $and$ls180.v:3842$298_Y - end - attribute \src "ls180.v:3842.161-3842.291" - cell $and $and$ls180.v:3842$300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$298_Y - connect \B $not$ls180.v:3842$299_Y - connect \Y $and$ls180.v:3842$300_Y - end - attribute \src "ls180.v:3842.76-3842.333" - cell $and $and$ls180.v:3842$303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$296_Y - connect \B $or$ls180.v:3842$302_Y - connect \Y $and$ls180.v:3842$303_Y - end - attribute \src "ls180.v:3842.338-3842.505" - cell $and $and$ls180.v:3842$306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3842$304_Y - connect \B $eq$ls180.v:3842$305_Y - connect \Y $and$ls180.v:3842$306_Y - end - attribute \src "ls180.v:3842.38-3842.507" - cell $and $and$ls180.v:3842$308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3842$307_Y - connect \Y $and$ls180.v:3842$308_Y - end - attribute \src "ls180.v:3843.77-3843.153" - cell $and $and$ls180.v:3843$309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3843$309_Y - end - attribute \src "ls180.v:3843.162-3843.246" - cell $and $and$ls180.v:3843$311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3843$310_Y - connect \Y $and$ls180.v:3843$311_Y - end - attribute \src "ls180.v:3843.161-3843.291" - cell $and $and$ls180.v:3843$313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$311_Y - connect \B $not$ls180.v:3843$312_Y - connect \Y $and$ls180.v:3843$313_Y - end - attribute \src "ls180.v:3843.76-3843.333" - cell $and $and$ls180.v:3843$316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$309_Y - connect \B $or$ls180.v:3843$315_Y - connect \Y $and$ls180.v:3843$316_Y - end - attribute \src "ls180.v:3843.338-3843.505" - cell $and $and$ls180.v:3843$319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3843$317_Y - connect \B $eq$ls180.v:3843$318_Y - connect \Y $and$ls180.v:3843$319_Y - end - attribute \src "ls180.v:3843.38-3843.507" - cell $and $and$ls180.v:3843$321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3843$320_Y - connect \Y $and$ls180.v:3843$321_Y - end - attribute \src "ls180.v:3844.77-3844.153" - cell $and $and$ls180.v:3844$322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3844$322_Y - end - attribute \src "ls180.v:3844.162-3844.246" - cell $and $and$ls180.v:3844$324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3844$323_Y - connect \Y $and$ls180.v:3844$324_Y - end - attribute \src "ls180.v:3844.161-3844.291" - cell $and $and$ls180.v:3844$326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$324_Y - connect \B $not$ls180.v:3844$325_Y - connect \Y $and$ls180.v:3844$326_Y - end - attribute \src "ls180.v:3844.76-3844.333" - cell $and $and$ls180.v:3844$329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$322_Y - connect \B $or$ls180.v:3844$328_Y - connect \Y $and$ls180.v:3844$329_Y - end - attribute \src "ls180.v:3844.338-3844.505" - cell $and $and$ls180.v:3844$332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3844$330_Y - connect \B $eq$ls180.v:3844$331_Y - connect \Y $and$ls180.v:3844$332_Y - end - attribute \src "ls180.v:3844.38-3844.507" - cell $and $and$ls180.v:3844$334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3844$333_Y - connect \Y $and$ls180.v:3844$334_Y - end - attribute \src "ls180.v:3845.77-3845.153" - cell $and $and$ls180.v:3845$335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3845$335_Y - end - attribute \src "ls180.v:3845.162-3845.246" - cell $and $and$ls180.v:3845$337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3845$336_Y - connect \Y $and$ls180.v:3845$337_Y - end - attribute \src "ls180.v:3845.161-3845.291" - cell $and $and$ls180.v:3845$339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3845$337_Y - connect \B $not$ls180.v:3845$338_Y - connect \Y $and$ls180.v:3845$339_Y - end - attribute \src "ls180.v:3845.76-3845.333" - cell $and $and$ls180.v:3845$342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3845$335_Y - connect \B $or$ls180.v:3845$341_Y - connect \Y $and$ls180.v:3845$342_Y - end - attribute \src "ls180.v:3845.338-3845.505" - cell $and $and$ls180.v:3845$345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3845$343_Y - connect \B $eq$ls180.v:3845$344_Y - connect \Y $and$ls180.v:3845$345_Y - end - attribute \src "ls180.v:3845.38-3845.507" - cell $and $and$ls180.v:3845$347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3845$346_Y - connect \Y $and$ls180.v:3845$347_Y - end - attribute \src "ls180.v:3874.8-3874.73" - cell $and $and$ls180.v:3874$352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3874$352_Y - end - attribute \src "ls180.v:3874.7-3874.114" - cell $and $and$ls180.v:3874$354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3874$352_Y - connect \B $eq$ls180.v:3874$353_Y - connect \Y $and$ls180.v:3874$354_Y - end - attribute \src "ls180.v:3877.8-3877.73" - cell $and $and$ls180.v:3877$355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3877$355_Y - end - attribute \src "ls180.v:3877.7-3877.114" - cell $and $and$ls180.v:3877$357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3877$355_Y - connect \B $eq$ls180.v:3877$356_Y - connect \Y $and$ls180.v:3877$357_Y - end - attribute \src "ls180.v:3883.8-3883.73" - cell $and $and$ls180.v:3883$359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3883$359_Y - end - attribute \src "ls180.v:3883.7-3883.114" - cell $and $and$ls180.v:3883$361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3883$359_Y - connect \B $eq$ls180.v:3883$360_Y - connect \Y $and$ls180.v:3883$361_Y - end - attribute \src "ls180.v:3886.8-3886.73" - cell $and $and$ls180.v:3886$362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3886$362_Y - end - attribute \src "ls180.v:3886.7-3886.114" - cell $and $and$ls180.v:3886$364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3886$362_Y - connect \B $eq$ls180.v:3886$363_Y - connect \Y $and$ls180.v:3886$364_Y - end - attribute \src "ls180.v:3892.8-3892.73" - cell $and $and$ls180.v:3892$366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3892$366_Y - end - attribute \src "ls180.v:3892.7-3892.114" - cell $and $and$ls180.v:3892$368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3892$366_Y - connect \B $eq$ls180.v:3892$367_Y - connect \Y $and$ls180.v:3892$368_Y - end - attribute \src "ls180.v:3895.8-3895.73" - cell $and $and$ls180.v:3895$369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3895$369_Y - end - attribute \src "ls180.v:3895.7-3895.114" - cell $and $and$ls180.v:3895$371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3895$369_Y - connect \B $eq$ls180.v:3895$370_Y - connect \Y $and$ls180.v:3895$371_Y - end - attribute \src "ls180.v:3901.8-3901.73" - cell $and $and$ls180.v:3901$373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3901$373_Y - end - attribute \src "ls180.v:3901.7-3901.114" - cell $and $and$ls180.v:3901$375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3901$373_Y - connect \B $eq$ls180.v:3901$374_Y - connect \Y $and$ls180.v:3901$375_Y - end - attribute \src "ls180.v:3904.8-3904.73" - cell $and $and$ls180.v:3904$376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3904$376_Y - end - attribute \src "ls180.v:3904.7-3904.114" - cell $and $and$ls180.v:3904$378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3904$376_Y - connect \B $eq$ls180.v:3904$377_Y - connect \Y $and$ls180.v:3904$378_Y - end - attribute \src "ls180.v:3929.71-3929.151" - cell $and $and$ls180.v:3929$383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3929$382_Y - connect \Y $and$ls180.v:3929$383_Y - end - attribute \src "ls180.v:3929.70-3929.194" - cell $and $and$ls180.v:3929$385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3929$383_Y - connect \B $not$ls180.v:3929$384_Y - connect \Y $and$ls180.v:3929$385_Y - end - attribute \src "ls180.v:3929.41-3929.222" - cell $and $and$ls180.v:3929$388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3929$387_Y - connect \Y $and$ls180.v:3929$388_Y - end - attribute \src "ls180.v:3967.71-3967.151" - cell $and $and$ls180.v:3967$392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3967$391_Y - connect \Y $and$ls180.v:3967$392_Y - end - attribute \src "ls180.v:3967.70-3967.194" - cell $and $and$ls180.v:3967$394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3967$392_Y - connect \B $not$ls180.v:3967$393_Y - connect \Y $and$ls180.v:3967$394_Y - end - attribute \src "ls180.v:3967.41-3967.222" - cell $and $and$ls180.v:3967$397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3967$396_Y - connect \Y $and$ls180.v:3967$397_Y - end - attribute \src "ls180.v:3985.110-3985.179" - cell $and $and$ls180.v:3985$402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3985$401_Y - connect \Y $and$ls180.v:3985$402_Y - end - attribute \src "ls180.v:3985.185-3985.254" - cell $and $and$ls180.v:3985$405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3985$404_Y - connect \Y $and$ls180.v:3985$405_Y - end - attribute \src "ls180.v:3985.260-3985.329" - cell $and $and$ls180.v:3985$408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3985$407_Y - connect \Y $and$ls180.v:3985$408_Y - end - attribute \src "ls180.v:3985.41-3985.332" - cell $and $and$ls180.v:3985$411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3985$400_Y - connect \B $not$ls180.v:3985$410_Y - connect \Y $and$ls180.v:3985$411_Y - end - attribute \src "ls180.v:3985.40-3985.355" - cell $and $and$ls180.v:3985$412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3985$411_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3985$412_Y - end - attribute \src "ls180.v:3986.34-3986.106" - cell $and $and$ls180.v:3986$415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3986$413_Y - connect \B $not$ls180.v:3986$414_Y - connect \Y $and$ls180.v:3986$415_Y - end - attribute \src "ls180.v:3990.110-3990.179" - cell $and $and$ls180.v:3990$418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3990$417_Y - connect \Y $and$ls180.v:3990$418_Y - end - attribute \src "ls180.v:3990.185-3990.254" - cell $and $and$ls180.v:3990$421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:3990$420_Y - connect \Y $and$ls180.v:3990$421_Y - end - attribute \src "ls180.v:3990.260-3990.329" - cell $and $and$ls180.v:3990$424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3990$423_Y - connect \Y $and$ls180.v:3990$424_Y - end - attribute \src "ls180.v:3990.41-3990.332" - cell $and $and$ls180.v:3990$427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3990$416_Y - connect \B $not$ls180.v:3990$426_Y - connect \Y $and$ls180.v:3990$427_Y - end - attribute \src "ls180.v:3990.40-3990.355" - cell $and $and$ls180.v:3990$428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3990$427_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3990$428_Y - end - attribute \src "ls180.v:3991.34-3991.106" - cell $and $and$ls180.v:3991$431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3991$429_Y - connect \B $not$ls180.v:3991$430_Y - connect \Y $and$ls180.v:3991$431_Y - end - attribute \src "ls180.v:3995.110-3995.179" - cell $and $and$ls180.v:3995$434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:3995$433_Y - connect \Y $and$ls180.v:3995$434_Y - end - attribute \src "ls180.v:3995.185-3995.254" - cell $and $and$ls180.v:3995$437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:3995$436_Y - connect \Y $and$ls180.v:3995$437_Y - end - attribute \src "ls180.v:3995.260-3995.329" - cell $and $and$ls180.v:3995$440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:3995$439_Y - connect \Y $and$ls180.v:3995$440_Y - end - attribute \src "ls180.v:3995.41-3995.332" - cell $and $and$ls180.v:3995$443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3995$432_Y - connect \B $not$ls180.v:3995$442_Y - connect \Y $and$ls180.v:3995$443_Y - end - attribute \src "ls180.v:3995.40-3995.355" - cell $and $and$ls180.v:3995$444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3995$443_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:3995$444_Y - end - attribute \src "ls180.v:3996.34-3996.106" - cell $and $and$ls180.v:3996$447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3996$445_Y - connect \B $not$ls180.v:3996$446_Y - connect \Y $and$ls180.v:3996$447_Y - end - attribute \src "ls180.v:4000.110-4000.179" - cell $and $and$ls180.v:4000$450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4000$449_Y - connect \Y $and$ls180.v:4000$450_Y - end - attribute \src "ls180.v:4000.185-4000.254" - cell $and $and$ls180.v:4000$453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4000$452_Y - connect \Y $and$ls180.v:4000$453_Y - end - attribute \src "ls180.v:4000.260-4000.329" - cell $and $and$ls180.v:4000$456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4000$455_Y - connect \Y $and$ls180.v:4000$456_Y - end - attribute \src "ls180.v:4000.41-4000.332" - cell $and $and$ls180.v:4000$459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4000$448_Y - connect \B $not$ls180.v:4000$458_Y - connect \Y $and$ls180.v:4000$459_Y - end - attribute \src "ls180.v:4000.40-4000.355" - cell $and $and$ls180.v:4000$460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4000$459_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4000$460_Y - end - attribute \src "ls180.v:4001.34-4001.106" - cell $and $and$ls180.v:4001$463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4001$461_Y - connect \B $not$ls180.v:4001$462_Y - connect \Y $and$ls180.v:4001$463_Y - end - attribute \src "ls180.v:4005.151-4005.220" - cell $and $and$ls180.v:4005$467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4005$466_Y - connect \Y $and$ls180.v:4005$467_Y - end - attribute \src "ls180.v:4005.226-4005.295" - cell $and $and$ls180.v:4005$470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4005$469_Y - connect \Y $and$ls180.v:4005$470_Y - end - attribute \src "ls180.v:4005.301-4005.370" - cell $and $and$ls180.v:4005$473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4005$472_Y - connect \Y $and$ls180.v:4005$473_Y - end - attribute \src "ls180.v:4005.82-4005.373" - cell $and $and$ls180.v:4005$476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$465_Y - connect \B $not$ls180.v:4005$475_Y - connect \Y $and$ls180.v:4005$476_Y - end - attribute \src "ls180.v:4005.43-4005.374" - cell $and $and$ls180.v:4005$477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$464_Y - connect \B $and$ls180.v:4005$476_Y - connect \Y $and$ls180.v:4005$477_Y - end - attribute \src "ls180.v:4005.42-4005.410" - cell $and $and$ls180.v:4005$478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4005$477_Y - connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4005$478_Y - end - attribute \src "ls180.v:4005.525-4005.594" - cell $and $and$ls180.v:4005$483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4005$482_Y - connect \Y $and$ls180.v:4005$483_Y - end - attribute \src "ls180.v:4005.600-4005.669" - cell $and $and$ls180.v:4005$486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4005$485_Y - connect \Y $and$ls180.v:4005$486_Y - end - attribute \src "ls180.v:4005.675-4005.744" - cell $and $and$ls180.v:4005$489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4005$488_Y - connect \Y $and$ls180.v:4005$489_Y - end - attribute \src "ls180.v:4005.456-4005.747" - cell $and $and$ls180.v:4005$492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$481_Y - connect \B $not$ls180.v:4005$491_Y - connect \Y $and$ls180.v:4005$492_Y - end - attribute \src "ls180.v:4005.417-4005.748" - cell $and $and$ls180.v:4005$493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$480_Y - connect \B $and$ls180.v:4005$492_Y - connect \Y $and$ls180.v:4005$493_Y - end - attribute \src "ls180.v:4005.416-4005.784" - cell $and $and$ls180.v:4005$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4005$493_Y - connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4005$494_Y - end - attribute \src "ls180.v:4005.899-4005.968" - cell $and $and$ls180.v:4005$499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4005$498_Y - connect \Y $and$ls180.v:4005$499_Y - end - attribute \src "ls180.v:4005.974-4005.1043" - cell $and $and$ls180.v:4005$502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4005$501_Y - connect \Y $and$ls180.v:4005$502_Y - end - attribute \src "ls180.v:4005.1049-4005.1118" - cell $and $and$ls180.v:4005$505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4005$504_Y - connect \Y $and$ls180.v:4005$505_Y - end - attribute \src "ls180.v:4005.830-4005.1121" - cell $and $and$ls180.v:4005$508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$497_Y - connect \B $not$ls180.v:4005$507_Y - connect \Y $and$ls180.v:4005$508_Y - end - attribute \src "ls180.v:4005.791-4005.1122" - cell $and $and$ls180.v:4005$509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$496_Y - connect \B $and$ls180.v:4005$508_Y - connect \Y $and$ls180.v:4005$509_Y - end - attribute \src "ls180.v:4005.790-4005.1158" - cell $and $and$ls180.v:4005$510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4005$509_Y - connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4005$510_Y - end - attribute \src "ls180.v:4005.1273-4005.1342" - cell $and $and$ls180.v:4005$515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4005$514_Y - connect \Y $and$ls180.v:4005$515_Y - end - attribute \src "ls180.v:4005.1348-4005.1417" - cell $and $and$ls180.v:4005$518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4005$517_Y - connect \Y $and$ls180.v:4005$518_Y - end - attribute \src "ls180.v:4005.1423-4005.1492" - cell $and $and$ls180.v:4005$521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4005$520_Y - connect \Y $and$ls180.v:4005$521_Y - end - attribute \src "ls180.v:4005.1204-4005.1495" - cell $and $and$ls180.v:4005$524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$513_Y - connect \B $not$ls180.v:4005$523_Y - connect \Y $and$ls180.v:4005$524_Y - end - attribute \src "ls180.v:4005.1165-4005.1496" - cell $and $and$ls180.v:4005$525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4005$512_Y - connect \B $and$ls180.v:4005$524_Y - connect \Y $and$ls180.v:4005$525_Y - end - attribute \src "ls180.v:4005.1164-4005.1532" - cell $and $and$ls180.v:4005$526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4005$525_Y - connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4005$526_Y - end - attribute \src "ls180.v:4063.9-4063.46" - cell $and $and$ls180.v:4063$532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4063$532_Y - end - attribute \src "ls180.v:4081.9-4081.46" - cell $and $and$ls180.v:4081$539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4081$539_Y - end - attribute \src "ls180.v:4094.32-4094.75" - cell $and $and$ls180.v:4094$543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4094$543_Y - end - attribute \src "ls180.v:4094.31-4094.99" - cell $and $and$ls180.v:4094$545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4094$543_Y - connect \B $not$ls180.v:4094$544_Y - connect \Y $and$ls180.v:4094$545_Y - end - attribute \src "ls180.v:4095.34-4095.102" - cell $and $and$ls180.v:4095$547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4095$546_Y - connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4095$547_Y - end - attribute \src "ls180.v:4095.33-4095.128" - cell $and $and$ls180.v:4095$549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4095$547_Y - connect \B $not$ls180.v:4095$548_Y - connect \Y $and$ls180.v:4095$549_Y - end - attribute \src "ls180.v:4096.33-4096.104" - cell $and $and$ls180.v:4096$552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4096$550_Y - connect \B $not$ls180.v:4096$551_Y - connect \Y $and$ls180.v:4096$552_Y - end - attribute \src "ls180.v:4097.49-4097.85" - cell $and $and$ls180.v:4097$553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \B \main_ack_wdata - connect \Y $and$ls180.v:4097$553_Y - end - attribute \src "ls180.v:4097.90-4097.129" - cell $and $and$ls180.v:4097$555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4097$554_Y - connect \B \main_ack_rdata - connect \Y $and$ls180.v:4097$555_Y - end - attribute \src "ls180.v:4097.32-4097.131" - cell $and $and$ls180.v:4097$557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_ack_cmd - connect \B $or$ls180.v:4097$556_Y - connect \Y $and$ls180.v:4097$557_Y - end - attribute \src "ls180.v:4098.25-4098.66" - cell $and $and$ls180.v:4098$558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4098$558_Y - end - attribute \src "ls180.v:4099.27-4099.72" - cell $and $and$ls180.v:4099$560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4099$560_Y - end - attribute \src "ls180.v:4100.26-4100.71" - cell $and $and$ls180.v:4100$562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_rdata_valid - connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4100$562_Y - end - attribute \src "ls180.v:4129.64-4129.88" - cell $and $and$ls180.v:4129$568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4129$568_Y - end - attribute \src "ls180.v:4133.7-4133.78" - cell $and $and$ls180.v:4133$572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4133$572_Y - end - attribute \src "ls180.v:4144.7-4144.78" - cell $and $and$ls180.v:4144$575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4144$575_Y - end - attribute \src "ls180.v:4153.26-4153.97" - cell $and $and$ls180.v:4153$577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [0] - connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4153$577_Y - end - attribute \src "ls180.v:4153.102-4153.173" - cell $and $and$ls180.v:4153$578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [1] - connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4153$578_Y - end - attribute \src "ls180.v:4168.41-4168.133" - cell $and $and$ls180.v:4168$582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4168$581_Y - connect \Y $and$ls180.v:4168$582_Y - end - attribute \src "ls180.v:4179.39-4179.136" - cell $and $and$ls180.v:4179$587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4179$586_Y - connect \Y $and$ls180.v:4179$587_Y - end - attribute \src "ls180.v:4180.37-4180.104" - cell $and $and$ls180.v:4180$588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4180$588_Y - end - attribute \src "ls180.v:4198.41-4198.133" - cell $and $and$ls180.v:4198$593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4198$592_Y - connect \Y $and$ls180.v:4198$593_Y - end - attribute \src "ls180.v:4209.39-4209.136" - cell $and $and$ls180.v:4209$598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4209$597_Y - connect \Y $and$ls180.v:4209$598_Y - end - attribute \src "ls180.v:4210.37-4210.104" - cell $and $and$ls180.v:4210$599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4210$599_Y - end - attribute \src "ls180.v:4398.33-4398.86" - cell $and $and$ls180.v:4398$641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4398$640_Y - connect \Y $and$ls180.v:4398$641_Y - end - attribute \src "ls180.v:4502.9-4502.68" - cell $and $and$ls180.v:4502$650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4502$650_Y - end - attribute \src "ls180.v:4522.53-4522.145" - cell $and $and$ls180.v:4522$653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4522$652_Y - connect \Y $and$ls180.v:4522$653_Y - end - attribute \src "ls180.v:4541.52-4541.137" - cell $and $and$ls180.v:4541$656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4541$656_Y - end - attribute \src "ls180.v:4582.9-4582.68" - cell $and $and$ls180.v:4582$664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4582$664_Y - end - attribute \src "ls180.v:4620.9-4620.68" - cell $and $and$ls180.v:4620$670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4620$670_Y - end - attribute \src "ls180.v:4629.10-4629.69" - cell $and $and$ls180.v:4629$671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_sink_valid - connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4629$671_Y - end - attribute \src "ls180.v:4629.9-4629.93" - cell $and $and$ls180.v:4629$672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4629$671_Y - connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4629$672_Y - end - attribute \src "ls180.v:4649.54-4649.117" - cell $and $and$ls180.v:4649$674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_valid - connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4649$674_Y - end - attribute \src "ls180.v:4668.53-4668.140" - cell $and $and$ls180.v:4668$677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4668$677_Y - end - attribute \src "ls180.v:4765.9-4765.70" - cell $and $and$ls180.v:4765$687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4765$687_Y - end - attribute \src "ls180.v:4783.55-4783.120" - cell $and $and$ls180.v:4783$689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_valid - connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4783$689_Y - end - attribute \src "ls180.v:4802.54-4802.143" - cell $and $and$ls180.v:4802$692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4802$692_Y - end - attribute \src "ls180.v:4884.9-4884.70" - cell $and $and$ls180.v:4884$707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_valid - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4884$707_Y - end - attribute \src "ls180.v:4891.9-4891.70" - cell $and $and$ls180.v:4891$708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_sink_valid - connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4891$708_Y - end - attribute \src "ls180.v:4972.48-4972.124" - cell $and $and$ls180.v:4972$831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4972$831_Y - end - attribute \src "ls180.v:4972.47-4972.165" - cell $and $and$ls180.v:4972$832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4972$831_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4972$832_Y - end - attribute \src "ls180.v:4973.50-4973.127" - cell $and $and$ls180.v:4973$833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4973$833_Y - end - attribute \src "ls180.v:4975.48-4975.124" - cell $and $and$ls180.v:4975$834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4975$834_Y - end - attribute \src "ls180.v:4975.47-4975.165" - cell $and $and$ls180.v:4975$835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4975$834_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4975$835_Y - end - attribute \src "ls180.v:4976.50-4976.127" - cell $and $and$ls180.v:4976$836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4976$836_Y - end - attribute \src "ls180.v:4978.48-4978.124" - cell $and $and$ls180.v:4978$837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4978$837_Y - end - attribute \src "ls180.v:4978.47-4978.165" - cell $and $and$ls180.v:4978$838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4978$837_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4978$838_Y - end - attribute \src "ls180.v:4979.50-4979.127" - cell $and $and$ls180.v:4979$839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4979$839_Y - end - attribute \src "ls180.v:4981.48-4981.124" - cell $and $and$ls180.v:4981$840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:4981$840_Y - end - attribute \src "ls180.v:4981.47-4981.165" - cell $and $and$ls180.v:4981$841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4981$840_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4981$841_Y - end - attribute \src "ls180.v:4982.50-4982.127" - cell $and $and$ls180.v:4982$842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:4982$842_Y - end - attribute \src "ls180.v:5095.10-5095.86" - cell $and $and$ls180.v:5095$891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5095$891_Y - end - attribute \src "ls180.v:5095.9-5095.127" - cell $and $and$ls180.v:5095$892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5095$891_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5095$892_Y - end - attribute \src "ls180.v:5105.9-5105.152" - cell $and $and$ls180.v:5105$896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5105$894_Y - connect \B $eq$ls180.v:5105$895_Y - connect \Y $and$ls180.v:5105$896_Y - end - attribute \src "ls180.v:5105.8-5105.226" - cell $and $and$ls180.v:5105$898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5105$896_Y - connect \B $eq$ls180.v:5105$897_Y - connect \Y $and$ls180.v:5105$898_Y - end - attribute \src "ls180.v:5105.7-5105.300" - cell $and $and$ls180.v:5105$900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5105$898_Y - connect \B $eq$ls180.v:5105$899_Y - connect \Y $and$ls180.v:5105$900_Y - end - attribute \src "ls180.v:5110.49-5110.124" - cell $and $and$ls180.v:5110$901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5110$901_Y - end - attribute \src "ls180.v:5120.49-5120.124" - cell $and $and$ls180.v:5120$904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5120$904_Y - end - attribute \src "ls180.v:5130.49-5130.124" - cell $and $and$ls180.v:5130$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5130$907_Y - end - attribute \src "ls180.v:5140.49-5140.124" - cell $and $and$ls180.v:5140$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5140$910_Y - end - attribute \src "ls180.v:5152.7-5152.84" - cell $and $and$ls180.v:5152$915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5152$914_Y - connect \Y $and$ls180.v:5152$915_Y - end - attribute \src "ls180.v:5270.9-5270.64" - cell $and $and$ls180.v:5270$964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5270$964_Y - end - attribute \src "ls180.v:5322.10-5322.66" - cell $and $and$ls180.v:5322$973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5322$973_Y - end - attribute \src "ls180.v:5322.9-5322.97" - cell $and $and$ls180.v:5322$974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5322$973_Y - connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5322$974_Y - end - attribute \src "ls180.v:5348.11-5348.71" - cell $and $and$ls180.v:5348$982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_last - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5348$982_Y - end - attribute \src "ls180.v:5432.43-5432.152" - cell $and $and$ls180.v:5432$990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5432$989_Y - connect \Y $and$ls180.v:5432$990_Y - end - attribute \src "ls180.v:5433.41-5433.116" - cell $and $and$ls180.v:5433$991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_readable - connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5433$991_Y - end - attribute \src "ls180.v:5445.48-5445.125" - cell $and $and$ls180.v:5445$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5445$996_Y - end - attribute \src "ls180.v:5472.9-5472.102" - cell $and $and$ls180.v:5472$1000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid - connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5472$1000_Y - end - attribute \src "ls180.v:5545.9-5545.58" - cell $and $and$ls180.v:5545$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_bus_stb - connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5545$1006_Y - end - attribute \src "ls180.v:5598.51-5598.123" - cell $and $and$ls180.v:5598$1014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_first - connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5598$1014_Y - end - attribute \src "ls180.v:5599.50-5599.120" - cell $and $and$ls180.v:5599$1015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_last - connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5599$1015_Y - end - attribute \src "ls180.v:5600.49-5600.122" - cell $and $and$ls180.v:5600$1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_last - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5600$1016_Y - end - attribute \src "ls180.v:5640.43-5640.152" - cell $and $and$ls180.v:5640$1021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5640$1020_Y - connect \Y $and$ls180.v:5640$1021_Y - end - attribute \src "ls180.v:5641.41-5641.116" - cell $and $and$ls180.v:5641$1022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_readable - connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5641$1022_Y - end - attribute \src "ls180.v:5673.9-5673.76" - cell $and $and$ls180.v:5673$1026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_cyc - connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5673$1026_Y - end - attribute \src "ls180.v:5676.44-5676.120" - cell $and $and$ls180.v:5676$1028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5676$1027_Y - connect \Y $and$ls180.v:5676$1028_Y - end - attribute \src "ls180.v:5696.63-5696.107" - cell $and $and$ls180.v:5696$1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5696$1029_Y - connect \Y $and$ls180.v:5696$1030_Y - end - attribute \src "ls180.v:5697.63-5697.107" - cell $and $and$ls180.v:5697$1032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5697$1031_Y - connect \Y $and$ls180.v:5697$1032_Y - end - attribute \src "ls180.v:5698.63-5698.107" - cell $and $and$ls180.v:5698$1034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5698$1033_Y - connect \Y $and$ls180.v:5698$1034_Y - end - attribute \src "ls180.v:5699.35-5699.79" - cell $and $and$ls180.v:5699$1036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5699$1035_Y - connect \Y $and$ls180.v:5699$1036_Y - end - attribute \src "ls180.v:5700.35-5700.79" - cell $and $and$ls180.v:5700$1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5700$1037_Y - connect \Y $and$ls180.v:5700$1038_Y - end - attribute \src "ls180.v:5701.63-5701.107" - cell $and $and$ls180.v:5701$1040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5701$1039_Y - connect \Y $and$ls180.v:5701$1040_Y - end - attribute \src "ls180.v:5702.63-5702.107" - cell $and $and$ls180.v:5702$1042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5702$1041_Y - connect \Y $and$ls180.v:5702$1042_Y - end - attribute \src "ls180.v:5703.63-5703.107" - cell $and $and$ls180.v:5703$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5703$1043_Y - connect \Y $and$ls180.v:5703$1044_Y - end - attribute \src "ls180.v:5704.35-5704.79" - cell $and $and$ls180.v:5704$1046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5704$1045_Y - connect \Y $and$ls180.v:5704$1046_Y - end - attribute \src "ls180.v:5705.35-5705.79" - cell $and $and$ls180.v:5705$1048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5705$1047_Y - connect \Y $and$ls180.v:5705$1048_Y - end - attribute \src "ls180.v:5750.40-5750.81" - cell $and $and$ls180.v:5750$1055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5750$1055_Y - end - attribute \src "ls180.v:5751.50-5751.91" - cell $and $and$ls180.v:5751$1056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5751$1056_Y - end - attribute \src "ls180.v:5752.50-5752.91" - cell $and $and$ls180.v:5752$1057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5752$1057_Y - end - attribute \src "ls180.v:5753.29-5753.70" - cell $and $and$ls180.v:5753$1058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5753$1058_Y - end - attribute \src "ls180.v:5754.44-5754.85" - cell $and $and$ls180.v:5754$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5754$1059_Y - end - attribute \src "ls180.v:5756.25-5756.64" - cell $and $and$ls180.v:5756$1064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_stb - connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5756$1064_Y - end - attribute \src "ls180.v:5756.24-5756.89" - cell $and $and$ls180.v:5756$1066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5756$1064_Y - connect \B $not$ls180.v:5756$1065_Y - connect \Y $and$ls180.v:5756$1066_Y - end - attribute \src "ls180.v:5762.31-5762.92" - cell $and $and$ls180.v:5762$1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } - connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5762$1072_Y - end - attribute \src "ls180.v:5762.97-5762.168" - cell $and $and$ls180.v:5762$1073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_libresocsim_libresoc_xics_icp_dat_r - connect \Y $and$ls180.v:5762$1073_Y - end - attribute \src "ls180.v:5762.174-5762.245" - cell $and $and$ls180.v:5762$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_libresocsim_libresoc_xics_ics_dat_r - connect \Y $and$ls180.v:5762$1075_Y - end - attribute \src "ls180.v:5762.251-5762.301" - cell $and $and$ls180.v:5762$1077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_wb_sdram_dat_r - connect \Y $and$ls180.v:5762$1077_Y - end - attribute \src "ls180.v:5762.307-5762.372" - cell $and $and$ls180.v:5762$1079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \builder_libresocsim_wishbone_dat_r - connect \Y $and$ls180.v:5762$1079_Y - end - attribute \src "ls180.v:5772.39-5772.92" - cell $and $and$ls180.v:5772$1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5772$1083_Y - end - attribute \src "ls180.v:5772.38-5772.142" - cell $and $and$ls180.v:5772$1085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5772$1083_Y - connect \B $eq$ls180.v:5772$1084_Y - connect \Y $and$ls180.v:5772$1085_Y - end - attribute \src "ls180.v:5773.39-5773.95" - cell $and $and$ls180.v:5773$1087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5773$1086_Y - connect \Y $and$ls180.v:5773$1087_Y - end - attribute \src "ls180.v:5773.38-5773.145" - cell $and $and$ls180.v:5773$1089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5773$1087_Y - connect \B $eq$ls180.v:5773$1088_Y - connect \Y $and$ls180.v:5773$1089_Y - end - attribute \src "ls180.v:5775.41-5775.94" - cell $and $and$ls180.v:5775$1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5775$1090_Y - end - attribute \src "ls180.v:5775.40-5775.144" - cell $and $and$ls180.v:5775$1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5775$1090_Y - connect \B $eq$ls180.v:5775$1091_Y - connect \Y $and$ls180.v:5775$1092_Y - end - attribute \src "ls180.v:5776.41-5776.97" - cell $and $and$ls180.v:5776$1094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5776$1093_Y - connect \Y $and$ls180.v:5776$1094_Y - end - attribute \src "ls180.v:5776.40-5776.147" - cell $and $and$ls180.v:5776$1096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5776$1094_Y - connect \B $eq$ls180.v:5776$1095_Y - connect \Y $and$ls180.v:5776$1096_Y - end - attribute \src "ls180.v:5778.41-5778.94" - cell $and $and$ls180.v:5778$1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5778$1097_Y - end - attribute \src "ls180.v:5778.40-5778.144" - cell $and $and$ls180.v:5778$1099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5778$1097_Y - connect \B $eq$ls180.v:5778$1098_Y - connect \Y $and$ls180.v:5778$1099_Y - end - attribute \src "ls180.v:5779.41-5779.97" - cell $and $and$ls180.v:5779$1101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5779$1100_Y - connect \Y $and$ls180.v:5779$1101_Y - end - attribute \src "ls180.v:5779.40-5779.147" - cell $and $and$ls180.v:5779$1103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5779$1101_Y - connect \B $eq$ls180.v:5779$1102_Y - connect \Y $and$ls180.v:5779$1103_Y - end - attribute \src "ls180.v:5781.41-5781.94" - cell $and $and$ls180.v:5781$1104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5781$1104_Y - end - attribute \src "ls180.v:5781.40-5781.144" - cell $and $and$ls180.v:5781$1106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5781$1104_Y - connect \B $eq$ls180.v:5781$1105_Y - connect \Y $and$ls180.v:5781$1106_Y - end - attribute \src "ls180.v:5782.41-5782.97" - cell $and $and$ls180.v:5782$1108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5782$1107_Y - connect \Y $and$ls180.v:5782$1108_Y - end - attribute \src "ls180.v:5782.40-5782.147" - cell $and $and$ls180.v:5782$1110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5782$1108_Y - connect \B $eq$ls180.v:5782$1109_Y - connect \Y $and$ls180.v:5782$1110_Y - end - attribute \src "ls180.v:5784.41-5784.94" - cell $and $and$ls180.v:5784$1111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5784$1111_Y - end - attribute \src "ls180.v:5784.40-5784.144" - cell $and $and$ls180.v:5784$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5784$1111_Y - connect \B $eq$ls180.v:5784$1112_Y - connect \Y $and$ls180.v:5784$1113_Y - end - attribute \src "ls180.v:5785.41-5785.97" - cell $and $and$ls180.v:5785$1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5785$1114_Y - connect \Y $and$ls180.v:5785$1115_Y - end - attribute \src "ls180.v:5785.40-5785.147" - cell $and $and$ls180.v:5785$1117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5785$1115_Y - connect \B $eq$ls180.v:5785$1116_Y - connect \Y $and$ls180.v:5785$1117_Y - end - attribute \src "ls180.v:5787.44-5787.97" - cell $and $and$ls180.v:5787$1118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5787$1118_Y - end - attribute \src "ls180.v:5787.43-5787.147" - cell $and $and$ls180.v:5787$1120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5787$1118_Y - connect \B $eq$ls180.v:5787$1119_Y - connect \Y $and$ls180.v:5787$1120_Y - end - attribute \src "ls180.v:5788.44-5788.100" - cell $and $and$ls180.v:5788$1122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5788$1121_Y - connect \Y $and$ls180.v:5788$1122_Y - end - attribute \src "ls180.v:5788.43-5788.150" - cell $and $and$ls180.v:5788$1124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5788$1122_Y - connect \B $eq$ls180.v:5788$1123_Y - connect \Y $and$ls180.v:5788$1124_Y - end - attribute \src "ls180.v:5790.44-5790.97" - cell $and $and$ls180.v:5790$1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5790$1125_Y - end - attribute \src "ls180.v:5790.43-5790.147" - cell $and $and$ls180.v:5790$1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5790$1125_Y - connect \B $eq$ls180.v:5790$1126_Y - connect \Y $and$ls180.v:5790$1127_Y - end - attribute \src "ls180.v:5791.44-5791.100" - cell $and $and$ls180.v:5791$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5791$1128_Y - connect \Y $and$ls180.v:5791$1129_Y - end - attribute \src "ls180.v:5791.43-5791.150" - cell $and $and$ls180.v:5791$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5791$1129_Y - connect \B $eq$ls180.v:5791$1130_Y - connect \Y $and$ls180.v:5791$1131_Y - end - attribute \src "ls180.v:5793.44-5793.97" - cell $and $and$ls180.v:5793$1132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5793$1132_Y - end - attribute \src "ls180.v:5793.43-5793.147" - cell $and $and$ls180.v:5793$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5793$1132_Y - connect \B $eq$ls180.v:5793$1133_Y - connect \Y $and$ls180.v:5793$1134_Y - end - attribute \src "ls180.v:5794.44-5794.100" - cell $and $and$ls180.v:5794$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5794$1135_Y - connect \Y $and$ls180.v:5794$1136_Y - end - attribute \src "ls180.v:5794.43-5794.150" - cell $and $and$ls180.v:5794$1138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5794$1136_Y - connect \B $eq$ls180.v:5794$1137_Y - connect \Y $and$ls180.v:5794$1138_Y - end - attribute \src "ls180.v:5796.44-5796.97" - cell $and $and$ls180.v:5796$1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5796$1139_Y - end - attribute \src "ls180.v:5796.43-5796.147" - cell $and $and$ls180.v:5796$1141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5796$1139_Y - connect \B $eq$ls180.v:5796$1140_Y - connect \Y $and$ls180.v:5796$1141_Y - end - attribute \src "ls180.v:5797.44-5797.100" - cell $and $and$ls180.v:5797$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5797$1142_Y - connect \Y $and$ls180.v:5797$1143_Y - end - attribute \src "ls180.v:5797.43-5797.150" - cell $and $and$ls180.v:5797$1145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5797$1143_Y - connect \B $eq$ls180.v:5797$1144_Y - connect \Y $and$ls180.v:5797$1145_Y - end - attribute \src "ls180.v:5810.36-5810.89" - cell $and $and$ls180.v:5810$1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5810$1147_Y - end - attribute \src "ls180.v:5810.35-5810.139" - cell $and $and$ls180.v:5810$1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5810$1147_Y - connect \B $eq$ls180.v:5810$1148_Y - connect \Y $and$ls180.v:5810$1149_Y - end - attribute \src "ls180.v:5811.36-5811.92" - cell $and $and$ls180.v:5811$1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5811$1150_Y - connect \Y $and$ls180.v:5811$1151_Y - end - attribute \src "ls180.v:5811.35-5811.142" - cell $and $and$ls180.v:5811$1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5811$1151_Y - connect \B $eq$ls180.v:5811$1152_Y - connect \Y $and$ls180.v:5811$1153_Y - end - attribute \src "ls180.v:5813.36-5813.89" - cell $and $and$ls180.v:5813$1154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5813$1154_Y - end - attribute \src "ls180.v:5813.35-5813.139" - cell $and $and$ls180.v:5813$1156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5813$1154_Y - connect \B $eq$ls180.v:5813$1155_Y - connect \Y $and$ls180.v:5813$1156_Y - end - attribute \src "ls180.v:5814.36-5814.92" - cell $and $and$ls180.v:5814$1158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5814$1157_Y - connect \Y $and$ls180.v:5814$1158_Y - end - attribute \src "ls180.v:5814.35-5814.142" - cell $and $and$ls180.v:5814$1160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5814$1158_Y - connect \B $eq$ls180.v:5814$1159_Y - connect \Y $and$ls180.v:5814$1160_Y - end - attribute \src "ls180.v:5816.36-5816.89" - cell $and $and$ls180.v:5816$1161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5816$1161_Y - end - attribute \src "ls180.v:5816.35-5816.139" - cell $and $and$ls180.v:5816$1163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5816$1161_Y - connect \B $eq$ls180.v:5816$1162_Y - connect \Y $and$ls180.v:5816$1163_Y - end - attribute \src "ls180.v:5817.36-5817.92" - cell $and $and$ls180.v:5817$1165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5817$1164_Y - connect \Y $and$ls180.v:5817$1165_Y - end - attribute \src "ls180.v:5817.35-5817.142" - cell $and $and$ls180.v:5817$1167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5817$1165_Y - connect \B $eq$ls180.v:5817$1166_Y - connect \Y $and$ls180.v:5817$1167_Y - end - attribute \src "ls180.v:5819.36-5819.89" - cell $and $and$ls180.v:5819$1168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5819$1168_Y - end - attribute \src "ls180.v:5819.35-5819.139" - cell $and $and$ls180.v:5819$1170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5819$1168_Y - connect \B $eq$ls180.v:5819$1169_Y - connect \Y $and$ls180.v:5819$1170_Y - end - attribute \src "ls180.v:5820.36-5820.92" - cell $and $and$ls180.v:5820$1172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5820$1171_Y - connect \Y $and$ls180.v:5820$1172_Y - end - attribute \src "ls180.v:5820.35-5820.142" - cell $and $and$ls180.v:5820$1174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5820$1172_Y - connect \B $eq$ls180.v:5820$1173_Y - connect \Y $and$ls180.v:5820$1174_Y - end - attribute \src "ls180.v:5822.37-5822.90" - cell $and $and$ls180.v:5822$1175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5822$1175_Y - end - attribute \src "ls180.v:5822.36-5822.140" - cell $and $and$ls180.v:5822$1177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5822$1175_Y - connect \B $eq$ls180.v:5822$1176_Y - connect \Y $and$ls180.v:5822$1177_Y - end - attribute \src "ls180.v:5823.37-5823.93" - cell $and $and$ls180.v:5823$1179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5823$1178_Y - connect \Y $and$ls180.v:5823$1179_Y - end - attribute \src "ls180.v:5823.36-5823.143" - cell $and $and$ls180.v:5823$1181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5823$1179_Y - connect \B $eq$ls180.v:5823$1180_Y - connect \Y $and$ls180.v:5823$1181_Y - end - attribute \src "ls180.v:5825.37-5825.90" - cell $and $and$ls180.v:5825$1182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5825$1182_Y - end - attribute \src "ls180.v:5825.36-5825.140" - cell $and $and$ls180.v:5825$1184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5825$1182_Y - connect \B $eq$ls180.v:5825$1183_Y - connect \Y $and$ls180.v:5825$1184_Y - end - attribute \src "ls180.v:5826.37-5826.93" - cell $and $and$ls180.v:5826$1186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5826$1185_Y - connect \Y $and$ls180.v:5826$1186_Y - end - attribute \src "ls180.v:5826.36-5826.143" - cell $and $and$ls180.v:5826$1188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5826$1186_Y - connect \B $eq$ls180.v:5826$1187_Y - connect \Y $and$ls180.v:5826$1188_Y - end - attribute \src "ls180.v:5836.35-5836.88" - cell $and $and$ls180.v:5836$1190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5836$1190_Y - end - attribute \src "ls180.v:5836.34-5836.136" - cell $and $and$ls180.v:5836$1192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5836$1190_Y - connect \B $eq$ls180.v:5836$1191_Y - connect \Y $and$ls180.v:5836$1192_Y - end - attribute \src "ls180.v:5837.35-5837.91" - cell $and $and$ls180.v:5837$1194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5837$1193_Y - connect \Y $and$ls180.v:5837$1194_Y - end - attribute \src "ls180.v:5837.34-5837.139" - cell $and $and$ls180.v:5837$1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5837$1194_Y - connect \B $eq$ls180.v:5837$1195_Y - connect \Y $and$ls180.v:5837$1196_Y - end - attribute \src "ls180.v:5839.34-5839.87" - cell $and $and$ls180.v:5839$1197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5839$1197_Y - end - attribute \src "ls180.v:5839.33-5839.135" - cell $and $and$ls180.v:5839$1199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5839$1197_Y - connect \B $eq$ls180.v:5839$1198_Y - connect \Y $and$ls180.v:5839$1199_Y - end - attribute \src "ls180.v:5840.34-5840.90" - cell $and $and$ls180.v:5840$1201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5840$1200_Y - connect \Y $and$ls180.v:5840$1201_Y - end - attribute \src "ls180.v:5840.33-5840.138" - cell $and $and$ls180.v:5840$1203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5840$1201_Y - connect \B $eq$ls180.v:5840$1202_Y - connect \Y $and$ls180.v:5840$1203_Y - end - attribute \src "ls180.v:5850.40-5850.93" - cell $and $and$ls180.v:5850$1205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5850$1205_Y - end - attribute \src "ls180.v:5850.39-5850.143" - cell $and $and$ls180.v:5850$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5850$1205_Y - connect \B $eq$ls180.v:5850$1206_Y - connect \Y $and$ls180.v:5850$1207_Y - end - attribute \src "ls180.v:5851.40-5851.96" - cell $and $and$ls180.v:5851$1209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5851$1208_Y - connect \Y $and$ls180.v:5851$1209_Y - end - attribute \src "ls180.v:5851.39-5851.146" - cell $and $and$ls180.v:5851$1211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5851$1209_Y - connect \B $eq$ls180.v:5851$1210_Y - connect \Y $and$ls180.v:5851$1211_Y - end - attribute \src "ls180.v:5853.39-5853.92" - cell $and $and$ls180.v:5853$1212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5853$1212_Y - end - attribute \src "ls180.v:5853.38-5853.142" - cell $and $and$ls180.v:5853$1214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5853$1212_Y - connect \B $eq$ls180.v:5853$1213_Y - connect \Y $and$ls180.v:5853$1214_Y - end - attribute \src "ls180.v:5854.39-5854.95" - cell $and $and$ls180.v:5854$1216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5854$1215_Y - connect \Y $and$ls180.v:5854$1216_Y - end - attribute \src "ls180.v:5854.38-5854.145" - cell $and $and$ls180.v:5854$1218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5854$1216_Y - connect \B $eq$ls180.v:5854$1217_Y - connect \Y $and$ls180.v:5854$1218_Y - end - attribute \src "ls180.v:5856.39-5856.92" - cell $and $and$ls180.v:5856$1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5856$1219_Y - end - attribute \src "ls180.v:5856.38-5856.142" - cell $and $and$ls180.v:5856$1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5856$1219_Y - connect \B $eq$ls180.v:5856$1220_Y - connect \Y $and$ls180.v:5856$1221_Y - end - attribute \src "ls180.v:5857.39-5857.95" - cell $and $and$ls180.v:5857$1223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5857$1222_Y - connect \Y $and$ls180.v:5857$1223_Y - end - attribute \src "ls180.v:5857.38-5857.145" - cell $and $and$ls180.v:5857$1225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5857$1223_Y - connect \B $eq$ls180.v:5857$1224_Y - connect \Y $and$ls180.v:5857$1225_Y - end - attribute \src "ls180.v:5859.39-5859.92" - cell $and $and$ls180.v:5859$1226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5859$1226_Y - end - attribute \src "ls180.v:5859.38-5859.142" - cell $and $and$ls180.v:5859$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5859$1226_Y - connect \B $eq$ls180.v:5859$1227_Y - connect \Y $and$ls180.v:5859$1228_Y - end - attribute \src "ls180.v:5860.39-5860.95" - cell $and $and$ls180.v:5860$1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5860$1229_Y - connect \Y $and$ls180.v:5860$1230_Y - end - attribute \src "ls180.v:5860.38-5860.145" - cell $and $and$ls180.v:5860$1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5860$1230_Y - connect \B $eq$ls180.v:5860$1231_Y - connect \Y $and$ls180.v:5860$1232_Y - end - attribute \src "ls180.v:5862.39-5862.92" - cell $and $and$ls180.v:5862$1233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5862$1233_Y - end - attribute \src "ls180.v:5862.38-5862.142" - cell $and $and$ls180.v:5862$1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5862$1233_Y - connect \B $eq$ls180.v:5862$1234_Y - connect \Y $and$ls180.v:5862$1235_Y - end - attribute \src "ls180.v:5863.39-5863.95" - cell $and $and$ls180.v:5863$1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5863$1236_Y - connect \Y $and$ls180.v:5863$1237_Y - end - attribute \src "ls180.v:5863.38-5863.145" - cell $and $and$ls180.v:5863$1239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5863$1237_Y - connect \B $eq$ls180.v:5863$1238_Y - connect \Y $and$ls180.v:5863$1239_Y - end - attribute \src "ls180.v:5865.40-5865.93" - cell $and $and$ls180.v:5865$1240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5865$1240_Y - end - attribute \src "ls180.v:5865.39-5865.143" - cell $and $and$ls180.v:5865$1242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5865$1240_Y - connect \B $eq$ls180.v:5865$1241_Y - connect \Y $and$ls180.v:5865$1242_Y - end - attribute \src "ls180.v:5866.40-5866.96" - cell $and $and$ls180.v:5866$1244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5866$1243_Y - connect \Y $and$ls180.v:5866$1244_Y - end - attribute \src "ls180.v:5866.39-5866.146" - cell $and $and$ls180.v:5866$1246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5866$1244_Y - connect \B $eq$ls180.v:5866$1245_Y - connect \Y $and$ls180.v:5866$1246_Y - end - attribute \src "ls180.v:5868.40-5868.93" - cell $and $and$ls180.v:5868$1247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5868$1247_Y - end - attribute \src "ls180.v:5868.39-5868.143" - cell $and $and$ls180.v:5868$1249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5868$1247_Y - connect \B $eq$ls180.v:5868$1248_Y - connect \Y $and$ls180.v:5868$1249_Y - end - attribute \src "ls180.v:5869.40-5869.96" - cell $and $and$ls180.v:5869$1251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5869$1250_Y - connect \Y $and$ls180.v:5869$1251_Y - end - attribute \src "ls180.v:5869.39-5869.146" - cell $and $and$ls180.v:5869$1253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5869$1251_Y - connect \B $eq$ls180.v:5869$1252_Y - connect \Y $and$ls180.v:5869$1253_Y - end - attribute \src "ls180.v:5871.40-5871.93" - cell $and $and$ls180.v:5871$1254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5871$1254_Y - end - attribute \src "ls180.v:5871.39-5871.143" - cell $and $and$ls180.v:5871$1256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5871$1254_Y - connect \B $eq$ls180.v:5871$1255_Y - connect \Y $and$ls180.v:5871$1256_Y - end - attribute \src "ls180.v:5872.40-5872.96" - cell $and $and$ls180.v:5872$1258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5872$1257_Y - connect \Y $and$ls180.v:5872$1258_Y - end - attribute \src "ls180.v:5872.39-5872.146" - cell $and $and$ls180.v:5872$1260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5872$1258_Y - connect \B $eq$ls180.v:5872$1259_Y - connect \Y $and$ls180.v:5872$1260_Y - end - attribute \src "ls180.v:5874.40-5874.93" - cell $and $and$ls180.v:5874$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5874$1261_Y - end - attribute \src "ls180.v:5874.39-5874.143" - cell $and $and$ls180.v:5874$1263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1261_Y - connect \B $eq$ls180.v:5874$1262_Y - connect \Y $and$ls180.v:5874$1263_Y - end - attribute \src "ls180.v:5875.40-5875.96" - cell $and $and$ls180.v:5875$1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5875$1264_Y - connect \Y $and$ls180.v:5875$1265_Y - end - attribute \src "ls180.v:5875.39-5875.146" - cell $and $and$ls180.v:5875$1267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5875$1265_Y - connect \B $eq$ls180.v:5875$1266_Y - connect \Y $and$ls180.v:5875$1267_Y - end - attribute \src "ls180.v:5887.40-5887.93" - cell $and $and$ls180.v:5887$1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5887$1269_Y - end - attribute \src "ls180.v:5887.39-5887.143" - cell $and $and$ls180.v:5887$1271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5887$1269_Y - connect \B $eq$ls180.v:5887$1270_Y - connect \Y $and$ls180.v:5887$1271_Y - end - attribute \src "ls180.v:5888.40-5888.96" - cell $and $and$ls180.v:5888$1273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5888$1272_Y - connect \Y $and$ls180.v:5888$1273_Y - end - attribute \src "ls180.v:5888.39-5888.146" - cell $and $and$ls180.v:5888$1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5888$1273_Y - connect \B $eq$ls180.v:5888$1274_Y - connect \Y $and$ls180.v:5888$1275_Y - end - attribute \src "ls180.v:5890.39-5890.92" - cell $and $and$ls180.v:5890$1276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5890$1276_Y - end - attribute \src "ls180.v:5890.38-5890.142" - cell $and $and$ls180.v:5890$1278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5890$1276_Y - connect \B $eq$ls180.v:5890$1277_Y - connect \Y $and$ls180.v:5890$1278_Y - end - attribute \src "ls180.v:5891.39-5891.95" - cell $and $and$ls180.v:5891$1280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5891$1279_Y - connect \Y $and$ls180.v:5891$1280_Y - end - attribute \src "ls180.v:5891.38-5891.145" - cell $and $and$ls180.v:5891$1282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5891$1280_Y - connect \B $eq$ls180.v:5891$1281_Y - connect \Y $and$ls180.v:5891$1282_Y - end - attribute \src "ls180.v:5893.39-5893.92" - cell $and $and$ls180.v:5893$1283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5893$1283_Y - end - attribute \src "ls180.v:5893.38-5893.142" - cell $and $and$ls180.v:5893$1285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5893$1283_Y - connect \B $eq$ls180.v:5893$1284_Y - connect \Y $and$ls180.v:5893$1285_Y - end - attribute \src "ls180.v:5894.39-5894.95" - cell $and $and$ls180.v:5894$1287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5894$1286_Y - connect \Y $and$ls180.v:5894$1287_Y - end - attribute \src "ls180.v:5894.38-5894.145" - cell $and $and$ls180.v:5894$1289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5894$1287_Y - connect \B $eq$ls180.v:5894$1288_Y - connect \Y $and$ls180.v:5894$1289_Y - end - attribute \src "ls180.v:5896.39-5896.92" - cell $and $and$ls180.v:5896$1290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5896$1290_Y - end - attribute \src "ls180.v:5896.38-5896.142" - cell $and $and$ls180.v:5896$1292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5896$1290_Y - connect \B $eq$ls180.v:5896$1291_Y - connect \Y $and$ls180.v:5896$1292_Y - end - attribute \src "ls180.v:5897.39-5897.95" - cell $and $and$ls180.v:5897$1294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5897$1293_Y - connect \Y $and$ls180.v:5897$1294_Y - end - attribute \src "ls180.v:5897.38-5897.145" - cell $and $and$ls180.v:5897$1296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5897$1294_Y - connect \B $eq$ls180.v:5897$1295_Y - connect \Y $and$ls180.v:5897$1296_Y - end - attribute \src "ls180.v:5899.39-5899.92" - cell $and $and$ls180.v:5899$1297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5899$1297_Y - end - attribute \src "ls180.v:5899.38-5899.142" - cell $and $and$ls180.v:5899$1299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5899$1297_Y - connect \B $eq$ls180.v:5899$1298_Y - connect \Y $and$ls180.v:5899$1299_Y - end - attribute \src "ls180.v:5900.39-5900.95" - cell $and $and$ls180.v:5900$1301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5900$1300_Y - connect \Y $and$ls180.v:5900$1301_Y - end - attribute \src "ls180.v:5900.38-5900.145" - cell $and $and$ls180.v:5900$1303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5900$1301_Y - connect \B $eq$ls180.v:5900$1302_Y - connect \Y $and$ls180.v:5900$1303_Y - end - attribute \src "ls180.v:5902.40-5902.93" - cell $and $and$ls180.v:5902$1304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5902$1304_Y - end - attribute \src "ls180.v:5902.39-5902.143" - cell $and $and$ls180.v:5902$1306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5902$1304_Y - connect \B $eq$ls180.v:5902$1305_Y - connect \Y $and$ls180.v:5902$1306_Y - end - attribute \src "ls180.v:5903.40-5903.96" - cell $and $and$ls180.v:5903$1308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5903$1307_Y - connect \Y $and$ls180.v:5903$1308_Y - end - attribute \src "ls180.v:5903.39-5903.146" - cell $and $and$ls180.v:5903$1310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5903$1308_Y - connect \B $eq$ls180.v:5903$1309_Y - connect \Y $and$ls180.v:5903$1310_Y - end - attribute \src "ls180.v:5905.40-5905.93" - cell $and $and$ls180.v:5905$1311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5905$1311_Y - end - attribute \src "ls180.v:5905.39-5905.143" - cell $and $and$ls180.v:5905$1313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5905$1311_Y - connect \B $eq$ls180.v:5905$1312_Y - connect \Y $and$ls180.v:5905$1313_Y - end - attribute \src "ls180.v:5906.40-5906.96" - cell $and $and$ls180.v:5906$1315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5906$1314_Y - connect \Y $and$ls180.v:5906$1315_Y - end - attribute \src "ls180.v:5906.39-5906.146" - cell $and $and$ls180.v:5906$1317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5906$1315_Y - connect \B $eq$ls180.v:5906$1316_Y - connect \Y $and$ls180.v:5906$1317_Y - end - attribute \src "ls180.v:5908.40-5908.93" - cell $and $and$ls180.v:5908$1318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5908$1318_Y - end - attribute \src "ls180.v:5908.39-5908.143" - cell $and $and$ls180.v:5908$1320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5908$1318_Y - connect \B $eq$ls180.v:5908$1319_Y - connect \Y $and$ls180.v:5908$1320_Y - end - attribute \src "ls180.v:5909.40-5909.96" - cell $and $and$ls180.v:5909$1322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5909$1321_Y - connect \Y $and$ls180.v:5909$1322_Y - end - attribute \src "ls180.v:5909.39-5909.146" - cell $and $and$ls180.v:5909$1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5909$1322_Y - connect \B $eq$ls180.v:5909$1323_Y - connect \Y $and$ls180.v:5909$1324_Y - end - attribute \src "ls180.v:5911.40-5911.93" - cell $and $and$ls180.v:5911$1325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5911$1325_Y - end - attribute \src "ls180.v:5911.39-5911.143" - cell $and $and$ls180.v:5911$1327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5911$1325_Y - connect \B $eq$ls180.v:5911$1326_Y - connect \Y $and$ls180.v:5911$1327_Y - end - attribute \src "ls180.v:5912.40-5912.96" - cell $and $and$ls180.v:5912$1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5912$1328_Y - connect \Y $and$ls180.v:5912$1329_Y - end - attribute \src "ls180.v:5912.39-5912.146" - cell $and $and$ls180.v:5912$1331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5912$1329_Y - connect \B $eq$ls180.v:5912$1330_Y - connect \Y $and$ls180.v:5912$1331_Y - end - attribute \src "ls180.v:5924.42-5924.95" - cell $and $and$ls180.v:5924$1333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5924$1333_Y - end - attribute \src "ls180.v:5924.41-5924.145" - cell $and $and$ls180.v:5924$1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5924$1333_Y - connect \B $eq$ls180.v:5924$1334_Y - connect \Y $and$ls180.v:5924$1335_Y - end - attribute \src "ls180.v:5925.42-5925.98" - cell $and $and$ls180.v:5925$1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5925$1336_Y - connect \Y $and$ls180.v:5925$1337_Y - end - attribute \src "ls180.v:5925.41-5925.148" - cell $and $and$ls180.v:5925$1339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5925$1337_Y - connect \B $eq$ls180.v:5925$1338_Y - connect \Y $and$ls180.v:5925$1339_Y - end - attribute \src "ls180.v:5927.42-5927.95" - cell $and $and$ls180.v:5927$1340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5927$1340_Y - end - attribute \src "ls180.v:5927.41-5927.145" - cell $and $and$ls180.v:5927$1342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5927$1340_Y - connect \B $eq$ls180.v:5927$1341_Y - connect \Y $and$ls180.v:5927$1342_Y - end - attribute \src "ls180.v:5928.42-5928.98" - cell $and $and$ls180.v:5928$1344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5928$1343_Y - connect \Y $and$ls180.v:5928$1344_Y - end - attribute \src "ls180.v:5928.41-5928.148" - cell $and $and$ls180.v:5928$1346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5928$1344_Y - connect \B $eq$ls180.v:5928$1345_Y - connect \Y $and$ls180.v:5928$1346_Y - end - attribute \src "ls180.v:5930.42-5930.95" - cell $and $and$ls180.v:5930$1347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5930$1347_Y - end - attribute \src "ls180.v:5930.41-5930.145" - cell $and $and$ls180.v:5930$1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5930$1347_Y - connect \B $eq$ls180.v:5930$1348_Y - connect \Y $and$ls180.v:5930$1349_Y - end - attribute \src "ls180.v:5931.42-5931.98" - cell $and $and$ls180.v:5931$1351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5931$1350_Y - connect \Y $and$ls180.v:5931$1351_Y - end - attribute \src "ls180.v:5931.41-5931.148" - cell $and $and$ls180.v:5931$1353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5931$1351_Y - connect \B $eq$ls180.v:5931$1352_Y - connect \Y $and$ls180.v:5931$1353_Y - end - attribute \src "ls180.v:5933.42-5933.95" - cell $and $and$ls180.v:5933$1354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5933$1354_Y - end - attribute \src "ls180.v:5933.41-5933.145" - cell $and $and$ls180.v:5933$1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5933$1354_Y - connect \B $eq$ls180.v:5933$1355_Y - connect \Y $and$ls180.v:5933$1356_Y - end - attribute \src "ls180.v:5934.42-5934.98" - cell $and $and$ls180.v:5934$1358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5934$1357_Y - connect \Y $and$ls180.v:5934$1358_Y - end - attribute \src "ls180.v:5934.41-5934.148" - cell $and $and$ls180.v:5934$1360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5934$1358_Y - connect \B $eq$ls180.v:5934$1359_Y - connect \Y $and$ls180.v:5934$1360_Y - end - attribute \src "ls180.v:5936.42-5936.95" - cell $and $and$ls180.v:5936$1361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5936$1361_Y - end - attribute \src "ls180.v:5936.41-5936.145" - cell $and $and$ls180.v:5936$1363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5936$1361_Y - connect \B $eq$ls180.v:5936$1362_Y - connect \Y $and$ls180.v:5936$1363_Y - end - attribute \src "ls180.v:5937.42-5937.98" - cell $and $and$ls180.v:5937$1365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5937$1364_Y - connect \Y $and$ls180.v:5937$1365_Y - end - attribute \src "ls180.v:5937.41-5937.148" - cell $and $and$ls180.v:5937$1367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5937$1365_Y - connect \B $eq$ls180.v:5937$1366_Y - connect \Y $and$ls180.v:5937$1367_Y - end - attribute \src "ls180.v:5939.42-5939.95" - cell $and $and$ls180.v:5939$1368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5939$1368_Y - end - attribute \src "ls180.v:5939.41-5939.145" - cell $and $and$ls180.v:5939$1370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5939$1368_Y - connect \B $eq$ls180.v:5939$1369_Y - connect \Y $and$ls180.v:5939$1370_Y - end - attribute \src "ls180.v:5940.42-5940.98" - cell $and $and$ls180.v:5940$1372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5940$1371_Y - connect \Y $and$ls180.v:5940$1372_Y - end - attribute \src "ls180.v:5940.41-5940.148" - cell $and $and$ls180.v:5940$1374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5940$1372_Y - connect \B $eq$ls180.v:5940$1373_Y - connect \Y $and$ls180.v:5940$1374_Y - end - attribute \src "ls180.v:5942.42-5942.95" - cell $and $and$ls180.v:5942$1375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5942$1375_Y - end - attribute \src "ls180.v:5942.41-5942.145" - cell $and $and$ls180.v:5942$1377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5942$1375_Y - connect \B $eq$ls180.v:5942$1376_Y - connect \Y $and$ls180.v:5942$1377_Y - end - attribute \src "ls180.v:5943.42-5943.98" - cell $and $and$ls180.v:5943$1379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5943$1378_Y - connect \Y $and$ls180.v:5943$1379_Y - end - attribute \src "ls180.v:5943.41-5943.148" - cell $and $and$ls180.v:5943$1381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5943$1379_Y - connect \B $eq$ls180.v:5943$1380_Y - connect \Y $and$ls180.v:5943$1381_Y - end - attribute \src "ls180.v:5945.42-5945.95" - cell $and $and$ls180.v:5945$1382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5945$1382_Y - end - attribute \src "ls180.v:5945.41-5945.145" - cell $and $and$ls180.v:5945$1384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5945$1382_Y - connect \B $eq$ls180.v:5945$1383_Y - connect \Y $and$ls180.v:5945$1384_Y - end - attribute \src "ls180.v:5946.42-5946.98" - cell $and $and$ls180.v:5946$1386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5946$1385_Y - connect \Y $and$ls180.v:5946$1386_Y - end - attribute \src "ls180.v:5946.41-5946.148" - cell $and $and$ls180.v:5946$1388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5946$1386_Y - connect \B $eq$ls180.v:5946$1387_Y - connect \Y $and$ls180.v:5946$1388_Y - end - attribute \src "ls180.v:5948.44-5948.97" - cell $and $and$ls180.v:5948$1389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5948$1389_Y - end - attribute \src "ls180.v:5948.43-5948.147" - cell $and $and$ls180.v:5948$1391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5948$1389_Y - connect \B $eq$ls180.v:5948$1390_Y - connect \Y $and$ls180.v:5948$1391_Y - end - attribute \src "ls180.v:5949.44-5949.100" - cell $and $and$ls180.v:5949$1393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5949$1392_Y - connect \Y $and$ls180.v:5949$1393_Y - end - attribute \src "ls180.v:5949.43-5949.150" - cell $and $and$ls180.v:5949$1395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5949$1393_Y - connect \B $eq$ls180.v:5949$1394_Y - connect \Y $and$ls180.v:5949$1395_Y - end - attribute \src "ls180.v:5951.44-5951.97" - cell $and $and$ls180.v:5951$1396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5951$1396_Y - end - attribute \src "ls180.v:5951.43-5951.147" - cell $and $and$ls180.v:5951$1398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5951$1396_Y - connect \B $eq$ls180.v:5951$1397_Y - connect \Y $and$ls180.v:5951$1398_Y - end - attribute \src "ls180.v:5952.44-5952.100" - cell $and $and$ls180.v:5952$1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5952$1399_Y - connect \Y $and$ls180.v:5952$1400_Y - end - attribute \src "ls180.v:5952.43-5952.150" - cell $and $and$ls180.v:5952$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5952$1400_Y - connect \B $eq$ls180.v:5952$1401_Y - connect \Y $and$ls180.v:5952$1402_Y - end - attribute \src "ls180.v:5954.44-5954.97" - cell $and $and$ls180.v:5954$1403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5954$1403_Y - end - attribute \src "ls180.v:5954.43-5954.148" - cell $and $and$ls180.v:5954$1405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1403_Y - connect \B $eq$ls180.v:5954$1404_Y - connect \Y $and$ls180.v:5954$1405_Y - end - attribute \src "ls180.v:5955.44-5955.100" - cell $and $and$ls180.v:5955$1407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5955$1406_Y - connect \Y $and$ls180.v:5955$1407_Y - end - attribute \src "ls180.v:5955.43-5955.151" - cell $and $and$ls180.v:5955$1409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5955$1407_Y - connect \B $eq$ls180.v:5955$1408_Y - connect \Y $and$ls180.v:5955$1409_Y - end - attribute \src "ls180.v:5957.44-5957.97" - cell $and $and$ls180.v:5957$1410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5957$1410_Y - end - attribute \src "ls180.v:5957.43-5957.148" - cell $and $and$ls180.v:5957$1412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5957$1410_Y - connect \B $eq$ls180.v:5957$1411_Y - connect \Y $and$ls180.v:5957$1412_Y - end - attribute \src "ls180.v:5958.44-5958.100" - cell $and $and$ls180.v:5958$1414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5958$1413_Y - connect \Y $and$ls180.v:5958$1414_Y - end - attribute \src "ls180.v:5958.43-5958.151" - cell $and $and$ls180.v:5958$1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5958$1414_Y - connect \B $eq$ls180.v:5958$1415_Y - connect \Y $and$ls180.v:5958$1416_Y - end - attribute \src "ls180.v:5960.44-5960.97" - cell $and $and$ls180.v:5960$1417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5960$1417_Y - end - attribute \src "ls180.v:5960.43-5960.148" - cell $and $and$ls180.v:5960$1419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5960$1417_Y - connect \B $eq$ls180.v:5960$1418_Y - connect \Y $and$ls180.v:5960$1419_Y - end - attribute \src "ls180.v:5961.44-5961.100" - cell $and $and$ls180.v:5961$1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5961$1420_Y - connect \Y $and$ls180.v:5961$1421_Y - end - attribute \src "ls180.v:5961.43-5961.151" - cell $and $and$ls180.v:5961$1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5961$1421_Y - connect \B $eq$ls180.v:5961$1422_Y - connect \Y $and$ls180.v:5961$1423_Y - end - attribute \src "ls180.v:5963.41-5963.94" - cell $and $and$ls180.v:5963$1424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5963$1424_Y - end - attribute \src "ls180.v:5963.40-5963.145" - cell $and $and$ls180.v:5963$1426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5963$1424_Y - connect \B $eq$ls180.v:5963$1425_Y - connect \Y $and$ls180.v:5963$1426_Y - end - attribute \src "ls180.v:5964.41-5964.97" - cell $and $and$ls180.v:5964$1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5964$1427_Y - connect \Y $and$ls180.v:5964$1428_Y - end - attribute \src "ls180.v:5964.40-5964.148" - cell $and $and$ls180.v:5964$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5964$1428_Y - connect \B $eq$ls180.v:5964$1429_Y - connect \Y $and$ls180.v:5964$1430_Y - end - attribute \src "ls180.v:5966.42-5966.95" - cell $and $and$ls180.v:5966$1431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:5966$1431_Y - end - attribute \src "ls180.v:5966.41-5966.146" - cell $and $and$ls180.v:5966$1433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5966$1431_Y - connect \B $eq$ls180.v:5966$1432_Y - connect \Y $and$ls180.v:5966$1433_Y - end - attribute \src "ls180.v:5967.42-5967.98" - cell $and $and$ls180.v:5967$1435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:5967$1434_Y - connect \Y $and$ls180.v:5967$1435_Y - end - attribute \src "ls180.v:5967.41-5967.149" - cell $and $and$ls180.v:5967$1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5967$1435_Y - connect \B $eq$ls180.v:5967$1436_Y - connect \Y $and$ls180.v:5967$1437_Y - end - attribute \src "ls180.v:5986.46-5986.99" - cell $and $and$ls180.v:5986$1439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5986$1439_Y - end - attribute \src "ls180.v:5986.45-5986.149" - cell $and $and$ls180.v:5986$1441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5986$1439_Y - connect \B $eq$ls180.v:5986$1440_Y - connect \Y $and$ls180.v:5986$1441_Y - end - attribute \src "ls180.v:5987.46-5987.102" - cell $and $and$ls180.v:5987$1443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5987$1442_Y - connect \Y $and$ls180.v:5987$1443_Y - end - attribute \src "ls180.v:5987.45-5987.152" - cell $and $and$ls180.v:5987$1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5987$1443_Y - connect \B $eq$ls180.v:5987$1444_Y - connect \Y $and$ls180.v:5987$1445_Y - end - attribute \src "ls180.v:5989.46-5989.99" - cell $and $and$ls180.v:5989$1446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5989$1446_Y - end - attribute \src "ls180.v:5989.45-5989.149" - cell $and $and$ls180.v:5989$1448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5989$1446_Y - connect \B $eq$ls180.v:5989$1447_Y - connect \Y $and$ls180.v:5989$1448_Y - end - attribute \src "ls180.v:5990.46-5990.102" - cell $and $and$ls180.v:5990$1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5990$1449_Y - connect \Y $and$ls180.v:5990$1450_Y - end - attribute \src "ls180.v:5990.45-5990.152" - cell $and $and$ls180.v:5990$1452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5990$1450_Y - connect \B $eq$ls180.v:5990$1451_Y - connect \Y $and$ls180.v:5990$1452_Y - end - attribute \src "ls180.v:5992.46-5992.99" - cell $and $and$ls180.v:5992$1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5992$1453_Y - end - attribute \src "ls180.v:5992.45-5992.149" - cell $and $and$ls180.v:5992$1455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5992$1453_Y - connect \B $eq$ls180.v:5992$1454_Y - connect \Y $and$ls180.v:5992$1455_Y - end - attribute \src "ls180.v:5993.46-5993.102" - cell $and $and$ls180.v:5993$1457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5993$1456_Y - connect \Y $and$ls180.v:5993$1457_Y - end - attribute \src "ls180.v:5993.45-5993.152" - cell $and $and$ls180.v:5993$1459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5993$1457_Y - connect \B $eq$ls180.v:5993$1458_Y - connect \Y $and$ls180.v:5993$1459_Y - end - attribute \src "ls180.v:5995.46-5995.99" - cell $and $and$ls180.v:5995$1460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5995$1460_Y - end - attribute \src "ls180.v:5995.45-5995.149" - cell $and $and$ls180.v:5995$1462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5995$1460_Y - connect \B $eq$ls180.v:5995$1461_Y - connect \Y $and$ls180.v:5995$1462_Y - end - attribute \src "ls180.v:5996.46-5996.102" - cell $and $and$ls180.v:5996$1464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5996$1463_Y - connect \Y $and$ls180.v:5996$1464_Y - end - attribute \src "ls180.v:5996.45-5996.152" - cell $and $and$ls180.v:5996$1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5996$1464_Y - connect \B $eq$ls180.v:5996$1465_Y - connect \Y $and$ls180.v:5996$1466_Y - end - attribute \src "ls180.v:5998.45-5998.98" - cell $and $and$ls180.v:5998$1467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:5998$1467_Y - end - attribute \src "ls180.v:5998.44-5998.148" - cell $and $and$ls180.v:5998$1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5998$1467_Y - connect \B $eq$ls180.v:5998$1468_Y - connect \Y $and$ls180.v:5998$1469_Y - end - attribute \src "ls180.v:5999.45-5999.101" - cell $and $and$ls180.v:5999$1471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:5999$1470_Y - connect \Y $and$ls180.v:5999$1471_Y - end - attribute \src "ls180.v:5999.44-5999.151" - cell $and $and$ls180.v:5999$1473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5999$1471_Y - connect \B $eq$ls180.v:5999$1472_Y - connect \Y $and$ls180.v:5999$1473_Y - end - attribute \src "ls180.v:6001.45-6001.98" - cell $and $and$ls180.v:6001$1474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6001$1474_Y - end - attribute \src "ls180.v:6001.44-6001.148" - cell $and $and$ls180.v:6001$1476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6001$1474_Y - connect \B $eq$ls180.v:6001$1475_Y - connect \Y $and$ls180.v:6001$1476_Y - end - attribute \src "ls180.v:6002.45-6002.101" - cell $and $and$ls180.v:6002$1478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6002$1477_Y - connect \Y $and$ls180.v:6002$1478_Y - end - attribute \src "ls180.v:6002.44-6002.151" - cell $and $and$ls180.v:6002$1480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6002$1478_Y - connect \B $eq$ls180.v:6002$1479_Y - connect \Y $and$ls180.v:6002$1480_Y - end - attribute \src "ls180.v:6004.45-6004.98" - cell $and $and$ls180.v:6004$1481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6004$1481_Y - end - attribute \src "ls180.v:6004.44-6004.148" - cell $and $and$ls180.v:6004$1483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6004$1481_Y - connect \B $eq$ls180.v:6004$1482_Y - connect \Y $and$ls180.v:6004$1483_Y - end - attribute \src "ls180.v:6005.45-6005.101" - cell $and $and$ls180.v:6005$1485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6005$1484_Y - connect \Y $and$ls180.v:6005$1485_Y - end - attribute \src "ls180.v:6005.44-6005.151" - cell $and $and$ls180.v:6005$1487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6005$1485_Y - connect \B $eq$ls180.v:6005$1486_Y - connect \Y $and$ls180.v:6005$1487_Y - end - attribute \src "ls180.v:6007.45-6007.98" - cell $and $and$ls180.v:6007$1488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6007$1488_Y - end - attribute \src "ls180.v:6007.44-6007.148" - cell $and $and$ls180.v:6007$1490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6007$1488_Y - connect \B $eq$ls180.v:6007$1489_Y - connect \Y $and$ls180.v:6007$1490_Y - end - attribute \src "ls180.v:6008.45-6008.101" - cell $and $and$ls180.v:6008$1492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6008$1491_Y - connect \Y $and$ls180.v:6008$1492_Y - end - attribute \src "ls180.v:6008.44-6008.151" - cell $and $and$ls180.v:6008$1494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6008$1492_Y - connect \B $eq$ls180.v:6008$1493_Y - connect \Y $and$ls180.v:6008$1494_Y - end - attribute \src "ls180.v:6010.36-6010.89" - cell $and $and$ls180.v:6010$1495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6010$1495_Y - end - attribute \src "ls180.v:6010.35-6010.139" - cell $and $and$ls180.v:6010$1497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6010$1495_Y - connect \B $eq$ls180.v:6010$1496_Y - connect \Y $and$ls180.v:6010$1497_Y - end - attribute \src "ls180.v:6011.36-6011.92" - cell $and $and$ls180.v:6011$1499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6011$1498_Y - connect \Y $and$ls180.v:6011$1499_Y - end - attribute \src "ls180.v:6011.35-6011.142" - cell $and $and$ls180.v:6011$1501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6011$1499_Y - connect \B $eq$ls180.v:6011$1500_Y - connect \Y $and$ls180.v:6011$1501_Y - end - attribute \src "ls180.v:6013.47-6013.100" - cell $and $and$ls180.v:6013$1502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6013$1502_Y - end - attribute \src "ls180.v:6013.46-6013.150" - cell $and $and$ls180.v:6013$1504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6013$1502_Y - connect \B $eq$ls180.v:6013$1503_Y - connect \Y $and$ls180.v:6013$1504_Y - end - attribute \src "ls180.v:6014.47-6014.103" - cell $and $and$ls180.v:6014$1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6014$1505_Y - connect \Y $and$ls180.v:6014$1506_Y - end - attribute \src "ls180.v:6014.46-6014.153" - cell $and $and$ls180.v:6014$1508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6014$1506_Y - connect \B $eq$ls180.v:6014$1507_Y - connect \Y $and$ls180.v:6014$1508_Y - end - attribute \src "ls180.v:6016.47-6016.100" - cell $and $and$ls180.v:6016$1509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6016$1509_Y - end - attribute \src "ls180.v:6016.46-6016.151" - cell $and $and$ls180.v:6016$1511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6016$1509_Y - connect \B $eq$ls180.v:6016$1510_Y - connect \Y $and$ls180.v:6016$1511_Y - end - attribute \src "ls180.v:6017.47-6017.103" - cell $and $and$ls180.v:6017$1513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6017$1512_Y - connect \Y $and$ls180.v:6017$1513_Y - end - attribute \src "ls180.v:6017.46-6017.154" - cell $and $and$ls180.v:6017$1515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6017$1513_Y - connect \B $eq$ls180.v:6017$1514_Y - connect \Y $and$ls180.v:6017$1515_Y - end - attribute \src "ls180.v:6019.47-6019.100" - cell $and $and$ls180.v:6019$1516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6019$1516_Y - end - attribute \src "ls180.v:6019.46-6019.151" - cell $and $and$ls180.v:6019$1518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6019$1516_Y - connect \B $eq$ls180.v:6019$1517_Y - connect \Y $and$ls180.v:6019$1518_Y - end - attribute \src "ls180.v:6020.47-6020.103" - cell $and $and$ls180.v:6020$1520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6020$1519_Y - connect \Y $and$ls180.v:6020$1520_Y - end - attribute \src "ls180.v:6020.46-6020.154" - cell $and $and$ls180.v:6020$1522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6020$1520_Y - connect \B $eq$ls180.v:6020$1521_Y - connect \Y $and$ls180.v:6020$1522_Y - end - attribute \src "ls180.v:6022.47-6022.100" - cell $and $and$ls180.v:6022$1523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6022$1523_Y - end - attribute \src "ls180.v:6022.46-6022.151" - cell $and $and$ls180.v:6022$1525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6022$1523_Y - connect \B $eq$ls180.v:6022$1524_Y - connect \Y $and$ls180.v:6022$1525_Y - end - attribute \src "ls180.v:6023.47-6023.103" - cell $and $and$ls180.v:6023$1527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6023$1526_Y - connect \Y $and$ls180.v:6023$1527_Y - end - attribute \src "ls180.v:6023.46-6023.154" - cell $and $and$ls180.v:6023$1529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6023$1527_Y - connect \B $eq$ls180.v:6023$1528_Y - connect \Y $and$ls180.v:6023$1529_Y - end - attribute \src "ls180.v:6025.47-6025.100" - cell $and $and$ls180.v:6025$1530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6025$1530_Y - end - attribute \src "ls180.v:6025.46-6025.151" - cell $and $and$ls180.v:6025$1532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6025$1530_Y - connect \B $eq$ls180.v:6025$1531_Y - connect \Y $and$ls180.v:6025$1532_Y - end - attribute \src "ls180.v:6026.47-6026.103" - cell $and $and$ls180.v:6026$1534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6026$1533_Y - connect \Y $and$ls180.v:6026$1534_Y - end - attribute \src "ls180.v:6026.46-6026.154" - cell $and $and$ls180.v:6026$1536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6026$1534_Y - connect \B $eq$ls180.v:6026$1535_Y - connect \Y $and$ls180.v:6026$1536_Y - end - attribute \src "ls180.v:6028.47-6028.100" - cell $and $and$ls180.v:6028$1537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6028$1537_Y - end - attribute \src "ls180.v:6028.46-6028.151" - cell $and $and$ls180.v:6028$1539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6028$1537_Y - connect \B $eq$ls180.v:6028$1538_Y - connect \Y $and$ls180.v:6028$1539_Y - end - attribute \src "ls180.v:6029.47-6029.103" - cell $and $and$ls180.v:6029$1541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6029$1540_Y - connect \Y $and$ls180.v:6029$1541_Y - end - attribute \src "ls180.v:6029.46-6029.154" - cell $and $and$ls180.v:6029$1543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6029$1541_Y - connect \B $eq$ls180.v:6029$1542_Y - connect \Y $and$ls180.v:6029$1543_Y - end - attribute \src "ls180.v:6031.46-6031.99" - cell $and $and$ls180.v:6031$1544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6031$1544_Y - end - attribute \src "ls180.v:6031.45-6031.150" - cell $and $and$ls180.v:6031$1546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6031$1544_Y - connect \B $eq$ls180.v:6031$1545_Y - connect \Y $and$ls180.v:6031$1546_Y - end - attribute \src "ls180.v:6032.46-6032.102" - cell $and $and$ls180.v:6032$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6032$1547_Y - connect \Y $and$ls180.v:6032$1548_Y - end - attribute \src "ls180.v:6032.45-6032.153" - cell $and $and$ls180.v:6032$1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6032$1548_Y - connect \B $eq$ls180.v:6032$1549_Y - connect \Y $and$ls180.v:6032$1550_Y - end - attribute \src "ls180.v:6034.46-6034.99" - cell $and $and$ls180.v:6034$1551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6034$1551_Y - end - attribute \src "ls180.v:6034.45-6034.150" - cell $and $and$ls180.v:6034$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6034$1551_Y - connect \B $eq$ls180.v:6034$1552_Y - connect \Y $and$ls180.v:6034$1553_Y - end - attribute \src "ls180.v:6035.46-6035.102" - cell $and $and$ls180.v:6035$1555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6035$1554_Y - connect \Y $and$ls180.v:6035$1555_Y - end - attribute \src "ls180.v:6035.45-6035.153" - cell $and $and$ls180.v:6035$1557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6035$1555_Y - connect \B $eq$ls180.v:6035$1556_Y - connect \Y $and$ls180.v:6035$1557_Y - end - attribute \src "ls180.v:6037.46-6037.99" - cell $and $and$ls180.v:6037$1558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6037$1558_Y - end - attribute \src "ls180.v:6037.45-6037.150" - cell $and $and$ls180.v:6037$1560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6037$1558_Y - connect \B $eq$ls180.v:6037$1559_Y - connect \Y $and$ls180.v:6037$1560_Y - end - attribute \src "ls180.v:6038.46-6038.102" - cell $and $and$ls180.v:6038$1562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6038$1561_Y - connect \Y $and$ls180.v:6038$1562_Y - end - attribute \src "ls180.v:6038.45-6038.153" - cell $and $and$ls180.v:6038$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6038$1562_Y - connect \B $eq$ls180.v:6038$1563_Y - connect \Y $and$ls180.v:6038$1564_Y - end - attribute \src "ls180.v:6040.46-6040.99" - cell $and $and$ls180.v:6040$1565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6040$1565_Y - end - attribute \src "ls180.v:6040.45-6040.150" - cell $and $and$ls180.v:6040$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6040$1565_Y - connect \B $eq$ls180.v:6040$1566_Y - connect \Y $and$ls180.v:6040$1567_Y - end - attribute \src "ls180.v:6041.46-6041.102" - cell $and $and$ls180.v:6041$1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6041$1568_Y - connect \Y $and$ls180.v:6041$1569_Y - end - attribute \src "ls180.v:6041.45-6041.153" - cell $and $and$ls180.v:6041$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6041$1569_Y - connect \B $eq$ls180.v:6041$1570_Y - connect \Y $and$ls180.v:6041$1571_Y - end - attribute \src "ls180.v:6043.46-6043.99" - cell $and $and$ls180.v:6043$1572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6043$1572_Y - end - attribute \src "ls180.v:6043.45-6043.150" - cell $and $and$ls180.v:6043$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1572_Y - connect \B $eq$ls180.v:6043$1573_Y - connect \Y $and$ls180.v:6043$1574_Y - end - attribute \src "ls180.v:6044.46-6044.102" - cell $and $and$ls180.v:6044$1576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6044$1575_Y - connect \Y $and$ls180.v:6044$1576_Y - end - attribute \src "ls180.v:6044.45-6044.153" - cell $and $and$ls180.v:6044$1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1576_Y - connect \B $eq$ls180.v:6044$1577_Y - connect \Y $and$ls180.v:6044$1578_Y - end - attribute \src "ls180.v:6046.46-6046.99" - cell $and $and$ls180.v:6046$1579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6046$1579_Y - end - attribute \src "ls180.v:6046.45-6046.150" - cell $and $and$ls180.v:6046$1581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1579_Y - connect \B $eq$ls180.v:6046$1580_Y - connect \Y $and$ls180.v:6046$1581_Y - end - attribute \src "ls180.v:6047.46-6047.102" - cell $and $and$ls180.v:6047$1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6047$1582_Y - connect \Y $and$ls180.v:6047$1583_Y - end - attribute \src "ls180.v:6047.45-6047.153" - cell $and $and$ls180.v:6047$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1583_Y - connect \B $eq$ls180.v:6047$1584_Y - connect \Y $and$ls180.v:6047$1585_Y - end - attribute \src "ls180.v:6049.46-6049.99" - cell $and $and$ls180.v:6049$1586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6049$1586_Y - end - attribute \src "ls180.v:6049.45-6049.150" - cell $and $and$ls180.v:6049$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6049$1586_Y - connect \B $eq$ls180.v:6049$1587_Y - connect \Y $and$ls180.v:6049$1588_Y - end - attribute \src "ls180.v:6050.46-6050.102" - cell $and $and$ls180.v:6050$1590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6050$1589_Y - connect \Y $and$ls180.v:6050$1590_Y - end - attribute \src "ls180.v:6050.45-6050.153" - cell $and $and$ls180.v:6050$1592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6050$1590_Y - connect \B $eq$ls180.v:6050$1591_Y - connect \Y $and$ls180.v:6050$1592_Y - end - attribute \src "ls180.v:6052.46-6052.99" - cell $and $and$ls180.v:6052$1593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6052$1593_Y - end - attribute \src "ls180.v:6052.45-6052.150" - cell $and $and$ls180.v:6052$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6052$1593_Y - connect \B $eq$ls180.v:6052$1594_Y - connect \Y $and$ls180.v:6052$1595_Y - end - attribute \src "ls180.v:6053.46-6053.102" - cell $and $and$ls180.v:6053$1597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6053$1596_Y - connect \Y $and$ls180.v:6053$1597_Y - end - attribute \src "ls180.v:6053.45-6053.153" - cell $and $and$ls180.v:6053$1599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6053$1597_Y - connect \B $eq$ls180.v:6053$1598_Y - connect \Y $and$ls180.v:6053$1599_Y - end - attribute \src "ls180.v:6055.46-6055.99" - cell $and $and$ls180.v:6055$1600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6055$1600_Y - end - attribute \src "ls180.v:6055.45-6055.150" - cell $and $and$ls180.v:6055$1602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6055$1600_Y - connect \B $eq$ls180.v:6055$1601_Y - connect \Y $and$ls180.v:6055$1602_Y - end - attribute \src "ls180.v:6056.46-6056.102" - cell $and $and$ls180.v:6056$1604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6056$1603_Y - connect \Y $and$ls180.v:6056$1604_Y - end - attribute \src "ls180.v:6056.45-6056.153" - cell $and $and$ls180.v:6056$1606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6056$1604_Y - connect \B $eq$ls180.v:6056$1605_Y - connect \Y $and$ls180.v:6056$1606_Y - end - attribute \src "ls180.v:6058.46-6058.99" - cell $and $and$ls180.v:6058$1607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6058$1607_Y - end - attribute \src "ls180.v:6058.45-6058.150" - cell $and $and$ls180.v:6058$1609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6058$1607_Y - connect \B $eq$ls180.v:6058$1608_Y - connect \Y $and$ls180.v:6058$1609_Y - end - attribute \src "ls180.v:6059.46-6059.102" - cell $and $and$ls180.v:6059$1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6059$1610_Y - connect \Y $and$ls180.v:6059$1611_Y - end - attribute \src "ls180.v:6059.45-6059.153" - cell $and $and$ls180.v:6059$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6059$1611_Y - connect \B $eq$ls180.v:6059$1612_Y - connect \Y $and$ls180.v:6059$1613_Y - end - attribute \src "ls180.v:6061.42-6061.95" - cell $and $and$ls180.v:6061$1614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6061$1614_Y - end - attribute \src "ls180.v:6061.41-6061.146" - cell $and $and$ls180.v:6061$1616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6061$1614_Y - connect \B $eq$ls180.v:6061$1615_Y - connect \Y $and$ls180.v:6061$1616_Y - end - attribute \src "ls180.v:6062.42-6062.98" - cell $and $and$ls180.v:6062$1618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6062$1617_Y - connect \Y $and$ls180.v:6062$1618_Y - end - attribute \src "ls180.v:6062.41-6062.149" - cell $and $and$ls180.v:6062$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6062$1618_Y - connect \B $eq$ls180.v:6062$1619_Y - connect \Y $and$ls180.v:6062$1620_Y - end - attribute \src "ls180.v:6064.43-6064.96" - cell $and $and$ls180.v:6064$1621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6064$1621_Y - end - attribute \src "ls180.v:6064.42-6064.147" - cell $and $and$ls180.v:6064$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6064$1621_Y - connect \B $eq$ls180.v:6064$1622_Y - connect \Y $and$ls180.v:6064$1623_Y - end - attribute \src "ls180.v:6065.43-6065.99" - cell $and $and$ls180.v:6065$1625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6065$1624_Y - connect \Y $and$ls180.v:6065$1625_Y - end - attribute \src "ls180.v:6065.42-6065.150" - cell $and $and$ls180.v:6065$1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6065$1625_Y - connect \B $eq$ls180.v:6065$1626_Y - connect \Y $and$ls180.v:6065$1627_Y - end - attribute \src "ls180.v:6067.46-6067.99" - cell $and $and$ls180.v:6067$1628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6067$1628_Y - end - attribute \src "ls180.v:6067.45-6067.150" - cell $and $and$ls180.v:6067$1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1628_Y - connect \B $eq$ls180.v:6067$1629_Y - connect \Y $and$ls180.v:6067$1630_Y - end - attribute \src "ls180.v:6068.46-6068.102" - cell $and $and$ls180.v:6068$1632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6068$1631_Y - connect \Y $and$ls180.v:6068$1632_Y - end - attribute \src "ls180.v:6068.45-6068.153" - cell $and $and$ls180.v:6068$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6068$1632_Y - connect \B $eq$ls180.v:6068$1633_Y - connect \Y $and$ls180.v:6068$1634_Y - end - attribute \src "ls180.v:6070.46-6070.99" - cell $and $and$ls180.v:6070$1635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6070$1635_Y - end - attribute \src "ls180.v:6070.45-6070.150" - cell $and $and$ls180.v:6070$1637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6070$1635_Y - connect \B $eq$ls180.v:6070$1636_Y - connect \Y $and$ls180.v:6070$1637_Y - end - attribute \src "ls180.v:6071.46-6071.102" - cell $and $and$ls180.v:6071$1639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6071$1638_Y - connect \Y $and$ls180.v:6071$1639_Y - end - attribute \src "ls180.v:6071.45-6071.153" - cell $and $and$ls180.v:6071$1641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6071$1639_Y - connect \B $eq$ls180.v:6071$1640_Y - connect \Y $and$ls180.v:6071$1641_Y - end - attribute \src "ls180.v:6073.45-6073.98" - cell $and $and$ls180.v:6073$1642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6073$1642_Y - end - attribute \src "ls180.v:6073.44-6073.149" - cell $and $and$ls180.v:6073$1644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6073$1642_Y - connect \B $eq$ls180.v:6073$1643_Y - connect \Y $and$ls180.v:6073$1644_Y - end - attribute \src "ls180.v:6074.45-6074.101" - cell $and $and$ls180.v:6074$1646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6074$1645_Y - connect \Y $and$ls180.v:6074$1646_Y - end - attribute \src "ls180.v:6074.44-6074.152" - cell $and $and$ls180.v:6074$1648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6074$1646_Y - connect \B $eq$ls180.v:6074$1647_Y - connect \Y $and$ls180.v:6074$1648_Y - end - attribute \src "ls180.v:6076.45-6076.98" - cell $and $and$ls180.v:6076$1649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6076$1649_Y - end - attribute \src "ls180.v:6076.44-6076.149" - cell $and $and$ls180.v:6076$1651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6076$1649_Y - connect \B $eq$ls180.v:6076$1650_Y - connect \Y $and$ls180.v:6076$1651_Y - end - attribute \src "ls180.v:6077.45-6077.101" - cell $and $and$ls180.v:6077$1653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6077$1652_Y - connect \Y $and$ls180.v:6077$1653_Y - end - attribute \src "ls180.v:6077.44-6077.152" - cell $and $and$ls180.v:6077$1655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6077$1653_Y - connect \B $eq$ls180.v:6077$1654_Y - connect \Y $and$ls180.v:6077$1655_Y - end - attribute \src "ls180.v:6079.45-6079.98" - cell $and $and$ls180.v:6079$1656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6079$1656_Y - end - attribute \src "ls180.v:6079.44-6079.149" - cell $and $and$ls180.v:6079$1658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6079$1656_Y - connect \B $eq$ls180.v:6079$1657_Y - connect \Y $and$ls180.v:6079$1658_Y - end - attribute \src "ls180.v:6080.45-6080.101" - cell $and $and$ls180.v:6080$1660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6080$1659_Y - connect \Y $and$ls180.v:6080$1660_Y - end - attribute \src "ls180.v:6080.44-6080.152" - cell $and $and$ls180.v:6080$1662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6080$1660_Y - connect \B $eq$ls180.v:6080$1661_Y - connect \Y $and$ls180.v:6080$1662_Y - end - attribute \src "ls180.v:6082.45-6082.98" - cell $and $and$ls180.v:6082$1663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6082$1663_Y - end - attribute \src "ls180.v:6082.44-6082.149" - cell $and $and$ls180.v:6082$1665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6082$1663_Y - connect \B $eq$ls180.v:6082$1664_Y - connect \Y $and$ls180.v:6082$1665_Y - end - attribute \src "ls180.v:6083.45-6083.101" - cell $and $and$ls180.v:6083$1667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6083$1666_Y - connect \Y $and$ls180.v:6083$1667_Y - end - attribute \src "ls180.v:6083.44-6083.152" - cell $and $and$ls180.v:6083$1669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6083$1667_Y - connect \B $eq$ls180.v:6083$1668_Y - connect \Y $and$ls180.v:6083$1669_Y - end - attribute \src "ls180.v:6121.42-6121.95" - cell $and $and$ls180.v:6121$1671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6121$1671_Y - end - attribute \src "ls180.v:6121.41-6121.145" - cell $and $and$ls180.v:6121$1673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6121$1671_Y - connect \B $eq$ls180.v:6121$1672_Y - connect \Y $and$ls180.v:6121$1673_Y - end - attribute \src "ls180.v:6122.42-6122.98" - cell $and $and$ls180.v:6122$1675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6122$1674_Y - connect \Y $and$ls180.v:6122$1675_Y - end - attribute \src "ls180.v:6122.41-6122.148" - cell $and $and$ls180.v:6122$1677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6122$1675_Y - connect \B $eq$ls180.v:6122$1676_Y - connect \Y $and$ls180.v:6122$1677_Y - end - attribute \src "ls180.v:6124.42-6124.95" - cell $and $and$ls180.v:6124$1678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6124$1678_Y - end - attribute \src "ls180.v:6124.41-6124.145" - cell $and $and$ls180.v:6124$1680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1678_Y - connect \B $eq$ls180.v:6124$1679_Y - connect \Y $and$ls180.v:6124$1680_Y - end - attribute \src "ls180.v:6125.42-6125.98" - cell $and $and$ls180.v:6125$1682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6125$1681_Y - connect \Y $and$ls180.v:6125$1682_Y - end - attribute \src "ls180.v:6125.41-6125.148" - cell $and $and$ls180.v:6125$1684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6125$1682_Y - connect \B $eq$ls180.v:6125$1683_Y - connect \Y $and$ls180.v:6125$1684_Y - end - attribute \src "ls180.v:6127.42-6127.95" - cell $and $and$ls180.v:6127$1685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6127$1685_Y - end - attribute \src "ls180.v:6127.41-6127.145" - cell $and $and$ls180.v:6127$1687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1685_Y - connect \B $eq$ls180.v:6127$1686_Y - connect \Y $and$ls180.v:6127$1687_Y - end - attribute \src "ls180.v:6128.42-6128.98" - cell $and $and$ls180.v:6128$1689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6128$1688_Y - connect \Y $and$ls180.v:6128$1689_Y - end - attribute \src "ls180.v:6128.41-6128.148" - cell $and $and$ls180.v:6128$1691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6128$1689_Y - connect \B $eq$ls180.v:6128$1690_Y - connect \Y $and$ls180.v:6128$1691_Y - end - attribute \src "ls180.v:6130.42-6130.95" - cell $and $and$ls180.v:6130$1692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6130$1692_Y - end - attribute \src "ls180.v:6130.41-6130.145" - cell $and $and$ls180.v:6130$1694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1692_Y - connect \B $eq$ls180.v:6130$1693_Y - connect \Y $and$ls180.v:6130$1694_Y - end - attribute \src "ls180.v:6131.42-6131.98" - cell $and $and$ls180.v:6131$1696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6131$1695_Y - connect \Y $and$ls180.v:6131$1696_Y - end - attribute \src "ls180.v:6131.41-6131.148" - cell $and $and$ls180.v:6131$1698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6131$1696_Y - connect \B $eq$ls180.v:6131$1697_Y - connect \Y $and$ls180.v:6131$1698_Y - end - attribute \src "ls180.v:6133.42-6133.95" - cell $and $and$ls180.v:6133$1699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6133$1699_Y - end - attribute \src "ls180.v:6133.41-6133.145" - cell $and $and$ls180.v:6133$1701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1699_Y - connect \B $eq$ls180.v:6133$1700_Y - connect \Y $and$ls180.v:6133$1701_Y - end - attribute \src "ls180.v:6134.42-6134.98" - cell $and $and$ls180.v:6134$1703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6134$1702_Y - connect \Y $and$ls180.v:6134$1703_Y - end - attribute \src "ls180.v:6134.41-6134.148" - cell $and $and$ls180.v:6134$1705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6134$1703_Y - connect \B $eq$ls180.v:6134$1704_Y - connect \Y $and$ls180.v:6134$1705_Y - end - attribute \src "ls180.v:6136.42-6136.95" - cell $and $and$ls180.v:6136$1706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6136$1706_Y - end - attribute \src "ls180.v:6136.41-6136.145" - cell $and $and$ls180.v:6136$1708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1706_Y - connect \B $eq$ls180.v:6136$1707_Y - connect \Y $and$ls180.v:6136$1708_Y - end - attribute \src "ls180.v:6137.42-6137.98" - cell $and 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parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1713_Y - connect \B $eq$ls180.v:6139$1714_Y - connect \Y $and$ls180.v:6139$1715_Y - end - attribute \src "ls180.v:6140.42-6140.98" - cell $and $and$ls180.v:6140$1717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6140$1716_Y - connect \Y $and$ls180.v:6140$1717_Y - end - attribute \src "ls180.v:6140.41-6140.148" - cell $and $and$ls180.v:6140$1719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6140$1717_Y - connect \B $eq$ls180.v:6140$1718_Y - connect \Y $and$ls180.v:6140$1719_Y - end - attribute \src "ls180.v:6142.42-6142.95" - cell $and $and$ls180.v:6142$1720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6142$1720_Y - end - attribute \src "ls180.v:6142.41-6142.145" - cell $and $and$ls180.v:6142$1722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1720_Y - connect \B $eq$ls180.v:6142$1721_Y - connect \Y $and$ls180.v:6142$1722_Y - end - attribute \src "ls180.v:6143.42-6143.98" - cell $and $and$ls180.v:6143$1724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6143$1723_Y - connect \Y $and$ls180.v:6143$1724_Y - end - attribute \src "ls180.v:6143.41-6143.148" - cell $and $and$ls180.v:6143$1726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6143$1724_Y - connect \B $eq$ls180.v:6143$1725_Y - connect \Y $and$ls180.v:6143$1726_Y - end - attribute \src "ls180.v:6145.44-6145.97" - cell $and $and$ls180.v:6145$1727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6145$1727_Y - end - attribute \src "ls180.v:6145.43-6145.147" - cell $and $and$ls180.v:6145$1729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1727_Y - connect \B $eq$ls180.v:6145$1728_Y - connect \Y $and$ls180.v:6145$1729_Y - end - attribute \src "ls180.v:6146.44-6146.100" - cell $and $and$ls180.v:6146$1731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6146$1730_Y - connect \Y $and$ls180.v:6146$1731_Y - end - attribute \src "ls180.v:6146.43-6146.150" - cell $and $and$ls180.v:6146$1733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6146$1731_Y - connect \B $eq$ls180.v:6146$1732_Y - connect \Y $and$ls180.v:6146$1733_Y - end - attribute \src "ls180.v:6148.44-6148.97" - cell $and $and$ls180.v:6148$1734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6148$1734_Y - end - attribute \src "ls180.v:6148.43-6148.147" - cell $and $and$ls180.v:6148$1736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1734_Y - connect \B $eq$ls180.v:6148$1735_Y - connect \Y $and$ls180.v:6148$1736_Y - end - attribute \src "ls180.v:6149.44-6149.100" - cell $and $and$ls180.v:6149$1738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6149$1737_Y - connect \Y $and$ls180.v:6149$1738_Y - end - attribute \src "ls180.v:6149.43-6149.150" - cell $and $and$ls180.v:6149$1740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6149$1738_Y - connect \B $eq$ls180.v:6149$1739_Y - connect \Y $and$ls180.v:6149$1740_Y - end - attribute \src "ls180.v:6151.44-6151.97" - cell $and $and$ls180.v:6151$1741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6151$1741_Y - end - attribute \src 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parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6155$1752_Y - connect \B $eq$ls180.v:6155$1753_Y - connect \Y $and$ls180.v:6155$1754_Y - end - attribute \src "ls180.v:6157.44-6157.97" - cell $and $and$ls180.v:6157$1755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6157$1755_Y - end - attribute \src "ls180.v:6157.43-6157.148" - cell $and $and$ls180.v:6157$1757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6157$1755_Y - connect \B $eq$ls180.v:6157$1756_Y - connect \Y $and$ls180.v:6157$1757_Y - end - attribute \src "ls180.v:6158.44-6158.100" - cell $and $and$ls180.v:6158$1759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6158$1758_Y - connect \Y $and$ls180.v:6158$1759_Y - end - attribute \src "ls180.v:6158.43-6158.151" - cell $and $and$ls180.v:6158$1761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6158$1759_Y - connect \B $eq$ls180.v:6158$1760_Y - connect \Y $and$ls180.v:6158$1761_Y - end - attribute \src "ls180.v:6160.41-6160.94" - cell $and $and$ls180.v:6160$1762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6160$1762_Y - end - attribute \src "ls180.v:6160.40-6160.145" - cell $and $and$ls180.v:6160$1764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6160$1762_Y - connect \B $eq$ls180.v:6160$1763_Y - connect \Y $and$ls180.v:6160$1764_Y - end - attribute \src "ls180.v:6161.41-6161.97" - cell $and $and$ls180.v:6161$1766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6161$1765_Y - connect \Y $and$ls180.v:6161$1766_Y - end - attribute \src "ls180.v:6161.40-6161.148" - cell $and $and$ls180.v:6161$1768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6161$1766_Y - connect \B $eq$ls180.v:6161$1767_Y - connect \Y $and$ls180.v:6161$1768_Y - end - attribute \src "ls180.v:6163.42-6163.95" - cell $and $and$ls180.v:6163$1769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6163$1769_Y - end - attribute \src "ls180.v:6163.41-6163.146" - cell $and $and$ls180.v:6163$1771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6163$1769_Y - connect \B $eq$ls180.v:6163$1770_Y - connect \Y $and$ls180.v:6163$1771_Y - end - attribute \src "ls180.v:6164.42-6164.98" - cell $and $and$ls180.v:6164$1773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6164$1772_Y - connect \Y $and$ls180.v:6164$1773_Y - end - attribute \src "ls180.v:6164.41-6164.149" - cell $and $and$ls180.v:6164$1775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6164$1773_Y - connect \B $eq$ls180.v:6164$1774_Y - connect \Y $and$ls180.v:6164$1775_Y - end - attribute \src "ls180.v:6166.44-6166.97" - cell $and $and$ls180.v:6166$1776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6166$1776_Y - end - attribute \src "ls180.v:6166.43-6166.148" - cell $and $and$ls180.v:6166$1778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6166$1776_Y - connect \B $eq$ls180.v:6166$1777_Y - connect \Y $and$ls180.v:6166$1778_Y - end - attribute \src "ls180.v:6167.44-6167.100" - cell $and $and$ls180.v:6167$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6167$1779_Y - connect \Y $and$ls180.v:6167$1780_Y - end - attribute \src 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$and$ls180.v:6170$1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6170$1786_Y - connect \Y $and$ls180.v:6170$1787_Y - end - attribute \src "ls180.v:6170.43-6170.151" - cell $and $and$ls180.v:6170$1789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6170$1787_Y - connect \B $eq$ls180.v:6170$1788_Y - connect \Y $and$ls180.v:6170$1789_Y - end - attribute \src "ls180.v:6172.44-6172.97" - cell $and $and$ls180.v:6172$1790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6172$1790_Y - end - attribute \src "ls180.v:6172.43-6172.148" - cell $and $and$ls180.v:6172$1792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6172$1790_Y - connect \B $eq$ls180.v:6172$1791_Y - connect \Y $and$ls180.v:6172$1792_Y - end - attribute \src "ls180.v:6173.44-6173.100" - cell $and $and$ls180.v:6173$1794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6173$1793_Y - connect \Y $and$ls180.v:6173$1794_Y - end - attribute \src "ls180.v:6173.43-6173.151" - cell $and $and$ls180.v:6173$1796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6173$1794_Y - connect \B $eq$ls180.v:6173$1795_Y - connect \Y $and$ls180.v:6173$1796_Y - end - attribute \src "ls180.v:6175.44-6175.97" - cell $and $and$ls180.v:6175$1797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6175$1797_Y - end - attribute \src "ls180.v:6175.43-6175.148" - cell $and $and$ls180.v:6175$1799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6175$1797_Y - connect \B $eq$ls180.v:6175$1798_Y - connect \Y $and$ls180.v:6175$1799_Y - end - attribute \src "ls180.v:6176.44-6176.100" - cell $and $and$ls180.v:6176$1801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6176$1800_Y - connect \Y $and$ls180.v:6176$1801_Y - end - attribute \src "ls180.v:6176.43-6176.151" - cell $and $and$ls180.v:6176$1803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6176$1801_Y - connect \B $eq$ls180.v:6176$1802_Y - connect \Y $and$ls180.v:6176$1803_Y - end - attribute \src "ls180.v:6200.44-6200.97" - cell $and $and$ls180.v:6200$1805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6200$1805_Y - end - attribute \src "ls180.v:6200.43-6200.147" - cell $and $and$ls180.v:6200$1807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6200$1805_Y - connect \B $eq$ls180.v:6200$1806_Y - connect \Y $and$ls180.v:6200$1807_Y - end - attribute \src "ls180.v:6201.44-6201.100" - cell $and $and$ls180.v:6201$1809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6201$1808_Y - connect \Y $and$ls180.v:6201$1809_Y - end - attribute \src "ls180.v:6201.43-6201.150" - cell $and $and$ls180.v:6201$1811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1809_Y - connect \B $eq$ls180.v:6201$1810_Y - connect \Y $and$ls180.v:6201$1811_Y - end - attribute \src "ls180.v:6203.49-6203.102" - cell $and $and$ls180.v:6203$1812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6203$1812_Y - end - attribute \src "ls180.v:6203.48-6203.152" - cell $and $and$ls180.v:6203$1814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6203$1812_Y - connect \B $eq$ls180.v:6203$1813_Y - connect \Y $and$ls180.v:6203$1814_Y - end - attribute \src "ls180.v:6204.49-6204.105" - cell $and $and$ls180.v:6204$1816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6204$1815_Y - connect \Y $and$ls180.v:6204$1816_Y - end - attribute \src "ls180.v:6204.48-6204.155" - cell $and $and$ls180.v:6204$1818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1816_Y - connect \B $eq$ls180.v:6204$1817_Y - connect \Y $and$ls180.v:6204$1818_Y - end - attribute \src "ls180.v:6206.49-6206.102" - cell $and $and$ls180.v:6206$1819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6206$1819_Y - end - attribute \src "ls180.v:6206.48-6206.152" - cell $and $and$ls180.v:6206$1821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6206$1819_Y - connect \B $eq$ls180.v:6206$1820_Y - connect \Y $and$ls180.v:6206$1821_Y - end - attribute \src "ls180.v:6207.49-6207.105" - cell $and $and$ls180.v:6207$1823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6207$1822_Y - connect \Y $and$ls180.v:6207$1823_Y - end - attribute \src "ls180.v:6207.48-6207.155" - cell $and $and$ls180.v:6207$1825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1823_Y - connect \B $eq$ls180.v:6207$1824_Y - connect \Y $and$ls180.v:6207$1825_Y - end - attribute \src "ls180.v:6209.42-6209.95" - cell $and $and$ls180.v:6209$1826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6209$1826_Y - end - attribute \src "ls180.v:6209.41-6209.145" - cell $and $and$ls180.v:6209$1828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6209$1826_Y - connect \B $eq$ls180.v:6209$1827_Y - connect \Y $and$ls180.v:6209$1828_Y - end - attribute \src "ls180.v:6210.42-6210.98" - cell $and $and$ls180.v:6210$1830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6210$1829_Y - connect \Y $and$ls180.v:6210$1830_Y - end - attribute \src "ls180.v:6210.41-6210.148" - cell $and $and$ls180.v:6210$1832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1830_Y - connect \B $eq$ls180.v:6210$1831_Y - connect \Y $and$ls180.v:6210$1832_Y - end - attribute \src "ls180.v:6217.46-6217.99" - cell $and $and$ls180.v:6217$1834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6217$1834_Y - end - attribute \src "ls180.v:6217.45-6217.149" - cell $and $and$ls180.v:6217$1836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6217$1834_Y - connect \B $eq$ls180.v:6217$1835_Y - connect \Y $and$ls180.v:6217$1836_Y - end - attribute \src "ls180.v:6218.46-6218.102" - cell $and $and$ls180.v:6218$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6218$1837_Y - connect \Y $and$ls180.v:6218$1838_Y - end - attribute \src "ls180.v:6218.45-6218.152" - cell $and $and$ls180.v:6218$1840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6218$1838_Y - connect \B $eq$ls180.v:6218$1839_Y - connect \Y $and$ls180.v:6218$1840_Y - end - attribute \src "ls180.v:6220.50-6220.103" - cell $and $and$ls180.v:6220$1841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6220$1841_Y - end - attribute \src "ls180.v:6220.49-6220.153" - cell $and $and$ls180.v:6220$1843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6220$1841_Y - connect \B $eq$ls180.v:6220$1842_Y - connect \Y $and$ls180.v:6220$1843_Y - end - attribute \src "ls180.v:6221.50-6221.106" - cell $and $and$ls180.v:6221$1845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6221$1844_Y - connect \Y $and$ls180.v:6221$1845_Y - end - attribute \src "ls180.v:6221.49-6221.156" - cell $and $and$ls180.v:6221$1847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6221$1845_Y - connect \B $eq$ls180.v:6221$1846_Y - connect \Y $and$ls180.v:6221$1847_Y - end - attribute \src "ls180.v:6223.40-6223.93" - cell $and $and$ls180.v:6223$1848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6223$1848_Y - end - attribute \src "ls180.v:6223.39-6223.143" - cell $and $and$ls180.v:6223$1850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1848_Y - connect \B $eq$ls180.v:6223$1849_Y - connect \Y $and$ls180.v:6223$1850_Y - end - attribute \src "ls180.v:6224.40-6224.96" - cell $and $and$ls180.v:6224$1852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6224$1851_Y - connect \Y $and$ls180.v:6224$1852_Y - end - attribute \src "ls180.v:6224.39-6224.146" - cell $and $and$ls180.v:6224$1854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6224$1852_Y - connect \B $eq$ls180.v:6224$1853_Y - connect \Y $and$ls180.v:6224$1854_Y - end - attribute \src "ls180.v:6226.50-6226.103" - cell $and $and$ls180.v:6226$1855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6226$1855_Y - end - attribute \src "ls180.v:6226.49-6226.153" - cell $and $and$ls180.v:6226$1857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1855_Y - connect \B $eq$ls180.v:6226$1856_Y - connect \Y $and$ls180.v:6226$1857_Y - end - attribute \src "ls180.v:6227.50-6227.106" - cell $and $and$ls180.v:6227$1859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6227$1858_Y - connect \Y $and$ls180.v:6227$1859_Y - end - attribute \src "ls180.v:6227.49-6227.156" - cell $and $and$ls180.v:6227$1861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6227$1859_Y - connect \B $eq$ls180.v:6227$1860_Y - connect \Y $and$ls180.v:6227$1861_Y - end - attribute \src "ls180.v:6229.50-6229.103" - cell $and $and$ls180.v:6229$1862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6229$1862_Y - end - attribute \src "ls180.v:6229.49-6229.153" - cell $and $and$ls180.v:6229$1864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1862_Y - connect \B $eq$ls180.v:6229$1863_Y - connect \Y $and$ls180.v:6229$1864_Y - end - attribute \src "ls180.v:6230.50-6230.106" - cell $and $and$ls180.v:6230$1866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6230$1865_Y - connect \Y $and$ls180.v:6230$1866_Y - end - attribute \src "ls180.v:6230.49-6230.156" - cell $and $and$ls180.v:6230$1868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6230$1866_Y - connect \B $eq$ls180.v:6230$1867_Y - connect \Y $and$ls180.v:6230$1868_Y - end - attribute \src "ls180.v:6232.51-6232.104" - cell $and $and$ls180.v:6232$1869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6232$1869_Y - end - attribute \src "ls180.v:6232.50-6232.154" - cell $and $and$ls180.v:6232$1871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1869_Y - connect \B $eq$ls180.v:6232$1870_Y - connect \Y $and$ls180.v:6232$1871_Y - end - attribute \src "ls180.v:6233.51-6233.107" - cell $and $and$ls180.v:6233$1873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6233$1872_Y - connect \Y $and$ls180.v:6233$1873_Y - end - attribute \src "ls180.v:6233.50-6233.157" - cell $and $and$ls180.v:6233$1875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6233$1873_Y - connect \B $eq$ls180.v:6233$1874_Y - connect \Y $and$ls180.v:6233$1875_Y - end - attribute \src "ls180.v:6235.49-6235.102" - cell $and $and$ls180.v:6235$1876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6235$1876_Y - end - attribute \src "ls180.v:6235.48-6235.152" - cell $and $and$ls180.v:6235$1878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1876_Y - connect \B $eq$ls180.v:6235$1877_Y - connect \Y $and$ls180.v:6235$1878_Y - end - attribute \src "ls180.v:6236.49-6236.105" - cell $and $and$ls180.v:6236$1880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6236$1879_Y - connect \Y $and$ls180.v:6236$1880_Y - end - attribute \src "ls180.v:6236.48-6236.155" - cell $and $and$ls180.v:6236$1882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6236$1880_Y - connect \B $eq$ls180.v:6236$1881_Y - connect \Y $and$ls180.v:6236$1882_Y - end - attribute \src "ls180.v:6238.49-6238.102" - cell $and $and$ls180.v:6238$1883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6238$1883_Y - end - attribute \src "ls180.v:6238.48-6238.152" - cell $and $and$ls180.v:6238$1885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1883_Y - connect \B $eq$ls180.v:6238$1884_Y - connect \Y $and$ls180.v:6238$1885_Y - end - attribute \src "ls180.v:6239.49-6239.105" - cell $and $and$ls180.v:6239$1887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6239$1886_Y - connect \Y $and$ls180.v:6239$1887_Y - end - attribute \src "ls180.v:6239.48-6239.155" - cell $and $and$ls180.v:6239$1889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6239$1887_Y - connect \B $eq$ls180.v:6239$1888_Y - connect \Y $and$ls180.v:6239$1889_Y - end - attribute \src "ls180.v:6241.49-6241.102" - cell $and $and$ls180.v:6241$1890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6241$1890_Y - end - attribute \src "ls180.v:6241.48-6241.152" - cell $and $and$ls180.v:6241$1892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1890_Y - connect \B $eq$ls180.v:6241$1891_Y - connect \Y $and$ls180.v:6241$1892_Y - end - attribute \src "ls180.v:6242.49-6242.105" - cell $and $and$ls180.v:6242$1894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6242$1893_Y - connect \Y $and$ls180.v:6242$1894_Y - end - attribute \src "ls180.v:6242.48-6242.155" - cell $and $and$ls180.v:6242$1896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6242$1894_Y - connect \B $eq$ls180.v:6242$1895_Y - connect \Y $and$ls180.v:6242$1896_Y - end - attribute \src "ls180.v:6244.49-6244.102" - cell $and $and$ls180.v:6244$1897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6244$1897_Y - end - attribute \src "ls180.v:6244.48-6244.152" - cell $and $and$ls180.v:6244$1899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6244$1897_Y - connect \B $eq$ls180.v:6244$1898_Y - connect \Y $and$ls180.v:6244$1899_Y - end - attribute \src "ls180.v:6245.49-6245.105" - cell $and $and$ls180.v:6245$1901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6245$1900_Y - connect \Y $and$ls180.v:6245$1901_Y - end - attribute \src "ls180.v:6245.48-6245.155" - cell $and $and$ls180.v:6245$1903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6245$1901_Y - connect \B $eq$ls180.v:6245$1902_Y - connect \Y $and$ls180.v:6245$1903_Y - end - attribute \src "ls180.v:6262.42-6262.97" - cell $and $and$ls180.v:6262$1905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6262$1905_Y - end - attribute \src "ls180.v:6262.41-6262.148" - cell $and $and$ls180.v:6262$1907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6262$1905_Y - connect \B $eq$ls180.v:6262$1906_Y - connect \Y $and$ls180.v:6262$1907_Y - end - attribute \src "ls180.v:6263.42-6263.100" - cell $and $and$ls180.v:6263$1909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6263$1908_Y - connect \Y $and$ls180.v:6263$1909_Y - end - attribute \src "ls180.v:6263.41-6263.151" - cell $and $and$ls180.v:6263$1911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6263$1909_Y - connect \B $eq$ls180.v:6263$1910_Y - connect \Y $and$ls180.v:6263$1911_Y - end - attribute \src "ls180.v:6265.42-6265.97" - cell $and $and$ls180.v:6265$1912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6265$1912_Y - end - attribute \src "ls180.v:6265.41-6265.148" - cell $and $and$ls180.v:6265$1914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6265$1912_Y - connect \B $eq$ls180.v:6265$1913_Y - connect \Y $and$ls180.v:6265$1914_Y - end - attribute \src "ls180.v:6266.42-6266.100" - cell $and $and$ls180.v:6266$1916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6266$1915_Y - connect \Y $and$ls180.v:6266$1916_Y - end - attribute \src "ls180.v:6266.41-6266.151" - cell $and $and$ls180.v:6266$1918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6266$1916_Y - connect \B $eq$ls180.v:6266$1917_Y - connect \Y $and$ls180.v:6266$1918_Y - end - attribute \src "ls180.v:6268.40-6268.95" - cell $and $and$ls180.v:6268$1919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6268$1919_Y - end - attribute \src "ls180.v:6268.39-6268.146" - cell $and $and$ls180.v:6268$1921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6268$1919_Y - connect \B $eq$ls180.v:6268$1920_Y - connect \Y $and$ls180.v:6268$1921_Y - end - attribute \src "ls180.v:6269.40-6269.98" - cell $and $and$ls180.v:6269$1923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6269$1922_Y - connect \Y $and$ls180.v:6269$1923_Y - end - attribute \src "ls180.v:6269.39-6269.149" - cell $and $and$ls180.v:6269$1925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6269$1923_Y - connect \B $eq$ls180.v:6269$1924_Y - connect \Y $and$ls180.v:6269$1925_Y - end - attribute \src "ls180.v:6271.39-6271.94" - cell $and $and$ls180.v:6271$1926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6271$1926_Y - end - attribute \src "ls180.v:6271.38-6271.145" - cell $and $and$ls180.v:6271$1928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6271$1926_Y - connect \B $eq$ls180.v:6271$1927_Y - connect \Y $and$ls180.v:6271$1928_Y - end - attribute \src "ls180.v:6272.39-6272.97" - cell $and $and$ls180.v:6272$1930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6272$1929_Y - connect \Y $and$ls180.v:6272$1930_Y - end - attribute \src "ls180.v:6272.38-6272.148" - cell $and $and$ls180.v:6272$1932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6272$1930_Y - connect \B $eq$ls180.v:6272$1931_Y - connect \Y $and$ls180.v:6272$1932_Y - end - attribute \src "ls180.v:6274.38-6274.93" - cell $and $and$ls180.v:6274$1933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6274$1933_Y - end - attribute \src "ls180.v:6274.37-6274.144" - cell $and $and$ls180.v:6274$1935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6274$1933_Y - connect \B $eq$ls180.v:6274$1934_Y - connect \Y $and$ls180.v:6274$1935_Y - end - attribute \src "ls180.v:6275.38-6275.96" - cell $and $and$ls180.v:6275$1937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6275$1936_Y - connect \Y $and$ls180.v:6275$1937_Y - end - attribute \src "ls180.v:6275.37-6275.147" - cell $and $and$ls180.v:6275$1939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6275$1937_Y - connect \B $eq$ls180.v:6275$1938_Y - connect \Y $and$ls180.v:6275$1939_Y - end - attribute \src "ls180.v:6277.37-6277.92" - cell $and $and$ls180.v:6277$1940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6277$1940_Y - end - attribute \src "ls180.v:6277.36-6277.143" - cell $and $and$ls180.v:6277$1942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6277$1940_Y - connect \B $eq$ls180.v:6277$1941_Y - connect \Y $and$ls180.v:6277$1942_Y - end - attribute \src "ls180.v:6278.37-6278.95" - cell $and $and$ls180.v:6278$1944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6278$1943_Y - connect \Y $and$ls180.v:6278$1944_Y - end - attribute \src "ls180.v:6278.36-6278.146" - cell $and $and$ls180.v:6278$1946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6278$1944_Y - connect \B $eq$ls180.v:6278$1945_Y - connect \Y $and$ls180.v:6278$1946_Y - end - attribute \src "ls180.v:6280.43-6280.98" - cell $and $and$ls180.v:6280$1947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6280$1947_Y - end - attribute \src "ls180.v:6280.42-6280.149" - cell $and $and$ls180.v:6280$1949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6280$1947_Y - connect \B $eq$ls180.v:6280$1948_Y - connect \Y $and$ls180.v:6280$1949_Y - end - attribute \src "ls180.v:6281.43-6281.101" - cell $and $and$ls180.v:6281$1951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6281$1950_Y - connect \Y $and$ls180.v:6281$1951_Y - end - attribute \src "ls180.v:6281.42-6281.152" - cell $and $and$ls180.v:6281$1953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6281$1951_Y - connect \B $eq$ls180.v:6281$1952_Y - connect \Y $and$ls180.v:6281$1953_Y - end - attribute \src "ls180.v:6302.42-6302.97" - cell $and $and$ls180.v:6302$1956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6302$1956_Y - end - attribute \src "ls180.v:6302.41-6302.148" - cell $and $and$ls180.v:6302$1958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6302$1956_Y - connect \B $eq$ls180.v:6302$1957_Y - connect \Y $and$ls180.v:6302$1958_Y - end - attribute \src "ls180.v:6303.42-6303.100" - cell $and $and$ls180.v:6303$1960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6303$1959_Y - connect \Y $and$ls180.v:6303$1960_Y - end - attribute \src "ls180.v:6303.41-6303.151" - cell $and $and$ls180.v:6303$1962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$1960_Y - connect \B $eq$ls180.v:6303$1961_Y - connect \Y $and$ls180.v:6303$1962_Y - end - attribute \src "ls180.v:6305.42-6305.97" - cell $and $and$ls180.v:6305$1963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6305$1963_Y - end - attribute \src "ls180.v:6305.41-6305.148" - cell $and $and$ls180.v:6305$1965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6305$1963_Y - connect \B $eq$ls180.v:6305$1964_Y - connect \Y $and$ls180.v:6305$1965_Y - end - attribute \src "ls180.v:6306.42-6306.100" - cell $and $and$ls180.v:6306$1967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6306$1966_Y - connect \Y $and$ls180.v:6306$1967_Y - end - attribute \src "ls180.v:6306.41-6306.151" - cell $and $and$ls180.v:6306$1969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$1967_Y - connect \B $eq$ls180.v:6306$1968_Y - connect \Y $and$ls180.v:6306$1969_Y - end - attribute \src "ls180.v:6308.40-6308.95" - cell $and $and$ls180.v:6308$1970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6308$1970_Y - end - attribute \src "ls180.v:6308.39-6308.146" - cell $and $and$ls180.v:6308$1972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6308$1970_Y - connect \B $eq$ls180.v:6308$1971_Y - connect \Y $and$ls180.v:6308$1972_Y - end - attribute \src "ls180.v:6309.40-6309.98" - cell $and $and$ls180.v:6309$1974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6309$1973_Y - connect \Y $and$ls180.v:6309$1974_Y - end - attribute \src "ls180.v:6309.39-6309.149" - cell $and $and$ls180.v:6309$1976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$1974_Y - connect \B $eq$ls180.v:6309$1975_Y - connect \Y $and$ls180.v:6309$1976_Y - end - attribute \src "ls180.v:6311.39-6311.94" - cell $and $and$ls180.v:6311$1977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6311$1977_Y - end - attribute \src "ls180.v:6311.38-6311.145" - cell $and $and$ls180.v:6311$1979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6311$1977_Y - connect \B $eq$ls180.v:6311$1978_Y - connect \Y $and$ls180.v:6311$1979_Y - end - attribute \src "ls180.v:6312.39-6312.97" - cell $and $and$ls180.v:6312$1981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6312$1980_Y - connect \Y $and$ls180.v:6312$1981_Y - end - attribute \src "ls180.v:6312.38-6312.148" - cell $and $and$ls180.v:6312$1983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$1981_Y - connect \B $eq$ls180.v:6312$1982_Y - connect \Y $and$ls180.v:6312$1983_Y - end - attribute \src "ls180.v:6314.38-6314.93" - cell $and $and$ls180.v:6314$1984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6314$1984_Y - end - attribute \src "ls180.v:6314.37-6314.144" - cell $and $and$ls180.v:6314$1986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6314$1984_Y - connect \B $eq$ls180.v:6314$1985_Y - connect \Y $and$ls180.v:6314$1986_Y - end - attribute \src "ls180.v:6315.38-6315.96" - cell $and $and$ls180.v:6315$1988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6315$1987_Y - connect \Y $and$ls180.v:6315$1988_Y - end - attribute \src "ls180.v:6315.37-6315.147" - cell $and $and$ls180.v:6315$1990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$1988_Y - connect \B $eq$ls180.v:6315$1989_Y - connect \Y $and$ls180.v:6315$1990_Y - end - attribute \src "ls180.v:6317.37-6317.92" - cell $and $and$ls180.v:6317$1991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6317$1991_Y - end - attribute \src "ls180.v:6317.36-6317.143" - cell $and $and$ls180.v:6317$1993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6317$1991_Y - connect \B $eq$ls180.v:6317$1992_Y - connect \Y $and$ls180.v:6317$1993_Y - end - attribute \src "ls180.v:6318.37-6318.95" - cell $and $and$ls180.v:6318$1995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6318$1994_Y - connect \Y $and$ls180.v:6318$1995_Y - end - attribute \src "ls180.v:6318.36-6318.146" - cell $and $and$ls180.v:6318$1997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1995_Y - connect \B $eq$ls180.v:6318$1996_Y - connect \Y $and$ls180.v:6318$1997_Y - end - attribute \src "ls180.v:6320.43-6320.98" - cell $and $and$ls180.v:6320$1998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6320$1998_Y - end - attribute \src "ls180.v:6320.42-6320.149" - cell $and $and$ls180.v:6320$2000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6320$1998_Y - connect \B $eq$ls180.v:6320$1999_Y - connect \Y $and$ls180.v:6320$2000_Y - end - attribute \src "ls180.v:6321.43-6321.101" - cell $and $and$ls180.v:6321$2002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6321$2001_Y - connect \Y $and$ls180.v:6321$2002_Y - end - attribute \src "ls180.v:6321.42-6321.152" - cell $and $and$ls180.v:6321$2004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$2002_Y - connect \B $eq$ls180.v:6321$2003_Y - connect \Y $and$ls180.v:6321$2004_Y - end - attribute \src "ls180.v:6323.46-6323.101" - cell $and $and$ls180.v:6323$2005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6323$2005_Y - end - attribute \src "ls180.v:6323.45-6323.152" - cell $and $and$ls180.v:6323$2007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6323$2005_Y - connect \B $eq$ls180.v:6323$2006_Y - connect \Y $and$ls180.v:6323$2007_Y - end - attribute \src "ls180.v:6324.46-6324.104" - cell $and $and$ls180.v:6324$2009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6324$2008_Y - connect \Y $and$ls180.v:6324$2009_Y - end - attribute \src "ls180.v:6324.45-6324.155" - cell $and $and$ls180.v:6324$2011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$2009_Y - connect \B $eq$ls180.v:6324$2010_Y - connect \Y $and$ls180.v:6324$2011_Y - end - attribute \src "ls180.v:6326.46-6326.101" - cell $and $and$ls180.v:6326$2012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6326$2012_Y - end - attribute \src "ls180.v:6326.45-6326.152" - cell $and $and$ls180.v:6326$2014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6326$2012_Y - connect \B $eq$ls180.v:6326$2013_Y - connect \Y $and$ls180.v:6326$2014_Y - end - attribute \src "ls180.v:6327.46-6327.104" - cell $and $and$ls180.v:6327$2016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6327$2015_Y - connect \Y $and$ls180.v:6327$2016_Y - end - attribute \src "ls180.v:6327.45-6327.155" - cell $and $and$ls180.v:6327$2018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6327$2016_Y - connect \B $eq$ls180.v:6327$2017_Y - connect \Y $and$ls180.v:6327$2018_Y - end - attribute \src "ls180.v:6350.39-6350.94" - cell $and $and$ls180.v:6350$2021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6350$2021_Y - end - attribute \src "ls180.v:6350.38-6350.145" - cell $and $and$ls180.v:6350$2023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6350$2021_Y - connect \B $eq$ls180.v:6350$2022_Y - connect \Y $and$ls180.v:6350$2023_Y - end - attribute \src "ls180.v:6351.39-6351.97" - cell $and $and$ls180.v:6351$2025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6351$2024_Y - connect \Y $and$ls180.v:6351$2025_Y - end - attribute \src "ls180.v:6351.38-6351.148" - cell $and $and$ls180.v:6351$2027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6351$2025_Y - connect \B $eq$ls180.v:6351$2026_Y - connect \Y $and$ls180.v:6351$2027_Y - end - attribute \src "ls180.v:6353.39-6353.94" - cell $and $and$ls180.v:6353$2028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6353$2028_Y - end - attribute \src "ls180.v:6353.38-6353.145" - cell $and $and$ls180.v:6353$2030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6353$2028_Y - connect \B $eq$ls180.v:6353$2029_Y - connect \Y $and$ls180.v:6353$2030_Y - end - attribute \src "ls180.v:6354.39-6354.97" - cell $and $and$ls180.v:6354$2032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6354$2031_Y - connect \Y $and$ls180.v:6354$2032_Y - end - attribute \src "ls180.v:6354.38-6354.148" - cell $and $and$ls180.v:6354$2034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6354$2032_Y - connect \B $eq$ls180.v:6354$2033_Y - connect \Y $and$ls180.v:6354$2034_Y - end - attribute \src "ls180.v:6356.39-6356.94" - cell $and $and$ls180.v:6356$2035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6356$2035_Y - end - attribute \src "ls180.v:6356.38-6356.145" - cell $and $and$ls180.v:6356$2037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6356$2035_Y - connect \B $eq$ls180.v:6356$2036_Y - connect \Y $and$ls180.v:6356$2037_Y - end - attribute \src "ls180.v:6357.39-6357.97" - cell $and $and$ls180.v:6357$2039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6357$2038_Y - connect \Y $and$ls180.v:6357$2039_Y - end - attribute \src "ls180.v:6357.38-6357.148" - cell $and $and$ls180.v:6357$2041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6357$2039_Y - connect \B $eq$ls180.v:6357$2040_Y - connect \Y $and$ls180.v:6357$2041_Y - end - attribute \src "ls180.v:6359.39-6359.94" - cell $and $and$ls180.v:6359$2042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6359$2042_Y - end - attribute \src "ls180.v:6359.38-6359.145" - cell $and $and$ls180.v:6359$2044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6359$2042_Y - connect \B $eq$ls180.v:6359$2043_Y - connect \Y $and$ls180.v:6359$2044_Y - end - attribute \src "ls180.v:6360.39-6360.97" - cell $and $and$ls180.v:6360$2046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6360$2045_Y - connect \Y $and$ls180.v:6360$2046_Y - end - attribute \src "ls180.v:6360.38-6360.148" - cell $and $and$ls180.v:6360$2048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6360$2046_Y - connect \B $eq$ls180.v:6360$2047_Y - connect \Y $and$ls180.v:6360$2048_Y - end - attribute \src "ls180.v:6362.41-6362.96" - cell $and $and$ls180.v:6362$2049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6362$2049_Y - end - attribute \src "ls180.v:6362.40-6362.147" - cell $and $and$ls180.v:6362$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6362$2049_Y - connect \B $eq$ls180.v:6362$2050_Y - connect \Y $and$ls180.v:6362$2051_Y - end - attribute \src "ls180.v:6363.41-6363.99" - cell $and $and$ls180.v:6363$2053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6363$2052_Y - connect \Y $and$ls180.v:6363$2053_Y - end - attribute \src "ls180.v:6363.40-6363.150" - cell $and $and$ls180.v:6363$2055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6363$2053_Y - connect \B $eq$ls180.v:6363$2054_Y - connect \Y $and$ls180.v:6363$2055_Y - end - attribute \src "ls180.v:6365.41-6365.96" - cell $and $and$ls180.v:6365$2056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6365$2056_Y - end - attribute \src "ls180.v:6365.40-6365.147" - cell $and $and$ls180.v:6365$2058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6365$2056_Y - connect \B $eq$ls180.v:6365$2057_Y - connect \Y $and$ls180.v:6365$2058_Y - end - attribute \src "ls180.v:6366.41-6366.99" - cell $and $and$ls180.v:6366$2060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6366$2059_Y - connect \Y $and$ls180.v:6366$2060_Y - end - attribute \src "ls180.v:6366.40-6366.150" - cell $and $and$ls180.v:6366$2062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6366$2060_Y - connect \B $eq$ls180.v:6366$2061_Y - connect \Y $and$ls180.v:6366$2062_Y - end - attribute \src "ls180.v:6368.41-6368.96" - cell $and $and$ls180.v:6368$2063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6368$2063_Y - end - attribute \src "ls180.v:6368.40-6368.147" - cell $and $and$ls180.v:6368$2065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6368$2063_Y - connect \B $eq$ls180.v:6368$2064_Y - connect \Y $and$ls180.v:6368$2065_Y - end - attribute \src "ls180.v:6369.41-6369.99" - cell $and $and$ls180.v:6369$2067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6369$2066_Y - connect \Y $and$ls180.v:6369$2067_Y - end - attribute \src "ls180.v:6369.40-6369.150" - cell $and $and$ls180.v:6369$2069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6369$2067_Y - connect \B $eq$ls180.v:6369$2068_Y - connect \Y $and$ls180.v:6369$2069_Y - end - attribute \src "ls180.v:6371.41-6371.96" - cell $and $and$ls180.v:6371$2070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6371$2070_Y - end - attribute \src "ls180.v:6371.40-6371.147" - cell $and $and$ls180.v:6371$2072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6371$2070_Y - connect \B $eq$ls180.v:6371$2071_Y - connect \Y $and$ls180.v:6371$2072_Y - end - attribute \src "ls180.v:6372.41-6372.99" - cell $and $and$ls180.v:6372$2074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6372$2073_Y - connect \Y $and$ls180.v:6372$2074_Y - end - attribute \src "ls180.v:6372.40-6372.150" - cell $and $and$ls180.v:6372$2076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6372$2074_Y - connect \B $eq$ls180.v:6372$2075_Y - connect \Y $and$ls180.v:6372$2076_Y - end - attribute \src "ls180.v:6374.37-6374.92" - cell $and $and$ls180.v:6374$2077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6374$2077_Y - end - attribute \src "ls180.v:6374.36-6374.143" - cell $and $and$ls180.v:6374$2079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6374$2077_Y - connect \B $eq$ls180.v:6374$2078_Y - connect \Y $and$ls180.v:6374$2079_Y - end - attribute \src "ls180.v:6375.37-6375.95" - cell $and $and$ls180.v:6375$2081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6375$2080_Y - connect \Y $and$ls180.v:6375$2081_Y - end - attribute \src "ls180.v:6375.36-6375.146" - cell $and $and$ls180.v:6375$2083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6375$2081_Y - connect \B $eq$ls180.v:6375$2082_Y - connect \Y $and$ls180.v:6375$2083_Y - end - attribute \src "ls180.v:6377.47-6377.102" - cell $and $and$ls180.v:6377$2084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6377$2084_Y - end - attribute \src "ls180.v:6377.46-6377.153" - cell $and $and$ls180.v:6377$2086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6377$2084_Y - connect \B $eq$ls180.v:6377$2085_Y - connect \Y $and$ls180.v:6377$2086_Y - end - attribute \src "ls180.v:6378.47-6378.105" - cell $and $and$ls180.v:6378$2088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6378$2087_Y - connect \Y $and$ls180.v:6378$2088_Y - end - attribute \src "ls180.v:6378.46-6378.156" - cell $and $and$ls180.v:6378$2090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6378$2088_Y - connect \B $eq$ls180.v:6378$2089_Y - connect \Y $and$ls180.v:6378$2090_Y - end - attribute \src "ls180.v:6380.40-6380.95" - cell $and $and$ls180.v:6380$2091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6380$2091_Y - end - attribute \src "ls180.v:6380.39-6380.147" - cell $and $and$ls180.v:6380$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6380$2091_Y - connect \B $eq$ls180.v:6380$2092_Y - connect \Y $and$ls180.v:6380$2093_Y - end - attribute \src "ls180.v:6381.40-6381.98" - cell $and $and$ls180.v:6381$2095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6381$2094_Y - connect \Y $and$ls180.v:6381$2095_Y - end - attribute \src "ls180.v:6381.39-6381.150" - cell $and $and$ls180.v:6381$2097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6381$2095_Y - connect \B $eq$ls180.v:6381$2096_Y - connect \Y $and$ls180.v:6381$2097_Y - end - attribute \src "ls180.v:6383.40-6383.95" - cell $and $and$ls180.v:6383$2098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6383$2098_Y - end - attribute \src "ls180.v:6383.39-6383.147" - cell $and $and$ls180.v:6383$2100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6383$2098_Y - connect \B $eq$ls180.v:6383$2099_Y - connect \Y $and$ls180.v:6383$2100_Y - end - attribute \src "ls180.v:6384.40-6384.98" - cell $and $and$ls180.v:6384$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6384$2101_Y - connect \Y $and$ls180.v:6384$2102_Y - end - attribute \src "ls180.v:6384.39-6384.150" - cell $and $and$ls180.v:6384$2104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6384$2102_Y - connect \B $eq$ls180.v:6384$2103_Y - connect \Y $and$ls180.v:6384$2104_Y - end - attribute \src "ls180.v:6386.40-6386.95" - cell $and $and$ls180.v:6386$2105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6386$2105_Y - end - attribute \src "ls180.v:6386.39-6386.147" - cell $and $and$ls180.v:6386$2107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6386$2105_Y - connect \B $eq$ls180.v:6386$2106_Y - connect \Y $and$ls180.v:6386$2107_Y - end - attribute \src "ls180.v:6387.40-6387.98" - cell $and $and$ls180.v:6387$2109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6387$2108_Y - connect \Y $and$ls180.v:6387$2109_Y - end - attribute \src "ls180.v:6387.39-6387.150" - cell $and $and$ls180.v:6387$2111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6387$2109_Y - connect \B $eq$ls180.v:6387$2110_Y - connect \Y $and$ls180.v:6387$2111_Y - end - attribute \src "ls180.v:6389.40-6389.95" - cell $and $and$ls180.v:6389$2112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6389$2112_Y - end - attribute \src "ls180.v:6389.39-6389.147" - cell $and $and$ls180.v:6389$2114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6389$2112_Y - connect \B $eq$ls180.v:6389$2113_Y - connect \Y $and$ls180.v:6389$2114_Y - end - attribute \src "ls180.v:6390.40-6390.98" - cell $and $and$ls180.v:6390$2116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6390$2115_Y - connect \Y $and$ls180.v:6390$2116_Y - end - attribute \src "ls180.v:6390.39-6390.150" - cell $and $and$ls180.v:6390$2118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6390$2116_Y - connect \B $eq$ls180.v:6390$2117_Y - connect \Y $and$ls180.v:6390$2118_Y - end - attribute \src "ls180.v:6392.52-6392.107" - cell $and $and$ls180.v:6392$2119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6392$2119_Y - end - attribute \src "ls180.v:6392.51-6392.159" - cell $and $and$ls180.v:6392$2121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6392$2119_Y - connect \B $eq$ls180.v:6392$2120_Y - connect \Y $and$ls180.v:6392$2121_Y - end - attribute \src "ls180.v:6393.52-6393.110" - cell $and $and$ls180.v:6393$2123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6393$2122_Y - connect \Y $and$ls180.v:6393$2123_Y - end - attribute \src "ls180.v:6393.51-6393.162" - cell $and $and$ls180.v:6393$2125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6393$2123_Y - connect \B $eq$ls180.v:6393$2124_Y - connect \Y $and$ls180.v:6393$2125_Y - end - attribute \src "ls180.v:6395.53-6395.108" - cell $and $and$ls180.v:6395$2126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6395$2126_Y - end - attribute \src "ls180.v:6395.52-6395.160" - cell $and $and$ls180.v:6395$2128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$2126_Y - connect \B $eq$ls180.v:6395$2127_Y - connect \Y $and$ls180.v:6395$2128_Y - end - attribute \src "ls180.v:6396.53-6396.111" - cell $and $and$ls180.v:6396$2130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6396$2129_Y - connect \Y $and$ls180.v:6396$2130_Y - end - attribute \src "ls180.v:6396.52-6396.163" - cell $and $and$ls180.v:6396$2132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6396$2130_Y - connect \B $eq$ls180.v:6396$2131_Y - connect \Y $and$ls180.v:6396$2132_Y - end - attribute \src "ls180.v:6398.44-6398.99" - cell $and $and$ls180.v:6398$2133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6398$2133_Y - end - attribute \src "ls180.v:6398.43-6398.151" - cell $and $and$ls180.v:6398$2135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6398$2133_Y - connect \B $eq$ls180.v:6398$2134_Y - connect \Y $and$ls180.v:6398$2135_Y - end - attribute \src "ls180.v:6399.44-6399.102" - cell $and $and$ls180.v:6399$2137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6399$2136_Y - connect \Y $and$ls180.v:6399$2137_Y - end - attribute \src "ls180.v:6399.43-6399.154" - cell $and $and$ls180.v:6399$2139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6399$2137_Y - connect \B $eq$ls180.v:6399$2138_Y - connect \Y $and$ls180.v:6399$2139_Y - end - attribute \src "ls180.v:6418.30-6418.85" - cell $and $and$ls180.v:6418$2141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6418$2141_Y - end - attribute \src "ls180.v:6418.29-6418.136" - cell $and $and$ls180.v:6418$2143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6418$2141_Y - connect \B $eq$ls180.v:6418$2142_Y - connect \Y $and$ls180.v:6418$2143_Y - end - attribute \src "ls180.v:6419.30-6419.88" - cell $and $and$ls180.v:6419$2145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6419$2144_Y - connect \Y $and$ls180.v:6419$2145_Y - end - attribute \src "ls180.v:6419.29-6419.139" - cell $and $and$ls180.v:6419$2147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6419$2145_Y - connect \B $eq$ls180.v:6419$2146_Y - connect \Y $and$ls180.v:6419$2147_Y - end - attribute \src "ls180.v:6421.40-6421.95" - cell $and $and$ls180.v:6421$2148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6421$2148_Y - end - attribute \src "ls180.v:6421.39-6421.146" - cell $and $and$ls180.v:6421$2150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6421$2148_Y - connect \B $eq$ls180.v:6421$2149_Y - connect \Y $and$ls180.v:6421$2150_Y - end - attribute \src "ls180.v:6422.40-6422.98" - cell $and $and$ls180.v:6422$2152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6422$2151_Y - connect \Y $and$ls180.v:6422$2152_Y - end - attribute \src "ls180.v:6422.39-6422.149" - cell $and $and$ls180.v:6422$2154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6422$2152_Y - connect \B $eq$ls180.v:6422$2153_Y - connect \Y $and$ls180.v:6422$2154_Y - end - attribute \src "ls180.v:6424.41-6424.96" - cell $and $and$ls180.v:6424$2155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6424$2155_Y - end - attribute \src "ls180.v:6424.40-6424.147" - cell $and $and$ls180.v:6424$2157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6424$2155_Y - connect \B $eq$ls180.v:6424$2156_Y - connect \Y $and$ls180.v:6424$2157_Y - end - attribute \src "ls180.v:6425.41-6425.99" - cell $and $and$ls180.v:6425$2159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6425$2158_Y - connect \Y $and$ls180.v:6425$2159_Y - end - attribute \src "ls180.v:6425.40-6425.150" - cell $and $and$ls180.v:6425$2161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6425$2159_Y - connect \B $eq$ls180.v:6425$2160_Y - connect \Y $and$ls180.v:6425$2161_Y - end - attribute \src "ls180.v:6427.45-6427.100" - cell $and $and$ls180.v:6427$2162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6427$2162_Y - end - attribute \src "ls180.v:6427.44-6427.151" - cell $and $and$ls180.v:6427$2164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6427$2162_Y - connect \B $eq$ls180.v:6427$2163_Y - connect \Y $and$ls180.v:6427$2164_Y - end - attribute \src "ls180.v:6428.45-6428.103" - cell $and $and$ls180.v:6428$2166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6428$2165_Y - connect \Y $and$ls180.v:6428$2166_Y - end - attribute \src "ls180.v:6428.44-6428.154" - cell $and $and$ls180.v:6428$2168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6428$2166_Y - connect \B $eq$ls180.v:6428$2167_Y - connect \Y $and$ls180.v:6428$2168_Y - end - attribute \src "ls180.v:6430.46-6430.101" - cell $and $and$ls180.v:6430$2169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6430$2169_Y - end - attribute \src "ls180.v:6430.45-6430.152" - cell $and $and$ls180.v:6430$2171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6430$2169_Y - connect \B $eq$ls180.v:6430$2170_Y - connect \Y $and$ls180.v:6430$2171_Y - end - attribute \src "ls180.v:6431.46-6431.104" - cell $and $and$ls180.v:6431$2173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6431$2172_Y - connect \Y $and$ls180.v:6431$2173_Y - end - attribute \src "ls180.v:6431.45-6431.155" - cell $and $and$ls180.v:6431$2175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6431$2173_Y - connect \B $eq$ls180.v:6431$2174_Y - connect \Y $and$ls180.v:6431$2175_Y - end - attribute \src "ls180.v:6433.44-6433.99" - cell $and $and$ls180.v:6433$2176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6433$2176_Y - end - attribute \src "ls180.v:6433.43-6433.150" - cell $and $and$ls180.v:6433$2178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6433$2176_Y - connect \B $eq$ls180.v:6433$2177_Y - connect \Y $and$ls180.v:6433$2178_Y - end - attribute \src "ls180.v:6434.44-6434.102" - cell $and $and$ls180.v:6434$2180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6434$2179_Y - connect \Y $and$ls180.v:6434$2180_Y - end - attribute \src "ls180.v:6434.43-6434.153" - cell $and $and$ls180.v:6434$2182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6434$2180_Y - connect \B $eq$ls180.v:6434$2181_Y - connect \Y $and$ls180.v:6434$2182_Y - end - attribute \src "ls180.v:6436.41-6436.96" - cell $and $and$ls180.v:6436$2183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6436$2183_Y - end - attribute \src "ls180.v:6436.40-6436.147" - cell $and $and$ls180.v:6436$2185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6436$2183_Y - connect \B $eq$ls180.v:6436$2184_Y - connect \Y $and$ls180.v:6436$2185_Y - end - attribute \src "ls180.v:6437.41-6437.99" - cell $and $and$ls180.v:6437$2187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6437$2186_Y - connect \Y $and$ls180.v:6437$2187_Y - end - attribute \src "ls180.v:6437.40-6437.150" - cell $and $and$ls180.v:6437$2189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6437$2187_Y - connect \B $eq$ls180.v:6437$2188_Y - connect \Y $and$ls180.v:6437$2189_Y - end - attribute \src "ls180.v:6439.40-6439.95" - cell $and $and$ls180.v:6439$2190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6439$2190_Y - end - attribute \src "ls180.v:6439.39-6439.146" - cell $and $and$ls180.v:6439$2192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6439$2190_Y - connect \B $eq$ls180.v:6439$2191_Y - connect \Y $and$ls180.v:6439$2192_Y - end - attribute \src "ls180.v:6440.40-6440.98" - cell $and $and$ls180.v:6440$2194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6440$2193_Y - connect \Y $and$ls180.v:6440$2194_Y - end - attribute \src "ls180.v:6440.39-6440.149" - cell $and $and$ls180.v:6440$2196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6440$2194_Y - connect \B $eq$ls180.v:6440$2195_Y - connect \Y $and$ls180.v:6440$2196_Y - end - attribute \src "ls180.v:6452.46-6452.101" - cell $and $and$ls180.v:6452$2198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6452$2198_Y - end - attribute \src "ls180.v:6452.45-6452.152" - cell $and $and$ls180.v:6452$2200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6452$2198_Y - connect \B $eq$ls180.v:6452$2199_Y - connect \Y $and$ls180.v:6452$2200_Y - end - attribute \src "ls180.v:6453.46-6453.104" - cell $and $and$ls180.v:6453$2202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6453$2201_Y - connect \Y $and$ls180.v:6453$2202_Y - end - attribute \src "ls180.v:6453.45-6453.155" - cell $and $and$ls180.v:6453$2204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6453$2202_Y - connect \B $eq$ls180.v:6453$2203_Y - connect \Y $and$ls180.v:6453$2204_Y - end - attribute \src "ls180.v:6455.46-6455.101" - cell $and $and$ls180.v:6455$2205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6455$2205_Y - end - attribute \src "ls180.v:6455.45-6455.152" - cell $and $and$ls180.v:6455$2207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6455$2205_Y - connect \B $eq$ls180.v:6455$2206_Y - connect \Y $and$ls180.v:6455$2207_Y - end - attribute \src "ls180.v:6456.46-6456.104" - cell $and $and$ls180.v:6456$2209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6456$2208_Y - connect \Y $and$ls180.v:6456$2209_Y - end - attribute \src "ls180.v:6456.45-6456.155" - cell $and $and$ls180.v:6456$2211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6456$2209_Y - connect \B $eq$ls180.v:6456$2210_Y - connect \Y $and$ls180.v:6456$2211_Y - end - attribute \src "ls180.v:6458.46-6458.101" - cell $and $and$ls180.v:6458$2212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6458$2212_Y - end - attribute \src "ls180.v:6458.45-6458.152" - cell $and $and$ls180.v:6458$2214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6458$2212_Y - connect \B $eq$ls180.v:6458$2213_Y - connect \Y $and$ls180.v:6458$2214_Y - end - attribute \src "ls180.v:6459.46-6459.104" - cell $and $and$ls180.v:6459$2216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6459$2215_Y - connect \Y $and$ls180.v:6459$2216_Y - end - attribute \src "ls180.v:6459.45-6459.155" - cell $and $and$ls180.v:6459$2218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6459$2216_Y - connect \B $eq$ls180.v:6459$2217_Y - connect \Y $and$ls180.v:6459$2218_Y - end - attribute \src "ls180.v:6461.46-6461.101" - cell $and $and$ls180.v:6461$2219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6461$2219_Y - end - attribute \src "ls180.v:6461.45-6461.152" - cell $and $and$ls180.v:6461$2221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6461$2219_Y - connect \B $eq$ls180.v:6461$2220_Y - connect \Y $and$ls180.v:6461$2221_Y - end - attribute \src "ls180.v:6462.46-6462.104" - cell $and $and$ls180.v:6462$2223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6462$2222_Y - connect \Y $and$ls180.v:6462$2223_Y - end - attribute \src "ls180.v:6462.45-6462.155" - cell $and $and$ls180.v:6462$2225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6462$2223_Y - connect \B $eq$ls180.v:6462$2224_Y - connect \Y $and$ls180.v:6462$2225_Y - end - attribute \src "ls180.v:6843.109-6843.178" - cell $and $and$ls180.v:6843$2263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6843$2262_Y - connect \Y $and$ls180.v:6843$2263_Y - end - attribute \src "ls180.v:6843.184-6843.253" - cell $and $and$ls180.v:6843$2266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6843$2265_Y - connect \Y $and$ls180.v:6843$2266_Y - end - attribute \src "ls180.v:6843.259-6843.328" - cell $and $and$ls180.v:6843$2269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6843$2268_Y - connect \Y $and$ls180.v:6843$2269_Y - end - attribute \src "ls180.v:6843.40-6843.331" - cell $and $and$ls180.v:6843$2272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6843$2261_Y - connect \B $not$ls180.v:6843$2271_Y - connect \Y $and$ls180.v:6843$2272_Y - end - attribute \src "ls180.v:6843.39-6843.354" - cell $and $and$ls180.v:6843$2273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6843$2272_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6843$2273_Y - end - attribute \src "ls180.v:6867.109-6867.178" - cell $and $and$ls180.v:6867$2279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6867$2278_Y - connect \Y $and$ls180.v:6867$2279_Y - end - attribute \src "ls180.v:6867.184-6867.253" - cell $and $and$ls180.v:6867$2282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6867$2281_Y - connect \Y $and$ls180.v:6867$2282_Y - end - attribute \src "ls180.v:6867.259-6867.328" - cell $and $and$ls180.v:6867$2285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6867$2284_Y - connect \Y $and$ls180.v:6867$2285_Y - end - attribute \src "ls180.v:6867.40-6867.331" - cell $and $and$ls180.v:6867$2288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6867$2277_Y - connect \B $not$ls180.v:6867$2287_Y - connect \Y $and$ls180.v:6867$2288_Y - end - attribute \src "ls180.v:6867.39-6867.354" - cell $and $and$ls180.v:6867$2289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6867$2288_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6867$2289_Y - end - attribute \src "ls180.v:6891.109-6891.178" - cell $and $and$ls180.v:6891$2295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6891$2294_Y - connect \Y $and$ls180.v:6891$2295_Y - end - attribute \src "ls180.v:6891.184-6891.253" - cell $and $and$ls180.v:6891$2298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6891$2297_Y - connect \Y $and$ls180.v:6891$2298_Y - end - attribute \src "ls180.v:6891.259-6891.328" - cell $and $and$ls180.v:6891$2301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6891$2300_Y - connect \Y $and$ls180.v:6891$2301_Y - end - attribute \src "ls180.v:6891.40-6891.331" - cell $and $and$ls180.v:6891$2304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6891$2293_Y - connect \B $not$ls180.v:6891$2303_Y - connect \Y $and$ls180.v:6891$2304_Y - end - attribute \src "ls180.v:6891.39-6891.354" - cell $and $and$ls180.v:6891$2305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6891$2304_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6891$2305_Y - end - attribute \src "ls180.v:6915.109-6915.178" - cell $and $and$ls180.v:6915$2311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6915$2310_Y - connect \Y $and$ls180.v:6915$2311_Y - end - attribute \src "ls180.v:6915.184-6915.253" - cell $and $and$ls180.v:6915$2314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6915$2313_Y - connect \Y $and$ls180.v:6915$2314_Y - end - attribute \src "ls180.v:6915.259-6915.328" - cell $and $and$ls180.v:6915$2317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6915$2316_Y - connect \Y $and$ls180.v:6915$2317_Y - end - attribute \src "ls180.v:6915.40-6915.331" - cell $and $and$ls180.v:6915$2320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6915$2309_Y - connect \B $not$ls180.v:6915$2319_Y - connect \Y $and$ls180.v:6915$2320_Y - end - attribute \src "ls180.v:6915.39-6915.354" - cell $and $and$ls180.v:6915$2321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6915$2320_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6915$2321_Y - end - attribute \src "ls180.v:7120.39-7120.104" - cell $and $and$ls180.v:7120$2333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7120$2333_Y - end - attribute \src "ls180.v:7120.38-7120.145" - cell $and $and$ls180.v:7120$2334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7120$2333_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7120$2334_Y - end - attribute \src "ls180.v:7123.39-7123.104" - cell $and $and$ls180.v:7123$2335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7123$2335_Y - end - attribute \src "ls180.v:7123.38-7123.145" - cell $and $and$ls180.v:7123$2336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7123$2335_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7123$2336_Y - end - attribute \src "ls180.v:7126.39-7126.82" - cell $and $and$ls180.v:7126$2337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7126$2337_Y - end - attribute \src "ls180.v:7126.38-7126.112" - cell $and $and$ls180.v:7126$2338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7126$2337_Y - connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7126$2338_Y - end - attribute \src "ls180.v:7137.39-7137.104" - cell $and $and$ls180.v:7137$2340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7137$2340_Y - end - attribute \src "ls180.v:7137.38-7137.145" - cell $and $and$ls180.v:7137$2341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7137$2340_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7137$2341_Y - end - attribute \src "ls180.v:7140.39-7140.104" - cell $and $and$ls180.v:7140$2342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7140$2342_Y - end - attribute \src "ls180.v:7140.38-7140.145" - cell $and $and$ls180.v:7140$2343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7140$2342_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7140$2343_Y - end - attribute \src "ls180.v:7143.39-7143.82" - cell $and $and$ls180.v:7143$2344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7143$2344_Y - end - attribute \src "ls180.v:7143.38-7143.112" - cell $and $and$ls180.v:7143$2345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7143$2344_Y - connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7143$2345_Y - end - attribute \src "ls180.v:7154.39-7154.104" - cell $and $and$ls180.v:7154$2347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7154$2347_Y - end - attribute \src "ls180.v:7154.38-7154.144" - cell $and $and$ls180.v:7154$2348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7154$2347_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7154$2348_Y - end - attribute \src "ls180.v:7157.39-7157.104" - cell $and $and$ls180.v:7157$2349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7157$2349_Y - end - attribute \src "ls180.v:7157.38-7157.144" - cell $and $and$ls180.v:7157$2350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7157$2349_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7157$2350_Y - end - attribute \src "ls180.v:7160.39-7160.82" - cell $and $and$ls180.v:7160$2351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7160$2351_Y - end - attribute \src "ls180.v:7160.38-7160.111" - cell $and $and$ls180.v:7160$2352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7160$2351_Y - connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7160$2352_Y - end - attribute \src "ls180.v:7171.39-7171.104" - cell $and $and$ls180.v:7171$2354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7171$2354_Y - end - attribute \src "ls180.v:7171.38-7171.149" - cell $and $and$ls180.v:7171$2355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7171$2354_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7171$2355_Y - end - attribute \src "ls180.v:7174.39-7174.104" - cell $and $and$ls180.v:7174$2356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7174$2356_Y - end - attribute \src "ls180.v:7174.38-7174.149" - cell $and $and$ls180.v:7174$2357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7174$2356_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7174$2357_Y - end - attribute \src "ls180.v:7177.39-7177.82" - cell $and $and$ls180.v:7177$2358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7177$2358_Y - end - attribute \src "ls180.v:7177.38-7177.116" - cell $and $and$ls180.v:7177$2359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7177$2358_Y - connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7177$2359_Y - end - attribute \src "ls180.v:7188.39-7188.104" - cell $and $and$ls180.v:7188$2361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7188$2361_Y - end - attribute \src "ls180.v:7188.38-7188.150" - cell $and $and$ls180.v:7188$2362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7188$2361_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7188$2362_Y - end - attribute \src "ls180.v:7191.39-7191.104" - cell $and $and$ls180.v:7191$2363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7191$2363_Y - end - attribute \src "ls180.v:7191.38-7191.150" - cell $and $and$ls180.v:7191$2364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7191$2363_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7191$2364_Y - end - attribute \src "ls180.v:7194.39-7194.82" - cell $and $and$ls180.v:7194$2365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7194$2365_Y - end - attribute \src "ls180.v:7194.38-7194.117" - cell $and $and$ls180.v:7194$2366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7194$2365_Y - connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7194$2366_Y - end - attribute \src "ls180.v:7413.17-7413.67" - cell $and $and$ls180.v:7413$2373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7413$2372_Y - connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7413$2373_Y - end - attribute \src "ls180.v:7504.8-7504.67" - cell $and $and$ls180.v:7504$2416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7504$2416_Y - end - attribute \src "ls180.v:7504.7-7504.102" - cell $and $and$ls180.v:7504$2418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7504$2416_Y - connect \B $not$ls180.v:7504$2417_Y - connect \Y $and$ls180.v:7504$2418_Y - end - attribute \src "ls180.v:7523.7-7523.75" - cell $and $and$ls180.v:7523$2422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7523$2421_Y - connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7523$2422_Y - end - attribute \src "ls180.v:7531.7-7531.56" - cell $and $and$ls180.v:7531$2424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7531$2423_Y - connect \Y $and$ls180.v:7531$2424_Y - end - attribute \src "ls180.v:7559.7-7559.75" - cell $and $and$ls180.v:7559$2431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7559$2430_Y - connect \Y $and$ls180.v:7559$2431_Y - end - attribute \src "ls180.v:7601.8-7601.131" - cell $and $and$ls180.v:7601$2437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7601$2437_Y - end - attribute \src "ls180.v:7601.7-7601.190" - cell $and $and$ls180.v:7601$2439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7601$2437_Y - connect \B $not$ls180.v:7601$2438_Y - connect \Y $and$ls180.v:7601$2439_Y - end - attribute \src "ls180.v:7607.8-7607.131" - cell $and $and$ls180.v:7607$2442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7607$2442_Y - end - attribute \src "ls180.v:7607.7-7607.190" - cell $and $and$ls180.v:7607$2444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7607$2442_Y - connect \B $not$ls180.v:7607$2443_Y - connect \Y $and$ls180.v:7607$2444_Y - end - attribute \src "ls180.v:7647.8-7647.131" - cell $and $and$ls180.v:7647$2453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7647$2453_Y - end - attribute \src "ls180.v:7647.7-7647.190" - cell $and $and$ls180.v:7647$2455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7647$2453_Y - connect \B $not$ls180.v:7647$2454_Y - connect \Y $and$ls180.v:7647$2455_Y - end - attribute \src "ls180.v:7653.8-7653.131" - cell $and $and$ls180.v:7653$2458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7653$2458_Y - end - attribute \src "ls180.v:7653.7-7653.190" - cell $and $and$ls180.v:7653$2460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7653$2458_Y - connect \B $not$ls180.v:7653$2459_Y - connect \Y $and$ls180.v:7653$2460_Y - end - attribute \src "ls180.v:7693.8-7693.131" - cell $and $and$ls180.v:7693$2469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7693$2469_Y - end - attribute \src "ls180.v:7693.7-7693.190" - cell $and $and$ls180.v:7693$2471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7693$2469_Y - connect \B $not$ls180.v:7693$2470_Y - connect \Y $and$ls180.v:7693$2471_Y - end - attribute \src "ls180.v:7699.8-7699.131" - cell $and $and$ls180.v:7699$2474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7699$2474_Y - end - attribute \src "ls180.v:7699.7-7699.190" - cell $and $and$ls180.v:7699$2476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7699$2474_Y - connect \B $not$ls180.v:7699$2475_Y - connect \Y $and$ls180.v:7699$2476_Y - end - attribute \src "ls180.v:7739.8-7739.131" - cell $and $and$ls180.v:7739$2485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7739$2485_Y - end - attribute \src "ls180.v:7739.7-7739.190" - cell $and $and$ls180.v:7739$2487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7739$2485_Y - connect \B $not$ls180.v:7739$2486_Y - connect \Y $and$ls180.v:7739$2487_Y - end - attribute \src "ls180.v:7745.8-7745.131" - cell $and $and$ls180.v:7745$2490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7745$2490_Y - end - attribute \src "ls180.v:7745.7-7745.190" - cell $and $and$ls180.v:7745$2492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7745$2490_Y - connect \B $not$ls180.v:7745$2491_Y - connect \Y $and$ls180.v:7745$2492_Y - end - attribute \src "ls180.v:7942.48-7942.124" - cell $and $and$ls180.v:7942$2517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7942$2516_Y - connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:7942$2517_Y - end - attribute \src "ls180.v:7942.130-7942.206" - cell $and $and$ls180.v:7942$2520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7942$2519_Y - connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:7942$2520_Y - end - attribute \src "ls180.v:7942.212-7942.288" - cell $and $and$ls180.v:7942$2523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7942$2522_Y - connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:7942$2523_Y - end - attribute \src "ls180.v:7942.294-7942.370" - cell $and $and$ls180.v:7942$2526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7942$2525_Y - connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:7942$2526_Y - end - attribute \src "ls180.v:7943.49-7943.125" - cell $and $and$ls180.v:7943$2529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7943$2528_Y - connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:7943$2529_Y - end - attribute \src "ls180.v:7943.131-7943.207" - cell $and $and$ls180.v:7943$2532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7943$2531_Y - connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:7943$2532_Y - end - attribute \src "ls180.v:7943.213-7943.289" - cell $and $and$ls180.v:7943$2535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7943$2534_Y - connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:7943$2535_Y - end - attribute \src "ls180.v:7943.295-7943.371" - cell $and $and$ls180.v:7943$2538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:7943$2537_Y - connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:7943$2538_Y - end - attribute \src "ls180.v:7962.8-7962.49" - cell $and $and$ls180.v:7962$2541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:7962$2541_Y - end - attribute \src "ls180.v:7965.8-7965.53" - cell $and $and$ls180.v:7965$2542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:7965$2542_Y - end - attribute \src "ls180.v:7970.8-7970.59" - cell $and $and$ls180.v:7970$2544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:7970$2543_Y - connect \Y $and$ls180.v:7970$2544_Y - end - attribute \src "ls180.v:7970.7-7970.90" - cell $and $and$ls180.v:7970$2546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7970$2544_Y - connect \B $not$ls180.v:7970$2545_Y - connect \Y $and$ls180.v:7970$2546_Y - end - attribute \src "ls180.v:7976.8-7976.59" - cell $and $and$ls180.v:7976$2547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_uart_clk_txen - connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:7976$2547_Y - end - attribute \src "ls180.v:8000.8-8000.48" - cell $and $and$ls180.v:8000$2554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8000$2553_Y - connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8000$2554_Y - end - attribute \src "ls180.v:8033.7-8033.57" - cell $and $and$ls180.v:8033$2560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8033$2559_Y - connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8033$2560_Y - end - attribute \src "ls180.v:8040.7-8040.57" - cell $and $and$ls180.v:8040$2562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8040$2561_Y - connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8040$2562_Y - end - attribute \src "ls180.v:8050.8-8050.75" - cell $and $and$ls180.v:8050$2563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8050$2563_Y - end - attribute \src "ls180.v:8050.7-8050.107" - cell $and $and$ls180.v:8050$2565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8050$2563_Y - connect \B $not$ls180.v:8050$2564_Y - connect \Y $and$ls180.v:8050$2565_Y - end - attribute \src "ls180.v:8056.8-8056.75" - cell $and $and$ls180.v:8056$2568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8056$2568_Y - end - attribute \src "ls180.v:8056.7-8056.107" - cell $and $and$ls180.v:8056$2570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8056$2568_Y - connect \B $not$ls180.v:8056$2569_Y - connect \Y $and$ls180.v:8056$2570_Y - end - attribute \src "ls180.v:8072.8-8072.75" - cell $and $and$ls180.v:8072$2574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8072$2574_Y - end - attribute \src "ls180.v:8072.7-8072.107" - cell $and $and$ls180.v:8072$2576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8072$2574_Y - connect \B $not$ls180.v:8072$2575_Y - connect \Y $and$ls180.v:8072$2576_Y - end - attribute \src "ls180.v:8078.8-8078.75" - cell $and $and$ls180.v:8078$2579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8078$2579_Y - end - attribute \src "ls180.v:8078.7-8078.107" - cell $and $and$ls180.v:8078$2581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8078$2579_Y - connect \B $not$ls180.v:8078$2580_Y - connect \Y $and$ls180.v:8078$2581_Y - end - attribute \src "ls180.v:8226.7-8226.96" - cell $and $and$ls180.v:8226$2609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_source_valid - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8226$2609_Y - end - attribute \src "ls180.v:8227.8-8227.93" - cell $and $and$ls180.v:8227$2610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8227$2610_Y - end - attribute \src "ls180.v:8235.8-8235.93" - cell $and $and$ls180.v:8235$2611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8235$2611_Y - end - attribute \src "ls180.v:8307.7-8307.98" - cell $and $and$ls180.v:8307$2621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_source_valid - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8307$2621_Y - end - attribute \src "ls180.v:8308.8-8308.95" - cell $and $and$ls180.v:8308$2622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8308$2622_Y - end - attribute \src "ls180.v:8316.8-8316.95" - cell $and $and$ls180.v:8316$2623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8316$2623_Y - end - attribute \src "ls180.v:8386.7-8386.100" - cell $and $and$ls180.v:8386$2633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_source_valid - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8386$2633_Y - end - attribute \src "ls180.v:8387.8-8387.97" - cell $and $and$ls180.v:8387$2634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8387$2634_Y - end - attribute \src "ls180.v:8395.8-8395.97" - cell $and $and$ls180.v:8395$2635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8395$2635_Y - end - attribute \src "ls180.v:8486.7-8486.82" - cell $and $and$ls180.v:8486$2641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8486$2641_Y - end - attribute \src "ls180.v:8489.7-8489.82" - cell $and $and$ls180.v:8489$2642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8489$2642_Y - end - attribute \src "ls180.v:8492.7-8492.82" - cell $and $and$ls180.v:8492$2643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8492$2643_Y - end - attribute \src "ls180.v:8495.7-8495.82" - cell $and $and$ls180.v:8495$2644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8495$2644_Y - end - attribute \src "ls180.v:8498.7-8498.82" - cell $and $and$ls180.v:8498$2645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8498$2645_Y - end - attribute \src "ls180.v:8503.7-8503.82" - cell $and $and$ls180.v:8503$2646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8503$2646_Y - end - attribute \src "ls180.v:8508.7-8508.82" - cell $and $and$ls180.v:8508$2647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8508$2647_Y - end - attribute \src "ls180.v:8513.7-8513.82" - cell $and $and$ls180.v:8513$2648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8513$2648_Y - end - attribute \src "ls180.v:8518.7-8518.82" - cell $and $and$ls180.v:8518$2649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8518$2649_Y - end - attribute \src "ls180.v:8583.8-8583.83" - cell $and $and$ls180.v:8583$2652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8583$2652_Y - end - attribute \src "ls180.v:8583.7-8583.119" - cell $and $and$ls180.v:8583$2654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8583$2652_Y - connect \B $not$ls180.v:8583$2653_Y - connect \Y $and$ls180.v:8583$2654_Y - end - attribute \src "ls180.v:8589.8-8589.83" - cell $and $and$ls180.v:8589$2657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8589$2657_Y - end - attribute \src "ls180.v:8589.7-8589.119" - cell $and $and$ls180.v:8589$2659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8589$2657_Y - connect \B $not$ls180.v:8589$2658_Y - connect \Y $and$ls180.v:8589$2659_Y - end - attribute \src "ls180.v:8609.7-8609.88" - cell $and $and$ls180.v:8609$2666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_source_valid - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8609$2666_Y - end - attribute \src "ls180.v:8610.8-8610.85" - cell $and $and$ls180.v:8610$2667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8610$2667_Y - end - attribute \src "ls180.v:8618.8-8618.85" - cell $and $and$ls180.v:8618$2668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8618$2668_Y - end - attribute \src "ls180.v:8662.7-8662.88" - cell $and $and$ls180.v:8662$2672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_source_valid - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8662$2672_Y - end - attribute \src "ls180.v:8669.8-8669.83" - cell $and $and$ls180.v:8669$2674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8669$2674_Y - end - attribute \src "ls180.v:8669.7-8669.119" - cell $and $and$ls180.v:8669$2676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8669$2674_Y - connect \B $not$ls180.v:8669$2675_Y - connect \Y $and$ls180.v:8669$2676_Y - end - attribute \src "ls180.v:8675.8-8675.83" - cell $and $and$ls180.v:8675$2679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8675$2679_Y - end - attribute \src "ls180.v:8675.7-8675.119" - cell $and $and$ls180.v:8675$2681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8675$2679_Y - connect \B $not$ls180.v:8675$2680_Y - connect \Y $and$ls180.v:8675$2681_Y - end - attribute \src "ls180.v:2811.42-2811.101" - cell $eq $eq$ls180.v:2811$18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2811$18_Y - end - attribute \src "ls180.v:2818.11-2818.54" - cell $eq $eq$ls180.v:2818$23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2818$23_Y - end - attribute \src "ls180.v:2871.42-2871.101" - cell $eq $eq$ls180.v:2871$29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2871$29_Y - end - attribute \src "ls180.v:2878.11-2878.54" - cell $eq $eq$ls180.v:2878$34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2878$34_Y - end - attribute \src "ls180.v:2931.42-2931.101" - cell $eq $eq$ls180.v:2931$40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2931$40_Y - end - attribute \src "ls180.v:2938.11-2938.54" - cell $eq $eq$ls180.v:2938$45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2938$45_Y - end - attribute \src "ls180.v:3124.34-3124.65" - cell $eq $eq$ls180.v:3124$73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_count1 - connect \B 1'0 - connect \Y $eq$ls180.v:3124$73_Y - end - attribute \src "ls180.v:3128.68-3128.102" - cell $eq $eq$ls180.v:3128$76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $eq$ls180.v:3128$76_Y - end - attribute \src "ls180.v:3172.43-3172.134" - cell $eq $eq$ls180.v:3172$81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3172$81_Y - end - attribute \src "ls180.v:3189.47-3189.88" - cell $eq $eq$ls180.v:3189$94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3189$94_Y - end - attribute \src "ls180.v:3329.43-3329.134" - cell $eq $eq$ls180.v:3329$111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3329$111_Y - end - attribute \src "ls180.v:3346.47-3346.88" - cell $eq $eq$ls180.v:3346$124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3346$124_Y - end - attribute \src "ls180.v:3486.43-3486.134" - cell $eq $eq$ls180.v:3486$141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3486$141_Y - end - attribute \src "ls180.v:3503.47-3503.88" - cell $eq $eq$ls180.v:3503$154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3503$154_Y - end - attribute \src "ls180.v:3643.43-3643.134" - cell $eq $eq$ls180.v:3643$171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3643$171_Y - end - attribute \src "ls180.v:3660.47-3660.88" - cell $eq $eq$ls180.v:3660$184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3660$184_Y - end - attribute \src "ls180.v:3797.32-3797.56" - cell $eq $eq$ls180.v:3797$231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time0 - connect \B 1'0 - connect \Y $eq$ls180.v:3797$231_Y - end - attribute \src "ls180.v:3798.32-3798.56" - cell $eq $eq$ls180.v:3798$232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_time1 - connect \B 1'0 - connect \Y $eq$ls180.v:3798$232_Y - end - attribute \src "ls180.v:3809.339-3809.418" - cell $eq $eq$ls180.v:3809$246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3809$246_Y - end - attribute \src "ls180.v:3809.423-3809.504" - cell $eq $eq$ls180.v:3809$247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3809$247_Y - end - attribute \src "ls180.v:3810.339-3810.418" - cell $eq $eq$ls180.v:3810$259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3810$259_Y - end - attribute \src "ls180.v:3810.423-3810.504" - cell $eq $eq$ls180.v:3810$260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3810$260_Y - end - attribute \src "ls180.v:3811.339-3811.418" - cell $eq $eq$ls180.v:3811$272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3811$272_Y - end - attribute \src "ls180.v:3811.423-3811.504" - cell $eq $eq$ls180.v:3811$273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3811$273_Y - end - attribute \src "ls180.v:3812.339-3812.418" - cell $eq $eq$ls180.v:3812$285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3812$285_Y - end - attribute \src "ls180.v:3812.423-3812.504" - cell $eq $eq$ls180.v:3812$286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3812$286_Y - end - attribute \src "ls180.v:3842.339-3842.418" - cell $eq $eq$ls180.v:3842$304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3842$304_Y - end - attribute \src "ls180.v:3842.423-3842.504" - cell $eq $eq$ls180.v:3842$305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3842$305_Y - end - attribute \src "ls180.v:3843.339-3843.418" - cell $eq $eq$ls180.v:3843$317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3843$317_Y - end - attribute \src "ls180.v:3843.423-3843.504" - cell $eq $eq$ls180.v:3843$318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3843$318_Y - end - attribute \src "ls180.v:3844.339-3844.418" - cell $eq $eq$ls180.v:3844$330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3844$330_Y - end - attribute \src "ls180.v:3844.423-3844.504" - cell $eq $eq$ls180.v:3844$331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3844$331_Y - end - attribute \src "ls180.v:3845.339-3845.418" - cell $eq $eq$ls180.v:3845$343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3845$343_Y - end - attribute \src "ls180.v:3845.423-3845.504" - cell $eq $eq$ls180.v:3845$344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3845$344_Y - end - attribute \src "ls180.v:3874.78-3874.113" - cell $eq $eq$ls180.v:3874$353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3874$353_Y - end - attribute \src "ls180.v:3877.78-3877.113" - cell $eq $eq$ls180.v:3877$356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3877$356_Y - end - attribute \src "ls180.v:3883.78-3883.113" - cell $eq $eq$ls180.v:3883$360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3883$360_Y - end - attribute \src "ls180.v:3886.78-3886.113" - cell $eq $eq$ls180.v:3886$363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3886$363_Y - end - attribute \src "ls180.v:3892.78-3892.113" - cell $eq $eq$ls180.v:3892$367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3892$367_Y - end - attribute \src "ls180.v:3895.78-3895.113" - cell $eq $eq$ls180.v:3895$370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3895$370_Y - end - attribute \src "ls180.v:3901.78-3901.113" - cell $eq $eq$ls180.v:3901$374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3901$374_Y - end - attribute \src "ls180.v:3904.78-3904.113" - cell $eq $eq$ls180.v:3904$377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3904$377_Y - end - attribute \src "ls180.v:3985.42-3985.82" - cell $eq $eq$ls180.v:3985$400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:3985$400_Y - end - attribute \src "ls180.v:3985.145-3985.178" - cell $eq $eq$ls180.v:3985$401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3985$401_Y - end - attribute \src "ls180.v:3985.220-3985.253" - cell $eq $eq$ls180.v:3985$404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3985$404_Y - end - attribute \src "ls180.v:3985.295-3985.328" - cell $eq $eq$ls180.v:3985$407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3985$407_Y - end - attribute \src "ls180.v:3990.42-3990.82" - cell $eq $eq$ls180.v:3990$416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:3990$416_Y - end - attribute \src "ls180.v:3990.145-3990.178" - cell $eq $eq$ls180.v:3990$417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3990$417_Y - end - attribute \src "ls180.v:3990.220-3990.253" - cell $eq $eq$ls180.v:3990$420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3990$420_Y - end - attribute \src "ls180.v:3990.295-3990.328" - cell $eq $eq$ls180.v:3990$423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3990$423_Y - end - attribute \src "ls180.v:3995.42-3995.82" - cell $eq $eq$ls180.v:3995$432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:3995$432_Y - end - attribute \src "ls180.v:3995.145-3995.178" - cell $eq $eq$ls180.v:3995$433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3995$433_Y - end - attribute \src "ls180.v:3995.220-3995.253" - cell $eq $eq$ls180.v:3995$436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3995$436_Y - end - attribute \src "ls180.v:3995.295-3995.328" - cell $eq $eq$ls180.v:3995$439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3995$439_Y - end - attribute \src "ls180.v:4000.42-4000.82" - cell $eq $eq$ls180.v:4000$448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4000$448_Y - end - attribute \src "ls180.v:4000.145-4000.178" - cell $eq $eq$ls180.v:4000$449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4000$449_Y - end - attribute \src "ls180.v:4000.220-4000.253" - cell $eq $eq$ls180.v:4000$452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4000$452_Y - end - attribute \src "ls180.v:4000.295-4000.328" - cell $eq $eq$ls180.v:4000$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4000$455_Y - end - attribute \src "ls180.v:4005.44-4005.77" - cell $eq $eq$ls180.v:4005$464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$464_Y - end - attribute \src "ls180.v:4005.83-4005.123" - cell $eq $eq$ls180.v:4005$465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:4005$465_Y - end - attribute \src "ls180.v:4005.186-4005.219" - cell $eq $eq$ls180.v:4005$466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$466_Y - end - attribute \src "ls180.v:4005.261-4005.294" - cell $eq $eq$ls180.v:4005$469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$469_Y - end - attribute \src "ls180.v:4005.336-4005.369" - cell $eq $eq$ls180.v:4005$472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$472_Y - end - attribute \src "ls180.v:4005.418-4005.451" - cell $eq $eq$ls180.v:4005$480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$480_Y - end - attribute \src "ls180.v:4005.457-4005.497" - cell $eq $eq$ls180.v:4005$481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:4005$481_Y - end - attribute \src "ls180.v:4005.560-4005.593" - cell $eq $eq$ls180.v:4005$482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$482_Y - end - attribute \src "ls180.v:4005.635-4005.668" - cell $eq $eq$ls180.v:4005$485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$485_Y - end - attribute \src "ls180.v:4005.710-4005.743" - cell $eq $eq$ls180.v:4005$488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$488_Y - end - attribute \src "ls180.v:4005.792-4005.825" - cell $eq $eq$ls180.v:4005$496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$496_Y - end - attribute \src "ls180.v:4005.831-4005.871" - cell $eq $eq$ls180.v:4005$497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:4005$497_Y - end - attribute \src "ls180.v:4005.934-4005.967" - cell $eq $eq$ls180.v:4005$498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$498_Y - end - attribute \src "ls180.v:4005.1009-4005.1042" - cell $eq $eq$ls180.v:4005$501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$501_Y - end - attribute \src "ls180.v:4005.1084-4005.1117" - cell $eq $eq$ls180.v:4005$504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$504_Y - end - attribute \src "ls180.v:4005.1166-4005.1199" - cell $eq $eq$ls180.v:4005$512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$512_Y - end - attribute \src "ls180.v:4005.1205-4005.1245" - cell $eq $eq$ls180.v:4005$513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4005$513_Y - end - attribute \src "ls180.v:4005.1308-4005.1341" - cell $eq $eq$ls180.v:4005$514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$514_Y - end - attribute \src "ls180.v:4005.1383-4005.1416" - cell $eq $eq$ls180.v:4005$517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$517_Y - end - attribute \src "ls180.v:4005.1458-4005.1491" - cell $eq $eq$ls180.v:4005$520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4005$520_Y - end - attribute \src "ls180.v:4064.29-4064.57" - cell $eq $eq$ls180.v:4064$533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_sel - connect \B 1'0 - connect \Y $eq$ls180.v:4064$533_Y - end - attribute \src "ls180.v:4071.11-4071.41" - cell $eq $eq$ls180.v:4071$538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $eq$ls180.v:4071$538_Y - end - attribute \src "ls180.v:4228.37-4228.111" - cell $eq $eq$ls180.v:4228$603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4228$602_Y - connect \Y $eq$ls180.v:4228$603_Y - end - attribute \src "ls180.v:4229.37-4229.105" - cell $eq $eq$ls180.v:4229$605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4229$604_Y - connect \Y $eq$ls180.v:4229$605_Y - end - attribute \src "ls180.v:4256.10-4256.67" - cell $eq $eq$ls180.v:4256$609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4256$608_Y - connect \Y $eq$ls180.v:4256$609_Y - end - attribute \src "ls180.v:4286.35-4286.108" - cell $eq $eq$ls180.v:4286$611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4286$610_Y - connect \Y $eq$ls180.v:4286$611_Y - end - attribute \src "ls180.v:4287.35-4287.102" - cell $eq $eq$ls180.v:4287$613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4287$612_Y - connect \Y $eq$ls180.v:4287$613_Y - end - attribute \src "ls180.v:4315.10-4315.65" - cell $eq $eq$ls180.v:4315$617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4315$616_Y - connect \Y $eq$ls180.v:4315$617_Y - end - attribute \src "ls180.v:4419.10-4419.40" - cell $eq $eq$ls180.v:4419$644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_count - connect \B 7'1001111 - connect \Y $eq$ls180.v:4419$644_Y - end - attribute \src "ls180.v:4476.10-4476.39" - cell $eq $eq$ls180.v:4476$647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4476$647_Y - end - attribute \src "ls180.v:4493.10-4493.39" - cell $eq $eq$ls180.v:4493$649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4493$649_Y - end - attribute \src "ls180.v:4521.38-4521.88" - cell $eq $eq$ls180.v:4521$651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \B 1'0 - connect \Y $eq$ls180.v:4521$651_Y - end - attribute \src "ls180.v:4571.9-4571.40" - cell $eq $eq$ls180.v:4571$661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4571$661_Y - end - attribute \src "ls180.v:4580.36-4580.105" - cell $eq $eq$ls180.v:4580$663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4580$662_Y - connect \Y $eq$ls180.v:4580$663_Y - end - attribute \src "ls180.v:4599.9-4599.40" - cell $eq $eq$ls180.v:4599$667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4599$667_Y - end - attribute \src "ls180.v:4611.10-4611.39" - cell $eq $eq$ls180.v:4611$669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B 3'111 - connect \Y $eq$ls180.v:4611$669_Y - end - attribute \src "ls180.v:4648.39-4648.94" - cell $eq $eq$ls180.v:4648$673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \B 1'0 - connect \Y $eq$ls180.v:4648$673_Y - end - attribute \src "ls180.v:4685.32-4685.89" - cell $eq $eq$ls180.v:4685$682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $eq$ls180.v:4685$682_Y - end - attribute \src "ls180.v:4733.10-4733.40" - cell $eq $eq$ls180.v:4733$686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $eq$ls180.v:4733$686_Y - end - attribute \src "ls180.v:4782.40-4782.98" - cell $eq $eq$ls180.v:4782$688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_payload_data_i - connect \B 1'0 - connect \Y $eq$ls180.v:4782$688_Y - end - attribute \src "ls180.v:4833.9-4833.41" - cell $eq $eq$ls180.v:4833$698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4833$698_Y - end - attribute \src "ls180.v:4842.37-4842.123" - cell $eq $eq$ls180.v:4842$701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4842$700_Y - connect \Y $eq$ls180.v:4842$701_Y - end - attribute \src "ls180.v:4865.9-4865.41" - cell $eq $eq$ls180.v:4865$704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4865$704_Y - end - attribute \src "ls180.v:4875.10-4875.41" - cell $eq $eq$ls180.v:4875$706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B 6'100111 - connect \Y $eq$ls180.v:4875$706_Y - end - attribute \src "ls180.v:5044.9-5044.47" - cell $eq $eq$ls180.v:5044$888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5044$888_Y - end - attribute \src "ls180.v:5074.10-5074.48" - cell $eq $eq$ls180.v:5074$889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5074$889_Y - end - attribute \src "ls180.v:5105.10-5105.78" - cell $eq $eq$ls180.v:5105$894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo0 - connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5105$894_Y - end - attribute \src "ls180.v:5105.83-5105.151" - cell $eq $eq$ls180.v:5105$895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo1 - connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5105$895_Y - end - attribute \src "ls180.v:5105.157-5105.225" - cell $eq $eq$ls180.v:5105$897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo2 - connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5105$897_Y - end - attribute \src "ls180.v:5105.231-5105.299" - cell $eq $eq$ls180.v:5105$899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo3 - connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5105$899_Y - end - attribute \src "ls180.v:5113.7-5113.44" - cell $eq $eq$ls180.v:5113$903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5113$903_Y - end - attribute \src "ls180.v:5123.7-5123.44" - cell $eq $eq$ls180.v:5123$906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5123$906_Y - end - attribute \src "ls180.v:5133.7-5133.44" - cell $eq $eq$ls180.v:5133$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5133$909_Y - end - attribute \src "ls180.v:5143.7-5143.44" - cell $eq $eq$ls180.v:5143$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5143$912_Y - end - attribute \src "ls180.v:5267.36-5267.64" - cell $eq $eq$ls180.v:5267$963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5267$963_Y - end - attribute \src "ls180.v:5273.10-5273.39" - cell $eq $eq$ls180.v:5273$966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_count - connect \B 3'101 - connect \Y $eq$ls180.v:5273$966_Y - end - attribute \src "ls180.v:5274.11-5274.39" - cell $eq $eq$ls180.v:5274$967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5274$967_Y - end - attribute \src "ls180.v:5286.34-5286.63" - cell $eq $eq$ls180.v:5286$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'0 - connect \Y $eq$ls180.v:5286$968_Y - end - attribute \src "ls180.v:5287.9-5287.37" - cell $eq $eq$ls180.v:5287$969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 2'10 - connect \Y $eq$ls180.v:5287$969_Y - end - attribute \src "ls180.v:5294.10-5294.55" - cell $eq $eq$ls180.v:5294$970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5294$970_Y - end - attribute \src "ls180.v:5300.12-5300.41" - cell $eq $eq$ls180.v:5300$971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 2'10 - connect \Y $eq$ls180.v:5300$971_Y - end - attribute \src "ls180.v:5303.13-5303.42" - cell $eq $eq$ls180.v:5303$972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'1 - connect \Y $eq$ls180.v:5303$972_Y - end - attribute \src "ls180.v:5325.10-5325.76" - cell $eq $eq$ls180.v:5325$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5325$976_Y - connect \Y $eq$ls180.v:5325$977_Y - end - attribute \src "ls180.v:5340.35-5340.101" - cell $eq $eq$ls180.v:5340$980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5340$979_Y - connect \Y $eq$ls180.v:5340$980_Y - end - attribute \src "ls180.v:5342.10-5342.56" - cell $eq $eq$ls180.v:5342$981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'0 - connect \Y $eq$ls180.v:5342$981_Y - end - attribute \src "ls180.v:5351.12-5351.78" - cell $eq $eq$ls180.v:5351$985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5351$984_Y - connect \Y $eq$ls180.v:5351$985_Y - end - attribute \src "ls180.v:5358.11-5358.57" - cell $eq $eq$ls180.v:5358$986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5358$986_Y - end - attribute \src "ls180.v:5475.10-5475.105" - cell $eq $eq$ls180.v:5475$1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5475$1002_Y - connect \Y $eq$ls180.v:5475$1003_Y - end - attribute \src "ls180.v:5565.39-5565.106" - cell $eq $eq$ls180.v:5565$1009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5565$1008_Y - connect \Y $eq$ls180.v:5565$1009_Y - end - attribute \src "ls180.v:5595.44-5595.82" - cell $eq $eq$ls180.v:5595$1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 1'0 - connect \Y $eq$ls180.v:5595$1012_Y - end - attribute \src "ls180.v:5596.43-5596.81" - cell $eq $eq$ls180.v:5596$1013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 2'11 - connect \Y $eq$ls180.v:5596$1013_Y - end - attribute \src "ls180.v:5696.85-5696.106" - cell $eq $eq$ls180.v:5696$1029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5696$1029_Y - end - attribute \src "ls180.v:5697.85-5697.106" - cell $eq $eq$ls180.v:5697$1031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5697$1031_Y - end - attribute \src "ls180.v:5698.85-5698.106" - cell $eq $eq$ls180.v:5698$1033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5698$1033_Y - end - attribute \src "ls180.v:5699.57-5699.78" - cell $eq $eq$ls180.v:5699$1035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5699$1035_Y - end - attribute \src "ls180.v:5700.57-5700.78" - cell $eq $eq$ls180.v:5700$1037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5700$1037_Y - end - attribute \src "ls180.v:5701.85-5701.106" - cell $eq $eq$ls180.v:5701$1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5701$1039_Y - end - attribute \src "ls180.v:5702.85-5702.106" - cell $eq $eq$ls180.v:5702$1041 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5702$1041_Y - end - attribute \src "ls180.v:5703.85-5703.106" - cell $eq $eq$ls180.v:5703$1043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5703$1043_Y - end - attribute \src "ls180.v:5704.57-5704.78" - cell $eq $eq$ls180.v:5704$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5704$1045_Y - end - attribute \src "ls180.v:5705.57-5705.78" - cell $eq $eq$ls180.v:5705$1047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5705$1047_Y - end - attribute \src "ls180.v:5709.27-5709.59" - cell $eq $eq$ls180.v:5709$1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 23 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:7] - connect \B 1'0 - connect \Y $eq$ls180.v:5709$1050_Y - end - attribute \src "ls180.v:5710.27-5710.68" - cell $eq $eq$ls180.v:5710$1051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 27 - parameter \B_SIGNED 0 - parameter \B_WIDTH 27 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:3] - connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5710$1051_Y - end - attribute \src "ls180.v:5711.27-5711.66" - cell $eq $eq$ls180.v:5711$1052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 20 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:10] - connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5711$1052_Y - end - attribute \src "ls180.v:5712.27-5712.61" - cell $eq $eq$ls180.v:5712$1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:23] - connect \B 7'1001000 - connect \Y $eq$ls180.v:5712$1053_Y - end - attribute \src "ls180.v:5713.27-5713.65" - cell $eq $eq$ls180.v:5713$1054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:14] - connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5713$1054_Y - end - attribute \src "ls180.v:5769.24-5769.45" - cell $eq $eq$ls180.v:5769$1081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_count - connect \B 1'0 - connect \Y $eq$ls180.v:5769$1081_Y - end - attribute \src "ls180.v:5770.32-5770.77" - cell $eq $eq$ls180.v:5770$1082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:9] - connect \B 1'0 - connect \Y $eq$ls180.v:5770$1082_Y - end - attribute \src "ls180.v:5772.97-5772.141" - cell $eq $eq$ls180.v:5772$1084 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5772$1084_Y - end - attribute \src "ls180.v:5773.100-5773.144" - cell $eq $eq$ls180.v:5773$1088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5773$1088_Y - end - attribute \src "ls180.v:5775.99-5775.143" - cell $eq $eq$ls180.v:5775$1091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5775$1091_Y - end - attribute \src "ls180.v:5776.102-5776.146" - cell $eq $eq$ls180.v:5776$1095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5776$1095_Y - end - attribute \src "ls180.v:5778.99-5778.143" - cell $eq $eq$ls180.v:5778$1098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5778$1098_Y - end - attribute \src "ls180.v:5779.102-5779.146" - cell $eq $eq$ls180.v:5779$1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5779$1102_Y - end - attribute \src "ls180.v:5781.99-5781.143" - cell $eq $eq$ls180.v:5781$1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5781$1105_Y - end - attribute \src "ls180.v:5782.102-5782.146" - cell $eq $eq$ls180.v:5782$1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5782$1109_Y - end - attribute \src "ls180.v:5784.99-5784.143" - cell $eq $eq$ls180.v:5784$1112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5784$1112_Y - end - attribute \src "ls180.v:5785.102-5785.146" - cell $eq $eq$ls180.v:5785$1116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5785$1116_Y - end - attribute \src "ls180.v:5787.102-5787.146" - cell $eq $eq$ls180.v:5787$1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5787$1119_Y - end - attribute \src "ls180.v:5788.105-5788.149" - cell $eq $eq$ls180.v:5788$1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5788$1123_Y - end - attribute \src "ls180.v:5790.102-5790.146" - cell $eq $eq$ls180.v:5790$1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5790$1126_Y - end - attribute \src "ls180.v:5791.105-5791.149" - cell $eq $eq$ls180.v:5791$1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5791$1130_Y - end - attribute \src "ls180.v:5793.102-5793.146" - cell $eq $eq$ls180.v:5793$1133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5793$1133_Y - end - attribute \src "ls180.v:5794.105-5794.149" - cell $eq $eq$ls180.v:5794$1137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5794$1137_Y - end - attribute \src "ls180.v:5796.102-5796.146" - cell $eq $eq$ls180.v:5796$1140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5796$1140_Y - end - attribute \src "ls180.v:5797.105-5797.149" - cell $eq $eq$ls180.v:5797$1144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5797$1144_Y - end - attribute \src "ls180.v:5808.32-5808.77" - cell $eq $eq$ls180.v:5808$1146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:9] - connect \B 3'110 - connect \Y $eq$ls180.v:5808$1146_Y - end - attribute \src "ls180.v:5810.94-5810.138" - cell $eq $eq$ls180.v:5810$1148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5810$1148_Y - end - attribute \src "ls180.v:5811.97-5811.141" - cell $eq $eq$ls180.v:5811$1152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5811$1152_Y - end - attribute \src "ls180.v:5813.94-5813.138" - cell $eq $eq$ls180.v:5813$1155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5813$1155_Y - end - attribute \src "ls180.v:5814.97-5814.141" - cell $eq $eq$ls180.v:5814$1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5814$1159_Y - end - attribute \src "ls180.v:5816.94-5816.138" - cell $eq $eq$ls180.v:5816$1162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5816$1162_Y - end - attribute \src "ls180.v:5817.97-5817.141" - cell $eq $eq$ls180.v:5817$1166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5817$1166_Y - end - attribute \src "ls180.v:5819.94-5819.138" - cell $eq $eq$ls180.v:5819$1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5819$1169_Y - end - attribute \src "ls180.v:5820.97-5820.141" - cell $eq $eq$ls180.v:5820$1173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5820$1173_Y - end - attribute \src "ls180.v:5822.95-5822.139" - cell $eq $eq$ls180.v:5822$1176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5822$1176_Y - end - attribute \src "ls180.v:5823.98-5823.142" - cell $eq $eq$ls180.v:5823$1180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5823$1180_Y - end - attribute \src "ls180.v:5825.95-5825.139" - cell $eq $eq$ls180.v:5825$1183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5825$1183_Y - end - attribute \src "ls180.v:5826.98-5826.142" - cell $eq $eq$ls180.v:5826$1187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5826$1187_Y - end - attribute \src "ls180.v:5834.32-5834.78" - cell $eq $eq$ls180.v:5834$1189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:9] - connect \B 4'1011 - connect \Y $eq$ls180.v:5834$1189_Y - end - attribute \src "ls180.v:5836.93-5836.135" - cell $eq $eq$ls180.v:5836$1191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5836$1191_Y - end - attribute \src "ls180.v:5837.96-5837.138" - cell $eq $eq$ls180.v:5837$1195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5837$1195_Y - end - attribute \src "ls180.v:5839.92-5839.134" - cell $eq $eq$ls180.v:5839$1198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:5839$1198_Y - end - attribute \src "ls180.v:5840.95-5840.137" - cell $eq $eq$ls180.v:5840$1202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'1 - connect \Y $eq$ls180.v:5840$1202_Y - end - attribute \src "ls180.v:5848.32-5848.77" - cell $eq $eq$ls180.v:5848$1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:9] - connect \B 4'1001 - connect \Y $eq$ls180.v:5848$1204_Y - end - attribute \src "ls180.v:5850.98-5850.142" - cell $eq $eq$ls180.v:5850$1206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5850$1206_Y - end - attribute \src "ls180.v:5851.101-5851.145" - cell $eq $eq$ls180.v:5851$1210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5851$1210_Y - end - attribute \src "ls180.v:5853.97-5853.141" - cell $eq $eq$ls180.v:5853$1213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5853$1213_Y - end - attribute \src "ls180.v:5854.100-5854.144" - cell $eq $eq$ls180.v:5854$1217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5854$1217_Y - end - attribute \src "ls180.v:5856.97-5856.141" - cell $eq $eq$ls180.v:5856$1220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5856$1220_Y - end - attribute \src "ls180.v:5857.100-5857.144" - cell $eq $eq$ls180.v:5857$1224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5857$1224_Y - end - attribute \src "ls180.v:5859.97-5859.141" - cell $eq $eq$ls180.v:5859$1227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5859$1227_Y - end - attribute \src "ls180.v:5860.100-5860.144" - cell $eq $eq$ls180.v:5860$1231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5860$1231_Y - end - attribute \src "ls180.v:5862.97-5862.141" - cell $eq $eq$ls180.v:5862$1234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5862$1234_Y - end - attribute \src "ls180.v:5863.100-5863.144" - cell $eq $eq$ls180.v:5863$1238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5863$1238_Y - end - attribute \src "ls180.v:5865.98-5865.142" - cell $eq $eq$ls180.v:5865$1241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5865$1241_Y - end - attribute \src "ls180.v:5866.101-5866.145" - cell $eq $eq$ls180.v:5866$1245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5866$1245_Y - end - attribute \src "ls180.v:5868.98-5868.142" - cell $eq $eq$ls180.v:5868$1248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5868$1248_Y - end - attribute \src "ls180.v:5869.101-5869.145" - cell $eq $eq$ls180.v:5869$1252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5869$1252_Y - end - attribute \src "ls180.v:5871.98-5871.142" - cell $eq $eq$ls180.v:5871$1255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5871$1255_Y - end - attribute \src "ls180.v:5872.101-5872.145" - cell $eq $eq$ls180.v:5872$1259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5872$1259_Y - end - attribute \src "ls180.v:5874.98-5874.142" - cell $eq $eq$ls180.v:5874$1262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5874$1262_Y - end - attribute \src "ls180.v:5875.101-5875.145" - cell $eq $eq$ls180.v:5875$1266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5875$1266_Y - end - attribute \src "ls180.v:5885.32-5885.78" - cell $eq $eq$ls180.v:5885$1268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:9] - connect \B 4'1010 - connect \Y $eq$ls180.v:5885$1268_Y - end - attribute \src "ls180.v:5887.98-5887.142" - cell $eq $eq$ls180.v:5887$1270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5887$1270_Y - end - attribute \src "ls180.v:5888.101-5888.145" - cell $eq $eq$ls180.v:5888$1274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5888$1274_Y - end - attribute \src "ls180.v:5890.97-5890.141" - cell $eq $eq$ls180.v:5890$1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5890$1277_Y - end - attribute \src "ls180.v:5891.100-5891.144" - cell $eq $eq$ls180.v:5891$1281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5891$1281_Y - end - attribute \src "ls180.v:5893.97-5893.141" - cell $eq $eq$ls180.v:5893$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5893$1284_Y - end - attribute \src "ls180.v:5894.100-5894.144" - cell $eq $eq$ls180.v:5894$1288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5894$1288_Y - end - attribute \src "ls180.v:5896.97-5896.141" - cell $eq $eq$ls180.v:5896$1291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5896$1291_Y - end - attribute \src "ls180.v:5897.100-5897.144" - cell $eq $eq$ls180.v:5897$1295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5897$1295_Y - end - attribute \src "ls180.v:5899.97-5899.141" - cell $eq $eq$ls180.v:5899$1298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5899$1298_Y - end - attribute \src "ls180.v:5900.100-5900.144" - cell $eq $eq$ls180.v:5900$1302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5900$1302_Y - end - attribute \src "ls180.v:5902.98-5902.142" - cell $eq $eq$ls180.v:5902$1305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5902$1305_Y - end - attribute \src "ls180.v:5903.101-5903.145" - cell $eq $eq$ls180.v:5903$1309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5903$1309_Y - end - attribute \src "ls180.v:5905.98-5905.142" - cell $eq $eq$ls180.v:5905$1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5905$1312_Y - end - attribute \src "ls180.v:5906.101-5906.145" - cell $eq $eq$ls180.v:5906$1316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5906$1316_Y - end - attribute \src "ls180.v:5908.98-5908.142" - cell $eq $eq$ls180.v:5908$1319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5908$1319_Y - end - attribute \src "ls180.v:5909.101-5909.145" - cell $eq $eq$ls180.v:5909$1323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5909$1323_Y - end - attribute \src "ls180.v:5911.98-5911.142" - cell $eq $eq$ls180.v:5911$1326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5911$1326_Y - end - attribute \src "ls180.v:5912.101-5912.145" - cell $eq $eq$ls180.v:5912$1330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5912$1330_Y - end - attribute \src "ls180.v:5922.32-5922.78" - cell $eq $eq$ls180.v:5922$1332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:9] - connect \B 4'1110 - connect \Y $eq$ls180.v:5922$1332_Y - end - attribute \src "ls180.v:5924.100-5924.144" - cell $eq $eq$ls180.v:5924$1334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5924$1334_Y - end - attribute \src "ls180.v:5925.103-5925.147" - cell $eq $eq$ls180.v:5925$1338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5925$1338_Y - end - attribute \src "ls180.v:5927.100-5927.144" - cell $eq $eq$ls180.v:5927$1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5927$1341_Y - end - attribute \src "ls180.v:5928.103-5928.147" - cell $eq $eq$ls180.v:5928$1345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5928$1345_Y - end - attribute \src "ls180.v:5930.100-5930.144" - cell $eq $eq$ls180.v:5930$1348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5930$1348_Y - end - attribute \src "ls180.v:5931.103-5931.147" - cell $eq $eq$ls180.v:5931$1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5931$1352_Y - end - attribute \src "ls180.v:5933.100-5933.144" - cell $eq $eq$ls180.v:5933$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5933$1355_Y - end - attribute \src "ls180.v:5934.103-5934.147" - cell $eq $eq$ls180.v:5934$1359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5934$1359_Y - end - attribute \src "ls180.v:5936.100-5936.144" - cell $eq $eq$ls180.v:5936$1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5936$1362_Y - end - attribute \src "ls180.v:5937.103-5937.147" - cell $eq $eq$ls180.v:5937$1366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5937$1366_Y - end - attribute \src "ls180.v:5939.100-5939.144" - cell $eq $eq$ls180.v:5939$1369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5939$1369_Y - end - attribute \src "ls180.v:5940.103-5940.147" - cell $eq $eq$ls180.v:5940$1373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5940$1373_Y - end - attribute \src "ls180.v:5942.100-5942.144" - cell $eq $eq$ls180.v:5942$1376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5942$1376_Y - end - attribute \src "ls180.v:5943.103-5943.147" - cell $eq $eq$ls180.v:5943$1380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5943$1380_Y - end - attribute \src "ls180.v:5945.100-5945.144" - cell $eq $eq$ls180.v:5945$1383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5945$1383_Y - end - attribute \src "ls180.v:5946.103-5946.147" - cell $eq $eq$ls180.v:5946$1387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5946$1387_Y - end - attribute \src "ls180.v:5948.102-5948.146" - cell $eq $eq$ls180.v:5948$1390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5948$1390_Y - end - attribute \src "ls180.v:5949.105-5949.149" - cell $eq $eq$ls180.v:5949$1394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5949$1394_Y - end - attribute \src "ls180.v:5951.102-5951.146" - cell $eq $eq$ls180.v:5951$1397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5951$1397_Y - end - attribute \src "ls180.v:5952.105-5952.149" - cell $eq $eq$ls180.v:5952$1401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:5952$1401_Y - end - attribute \src "ls180.v:5954.102-5954.147" - cell $eq $eq$ls180.v:5954$1404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5954$1404_Y - end - attribute \src "ls180.v:5955.105-5955.150" - cell $eq $eq$ls180.v:5955$1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:5955$1408_Y - end - attribute \src "ls180.v:5957.102-5957.147" - cell $eq $eq$ls180.v:5957$1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5957$1411_Y - end - attribute \src "ls180.v:5958.105-5958.150" - cell $eq $eq$ls180.v:5958$1415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:5958$1415_Y - end - attribute \src "ls180.v:5960.102-5960.147" - cell $eq $eq$ls180.v:5960$1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5960$1418_Y - end - attribute \src "ls180.v:5961.105-5961.150" - cell $eq $eq$ls180.v:5961$1422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:5961$1422_Y - end - attribute \src "ls180.v:5963.99-5963.144" - cell $eq $eq$ls180.v:5963$1425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5963$1425_Y - end - attribute \src "ls180.v:5964.102-5964.147" - cell $eq $eq$ls180.v:5964$1429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:5964$1429_Y - end - attribute \src "ls180.v:5966.100-5966.145" - cell $eq $eq$ls180.v:5966$1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5966$1432_Y - end - attribute \src "ls180.v:5967.103-5967.148" - cell $eq $eq$ls180.v:5967$1436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:5967$1436_Y - end - attribute \src "ls180.v:5984.32-5984.78" - cell $eq $eq$ls180.v:5984$1438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:9] - connect \B 4'1101 - connect \Y $eq$ls180.v:5984$1438_Y - end - attribute \src "ls180.v:5986.104-5986.148" - cell $eq $eq$ls180.v:5986$1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5986$1440_Y - end - attribute \src "ls180.v:5987.107-5987.151" - cell $eq $eq$ls180.v:5987$1444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5987$1444_Y - end - attribute \src "ls180.v:5989.104-5989.148" - cell $eq $eq$ls180.v:5989$1447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5989$1447_Y - end - attribute \src "ls180.v:5990.107-5990.151" - cell $eq $eq$ls180.v:5990$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5990$1451_Y - end - attribute \src "ls180.v:5992.104-5992.148" - cell $eq $eq$ls180.v:5992$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5992$1454_Y - end - attribute \src "ls180.v:5993.107-5993.151" - cell $eq $eq$ls180.v:5993$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5993$1458_Y - end - attribute \src "ls180.v:5995.104-5995.148" - cell $eq $eq$ls180.v:5995$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5995$1461_Y - end - attribute \src "ls180.v:5996.107-5996.151" - cell $eq $eq$ls180.v:5996$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5996$1465_Y - end - attribute \src "ls180.v:5998.103-5998.147" - cell $eq $eq$ls180.v:5998$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5998$1468_Y - end - attribute \src "ls180.v:5999.106-5999.150" - cell $eq $eq$ls180.v:5999$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5999$1472_Y - end - attribute \src "ls180.v:6001.103-6001.147" - cell $eq $eq$ls180.v:6001$1475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6001$1475_Y - end - attribute \src "ls180.v:6002.106-6002.150" - cell $eq $eq$ls180.v:6002$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6002$1479_Y - end - attribute \src "ls180.v:6004.103-6004.147" - cell $eq $eq$ls180.v:6004$1482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6004$1482_Y - end - attribute \src "ls180.v:6005.106-6005.150" - cell $eq $eq$ls180.v:6005$1486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6005$1486_Y - end - attribute \src "ls180.v:6007.103-6007.147" - cell $eq $eq$ls180.v:6007$1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6007$1489_Y - end - attribute \src "ls180.v:6008.106-6008.150" - cell $eq $eq$ls180.v:6008$1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6008$1493_Y - end - attribute \src "ls180.v:6010.94-6010.138" - cell $eq $eq$ls180.v:6010$1496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6010$1496_Y - end - attribute \src "ls180.v:6011.97-6011.141" - cell $eq $eq$ls180.v:6011$1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6011$1500_Y - end - attribute \src "ls180.v:6013.105-6013.149" - cell $eq $eq$ls180.v:6013$1503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6013$1503_Y - end - attribute \src "ls180.v:6014.108-6014.152" - cell $eq $eq$ls180.v:6014$1507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6014$1507_Y - end - attribute \src "ls180.v:6016.105-6016.150" - cell $eq $eq$ls180.v:6016$1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6016$1510_Y - end - attribute \src "ls180.v:6017.108-6017.153" - cell $eq $eq$ls180.v:6017$1514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6017$1514_Y - end - attribute \src "ls180.v:6019.105-6019.150" - cell $eq $eq$ls180.v:6019$1517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6019$1517_Y - end - attribute \src "ls180.v:6020.108-6020.153" - cell $eq $eq$ls180.v:6020$1521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6020$1521_Y - end - attribute \src "ls180.v:6022.105-6022.150" - cell $eq $eq$ls180.v:6022$1524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6022$1524_Y - end - attribute \src "ls180.v:6023.108-6023.153" - cell $eq $eq$ls180.v:6023$1528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6023$1528_Y - end - attribute \src "ls180.v:6025.105-6025.150" - cell $eq $eq$ls180.v:6025$1531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6025$1531_Y - end - attribute \src "ls180.v:6026.108-6026.153" - cell $eq $eq$ls180.v:6026$1535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6026$1535_Y - end - attribute \src "ls180.v:6028.105-6028.150" - cell $eq $eq$ls180.v:6028$1538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6028$1538_Y - end - attribute \src "ls180.v:6029.108-6029.153" - cell $eq $eq$ls180.v:6029$1542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6029$1542_Y - end - attribute \src "ls180.v:6031.104-6031.149" - cell $eq $eq$ls180.v:6031$1545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6031$1545_Y - end - attribute \src "ls180.v:6032.107-6032.152" - cell $eq $eq$ls180.v:6032$1549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6032$1549_Y - end - attribute \src "ls180.v:6034.104-6034.149" - cell $eq $eq$ls180.v:6034$1552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6034$1552_Y - end - attribute \src "ls180.v:6035.107-6035.152" - cell $eq $eq$ls180.v:6035$1556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6035$1556_Y - end - attribute \src "ls180.v:6037.104-6037.149" - cell $eq $eq$ls180.v:6037$1559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6037$1559_Y - end - attribute \src "ls180.v:6038.107-6038.152" - cell $eq $eq$ls180.v:6038$1563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6038$1563_Y - end - attribute \src "ls180.v:6040.104-6040.149" - cell $eq $eq$ls180.v:6040$1566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6040$1566_Y - end - attribute \src "ls180.v:6041.107-6041.152" - cell $eq $eq$ls180.v:6041$1570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6041$1570_Y - end - attribute \src "ls180.v:6043.104-6043.149" - cell $eq $eq$ls180.v:6043$1573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6043$1573_Y - end - attribute \src "ls180.v:6044.107-6044.152" - cell $eq $eq$ls180.v:6044$1577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6044$1577_Y - end - attribute \src "ls180.v:6046.104-6046.149" - cell $eq $eq$ls180.v:6046$1580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6046$1580_Y - end - attribute \src "ls180.v:6047.107-6047.152" - cell $eq $eq$ls180.v:6047$1584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6047$1584_Y - end - attribute \src "ls180.v:6049.104-6049.149" - cell $eq $eq$ls180.v:6049$1587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6049$1587_Y - end - attribute \src "ls180.v:6050.107-6050.152" - cell $eq $eq$ls180.v:6050$1591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6050$1591_Y - end - attribute \src "ls180.v:6052.104-6052.149" - cell $eq $eq$ls180.v:6052$1594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6052$1594_Y - end - attribute \src "ls180.v:6053.107-6053.152" - cell $eq $eq$ls180.v:6053$1598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6053$1598_Y - end - attribute \src "ls180.v:6055.104-6055.149" - cell $eq $eq$ls180.v:6055$1601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6055$1601_Y - end - attribute \src "ls180.v:6056.107-6056.152" - cell $eq $eq$ls180.v:6056$1605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6056$1605_Y - end - attribute \src "ls180.v:6058.104-6058.149" - cell $eq $eq$ls180.v:6058$1608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6058$1608_Y - end - attribute \src "ls180.v:6059.107-6059.152" - cell $eq $eq$ls180.v:6059$1612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6059$1612_Y - end - attribute \src "ls180.v:6061.100-6061.145" - cell $eq $eq$ls180.v:6061$1615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6061$1615_Y - end - attribute \src "ls180.v:6062.103-6062.148" - cell $eq $eq$ls180.v:6062$1619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6062$1619_Y - end - attribute \src "ls180.v:6064.101-6064.146" - cell $eq $eq$ls180.v:6064$1622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6064$1622_Y - end - attribute \src "ls180.v:6065.104-6065.149" - cell $eq $eq$ls180.v:6065$1626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6065$1626_Y - end - attribute \src "ls180.v:6067.104-6067.149" - cell $eq $eq$ls180.v:6067$1629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6067$1629_Y - end - attribute \src "ls180.v:6068.107-6068.152" - cell $eq $eq$ls180.v:6068$1633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6068$1633_Y - end - attribute \src "ls180.v:6070.104-6070.149" - cell $eq $eq$ls180.v:6070$1636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6070$1636_Y - end - attribute \src "ls180.v:6071.107-6071.152" - cell $eq $eq$ls180.v:6071$1640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6071$1640_Y - end - attribute \src "ls180.v:6073.103-6073.148" - cell $eq $eq$ls180.v:6073$1643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6073$1643_Y - end - attribute \src "ls180.v:6074.106-6074.151" - cell $eq $eq$ls180.v:6074$1647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6074$1647_Y - end - attribute \src "ls180.v:6076.103-6076.148" - cell $eq $eq$ls180.v:6076$1650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6076$1650_Y - end - attribute \src "ls180.v:6077.106-6077.151" - cell $eq $eq$ls180.v:6077$1654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6077$1654_Y - end - attribute \src "ls180.v:6079.103-6079.148" - cell $eq $eq$ls180.v:6079$1657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6079$1657_Y - end - attribute \src "ls180.v:6080.106-6080.151" - cell $eq $eq$ls180.v:6080$1661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6080$1661_Y - end - attribute \src "ls180.v:6082.103-6082.148" - cell $eq $eq$ls180.v:6082$1664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6082$1664_Y - end - attribute \src "ls180.v:6083.106-6083.151" - cell $eq $eq$ls180.v:6083$1668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6083$1668_Y - end - attribute \src "ls180.v:6119.32-6119.78" - cell $eq $eq$ls180.v:6119$1670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:9] - connect \B 4'1111 - connect \Y $eq$ls180.v:6119$1670_Y - end - attribute \src "ls180.v:6121.100-6121.144" - cell $eq $eq$ls180.v:6121$1672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6121$1672_Y - end - attribute \src "ls180.v:6122.103-6122.147" - cell $eq $eq$ls180.v:6122$1676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6122$1676_Y - end - attribute \src "ls180.v:6124.100-6124.144" - cell $eq $eq$ls180.v:6124$1679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6124$1679_Y - end - attribute \src "ls180.v:6125.103-6125.147" - cell $eq $eq$ls180.v:6125$1683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6125$1683_Y - end - attribute \src "ls180.v:6127.100-6127.144" - cell $eq $eq$ls180.v:6127$1686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6127$1686_Y - end - attribute \src "ls180.v:6128.103-6128.147" - cell $eq $eq$ls180.v:6128$1690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6128$1690_Y - end - attribute \src "ls180.v:6130.100-6130.144" - cell $eq $eq$ls180.v:6130$1693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6130$1693_Y - end - attribute \src "ls180.v:6131.103-6131.147" - cell $eq $eq$ls180.v:6131$1697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6131$1697_Y - end - attribute \src "ls180.v:6133.100-6133.144" - cell $eq $eq$ls180.v:6133$1700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6133$1700_Y - end - attribute \src "ls180.v:6134.103-6134.147" - cell $eq $eq$ls180.v:6134$1704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6134$1704_Y - end - attribute \src "ls180.v:6136.100-6136.144" - cell $eq $eq$ls180.v:6136$1707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6136$1707_Y - end - attribute \src "ls180.v:6137.103-6137.147" - cell $eq $eq$ls180.v:6137$1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6137$1711_Y - end - attribute \src "ls180.v:6139.100-6139.144" - cell $eq $eq$ls180.v:6139$1714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6139$1714_Y - end - attribute \src "ls180.v:6140.103-6140.147" - cell $eq $eq$ls180.v:6140$1718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6140$1718_Y - end - attribute \src "ls180.v:6142.100-6142.144" - cell $eq $eq$ls180.v:6142$1721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6142$1721_Y - end - attribute \src "ls180.v:6143.103-6143.147" - cell $eq $eq$ls180.v:6143$1725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6143$1725_Y - end - attribute \src "ls180.v:6145.102-6145.146" - cell $eq $eq$ls180.v:6145$1728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6145$1728_Y - end - attribute \src "ls180.v:6146.105-6146.149" - cell $eq $eq$ls180.v:6146$1732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6146$1732_Y - end - attribute \src "ls180.v:6148.102-6148.146" - cell $eq $eq$ls180.v:6148$1735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6148$1735_Y - end - attribute \src "ls180.v:6149.105-6149.149" - cell $eq $eq$ls180.v:6149$1739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6149$1739_Y - end - attribute \src "ls180.v:6151.102-6151.147" - cell $eq $eq$ls180.v:6151$1742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6151$1742_Y - end - attribute \src "ls180.v:6152.105-6152.150" - cell $eq $eq$ls180.v:6152$1746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6152$1746_Y - end - attribute \src "ls180.v:6154.102-6154.147" - cell $eq $eq$ls180.v:6154$1749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6154$1749_Y - end - attribute \src "ls180.v:6155.105-6155.150" - cell $eq $eq$ls180.v:6155$1753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6155$1753_Y - end - attribute \src "ls180.v:6157.102-6157.147" - cell $eq $eq$ls180.v:6157$1756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6157$1756_Y - end - attribute \src "ls180.v:6158.105-6158.150" - cell $eq $eq$ls180.v:6158$1760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6158$1760_Y - end - attribute \src "ls180.v:6160.99-6160.144" - cell $eq $eq$ls180.v:6160$1763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6160$1763_Y - end - attribute \src "ls180.v:6161.102-6161.147" - cell $eq $eq$ls180.v:6161$1767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6161$1767_Y - end - attribute \src "ls180.v:6163.100-6163.145" - cell $eq $eq$ls180.v:6163$1770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6163$1770_Y - end - attribute \src "ls180.v:6164.103-6164.148" - cell $eq $eq$ls180.v:6164$1774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6164$1774_Y - end - attribute \src "ls180.v:6166.102-6166.147" - cell $eq $eq$ls180.v:6166$1777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6166$1777_Y - end - attribute \src "ls180.v:6167.105-6167.150" - cell $eq $eq$ls180.v:6167$1781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6167$1781_Y - end - attribute \src "ls180.v:6169.102-6169.147" - cell $eq $eq$ls180.v:6169$1784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6169$1784_Y - end - attribute \src "ls180.v:6170.105-6170.150" - cell $eq $eq$ls180.v:6170$1788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6170$1788_Y - end - attribute \src "ls180.v:6172.102-6172.147" - cell $eq $eq$ls180.v:6172$1791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6172$1791_Y - end - attribute \src "ls180.v:6173.105-6173.150" - cell $eq $eq$ls180.v:6173$1795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6173$1795_Y - end - attribute \src "ls180.v:6175.102-6175.147" - cell $eq $eq$ls180.v:6175$1798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6175$1798_Y - end - attribute \src "ls180.v:6176.105-6176.150" - cell $eq $eq$ls180.v:6176$1802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6176$1802_Y - end - attribute \src "ls180.v:6198.32-6198.78" - cell $eq $eq$ls180.v:6198$1804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:9] - connect \B 4'1100 - connect \Y $eq$ls180.v:6198$1804_Y - end - attribute \src "ls180.v:6200.102-6200.146" - cell $eq $eq$ls180.v:6200$1806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6200$1806_Y - end - attribute \src "ls180.v:6201.105-6201.149" - cell $eq $eq$ls180.v:6201$1810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6201$1810_Y - end - attribute \src "ls180.v:6203.107-6203.151" - cell $eq $eq$ls180.v:6203$1813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6203$1813_Y - end - attribute \src "ls180.v:6204.110-6204.154" - cell $eq $eq$ls180.v:6204$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6204$1817_Y - end - attribute \src "ls180.v:6206.107-6206.151" - cell $eq $eq$ls180.v:6206$1820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6206$1820_Y - end - attribute \src "ls180.v:6207.110-6207.154" - cell $eq $eq$ls180.v:6207$1824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6207$1824_Y - end - attribute \src "ls180.v:6209.100-6209.144" - cell $eq $eq$ls180.v:6209$1827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6209$1827_Y - end - attribute \src "ls180.v:6210.103-6210.147" - cell $eq $eq$ls180.v:6210$1831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6210$1831_Y - end - attribute \src "ls180.v:6215.32-6215.77" - cell $eq $eq$ls180.v:6215$1833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:9] - connect \B 2'11 - connect \Y $eq$ls180.v:6215$1833_Y - end - attribute \src "ls180.v:6217.104-6217.148" - cell $eq $eq$ls180.v:6217$1835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6217$1835_Y - end - attribute \src "ls180.v:6218.107-6218.151" - cell $eq $eq$ls180.v:6218$1839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6218$1839_Y - end - attribute \src "ls180.v:6220.108-6220.152" - cell $eq $eq$ls180.v:6220$1842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6220$1842_Y - end - attribute \src "ls180.v:6221.111-6221.155" - cell $eq $eq$ls180.v:6221$1846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6221$1846_Y - end - attribute \src "ls180.v:6223.98-6223.142" - cell $eq $eq$ls180.v:6223$1849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6223$1849_Y - end - attribute \src "ls180.v:6224.101-6224.145" - cell $eq $eq$ls180.v:6224$1853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6224$1853_Y - end - attribute \src "ls180.v:6226.108-6226.152" - cell $eq $eq$ls180.v:6226$1856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6226$1856_Y - end - attribute \src "ls180.v:6227.111-6227.155" - cell $eq $eq$ls180.v:6227$1860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6227$1860_Y - end - attribute \src "ls180.v:6229.108-6229.152" - cell $eq $eq$ls180.v:6229$1863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6229$1863_Y - end - attribute \src "ls180.v:6230.111-6230.155" - cell $eq $eq$ls180.v:6230$1867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6230$1867_Y - end - attribute \src "ls180.v:6232.109-6232.153" - cell $eq $eq$ls180.v:6232$1870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6232$1870_Y - end - attribute \src "ls180.v:6233.112-6233.156" - cell $eq $eq$ls180.v:6233$1874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6233$1874_Y - end - attribute \src "ls180.v:6235.107-6235.151" - cell $eq $eq$ls180.v:6235$1877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6235$1877_Y - end - attribute \src "ls180.v:6236.110-6236.154" - cell $eq $eq$ls180.v:6236$1881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6236$1881_Y - end - attribute \src "ls180.v:6238.107-6238.151" - cell $eq $eq$ls180.v:6238$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6238$1884_Y - end - attribute \src "ls180.v:6239.110-6239.154" - cell $eq $eq$ls180.v:6239$1888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6239$1888_Y - end - attribute \src "ls180.v:6241.107-6241.151" - cell $eq $eq$ls180.v:6241$1891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6241$1891_Y - end - attribute \src "ls180.v:6242.110-6242.154" - cell $eq $eq$ls180.v:6242$1895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6242$1895_Y - end - attribute \src "ls180.v:6244.107-6244.151" - cell $eq $eq$ls180.v:6244$1898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6244$1898_Y - end - attribute \src "ls180.v:6245.110-6245.154" - cell $eq $eq$ls180.v:6245$1902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6245$1902_Y - end - attribute \src "ls180.v:6260.33-6260.79" - cell $eq $eq$ls180.v:6260$1904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:9] - connect \B 3'111 - connect \Y $eq$ls180.v:6260$1904_Y - end - attribute \src "ls180.v:6262.102-6262.147" - cell $eq $eq$ls180.v:6262$1906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6262$1906_Y - end - attribute \src "ls180.v:6263.105-6263.150" - cell $eq $eq$ls180.v:6263$1910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6263$1910_Y - end - attribute \src "ls180.v:6265.102-6265.147" - cell $eq $eq$ls180.v:6265$1913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6265$1913_Y - end - attribute \src "ls180.v:6266.105-6266.150" - cell $eq $eq$ls180.v:6266$1917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6266$1917_Y - end - attribute \src "ls180.v:6268.100-6268.145" - cell $eq $eq$ls180.v:6268$1920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6268$1920_Y - end - attribute \src "ls180.v:6269.103-6269.148" - cell $eq $eq$ls180.v:6269$1924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6269$1924_Y - end - attribute \src "ls180.v:6271.99-6271.144" - cell $eq $eq$ls180.v:6271$1927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6271$1927_Y - end - attribute \src "ls180.v:6272.102-6272.147" - cell $eq $eq$ls180.v:6272$1931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6272$1931_Y - end - attribute \src "ls180.v:6274.98-6274.143" - cell $eq $eq$ls180.v:6274$1934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6274$1934_Y - end - attribute \src "ls180.v:6275.101-6275.146" - cell $eq $eq$ls180.v:6275$1938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6275$1938_Y - end - attribute \src "ls180.v:6277.97-6277.142" - cell $eq $eq$ls180.v:6277$1941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6277$1941_Y - end - attribute \src "ls180.v:6278.100-6278.145" - cell $eq $eq$ls180.v:6278$1945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6278$1945_Y - end - attribute \src "ls180.v:6280.103-6280.148" - cell $eq $eq$ls180.v:6280$1948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6280$1948_Y - end - attribute \src "ls180.v:6281.106-6281.151" - cell $eq $eq$ls180.v:6281$1952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6281$1952_Y - end - attribute \src "ls180.v:6300.33-6300.79" - cell $eq $eq$ls180.v:6300$1955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:9] - connect \B 4'1000 - connect \Y $eq$ls180.v:6300$1955_Y - end - attribute \src "ls180.v:6302.102-6302.147" - cell $eq $eq$ls180.v:6302$1957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6302$1957_Y - end - attribute \src "ls180.v:6303.105-6303.150" - cell $eq $eq$ls180.v:6303$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6303$1961_Y - end - attribute \src "ls180.v:6305.102-6305.147" - cell $eq $eq$ls180.v:6305$1964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6305$1964_Y - end - attribute \src "ls180.v:6306.105-6306.150" - cell $eq $eq$ls180.v:6306$1968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6306$1968_Y - end - attribute \src "ls180.v:6308.100-6308.145" - cell $eq $eq$ls180.v:6308$1971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6308$1971_Y - end - attribute \src "ls180.v:6309.103-6309.148" - cell $eq $eq$ls180.v:6309$1975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6309$1975_Y - end - attribute \src "ls180.v:6311.99-6311.144" - cell $eq $eq$ls180.v:6311$1978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6311$1978_Y - end - attribute \src "ls180.v:6312.102-6312.147" - cell $eq $eq$ls180.v:6312$1982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6312$1982_Y - end - attribute \src "ls180.v:6314.98-6314.143" - cell $eq $eq$ls180.v:6314$1985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6314$1985_Y - end - attribute \src "ls180.v:6315.101-6315.146" - cell $eq $eq$ls180.v:6315$1989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6315$1989_Y - end - attribute \src "ls180.v:6317.97-6317.142" - cell $eq $eq$ls180.v:6317$1992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6317$1992_Y - end - attribute \src "ls180.v:6318.100-6318.145" - cell $eq $eq$ls180.v:6318$1996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6318$1996_Y - end - attribute \src "ls180.v:6320.103-6320.148" - cell $eq $eq$ls180.v:6320$1999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6320$1999_Y - end - attribute \src "ls180.v:6321.106-6321.151" - cell $eq $eq$ls180.v:6321$2003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6321$2003_Y - end - attribute \src "ls180.v:6323.106-6323.151" - cell $eq $eq$ls180.v:6323$2006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6323$2006_Y - end - attribute \src "ls180.v:6324.109-6324.154" - cell $eq $eq$ls180.v:6324$2010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6324$2010_Y - end - attribute \src "ls180.v:6326.106-6326.151" - cell $eq $eq$ls180.v:6326$2013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6326$2013_Y - end - attribute \src "ls180.v:6327.109-6327.154" - cell $eq $eq$ls180.v:6327$2017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6327$2017_Y - end - attribute \src "ls180.v:6348.33-6348.79" - cell $eq $eq$ls180.v:6348$2020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:9] - connect \B 2'10 - connect \Y $eq$ls180.v:6348$2020_Y - end - attribute \src "ls180.v:6350.99-6350.144" - cell $eq $eq$ls180.v:6350$2022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6350$2022_Y - end - attribute \src "ls180.v:6351.102-6351.147" - cell $eq $eq$ls180.v:6351$2026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6351$2026_Y - end - attribute \src "ls180.v:6353.99-6353.144" - cell $eq $eq$ls180.v:6353$2029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6353$2029_Y - end - attribute \src "ls180.v:6354.102-6354.147" - cell $eq $eq$ls180.v:6354$2033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6354$2033_Y - end - attribute \src "ls180.v:6356.99-6356.144" - cell $eq $eq$ls180.v:6356$2036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6356$2036_Y - end - attribute \src "ls180.v:6357.102-6357.147" - cell $eq $eq$ls180.v:6357$2040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6357$2040_Y - end - attribute \src "ls180.v:6359.99-6359.144" - cell $eq $eq$ls180.v:6359$2043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6359$2043_Y - end - attribute \src "ls180.v:6360.102-6360.147" - cell $eq $eq$ls180.v:6360$2047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6360$2047_Y - end - attribute \src "ls180.v:6362.101-6362.146" - cell $eq $eq$ls180.v:6362$2050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6362$2050_Y - end - attribute \src "ls180.v:6363.104-6363.149" - cell $eq $eq$ls180.v:6363$2054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6363$2054_Y - end - attribute \src "ls180.v:6365.101-6365.146" - cell $eq $eq$ls180.v:6365$2057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6365$2057_Y - end - attribute \src "ls180.v:6366.104-6366.149" - cell $eq $eq$ls180.v:6366$2061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6366$2061_Y - end - attribute \src "ls180.v:6368.101-6368.146" - cell $eq $eq$ls180.v:6368$2064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6368$2064_Y - end - attribute \src "ls180.v:6369.104-6369.149" - cell $eq $eq$ls180.v:6369$2068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6369$2068_Y - end - attribute \src "ls180.v:6371.101-6371.146" - cell $eq $eq$ls180.v:6371$2071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6371$2071_Y - end - attribute \src "ls180.v:6372.104-6372.149" - cell $eq $eq$ls180.v:6372$2075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6372$2075_Y - end - attribute \src "ls180.v:6374.97-6374.142" - cell $eq $eq$ls180.v:6374$2078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6374$2078_Y - end - attribute \src "ls180.v:6375.100-6375.145" - cell $eq $eq$ls180.v:6375$2082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6375$2082_Y - end - attribute \src "ls180.v:6377.107-6377.152" - cell $eq $eq$ls180.v:6377$2085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6377$2085_Y - end - attribute \src "ls180.v:6378.110-6378.155" - cell $eq $eq$ls180.v:6378$2089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6378$2089_Y - end - attribute \src "ls180.v:6380.100-6380.146" - cell $eq $eq$ls180.v:6380$2092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6380$2092_Y - end - attribute \src "ls180.v:6381.103-6381.149" - cell $eq $eq$ls180.v:6381$2096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6381$2096_Y - end - attribute \src "ls180.v:6383.100-6383.146" - cell $eq $eq$ls180.v:6383$2099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6383$2099_Y - end - attribute \src "ls180.v:6384.103-6384.149" - cell $eq $eq$ls180.v:6384$2103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6384$2103_Y - end - attribute \src "ls180.v:6386.100-6386.146" - cell $eq $eq$ls180.v:6386$2106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6386$2106_Y - end - attribute \src "ls180.v:6387.103-6387.149" - cell $eq $eq$ls180.v:6387$2110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6387$2110_Y - end - attribute \src "ls180.v:6389.100-6389.146" - cell $eq $eq$ls180.v:6389$2113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6389$2113_Y - end - attribute \src "ls180.v:6390.103-6390.149" - cell $eq $eq$ls180.v:6390$2117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6390$2117_Y - end - attribute \src "ls180.v:6392.112-6392.158" - cell $eq $eq$ls180.v:6392$2120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6392$2120_Y - end - attribute \src "ls180.v:6393.115-6393.161" - cell $eq $eq$ls180.v:6393$2124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6393$2124_Y - end - attribute \src "ls180.v:6395.113-6395.159" - cell $eq $eq$ls180.v:6395$2127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6395$2127_Y - end - attribute \src "ls180.v:6396.116-6396.162" - cell $eq $eq$ls180.v:6396$2131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6396$2131_Y - end - attribute \src "ls180.v:6398.104-6398.150" - cell $eq $eq$ls180.v:6398$2134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6398$2134_Y - end - attribute \src "ls180.v:6399.107-6399.153" - cell $eq $eq$ls180.v:6399$2138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6399$2138_Y - end - attribute \src "ls180.v:6416.33-6416.79" - cell $eq $eq$ls180.v:6416$2140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:9] - connect \B 3'101 - connect \Y $eq$ls180.v:6416$2140_Y - end - attribute \src "ls180.v:6418.90-6418.135" - cell $eq $eq$ls180.v:6418$2142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6418$2142_Y - end - attribute \src "ls180.v:6419.93-6419.138" - cell $eq $eq$ls180.v:6419$2146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6419$2146_Y - end - attribute \src "ls180.v:6421.100-6421.145" - cell $eq $eq$ls180.v:6421$2149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6421$2149_Y - end - attribute \src "ls180.v:6422.103-6422.148" - cell $eq $eq$ls180.v:6422$2153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6422$2153_Y - end - attribute \src "ls180.v:6424.101-6424.146" - cell $eq $eq$ls180.v:6424$2156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6424$2156_Y - end - attribute \src "ls180.v:6425.104-6425.149" - cell $eq $eq$ls180.v:6425$2160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6425$2160_Y - end - attribute \src "ls180.v:6427.105-6427.150" - cell $eq $eq$ls180.v:6427$2163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6427$2163_Y - end - attribute \src "ls180.v:6428.108-6428.153" - cell $eq $eq$ls180.v:6428$2167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6428$2167_Y - end - attribute \src "ls180.v:6430.106-6430.151" - cell $eq $eq$ls180.v:6430$2170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6430$2170_Y - end - attribute \src "ls180.v:6431.109-6431.154" - cell $eq $eq$ls180.v:6431$2174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6431$2174_Y - end - attribute \src "ls180.v:6433.104-6433.149" - cell $eq $eq$ls180.v:6433$2177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6433$2177_Y - end - attribute \src "ls180.v:6434.107-6434.152" - cell $eq $eq$ls180.v:6434$2181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6434$2181_Y - end - attribute \src "ls180.v:6436.101-6436.146" - cell $eq $eq$ls180.v:6436$2184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6436$2184_Y - end - attribute \src "ls180.v:6437.104-6437.149" - cell $eq $eq$ls180.v:6437$2188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6437$2188_Y - end - attribute \src "ls180.v:6439.100-6439.145" - cell $eq $eq$ls180.v:6439$2191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6439$2191_Y - end - attribute \src "ls180.v:6440.103-6440.148" - cell $eq $eq$ls180.v:6440$2195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6440$2195_Y - end - attribute \src "ls180.v:6450.33-6450.79" - cell $eq $eq$ls180.v:6450$2197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:9] - connect \B 3'100 - connect \Y $eq$ls180.v:6450$2197_Y - end - attribute \src "ls180.v:6452.106-6452.151" - cell $eq $eq$ls180.v:6452$2199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6452$2199_Y - end - attribute \src "ls180.v:6453.109-6453.154" - cell $eq $eq$ls180.v:6453$2203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6453$2203_Y - end - attribute \src "ls180.v:6455.106-6455.151" - cell $eq $eq$ls180.v:6455$2206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6455$2206_Y - end - attribute \src "ls180.v:6456.109-6456.154" - cell $eq $eq$ls180.v:6456$2210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6456$2210_Y - end - attribute \src "ls180.v:6458.106-6458.151" - cell $eq $eq$ls180.v:6458$2213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6458$2213_Y - end - attribute \src "ls180.v:6459.109-6459.154" - cell $eq $eq$ls180.v:6459$2217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6459$2217_Y - end - attribute \src "ls180.v:6461.106-6461.151" - cell $eq $eq$ls180.v:6461$2220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6461$2220_Y - end - attribute \src "ls180.v:6462.109-6462.154" - cell $eq $eq$ls180.v:6462$2224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6462$2224_Y - end - attribute \src "ls180.v:6843.41-6843.81" - cell $eq $eq$ls180.v:6843$2261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:6843$2261_Y - end - attribute \src "ls180.v:6843.144-6843.177" - cell $eq $eq$ls180.v:6843$2262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6843$2262_Y - end - attribute \src "ls180.v:6843.219-6843.252" - cell $eq $eq$ls180.v:6843$2265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6843$2265_Y - end - attribute \src "ls180.v:6843.294-6843.327" - cell $eq $eq$ls180.v:6843$2268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6843$2268_Y - end - attribute \src "ls180.v:6867.41-6867.81" - cell $eq $eq$ls180.v:6867$2277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:6867$2277_Y - end - attribute \src "ls180.v:6867.144-6867.177" - cell $eq $eq$ls180.v:6867$2278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6867$2278_Y - end - attribute \src "ls180.v:6867.219-6867.252" - cell $eq $eq$ls180.v:6867$2281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6867$2281_Y - end - attribute \src "ls180.v:6867.294-6867.327" - cell $eq $eq$ls180.v:6867$2284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6867$2284_Y - end - attribute \src "ls180.v:6891.41-6891.81" - cell $eq $eq$ls180.v:6891$2293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:6891$2293_Y - end - attribute \src "ls180.v:6891.144-6891.177" - cell $eq $eq$ls180.v:6891$2294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6891$2294_Y - end - attribute \src "ls180.v:6891.219-6891.252" - cell $eq $eq$ls180.v:6891$2297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6891$2297_Y - end - attribute \src "ls180.v:6891.294-6891.327" - cell $eq $eq$ls180.v:6891$2300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6891$2300_Y - end - attribute \src "ls180.v:6915.41-6915.81" - cell $eq $eq$ls180.v:6915$2309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:6915$2309_Y - end - attribute \src "ls180.v:6915.144-6915.177" - cell $eq $eq$ls180.v:6915$2310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6915$2310_Y - end - attribute \src "ls180.v:6915.219-6915.252" - cell $eq $eq$ls180.v:6915$2313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6915$2313_Y - end - attribute \src "ls180.v:6915.294-6915.327" - cell $eq $eq$ls180.v:6915$2316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6915$2316_Y - end - attribute \src "ls180.v:7508.8-7508.38" - cell $eq $eq$ls180.v:7508$2419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $eq$ls180.v:7508$2419_Y - end - attribute \src "ls180.v:7539.8-7539.42" - cell $eq $eq$ls180.v:7539$2427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'0 - connect \Y $eq$ls180.v:7539$2427_Y - end - attribute \src "ls180.v:7559.38-7559.74" - cell $eq $eq$ls180.v:7559$2430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $eq$ls180.v:7559$2430_Y - end - attribute \src "ls180.v:7566.7-7566.43" - cell $eq $eq$ls180.v:7566$2432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 2'10 - connect \Y $eq$ls180.v:7566$2432_Y - end - attribute \src "ls180.v:7573.7-7573.43" - cell $eq $eq$ls180.v:7573$2433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7573$2433_Y - end - attribute \src "ls180.v:7581.7-7581.43" - cell $eq $eq$ls180.v:7581$2434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7581$2434_Y - end - attribute \src "ls180.v:7633.9-7633.54" - cell $eq $eq$ls180.v:7633$2452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7633$2452_Y - end - attribute \src "ls180.v:7679.9-7679.54" - cell $eq $eq$ls180.v:7679$2468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7679$2468_Y - end - attribute \src "ls180.v:7725.9-7725.54" - cell $eq $eq$ls180.v:7725$2484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7725$2484_Y - end - attribute \src "ls180.v:7771.9-7771.54" - cell $eq $eq$ls180.v:7771$2500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7771$2500_Y - end - attribute \src "ls180.v:7921.9-7921.41" - cell $eq $eq$ls180.v:7921$2512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7921$2512_Y - end - attribute \src "ls180.v:7936.9-7936.41" - cell $eq $eq$ls180.v:7936$2515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7936$2515_Y - end - attribute \src "ls180.v:7942.49-7942.82" - cell $eq $eq$ls180.v:7942$2516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7942$2516_Y - end - attribute \src "ls180.v:7942.131-7942.164" - cell $eq $eq$ls180.v:7942$2519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7942$2519_Y - end - attribute \src "ls180.v:7942.213-7942.246" - cell $eq $eq$ls180.v:7942$2522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7942$2522_Y - end - attribute \src "ls180.v:7942.295-7942.328" - cell $eq $eq$ls180.v:7942$2525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7942$2525_Y - end - attribute \src "ls180.v:7943.50-7943.83" - cell $eq $eq$ls180.v:7943$2528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7943$2528_Y - end - attribute \src "ls180.v:7943.132-7943.165" - cell $eq $eq$ls180.v:7943$2531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7943$2531_Y - end - attribute \src "ls180.v:7943.214-7943.247" - cell $eq $eq$ls180.v:7943$2534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7943$2534_Y - end - attribute \src "ls180.v:7943.296-7943.329" - cell $eq $eq$ls180.v:7943$2537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:7943$2537_Y - end - attribute \src "ls180.v:7978.9-7978.42" - cell $eq $eq$ls180.v:7978$2549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1000 - connect \Y $eq$ls180.v:7978$2549_Y - end - attribute \src "ls180.v:7981.10-7981.43" - cell $eq $eq$ls180.v:7981$2550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:7981$2550_Y - end - attribute \src "ls180.v:8007.9-8007.42" - cell $eq $eq$ls180.v:8007$2556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'0 - connect \Y $eq$ls180.v:8007$2556_Y - end - attribute \src "ls180.v:8012.10-8012.43" - cell $eq $eq$ls180.v:8012$2557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:8012$2557_Y - end - attribute \src "ls180.v:8219.9-8219.53" - cell $eq $eq$ls180.v:8219$2606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8219$2606_Y - end - attribute \src "ls180.v:8300.9-8300.54" - cell $eq $eq$ls180.v:8300$2618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8300$2618_Y - end - attribute \src "ls180.v:8379.9-8379.55" - cell $eq $eq$ls180.v:8379$2630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $eq$ls180.v:8379$2630_Y - end - attribute \src "ls180.v:8602.9-8602.49" - cell $eq $eq$ls180.v:8602$2663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_demux - connect \B 2'11 - connect \Y $eq$ls180.v:8602$2663_Y - end - attribute \src "ls180.v:8178.8-8178.54" - cell $ge $ge$ls180.v:8178$2598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8178$2597_Y - connect \Y $ge$ls180.v:8178$2598_Y - end - attribute \src "ls180.v:8192.8-8192.54" - cell $ge $ge$ls180.v:8192$2602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8192$2601_Y - connect \Y $ge$ls180.v:8192$2602_Y - end - attribute \src "ls180.v:5152.47-5152.83" - cell $gt $gt$ls180.v:5152$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $gt$ls180.v:5152$914_Y - end - attribute \src "ls180.v:5158.7-5158.43" - cell $lt $lt$ls180.v:5158$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1000 - connect \Y $lt$ls180.v:5158$917_Y - end - attribute \src "ls180.v:8173.8-8173.43" - cell $lt $lt$ls180.v:8173$2596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8173$2596_Y - end - attribute \src "ls180.v:8187.8-8187.43" - cell $lt $lt$ls180.v:8187$2600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8187$2600_Y - end - attribute \src "ls180.v:10068.33-10068.36" - cell $memrd $memrd$\mem$ls180.v:10068$2705 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \TRANSPARENT 0 - parameter \WIDTH 32 - connect \ADDR \memadr - connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10068$2705_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10079.12-10079.19" - cell $memrd $memrd$\storage$ls180.v:10079$2710 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10079$2710_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10086.68-10086.75" - cell $memrd $memrd$\storage$ls180.v:10086$2712 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10086$2712_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10093.14-10093.23" - cell $memrd $memrd$\storage_1$ls180.v:10093$2717 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10093$2717_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10100.68-10100.77" - cell $memrd $memrd$\storage_1$ls180.v:10100$2719 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10100$2719_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10107.14-10107.23" - cell $memrd $memrd$\storage_2$ls180.v:10107$2724 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10107$2724_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10114.68-10114.77" - cell $memrd $memrd$\storage_2$ls180.v:10114$2726 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10114$2726_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10121.14-10121.23" - cell $memrd $memrd$\storage_3$ls180.v:10121$2731 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10121$2731_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10128.68-10128.77" - cell $memrd $memrd$\storage_3$ls180.v:10128$2733 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10128$2733_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10136.14-10136.23" - cell $memrd $memrd$\storage_4$ls180.v:10136$2738 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10136$2738_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10141.15-10141.24" - cell $memrd $memrd$\storage_4$ls180.v:10141$2740 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10141$2740_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10153.14-10153.23" - cell $memrd $memrd$\storage_5$ls180.v:10153$2745 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10153$2745_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10158.15-10158.24" - cell $memrd $memrd$\storage_5$ls180.v:10158$2747 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10158$2747_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10169.14-10169.23" - cell $memrd $memrd$\storage_6$ls180.v:10169$2752 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10169$2752_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10176.45-10176.54" - cell $memrd $memrd$\storage_6$ls180.v:10176$2754 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10176$2754_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10183.14-10183.23" - cell $memrd $memrd$\storage_7$ls180.v:10183$2759 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10183$2759_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10190.45-10190.54" - cell $memrd $memrd$\storage_7$ls180.v:10190$2761 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10190$2761_DATA - connect \EN 1'x - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2763 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2763 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10058$1_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10058$1_DATA - connect \EN $memwr$\mem$ls180.v:10058$1_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2764 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2764 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10060$2_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10060$2_DATA - connect \EN $memwr$\mem$ls180.v:10060$2_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2765 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2765 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10062$3_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10062$3_DATA - connect \EN $memwr$\mem$ls180.v:10062$3_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2766 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2766 - parameter \WIDTH 32 - connect \ADDR $memwr$\mem$ls180.v:10064$4_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10064$4_DATA - connect \EN $memwr$\mem$ls180.v:10064$4_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2767 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \PRIORITY 2767 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10078$5_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10078$5_DATA - connect \EN $memwr$\storage$ls180.v:10078$5_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2768 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \PRIORITY 2768 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10092$6_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10092$6_DATA - connect \EN $memwr$\storage_1$ls180.v:10092$6_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2769 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \PRIORITY 2769 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10106$7_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10106$7_DATA - connect \EN $memwr$\storage_2$ls180.v:10106$7_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2770 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \PRIORITY 2770 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10120$8_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10120$8_DATA - connect \EN $memwr$\storage_3$ls180.v:10120$8_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2771 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \PRIORITY 2771 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10135$9_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10135$9_DATA - connect \EN $memwr$\storage_4$ls180.v:10135$9_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2772 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \PRIORITY 2772 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10152$10_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10152$10_DATA - connect \EN $memwr$\storage_5$ls180.v:10152$10_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2773 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \PRIORITY 2773 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10168$11_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10168$11_DATA - connect \EN $memwr$\storage_6$ls180.v:10168$11_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2774 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \PRIORITY 2774 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10182$12_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10182$12_DATA - connect \EN $memwr$\storage_7$ls180.v:10182$12_EN - end - attribute \src "ls180.v:2966.41-2966.71" - cell $ne $ne$ls180.v:2966$60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $ne$ls180.v:2966$60_Y - end - attribute \src "ls180.v:3127.70-3127.104" - cell $ne $ne$ls180.v:3127$74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:3127$74_Y - end - attribute \src "ls180.v:3188.8-3188.142" - cell $ne $ne$ls180.v:3188$93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3188$93_Y - end - attribute \src "ls180.v:3220.75-3220.133" - cell $ne $ne$ls180.v:3220$100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3220$100_Y - end - attribute \src "ls180.v:3221.75-3221.133" - cell $ne $ne$ls180.v:3221$101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3221$101_Y - end - attribute \src "ls180.v:3345.8-3345.142" - cell $ne $ne$ls180.v:3345$123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3345$123_Y - end - attribute \src "ls180.v:3377.75-3377.133" - cell $ne $ne$ls180.v:3377$130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3377$130_Y - end - attribute \src "ls180.v:3378.75-3378.133" - cell $ne $ne$ls180.v:3378$131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3378$131_Y - end - attribute \src "ls180.v:3502.8-3502.142" - cell $ne $ne$ls180.v:3502$153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3502$153_Y - end - attribute \src "ls180.v:3534.75-3534.133" - cell $ne $ne$ls180.v:3534$160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3534$160_Y - end - attribute \src "ls180.v:3535.75-3535.133" - cell $ne $ne$ls180.v:3535$161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3535$161_Y - end - attribute \src "ls180.v:3659.8-3659.142" - cell $ne $ne$ls180.v:3659$183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3659$183_Y - end - attribute \src "ls180.v:3691.75-3691.133" - cell $ne $ne$ls180.v:3691$190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3691$190_Y - end - attribute \src "ls180.v:3692.75-3692.133" - cell $ne $ne$ls180.v:3692$191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3692$191_Y - end - attribute \src "ls180.v:4184.47-4184.80" - cell $ne $ne$ls180.v:4184$589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4184$589_Y - end - attribute \src "ls180.v:4185.47-4185.79" - cell $ne $ne$ls180.v:4185$590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4185$590_Y - end - attribute \src "ls180.v:4214.47-4214.80" - cell $ne $ne$ls180.v:4214$600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4214$600_Y - end - attribute \src "ls180.v:4215.47-4215.79" - cell $ne $ne$ls180.v:4215$601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4215$601_Y - end - attribute \src "ls180.v:4684.32-4684.89" - cell $ne $ne$ls180.v:4684$681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $ne$ls180.v:4684$681_Y - end - attribute \src "ls180.v:5331.10-5331.56" - cell $ne $ne$ls180.v:5331$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 2'10 - connect \Y $ne$ls180.v:5331$978_Y - end - attribute \src "ls180.v:5436.51-5436.87" - cell $ne $ne$ls180.v:5436$992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5436$992_Y - end - attribute \src "ls180.v:5437.51-5437.86" - cell $ne $ne$ls180.v:5437$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5437$993_Y - end - attribute \src "ls180.v:5644.51-5644.87" - cell $ne $ne$ls180.v:5644$1023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5644$1023_Y - end - attribute \src "ls180.v:5645.51-5645.86" - cell $ne $ne$ls180.v:5645$1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5645$1024_Y - end - attribute \src "ls180.v:5676.79-5676.119" - cell $ne $ne$ls180.v:5676$1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_sel - connect \B 1'0 - connect \Y $ne$ls180.v:5676$1027_Y - end - attribute \src "ls180.v:7498.7-7498.52" - cell $ne $ne$ls180.v:7498$2414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_bus_errors - connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7498$2414_Y - end - attribute \src "ls180.v:7548.9-7548.43" - cell $ne $ne$ls180.v:7548$2428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:7548$2428_Y - end - attribute \src "ls180.v:7584.8-7584.44" - cell $ne $ne$ls180.v:7584$2435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $ne$ls180.v:7584$2435_Y - end - attribute \src "ls180.v:8522.9-8522.47" - cell $ne $ne$ls180.v:8522$2650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1010 - connect \Y $ne$ls180.v:8522$2650_Y - end - attribute \src "ls180.v:2774.45-2774.80" - cell $not $not$ls180.v:2774$14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_ibus_cyc - connect \Y $not$ls180.v:2774$14_Y - end - attribute \src "ls180.v:2813.61-2813.94" - cell $not $not$ls180.v:2813$19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2813$19_Y - end - attribute \src "ls180.v:2814.61-2814.94" - cell $not $not$ls180.v:2814$20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter0_skip - connect \Y $not$ls180.v:2814$20_Y - end - attribute \src "ls180.v:2834.45-2834.80" - cell $not $not$ls180.v:2834$25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_dbus_cyc - connect \Y $not$ls180.v:2834$25_Y - end - attribute \src "ls180.v:2873.61-2873.94" - cell $not $not$ls180.v:2873$30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2873$30_Y - end - attribute \src "ls180.v:2874.61-2874.94" - cell $not $not$ls180.v:2874$31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter1_skip - connect \Y $not$ls180.v:2874$31_Y - end - attribute \src "ls180.v:2894.45-2894.83" - cell $not $not$ls180.v:2894$36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_jtag_wb_cyc - connect \Y $not$ls180.v:2894$36_Y - end - attribute \src "ls180.v:2933.61-2933.94" - cell $not $not$ls180.v:2933$41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2933$41_Y - end - attribute \src "ls180.v:2934.61-2934.94" - cell $not $not$ls180.v:2934$42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_converter2_skip - connect \Y $not$ls180.v:2934$42_Y - end - attribute \src "ls180.v:3076.34-3076.64" - cell $not $not$ls180.v:3076$66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3076$66_Y - end - attribute \src "ls180.v:3077.31-3077.61" - cell $not $not$ls180.v:3077$67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3077$67_Y - end - attribute \src "ls180.v:3078.32-3078.62" - cell $not $not$ls180.v:3078$68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3078$68_Y - end - attribute \src "ls180.v:3079.32-3079.62" - cell $not $not$ls180.v:3079$69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3079$69_Y - end - attribute \src "ls180.v:3121.33-3121.56" - cell $not $not$ls180.v:3121$72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3121$72_Y - end - attribute \src "ls180.v:3222.58-3222.106" - cell $not $not$ls180.v:3222$102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3222$102_Y - end - attribute \src "ls180.v:3276.9-3276.45" - cell $not $not$ls180.v:3276$107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3276$107_Y - end - attribute \src "ls180.v:3379.58-3379.106" - cell $not $not$ls180.v:3379$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3379$132_Y - end - attribute \src "ls180.v:3433.9-3433.45" - cell $not $not$ls180.v:3433$137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3433$137_Y - end - attribute \src "ls180.v:3536.58-3536.106" - cell $not $not$ls180.v:3536$162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3536$162_Y - end - attribute \src "ls180.v:3590.9-3590.45" - cell $not $not$ls180.v:3590$167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3590$167_Y - end - attribute \src "ls180.v:3693.58-3693.106" - cell $not $not$ls180.v:3693$192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3693$192_Y - end - attribute \src "ls180.v:3747.9-3747.45" - cell $not $not$ls180.v:3747$197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3747$197_Y - end - attribute \src "ls180.v:3789.149-3789.187" - cell $not $not$ls180.v:3789$200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3789$200_Y - end - attribute \src "ls180.v:3789.193-3789.230" - cell $not $not$ls180.v:3789$202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3789$202_Y - end - attribute \src "ls180.v:3790.149-3790.187" - cell $not $not$ls180.v:3790$206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3790$206_Y - end - attribute \src "ls180.v:3790.193-3790.230" - cell $not $not$ls180.v:3790$208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3790$208_Y - end - attribute \src "ls180.v:3806.43-3806.73" - cell $not $not$ls180.v:3806$236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3806$236_Y - end - attribute \src "ls180.v:3809.205-3809.245" - cell $not $not$ls180.v:3809$239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3809$239_Y - end - attribute \src "ls180.v:3809.251-3809.290" - cell $not $not$ls180.v:3809$241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3809$241_Y - end - attribute \src "ls180.v:3809.159-3809.292" - cell $not $not$ls180.v:3809$243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$242_Y - connect \Y $not$ls180.v:3809$243_Y - end - attribute \src "ls180.v:3810.205-3810.245" - cell $not $not$ls180.v:3810$252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3810$252_Y - end - attribute \src "ls180.v:3810.251-3810.290" - cell $not $not$ls180.v:3810$254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3810$254_Y - end - attribute \src "ls180.v:3810.159-3810.292" - cell $not $not$ls180.v:3810$256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$255_Y - connect \Y $not$ls180.v:3810$256_Y - end - attribute \src "ls180.v:3811.205-3811.245" - cell $not $not$ls180.v:3811$265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3811$265_Y - end - attribute \src "ls180.v:3811.251-3811.290" - cell $not $not$ls180.v:3811$267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3811$267_Y - end - attribute \src "ls180.v:3811.159-3811.292" - cell $not $not$ls180.v:3811$269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$268_Y - connect \Y $not$ls180.v:3811$269_Y - end - attribute \src "ls180.v:3812.205-3812.245" - cell $not $not$ls180.v:3812$278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3812$278_Y - end - attribute \src "ls180.v:3812.251-3812.290" - cell $not $not$ls180.v:3812$280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3812$280_Y - end - attribute \src "ls180.v:3812.159-3812.292" - cell $not $not$ls180.v:3812$282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3812$281_Y - connect \Y $not$ls180.v:3812$282_Y - end - attribute \src "ls180.v:3839.71-3839.103" - cell $not $not$ls180.v:3839$293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3839$293_Y - end - attribute \src "ls180.v:3842.205-3842.245" - cell $not $not$ls180.v:3842$297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3842$297_Y - end - attribute \src "ls180.v:3842.251-3842.290" - cell $not $not$ls180.v:3842$299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3842$299_Y - end - attribute \src "ls180.v:3842.159-3842.292" - cell $not $not$ls180.v:3842$301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$300_Y - connect \Y $not$ls180.v:3842$301_Y - end - attribute \src "ls180.v:3843.205-3843.245" - cell $not $not$ls180.v:3843$310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3843$310_Y - end - attribute \src "ls180.v:3843.251-3843.290" - cell $not $not$ls180.v:3843$312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3843$312_Y - end - attribute \src "ls180.v:3843.159-3843.292" - cell $not $not$ls180.v:3843$314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$313_Y - connect \Y $not$ls180.v:3843$314_Y - end - attribute \src "ls180.v:3844.205-3844.245" - cell $not $not$ls180.v:3844$323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3844$323_Y - end - attribute \src "ls180.v:3844.251-3844.290" - cell $not $not$ls180.v:3844$325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3844$325_Y - end - attribute \src "ls180.v:3844.159-3844.292" - cell $not $not$ls180.v:3844$327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$326_Y - connect \Y $not$ls180.v:3844$327_Y - end - attribute \src "ls180.v:3845.205-3845.245" - cell $not $not$ls180.v:3845$336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3845$336_Y - end - attribute \src "ls180.v:3845.251-3845.290" - cell $not $not$ls180.v:3845$338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3845$338_Y - end - attribute \src "ls180.v:3845.159-3845.292" - cell $not $not$ls180.v:3845$340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3845$339_Y - connect \Y $not$ls180.v:3845$340_Y - end - attribute \src "ls180.v:3908.71-3908.103" - cell $not $not$ls180.v:3908$379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3908$379_Y - end - attribute \src "ls180.v:3929.112-3929.150" - cell $not $not$ls180.v:3929$382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3929$382_Y - end - attribute \src "ls180.v:3929.156-3929.193" - cell $not $not$ls180.v:3929$384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3929$384_Y - end - attribute \src "ls180.v:3929.68-3929.195" - cell $not $not$ls180.v:3929$386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3929$385_Y - connect \Y $not$ls180.v:3929$386_Y - end - attribute \src "ls180.v:3937.11-3937.38" - cell $not $not$ls180.v:3937$389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_write_available - connect \Y $not$ls180.v:3937$389_Y - end - attribute \src "ls180.v:3967.112-3967.150" - cell $not $not$ls180.v:3967$391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3967$391_Y - end - attribute \src "ls180.v:3967.156-3967.193" - cell $not $not$ls180.v:3967$393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3967$393_Y - end - attribute \src "ls180.v:3967.68-3967.195" - cell $not $not$ls180.v:3967$395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3967$394_Y - connect \Y $not$ls180.v:3967$395_Y - end - attribute \src "ls180.v:3975.11-3975.37" - cell $not $not$ls180.v:3975$398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_read_available - connect \Y $not$ls180.v:3975$398_Y - end - attribute \src "ls180.v:3985.87-3985.331" - cell $not $not$ls180.v:3985$410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3985$409_Y - connect \Y $not$ls180.v:3985$410_Y - end - attribute \src "ls180.v:3986.35-3986.68" - cell $not $not$ls180.v:3986$413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:3986$413_Y - end - attribute \src "ls180.v:3986.73-3986.105" - cell $not $not$ls180.v:3986$414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:3986$414_Y - end - attribute \src "ls180.v:3990.87-3990.331" - cell $not $not$ls180.v:3990$426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3990$425_Y - connect \Y $not$ls180.v:3990$426_Y - end - attribute \src "ls180.v:3991.35-3991.68" - cell $not $not$ls180.v:3991$429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:3991$429_Y - end - attribute \src "ls180.v:3991.73-3991.105" - cell $not $not$ls180.v:3991$430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:3991$430_Y - end - attribute \src "ls180.v:3995.87-3995.331" - cell $not $not$ls180.v:3995$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3995$441_Y - connect \Y $not$ls180.v:3995$442_Y - end - attribute \src "ls180.v:3996.35-3996.68" - cell $not $not$ls180.v:3996$445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:3996$445_Y - end - attribute \src "ls180.v:3996.73-3996.105" - cell $not $not$ls180.v:3996$446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:3996$446_Y - end - attribute \src "ls180.v:4000.87-4000.331" - cell $not $not$ls180.v:4000$458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4000$457_Y - connect \Y $not$ls180.v:4000$458_Y - end - attribute \src "ls180.v:4001.35-4001.68" - cell $not $not$ls180.v:4001$461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4001$461_Y - end - attribute \src "ls180.v:4001.73-4001.105" - cell $not $not$ls180.v:4001$462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4001$462_Y - end - attribute \src "ls180.v:4005.128-4005.372" - cell $not $not$ls180.v:4005$475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$474_Y - connect \Y $not$ls180.v:4005$475_Y - end - attribute \src "ls180.v:4005.502-4005.746" - cell $not $not$ls180.v:4005$491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$490_Y - connect \Y $not$ls180.v:4005$491_Y - end - attribute \src "ls180.v:4005.876-4005.1120" - cell $not $not$ls180.v:4005$507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$506_Y - connect \Y $not$ls180.v:4005$507_Y - end - attribute \src "ls180.v:4005.1250-4005.1494" - cell $not $not$ls180.v:4005$523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$522_Y - connect \Y $not$ls180.v:4005$523_Y - end - attribute \src "ls180.v:4027.32-4027.50" - cell $not $not$ls180.v:4027$529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4027$529_Y - end - attribute \src "ls180.v:4066.30-4066.50" - cell $not $not$ls180.v:4066$534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4066$534_Y - end - attribute \src "ls180.v:4067.30-4067.50" - cell $not $not$ls180.v:4067$535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4067$535_Y - end - attribute \src "ls180.v:4092.27-4092.48" - cell $not $not$ls180.v:4092$541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4092$541_Y - end - attribute \src "ls180.v:4093.30-4093.50" - cell $not $not$ls180.v:4093$542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4093$542_Y - end - attribute \src "ls180.v:4094.80-4094.98" - cell $not $not$ls180.v:4094$544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4094$544_Y - end - attribute \src "ls180.v:4095.107-4095.127" - cell $not $not$ls180.v:4095$548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4095$548_Y - end - attribute \src "ls180.v:4096.78-4096.103" - cell $not $not$ls180.v:4096$551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4096$551_Y - end - attribute \src "ls180.v:4097.91-4097.111" - cell $not $not$ls180.v:4097$554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4097$554_Y - end - attribute \src "ls180.v:4113.35-4113.64" - cell $not $not$ls180.v:4113$563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4113$563_Y - end - attribute \src "ls180.v:4114.36-4114.67" - cell $not $not$ls180.v:4114$564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4114$564_Y - end - attribute \src "ls180.v:4120.32-4120.61" - cell $not $not$ls180.v:4120$565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4120$565_Y - end - attribute \src "ls180.v:4126.36-4126.67" - cell $not $not$ls180.v:4126$566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4126$566_Y - end - attribute \src "ls180.v:4127.35-4127.64" - cell $not $not$ls180.v:4127$567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4127$567_Y - end - attribute \src "ls180.v:4130.32-4130.63" - cell $not $not$ls180.v:4130$570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4130$570_Y - end - attribute \src "ls180.v:4168.81-4168.108" - cell $not $not$ls180.v:4168$580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4168$580_Y - end - attribute \src "ls180.v:4198.81-4198.108" - cell $not $not$ls180.v:4198$591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4198$591_Y - end - attribute \src "ls180.v:4398.60-4398.85" - cell $not $not$ls180.v:4398$640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4398$640_Y - end - attribute \src "ls180.v:4539.54-4539.96" - cell $not $not$ls180.v:4539$654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4539$654_Y - end - attribute \src "ls180.v:4542.48-4542.86" - cell $not $not$ls180.v:4542$657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4542$657_Y - end - attribute \src "ls180.v:4666.55-4666.98" - cell $not $not$ls180.v:4666$675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4666$675_Y - end - attribute \src "ls180.v:4669.49-4669.88" - cell $not $not$ls180.v:4669$678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4669$678_Y - end - attribute \src "ls180.v:4719.30-4719.58" - cell $not $not$ls180.v:4719$684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4719$684_Y - end - attribute \src "ls180.v:4800.56-4800.100" - cell $not $not$ls180.v:4800$690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4800$690_Y - end - attribute \src "ls180.v:4803.50-4803.90" - cell $not $not$ls180.v:4803$693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4803$693_Y - end - attribute \src "ls180.v:4919.42-4919.74" - cell $not $not$ls180.v:4919$709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4919$709_Y - end - attribute \src "ls180.v:5443.50-5443.88" - cell $not $not$ls180.v:5443$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5443$994_Y - end - attribute \src "ls180.v:5455.52-5455.102" - cell $not $not$ls180.v:5455$997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5455$997_Y - end - attribute \src "ls180.v:5514.38-5514.74" - cell $not $not$ls180.v:5514$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5514$1004_Y - end - attribute \src "ls180.v:5756.69-5756.88" - cell $not $not$ls180.v:5756$1065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \Y $not$ls180.v:5756$1065_Y - end - attribute \src "ls180.v:5773.63-5773.94" - cell $not $not$ls180.v:5773$1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5773$1086_Y - end - attribute \src "ls180.v:5776.65-5776.96" - cell $not $not$ls180.v:5776$1093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5776$1093_Y - end - attribute \src "ls180.v:5779.65-5779.96" - cell $not $not$ls180.v:5779$1100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5779$1100_Y - end - attribute \src "ls180.v:5782.65-5782.96" - cell $not $not$ls180.v:5782$1107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5782$1107_Y - end - attribute \src "ls180.v:5785.65-5785.96" - cell $not $not$ls180.v:5785$1114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5785$1114_Y - end - attribute \src "ls180.v:5788.68-5788.99" - cell $not $not$ls180.v:5788$1121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5788$1121_Y - end - attribute \src "ls180.v:5791.68-5791.99" - cell $not $not$ls180.v:5791$1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5791$1128_Y - end - attribute \src "ls180.v:5794.68-5794.99" - cell $not $not$ls180.v:5794$1135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5794$1135_Y - end - attribute \src "ls180.v:5797.68-5797.99" - cell $not $not$ls180.v:5797$1142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5797$1142_Y - end - attribute \src "ls180.v:5811.60-5811.91" - cell $not $not$ls180.v:5811$1150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5811$1150_Y - end - attribute \src "ls180.v:5814.60-5814.91" - cell $not $not$ls180.v:5814$1157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5814$1157_Y - end - attribute \src "ls180.v:5817.60-5817.91" - cell $not $not$ls180.v:5817$1164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5817$1164_Y - end - attribute \src "ls180.v:5820.60-5820.91" - cell $not $not$ls180.v:5820$1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5820$1171_Y - end - attribute \src "ls180.v:5823.61-5823.92" - cell $not $not$ls180.v:5823$1178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5823$1178_Y - end - attribute \src "ls180.v:5826.61-5826.92" - cell $not $not$ls180.v:5826$1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5826$1185_Y - end - attribute \src "ls180.v:5837.59-5837.90" - cell $not $not$ls180.v:5837$1193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5837$1193_Y - end - attribute \src "ls180.v:5840.58-5840.89" - cell $not $not$ls180.v:5840$1200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5840$1200_Y - end - attribute \src "ls180.v:5851.64-5851.95" - cell $not $not$ls180.v:5851$1208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5851$1208_Y - end - attribute \src "ls180.v:5854.63-5854.94" - cell $not $not$ls180.v:5854$1215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5854$1215_Y - end - attribute \src "ls180.v:5857.63-5857.94" - cell $not $not$ls180.v:5857$1222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5857$1222_Y - end - attribute \src "ls180.v:5860.63-5860.94" - cell $not $not$ls180.v:5860$1229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5860$1229_Y - end - attribute \src "ls180.v:5863.63-5863.94" - cell $not $not$ls180.v:5863$1236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5863$1236_Y - end - attribute \src "ls180.v:5866.64-5866.95" - cell $not $not$ls180.v:5866$1243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5866$1243_Y - end - attribute \src "ls180.v:5869.64-5869.95" - cell $not $not$ls180.v:5869$1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5869$1250_Y - end - attribute \src "ls180.v:5872.64-5872.95" - cell $not $not$ls180.v:5872$1257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5872$1257_Y - end - attribute \src "ls180.v:5875.64-5875.95" - cell $not $not$ls180.v:5875$1264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5875$1264_Y - end - attribute \src "ls180.v:5888.64-5888.95" - cell $not $not$ls180.v:5888$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5888$1272_Y - end - attribute \src "ls180.v:5891.63-5891.94" - cell $not $not$ls180.v:5891$1279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5891$1279_Y - end - attribute \src "ls180.v:5894.63-5894.94" - cell $not $not$ls180.v:5894$1286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - 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\Y $not$ls180.v:5906$1314_Y - end - attribute \src "ls180.v:5909.64-5909.95" - cell $not $not$ls180.v:5909$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5909$1321_Y - end - attribute \src "ls180.v:5912.64-5912.95" - cell $not $not$ls180.v:5912$1328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5912$1328_Y - end - attribute \src "ls180.v:5925.66-5925.97" - cell $not $not$ls180.v:5925$1336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5925$1336_Y - end - attribute \src "ls180.v:5928.66-5928.97" - cell $not $not$ls180.v:5928$1343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5928$1343_Y - end - attribute \src "ls180.v:5931.66-5931.97" - cell $not $not$ls180.v:5931$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5931$1350_Y - end - attribute \src "ls180.v:5934.66-5934.97" - cell $not $not$ls180.v:5934$1357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5934$1357_Y - end - attribute \src "ls180.v:5937.66-5937.97" - cell $not $not$ls180.v:5937$1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5937$1364_Y - end - attribute \src "ls180.v:5940.66-5940.97" - cell $not $not$ls180.v:5940$1371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5940$1371_Y - end - attribute \src "ls180.v:5943.66-5943.97" - cell $not $not$ls180.v:5943$1378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5943$1378_Y - end - attribute \src "ls180.v:5946.66-5946.97" - cell $not $not$ls180.v:5946$1385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5946$1385_Y - end - attribute \src "ls180.v:5949.68-5949.99" - cell $not $not$ls180.v:5949$1392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5949$1392_Y - end - attribute \src "ls180.v:5952.68-5952.99" - cell $not $not$ls180.v:5952$1399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5952$1399_Y - end - attribute \src "ls180.v:5955.68-5955.99" - cell $not $not$ls180.v:5955$1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5955$1406_Y - end - attribute \src "ls180.v:5958.68-5958.99" - cell $not $not$ls180.v:5958$1413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5958$1413_Y - end - attribute \src "ls180.v:5961.68-5961.99" - cell $not $not$ls180.v:5961$1420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5961$1420_Y - end - attribute \src "ls180.v:5964.65-5964.96" - cell $not $not$ls180.v:5964$1427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5964$1427_Y - end - attribute \src "ls180.v:5967.66-5967.97" - cell $not $not$ls180.v:5967$1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:5967$1434_Y - end - attribute \src "ls180.v:5987.70-5987.101" - cell $not $not$ls180.v:5987$1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5987$1442_Y - end - attribute \src "ls180.v:5990.70-5990.101" - cell $not $not$ls180.v:5990$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5990$1449_Y - end - attribute \src "ls180.v:5993.70-5993.101" - cell $not $not$ls180.v:5993$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5993$1456_Y - end - attribute \src "ls180.v:5996.70-5996.101" - cell $not $not$ls180.v:5996$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5996$1463_Y - end - attribute \src "ls180.v:5999.69-5999.100" - cell $not $not$ls180.v:5999$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:5999$1470_Y - end - attribute \src "ls180.v:6002.69-6002.100" - cell $not $not$ls180.v:6002$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6002$1477_Y - end - attribute \src "ls180.v:6005.69-6005.100" - cell $not $not$ls180.v:6005$1484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6005$1484_Y - end - attribute \src "ls180.v:6008.69-6008.100" - cell $not $not$ls180.v:6008$1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6008$1491_Y - end - attribute \src "ls180.v:6011.60-6011.91" - cell $not $not$ls180.v:6011$1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6011$1498_Y - end - attribute \src "ls180.v:6014.71-6014.102" - cell $not $not$ls180.v:6014$1505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6014$1505_Y - end - attribute \src "ls180.v:6017.71-6017.102" - cell $not $not$ls180.v:6017$1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6017$1512_Y - end - attribute \src "ls180.v:6020.71-6020.102" - cell $not $not$ls180.v:6020$1519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6020$1519_Y - end - attribute \src "ls180.v:6023.71-6023.102" - cell $not $not$ls180.v:6023$1526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6023$1526_Y - end - attribute \src "ls180.v:6026.71-6026.102" - cell $not $not$ls180.v:6026$1533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6026$1533_Y - end - attribute \src "ls180.v:6029.71-6029.102" - cell $not $not$ls180.v:6029$1540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6029$1540_Y - end - attribute \src "ls180.v:6032.70-6032.101" - cell $not $not$ls180.v:6032$1547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6032$1547_Y - end - attribute \src "ls180.v:6035.70-6035.101" - cell $not $not$ls180.v:6035$1554 - parameter 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$not$ls180.v:6390$2115_Y - end - attribute \src "ls180.v:6393.77-6393.109" - cell $not $not$ls180.v:6393$2122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6393$2122_Y - end - attribute \src "ls180.v:6396.78-6396.110" - cell $not $not$ls180.v:6396$2129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6396$2129_Y - end - attribute \src "ls180.v:6399.69-6399.101" - cell $not $not$ls180.v:6399$2136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6399$2136_Y - end - attribute \src "ls180.v:6419.55-6419.87" - cell $not $not$ls180.v:6419$2144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6419$2144_Y - end - attribute \src "ls180.v:6422.65-6422.97" - cell $not $not$ls180.v:6422$2151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6422$2151_Y - end - attribute \src "ls180.v:6425.66-6425.98" - cell $not $not$ls180.v:6425$2158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6425$2158_Y - end - attribute \src "ls180.v:6428.70-6428.102" - cell $not $not$ls180.v:6428$2165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6428$2165_Y - end - attribute \src "ls180.v:6431.71-6431.103" - cell $not $not$ls180.v:6431$2172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6431$2172_Y - end - attribute \src "ls180.v:6434.69-6434.101" - cell $not $not$ls180.v:6434$2179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6434$2179_Y - end - attribute \src "ls180.v:6437.66-6437.98" - cell $not $not$ls180.v:6437$2186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6437$2186_Y - end - attribute \src "ls180.v:6440.65-6440.97" - cell $not $not$ls180.v:6440$2193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6440$2193_Y - end - attribute \src "ls180.v:6453.71-6453.103" - cell $not $not$ls180.v:6453$2201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6453$2201_Y - end - attribute \src "ls180.v:6456.71-6456.103" - cell $not $not$ls180.v:6456$2208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6456$2208_Y - end - attribute \src "ls180.v:6459.71-6459.103" - cell $not $not$ls180.v:6459$2215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6459$2215_Y - end - attribute \src "ls180.v:6462.71-6462.103" - cell $not $not$ls180.v:6462$2222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6462$2222_Y - end - attribute \src "ls180.v:6843.86-6843.330" - cell $not $not$ls180.v:6843$2271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6843$2270_Y - connect \Y $not$ls180.v:6843$2271_Y - end - attribute \src "ls180.v:6867.86-6867.330" - cell $not $not$ls180.v:6867$2287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6867$2286_Y - connect \Y $not$ls180.v:6867$2287_Y - end - attribute \src "ls180.v:6891.86-6891.330" - cell $not $not$ls180.v:6891$2303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6891$2302_Y - connect \Y $not$ls180.v:6891$2303_Y - end - attribute \src "ls180.v:6915.86-6915.330" - cell $not $not$ls180.v:6915$2319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6915$2318_Y - connect \Y $not$ls180.v:6915$2319_Y - end - attribute \src "ls180.v:7413.18-7413.42" - cell $not $not$ls180.v:7413$2372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7413$2372_Y - end - attribute \src "ls180.v:7504.72-7504.101" - cell $not $not$ls180.v:7504$2417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7504$2417_Y - end - attribute \src "ls180.v:7523.8-7523.38" - cell $not $not$ls180.v:7523$2421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7523$2421_Y - end - attribute \src "ls180.v:7531.32-7531.55" - cell $not $not$ls180.v:7531$2423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7531$2423_Y - end - attribute \src "ls180.v:7601.136-7601.189" - cell $not $not$ls180.v:7601$2438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7601$2438_Y - end - attribute \src "ls180.v:7607.136-7607.189" - cell $not $not$ls180.v:7607$2443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7607$2443_Y - end - attribute \src "ls180.v:7608.8-7608.61" - cell $not $not$ls180.v:7608$2445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7608$2445_Y - end - attribute \src "ls180.v:7616.8-7616.56" - cell $not $not$ls180.v:7616$2448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7616$2448_Y - end - attribute \src "ls180.v:7631.8-7631.46" - cell $not $not$ls180.v:7631$2450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7631$2450_Y - end - attribute \src "ls180.v:7647.136-7647.189" - cell $not $not$ls180.v:7647$2454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7647$2454_Y - end - attribute \src "ls180.v:7653.136-7653.189" - cell $not $not$ls180.v:7653$2459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7653$2459_Y - end - attribute \src "ls180.v:7654.8-7654.61" - cell $not $not$ls180.v:7654$2461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7654$2461_Y - end - attribute \src "ls180.v:7662.8-7662.56" - cell $not $not$ls180.v:7662$2464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7662$2464_Y - end - attribute \src "ls180.v:7677.8-7677.46" - cell $not $not$ls180.v:7677$2466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7677$2466_Y - end - attribute \src "ls180.v:7693.136-7693.189" - cell $not $not$ls180.v:7693$2470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7693$2470_Y - end - attribute \src "ls180.v:7699.136-7699.189" - cell $not $not$ls180.v:7699$2475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7699$2475_Y - end - attribute \src "ls180.v:7700.8-7700.61" - cell $not $not$ls180.v:7700$2477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7700$2477_Y - end - attribute \src "ls180.v:7708.8-7708.56" - cell $not $not$ls180.v:7708$2480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7708$2480_Y - end - attribute \src "ls180.v:7723.8-7723.46" - cell $not $not$ls180.v:7723$2482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7723$2482_Y - end - attribute \src "ls180.v:7739.136-7739.189" - cell $not $not$ls180.v:7739$2486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7739$2486_Y - end - attribute \src "ls180.v:7745.136-7745.189" - cell $not $not$ls180.v:7745$2491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7745$2491_Y - end - attribute \src "ls180.v:7746.8-7746.61" - cell $not $not$ls180.v:7746$2493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7746$2493_Y - end - attribute \src "ls180.v:7754.8-7754.56" - cell $not $not$ls180.v:7754$2496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7754$2496_Y - end - attribute \src "ls180.v:7769.8-7769.46" - cell $not $not$ls180.v:7769$2498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7769$2498_Y - end - attribute \src "ls180.v:7777.7-7777.22" - cell $not $not$ls180.v:7777$2501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7777$2501_Y - end - attribute \src "ls180.v:7780.8-7780.29" - cell $not $not$ls180.v:7780$2502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7780$2502_Y - end - attribute \src "ls180.v:7784.7-7784.22" - cell $not $not$ls180.v:7784$2504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7784$2504_Y - end - attribute \src "ls180.v:7787.8-7787.29" - cell $not $not$ls180.v:7787$2505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7787$2505_Y - end - attribute \src "ls180.v:7906.30-7906.60" - cell $not $not$ls180.v:7906$2507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:7906$2507_Y - end - attribute \src "ls180.v:7907.30-7907.60" - cell $not $not$ls180.v:7907$2508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:7907$2508_Y - end - attribute \src "ls180.v:7908.29-7908.59" - cell $not $not$ls180.v:7908$2509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:7908$2509_Y - end - attribute \src "ls180.v:7919.8-7919.33" - cell $not $not$ls180.v:7919$2510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:7919$2510_Y - end - attribute \src "ls180.v:7934.8-7934.33" - cell $not $not$ls180.v:7934$2513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:7934$2513_Y - end - attribute \src "ls180.v:7970.36-7970.58" - cell $not $not$ls180.v:7970$2543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:7970$2543_Y - end - attribute \src "ls180.v:7970.64-7970.89" - cell $not $not$ls180.v:7970$2545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:7970$2545_Y - end - attribute \src "ls180.v:7999.7-7999.29" - cell $not $not$ls180.v:7999$2552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:7999$2552_Y - end - attribute \src "ls180.v:8000.9-8000.26" - cell $not $not$ls180.v:8000$2553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8000$2553_Y - end - attribute \src "ls180.v:8033.8-8033.29" - cell $not $not$ls180.v:8033$2559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8033$2559_Y - end - attribute \src "ls180.v:8040.8-8040.29" - cell $not $not$ls180.v:8040$2561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8040$2561_Y - end - attribute \src "ls180.v:8050.80-8050.106" - cell $not $not$ls180.v:8050$2564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8050$2564_Y - end - attribute \src "ls180.v:8056.80-8056.106" - cell $not $not$ls180.v:8056$2569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8056$2569_Y - end - attribute \src "ls180.v:8057.8-8057.34" - cell $not $not$ls180.v:8057$2571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8057$2571_Y - end - attribute \src "ls180.v:8072.80-8072.106" - cell $not $not$ls180.v:8072$2575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8072$2575_Y - end - attribute \src "ls180.v:8078.80-8078.106" - cell $not $not$ls180.v:8078$2580 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8078$2580_Y - end - attribute \src "ls180.v:8079.8-8079.34" - cell $not $not$ls180.v:8079$2582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8079$2582_Y - end - attribute \src "ls180.v:8110.22-8110.41" - cell $not $not$ls180.v:8110$2586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8110$2586_Y - end - attribute \src "ls180.v:8110.46-8110.73" - cell $not $not$ls180.v:8110$2587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8110$2587_Y - end - attribute \src "ls180.v:8145.22-8145.40" - cell $not $not$ls180.v:8145$2591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8145$2591_Y - end - attribute \src "ls180.v:8145.45-8145.70" - cell $not $not$ls180.v:8145$2592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8145$2592_Y - end - attribute \src "ls180.v:8199.7-8199.31" - cell $not $not$ls180.v:8199$2603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8199$2603_Y - end - attribute \src "ls180.v:8271.8-8271.46" - cell $not $not$ls180.v:8271$2615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8271$2615_Y - end - attribute \src "ls180.v:8352.8-8352.47" - cell $not $not$ls180.v:8352$2627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8352$2627_Y - end - attribute \src "ls180.v:8413.8-8413.48" - cell $not $not$ls180.v:8413$2639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8413$2639_Y - end - attribute \src "ls180.v:8583.88-8583.118" - cell $not $not$ls180.v:8583$2653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8583$2653_Y - end - attribute \src "ls180.v:8589.88-8589.118" - cell $not $not$ls180.v:8589$2658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8589$2658_Y - end - attribute \src "ls180.v:8590.8-8590.38" - cell $not $not$ls180.v:8590$2660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8590$2660_Y - end - attribute \src "ls180.v:8669.88-8669.118" - cell $not $not$ls180.v:8669$2675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8669$2675_Y - end - attribute \src "ls180.v:8675.88-8675.118" - cell $not $not$ls180.v:8675$2680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8675$2680_Y - end - attribute \src "ls180.v:8676.8-8676.38" - cell $not $not$ls180.v:8676$2682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8676$2682_Y - end - attribute \src "ls180.v:8696.9-8696.28" - cell $not $not$ls180.v:8696$2685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [0] - connect \Y $not$ls180.v:8696$2685_Y - end - attribute \src "ls180.v:8715.9-8715.28" - cell $not $not$ls180.v:8715$2686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [1] - connect \Y $not$ls180.v:8715$2686_Y - end - attribute \src "ls180.v:8734.9-8734.28" - cell $not $not$ls180.v:8734$2687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [2] - connect \Y $not$ls180.v:8734$2687_Y - end - attribute \src "ls180.v:8753.9-8753.28" - cell $not $not$ls180.v:8753$2688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [3] - connect \Y $not$ls180.v:8753$2688_Y - end - attribute \src "ls180.v:8772.9-8772.28" - cell $not $not$ls180.v:8772$2689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [4] - connect \Y $not$ls180.v:8772$2689_Y - end - attribute \src "ls180.v:8793.8-8793.21" - cell $not $not$ls180.v:8793$2690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_done - connect \Y $not$ls180.v:8793$2690_Y - end - attribute \src "ls180.v:10292.8-10292.51" - cell $or $or$ls180.v:10292$2762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sys_rst_1 - connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10292$2762_Y - end - attribute \src "ls180.v:2815.10-2815.96" - cell $or $or$ls180.v:2815$21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:2815$21_Y - end - attribute \src "ls180.v:2875.10-2875.96" - cell $or $or$ls180.v:2875$32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:2875$32_Y - end - attribute \src "ls180.v:2935.10-2935.96" - cell $or $or$ls180.v:2935$43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:2935$43_Y - end - attribute \src "ls180.v:3127.39-3127.105" - cell $or $or$ls180.v:3127$75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3127$74_Y - connect \Y $or$ls180.v:3127$75_Y - end - attribute \src "ls180.v:3170.59-3170.140" - cell $or $or$ls180.v:3170$79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_req_wdata_ready - connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3170$79_Y - end - attribute \src "ls180.v:3171.44-3171.151" - cell $or $or$ls180.v:3171$80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3171$80_Y - end - attribute \src "ls180.v:3179.45-3179.170" - cell $or $or$ls180.v:3179$84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3179$83_Y - connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3179$84_Y - end - attribute \src "ls180.v:3216.127-3216.245" - cell $or $or$ls180.v:3216$97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3216$97_Y - end - attribute \src "ls180.v:3222.57-3222.157" - cell $or $or$ls180.v:3222$103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3222$102_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3222$103_Y - end - attribute \src "ls180.v:3327.59-3327.140" - cell $or $or$ls180.v:3327$109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_req_wdata_ready - connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3327$109_Y - end - attribute \src "ls180.v:3328.44-3328.151" - cell $or $or$ls180.v:3328$110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3328$110_Y - end - attribute \src "ls180.v:3336.45-3336.170" - cell $or $or$ls180.v:3336$114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3336$113_Y - connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3336$114_Y - end - attribute \src "ls180.v:3373.127-3373.245" - cell $or $or$ls180.v:3373$127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3373$127_Y - end - attribute \src "ls180.v:3379.57-3379.157" - cell $or $or$ls180.v:3379$133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3379$132_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3379$133_Y - end - attribute \src "ls180.v:3484.59-3484.140" - cell $or $or$ls180.v:3484$139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_req_wdata_ready - connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3484$139_Y - end - attribute \src "ls180.v:3485.44-3485.151" - cell $or $or$ls180.v:3485$140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3485$140_Y - end - attribute \src "ls180.v:3493.45-3493.170" - cell $or $or$ls180.v:3493$144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3493$143_Y - connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3493$144_Y - end - attribute \src "ls180.v:3530.127-3530.245" - cell $or $or$ls180.v:3530$157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3530$157_Y - end - attribute \src "ls180.v:3536.57-3536.157" - cell $or $or$ls180.v:3536$163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3536$162_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3536$163_Y - end - attribute \src "ls180.v:3641.59-3641.140" - cell $or $or$ls180.v:3641$169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_req_wdata_ready - connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3641$169_Y - end - attribute \src "ls180.v:3642.44-3642.151" - cell $or $or$ls180.v:3642$170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3642$170_Y - end - attribute \src "ls180.v:3650.45-3650.170" - cell $or $or$ls180.v:3650$174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3650$173_Y - connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3650$174_Y - end - attribute \src "ls180.v:3687.127-3687.245" - cell $or $or$ls180.v:3687$187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3687$187_Y - end - attribute \src "ls180.v:3693.57-3693.157" - cell $or $or$ls180.v:3693$193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3693$192_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3693$193_Y - end - attribute \src "ls180.v:3792.107-3792.193" - cell $or $or$ls180.v:3792$213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_is_write - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3792$213_Y - end - attribute \src "ls180.v:3795.39-3795.204" - cell $or $or$ls180.v:3795$219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3795$217_Y - connect \B $and$ls180.v:3795$218_Y - connect \Y $or$ls180.v:3795$219_Y - end - attribute \src "ls180.v:3795.38-3795.289" - cell $or $or$ls180.v:3795$221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3795$219_Y - connect \B $and$ls180.v:3795$220_Y - connect \Y $or$ls180.v:3795$221_Y - end - attribute \src "ls180.v:3795.37-3795.374" - cell $or $or$ls180.v:3795$223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3795$221_Y - connect \B $and$ls180.v:3795$222_Y - connect \Y $or$ls180.v:3795$223_Y - end - attribute \src "ls180.v:3796.40-3796.207" - cell $or $or$ls180.v:3796$226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3796$224_Y - connect \B $and$ls180.v:3796$225_Y - connect \Y $or$ls180.v:3796$226_Y - end - attribute \src "ls180.v:3796.39-3796.293" - cell $or $or$ls180.v:3796$228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3796$226_Y - connect \B $and$ls180.v:3796$227_Y - connect \Y $or$ls180.v:3796$228_Y - end - attribute \src "ls180.v:3796.38-3796.379" - cell $or $or$ls180.v:3796$230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3796$228_Y - connect \B $and$ls180.v:3796$229_Y - connect \Y $or$ls180.v:3796$230_Y - end - attribute \src "ls180.v:3809.158-3809.332" - cell $or $or$ls180.v:3809$244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3809$243_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3809$244_Y - end - attribute \src "ls180.v:3809.75-3809.506" - cell $or $or$ls180.v:3809$249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3809$245_Y - connect \B $and$ls180.v:3809$248_Y - connect \Y $or$ls180.v:3809$249_Y - end - attribute \src "ls180.v:3810.158-3810.332" - cell $or $or$ls180.v:3810$257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3810$256_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3810$257_Y - end - attribute \src "ls180.v:3810.75-3810.506" - cell $or $or$ls180.v:3810$262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3810$258_Y - connect \B $and$ls180.v:3810$261_Y - connect \Y $or$ls180.v:3810$262_Y - end - attribute \src "ls180.v:3811.158-3811.332" - cell $or $or$ls180.v:3811$270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3811$269_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3811$270_Y - end - attribute \src "ls180.v:3811.75-3811.506" - cell $or $or$ls180.v:3811$275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3811$271_Y - connect \B $and$ls180.v:3811$274_Y - connect \Y $or$ls180.v:3811$275_Y - end - attribute \src "ls180.v:3812.158-3812.332" - cell $or $or$ls180.v:3812$283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3812$282_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3812$283_Y - end - attribute \src "ls180.v:3812.75-3812.506" - cell $or $or$ls180.v:3812$288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3812$284_Y - connect \B $and$ls180.v:3812$287_Y - connect \Y $or$ls180.v:3812$288_Y - end - attribute \src "ls180.v:3839.36-3839.104" - cell $or $or$ls180.v:3839$294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3839$293_Y - connect \Y $or$ls180.v:3839$294_Y - end - attribute \src "ls180.v:3842.158-3842.332" - cell $or $or$ls180.v:3842$302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3842$301_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3842$302_Y - end - attribute \src "ls180.v:3842.75-3842.506" - cell $or $or$ls180.v:3842$307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$303_Y - connect \B $and$ls180.v:3842$306_Y - connect \Y $or$ls180.v:3842$307_Y - end - attribute \src "ls180.v:3843.158-3843.332" - cell $or $or$ls180.v:3843$315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3843$314_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3843$315_Y - end - attribute \src "ls180.v:3843.75-3843.506" - cell $or $or$ls180.v:3843$320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$316_Y - connect \B $and$ls180.v:3843$319_Y - connect \Y $or$ls180.v:3843$320_Y - end - attribute \src "ls180.v:3844.158-3844.332" - cell $or $or$ls180.v:3844$328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3844$327_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3844$328_Y - end - attribute \src "ls180.v:3844.75-3844.506" - cell $or $or$ls180.v:3844$333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$329_Y - connect \B $and$ls180.v:3844$332_Y - connect \Y $or$ls180.v:3844$333_Y - end - attribute \src "ls180.v:3845.158-3845.332" - cell $or $or$ls180.v:3845$341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3845$340_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3845$341_Y - end - attribute \src "ls180.v:3845.75-3845.506" - cell $or $or$ls180.v:3845$346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3845$342_Y - connect \B $and$ls180.v:3845$345_Y - connect \Y $or$ls180.v:3845$346_Y - end - attribute \src "ls180.v:3908.36-3908.104" - cell $or $or$ls180.v:3908$380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3908$379_Y - connect \Y $or$ls180.v:3908$380_Y - end - attribute \src "ls180.v:3929.67-3929.221" - cell $or $or$ls180.v:3929$387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3929$386_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3929$387_Y - end - attribute \src "ls180.v:3937.10-3937.62" - cell $or $or$ls180.v:3937$390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3937$389_Y - connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:3937$390_Y - end - attribute \src "ls180.v:3967.67-3967.221" - cell $or $or$ls180.v:3967$396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3967$395_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3967$396_Y - end - attribute \src "ls180.v:3975.10-3975.61" - cell $or $or$ls180.v:3975$399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3975$398_Y - connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:3975$399_Y - end - attribute \src "ls180.v:3985.91-3985.180" - cell $or $or$ls180.v:3985$403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:3985$402_Y - connect \Y $or$ls180.v:3985$403_Y - end - attribute \src "ls180.v:3985.90-3985.255" - cell $or $or$ls180.v:3985$406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3985$403_Y - connect \B $and$ls180.v:3985$405_Y - connect \Y $or$ls180.v:3985$406_Y - end - attribute \src "ls180.v:3985.89-3985.330" - cell $or $or$ls180.v:3985$409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3985$406_Y - connect \B $and$ls180.v:3985$408_Y - connect \Y $or$ls180.v:3985$409_Y - end - attribute \src "ls180.v:3990.91-3990.180" - cell $or $or$ls180.v:3990$419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:3990$418_Y - connect \Y $or$ls180.v:3990$419_Y - end - attribute \src "ls180.v:3990.90-3990.255" - cell $or $or$ls180.v:3990$422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3990$419_Y - connect \B $and$ls180.v:3990$421_Y - connect \Y $or$ls180.v:3990$422_Y - end - attribute \src "ls180.v:3990.89-3990.330" - cell $or $or$ls180.v:3990$425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3990$422_Y - connect \B $and$ls180.v:3990$424_Y - connect \Y $or$ls180.v:3990$425_Y - end - attribute \src "ls180.v:3995.91-3995.180" - cell $or $or$ls180.v:3995$435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:3995$434_Y - connect \Y $or$ls180.v:3995$435_Y - end - attribute \src "ls180.v:3995.90-3995.255" - cell $or $or$ls180.v:3995$438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3995$435_Y - connect \B $and$ls180.v:3995$437_Y - connect \Y $or$ls180.v:3995$438_Y - end - attribute \src "ls180.v:3995.89-3995.330" - cell $or $or$ls180.v:3995$441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3995$438_Y - connect \B $and$ls180.v:3995$440_Y - connect \Y $or$ls180.v:3995$441_Y - end - attribute \src "ls180.v:4000.91-4000.180" - cell $or $or$ls180.v:4000$451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4000$450_Y - connect \Y $or$ls180.v:4000$451_Y - end - attribute \src "ls180.v:4000.90-4000.255" - cell $or $or$ls180.v:4000$454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4000$451_Y - connect \B $and$ls180.v:4000$453_Y - connect \Y $or$ls180.v:4000$454_Y - end - attribute \src "ls180.v:4000.89-4000.330" - cell $or $or$ls180.v:4000$457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4000$454_Y - connect \B $and$ls180.v:4000$456_Y - connect \Y $or$ls180.v:4000$457_Y - end - attribute \src "ls180.v:4005.132-4005.221" - cell $or $or$ls180.v:4005$468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:4005$467_Y - connect \Y $or$ls180.v:4005$468_Y - end - attribute \src "ls180.v:4005.131-4005.296" - cell $or $or$ls180.v:4005$471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$468_Y - connect \B $and$ls180.v:4005$470_Y - connect \Y $or$ls180.v:4005$471_Y - end - attribute \src "ls180.v:4005.130-4005.371" - cell $or $or$ls180.v:4005$474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$471_Y - connect \B $and$ls180.v:4005$473_Y - connect \Y $or$ls180.v:4005$474_Y - end - attribute \src "ls180.v:4005.34-4005.411" - cell $or $or$ls180.v:4005$479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:4005$478_Y - connect \Y $or$ls180.v:4005$479_Y - end - attribute \src "ls180.v:4005.506-4005.595" - cell $or $or$ls180.v:4005$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:4005$483_Y - connect \Y $or$ls180.v:4005$484_Y - end - attribute \src "ls180.v:4005.505-4005.670" - cell $or $or$ls180.v:4005$487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$484_Y - connect \B $and$ls180.v:4005$486_Y - connect \Y $or$ls180.v:4005$487_Y - end - attribute \src "ls180.v:4005.504-4005.745" - cell $or $or$ls180.v:4005$490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$487_Y - connect \B $and$ls180.v:4005$489_Y - connect \Y $or$ls180.v:4005$490_Y - end - attribute \src "ls180.v:4005.33-4005.785" - cell $or $or$ls180.v:4005$495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$479_Y - connect \B $and$ls180.v:4005$494_Y - connect \Y $or$ls180.v:4005$495_Y - end - attribute \src "ls180.v:4005.880-4005.969" - cell $or $or$ls180.v:4005$500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:4005$499_Y - connect \Y $or$ls180.v:4005$500_Y - end - attribute \src "ls180.v:4005.879-4005.1044" - cell $or $or$ls180.v:4005$503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$500_Y - connect \B $and$ls180.v:4005$502_Y - connect \Y $or$ls180.v:4005$503_Y - end - attribute \src "ls180.v:4005.878-4005.1119" - cell $or $or$ls180.v:4005$506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$503_Y - connect \B $and$ls180.v:4005$505_Y - connect \Y $or$ls180.v:4005$506_Y - end - attribute \src "ls180.v:4005.32-4005.1159" - cell $or $or$ls180.v:4005$511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$495_Y - connect \B $and$ls180.v:4005$510_Y - connect \Y $or$ls180.v:4005$511_Y - end - attribute \src "ls180.v:4005.1254-4005.1343" - cell $or $or$ls180.v:4005$516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4005$515_Y - connect \Y $or$ls180.v:4005$516_Y - end - attribute \src "ls180.v:4005.1253-4005.1418" - cell $or $or$ls180.v:4005$519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$516_Y - connect \B $and$ls180.v:4005$518_Y - connect \Y $or$ls180.v:4005$519_Y - end - attribute \src "ls180.v:4005.1252-4005.1493" - cell $or $or$ls180.v:4005$522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$519_Y - connect \B $and$ls180.v:4005$521_Y - connect \Y $or$ls180.v:4005$522_Y - end - attribute \src "ls180.v:4005.31-4005.1533" - cell $or $or$ls180.v:4005$527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4005$511_Y - connect \B $and$ls180.v:4005$526_Y - connect \Y $or$ls180.v:4005$527_Y - end - attribute \src "ls180.v:4068.10-4068.52" - cell $or $or$ls180.v:4068$536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:4068$536_Y - end - attribute \src "ls180.v:4095.35-4095.74" - cell $or $or$ls180.v:4095$546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4095$546_Y - end - attribute \src "ls180.v:4096.34-4096.73" - cell $or $or$ls180.v:4096$550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4096$550_Y - end - attribute \src "ls180.v:4097.48-4097.130" - cell $or $or$ls180.v:4097$556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4097$553_Y - connect \B $and$ls180.v:4097$555_Y - connect \Y $or$ls180.v:4097$556_Y - end - attribute \src "ls180.v:4098.24-4098.87" - cell $or $or$ls180.v:4098$559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4098$558_Y - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4098$559_Y - end - attribute \src "ls180.v:4099.26-4099.95" - cell $or $or$ls180.v:4099$561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4099$560_Y - connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4099$561_Y - end - attribute \src "ls180.v:4129.42-4129.89" - cell $or $or$ls180.v:4129$569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4129$568_Y - connect \Y $or$ls180.v:4129$569_Y - end - attribute \src "ls180.v:4153.25-4153.174" - cell $or $or$ls180.v:4153$579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4153$577_Y - connect \B $and$ls180.v:4153$578_Y - connect \Y $or$ls180.v:4153$579_Y - end - attribute \src "ls180.v:4168.80-4168.132" - cell $or $or$ls180.v:4168$581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4168$580_Y - connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4168$581_Y - end - attribute \src "ls180.v:4179.72-4179.135" - cell $or $or$ls180.v:4179$586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_writable - connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4179$586_Y - end - attribute \src "ls180.v:4198.80-4198.132" - cell $or $or$ls180.v:4198$592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4198$591_Y - connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4198$592_Y - end - attribute \src "ls180.v:4209.72-4209.135" - cell $or $or$ls180.v:4209$597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_writable - connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4209$597_Y - end - attribute \src "ls180.v:4343.36-4343.111" - cell $or $or$ls180.v:4343$618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_clk - connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4343$618_Y - end - attribute \src "ls180.v:4343.35-4343.151" - cell $or $or$ls180.v:4343$619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4343$618_Y - connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4343$619_Y - end - attribute \src "ls180.v:4343.34-4343.192" - cell $or $or$ls180.v:4343$620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4343$619_Y - connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4343$620_Y - end - attribute \src "ls180.v:4343.33-4343.233" - cell $or $or$ls180.v:4343$621 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4343$620_Y - connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4343$621_Y - end - attribute \src "ls180.v:4344.39-4344.120" - cell $or $or$ls180.v:4344$622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_oe - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4344$622_Y - end - attribute \src "ls180.v:4344.38-4344.163" - cell $or $or$ls180.v:4344$623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4344$622_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4344$623_Y - end - attribute \src "ls180.v:4344.37-4344.207" - cell $or $or$ls180.v:4344$624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4344$623_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4344$624_Y - end - attribute \src "ls180.v:4344.36-4344.251" - cell $or $or$ls180.v:4344$625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4344$624_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4344$625_Y - end - attribute \src "ls180.v:4345.38-4345.117" - cell $or $or$ls180.v:4345$626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_o - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4345$626_Y - end - attribute \src "ls180.v:4345.37-4345.159" - cell $or $or$ls180.v:4345$627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4345$626_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4345$627_Y - end - attribute \src "ls180.v:4345.36-4345.202" - cell $or $or$ls180.v:4345$628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4345$627_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4345$628_Y - end - attribute \src "ls180.v:4345.35-4345.245" - cell $or $or$ls180.v:4345$629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4345$628_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4345$629_Y - end - attribute \src "ls180.v:4346.40-4346.123" - cell $or $or$ls180.v:4346$630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_data_oe - connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4346$630_Y - end - attribute \src "ls180.v:4346.39-4346.167" - cell $or $or$ls180.v:4346$631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4346$630_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4346$631_Y - end - attribute \src "ls180.v:4346.38-4346.212" - cell $or $or$ls180.v:4346$632 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4346$631_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4346$632_Y - end - attribute \src "ls180.v:4346.37-4346.257" - cell $or $or$ls180.v:4346$633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4346$632_Y - connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4346$633_Y - end - attribute \src "ls180.v:4347.39-4347.120" - cell $or $or$ls180.v:4347$634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_init_pads_out_payload_data_o - connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4347$634_Y - end - attribute \src "ls180.v:4347.38-4347.163" - cell $or $or$ls180.v:4347$635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4347$634_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4347$635_Y - end - attribute \src "ls180.v:4347.37-4347.207" - cell $or $or$ls180.v:4347$636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4347$635_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4347$636_Y - end - attribute \src "ls180.v:4347.36-4347.251" - cell $or $or$ls180.v:4347$637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4347$636_Y - connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4347$637_Y - end - attribute \src "ls180.v:4368.35-4368.80" - cell $or $or$ls180.v:4368$638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_stop - connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4368$638_Y - end - attribute \src "ls180.v:4522.91-4522.144" - cell $or $or$ls180.v:4522$652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4522$652_Y - end - attribute \src "ls180.v:4539.53-4539.143" - cell $or $or$ls180.v:4539$655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4539$654_Y - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4539$655_Y - end - attribute \src "ls180.v:4542.47-4542.127" - cell $or $or$ls180.v:4542$658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4542$657_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4542$658_Y - end - attribute \src "ls180.v:4666.54-4666.146" - cell $or $or$ls180.v:4666$676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4666$675_Y - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4666$676_Y - end - attribute \src "ls180.v:4669.48-4669.130" - cell $or $or$ls180.v:4669$679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4669$678_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4669$679_Y - end - attribute \src "ls180.v:4800.55-4800.149" - cell $or $or$ls180.v:4800$691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4800$690_Y - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4800$691_Y - end - attribute \src "ls180.v:4803.49-4803.133" - cell $or $or$ls180.v:4803$694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4803$693_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4803$694_Y - end - attribute \src "ls180.v:5432.80-5432.151" - cell $or $or$ls180.v:5432$989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_writable - connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5432$989_Y - end - attribute \src "ls180.v:5443.49-5443.131" - cell $or $or$ls180.v:5443$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5443$994_Y - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5443$995_Y - end - attribute \src "ls180.v:5640.80-5640.151" - cell $or $or$ls180.v:5640$1020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_writable - connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5640$1020_Y - end - attribute \src "ls180.v:5755.33-5755.102" - cell $or $or$ls180.v:5755$1060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_err - connect \B \main_libresocsim_libresoc_xics_icp_err - connect \Y $or$ls180.v:5755$1060_Y - end - attribute \src "ls180.v:5755.32-5755.144" - cell $or $or$ls180.v:5755$1061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5755$1060_Y - connect \B \main_libresocsim_libresoc_xics_ics_err - connect \Y $or$ls180.v:5755$1061_Y - end - attribute \src "ls180.v:5755.31-5755.165" - cell $or $or$ls180.v:5755$1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5755$1061_Y - connect \B \main_wb_sdram_err - connect \Y $or$ls180.v:5755$1062_Y - end - attribute \src "ls180.v:5755.30-5755.201" - cell $or $or$ls180.v:5755$1063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5755$1062_Y - connect \B \builder_libresocsim_wishbone_err - connect \Y $or$ls180.v:5755$1063_Y - end - attribute \src "ls180.v:5761.28-5761.97" - cell $or $or$ls180.v:5761$1068 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \B \main_libresocsim_libresoc_xics_icp_ack - connect \Y $or$ls180.v:5761$1068_Y - end - attribute \src "ls180.v:5761.27-5761.139" - cell $or $or$ls180.v:5761$1069 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5761$1068_Y - connect \B \main_libresocsim_libresoc_xics_ics_ack - connect \Y $or$ls180.v:5761$1069_Y - end - attribute \src "ls180.v:5761.26-5761.160" - cell $or $or$ls180.v:5761$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5761$1069_Y - connect \B \main_wb_sdram_ack - connect \Y $or$ls180.v:5761$1070_Y - end - attribute \src "ls180.v:5761.25-5761.196" - cell $or $or$ls180.v:5761$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5761$1070_Y - connect \B \builder_libresocsim_wishbone_ack - connect \Y $or$ls180.v:5761$1071_Y - end - attribute \src "ls180.v:5762.30-5762.169" - cell $or $or$ls180.v:5762$1074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $and$ls180.v:5762$1072_Y - connect \B $and$ls180.v:5762$1073_Y - connect \Y $or$ls180.v:5762$1074_Y - end - attribute \src "ls180.v:5762.29-5762.246" - cell $or $or$ls180.v:5762$1076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5762$1074_Y - connect \B $and$ls180.v:5762$1075_Y - connect \Y $or$ls180.v:5762$1076_Y - end - attribute \src "ls180.v:5762.28-5762.302" - cell $or $or$ls180.v:5762$1078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5762$1076_Y - connect \B $and$ls180.v:5762$1077_Y - connect \Y $or$ls180.v:5762$1078_Y - end - attribute \src "ls180.v:5762.27-5762.373" - cell $or $or$ls180.v:5762$1080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $or$ls180.v:5762$1078_Y - connect \B $and$ls180.v:5762$1079_Y - connect \Y $or$ls180.v:5762$1080_Y - end - attribute \src "ls180.v:6516.55-6516.124" - cell $or $or$ls180.v:6516$2226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \builder_interface0_bank_bus_dat_r - connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2226_Y - end - attribute \src "ls180.v:6516.54-6516.161" - cell $or $or$ls180.v:6516$2227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2226_Y - connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2227_Y - end - attribute \src "ls180.v:6516.53-6516.198" - cell $or $or$ls180.v:6516$2228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2227_Y - connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2228_Y - end - attribute \src "ls180.v:6516.52-6516.235" - cell $or $or$ls180.v:6516$2229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2228_Y - connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2229_Y - end - attribute \src "ls180.v:6516.51-6516.272" - cell $or $or$ls180.v:6516$2230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2229_Y - connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2230_Y - end - attribute \src "ls180.v:6516.50-6516.309" - cell $or $or$ls180.v:6516$2231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2230_Y - connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2231_Y - end - attribute \src "ls180.v:6516.49-6516.346" - cell $or $or$ls180.v:6516$2232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2231_Y - connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2232_Y - end - attribute \src "ls180.v:6516.48-6516.383" - cell $or $or$ls180.v:6516$2233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2232_Y - connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2233_Y - end - attribute \src "ls180.v:6516.47-6516.420" - cell $or $or$ls180.v:6516$2234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2233_Y - connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2234_Y - end - attribute \src "ls180.v:6516.46-6516.458" - cell $or $or$ls180.v:6516$2235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2234_Y - connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2235_Y - end - attribute \src "ls180.v:6516.45-6516.496" - cell $or $or$ls180.v:6516$2236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2235_Y - connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2236_Y - end - attribute \src "ls180.v:6516.44-6516.534" - cell $or $or$ls180.v:6516$2237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2236_Y - connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2237_Y - end - attribute \src "ls180.v:6516.43-6516.572" - cell $or $or$ls180.v:6516$2238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2237_Y - connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2238_Y - end - attribute \src "ls180.v:6516.42-6516.610" - cell $or $or$ls180.v:6516$2239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6516$2238_Y - connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6516$2239_Y - end - attribute \src "ls180.v:6843.90-6843.179" - cell $or $or$ls180.v:6843$2264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:6843$2263_Y - connect \Y $or$ls180.v:6843$2264_Y - end - attribute \src "ls180.v:6843.89-6843.254" - cell $or $or$ls180.v:6843$2267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6843$2264_Y - connect \B $and$ls180.v:6843$2266_Y - connect \Y $or$ls180.v:6843$2267_Y - end - attribute \src "ls180.v:6843.88-6843.329" - cell $or $or$ls180.v:6843$2270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6843$2267_Y - connect \B $and$ls180.v:6843$2269_Y - connect \Y $or$ls180.v:6843$2270_Y - end - attribute \src "ls180.v:6867.90-6867.179" - cell $or $or$ls180.v:6867$2280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:6867$2279_Y - connect \Y $or$ls180.v:6867$2280_Y - end - attribute \src "ls180.v:6867.89-6867.254" - cell $or $or$ls180.v:6867$2283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6867$2280_Y - connect \B $and$ls180.v:6867$2282_Y - connect \Y $or$ls180.v:6867$2283_Y - end - attribute \src "ls180.v:6867.88-6867.329" - cell $or $or$ls180.v:6867$2286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6867$2283_Y - connect \B $and$ls180.v:6867$2285_Y - connect \Y $or$ls180.v:6867$2286_Y - end - attribute \src "ls180.v:6891.90-6891.179" - cell $or $or$ls180.v:6891$2296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:6891$2295_Y - connect \Y $or$ls180.v:6891$2296_Y - end - attribute \src "ls180.v:6891.89-6891.254" - cell $or $or$ls180.v:6891$2299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6891$2296_Y - connect \B $and$ls180.v:6891$2298_Y - connect \Y $or$ls180.v:6891$2299_Y - end - attribute \src "ls180.v:6891.88-6891.329" - cell $or $or$ls180.v:6891$2302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6891$2299_Y - connect \B $and$ls180.v:6891$2301_Y - connect \Y $or$ls180.v:6891$2302_Y - end - attribute \src "ls180.v:6915.90-6915.179" - cell $or $or$ls180.v:6915$2312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:6915$2311_Y - connect \Y $or$ls180.v:6915$2312_Y - end - attribute \src "ls180.v:6915.89-6915.254" - cell $or $or$ls180.v:6915$2315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6915$2312_Y - connect \B $and$ls180.v:6915$2314_Y - connect \Y $or$ls180.v:6915$2315_Y - end - attribute \src "ls180.v:6915.88-6915.329" - cell $or $or$ls180.v:6915$2318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6915$2315_Y - connect \B $and$ls180.v:6915$2317_Y - connect \Y $or$ls180.v:6915$2318_Y - end - attribute \src "ls180.v:7429.20-7429.71" - cell $or $or$ls180.v:7429$2375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [0] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7429$2375_Y - end - attribute \src "ls180.v:7430.20-7430.71" - cell $or $or$ls180.v:7430$2376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [1] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7430$2376_Y - end - attribute \src "ls180.v:7431.20-7431.71" - cell $or $or$ls180.v:7431$2377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [2] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7431$2377_Y - end - attribute \src "ls180.v:7432.20-7432.71" - cell $or $or$ls180.v:7432$2378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [3] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7432$2378_Y - end - attribute \src "ls180.v:7433.20-7433.71" - cell $or $or$ls180.v:7433$2379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [4] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7433$2379_Y - end - attribute \src "ls180.v:7434.20-7434.71" - cell $or $or$ls180.v:7434$2380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [5] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7434$2380_Y - end - attribute \src "ls180.v:7435.20-7435.71" - cell $or $or$ls180.v:7435$2381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [6] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7435$2381_Y - end - attribute \src "ls180.v:7436.20-7436.71" - cell $or $or$ls180.v:7436$2382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [7] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7436$2382_Y - end - attribute \src "ls180.v:7437.20-7437.71" - cell $or $or$ls180.v:7437$2383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [8] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7437$2383_Y - end - attribute \src "ls180.v:7438.20-7438.71" - cell $or $or$ls180.v:7438$2384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [9] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7438$2384_Y - end - attribute \src "ls180.v:7439.21-7439.73" - cell $or $or$ls180.v:7439$2385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [10] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7439$2385_Y - end - attribute \src "ls180.v:7440.21-7440.73" - cell $or $or$ls180.v:7440$2386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [11] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7440$2386_Y - end - attribute \src "ls180.v:7441.21-7441.73" - cell $or $or$ls180.v:7441$2387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [12] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7441$2387_Y - end - attribute \src "ls180.v:7442.21-7442.73" - cell $or $or$ls180.v:7442$2388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [13] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7442$2388_Y - end - attribute \src "ls180.v:7443.21-7443.73" - cell $or $or$ls180.v:7443$2389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [14] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7443$2389_Y - end - attribute \src "ls180.v:7444.21-7444.73" - cell $or $or$ls180.v:7444$2390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [15] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7444$2390_Y - end - attribute \src "ls180.v:7445.21-7445.73" - cell $or $or$ls180.v:7445$2391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [16] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7445$2391_Y - end - attribute \src "ls180.v:7446.21-7446.73" - cell $or $or$ls180.v:7446$2392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [17] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7446$2392_Y - end - attribute \src "ls180.v:7447.21-7447.73" - cell $or $or$ls180.v:7447$2393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [18] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7447$2393_Y - end - attribute \src "ls180.v:7448.21-7448.73" - cell $or $or$ls180.v:7448$2394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [19] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7448$2394_Y - end - attribute \src "ls180.v:7449.21-7449.73" - cell $or $or$ls180.v:7449$2395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [20] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7449$2395_Y - end - attribute \src "ls180.v:7450.21-7450.73" - cell $or $or$ls180.v:7450$2396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [21] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7450$2396_Y - end - attribute \src "ls180.v:7451.21-7451.73" - cell $or $or$ls180.v:7451$2397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [22] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7451$2397_Y - end - attribute \src "ls180.v:7452.21-7452.73" - cell $or $or$ls180.v:7452$2398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [23] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7452$2398_Y - end - attribute \src "ls180.v:7453.21-7453.73" - cell $or $or$ls180.v:7453$2399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [24] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7453$2399_Y - end - attribute \src "ls180.v:7454.21-7454.73" - cell $or $or$ls180.v:7454$2400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [25] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7454$2400_Y - end - attribute \src "ls180.v:7455.21-7455.73" - cell $or $or$ls180.v:7455$2401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [26] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7455$2401_Y - end - attribute \src "ls180.v:7456.21-7456.73" - cell $or $or$ls180.v:7456$2402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [27] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7456$2402_Y - end - attribute \src "ls180.v:7457.21-7457.73" - cell $or $or$ls180.v:7457$2403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [28] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7457$2403_Y - end - attribute \src "ls180.v:7458.21-7458.73" - cell $or $or$ls180.v:7458$2404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [29] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7458$2404_Y - end - attribute \src "ls180.v:7459.21-7459.73" - cell $or $or$ls180.v:7459$2405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [30] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7459$2405_Y - end - attribute \src "ls180.v:7460.21-7460.73" - cell $or $or$ls180.v:7460$2406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [31] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7460$2406_Y - end - attribute \src "ls180.v:7461.21-7461.73" - cell $or $or$ls180.v:7461$2407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [32] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7461$2407_Y - end - attribute \src "ls180.v:7462.21-7462.73" - cell $or $or$ls180.v:7462$2408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [33] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7462$2408_Y - end - attribute \src "ls180.v:7463.21-7463.73" - cell $or $or$ls180.v:7463$2409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [34] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7463$2409_Y - end - attribute \src "ls180.v:7464.21-7464.73" - cell $or $or$ls180.v:7464$2410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [35] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7464$2410_Y - end - attribute \src "ls180.v:7465.7-7465.93" - cell $or $or$ls180.v:7465$2411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface0_converted_interface_ack - connect \B \main_libresocsim_converter0_skip - connect \Y $or$ls180.v:7465$2411_Y - end - attribute \src "ls180.v:7476.7-7476.93" - cell $or $or$ls180.v:7476$2412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface1_converted_interface_ack - connect \B \main_libresocsim_converter1_skip - connect \Y $or$ls180.v:7476$2412_Y - end - attribute \src "ls180.v:7487.7-7487.93" - cell $or $or$ls180.v:7487$2413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_interface2_converted_interface_ack - connect \B \main_libresocsim_converter2_skip - connect \Y $or$ls180.v:7487$2413_Y - end - attribute \src "ls180.v:7616.7-7616.107" - cell $or $or$ls180.v:7616$2449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7616$2448_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7616$2449_Y - end - attribute \src "ls180.v:7662.7-7662.107" - cell $or $or$ls180.v:7662$2465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7662$2464_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7662$2465_Y - end - attribute \src "ls180.v:7708.7-7708.107" - cell $or $or$ls180.v:7708$2481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7708$2480_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7708$2481_Y - end - attribute \src "ls180.v:7754.7-7754.107" - cell $or $or$ls180.v:7754$2497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7754$2496_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7754$2497_Y - end - attribute \src "ls180.v:7942.40-7942.125" - cell $or $or$ls180.v:7942$2518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:7942$2517_Y - connect \Y $or$ls180.v:7942$2518_Y - end - attribute \src "ls180.v:7942.39-7942.207" - cell $or $or$ls180.v:7942$2521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7942$2518_Y - connect \B $and$ls180.v:7942$2520_Y - connect \Y $or$ls180.v:7942$2521_Y - end - attribute \src "ls180.v:7942.38-7942.289" - cell $or $or$ls180.v:7942$2524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7942$2521_Y - connect \B $and$ls180.v:7942$2523_Y - connect \Y $or$ls180.v:7942$2524_Y - end - attribute \src "ls180.v:7942.37-7942.371" - cell $or $or$ls180.v:7942$2527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7942$2524_Y - connect \B $and$ls180.v:7942$2526_Y - connect \Y $or$ls180.v:7942$2527_Y - end - attribute \src "ls180.v:7943.41-7943.126" - cell $or $or$ls180.v:7943$2530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:7943$2529_Y - connect \Y $or$ls180.v:7943$2530_Y - end - attribute \src "ls180.v:7943.40-7943.208" - cell $or $or$ls180.v:7943$2533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7943$2530_Y - connect \B $and$ls180.v:7943$2532_Y - connect \Y $or$ls180.v:7943$2533_Y - end - attribute \src "ls180.v:7943.39-7943.290" - cell $or $or$ls180.v:7943$2536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7943$2533_Y - connect \B $and$ls180.v:7943$2535_Y - connect \Y $or$ls180.v:7943$2536_Y - end - attribute \src "ls180.v:7943.38-7943.372" - cell $or $or$ls180.v:7943$2539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:7943$2536_Y - connect \B $and$ls180.v:7943$2538_Y - connect \Y $or$ls180.v:7943$2539_Y - end - attribute \src "ls180.v:7947.7-7947.49" - cell $or $or$ls180.v:7947$2540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:7947$2540_Y - end - attribute \src "ls180.v:8110.21-8110.74" - cell $or $or$ls180.v:8110$2588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8110$2586_Y - connect \B $not$ls180.v:8110$2587_Y - connect \Y $or$ls180.v:8110$2588_Y - end - attribute \src "ls180.v:8145.21-8145.71" - cell $or $or$ls180.v:8145$2593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8145$2591_Y - connect \B $not$ls180.v:8145$2592_Y - connect \Y $or$ls180.v:8145$2593_Y - end - attribute \src "ls180.v:8213.32-8213.85" - cell $or $or$ls180.v:8213$2605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8213$2605_Y - end - attribute \src "ls180.v:8219.8-8219.97" - cell $or $or$ls180.v:8219$2607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8219$2606_Y - connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8219$2607_Y - end - attribute \src "ls180.v:8236.52-8236.139" - cell $or $or$ls180.v:8236$2612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_first - connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8236$2612_Y - end - attribute \src "ls180.v:8237.51-8237.136" - cell $or $or$ls180.v:8237$2613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_last - connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8237$2613_Y - end - attribute \src "ls180.v:8271.7-8271.87" - cell $or $or$ls180.v:8271$2616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8271$2615_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8271$2616_Y - end - attribute \src "ls180.v:8294.33-8294.88" - cell $or $or$ls180.v:8294$2617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_start - connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8294$2617_Y - end - attribute \src "ls180.v:8300.8-8300.99" - cell $or $or$ls180.v:8300$2619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8300$2618_Y - connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8300$2619_Y - end - attribute \src "ls180.v:8317.53-8317.142" - cell $or $or$ls180.v:8317$2624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_first - connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8317$2624_Y - end - attribute \src "ls180.v:8318.52-8318.139" - cell $or $or$ls180.v:8318$2625 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_last - connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8318$2625_Y - end - attribute \src "ls180.v:8352.7-8352.89" - cell $or $or$ls180.v:8352$2628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8352$2627_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8352$2628_Y - end - attribute \src "ls180.v:8373.34-8373.91" - cell $or $or$ls180.v:8373$2629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_start - connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8373$2629_Y - end - attribute \src "ls180.v:8379.8-8379.101" - cell $or $or$ls180.v:8379$2631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8379$2630_Y - connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8379$2631_Y - end - attribute \src "ls180.v:8396.54-8396.145" - cell $or $or$ls180.v:8396$2636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_first - connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8396$2636_Y - end - attribute \src "ls180.v:8397.53-8397.142" - cell $or $or$ls180.v:8397$2637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_last - connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8397$2637_Y - end - attribute \src "ls180.v:8413.7-8413.91" - cell $or $or$ls180.v:8413$2640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8413$2639_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8413$2640_Y - end - attribute \src "ls180.v:8602.8-8602.89" - cell $or $or$ls180.v:8602$2664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8602$2663_Y - connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8602$2664_Y - end - attribute \src "ls180.v:8619.48-8619.127" - cell $or $or$ls180.v:8619$2669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_first - connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8619$2669_Y - end - attribute \src "ls180.v:8620.47-8620.124" - cell $or $or$ls180.v:8620$2670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_last - connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8620$2670_Y - end - attribute \src "ls180.v:3179.46-3179.94" - cell $sshl $sshl$ls180.v:3179$83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine0_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3179$83_Y - end - attribute \src "ls180.v:3336.46-3336.94" - cell $sshl $sshl$ls180.v:3336$113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine1_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3336$113_Y - end - attribute \src "ls180.v:3493.46-3493.94" - cell $sshl $sshl$ls180.v:3493$143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine2_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3493$143_Y - end - attribute \src "ls180.v:3650.46-3650.94" - cell $sshl $sshl$ls180.v:3650$173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine3_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3650$173_Y - end - attribute \src "ls180.v:3210.63-3210.122" - cell $sub $sub$ls180.v:3210$96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3210$96_Y - end - attribute \src "ls180.v:3367.63-3367.122" - cell $sub $sub$ls180.v:3367$126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3367$126_Y - end - attribute \src "ls180.v:3524.63-3524.122" - cell $sub $sub$ls180.v:3524$156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3524$156_Y - end - attribute \src "ls180.v:3681.63-3681.122" - cell $sub $sub$ls180.v:3681$186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3681$186_Y - end - attribute \src "ls180.v:4087.38-4087.75" - cell $sub $sub$ls180.v:4087$540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 30 - parameter \B_SIGNED 0 - parameter \B_WIDTH 31 - parameter \Y_WIDTH 31 - connect \A \main_litedram_wb_adr - connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4087$540_Y - end - attribute \src "ls180.v:4173.36-4173.68" - cell $sub $sub$ls180.v:4173$585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4173$585_Y - end - attribute \src "ls180.v:4203.36-4203.68" - cell $sub $sub$ls180.v:4203$596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4203$596_Y - end - attribute \src "ls180.v:4228.70-4228.110" - cell $sub $sub$ls180.v:4228$602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4228$602_Y - end - attribute \src "ls180.v:4229.70-4229.104" - cell $sub $sub$ls180.v:4229$604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider - connect \B 1'1 - connect \Y $sub$ls180.v:4229$604_Y - end - attribute \src "ls180.v:4256.37-4256.66" - cell $sub $sub$ls180.v:4256$608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spimaster1_length - connect \B 1'1 - connect \Y $sub$ls180.v:4256$608_Y - end - attribute \src "ls180.v:4286.67-4286.107" - cell $sub $sub$ls180.v:4286$610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4286$610_Y - end - attribute \src "ls180.v:4287.67-4287.101" - cell $sub $sub$ls180.v:4287$612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:4287$612_Y - end - attribute \src "ls180.v:4315.35-4315.64" - cell $sub $sub$ls180.v:4315$616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spisdcard_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:4315$616_Y - end - attribute \src "ls180.v:4569.60-4569.90" - cell $sub $sub$ls180.v:4569$660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4569$660_Y - end - attribute \src "ls180.v:4580.62-4580.104" - cell $sub $sub$ls180.v:4580$662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_sink_payload_length - connect \B 1'1 - connect \Y $sub$ls180.v:4580$662_Y - end - attribute \src "ls180.v:4597.60-4597.90" - cell $sub $sub$ls180.v:4597$666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4597$666_Y - end - attribute \src "ls180.v:4826.62-4826.93" - cell $sub $sub$ls180.v:4826$696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4826$696_Y - end - attribute \src "ls180.v:4831.62-4831.93" - cell $sub $sub$ls180.v:4831$697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4831$697_Y - end - attribute \src "ls180.v:4842.64-4842.122" - cell $sub $sub$ls180.v:4842$700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4842$699_Y - connect \B 1'1 - connect \Y $sub$ls180.v:4842$700_Y - end - attribute \src "ls180.v:4863.62-4863.93" - cell $sub $sub$ls180.v:4863$703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4863$703_Y - end - attribute \src "ls180.v:5325.37-5325.75" - cell $sub $sub$ls180.v:5325$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5325$976_Y - end - attribute \src "ls180.v:5340.62-5340.100" - cell $sub $sub$ls180.v:5340$979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5340$979_Y - end - attribute \src "ls180.v:5351.39-5351.77" - cell $sub $sub$ls180.v:5351$984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5351$984_Y - end - attribute \src "ls180.v:5426.40-5426.76" - cell $sub $sub$ls180.v:5426$988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5426$988_Y - end - attribute \src "ls180.v:5475.56-5475.104" - cell $sub $sub$ls180.v:5475$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_length - connect \B 1'1 - connect \Y $sub$ls180.v:5475$1002_Y - end - attribute \src "ls180.v:5565.71-5565.105" - cell $sub $sub$ls180.v:5565$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_length - connect \B 1'1 - connect \Y $sub$ls180.v:5565$1008_Y - end - attribute \src "ls180.v:5634.40-5634.76" - cell $sub $sub$ls180.v:5634$1019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5634$1019_Y - end - attribute \src "ls180.v:7511.31-7511.60" - cell $sub $sub$ls180.v:7511$2420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_value - connect \B 1'1 - connect \Y $sub$ls180.v:7511$2420_Y - end - attribute \src "ls180.v:7532.31-7532.61" - cell $sub $sub$ls180.v:7532$2425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdram_timer_count1 - connect \B 1'1 - connect \Y $sub$ls180.v:7532$2425_Y - end - attribute \src "ls180.v:7538.34-7538.67" - cell $sub $sub$ls180.v:7538$2426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7538$2426_Y - end - attribute \src "ls180.v:7549.36-7549.69" - cell $sub $sub$ls180.v:7549$2429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7549$2429_Y - end - attribute \src "ls180.v:7613.59-7613.116" - cell $sub $sub$ls180.v:7613$2447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7613$2447_Y - end - attribute \src "ls180.v:7632.46-7632.90" - cell $sub $sub$ls180.v:7632$2451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7632$2451_Y - end - attribute \src "ls180.v:7659.59-7659.116" - cell $sub $sub$ls180.v:7659$2463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7659$2463_Y - end - attribute \src "ls180.v:7678.46-7678.90" - cell $sub $sub$ls180.v:7678$2467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7678$2467_Y - end - attribute \src "ls180.v:7705.59-7705.116" - cell $sub $sub$ls180.v:7705$2479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7705$2479_Y - end - attribute \src "ls180.v:7724.46-7724.90" - cell $sub $sub$ls180.v:7724$2483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7724$2483_Y - end - attribute \src "ls180.v:7751.59-7751.116" - cell $sub $sub$ls180.v:7751$2495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7751$2495_Y - end - attribute \src "ls180.v:7770.46-7770.90" - cell $sub $sub$ls180.v:7770$2499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7770$2499_Y - end - attribute \src "ls180.v:7781.25-7781.48" - cell $sub $sub$ls180.v:7781$2503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdram_time0 - connect \B 1'1 - connect \Y $sub$ls180.v:7781$2503_Y - end - attribute \src "ls180.v:7788.25-7788.48" - cell $sub $sub$ls180.v:7788$2506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_time1 - connect \B 1'1 - connect \Y $sub$ls180.v:7788$2506_Y - end - attribute \src "ls180.v:7920.33-7920.64" - cell $sub $sub$ls180.v:7920$2511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7920$2511_Y - end - attribute \src "ls180.v:7935.33-7935.64" - cell $sub $sub$ls180.v:7935$2514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7935$2514_Y - end - attribute \src "ls180.v:8062.33-8062.64" - cell $sub $sub$ls180.v:8062$2573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8062$2573_Y - end - attribute \src "ls180.v:8084.33-8084.64" - cell $sub $sub$ls180.v:8084$2584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8084$2584_Y - end - attribute \src "ls180.v:8119.34-8119.66" - cell $sub $sub$ls180.v:8119$2589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster34_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8119$2589_Y - end - attribute \src "ls180.v:8154.32-8154.62" - cell $sub $sub$ls180.v:8154$2594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8154$2594_Y - end - attribute \src "ls180.v:8178.30-8178.53" - cell $sub $sub$ls180.v:8178$2597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_period - connect \B 1'1 - connect \Y $sub$ls180.v:8178$2597_Y - end - attribute \src "ls180.v:8192.30-8192.53" - cell $sub $sub$ls180.v:8192$2601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_period - connect \B 1'1 - connect \Y $sub$ls180.v:8192$2601_Y - end - attribute \src "ls180.v:8595.36-8595.70" - cell $sub $sub$ls180.v:8595$2662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8595$2662_Y - end - attribute \src "ls180.v:8681.36-8681.70" - cell $sub $sub$ls180.v:8681$2684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8681$2684_Y - end - attribute \src "ls180.v:8794.22-8794.42" - cell $sub $sub$ls180.v:8794$2691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 20 - connect \A \builder_count - connect \B 1'1 - connect \Y $sub$ls180.v:8794$2691_Y - end - attribute \src "ls180.v:4923.353-4923.425" - cell $xor $xor$ls180.v:4923$710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4923$710_Y - end - attribute \src "ls180.v:4923.200-4923.272" - cell $xor $xor$ls180.v:4923$711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4923$711_Y - end - attribute \src "ls180.v:4923.160-4923.273" - cell $xor $xor$ls180.v:4923$712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4923$711_Y - connect \Y $xor$ls180.v:4923$712_Y - end - attribute \src "ls180.v:4924.353-4924.425" - cell $xor $xor$ls180.v:4924$713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4924$713_Y - end - attribute \src "ls180.v:4924.200-4924.272" - cell $xor $xor$ls180.v:4924$714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4924$714_Y - end - attribute \src "ls180.v:4924.160-4924.273" - cell $xor $xor$ls180.v:4924$715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4924$714_Y - connect \Y $xor$ls180.v:4924$715_Y - end - attribute \src "ls180.v:4925.353-4925.425" - cell $xor $xor$ls180.v:4925$716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4925$716_Y - end - attribute \src "ls180.v:4925.200-4925.272" - cell $xor $xor$ls180.v:4925$717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4925$717_Y - end - attribute \src "ls180.v:4925.160-4925.273" - cell $xor $xor$ls180.v:4925$718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4925$717_Y - connect \Y $xor$ls180.v:4925$718_Y - end - attribute \src "ls180.v:4926.353-4926.425" - cell $xor $xor$ls180.v:4926$719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4926$719_Y - end - attribute \src "ls180.v:4926.200-4926.272" - cell $xor $xor$ls180.v:4926$720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4926$720_Y - end - attribute \src "ls180.v:4926.160-4926.273" - cell $xor $xor$ls180.v:4926$721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:4926$720_Y - connect \Y $xor$ls180.v:4926$721_Y - end - attribute \src "ls180.v:4927.353-4927.425" - cell $xor $xor$ls180.v:4927$722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4927$722_Y - end - attribute \src "ls180.v:4927.200-4927.272" - cell $xor $xor$ls180.v:4927$723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4927$723_Y - end - attribute \src "ls180.v:4927.160-4927.273" - cell $xor $xor$ls180.v:4927$724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:4927$723_Y - connect \Y $xor$ls180.v:4927$724_Y - end - attribute \src "ls180.v:4928.353-4928.425" - cell $xor $xor$ls180.v:4928$725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4928$725_Y - end - attribute \src "ls180.v:4928.200-4928.272" - cell $xor $xor$ls180.v:4928$726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4928$726_Y - end - attribute \src "ls180.v:4928.160-4928.273" - cell $xor $xor$ls180.v:4928$727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:4928$726_Y - connect \Y $xor$ls180.v:4928$727_Y - end - attribute \src "ls180.v:4929.353-4929.425" - cell $xor $xor$ls180.v:4929$728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4929$728_Y - end - attribute \src "ls180.v:4929.200-4929.272" - cell $xor $xor$ls180.v:4929$729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4929$729_Y - end - attribute \src "ls180.v:4929.160-4929.273" - cell $xor $xor$ls180.v:4929$730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:4929$729_Y - connect \Y $xor$ls180.v:4929$730_Y - end - attribute \src "ls180.v:4930.353-4930.425" - cell $xor $xor$ls180.v:4930$731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4930$731_Y - end - attribute \src "ls180.v:4930.200-4930.272" - cell $xor $xor$ls180.v:4930$732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4930$732_Y - end - attribute \src "ls180.v:4930.160-4930.273" - cell $xor $xor$ls180.v:4930$733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:4930$732_Y - connect \Y $xor$ls180.v:4930$733_Y - end - attribute \src "ls180.v:4931.353-4931.425" - cell $xor $xor$ls180.v:4931$734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4931$734_Y - end - attribute \src "ls180.v:4931.200-4931.272" - cell $xor $xor$ls180.v:4931$735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4931$735_Y - end - attribute \src "ls180.v:4931.160-4931.273" - cell $xor $xor$ls180.v:4931$736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:4931$735_Y - connect \Y $xor$ls180.v:4931$736_Y - end - attribute \src "ls180.v:4932.354-4932.426" - cell $xor $xor$ls180.v:4932$737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4932$737_Y - end - attribute \src "ls180.v:4932.201-4932.273" - cell $xor $xor$ls180.v:4932$738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4932$738_Y - end - attribute \src "ls180.v:4932.161-4932.274" - cell $xor $xor$ls180.v:4932$739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:4932$738_Y - connect \Y $xor$ls180.v:4932$739_Y - end - attribute \src "ls180.v:4933.361-4933.434" - cell $xor $xor$ls180.v:4933$740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4933$740_Y - end - attribute \src "ls180.v:4933.205-4933.278" - cell $xor $xor$ls180.v:4933$741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4933$741_Y - end - attribute \src "ls180.v:4933.164-4933.279" - cell $xor $xor$ls180.v:4933$742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:4933$741_Y - connect \Y $xor$ls180.v:4933$742_Y - end - attribute \src "ls180.v:4934.361-4934.434" - cell $xor $xor$ls180.v:4934$743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4934$743_Y - end - attribute \src "ls180.v:4934.205-4934.278" - cell $xor $xor$ls180.v:4934$744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4934$744_Y - end - attribute \src "ls180.v:4934.164-4934.279" - cell $xor $xor$ls180.v:4934$745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:4934$744_Y - connect \Y $xor$ls180.v:4934$745_Y - end - attribute \src "ls180.v:4935.361-4935.434" - cell $xor $xor$ls180.v:4935$746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4935$746_Y - end - attribute \src "ls180.v:4935.205-4935.278" - cell $xor $xor$ls180.v:4935$747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4935$747_Y - end - attribute \src "ls180.v:4935.164-4935.279" - cell $xor $xor$ls180.v:4935$748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:4935$747_Y - connect \Y $xor$ls180.v:4935$748_Y - end - attribute \src "ls180.v:4936.361-4936.434" - cell $xor $xor$ls180.v:4936$749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4936$749_Y - end - attribute \src "ls180.v:4936.205-4936.278" - cell $xor $xor$ls180.v:4936$750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4936$750_Y - end - attribute \src "ls180.v:4936.164-4936.279" - cell $xor $xor$ls180.v:4936$751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:4936$750_Y - connect \Y $xor$ls180.v:4936$751_Y - end - attribute \src "ls180.v:4937.361-4937.434" - cell $xor $xor$ls180.v:4937$752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4937$752_Y - end - attribute \src "ls180.v:4937.205-4937.278" - cell $xor $xor$ls180.v:4937$753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4937$753_Y - end - attribute \src "ls180.v:4937.164-4937.279" - cell $xor $xor$ls180.v:4937$754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:4937$753_Y - connect \Y $xor$ls180.v:4937$754_Y - end - attribute \src "ls180.v:4938.361-4938.434" - cell $xor $xor$ls180.v:4938$755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4938$755_Y - end - attribute \src "ls180.v:4938.205-4938.278" - cell $xor $xor$ls180.v:4938$756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4938$756_Y - end - attribute \src "ls180.v:4938.164-4938.279" - cell $xor $xor$ls180.v:4938$757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:4938$756_Y - connect \Y $xor$ls180.v:4938$757_Y - end - attribute \src "ls180.v:4939.361-4939.434" - cell $xor $xor$ls180.v:4939$758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4939$758_Y - end - attribute \src "ls180.v:4939.205-4939.278" - cell $xor $xor$ls180.v:4939$759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4939$759_Y - end - attribute \src "ls180.v:4939.164-4939.279" - cell $xor $xor$ls180.v:4939$760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:4939$759_Y - connect \Y $xor$ls180.v:4939$760_Y - end - attribute \src "ls180.v:4940.361-4940.434" - cell $xor $xor$ls180.v:4940$761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4940$761_Y - end - attribute \src "ls180.v:4940.205-4940.278" - cell $xor $xor$ls180.v:4940$762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4940$762_Y - end - attribute \src "ls180.v:4940.164-4940.279" - cell $xor $xor$ls180.v:4940$763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:4940$762_Y - connect \Y $xor$ls180.v:4940$763_Y - end - attribute \src "ls180.v:4941.361-4941.434" - cell $xor $xor$ls180.v:4941$764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4941$764_Y - end - attribute \src "ls180.v:4941.205-4941.278" - cell $xor $xor$ls180.v:4941$765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:4941$765_Y - end - attribute \src "ls180.v:4941.164-4941.279" - cell $xor $xor$ls180.v:4941$766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:4941$765_Y - connect \Y $xor$ls180.v:4941$766_Y - end - attribute \src "ls180.v:4942.361-4942.434" - cell $xor $xor$ls180.v:4942$767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4942$767_Y - end - attribute \src "ls180.v:4942.205-4942.278" - cell $xor $xor$ls180.v:4942$768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:4942$768_Y - end - attribute \src "ls180.v:4942.164-4942.279" - cell $xor $xor$ls180.v:4942$769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:4942$768_Y - connect \Y $xor$ls180.v:4942$769_Y - end - attribute \src "ls180.v:4943.361-4943.434" - cell $xor $xor$ls180.v:4943$770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4943$770_Y - end - attribute \src "ls180.v:4943.205-4943.278" - cell $xor $xor$ls180.v:4943$771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:4943$771_Y - end - attribute \src "ls180.v:4943.164-4943.279" - cell $xor $xor$ls180.v:4943$772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:4943$771_Y - connect \Y $xor$ls180.v:4943$772_Y - end - attribute \src "ls180.v:4944.361-4944.434" - cell $xor $xor$ls180.v:4944$773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4944$773_Y - end - attribute \src "ls180.v:4944.205-4944.278" - cell $xor $xor$ls180.v:4944$774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:4944$774_Y - end - attribute \src "ls180.v:4944.164-4944.279" - cell $xor $xor$ls180.v:4944$775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:4944$774_Y - connect \Y $xor$ls180.v:4944$775_Y - end - attribute \src "ls180.v:4945.361-4945.434" - cell $xor $xor$ls180.v:4945$776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4945$776_Y - end - attribute \src "ls180.v:4945.205-4945.278" - cell $xor $xor$ls180.v:4945$777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:4945$777_Y - end - attribute \src "ls180.v:4945.164-4945.279" - cell $xor $xor$ls180.v:4945$778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:4945$777_Y - connect \Y $xor$ls180.v:4945$778_Y - end - attribute \src "ls180.v:4946.361-4946.434" - cell $xor $xor$ls180.v:4946$779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4946$779_Y - end - attribute \src "ls180.v:4946.205-4946.278" - cell $xor $xor$ls180.v:4946$780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:4946$780_Y - end - attribute \src "ls180.v:4946.164-4946.279" - cell $xor $xor$ls180.v:4946$781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:4946$780_Y - connect \Y $xor$ls180.v:4946$781_Y - end - attribute \src "ls180.v:4947.361-4947.434" - cell $xor $xor$ls180.v:4947$782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4947$782_Y - end - attribute \src "ls180.v:4947.205-4947.278" - cell $xor $xor$ls180.v:4947$783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:4947$783_Y - end - attribute \src "ls180.v:4947.164-4947.279" - cell $xor $xor$ls180.v:4947$784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:4947$783_Y - connect \Y $xor$ls180.v:4947$784_Y - end - attribute \src "ls180.v:4948.361-4948.434" - cell $xor $xor$ls180.v:4948$785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4948$785_Y - end - attribute \src "ls180.v:4948.205-4948.278" - cell $xor $xor$ls180.v:4948$786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:4948$786_Y - end - attribute \src "ls180.v:4948.164-4948.279" - cell $xor $xor$ls180.v:4948$787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:4948$786_Y - connect \Y $xor$ls180.v:4948$787_Y - end - attribute \src "ls180.v:4949.361-4949.434" - cell $xor $xor$ls180.v:4949$788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4949$788_Y - end - attribute \src "ls180.v:4949.205-4949.278" - cell $xor $xor$ls180.v:4949$789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:4949$789_Y - end - attribute \src "ls180.v:4949.164-4949.279" - cell $xor $xor$ls180.v:4949$790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:4949$789_Y - connect \Y $xor$ls180.v:4949$790_Y - end - attribute \src "ls180.v:4950.361-4950.434" - cell $xor $xor$ls180.v:4950$791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4950$791_Y - end - attribute \src "ls180.v:4950.205-4950.278" - cell $xor $xor$ls180.v:4950$792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:4950$792_Y - end - attribute \src "ls180.v:4950.164-4950.279" - cell $xor $xor$ls180.v:4950$793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:4950$792_Y - connect \Y $xor$ls180.v:4950$793_Y - end - attribute \src "ls180.v:4951.361-4951.434" - cell $xor $xor$ls180.v:4951$794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4951$794_Y - end - attribute \src "ls180.v:4951.205-4951.278" - cell $xor $xor$ls180.v:4951$795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:4951$795_Y - end - attribute \src "ls180.v:4951.164-4951.279" - cell $xor $xor$ls180.v:4951$796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:4951$795_Y - connect \Y $xor$ls180.v:4951$796_Y - end - attribute \src "ls180.v:4952.361-4952.434" - cell $xor $xor$ls180.v:4952$797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4952$797_Y - end - attribute \src "ls180.v:4952.205-4952.278" - cell $xor $xor$ls180.v:4952$798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:4952$798_Y - end - attribute \src "ls180.v:4952.164-4952.279" - cell $xor $xor$ls180.v:4952$799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:4952$798_Y - connect \Y $xor$ls180.v:4952$799_Y - end - attribute \src "ls180.v:4953.360-4953.432" - cell $xor $xor$ls180.v:4953$800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4953$800_Y - end - attribute \src "ls180.v:4953.205-4953.277" - cell $xor $xor$ls180.v:4953$801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:4953$801_Y - end - attribute \src "ls180.v:4953.164-4953.278" - cell $xor $xor$ls180.v:4953$802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:4953$801_Y - connect \Y $xor$ls180.v:4953$802_Y - end - attribute \src "ls180.v:4954.360-4954.432" - cell $xor $xor$ls180.v:4954$803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4954$803_Y - end - attribute \src "ls180.v:4954.205-4954.277" - cell $xor $xor$ls180.v:4954$804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:4954$804_Y - end - attribute \src "ls180.v:4954.164-4954.278" - cell $xor $xor$ls180.v:4954$805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:4954$804_Y - connect \Y $xor$ls180.v:4954$805_Y - end - attribute \src "ls180.v:4955.360-4955.432" - cell $xor $xor$ls180.v:4955$806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4955$806_Y - end - attribute \src "ls180.v:4955.205-4955.277" - cell $xor $xor$ls180.v:4955$807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:4955$807_Y - end - attribute \src "ls180.v:4955.164-4955.278" - cell $xor $xor$ls180.v:4955$808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:4955$807_Y - connect \Y $xor$ls180.v:4955$808_Y - end - attribute \src "ls180.v:4956.360-4956.432" - cell $xor $xor$ls180.v:4956$809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4956$809_Y - end - attribute \src "ls180.v:4956.205-4956.277" - cell $xor $xor$ls180.v:4956$810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:4956$810_Y - end - attribute \src "ls180.v:4956.164-4956.278" - cell $xor $xor$ls180.v:4956$811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:4956$810_Y - connect \Y $xor$ls180.v:4956$811_Y - end - attribute \src "ls180.v:4957.360-4957.432" - cell $xor $xor$ls180.v:4957$812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4957$812_Y - end - attribute \src "ls180.v:4957.205-4957.277" - cell $xor $xor$ls180.v:4957$813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:4957$813_Y - end - attribute \src "ls180.v:4957.164-4957.278" - cell $xor $xor$ls180.v:4957$814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:4957$813_Y - connect \Y $xor$ls180.v:4957$814_Y - end - attribute \src "ls180.v:4958.360-4958.432" - cell $xor $xor$ls180.v:4958$815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4958$815_Y - end - attribute \src "ls180.v:4958.205-4958.277" - cell $xor $xor$ls180.v:4958$816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:4958$816_Y - end - attribute \src "ls180.v:4958.164-4958.278" - cell $xor $xor$ls180.v:4958$817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:4958$816_Y - connect \Y $xor$ls180.v:4958$817_Y - end - attribute \src "ls180.v:4959.360-4959.432" - cell $xor $xor$ls180.v:4959$818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4959$818_Y - end - attribute \src "ls180.v:4959.205-4959.277" - cell $xor $xor$ls180.v:4959$819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:4959$819_Y - end - attribute \src "ls180.v:4959.164-4959.278" - cell $xor $xor$ls180.v:4959$820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:4959$819_Y - connect \Y $xor$ls180.v:4959$820_Y - end - attribute \src "ls180.v:4960.360-4960.432" - cell $xor $xor$ls180.v:4960$821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4960$821_Y - end - attribute \src "ls180.v:4960.205-4960.277" - cell $xor $xor$ls180.v:4960$822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:4960$822_Y - end - attribute \src "ls180.v:4960.164-4960.278" - cell $xor $xor$ls180.v:4960$823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:4960$822_Y - connect \Y $xor$ls180.v:4960$823_Y - end - attribute \src "ls180.v:4961.360-4961.432" - cell $xor $xor$ls180.v:4961$824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4961$824_Y - end - attribute \src "ls180.v:4961.205-4961.277" - cell $xor $xor$ls180.v:4961$825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:4961$825_Y - end - attribute \src "ls180.v:4961.164-4961.278" - cell $xor $xor$ls180.v:4961$826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:4961$825_Y - connect \Y $xor$ls180.v:4961$826_Y - end - attribute \src "ls180.v:4962.360-4962.432" - cell $xor $xor$ls180.v:4962$827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4962$827_Y - end - attribute \src "ls180.v:4962.205-4962.277" - cell $xor $xor$ls180.v:4962$828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:4962$828_Y - end - attribute \src "ls180.v:4962.164-4962.278" - cell $xor $xor$ls180.v:4962$829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:4962$828_Y - connect \Y $xor$ls180.v:4962$829_Y - end - attribute \src "ls180.v:4983.899-4983.983" - cell $xor $xor$ls180.v:4983$843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4983$843_Y - end - attribute \src "ls180.v:4983.634-4983.718" - cell $xor $xor$ls180.v:4983$844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4983$844_Y - end - attribute \src "ls180.v:4983.588-4983.719" - cell $xor $xor$ls180.v:4983$845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:4983$844_Y - connect \Y $xor$ls180.v:4983$845_Y - end - attribute \src "ls180.v:4983.234-4983.318" - cell $xor $xor$ls180.v:4983$846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:4983$846_Y - end - attribute \src "ls180.v:4983.187-4983.319" - cell $xor $xor$ls180.v:4983$847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:4983$846_Y - connect \Y $xor$ls180.v:4983$847_Y - end - attribute \src "ls180.v:4984.899-4984.983" - cell $xor $xor$ls180.v:4984$848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4984$848_Y - end - attribute \src "ls180.v:4984.634-4984.718" - cell $xor $xor$ls180.v:4984$849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4984$849_Y - end - attribute \src "ls180.v:4984.588-4984.719" - cell $xor $xor$ls180.v:4984$850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:4984$849_Y - connect \Y $xor$ls180.v:4984$850_Y - end - attribute \src "ls180.v:4984.234-4984.318" - cell $xor $xor$ls180.v:4984$851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:4984$851_Y - end - attribute \src "ls180.v:4984.187-4984.319" - cell $xor $xor$ls180.v:4984$852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:4984$851_Y - connect \Y $xor$ls180.v:4984$852_Y - end - attribute \src "ls180.v:4993.899-4993.983" - cell $xor $xor$ls180.v:4993$854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4993$854_Y - end - attribute \src "ls180.v:4993.634-4993.718" - cell $xor $xor$ls180.v:4993$855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4993$855_Y - end - attribute \src "ls180.v:4993.588-4993.719" - cell $xor $xor$ls180.v:4993$856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:4993$855_Y - connect \Y $xor$ls180.v:4993$856_Y - end - attribute \src "ls180.v:4993.234-4993.318" - cell $xor $xor$ls180.v:4993$857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:4993$857_Y - end - attribute \src "ls180.v:4993.187-4993.319" - cell $xor $xor$ls180.v:4993$858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:4993$857_Y - connect \Y $xor$ls180.v:4993$858_Y - end - attribute \src "ls180.v:4994.899-4994.983" - cell $xor $xor$ls180.v:4994$859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4994$859_Y - end - attribute \src "ls180.v:4994.634-4994.718" - cell $xor $xor$ls180.v:4994$860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4994$860_Y - end - attribute \src "ls180.v:4994.588-4994.719" - cell $xor $xor$ls180.v:4994$861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:4994$860_Y - connect \Y $xor$ls180.v:4994$861_Y - end - attribute \src "ls180.v:4994.234-4994.318" - cell $xor $xor$ls180.v:4994$862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:4994$862_Y - end - attribute \src "ls180.v:4994.187-4994.319" - cell $xor $xor$ls180.v:4994$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:4994$862_Y - connect \Y $xor$ls180.v:4994$863_Y - end - attribute \src "ls180.v:5003.899-5003.983" - cell $xor $xor$ls180.v:5003$865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5003$865_Y - end - attribute \src "ls180.v:5003.634-5003.718" - cell $xor $xor$ls180.v:5003$866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5003$866_Y - end - attribute \src "ls180.v:5003.588-5003.719" - cell $xor $xor$ls180.v:5003$867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5003$866_Y - connect \Y $xor$ls180.v:5003$867_Y - end - attribute \src "ls180.v:5003.234-5003.318" - cell $xor $xor$ls180.v:5003$868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5003$868_Y - end - attribute \src "ls180.v:5003.187-5003.319" - cell $xor $xor$ls180.v:5003$869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5003$868_Y - connect \Y $xor$ls180.v:5003$869_Y - end - attribute \src "ls180.v:5004.899-5004.983" - cell $xor $xor$ls180.v:5004$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5004$870_Y - end - attribute \src "ls180.v:5004.634-5004.718" - cell $xor $xor$ls180.v:5004$871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5004$871_Y - end - attribute \src "ls180.v:5004.588-5004.719" - cell $xor $xor$ls180.v:5004$872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5004$871_Y - connect \Y $xor$ls180.v:5004$872_Y - end - attribute \src "ls180.v:5004.234-5004.318" - cell $xor $xor$ls180.v:5004$873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5004$873_Y - end - attribute \src "ls180.v:5004.187-5004.319" - cell $xor $xor$ls180.v:5004$874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5004$873_Y - connect \Y $xor$ls180.v:5004$874_Y - end - attribute \src "ls180.v:5013.899-5013.983" - cell $xor $xor$ls180.v:5013$876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5013$876_Y - end - attribute \src "ls180.v:5013.634-5013.718" - cell $xor $xor$ls180.v:5013$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5013$877_Y - end - attribute \src "ls180.v:5013.588-5013.719" - cell $xor $xor$ls180.v:5013$878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5013$877_Y - connect \Y $xor$ls180.v:5013$878_Y - end - attribute \src "ls180.v:5013.234-5013.318" - cell $xor $xor$ls180.v:5013$879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5013$879_Y - end - attribute \src "ls180.v:5013.187-5013.319" - cell $xor $xor$ls180.v:5013$880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5013$879_Y - connect \Y $xor$ls180.v:5013$880_Y - end - attribute \src "ls180.v:5014.899-5014.983" - cell $xor $xor$ls180.v:5014$881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5014$881_Y - end - attribute \src "ls180.v:5014.634-5014.718" - cell $xor $xor$ls180.v:5014$882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5014$882_Y - end - attribute \src "ls180.v:5014.588-5014.719" - cell $xor $xor$ls180.v:5014$883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5014$882_Y - connect \Y $xor$ls180.v:5014$883_Y - end - attribute \src "ls180.v:5014.234-5014.318" - cell $xor $xor$ls180.v:5014$884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5014$884_Y - end - attribute \src "ls180.v:5014.187-5014.319" - cell $xor $xor$ls180.v:5014$885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5014$884_Y - connect \Y $xor$ls180.v:5014$885_Y - end - attribute \src "ls180.v:5165.879-5165.961" - cell $xor $xor$ls180.v:5165$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5165$918_Y - end - attribute \src "ls180.v:5165.620-5165.702" - cell $xor $xor$ls180.v:5165$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5165$919_Y - end - attribute \src "ls180.v:5165.575-5165.703" - cell $xor $xor$ls180.v:5165$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5165$919_Y - connect \Y $xor$ls180.v:5165$920_Y - end - attribute \src "ls180.v:5165.229-5165.311" - cell $xor $xor$ls180.v:5165$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5165$921_Y - end - attribute \src "ls180.v:5165.183-5165.312" - cell $xor $xor$ls180.v:5165$922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5165$921_Y - connect \Y $xor$ls180.v:5165$922_Y - end - attribute \src "ls180.v:5166.879-5166.961" - cell $xor $xor$ls180.v:5166$923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5166$923_Y - end - attribute \src "ls180.v:5166.620-5166.702" - cell $xor $xor$ls180.v:5166$924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5166$924_Y - end - attribute \src "ls180.v:5166.575-5166.703" - cell $xor $xor$ls180.v:5166$925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5166$924_Y - connect \Y $xor$ls180.v:5166$925_Y - end - attribute \src "ls180.v:5166.229-5166.311" - cell $xor $xor$ls180.v:5166$926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5166$926_Y - end - attribute \src "ls180.v:5166.183-5166.312" - cell $xor $xor$ls180.v:5166$927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5166$926_Y - connect \Y $xor$ls180.v:5166$927_Y - end - attribute \src "ls180.v:5175.879-5175.961" - cell $xor $xor$ls180.v:5175$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5175$929_Y - end - attribute \src "ls180.v:5175.620-5175.702" - cell $xor $xor$ls180.v:5175$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5175$930_Y - end - attribute \src "ls180.v:5175.575-5175.703" - cell $xor $xor$ls180.v:5175$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5175$930_Y - connect \Y $xor$ls180.v:5175$931_Y - end - attribute \src "ls180.v:5175.229-5175.311" - cell $xor $xor$ls180.v:5175$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5175$932_Y - end - attribute \src "ls180.v:5175.183-5175.312" - cell $xor $xor$ls180.v:5175$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5175$932_Y - connect \Y $xor$ls180.v:5175$933_Y - end - attribute \src "ls180.v:5176.879-5176.961" - cell $xor $xor$ls180.v:5176$934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5176$934_Y - end - attribute \src "ls180.v:5176.620-5176.702" - cell $xor $xor$ls180.v:5176$935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5176$935_Y - end - attribute \src "ls180.v:5176.575-5176.703" - cell $xor $xor$ls180.v:5176$936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5176$935_Y - connect \Y $xor$ls180.v:5176$936_Y - end - attribute \src "ls180.v:5176.229-5176.311" - cell $xor $xor$ls180.v:5176$937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5176$937_Y - end - attribute \src "ls180.v:5176.183-5176.312" - cell $xor $xor$ls180.v:5176$938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5176$937_Y - connect \Y $xor$ls180.v:5176$938_Y - end - attribute \src "ls180.v:5185.879-5185.961" - cell $xor $xor$ls180.v:5185$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5185$940_Y - end - attribute \src "ls180.v:5185.620-5185.702" - cell $xor $xor$ls180.v:5185$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5185$941_Y - end - attribute \src "ls180.v:5185.575-5185.703" - cell $xor $xor$ls180.v:5185$942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5185$941_Y - connect \Y $xor$ls180.v:5185$942_Y - end - attribute \src "ls180.v:5185.229-5185.311" - cell $xor $xor$ls180.v:5185$943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5185$943_Y - end - attribute \src "ls180.v:5185.183-5185.312" - cell $xor $xor$ls180.v:5185$944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5185$943_Y - connect \Y $xor$ls180.v:5185$944_Y - end - attribute \src "ls180.v:5186.879-5186.961" - cell $xor $xor$ls180.v:5186$945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5186$945_Y - end - attribute \src "ls180.v:5186.620-5186.702" - cell $xor $xor$ls180.v:5186$946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5186$946_Y - end - attribute \src "ls180.v:5186.575-5186.703" - cell $xor $xor$ls180.v:5186$947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5186$946_Y - connect \Y $xor$ls180.v:5186$947_Y - end - attribute \src "ls180.v:5186.229-5186.311" - cell $xor $xor$ls180.v:5186$948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5186$948_Y - end - attribute \src "ls180.v:5186.183-5186.312" - cell $xor $xor$ls180.v:5186$949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5186$948_Y - connect \Y $xor$ls180.v:5186$949_Y - end - attribute \src "ls180.v:5195.879-5195.961" - cell $xor $xor$ls180.v:5195$951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5195$951_Y - end - attribute \src "ls180.v:5195.620-5195.702" - cell $xor $xor$ls180.v:5195$952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5195$952_Y - end - attribute \src "ls180.v:5195.575-5195.703" - cell $xor $xor$ls180.v:5195$953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5195$952_Y - connect \Y $xor$ls180.v:5195$953_Y - end - attribute \src "ls180.v:5195.229-5195.311" - cell $xor $xor$ls180.v:5195$954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5195$954_Y - end - attribute \src "ls180.v:5195.183-5195.312" - cell $xor $xor$ls180.v:5195$955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5195$954_Y - connect \Y $xor$ls180.v:5195$955_Y - end - attribute \src "ls180.v:5196.879-5196.961" - cell $xor $xor$ls180.v:5196$956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5196$956_Y - end - attribute \src "ls180.v:5196.620-5196.702" - cell $xor $xor$ls180.v:5196$957 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5196$957_Y - end - attribute \src "ls180.v:5196.575-5196.703" - cell $xor $xor$ls180.v:5196$958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5196$957_Y - connect \Y $xor$ls180.v:5196$958_Y - end - attribute \src "ls180.v:5196.229-5196.311" - cell $xor $xor$ls180.v:5196$959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5196$959_Y - end - attribute \src "ls180.v:5196.183-5196.312" - cell $xor $xor$ls180.v:5196$960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5196$959_Y - connect \Y $xor$ls180.v:5196$960_Y - end - attribute \module_not_derived 1 - attribute \src "ls180.v:10192.13-10569.2" - cell \test_issuer \test_issuer - connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck - connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi - connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo - connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms - connect \busy_o \main_libresocsim_libresoc0 - connect \clk \sys_clk_1 - connect \clk_sel_i \main_libresocsim_libresoc_clk_sel - connect \core_bigendian_i 1'0 - connect \dbus__ack \main_libresocsim_libresoc_dbus_ack - connect \dbus__adr \main_libresocsim_libresoc_dbus_adr - connect \dbus__bte \main_libresocsim_libresoc_dbus_bte - connect \dbus__cti \main_libresocsim_libresoc_dbus_cti - connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc - connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r - connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w - connect \dbus__err \main_libresocsim_libresoc_dbus_err - connect \dbus__sel \main_libresocsim_libresoc_dbus_sel - connect \dbus__stb \main_libresocsim_libresoc_dbus_stb - connect \dbus__we \main_libresocsim_libresoc_dbus_we - connect \eint_0__core__i \eint [0] - connect \eint_0__pad__i \eint_1 [0] - connect \eint_1__core__i \eint [1] - connect \eint_1__pad__i \eint_1 [1] - connect \eint_2__core__i \eint [2] - connect \eint_2__pad__i \eint_1 [2] - connect \gpio_e10__core__i \gpio_i [10] - connect \gpio_e10__core__o \gpio_o [10] - connect \gpio_e10__core__oe \gpio_oe [10] - connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] - connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] - connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] - connect \gpio_e11__core__i \gpio_i [11] - connect \gpio_e11__core__o \gpio_o [11] - connect \gpio_e11__core__oe \gpio_oe [11] - connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] - connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] - connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] - connect \gpio_e12__core__i \gpio_i [12] - connect \gpio_e12__core__o \gpio_o [12] - connect \gpio_e12__core__oe \gpio_oe [12] - connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] - connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] - connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] - connect \gpio_e13__core__i \gpio_i [13] - connect \gpio_e13__core__o \gpio_o [13] - connect \gpio_e13__core__oe \gpio_oe [13] - connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] - connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] - connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] - connect \gpio_e14__core__i \gpio_i [14] - connect \gpio_e14__core__o \gpio_o [14] - connect \gpio_e14__core__oe \gpio_oe [14] - connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] - connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] - connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] - connect \gpio_e15__core__i \gpio_i [15] - connect \gpio_e15__core__o \gpio_o [15] - connect \gpio_e15__core__oe \gpio_oe [15] - connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] - connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] - connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] - connect \gpio_e8__core__i \gpio_i [8] - connect \gpio_e8__core__o \gpio_o [8] - connect \gpio_e8__core__oe \gpio_oe [8] - connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] - connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] - connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] - connect \gpio_e9__core__i \gpio_i [9] - connect \gpio_e9__core__o \gpio_o [9] - connect \gpio_e9__core__oe \gpio_oe [9] - connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] - connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] - connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] - connect \gpio_s0__core__i \gpio_i [0] - connect \gpio_s0__core__o \gpio_o [0] - connect \gpio_s0__core__oe \gpio_oe [0] - connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] - connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] - connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] - connect \gpio_s1__core__i \gpio_i [1] - connect \gpio_s1__core__o \gpio_o [1] - connect \gpio_s1__core__oe \gpio_oe [1] - connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] - connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] - connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] - connect \gpio_s2__core__i \gpio_i [2] - connect \gpio_s2__core__o \gpio_o [2] - connect \gpio_s2__core__oe \gpio_oe [2] - connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] - connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] - connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] - connect \gpio_s3__core__i \gpio_i [3] - connect \gpio_s3__core__o \gpio_o [3] - connect \gpio_s3__core__oe \gpio_oe [3] - connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] - connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] - connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] - connect \gpio_s4__core__i \gpio_i [4] - connect \gpio_s4__core__o \gpio_o [4] - connect \gpio_s4__core__oe \gpio_oe [4] - connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] - connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] - connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] - connect \gpio_s5__core__i \gpio_i [5] - connect \gpio_s5__core__o \gpio_o [5] - connect \gpio_s5__core__oe \gpio_oe [5] - connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] - connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] - connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] - connect \gpio_s6__core__i \gpio_i [6] - connect \gpio_s6__core__o \gpio_o [6] - connect \gpio_s6__core__oe \gpio_oe [6] - connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] - connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] - connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] - connect \gpio_s7__core__i \gpio_i [7] - connect \gpio_s7__core__o \gpio_o [7] - connect \gpio_s7__core__oe \gpio_oe [7] - connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] - connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] - connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] - connect \ibus__ack \main_libresocsim_libresoc_ibus_ack - connect \ibus__adr \main_libresocsim_libresoc_ibus_adr - connect \ibus__bte \main_libresocsim_libresoc_ibus_bte - connect \ibus__cti \main_libresocsim_libresoc_ibus_cti - connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc - connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r - connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w - connect \ibus__err \main_libresocsim_libresoc_ibus_err - connect \ibus__sel \main_libresocsim_libresoc_ibus_sel - connect \ibus__stb \main_libresocsim_libresoc_ibus_stb - connect \ibus__we \main_libresocsim_libresoc_ibus_we - connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack - connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr - connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte - connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti - connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc - connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r - connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w - connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err - connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel - connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb - connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we - connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack - connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr - connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte - connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti - connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc - connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r - connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w - connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err - connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel - connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb - connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we - connect \int_level_i \main_libresocsim_libresoc_interrupt - connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack - connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr - connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc - connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r - connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w - connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err - connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel - connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb - connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we - connect \memerr_o \main_libresocsim_libresoc1 - connect \mspi0_clk__core__o \spimaster_clk - connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - connect \mspi0_cs_n__core__o \spimaster_cs_n - connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - connect \mspi0_miso__core__i \spimaster_miso - connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - connect \mspi0_mosi__core__o \spimaster_mosi - connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - connect \mspi1_clk__core__o \spisdcard_clk - connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - connect \mspi1_cs_n__core__o \spisdcard_cs_n - connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - connect \mspi1_miso__core__i \spisdcard_miso - connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - connect \mspi1_mosi__core__o \spisdcard_mosi - connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - connect \mtwi_scl__core__o \i2c_scl - connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - connect \mtwi_sda__core__i \i2c_sda_i - connect \mtwi_sda__core__o \i2c_sda_o - connect \mtwi_sda__core__oe \i2c_sda_oe - connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - connect \pc_i 1'0 - connect \pc_i_ok 1'0 - connect \pc_o \main_libresocsim_libresoc2 - connect \pll_48_o \main_libresocsim_libresoc_pll_48_o - connect \pwm_0__core__o \pwm [0] - connect \pwm_0__pad__o \pwm_1 [0] - connect \pwm_1__core__o \pwm [1] - connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10292$2762_Y - connect \sd0_clk__core__o \sdcard_clk - connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - connect \sd0_cmd__core__i \sdcard_cmd_i - connect \sd0_cmd__core__o \sdcard_cmd_o - connect \sd0_cmd__core__oe \sdcard_cmd_oe - connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data0__core__i \sdcard_cmd_i - connect \sd0_data0__core__o \sdcard_cmd_o - connect \sd0_data0__core__oe \sdcard_cmd_oe - connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data1__core__i \sdcard_cmd_i - connect \sd0_data1__core__o \sdcard_cmd_o - connect \sd0_data1__core__oe \sdcard_cmd_oe - connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data2__core__i \sdcard_cmd_i - connect \sd0_data2__core__o \sdcard_cmd_o - connect \sd0_data2__core__oe \sdcard_cmd_oe - connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data3__core__i \sdcard_cmd_i - connect \sd0_data3__core__o \sdcard_cmd_o - connect \sd0_data3__core__oe \sdcard_cmd_oe - connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sdr_a_0__core__o \sdram_a [0] - connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] - connect \sdr_a_10__core__o \sdram_a [10] - connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] - connect \sdr_a_11__core__o \sdram_a [11] - connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] - connect \sdr_a_12__core__o \sdram_a [12] - connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] - connect \sdr_a_1__core__o \sdram_a [1] - connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] - connect \sdr_a_2__core__o \sdram_a [2] - connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] - connect \sdr_a_3__core__o \sdram_a [3] - connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] - connect \sdr_a_4__core__o \sdram_a [4] - connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] - connect \sdr_a_5__core__o \sdram_a [5] - connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] - connect \sdr_a_6__core__o \sdram_a [6] - connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] - connect \sdr_a_7__core__o \sdram_a [7] - connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] - connect \sdr_a_8__core__o \sdram_a [8] - connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] - connect \sdr_a_9__core__o \sdram_a [9] - connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] - connect \sdr_ba_0__core__o \sdram_ba [0] - connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] - connect \sdr_ba_1__core__o \sdram_ba [1] - connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] - connect \sdr_cas_n__core__o \sdram_cas_n - connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - connect \sdr_cke__core__o \sdram_cke - connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - connect \sdr_clock__core__o \sdram_clock - connect \sdr_clock__pad__o \sdram_clock_1 - connect \sdr_cs_n__core__o \sdram_cs_n - connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - connect \sdr_dm_0__core__o \sdram_dm [0] - connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] - connect \sdr_dm_1__core__i \sdram_dq_i [1] - connect \sdr_dm_1__core__o \sdram_dq_o [1] - connect \sdr_dm_1__core__oe \sdram_dq_oe - connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_0__core__i \sdram_dq_i [0] - connect \sdr_dq_0__core__o \sdram_dq_o [0] - connect \sdr_dq_0__core__oe \sdram_dq_oe - connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] - connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] - connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_10__core__i \sdram_dq_i [10] - connect \sdr_dq_10__core__o \sdram_dq_o [10] - connect \sdr_dq_10__core__oe \sdram_dq_oe - connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] - connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] - connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_11__core__i \sdram_dq_i [11] - connect \sdr_dq_11__core__o \sdram_dq_o [11] - connect \sdr_dq_11__core__oe \sdram_dq_oe - connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] - connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] - connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_12__core__i \sdram_dq_i [12] - connect \sdr_dq_12__core__o \sdram_dq_o [12] - connect \sdr_dq_12__core__oe \sdram_dq_oe - connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] - connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] - connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_13__core__i \sdram_dq_i [13] - connect \sdr_dq_13__core__o \sdram_dq_o [13] - connect \sdr_dq_13__core__oe \sdram_dq_oe - connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] - connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] - connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_14__core__i \sdram_dq_i [14] - connect \sdr_dq_14__core__o \sdram_dq_o [14] - connect \sdr_dq_14__core__oe \sdram_dq_oe - connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] - connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] - connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_15__core__i \sdram_dq_i [15] - connect \sdr_dq_15__core__o \sdram_dq_o [15] - connect \sdr_dq_15__core__oe \sdram_dq_oe - connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] - connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] - connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_1__core__i \sdram_dq_i [1] - connect \sdr_dq_1__core__o \sdram_dq_o [1] - connect \sdr_dq_1__core__oe \sdram_dq_oe - connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_2__core__i \sdram_dq_i [2] - connect \sdr_dq_2__core__o \sdram_dq_o [2] - connect \sdr_dq_2__core__oe \sdram_dq_oe - connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] - connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] - connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_3__core__i \sdram_dq_i [3] - connect \sdr_dq_3__core__o \sdram_dq_o [3] - connect \sdr_dq_3__core__oe \sdram_dq_oe - connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] - connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] - connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_4__core__i \sdram_dq_i [4] - connect \sdr_dq_4__core__o \sdram_dq_o [4] - connect \sdr_dq_4__core__oe \sdram_dq_oe - connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] - connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] - connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_5__core__i \sdram_dq_i [5] - connect \sdr_dq_5__core__o \sdram_dq_o [5] - connect \sdr_dq_5__core__oe \sdram_dq_oe - connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] - connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] - connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_6__core__i \sdram_dq_i [6] - connect \sdr_dq_6__core__o \sdram_dq_o [6] - connect \sdr_dq_6__core__oe \sdram_dq_oe - connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] - connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] - connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_7__core__i \sdram_dq_i [7] - connect \sdr_dq_7__core__o \sdram_dq_o [7] - connect \sdr_dq_7__core__oe \sdram_dq_oe - connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] - connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] - connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_8__core__i \sdram_dq_i [8] - connect \sdr_dq_8__core__o \sdram_dq_o [8] - connect \sdr_dq_8__core__oe \sdram_dq_oe - connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] - connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] - connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_9__core__i \sdram_dq_i [9] - connect \sdr_dq_9__core__o \sdram_dq_o [9] - connect \sdr_dq_9__core__oe \sdram_dq_oe - connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] - connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] - connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_ras_n__core__o \sdram_ras_n - connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - connect \sdr_we_n__core__o \sdram_we_n - connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3720 - sync always - sync init - end - attribute \src "ls180.v:1001.12-1001.44" - process $proc$ls180.v:1001$3148 - assign { } { } - assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] - end - attribute \src "ls180.v:1002.5-1002.31" - process $proc$ls180.v:1002$3149 - assign { } { } - assign $1\main_spimaster12_re[0:0] 1'0 - sync always - sync init - update \main_spimaster12_re $1\main_spimaster12_re[0:0] - end - attribute \src "ls180.v:10056.1-10066.4" - process $proc$ls180.v:10056$2692 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 0 - assign $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 0 - assign $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 0 - assign $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 7'xxxxxxx - assign $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 0 - assign $0\memadr[6:0] \main_libresocsim_adr - attribute \src "ls180.v:10057.2-10058.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:10057.6-10057.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 255 - case - end - attribute \src "ls180.v:10059.2-10060.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:10059.6-10059.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 65280 - case - end - attribute \src "ls180.v:10061.2-10062.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:10061.6-10061.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 16711680 - case - end - attribute \src "ls180.v:10063.2-10064.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:10063.6-10063.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 32'11111111000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr $0\memadr[6:0] - update $memwr$\mem$ls180.v:10058$1_ADDR $0$memwr$\mem$ls180.v:10058$1_ADDR[6:0]$2693 - update $memwr$\mem$ls180.v:10058$1_DATA $0$memwr$\mem$ls180.v:10058$1_DATA[31:0]$2694 - update $memwr$\mem$ls180.v:10058$1_EN $0$memwr$\mem$ls180.v:10058$1_EN[31:0]$2695 - update $memwr$\mem$ls180.v:10060$2_ADDR $0$memwr$\mem$ls180.v:10060$2_ADDR[6:0]$2696 - update $memwr$\mem$ls180.v:10060$2_DATA $0$memwr$\mem$ls180.v:10060$2_DATA[31:0]$2697 - update $memwr$\mem$ls180.v:10060$2_EN $0$memwr$\mem$ls180.v:10060$2_EN[31:0]$2698 - update $memwr$\mem$ls180.v:10062$3_ADDR $0$memwr$\mem$ls180.v:10062$3_ADDR[6:0]$2699 - update $memwr$\mem$ls180.v:10062$3_DATA $0$memwr$\mem$ls180.v:10062$3_DATA[31:0]$2700 - update $memwr$\mem$ls180.v:10062$3_EN $0$memwr$\mem$ls180.v:10062$3_EN[31:0]$2701 - update $memwr$\mem$ls180.v:10064$4_ADDR $0$memwr$\mem$ls180.v:10064$4_ADDR[6:0]$2702 - update $memwr$\mem$ls180.v:10064$4_DATA $0$memwr$\mem$ls180.v:10064$4_DATA[31:0]$2703 - update $memwr$\mem$ls180.v:10064$4_EN $0$memwr$\mem$ls180.v:10064$4_EN[31:0]$2704 - end - attribute \src "ls180.v:1006.11-1006.42" - process $proc$ls180.v:1006$3150 - assign { } { } - assign $1\main_spimaster16_storage[7:0] 8'00000000 - sync always - sync init - update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] - end - attribute \src "ls180.v:1007.5-1007.31" - process $proc$ls180.v:1007$3151 - assign { } { } - assign $1\main_spimaster17_re[0:0] 1'0 - sync always - sync init - update \main_spimaster17_re $1\main_spimaster17_re[0:0] - end - attribute \src "ls180.v:10076.1-10080.4" - process $proc$ls180.v:10076$2706 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 3'xxx - assign $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10079$2710_DATA - attribute \src "ls180.v:10077.2-10078.129" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10077.6-10077.60" - case 1'1 - assign $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10078$5_ADDR $0$memwr$\storage$ls180.v:10078$5_ADDR[2:0]$2707 - update $memwr$\storage$ls180.v:10078$5_DATA $0$memwr$\storage$ls180.v:10078$5_DATA[24:0]$2708 - update $memwr$\storage$ls180.v:10078$5_EN $0$memwr$\storage$ls180.v:10078$5_EN[24:0]$2709 - end - attribute \src "ls180.v:10082.1-10083.4" - process $proc$ls180.v:10082$2711 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10090.1-10094.4" - process $proc$ls180.v:10090$2713 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 3'xxx - assign $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10093$2717_DATA - attribute \src "ls180.v:10091.2-10092.131" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10091.6-10091.60" - case 1'1 - assign $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10092$6_ADDR $0$memwr$\storage_1$ls180.v:10092$6_ADDR[2:0]$2714 - update $memwr$\storage_1$ls180.v:10092$6_DATA $0$memwr$\storage_1$ls180.v:10092$6_DATA[24:0]$2715 - update $memwr$\storage_1$ls180.v:10092$6_EN $0$memwr$\storage_1$ls180.v:10092$6_EN[24:0]$2716 - end - attribute \src "ls180.v:10096.1-10097.4" - process $proc$ls180.v:10096$2718 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10104.1-10108.4" - process $proc$ls180.v:10104$2720 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 3'xxx - assign $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10107$2724_DATA - attribute \src "ls180.v:10105.2-10106.131" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10105.6-10105.60" - case 1'1 - assign $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10106$7_ADDR $0$memwr$\storage_2$ls180.v:10106$7_ADDR[2:0]$2721 - update $memwr$\storage_2$ls180.v:10106$7_DATA $0$memwr$\storage_2$ls180.v:10106$7_DATA[24:0]$2722 - update $memwr$\storage_2$ls180.v:10106$7_EN $0$memwr$\storage_2$ls180.v:10106$7_EN[24:0]$2723 - end - attribute \src "ls180.v:1011.5-1011.36" - process $proc$ls180.v:1011$3152 - assign { } { } - assign $1\main_spimaster21_storage[0:0] 1'1 - sync always - sync init - update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] - end - attribute \src "ls180.v:10110.1-10111.4" - process $proc$ls180.v:10110$2725 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10118.1-10122.4" - process $proc$ls180.v:10118$2727 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 3'xxx - assign $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10121$2731_DATA - attribute \src "ls180.v:10119.2-10120.131" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10119.6-10119.60" - case 1'1 - assign $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10120$8_ADDR $0$memwr$\storage_3$ls180.v:10120$8_ADDR[2:0]$2728 - update $memwr$\storage_3$ls180.v:10120$8_DATA $0$memwr$\storage_3$ls180.v:10120$8_DATA[24:0]$2729 - update $memwr$\storage_3$ls180.v:10120$8_EN $0$memwr$\storage_3$ls180.v:10120$8_EN[24:0]$2730 - end - attribute \src "ls180.v:1012.5-1012.31" - process $proc$ls180.v:1012$3153 - assign { } { } - assign $1\main_spimaster22_re[0:0] 1'0 - sync always - sync init - update \main_spimaster22_re $1\main_spimaster22_re[0:0] - end - attribute \src "ls180.v:10124.1-10125.4" - process $proc$ls180.v:10124$2732 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1013.5-1013.36" - process $proc$ls180.v:1013$3154 - assign { } { } - assign $1\main_spimaster23_storage[0:0] 1'0 - sync always - sync init - update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] - end - attribute \src "ls180.v:10133.1-10137.4" - process $proc$ls180.v:10133$2734 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10136$2738_DATA - attribute \src "ls180.v:10134.2-10135.77" - switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10134.6-10134.33" - case 1'1 - assign $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10135$9_ADDR $0$memwr$\storage_4$ls180.v:10135$9_ADDR[3:0]$2735 - update $memwr$\storage_4$ls180.v:10135$9_DATA $0$memwr$\storage_4$ls180.v:10135$9_DATA[9:0]$2736 - update $memwr$\storage_4$ls180.v:10135$9_EN $0$memwr$\storage_4$ls180.v:10135$9_EN[9:0]$2737 - end - attribute \src "ls180.v:10139.1-10142.4" - process $proc$ls180.v:10139$2739 - assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10140.2-10141.55" - switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10140.6-10140.33" - case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10141$2740_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_5 $0\memdat_5[9:0] - end - attribute \src "ls180.v:1014.5-1014.31" - process $proc$ls180.v:1014$3155 - assign { } { } - assign $1\main_spimaster24_re[0:0] 1'0 - sync always - sync init - update \main_spimaster24_re $1\main_spimaster24_re[0:0] - end - attribute \src "ls180.v:1015.5-1015.39" - process $proc$ls180.v:1015$3156 - assign { } { } - assign $1\main_spimaster25_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] - end - attribute \src "ls180.v:10150.1-10154.4" - process $proc$ls180.v:10150$2741 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10153$2745_DATA - attribute \src "ls180.v:10151.2-10152.77" - switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10151.6-10151.33" - case 1'1 - assign $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10152$10_ADDR $0$memwr$\storage_5$ls180.v:10152$10_ADDR[3:0]$2742 - update $memwr$\storage_5$ls180.v:10152$10_DATA $0$memwr$\storage_5$ls180.v:10152$10_DATA[9:0]$2743 - update $memwr$\storage_5$ls180.v:10152$10_EN $0$memwr$\storage_5$ls180.v:10152$10_EN[9:0]$2744 - end - attribute \src "ls180.v:10156.1-10159.4" - process $proc$ls180.v:10156$2746 - assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10157.2-10158.55" - switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10157.6-10157.33" - case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10158$2747_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_7 $0\memdat_7[9:0] - end - attribute \src "ls180.v:1016.5-1016.38" - process $proc$ls180.v:1016$3157 - assign { } { } - assign $1\main_spimaster26_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] - end - attribute \src "ls180.v:10166.1-10170.4" - process $proc$ls180.v:10166$2748 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10169$2752_DATA - attribute \src "ls180.v:10167.2-10168.85" - switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10167.6-10167.37" - case 1'1 - assign $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10168$11_ADDR $0$memwr$\storage_6$ls180.v:10168$11_ADDR[4:0]$2749 - update $memwr$\storage_6$ls180.v:10168$11_DATA $0$memwr$\storage_6$ls180.v:10168$11_DATA[9:0]$2750 - update $memwr$\storage_6$ls180.v:10168$11_EN $0$memwr$\storage_6$ls180.v:10168$11_EN[9:0]$2751 - end - attribute \src "ls180.v:1017.11-1017.40" - process $proc$ls180.v:1017$3158 - assign { } { } - assign $1\main_spimaster27_count[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count $1\main_spimaster27_count[2:0] - end - attribute \src "ls180.v:10172.1-10173.4" - process $proc$ls180.v:10172$2753 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1018.5-1018.39" - process $proc$ls180.v:1018$3159 - assign { } { } - assign $1\main_spimaster28_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] - end - attribute \src "ls180.v:10180.1-10184.4" - process $proc$ls180.v:10180$2755 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10183$2759_DATA - attribute \src "ls180.v:10181.2-10182.85" - switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10181.6-10181.37" - case 1'1 - assign $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10182$12_ADDR $0$memwr$\storage_7$ls180.v:10182$12_ADDR[4:0]$2756 - update $memwr$\storage_7$ls180.v:10182$12_DATA $0$memwr$\storage_7$ls180.v:10182$12_DATA[9:0]$2757 - update $memwr$\storage_7$ls180.v:10182$12_EN $0$memwr$\storage_7$ls180.v:10182$12_EN[9:0]$2758 - end - attribute \src "ls180.v:10186.1-10187.4" - process $proc$ls180.v:10186$2760 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1019.5-1019.39" - process $proc$ls180.v:1019$3160 - assign { } { } - assign $1\main_spimaster29_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] - end - attribute \src "ls180.v:1020.12-1020.48" - process $proc$ls180.v:1020$3161 - assign { } { } - assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] - end - attribute \src "ls180.v:1023.11-1023.44" - process $proc$ls180.v:1023$3162 - assign { } { } - assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] - end - attribute \src "ls180.v:1024.11-1024.43" - process $proc$ls180.v:1024$3163 - assign { } { } - assign $1\main_spimaster34_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] - end - attribute \src "ls180.v:1025.11-1025.44" - process $proc$ls180.v:1025$3164 - assign { } { } - assign $1\main_spimaster35_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] - end - attribute \src "ls180.v:1028.5-1028.32" - process $proc$ls180.v:1028$3165 - assign { } { } - assign $1\main_spisdcard_done0[0:0] 1'0 - sync always - sync init - update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] - end - attribute \src "ls180.v:1029.5-1029.30" - process $proc$ls180.v:1029$3166 - assign { } { } - assign $1\main_spisdcard_irq[0:0] 1'0 - sync always - sync init - update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] - end - attribute \src "ls180.v:1031.11-1031.37" - process $proc$ls180.v:1031$3167 - assign { } { } - assign $1\main_spisdcard_miso[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] - end - attribute \src "ls180.v:1035.5-1035.33" - process $proc$ls180.v:1035$3168 - assign { } { } - assign $1\main_spisdcard_start1[0:0] 1'0 - sync always - sync init - update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:1037.12-1037.50" - process $proc$ls180.v:1037$3169 - assign { } { } - assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] - end - attribute \src "ls180.v:1038.5-1038.37" - process $proc$ls180.v:1038$3170 - assign { } { } - assign $1\main_spisdcard_control_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] - end - attribute \src "ls180.v:1042.11-1042.45" - process $proc$ls180.v:1042$3171 - assign { } { } - assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] - end - attribute \src "ls180.v:1043.5-1043.34" - process $proc$ls180.v:1043$3172 - assign { } { } - assign $1\main_spisdcard_mosi_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] - end - attribute \src "ls180.v:1047.5-1047.37" - process $proc$ls180.v:1047$3173 - assign { } { } - assign $1\main_spisdcard_cs_storage[0:0] 1'1 - sync always - sync init - update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] - end - attribute \src "ls180.v:1048.5-1048.32" - process $proc$ls180.v:1048$3174 - assign { } { } - assign $1\main_spisdcard_cs_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] - end - attribute \src "ls180.v:1049.5-1049.43" - process $proc$ls180.v:1049$3175 - assign { } { } - assign $1\main_spisdcard_loopback_storage[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] - end - attribute \src "ls180.v:1050.5-1050.38" - process $proc$ls180.v:1050$3176 - assign { } { } - assign $1\main_spisdcard_loopback_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] - end - attribute \src "ls180.v:1051.5-1051.37" - process $proc$ls180.v:1051$3177 - assign { } { } - assign $1\main_spisdcard_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] - end - attribute \src "ls180.v:1052.5-1052.36" - process $proc$ls180.v:1052$3178 - assign { } { } - assign $1\main_spisdcard_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] - end - attribute \src "ls180.v:1053.11-1053.38" - process $proc$ls180.v:1053$3179 - assign { } { } - assign $1\main_spisdcard_count[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count $1\main_spisdcard_count[2:0] - end - attribute \src "ls180.v:1054.5-1054.37" - process $proc$ls180.v:1054$3180 - assign { } { } - assign $1\main_spisdcard_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] - end - attribute \src "ls180.v:1055.5-1055.37" - process $proc$ls180.v:1055$3181 - assign { } { } - assign $1\main_spisdcard_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] - end - attribute \src "ls180.v:1056.12-1056.47" - process $proc$ls180.v:1056$3182 - assign { } { } - assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] - end - attribute \src "ls180.v:1059.11-1059.42" - process $proc$ls180.v:1059$3183 - assign { } { } - assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] - end - attribute \src "ls180.v:1060.11-1060.41" - process $proc$ls180.v:1060$3184 - assign { } { } - assign $1\main_spisdcard_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] - end - attribute \src "ls180.v:1061.11-1061.42" - process $proc$ls180.v:1061$3185 - assign { } { } - assign $1\main_spisdcard_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] - end - attribute \src "ls180.v:1062.12-1062.45" - process $proc$ls180.v:1062$3186 - assign { } { } - assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 - sync always - sync init - update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] - end - attribute \src "ls180.v:1063.5-1063.30" - process $proc$ls180.v:1063$3187 - assign { } { } - assign $1\main_spimaster1_re[0:0] 1'0 - sync always - sync init - update \main_spimaster1_re $1\main_spimaster1_re[0:0] - end - attribute \src "ls180.v:1065.12-1065.30" - process $proc$ls180.v:1065$3188 - assign { } { } - assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000 - sync always - sync init - update \main_dummy $1\main_dummy[35:0] - end - attribute \src "ls180.v:1069.12-1069.37" - process $proc$ls180.v:1069$3189 - assign { } { } - assign $1\main_pwm0_counter[31:0] 0 - sync always - sync init - update \main_pwm0_counter $1\main_pwm0_counter[31:0] - end - attribute \src "ls180.v:1070.5-1070.36" - process $proc$ls180.v:1070$3190 - assign { } { } - assign $1\main_pwm0_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] - end - attribute \src "ls180.v:1071.5-1071.31" - process $proc$ls180.v:1071$3191 - assign { } { } - assign $1\main_pwm0_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] - end - attribute \src "ls180.v:1072.12-1072.43" - process $proc$ls180.v:1072$3192 - assign { } { } - assign $1\main_pwm0_width_storage[31:0] 0 - sync always - sync init - update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] - end - attribute \src "ls180.v:1073.5-1073.30" - process $proc$ls180.v:1073$3193 - assign { } { } - assign $1\main_pwm0_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] - end - attribute \src "ls180.v:1074.12-1074.44" - process $proc$ls180.v:1074$3194 - assign { } { } - assign $1\main_pwm0_period_storage[31:0] 0 - sync always - sync init - update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] - end - attribute \src "ls180.v:1075.5-1075.31" - process $proc$ls180.v:1075$3195 - assign { } { } - assign $1\main_pwm0_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] - end - attribute \src "ls180.v:1079.12-1079.37" - process $proc$ls180.v:1079$3196 - assign { } { } - assign $1\main_pwm1_counter[31:0] 0 - sync always - sync init - update \main_pwm1_counter $1\main_pwm1_counter[31:0] - end - attribute \src "ls180.v:1080.5-1080.36" - process $proc$ls180.v:1080$3197 - assign { } { } - assign $1\main_pwm1_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] - end - attribute \src "ls180.v:1081.5-1081.31" - process $proc$ls180.v:1081$3198 - assign { } { } - assign $1\main_pwm1_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] - end - attribute \src "ls180.v:1082.12-1082.43" - process $proc$ls180.v:1082$3199 - assign { } { } - assign $1\main_pwm1_width_storage[31:0] 0 - sync always - sync init - update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] - end - attribute \src "ls180.v:1083.5-1083.30" - process $proc$ls180.v:1083$3200 - assign { } { } - assign $1\main_pwm1_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] - end - attribute \src "ls180.v:1084.12-1084.44" - process $proc$ls180.v:1084$3201 - assign { } { } - assign $1\main_pwm1_period_storage[31:0] 0 - sync always - sync init - update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] - end - attribute \src "ls180.v:1085.5-1085.31" - process $proc$ls180.v:1085$3202 - assign { } { } - assign $1\main_pwm1_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] - end - attribute \src "ls180.v:1089.11-1089.34" - process $proc$ls180.v:1089$3203 - assign { } { } - assign $1\main_i2c_storage[2:0] 3'000 - sync always - sync init - update \main_i2c_storage $1\main_i2c_storage[2:0] - end - attribute \src "ls180.v:1090.5-1090.23" - process $proc$ls180.v:1090$3204 - assign { } { } - assign $1\main_i2c_re[0:0] 1'0 - sync always - sync init - update \main_i2c_re $1\main_i2c_re[0:0] - end - attribute \src "ls180.v:1096.11-1096.46" - process $proc$ls180.v:1096$3205 - assign { } { } - assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 - sync always - sync init - update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] - end - attribute \src "ls180.v:1097.5-1097.33" - process $proc$ls180.v:1097$3206 - assign { } { } - assign $1\main_sdphy_clocker_re[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] - end - attribute \src "ls180.v:1099.5-1099.35" - process $proc$ls180.v:1099$3207 - assign { } { } - assign $1\main_sdphy_clocker_clk0[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] - end - attribute \src "ls180.v:1101.11-1101.41" - process $proc$ls180.v:1101$3208 - assign { } { } - assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 - sync always - sync init - update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] - end - attribute \src "ls180.v:1102.5-1102.35" - process $proc$ls180.v:1102$3209 - assign { } { } - assign $1\main_sdphy_clocker_clk1[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:1103.5-1103.36" - process $proc$ls180.v:1103$3210 - assign { } { } - assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] - end - attribute \src "ls180.v:1107.5-1107.40" - process $proc$ls180.v:1107$3211 - assign { } { } - assign $0\main_sdphy_init_initialize_w[0:0] 1'0 - sync always - update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] - sync init - end - attribute \src "ls180.v:1112.5-1112.48" - process $proc$ls180.v:1112$3212 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1113.5-1113.50" - process $proc$ls180.v:1113$3213 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1114.5-1114.51" - process $proc$ls180.v:1114$3214 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1115.11-1115.57" - process $proc$ls180.v:1115$3215 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1116.5-1116.52" - process $proc$ls180.v:1116$3216 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1117.11-1117.39" - process $proc$ls180.v:1117$3217 - assign { } { } - assign $1\main_sdphy_init_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] - end - attribute \src "ls180.v:1122.5-1122.48" - process $proc$ls180.v:1122$3218 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1123.5-1123.50" - process $proc$ls180.v:1123$3219 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1124.5-1124.51" - process $proc$ls180.v:1124$3220 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1125.11-1125.57" - process $proc$ls180.v:1125$3221 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1126.5-1126.52" - process $proc$ls180.v:1126$3222 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1127.5-1127.38" - process $proc$ls180.v:1127$3223 - assign { } { } - assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] - end - attribute \src "ls180.v:1128.5-1128.38" - process $proc$ls180.v:1128$3224 - assign { } { } - assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] - end - attribute \src "ls180.v:1129.5-1129.37" - process $proc$ls180.v:1129$3225 - assign { } { } - assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] - end - attribute \src "ls180.v:1130.11-1130.51" - process $proc$ls180.v:1130$3226 - assign { } { } - assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1131.5-1131.32" - process $proc$ls180.v:1131$3227 - assign { } { } - assign $1\main_sdphy_cmdw_done[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] - end - attribute \src "ls180.v:1132.11-1132.39" - process $proc$ls180.v:1132$3228 - assign { } { } - assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] - end - attribute \src "ls180.v:1135.5-1135.49" - process $proc$ls180.v:1135$3229 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1136.5-1136.48" - process $proc$ls180.v:1136$3230 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1137.5-1137.55" - process $proc$ls180.v:1137$3231 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1139.5-1139.57" - process $proc$ls180.v:1139$3232 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1140.5-1140.58" - process $proc$ls180.v:1140$3233 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1142.11-1142.64" - process $proc$ls180.v:1142$3234 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1143.5-1143.59" - process $proc$ls180.v:1143$3235 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1145.5-1145.48" - process $proc$ls180.v:1145$3236 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1146.5-1146.50" - process $proc$ls180.v:1146$3237 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1147.5-1147.51" - process $proc$ls180.v:1147$3238 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1148.11-1148.57" - process $proc$ls180.v:1148$3239 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1149.5-1149.52" - process $proc$ls180.v:1149$3240 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:115.5-115.49" - process $proc$ls180.v:115$2785 - assign { } { } - assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] - end - attribute \src "ls180.v:1150.5-1150.38" - process $proc$ls180.v:1150$3241 - assign { } { } - assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] - end - attribute \src "ls180.v:1151.5-1151.38" - process $proc$ls180.v:1151$3242 - assign { } { } - assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] - end - attribute \src "ls180.v:1152.5-1152.37" - process $proc$ls180.v:1152$3243 - assign { } { } - assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] - end - attribute \src "ls180.v:1153.11-1153.53" - process $proc$ls180.v:1153$3244 - assign { } { } - assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] - end - attribute \src "ls180.v:1154.5-1154.40" - process $proc$ls180.v:1154$3245 - assign { } { } - assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] - end - attribute \src "ls180.v:1155.5-1155.40" - process $proc$ls180.v:1155$3246 - assign { } { } - assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] - end - attribute \src "ls180.v:1156.5-1156.39" - process $proc$ls180.v:1156$3247 - assign { } { } - assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] - end - attribute \src "ls180.v:1157.11-1157.53" - process $proc$ls180.v:1157$3248 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] - end - attribute \src "ls180.v:1158.11-1158.55" - process $proc$ls180.v:1158$3249 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] - end - attribute \src "ls180.v:1159.12-1159.48" - process $proc$ls180.v:1159$3250 - assign { } { } - assign $1\main_sdphy_cmdr_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] - end - attribute \src "ls180.v:1160.11-1160.39" - process $proc$ls180.v:1160$3251 - assign { } { } - assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] - end - attribute \src "ls180.v:1162.5-1162.46" - process $proc$ls180.v:1162$3252 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:117.5-117.49" - process $proc$ls180.v:117$2786 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] - sync init - end - attribute \src "ls180.v:1173.5-1173.53" - process $proc$ls180.v:1173$3253 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1178.5-1178.36" - process $proc$ls180.v:1178$3254 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] - end - attribute \src "ls180.v:1181.5-1181.53" - process $proc$ls180.v:1181$3255 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1182.5-1182.52" - process $proc$ls180.v:1182$3256 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1186.5-1186.55" - process $proc$ls180.v:1186$3257 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - end - attribute \src "ls180.v:1187.5-1187.54" - process $proc$ls180.v:1187$3258 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - end - attribute \src "ls180.v:1188.11-1188.68" - process $proc$ls180.v:1188$3259 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1189.11-1189.81" - process $proc$ls180.v:1189$3260 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1190.11-1190.54" - process $proc$ls180.v:1190$3261 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - end - attribute \src "ls180.v:1192.5-1192.53" - process $proc$ls180.v:1192$3262 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1203.5-1203.49" - process $proc$ls180.v:1203$3263 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1205.5-1205.49" - process $proc$ls180.v:1205$3264 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - end - attribute \src "ls180.v:1206.5-1206.48" - process $proc$ls180.v:1206$3265 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - end - attribute \src "ls180.v:1207.11-1207.62" - process $proc$ls180.v:1207$3266 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1208.5-1208.38" - process $proc$ls180.v:1208$3267 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] - end - attribute \src "ls180.v:1213.5-1213.49" - process $proc$ls180.v:1213$3268 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1214.5-1214.51" - process $proc$ls180.v:1214$3269 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1215.5-1215.52" - process $proc$ls180.v:1215$3270 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1216.11-1216.58" - process $proc$ls180.v:1216$3271 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1217.5-1217.53" - process $proc$ls180.v:1217$3272 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1218.5-1218.39" - process $proc$ls180.v:1218$3273 - assign { } { } - assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] - end - attribute \src "ls180.v:1219.5-1219.39" - process $proc$ls180.v:1219$3274 - assign { } { } - assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] - end - attribute \src "ls180.v:1220.5-1220.39" - process $proc$ls180.v:1220$3275 - assign { } { } - assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] - end - attribute \src "ls180.v:1221.5-1221.38" - process $proc$ls180.v:1221$3276 - assign { } { } - assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] - end - attribute \src "ls180.v:1222.11-1222.52" - process $proc$ls180.v:1222$3277 - assign { } { } - assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1223.5-1223.33" - process $proc$ls180.v:1223$3278 - assign { } { } - assign $1\main_sdphy_dataw_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] - end - attribute \src "ls180.v:1224.11-1224.40" - process $proc$ls180.v:1224$3279 - assign { } { } - assign $1\main_sdphy_dataw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] - end - attribute \src "ls180.v:1225.5-1225.50" - process $proc$ls180.v:1225$3280 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - sync init - end - attribute \src "ls180.v:1227.5-1227.50" - process $proc$ls180.v:1227$3281 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1228.5-1228.49" - process $proc$ls180.v:1228$3282 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1229.5-1229.56" - process $proc$ls180.v:1229$3283 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1230.5-1230.58" - process $proc$ls180.v:1230$3284 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1231.5-1231.58" - process $proc$ls180.v:1231$3285 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1232.5-1232.59" - process $proc$ls180.v:1232$3286 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1233.11-1233.65" - process $proc$ls180.v:1233$3287 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - sync init - end - attribute \src "ls180.v:1234.11-1234.65" - process $proc$ls180.v:1234$3288 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1235.5-1235.60" - process $proc$ls180.v:1235$3289 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1236.5-1236.34" - process $proc$ls180.v:1236$3290 - assign { } { } - assign $1\main_sdphy_dataw_start[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] - end - attribute \src "ls180.v:1237.5-1237.34" - process $proc$ls180.v:1237$3291 - assign { } { } - assign $1\main_sdphy_dataw_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] - end - attribute \src "ls180.v:1238.5-1238.34" - process $proc$ls180.v:1238$3292 - assign { } { } - assign $1\main_sdphy_dataw_error[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] - end - attribute \src "ls180.v:1240.5-1240.47" - process $proc$ls180.v:1240$3293 - assign { } { } - assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1251.5-1251.54" - process $proc$ls180.v:1251$3294 - assign { } { } - assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1256.5-1256.37" - process $proc$ls180.v:1256$3295 - assign { } { } - assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] - end - attribute \src "ls180.v:1259.5-1259.54" - process $proc$ls180.v:1259$3296 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1260.5-1260.53" - process $proc$ls180.v:1260$3297 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1264.5-1264.56" - process $proc$ls180.v:1264$3298 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - end - attribute \src "ls180.v:1265.5-1265.55" - process $proc$ls180.v:1265$3299 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - end - attribute \src "ls180.v:1266.11-1266.69" - process $proc$ls180.v:1266$3300 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1267.11-1267.82" - process $proc$ls180.v:1267$3301 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1268.11-1268.55" - process $proc$ls180.v:1268$3302 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] - end - attribute \src "ls180.v:127.12-127.74" - process $proc$ls180.v:127$2787 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - sync init - end - attribute \src "ls180.v:1270.5-1270.54" - process $proc$ls180.v:1270$3303 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1281.5-1281.50" - process $proc$ls180.v:1281$3304 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1283.5-1283.50" - process $proc$ls180.v:1283$3305 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - end - attribute \src "ls180.v:1284.5-1284.49" - process $proc$ls180.v:1284$3306 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - end - attribute \src "ls180.v:1285.11-1285.63" - process $proc$ls180.v:1285$3307 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1286.5-1286.39" - process $proc$ls180.v:1286$3308 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] - end - attribute \src "ls180.v:1289.5-1289.50" - process $proc$ls180.v:1289$3309 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1290.5-1290.49" - process $proc$ls180.v:1290$3310 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1291.5-1291.56" - process $proc$ls180.v:1291$3311 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1293.5-1293.58" - process $proc$ls180.v:1293$3312 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1294.5-1294.59" - process $proc$ls180.v:1294$3313 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1296.11-1296.65" - process $proc$ls180.v:1296$3314 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1297.5-1297.60" - process $proc$ls180.v:1297$3315 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1299.5-1299.49" - process $proc$ls180.v:1299$3316 - assign { } { } - assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1300.5-1300.51" - process $proc$ls180.v:1300$3317 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1301.5-1301.52" - process $proc$ls180.v:1301$3318 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1302.11-1302.58" - process $proc$ls180.v:1302$3319 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1303.5-1303.53" - process $proc$ls180.v:1303$3320 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1304.5-1304.39" - process $proc$ls180.v:1304$3321 - assign { } { } - assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] - end - attribute \src "ls180.v:1305.5-1305.39" - process $proc$ls180.v:1305$3322 - assign { } { } - assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] - end - attribute \src "ls180.v:1306.5-1306.38" - process $proc$ls180.v:1306$3323 - assign { } { } - assign $1\main_sdphy_datar_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] - end - attribute \src "ls180.v:1307.11-1307.61" - process $proc$ls180.v:1307$3324 - assign { } { } - assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] - end - attribute \src "ls180.v:1308.5-1308.41" - process $proc$ls180.v:1308$3325 - assign { } { } - assign $1\main_sdphy_datar_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] - end - attribute \src "ls180.v:1309.5-1309.41" - process $proc$ls180.v:1309$3326 - assign { } { } - assign $1\main_sdphy_datar_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] - end - attribute \src "ls180.v:131.5-131.72" - process $proc$ls180.v:131$2788 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1310.5-1310.41" - process $proc$ls180.v:1310$3327 - assign { } { } - assign $0\main_sdphy_datar_source_first[0:0] 1'0 - sync always - update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] - sync init - end - attribute \src "ls180.v:1311.5-1311.40" - process $proc$ls180.v:1311$3328 - assign { } { } - assign $1\main_sdphy_datar_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] - end - attribute \src "ls180.v:1312.11-1312.54" - process $proc$ls180.v:1312$3329 - assign { } { } - assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] - end - attribute \src "ls180.v:1313.11-1313.56" - process $proc$ls180.v:1313$3330 - assign { } { } - assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] - end - attribute \src "ls180.v:1314.5-1314.33" - process $proc$ls180.v:1314$3331 - assign { } { } - assign $1\main_sdphy_datar_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] - end - attribute \src "ls180.v:1315.12-1315.49" - process $proc$ls180.v:1315$3332 - assign { } { } - assign $1\main_sdphy_datar_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] - end - attribute \src "ls180.v:1316.11-1316.41" - process $proc$ls180.v:1316$3333 - assign { } { } - assign $1\main_sdphy_datar_count[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] - end - attribute \src "ls180.v:1318.5-1318.48" - process $proc$ls180.v:1318$3334 - assign { } { } - assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1329.5-1329.55" - process $proc$ls180.v:1329$3335 - assign { } { } - assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] - end - attribute \src "ls180.v:1334.5-1334.38" - process $proc$ls180.v:1334$3336 - assign { } { } - assign $1\main_sdphy_datar_datar_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] - end - attribute \src "ls180.v:1337.5-1337.55" - process $proc$ls180.v:1337$3337 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1338.5-1338.54" - process $proc$ls180.v:1338$3338 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1342.5-1342.57" - process $proc$ls180.v:1342$3339 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] - end - attribute \src "ls180.v:1343.5-1343.56" - process $proc$ls180.v:1343$3340 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] - end - attribute \src "ls180.v:1344.11-1344.70" - process $proc$ls180.v:1344$3341 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1345.11-1345.83" - process $proc$ls180.v:1345$3342 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - end - attribute \src "ls180.v:1346.5-1346.50" - process $proc$ls180.v:1346$3343 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] - end - attribute \src "ls180.v:1348.5-1348.55" - process $proc$ls180.v:1348$3344 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - end - attribute \src "ls180.v:135.5-135.69" - process $proc$ls180.v:135$2789 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end - attribute \src "ls180.v:1359.5-1359.51" - process $proc$ls180.v:1359$3345 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] - end - attribute \src "ls180.v:1361.5-1361.51" - process $proc$ls180.v:1361$3346 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] - end - attribute \src "ls180.v:1362.5-1362.50" - process $proc$ls180.v:1362$3347 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] - end - attribute \src "ls180.v:1363.11-1363.64" - process $proc$ls180.v:1363$3348 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1364.5-1364.40" - process $proc$ls180.v:1364$3349 - assign { } { } - assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] - end - attribute \src "ls180.v:1366.5-1366.35" - process $proc$ls180.v:1366$3350 - assign { } { } - assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 - sync always - sync init - update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] - end - attribute \src "ls180.v:1369.11-1369.42" - process $proc$ls180.v:1369$3351 - assign { } { } - assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 - sync always - sync init - update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:1382.12-1382.52" - process $proc$ls180.v:1382$3352 - assign { } { } - assign $1\main_sdcore_cmd_argument_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] - end - attribute \src "ls180.v:1383.5-1383.39" - process $proc$ls180.v:1383$3353 - assign { } { } - assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] - end - attribute \src "ls180.v:1384.12-1384.51" - process $proc$ls180.v:1384$3354 - assign { } { } - assign $1\main_sdcore_cmd_command_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] - end - attribute \src "ls180.v:1385.5-1385.38" - process $proc$ls180.v:1385$3355 - assign { } { } - assign $1\main_sdcore_cmd_command_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] - end - attribute \src "ls180.v:1389.5-1389.34" - process $proc$ls180.v:1389$3356 - assign { } { } - assign $0\main_sdcore_cmd_send_w[0:0] 1'0 - sync always - update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] - sync init - end - attribute \src "ls180.v:1390.13-1390.53" - process $proc$ls180.v:1390$3357 - assign { } { } - assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] - end - attribute \src "ls180.v:1396.11-1396.51" - process $proc$ls180.v:1396$3358 - assign { } { } - assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 - sync always - sync init - update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] - end - attribute \src "ls180.v:1397.5-1397.39" - process $proc$ls180.v:1397$3359 - assign { } { } - assign $1\main_sdcore_block_length_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] - end - attribute \src "ls180.v:1398.12-1398.51" - process $proc$ls180.v:1398$3360 - assign { } { } - assign $1\main_sdcore_block_count_storage[31:0] 0 - sync always - sync init - update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] - end - attribute \src "ls180.v:1399.5-1399.38" - process $proc$ls180.v:1399$3361 - assign { } { } - assign $1\main_sdcore_block_count_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] - end - attribute \src "ls180.v:1400.11-1400.51" - process $proc$ls180.v:1400$3362 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - end - attribute \src "ls180.v:141.5-141.74" - process $proc$ls180.v:141$2790 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] - sync init - end - attribute \src "ls180.v:143.12-143.78" - process $proc$ls180.v:143$2791 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end - attribute \src "ls180.v:1442.11-1442.47" - process $proc$ls180.v:1442$3363 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:1446.5-1446.49" - process $proc$ls180.v:1446$3364 - assign { } { } - assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] - end - attribute \src "ls180.v:1450.5-1450.51" - process $proc$ls180.v:1450$3365 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] - end - attribute \src "ls180.v:1451.5-1451.51" - process $proc$ls180.v:1451$3366 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] - end - attribute \src "ls180.v:1452.5-1452.51" - process $proc$ls180.v:1452$3367 - assign { } { } - assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] - sync init - end - attribute \src "ls180.v:1453.5-1453.50" - process $proc$ls180.v:1453$3368 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] - end - attribute \src "ls180.v:1454.11-1454.64" - process $proc$ls180.v:1454$3369 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - end - attribute \src "ls180.v:1455.11-1455.48" - process $proc$ls180.v:1455$3370 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] - end - attribute \src "ls180.v:1456.12-1456.59" - process $proc$ls180.v:1456$3371 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1460.12-1460.55" - process $proc$ls180.v:1460$3372 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:1463.12-1463.59" - process $proc$ls180.v:1463$3373 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1467.12-1467.55" - process $proc$ls180.v:1467$3374 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:1470.12-1470.59" - process $proc$ls180.v:1470$3375 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1474.12-1474.55" - process $proc$ls180.v:1474$3376 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:1477.12-1477.59" - process $proc$ls180.v:1477$3377 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1481.12-1481.55" - process $proc$ls180.v:1481$3378 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:1484.12-1484.54" - process $proc$ls180.v:1484$3379 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - end - attribute \src "ls180.v:1485.12-1485.54" - process $proc$ls180.v:1485$3380 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - end - attribute \src "ls180.v:1486.12-1486.54" - process $proc$ls180.v:1486$3381 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - end - attribute \src "ls180.v:1487.12-1487.54" - process $proc$ls180.v:1487$3382 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - end - attribute \src "ls180.v:1488.5-1488.48" - process $proc$ls180.v:1488$3383 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] - end - attribute \src "ls180.v:1489.5-1489.48" - process $proc$ls180.v:1489$3384 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:1490.5-1490.48" - process $proc$ls180.v:1490$3385 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] - end - attribute \src "ls180.v:1491.5-1491.47" - process $proc$ls180.v:1491$3386 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] - end - attribute \src "ls180.v:1492.11-1492.61" - process $proc$ls180.v:1492$3387 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - end - attribute \src "ls180.v:1493.5-1493.50" - process $proc$ls180.v:1493$3388 - assign { } { } - assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:1495.5-1495.50" - process $proc$ls180.v:1495$3389 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] - sync init - end - attribute \src "ls180.v:1498.11-1498.47" - process $proc$ls180.v:1498$3390 - assign { } { } - assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] - end - attribute \src "ls180.v:1499.11-1499.47" - process $proc$ls180.v:1499$3391 - assign { } { } - assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - sync always - sync init - update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] - end - attribute \src "ls180.v:1500.12-1500.58" - process $proc$ls180.v:1500$3392 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1504.12-1504.54" - process $proc$ls180.v:1504$3393 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:1505.5-1505.46" - process $proc$ls180.v:1505$3394 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:1507.12-1507.58" - process $proc$ls180.v:1507$3395 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1511.12-1511.54" - process $proc$ls180.v:1511$3396 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:1512.5-1512.46" - process $proc$ls180.v:1512$3397 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:1514.12-1514.58" - process $proc$ls180.v:1514$3398 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1518.12-1518.54" - process $proc$ls180.v:1518$3399 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:1519.5-1519.46" - process $proc$ls180.v:1519$3400 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:1521.12-1521.58" - process $proc$ls180.v:1521$3401 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1525.12-1525.54" - process $proc$ls180.v:1525$3402 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:1526.5-1526.46" - process $proc$ls180.v:1526$3403 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:1528.12-1528.53" - process $proc$ls180.v:1528$3404 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] - end - attribute \src "ls180.v:1529.12-1529.53" - process $proc$ls180.v:1529$3405 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] - end - attribute \src "ls180.v:1530.12-1530.53" - process $proc$ls180.v:1530$3406 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] - end - attribute \src "ls180.v:1531.12-1531.53" - process $proc$ls180.v:1531$3407 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] - end - attribute \src "ls180.v:1532.5-1532.43" - process $proc$ls180.v:1532$3408 - assign { } { } - assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:1533.12-1533.51" - process $proc$ls180.v:1533$3409 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] - end - attribute \src "ls180.v:1534.12-1534.51" - process $proc$ls180.v:1534$3410 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] - end - attribute \src "ls180.v:1535.12-1535.51" - process $proc$ls180.v:1535$3411 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] - end - attribute \src "ls180.v:1536.12-1536.51" - process $proc$ls180.v:1536$3412 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] - end - attribute \src "ls180.v:1538.11-1538.39" - process $proc$ls180.v:1538$3413 - assign { } { } - assign $1\main_sdcore_cmd_count[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] - end - attribute \src "ls180.v:1539.5-1539.32" - process $proc$ls180.v:1539$3414 - assign { } { } - assign $1\main_sdcore_cmd_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] - end - attribute \src "ls180.v:154.11-154.24" - process $proc$ls180.v:154$2792 - assign { } { } - assign $0\eint_1[2:0] 3'000 - sync always - update \eint_1 $0\eint_1[2:0] - sync init - end - attribute \src "ls180.v:1540.5-1540.33" - process $proc$ls180.v:1540$3415 - assign { } { } - assign $1\main_sdcore_cmd_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] - end - attribute \src "ls180.v:1541.5-1541.35" - process $proc$ls180.v:1541$3416 - assign { } { } - assign $1\main_sdcore_cmd_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] - end - attribute \src "ls180.v:1543.12-1543.42" - process $proc$ls180.v:1543$3417 - assign { } { } - assign $1\main_sdcore_data_count[31:0] 0 - sync always - sync init - update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] - end - attribute \src "ls180.v:1544.5-1544.33" - process $proc$ls180.v:1544$3418 - assign { } { } - assign $1\main_sdcore_data_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] - end - attribute \src "ls180.v:1545.5-1545.34" - process $proc$ls180.v:1545$3419 - assign { } { } - assign $1\main_sdcore_data_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] - end - attribute \src "ls180.v:1546.5-1546.36" - process $proc$ls180.v:1546$3420 - assign { } { } - assign $1\main_sdcore_data_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] - end - attribute \src "ls180.v:1555.11-1555.41" - process $proc$ls180.v:1555$3421 - assign { } { } - assign $0\main_interface0_bus_cti[2:0] 3'000 - sync always - update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1556.11-1556.41" - process $proc$ls180.v:1556$3422 - assign { } { } - assign $0\main_interface0_bus_bte[1:0] 2'00 - sync always - update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1579.11-1579.45" - process $proc$ls180.v:1579$3423 - assign { } { } - assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] - end - attribute \src "ls180.v:1580.5-1580.41" - process $proc$ls180.v:1580$3424 - assign { } { } - assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 - sync always - update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1581.11-1581.47" - process $proc$ls180.v:1581$3425 - assign { } { } - assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] - end - attribute \src "ls180.v:1582.11-1582.47" - process $proc$ls180.v:1582$3426 - assign { } { } - assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] - end - attribute \src "ls180.v:1583.11-1583.50" - process $proc$ls180.v:1583$3427 - assign { } { } - assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:159.5-159.74" - process $proc$ls180.v:159$2793 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] - sync init - end - attribute \src "ls180.v:160.12-160.71" - process $proc$ls180.v:160$2794 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1603.5-1603.51" - process $proc$ls180.v:1603$3428 - assign { } { } - assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] - end - attribute \src "ls180.v:1604.5-1604.50" - process $proc$ls180.v:1604$3429 - assign { } { } - assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] - end - attribute \src "ls180.v:1605.12-1605.66" - process $proc$ls180.v:1605$3430 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] - end - attribute \src "ls180.v:1606.11-1606.77" - process $proc$ls180.v:1606$3431 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - end - attribute \src "ls180.v:1607.11-1607.50" - process $proc$ls180.v:1607$3432 - assign { } { } - assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 - sync always - sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] - end - attribute \src "ls180.v:1609.5-1609.49" - process $proc$ls180.v:1609$3433 - assign { } { } - assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] - end - attribute \src "ls180.v:161.12-161.73" - process $proc$ls180.v:161$2795 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1615.5-1615.45" - process $proc$ls180.v:1615$3434 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] - end - attribute \src "ls180.v:1617.12-1617.62" - process $proc$ls180.v:1617$3435 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] - end - attribute \src "ls180.v:1618.12-1618.60" - process $proc$ls180.v:1618$3436 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] - end - attribute \src "ls180.v:1620.5-1620.57" - process $proc$ls180.v:1620$3437 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - end - attribute \src "ls180.v:1624.12-1624.67" - process $proc$ls180.v:1624$3438 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - end - attribute \src "ls180.v:1625.5-1625.54" - process $proc$ls180.v:1625$3439 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - end - attribute \src "ls180.v:1626.12-1626.69" - process $proc$ls180.v:1626$3440 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - end - attribute \src "ls180.v:1627.5-1627.56" - process $proc$ls180.v:1627$3441 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - end - attribute \src "ls180.v:1628.5-1628.61" - process $proc$ls180.v:1628$3442 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - end - attribute \src "ls180.v:1629.5-1629.56" - process $proc$ls180.v:1629$3443 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - end - attribute \src "ls180.v:163.11-163.69" - process $proc$ls180.v:163$2796 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1630.5-1630.53" - process $proc$ls180.v:1630$3444 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - end - attribute \src "ls180.v:1632.5-1632.59" - process $proc$ls180.v:1632$3445 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - end - attribute \src "ls180.v:1633.5-1633.54" - process $proc$ls180.v:1633$3446 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - end - attribute \src "ls180.v:1635.12-1635.61" - process $proc$ls180.v:1635$3447 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - end - attribute \src "ls180.v:1638.12-1638.43" - process $proc$ls180.v:1638$3448 - assign { } { } - assign $1\main_interface1_bus_adr[31:0] 0 - sync always - sync init - update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] - end - attribute \src "ls180.v:1639.12-1639.45" - process $proc$ls180.v:1639$3449 - assign { } { } - assign $0\main_interface1_bus_dat_w[31:0] 0 - sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] - sync init - end - attribute \src "ls180.v:164.5-164.63" - process $proc$ls180.v:164$2797 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1641.11-1641.41" - process $proc$ls180.v:1641$3450 - assign { } { } - assign $1\main_interface1_bus_sel[3:0] 4'0000 - sync always - sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] - end - attribute \src "ls180.v:1642.5-1642.35" - process $proc$ls180.v:1642$3451 - assign { } { } - assign $1\main_interface1_bus_cyc[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] - end - attribute \src "ls180.v:1643.5-1643.35" - process $proc$ls180.v:1643$3452 - assign { } { } - assign $1\main_interface1_bus_stb[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] - end - attribute \src "ls180.v:1645.5-1645.34" - process $proc$ls180.v:1645$3453 - assign { } { } - assign $1\main_interface1_bus_we[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] - end - attribute \src "ls180.v:1646.11-1646.41" - process $proc$ls180.v:1646$3454 - assign { } { } - assign $0\main_interface1_bus_cti[2:0] 3'000 - sync always - update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1647.11-1647.41" - process $proc$ls180.v:1647$3455 - assign { } { } - assign $0\main_interface1_bus_bte[1:0] 2'00 - sync always - update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:165.5-165.63" - process $proc$ls180.v:165$2798 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1654.5-1654.43" - process $proc$ls180.v:1654$3456 - assign { } { } - assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] - end - attribute \src "ls180.v:1655.5-1655.43" - process $proc$ls180.v:1655$3457 - assign { } { } - assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] - end - attribute \src "ls180.v:1656.5-1656.42" - process $proc$ls180.v:1656$3458 - assign { } { } - assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] - end - attribute \src "ls180.v:1657.12-1657.61" - process $proc$ls180.v:1657$3459 - assign { } { } - assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] - end - attribute \src "ls180.v:1658.5-1658.45" - process $proc$ls180.v:1658$3460 - assign { } { } - assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] - end - attribute \src "ls180.v:1660.5-1660.45" - process $proc$ls180.v:1660$3461 - assign { } { } - assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 - sync always - update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] - sync init - end - attribute \src "ls180.v:1661.5-1661.44" - process $proc$ls180.v:1661$3462 - assign { } { } - assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] - end - attribute \src "ls180.v:1662.12-1662.60" - process $proc$ls180.v:1662$3463 - assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] - end - attribute \src "ls180.v:1663.12-1663.45" - process $proc$ls180.v:1663$3464 - assign { } { } - assign $1\main_sdmem2block_dma_data[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] - end - attribute \src "ls180.v:1664.12-1664.53" - process $proc$ls180.v:1664$3465 - assign { } { } - assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] - end - attribute \src "ls180.v:1665.5-1665.40" - process $proc$ls180.v:1665$3466 - assign { } { } - assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] - end - attribute \src "ls180.v:1666.12-1666.55" - process $proc$ls180.v:1666$3467 - assign { } { } - assign $1\main_sdmem2block_dma_length_storage[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] - end - attribute \src "ls180.v:1667.5-1667.42" - process $proc$ls180.v:1667$3468 - assign { } { } - assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] - end - attribute \src "ls180.v:1668.5-1668.47" - process $proc$ls180.v:1668$3469 - assign { } { } - assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] - end - attribute \src "ls180.v:1669.5-1669.42" - process $proc$ls180.v:1669$3470 - assign { } { } - assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] - end - attribute \src "ls180.v:167.5-167.62" - process $proc$ls180.v:167$2799 - assign { } { } - assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] - end - attribute \src "ls180.v:1670.5-1670.44" - process $proc$ls180.v:1670$3471 - assign { } { } - assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] - end - attribute \src "ls180.v:1672.5-1672.45" - process $proc$ls180.v:1672$3472 - assign { } { } - assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] - end - attribute \src "ls180.v:1673.5-1673.40" - process $proc$ls180.v:1673$3473 - assign { } { } - assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] - end - attribute \src "ls180.v:1677.12-1677.47" - process $proc$ls180.v:1677$3474 - assign { } { } - assign $1\main_sdmem2block_dma_offset[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] - end - attribute \src "ls180.v:168.11-168.69" - process $proc$ls180.v:168$2800 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1689.11-1689.64" - process $proc$ls180.v:1689$3475 - assign { } { } - assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:169.11-169.69" - process $proc$ls180.v:169$2801 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1691.11-1691.48" - process $proc$ls180.v:1691$3476 - assign { } { } - assign $1\main_sdmem2block_converter_mux[1:0] 2'00 - sync always - sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] - end - attribute \src "ls180.v:171.5-171.44" - process $proc$ls180.v:171$2802 - assign { } { } - assign $1\main_libresocsim_converter0_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] - end - attribute \src "ls180.v:1715.11-1715.45" - process $proc$ls180.v:1715$3477 - assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] - end - attribute \src "ls180.v:1716.5-1716.41" - process $proc$ls180.v:1716$3478 - assign { } { } - assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 - sync always - update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1717.11-1717.47" - process $proc$ls180.v:1717$3479 - assign { } { } - assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] - end - attribute \src "ls180.v:1718.11-1718.47" - process $proc$ls180.v:1718$3480 - assign { } { } - assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] - end - attribute \src "ls180.v:1719.11-1719.50" - process $proc$ls180.v:1719$3481 - assign { } { } - assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:172.5-172.47" - process $proc$ls180.v:172$2803 - assign { } { } - assign $1\main_libresocsim_converter0_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] - end - attribute \src "ls180.v:1732.5-1732.36" - process $proc$ls180.v:1732$3482 - assign { } { } - assign $1\builder_converter0_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_state $1\builder_converter0_state[0:0] - end - attribute \src "ls180.v:1733.5-1733.41" - process $proc$ls180.v:1733$3483 - assign { } { } - assign $1\builder_converter0_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] - end - attribute \src "ls180.v:1734.5-1734.69" - process $proc$ls180.v:1734$3484 - assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] - end - attribute \src "ls180.v:1735.5-1735.72" - process $proc$ls180.v:1735$3485 - assign { } { } - assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:1736.5-1736.36" - process $proc$ls180.v:1736$3486 - assign { } { } - assign $1\builder_converter1_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_state $1\builder_converter1_state[0:0] - end - attribute \src "ls180.v:1737.5-1737.41" - process $proc$ls180.v:1737$3487 - assign { } { } - assign $1\builder_converter1_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] - end - attribute \src "ls180.v:1738.5-1738.69" - process $proc$ls180.v:1738$3488 - assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] - end - attribute \src "ls180.v:1739.5-1739.72" - process $proc$ls180.v:1739$3489 - assign { } { } - assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:174.12-174.53" - process $proc$ls180.v:174$2804 - assign { } { } - assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] - end - attribute \src "ls180.v:1740.5-1740.36" - process $proc$ls180.v:1740$3490 - assign { } { } - assign $1\builder_converter2_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_state $1\builder_converter2_state[0:0] - end - attribute \src "ls180.v:1741.5-1741.41" - process $proc$ls180.v:1741$3491 - assign { } { } - assign $1\builder_converter2_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] - end - attribute \src "ls180.v:1742.5-1742.69" - process $proc$ls180.v:1742$3492 - assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] - end - attribute \src "ls180.v:1743.5-1743.72" - process $proc$ls180.v:1743$3493 - assign { } { } - assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:1744.11-1744.41" - process $proc$ls180.v:1744$3494 - assign { } { } - assign $1\builder_refresher_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_state $1\builder_refresher_state[1:0] - end - attribute \src "ls180.v:1745.11-1745.46" - process $proc$ls180.v:1745$3495 - assign { } { } - assign $1\builder_refresher_next_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:1746.11-1746.44" - process $proc$ls180.v:1746$3496 - assign { } { } - assign $1\builder_bankmachine0_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] - end - attribute \src "ls180.v:1747.11-1747.49" - process $proc$ls180.v:1747$3497 - assign { } { } - assign $1\builder_bankmachine0_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:1748.11-1748.44" - process $proc$ls180.v:1748$3498 - assign { } { } - assign $1\builder_bankmachine1_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] - end - attribute \src "ls180.v:1749.11-1749.49" - process $proc$ls180.v:1749$3499 - assign { } { } - assign $1\builder_bankmachine1_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:175.12-175.71" - process $proc$ls180.v:175$2805 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1750.11-1750.44" - process $proc$ls180.v:1750$3500 - assign { } { } - assign $1\builder_bankmachine2_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] - end - attribute \src "ls180.v:1751.11-1751.49" - process $proc$ls180.v:1751$3501 - assign { } { } - assign $1\builder_bankmachine2_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:1752.11-1752.44" - process $proc$ls180.v:1752$3502 - assign { } { } - assign $1\builder_bankmachine3_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] - end - attribute \src "ls180.v:1753.11-1753.49" - process $proc$ls180.v:1753$3503 - assign { } { } - assign $1\builder_bankmachine3_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:1754.11-1754.43" - process $proc$ls180.v:1754$3504 - assign { } { } - assign $1\builder_multiplexer_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] - end - attribute \src "ls180.v:1755.11-1755.48" - process $proc$ls180.v:1755$3505 - assign { } { } - assign $1\builder_multiplexer_next_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:176.12-176.73" - process $proc$ls180.v:176$2806 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:1768.5-1768.27" - process $proc$ls180.v:1768$3506 - assign { } { } - assign $0\builder_locked0[0:0] 1'0 - sync always - update \builder_locked0 $0\builder_locked0[0:0] - sync init - end - attribute \src "ls180.v:1769.5-1769.27" - process $proc$ls180.v:1769$3507 - assign { } { } - assign $0\builder_locked1[0:0] 1'0 - sync always - update \builder_locked1 $0\builder_locked1[0:0] - sync init - end - attribute \src "ls180.v:1770.5-1770.27" - process $proc$ls180.v:1770$3508 - assign { } { } - assign $0\builder_locked2[0:0] 1'0 - sync always - update \builder_locked2 $0\builder_locked2[0:0] - sync init - end - attribute \src "ls180.v:1771.5-1771.27" - process $proc$ls180.v:1771$3509 - assign { } { } - assign $0\builder_locked3[0:0] 1'0 - sync always - update \builder_locked3 $0\builder_locked3[0:0] - sync init - end - attribute \src "ls180.v:1772.5-1772.42" - process $proc$ls180.v:1772$3510 - assign { } { } - assign $1\builder_new_master_wdata_ready[0:0] 1'0 - sync always - sync init - update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] - end - attribute \src "ls180.v:1773.5-1773.43" - process $proc$ls180.v:1773$3511 - assign { } { } - assign $1\builder_new_master_rdata_valid0[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] - end - attribute \src "ls180.v:1774.5-1774.43" - process $proc$ls180.v:1774$3512 - assign { } { } - assign $1\builder_new_master_rdata_valid1[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] - end - attribute \src "ls180.v:1775.5-1775.43" - process $proc$ls180.v:1775$3513 - assign { } { } - assign $1\builder_new_master_rdata_valid2[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] - end - attribute \src "ls180.v:1776.5-1776.43" - process $proc$ls180.v:1776$3514 - assign { } { } - assign $1\builder_new_master_rdata_valid3[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] - end - attribute \src "ls180.v:1777.5-1777.35" - process $proc$ls180.v:1777$3515 - assign { } { } - assign $1\builder_converter_state[0:0] 1'0 - sync always - sync init - update \builder_converter_state $1\builder_converter_state[0:0] - end - attribute \src "ls180.v:1778.5-1778.40" - process $proc$ls180.v:1778$3516 - assign { } { } - assign $1\builder_converter_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter_next_state $1\builder_converter_next_state[0:0] - end - attribute \src "ls180.v:1779.5-1779.55" - process $proc$ls180.v:1779$3517 - assign { } { } - assign $1\main_converter_counter_converter_next_value[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] - end - attribute \src "ls180.v:178.11-178.69" - process $proc$ls180.v:178$2807 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] - end - attribute \src "ls180.v:1780.5-1780.58" - process $proc$ls180.v:1780$3518 - assign { } { } - assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:1781.11-1781.42" - process $proc$ls180.v:1781$3519 - assign { } { } - assign $1\builder_spimaster0_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] - end - attribute \src "ls180.v:1782.11-1782.47" - process $proc$ls180.v:1782$3520 - assign { } { } - assign $1\builder_spimaster0_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] - end - attribute \src "ls180.v:1783.11-1783.62" - process $proc$ls180.v:1783$3521 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] - end - attribute \src "ls180.v:1784.5-1784.59" - process $proc$ls180.v:1784$3522 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:1785.11-1785.42" - process $proc$ls180.v:1785$3523 - assign { } { } - assign $1\builder_spimaster1_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] - end - attribute \src "ls180.v:1786.11-1786.47" - process $proc$ls180.v:1786$3524 - assign { } { } - assign $1\builder_spimaster1_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] - end - attribute \src "ls180.v:1787.11-1787.60" - process $proc$ls180.v:1787$3525 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] - end - attribute \src "ls180.v:1788.5-1788.57" - process $proc$ls180.v:1788$3526 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:1789.5-1789.41" - process $proc$ls180.v:1789$3527 - assign { } { } - assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] - end - attribute \src "ls180.v:179.5-179.63" - process $proc$ls180.v:179$2808 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1790.5-1790.46" - process $proc$ls180.v:1790$3528 - assign { } { } - assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] - end - attribute \src "ls180.v:1791.11-1791.66" - process $proc$ls180.v:1791$3529 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - end - attribute \src "ls180.v:1792.5-1792.63" - process $proc$ls180.v:1792$3530 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:1793.11-1793.47" - process $proc$ls180.v:1793$3531 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] - end - attribute \src "ls180.v:1794.11-1794.52" - process $proc$ls180.v:1794$3532 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] - end - attribute \src "ls180.v:1795.11-1795.66" - process $proc$ls180.v:1795$3533 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - end - attribute \src "ls180.v:1796.5-1796.63" - process $proc$ls180.v:1796$3534 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:1797.11-1797.47" - process $proc$ls180.v:1797$3535 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] - end - attribute \src "ls180.v:1798.11-1798.52" - process $proc$ls180.v:1798$3536 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] - end - attribute \src "ls180.v:1799.11-1799.67" - process $proc$ls180.v:1799$3537 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - end - attribute \src "ls180.v:180.5-180.63" - process $proc$ls180.v:180$2809 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] - end - attribute \src "ls180.v:1800.5-1800.64" - process $proc$ls180.v:1800$3538 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - end - attribute \src "ls180.v:1801.12-1801.71" - process $proc$ls180.v:1801$3539 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - end - attribute \src "ls180.v:1802.5-1802.66" - process $proc$ls180.v:1802$3540 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - end - attribute \src "ls180.v:1803.5-1803.66" - process $proc$ls180.v:1803$3541 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - end - attribute \src "ls180.v:1804.5-1804.69" - process $proc$ls180.v:1804$3542 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:1805.5-1805.41" - process $proc$ls180.v:1805$3543 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] - end - attribute \src "ls180.v:1806.5-1806.46" - process $proc$ls180.v:1806$3544 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] - end - attribute \src "ls180.v:1807.5-1807.66" - process $proc$ls180.v:1807$3545 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - end - attribute \src "ls180.v:1808.5-1808.69" - process $proc$ls180.v:1808$3546 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:1809.11-1809.41" - process $proc$ls180.v:1809$3547 - assign { } { } - assign $1\builder_sdphy_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] - end - attribute \src "ls180.v:1810.11-1810.46" - process $proc$ls180.v:1810$3548 - assign { } { } - assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] - end - attribute \src "ls180.v:1811.11-1811.61" - process $proc$ls180.v:1811$3549 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - end - attribute \src "ls180.v:1812.5-1812.58" - process $proc$ls180.v:1812$3550 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1813.11-1813.48" - process $proc$ls180.v:1813$3551 - assign { } { } - assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] - end - attribute \src "ls180.v:1814.11-1814.53" - process $proc$ls180.v:1814$3552 - assign { } { } - assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] - end - attribute \src "ls180.v:1815.11-1815.70" - process $proc$ls180.v:1815$3553 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - end - attribute \src "ls180.v:1816.5-1816.66" - process $proc$ls180.v:1816$3554 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - end - attribute \src "ls180.v:1817.12-1817.73" - process $proc$ls180.v:1817$3555 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - end - attribute \src "ls180.v:1818.5-1818.68" - process $proc$ls180.v:1818$3556 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - end - attribute \src "ls180.v:1819.5-1819.69" - process $proc$ls180.v:1819$3557 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - end - attribute \src "ls180.v:182.5-182.62" - process $proc$ls180.v:182$2810 - assign { } { } - assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] - end - attribute \src "ls180.v:1820.5-1820.72" - process $proc$ls180.v:1820$3558 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:1821.5-1821.52" - process $proc$ls180.v:1821$3559 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] - end - attribute \src "ls180.v:1822.5-1822.57" - process $proc$ls180.v:1822$3560 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - end - attribute \src "ls180.v:1823.12-1823.93" - process $proc$ls180.v:1823$3561 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - end - attribute \src "ls180.v:1824.5-1824.88" - process $proc$ls180.v:1824$3562 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - end - attribute \src "ls180.v:1825.12-1825.93" - process $proc$ls180.v:1825$3563 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - end - attribute \src "ls180.v:1826.5-1826.88" - process $proc$ls180.v:1826$3564 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - end - attribute \src "ls180.v:1827.12-1827.93" - process $proc$ls180.v:1827$3565 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - end - attribute \src "ls180.v:1828.5-1828.88" - process $proc$ls180.v:1828$3566 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - end - attribute \src "ls180.v:1829.12-1829.93" - process $proc$ls180.v:1829$3567 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - end - attribute \src "ls180.v:183.11-183.69" - process $proc$ls180.v:183$2811 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1830.5-1830.88" - process $proc$ls180.v:1830$3568 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - end - attribute \src "ls180.v:1831.11-1831.87" - process $proc$ls180.v:1831$3569 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - end - attribute \src "ls180.v:1832.5-1832.84" - process $proc$ls180.v:1832$3570 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:1833.11-1833.42" - process $proc$ls180.v:1833$3571 - assign { } { } - assign $1\builder_sdcore_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] - end - attribute \src "ls180.v:1834.11-1834.47" - process $proc$ls180.v:1834$3572 - assign { } { } - assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] - end - attribute \src "ls180.v:1835.5-1835.55" - process $proc$ls180.v:1835$3573 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - end - attribute \src "ls180.v:1836.5-1836.58" - process $proc$ls180.v:1836$3574 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - end - attribute \src "ls180.v:1837.5-1837.56" - process $proc$ls180.v:1837$3575 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - end - attribute \src "ls180.v:1838.5-1838.59" - process $proc$ls180.v:1838$3576 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - end - attribute \src "ls180.v:1839.11-1839.62" - process $proc$ls180.v:1839$3577 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - end - attribute \src "ls180.v:184.11-184.69" - process $proc$ls180.v:184$2812 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:1840.5-1840.59" - process $proc$ls180.v:1840$3578 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - end - attribute \src "ls180.v:1841.12-1841.65" - process $proc$ls180.v:1841$3579 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - end - attribute \src "ls180.v:1842.5-1842.60" - process $proc$ls180.v:1842$3580 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - end - attribute \src "ls180.v:1843.5-1843.56" - process $proc$ls180.v:1843$3581 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - end - attribute \src "ls180.v:1844.5-1844.59" - process $proc$ls180.v:1844$3582 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - end - attribute \src "ls180.v:1845.5-1845.58" - process $proc$ls180.v:1845$3583 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - end - attribute \src "ls180.v:1846.5-1846.61" - process $proc$ls180.v:1846$3584 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - end - attribute \src "ls180.v:1847.5-1847.57" - process $proc$ls180.v:1847$3585 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - end - attribute \src "ls180.v:1848.5-1848.60" - process $proc$ls180.v:1848$3586 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - end - attribute \src "ls180.v:1849.5-1849.59" - process $proc$ls180.v:1849$3587 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - end - attribute \src "ls180.v:1850.5-1850.62" - process $proc$ls180.v:1850$3588 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - end - attribute \src "ls180.v:1851.13-1851.76" - process $proc$ls180.v:1851$3589 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - end - attribute \src "ls180.v:1852.5-1852.69" - process $proc$ls180.v:1852$3590 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:1853.11-1853.46" - process $proc$ls180.v:1853$3591 - assign { } { } - assign $1\builder_sdblock2memdma_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] - end - attribute \src "ls180.v:1854.11-1854.51" - process $proc$ls180.v:1854$3592 - assign { } { } - assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] - end - attribute \src "ls180.v:1855.12-1855.87" - process $proc$ls180.v:1855$3593 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - end - attribute \src "ls180.v:1856.5-1856.82" - process $proc$ls180.v:1856$3594 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:1857.5-1857.44" - process $proc$ls180.v:1857$3595 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] - end - attribute \src "ls180.v:1858.5-1858.49" - process $proc$ls180.v:1858$3596 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] - end - attribute \src "ls180.v:1859.12-1859.75" - process $proc$ls180.v:1859$3597 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - end - attribute \src "ls180.v:186.5-186.44" - process $proc$ls180.v:186$2813 - assign { } { } - assign $1\main_libresocsim_converter1_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] - end - attribute \src "ls180.v:1860.5-1860.70" - process $proc$ls180.v:1860$3598 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1861.11-1861.60" - process $proc$ls180.v:1861$3599 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] - end - attribute \src "ls180.v:1862.11-1862.65" - process $proc$ls180.v:1862$3600 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - end - attribute \src "ls180.v:1863.12-1863.87" - process $proc$ls180.v:1863$3601 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - end - attribute \src "ls180.v:1864.5-1864.82" - process $proc$ls180.v:1864$3602 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:1865.12-1865.43" - process $proc$ls180.v:1865$3603 - assign { } { } - assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] - end - attribute \src "ls180.v:1866.5-1866.34" - process $proc$ls180.v:1866$3604 - assign { } { } - assign $1\builder_libresocsim_we[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] - end - attribute \src "ls180.v:1867.11-1867.43" - process $proc$ls180.v:1867$3605 - assign { } { } - assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] - end - attribute \src "ls180.v:187.5-187.47" - process $proc$ls180.v:187$2814 - assign { } { } - assign $1\main_libresocsim_converter1_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] - end - attribute \src "ls180.v:1871.12-1871.54" - process $proc$ls180.v:1871$3606 - assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 - sync always - sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] - end - attribute \src "ls180.v:1875.5-1875.44" - process $proc$ls180.v:1875$3607 - assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] - end - attribute \src "ls180.v:1879.5-1879.44" - process $proc$ls180.v:1879$3608 - assign { } { } - assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] - sync init - end - attribute \src "ls180.v:1882.12-1882.40" - process $proc$ls180.v:1882$3609 - assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 - sync always - sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] - end - attribute \src "ls180.v:1886.5-1886.30" - process $proc$ls180.v:1886$3610 - assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 - sync always - sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] - end - attribute \src "ls180.v:189.12-189.53" - process $proc$ls180.v:189$2815 - assign { } { } - assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] - end - attribute \src "ls180.v:1892.11-1892.31" - process $proc$ls180.v:1892$3611 - assign { } { } - assign $1\builder_grant[2:0] 3'000 - sync always - sync init - update \builder_grant $1\builder_grant[2:0] - end - attribute \src "ls180.v:1893.11-1893.35" - process $proc$ls180.v:1893$3612 - assign { } { } - assign $1\builder_slave_sel[4:0] 5'00000 - sync always - sync init - update \builder_slave_sel $1\builder_slave_sel[4:0] - end - attribute \src "ls180.v:1894.11-1894.37" - process $proc$ls180.v:1894$3613 - assign { } { } - assign $1\builder_slave_sel_r[4:0] 5'00000 - sync always - sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] - end - attribute \src "ls180.v:1895.5-1895.25" - process $proc$ls180.v:1895$3614 - assign { } { } - assign $1\builder_error[0:0] 1'0 - sync always - sync init - update \builder_error $1\builder_error[0:0] - end - attribute \src "ls180.v:1898.12-1898.39" - process $proc$ls180.v:1898$3615 - assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 - sync always - sync init - update \builder_count $1\builder_count[19:0] - end - attribute \src "ls180.v:190.12-190.71" - process $proc$ls180.v:190$2816 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] - end - attribute \src "ls180.v:1902.11-1902.51" - process $proc$ls180.v:1902$3616 - assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:191.12-191.73" - process $proc$ls180.v:191$2817 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:193.11-193.69" - process $proc$ls180.v:193$2818 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] - end - attribute \src "ls180.v:194.5-194.63" - process $proc$ls180.v:194$2819 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] - end - attribute \src "ls180.v:1943.11-1943.51" - process $proc$ls180.v:1943$3617 - assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:195.5-195.63" - process $proc$ls180.v:195$2820 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] - end - attribute \src "ls180.v:197.5-197.62" - process $proc$ls180.v:197$2821 - assign { } { } - assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] - end - attribute \src "ls180.v:1972.11-1972.51" - process $proc$ls180.v:1972$3618 - assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:198.11-198.69" - process $proc$ls180.v:198$2822 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 - sync always - update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] - sync init - end - attribute \src "ls180.v:1985.11-1985.51" - process $proc$ls180.v:1985$3619 - assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:199.11-199.69" - process $proc$ls180.v:199$2823 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 - sync always - update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] - sync init - end - attribute \src "ls180.v:201.5-201.44" - process $proc$ls180.v:201$2824 - assign { } { } - assign $1\main_libresocsim_converter2_skip[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] - end - attribute \src "ls180.v:202.5-202.47" - process $proc$ls180.v:202$2825 - assign { } { } - assign $1\main_libresocsim_converter2_counter[0:0] 1'0 - sync always - sync init - update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] - end - attribute \src "ls180.v:2026.11-2026.51" - process $proc$ls180.v:2026$3620 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:204.12-204.53" - process $proc$ls180.v:204$2826 - assign { } { } - assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] - end - attribute \src "ls180.v:2067.11-2067.51" - process $proc$ls180.v:2067$3621 - assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:211.5-211.40" - process $proc$ls180.v:211$2827 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:2132.11-2132.51" - process $proc$ls180.v:2132$3622 - assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:215.5-215.40" - process $proc$ls180.v:215$2828 - assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:218.11-218.37" - process $proc$ls180.v:218$2829 - assign { } { } - assign $1\main_libresocsim_we[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_we $1\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:220.12-220.49" - process $proc$ls180.v:220$2830 - assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] - end - attribute \src "ls180.v:221.5-221.36" - process $proc$ls180.v:221$2831 - assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] - end - attribute \src "ls180.v:222.12-222.51" - process $proc$ls180.v:222$2832 - assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] - end - attribute \src "ls180.v:223.5-223.38" - process $proc$ls180.v:223$2833 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:224.5-224.39" - process $proc$ls180.v:224$2834 - assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:225.5-225.34" - process $proc$ls180.v:225$2835 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:226.5-226.49" - process $proc$ls180.v:226$2836 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:2265.11-2265.51" - process $proc$ls180.v:2265$3623 - assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:227.5-227.44" - process $proc$ls180.v:227$2837 - assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] - end - attribute \src "ls180.v:228.12-228.49" - process $proc$ls180.v:228$2838 - assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 - sync always - sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] - end - attribute \src "ls180.v:232.5-232.41" - process $proc$ls180.v:232$2839 - assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] - end - attribute \src "ls180.v:234.5-234.39" - process $proc$ls180.v:234$2840 - assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:2346.11-2346.51" - process $proc$ls180.v:2346$3624 - assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:235.5-235.45" - process $proc$ls180.v:235$2841 - assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] - end - attribute \src "ls180.v:2363.11-2363.51" - process $proc$ls180.v:2363$3625 - assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2404.11-2404.52" - process $proc$ls180.v:2404$3626 - assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2437.11-2437.52" - process $proc$ls180.v:2437$3627 - assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:244.5-244.49" - process $proc$ls180.v:244$2842 - assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] - end - attribute \src "ls180.v:245.5-245.44" - process $proc$ls180.v:245$2843 - assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] - end - attribute \src "ls180.v:246.12-246.42" - process $proc$ls180.v:246$2844 - assign { } { } - assign $1\main_libresocsim_value[31:0] 0 - sync always - sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] - end - attribute \src "ls180.v:2478.11-2478.52" - process $proc$ls180.v:2478$3628 - assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:250.5-250.24" - process $proc$ls180.v:250$2845 - assign { } { } - assign $1\main_int_rst[0:0] 1'1 - sync always - sync init - update \main_int_rst $1\main_int_rst[0:0] - end - attribute \src "ls180.v:2543.11-2543.52" - process $proc$ls180.v:2543$3629 - assign { } { } - assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2568.11-2568.52" - process $proc$ls180.v:2568$3630 - assign { } { } - assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2590.11-2590.31" - process $proc$ls180.v:2590$3631 - assign { } { } - assign $1\builder_state[1:0] 2'00 - sync always - sync init - update \builder_state $1\builder_state[1:0] - end - attribute \src "ls180.v:2591.11-2591.36" - process $proc$ls180.v:2591$3632 - assign { } { } - assign $1\builder_next_state[1:0] 2'00 - sync always - sync init - update \builder_next_state $1\builder_next_state[1:0] - end - attribute \src "ls180.v:2592.11-2592.55" - process $proc$ls180.v:2592$3633 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] - end - attribute \src "ls180.v:2593.5-2593.52" - process $proc$ls180.v:2593$3634 - assign { } { } - assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - end - attribute \src "ls180.v:2594.12-2594.55" - process $proc$ls180.v:2594$3635 - assign { } { } - assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] - end - attribute \src "ls180.v:2595.5-2595.50" - process $proc$ls180.v:2595$3636 - assign { } { } - assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] - end - attribute \src "ls180.v:2596.5-2596.46" - process $proc$ls180.v:2596$3637 - assign { } { } - assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] - end - attribute \src "ls180.v:2597.5-2597.49" - process $proc$ls180.v:2597$3638 - assign { } { } - assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:2598.5-2598.41" - process $proc$ls180.v:2598$3639 - assign { } { } - assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:2599.12-2599.49" - process $proc$ls180.v:2599$3640 - assign { } { } - assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2600.11-2600.47" - process $proc$ls180.v:2600$3641 - assign { } { } - assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:2601.5-2601.41" - process $proc$ls180.v:2601$3642 - assign { } { } - assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2602.5-2602.41" - process $proc$ls180.v:2602$3643 - assign { } { } - assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2603.5-2603.41" - process $proc$ls180.v:2603$3644 - assign { } { } - assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2604.5-2604.39" - process $proc$ls180.v:2604$3645 - assign { } { } - assign $1\builder_comb_t_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:2605.5-2605.39" - process $proc$ls180.v:2605$3646 - assign { } { } - assign $1\builder_comb_t_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:2606.5-2606.39" - process $proc$ls180.v:2606$3647 - assign { } { } - assign $1\builder_comb_t_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:2607.5-2607.41" - process $proc$ls180.v:2607$3648 - assign { } { } - assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2608.12-2608.49" - process $proc$ls180.v:2608$3649 - assign { } { } - assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:2609.11-2609.47" - process $proc$ls180.v:2609$3650 - assign { } { } - assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:2610.5-2610.41" - process $proc$ls180.v:2610$3651 - assign { } { } - assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:2611.5-2611.42" - process $proc$ls180.v:2611$3652 - assign { } { } - assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:2612.5-2612.42" - process $proc$ls180.v:2612$3653 - assign { } { } - assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:2613.5-2613.39" - process $proc$ls180.v:2613$3654 - assign { } { } - assign $1\builder_comb_t_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:2614.5-2614.39" - process $proc$ls180.v:2614$3655 - assign { } { } - assign $1\builder_comb_t_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:2615.5-2615.39" - process $proc$ls180.v:2615$3656 - assign { } { } - assign $1\builder_comb_t_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:2616.12-2616.50" - process $proc$ls180.v:2616$3657 - assign { } { } - assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:2617.5-2617.42" - process $proc$ls180.v:2617$3658 - assign { } { } - assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:2618.5-2618.42" - process $proc$ls180.v:2618$3659 - assign { } { } - assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:2619.12-2619.50" - process $proc$ls180.v:2619$3660 - assign { } { } - assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:2620.5-2620.42" - process $proc$ls180.v:2620$3661 - assign { } { } - assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:2621.5-2621.42" - process $proc$ls180.v:2621$3662 - assign { } { } - assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:2622.12-2622.50" - process $proc$ls180.v:2622$3663 - assign { } { } - assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:2623.5-2623.42" - process $proc$ls180.v:2623$3664 - assign { } { } - assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:2624.5-2624.42" - process $proc$ls180.v:2624$3665 - assign { } { } - assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:2625.12-2625.50" - process $proc$ls180.v:2625$3666 - assign { } { } - assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - sync always - sync init - update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:2626.5-2626.42" - process $proc$ls180.v:2626$3667 - assign { } { } - assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:2627.5-2627.42" - process $proc$ls180.v:2627$3668 - assign { } { } - assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:2628.12-2628.50" - process $proc$ls180.v:2628$3669 - assign { } { } - assign $1\builder_comb_rhs_array_muxed24[31:0] 0 - sync always - sync init - update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:2629.12-2629.50" - process $proc$ls180.v:2629$3670 - assign { } { } - assign $1\builder_comb_rhs_array_muxed25[31:0] 0 - sync always - sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:2630.11-2630.48" - process $proc$ls180.v:2630$3671 - assign { } { } - assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 - sync always - sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] - end - attribute \src "ls180.v:2631.5-2631.42" - process $proc$ls180.v:2631$3672 - assign { } { } - assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:2632.5-2632.42" - process $proc$ls180.v:2632$3673 - assign { } { } - assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:2633.5-2633.42" - process $proc$ls180.v:2633$3674 - assign { } { } - assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 - sync always - sync init - update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:2634.11-2634.48" - process $proc$ls180.v:2634$3675 - assign { } { } - assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 - sync always - sync init - update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:2635.11-2635.48" - process $proc$ls180.v:2635$3676 - assign { } { } - assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 - sync always - sync init - update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:2636.11-2636.47" - process $proc$ls180.v:2636$3677 - assign { } { } - assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 - sync always - sync init - update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:2637.12-2637.49" - process $proc$ls180.v:2637$3678 - assign { } { } - assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - sync always - sync init - update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:2638.5-2638.41" - process $proc$ls180.v:2638$3679 - assign { } { } - assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:2639.5-2639.41" - process $proc$ls180.v:2639$3680 - assign { } { } - assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:2640.5-2640.41" - process $proc$ls180.v:2640$3681 - assign { } { } - assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:2641.5-2641.41" - process $proc$ls180.v:2641$3682 - assign { } { } - assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:2642.5-2642.41" - process $proc$ls180.v:2642$3683 - assign { } { } - assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 - sync always - sync init - update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:2643.5-2643.39" - process $proc$ls180.v:2643$3684 - assign { } { } - assign $1\builder_sync_f_array_muxed0[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:2644.5-2644.39" - process $proc$ls180.v:2644$3685 - assign { } { } - assign $1\builder_sync_f_array_muxed1[0:0] 1'0 - sync always - sync init - update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:265.12-265.38" - process $proc$ls180.v:265$2846 - assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] - end - attribute \src "ls180.v:266.5-266.36" - process $proc$ls180.v:266$2847 - assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:267.11-267.32" - process $proc$ls180.v:267$2848 - assign { } { } - assign $1\main_rddata_en[2:0] 3'000 - sync always - sync init - update \main_rddata_en $1\main_rddata_en[2:0] - end - attribute \src "ls180.v:270.5-270.36" - process $proc$ls180.v:270$2849 - assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] - end - attribute \src "ls180.v:2701.32-2701.66" - process $proc$ls180.v:2701$3686 - assign { } { } - assign $1\builder_multiregimpl0_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] - end - attribute \src "ls180.v:2702.32-2702.66" - process $proc$ls180.v:2702$3687 - assign { } { } - assign $1\builder_multiregimpl0_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] - end - attribute \src "ls180.v:2703.32-2703.66" - process $proc$ls180.v:2703$3688 - assign { } { } - assign $1\builder_multiregimpl1_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] - end - attribute \src "ls180.v:2704.32-2704.66" - process $proc$ls180.v:2704$3689 - assign { } { } - assign $1\builder_multiregimpl1_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] - end - attribute \src "ls180.v:2705.32-2705.66" - process $proc$ls180.v:2705$3690 - assign { } { } - assign $1\builder_multiregimpl2_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] - end - attribute \src "ls180.v:2706.32-2706.66" - process $proc$ls180.v:2706$3691 - assign { } { } - assign $1\builder_multiregimpl2_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] - end - attribute \src "ls180.v:2707.32-2707.66" - process $proc$ls180.v:2707$3692 - assign { } { } - assign $1\builder_multiregimpl3_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] - end - attribute \src "ls180.v:2708.32-2708.66" - process $proc$ls180.v:2708$3693 - assign { } { } - assign $1\builder_multiregimpl3_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] - end - attribute \src "ls180.v:2709.32-2709.66" - process $proc$ls180.v:2709$3694 - assign { } { } - assign $1\builder_multiregimpl4_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] - end - attribute \src "ls180.v:271.5-271.35" - process $proc$ls180.v:271$2850 - assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] - end - attribute \src "ls180.v:2710.32-2710.66" - process $proc$ls180.v:2710$3695 - assign { } { } - assign $1\builder_multiregimpl4_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] - end - attribute \src "ls180.v:2711.32-2711.66" - process $proc$ls180.v:2711$3696 - assign { } { } - assign $1\builder_multiregimpl5_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] - end - attribute \src "ls180.v:2712.32-2712.66" - process $proc$ls180.v:2712$3697 - assign { } { } - assign $1\builder_multiregimpl5_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] - end - attribute \src "ls180.v:2713.32-2713.66" - process $proc$ls180.v:2713$3698 - assign { } { } - assign $1\builder_multiregimpl6_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] - end - attribute \src "ls180.v:2714.32-2714.66" - process $proc$ls180.v:2714$3699 - assign { } { } - assign $1\builder_multiregimpl6_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] - end - attribute \src "ls180.v:2715.32-2715.66" - process $proc$ls180.v:2715$3700 - assign { } { } - assign $1\builder_multiregimpl7_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] - end - attribute \src "ls180.v:2716.32-2716.66" - process $proc$ls180.v:2716$3701 - assign { } { } - assign $1\builder_multiregimpl7_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] - end - attribute \src "ls180.v:2717.32-2717.66" - process $proc$ls180.v:2717$3702 - assign { } { } - assign $1\builder_multiregimpl8_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] - end - attribute \src "ls180.v:2718.32-2718.66" - process $proc$ls180.v:2718$3703 - assign { } { } - assign $1\builder_multiregimpl8_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] - end - attribute \src "ls180.v:2719.32-2719.66" - process $proc$ls180.v:2719$3704 - assign { } { } - assign $1\builder_multiregimpl9_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] - end - attribute \src "ls180.v:272.5-272.36" - process $proc$ls180.v:272$2851 - assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] - end - attribute \src "ls180.v:2720.32-2720.66" - process $proc$ls180.v:2720$3705 - assign { } { } - assign $1\builder_multiregimpl9_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] - end - attribute \src "ls180.v:2721.32-2721.67" - process $proc$ls180.v:2721$3706 - assign { } { } - assign $1\builder_multiregimpl10_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] - end - attribute \src "ls180.v:2722.32-2722.67" - process $proc$ls180.v:2722$3707 - assign { } { } - assign $1\builder_multiregimpl10_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] - end - attribute \src "ls180.v:2723.32-2723.67" - process $proc$ls180.v:2723$3708 - assign { } { } - assign $1\builder_multiregimpl11_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] - end - attribute \src "ls180.v:2724.32-2724.67" - process $proc$ls180.v:2724$3709 - assign { } { } - assign $1\builder_multiregimpl11_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] - end - attribute \src "ls180.v:2725.32-2725.67" - process $proc$ls180.v:2725$3710 - assign { } { } - assign $1\builder_multiregimpl12_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] - end - attribute \src "ls180.v:2726.32-2726.67" - process $proc$ls180.v:2726$3711 - assign { } { } - assign $1\builder_multiregimpl12_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] - end - attribute \src "ls180.v:2727.32-2727.67" - process $proc$ls180.v:2727$3712 - assign { } { } - assign $1\builder_multiregimpl13_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] - end - attribute \src "ls180.v:2728.32-2728.67" - process $proc$ls180.v:2728$3713 - assign { } { } - assign $1\builder_multiregimpl13_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] - end - attribute \src "ls180.v:2729.32-2729.67" - process $proc$ls180.v:2729$3714 - assign { } { } - assign $1\builder_multiregimpl14_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] - end - attribute \src "ls180.v:273.5-273.35" - process $proc$ls180.v:273$2852 - assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:2730.32-2730.67" - process $proc$ls180.v:2730$3715 - assign { } { } - assign $1\builder_multiregimpl14_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] - end - attribute \src "ls180.v:2731.32-2731.67" - process $proc$ls180.v:2731$3716 - assign { } { } - assign $1\builder_multiregimpl15_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] - end - attribute \src "ls180.v:2732.32-2732.67" - process $proc$ls180.v:2732$3717 - assign { } { } - assign $1\builder_multiregimpl15_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] - end - attribute \src "ls180.v:2733.32-2733.67" - process $proc$ls180.v:2733$3718 - assign { } { } - assign $1\builder_multiregimpl16_regs0[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] - end - attribute \src "ls180.v:2734.32-2734.67" - process $proc$ls180.v:2734$3719 - assign { } { } - assign $1\builder_multiregimpl16_regs1[0:0] 1'0 - sync always - sync init - update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] - end - attribute \src "ls180.v:2768.1-2773.4" - process $proc$ls180.v:2768$13 - assign { } { } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 - assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq - assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq - sync always - update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:277.5-277.36" - process $proc$ls180.v:277$2853 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:2775.1-2785.4" - process $proc$ls180.v:2775$15 - assign { } { } - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2777.2-2784.9" - switch \main_libresocsim_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:2787.1-2833.4" - process $proc$ls180.v:2787$16 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - assign $0\main_libresocsim_converter0_skip[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 - assign { } { } - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 - assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2799.2-2832.9" - switch \builder_converter0_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } - attribute \src "ls180.v:2802.4-2809.11" - switch \main_libresocsim_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] - case - end - attribute \src "ls180.v:2810.4-2823.7" - switch $and$ls180.v:2810$17_Y - attribute \src "ls180.v:2810.8-2810.81" - case 1'1 - assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2811$18_Y - assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we - assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2813$19_Y - assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2814$20_Y - attribute \src "ls180.v:2815.5-2822.8" - switch $or$ls180.v:2815$21_Y - attribute \src "ls180.v:2815.9-2815.97" - case 1'1 - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2816$22_Y - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2818.6-2821.9" - switch $eq$ls180.v:2818$23_Y - attribute \src "ls180.v:2818.10-2818.55" - case 1'1 - assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 - assign $0\builder_converter0_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2828.4-2830.7" - switch $and$ls180.v:2828$24_Y - attribute \src "ls180.v:2828.8-2828.81" - case 1'1 - assign $0\builder_converter0_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] - update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] - update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] - update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] - update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] - update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] - update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] - update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] - update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:282.12-282.45" - process $proc$ls180.v:282$2854 - assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] - end - attribute \src "ls180.v:283.5-283.43" - process $proc$ls180.v:283$2855 - assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:2835.1-2845.4" - process $proc$ls180.v:2835$26 - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2837.2-2844.9" - switch \main_libresocsim_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:2847.1-2893.4" - process $proc$ls180.v:2847$27 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 - assign { } { } - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_converter1_skip[0:0] 1'0 - assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2859.2-2892.9" - switch \builder_converter1_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } - attribute \src "ls180.v:2862.4-2869.11" - switch \main_libresocsim_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] - case - end - attribute \src "ls180.v:2870.4-2883.7" - switch $and$ls180.v:2870$28_Y - attribute \src "ls180.v:2870.8-2870.81" - case 1'1 - assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2871$29_Y - assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we - assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2873$30_Y - assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2874$31_Y - attribute \src "ls180.v:2875.5-2882.8" - switch $or$ls180.v:2875$32_Y - attribute \src "ls180.v:2875.9-2875.97" - case 1'1 - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2876$33_Y - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2878.6-2881.9" - switch $eq$ls180.v:2878$34_Y - attribute \src "ls180.v:2878.10-2878.55" - case 1'1 - assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 - assign $0\builder_converter1_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2888.4-2890.7" - switch $and$ls180.v:2888$35_Y - attribute \src "ls180.v:2888.8-2888.81" - case 1'1 - assign $0\builder_converter1_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] - update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] - update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] - update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] - update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] - update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] - update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] - update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] - update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:2895.1-2905.4" - process $proc$ls180.v:2895$37 - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 - attribute \src "ls180.v:2897.2-2904.9" - switch \main_libresocsim_converter2_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] - case - end - sync always - update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] - end - attribute \src "ls180.v:2907.1-2953.4" - process $proc$ls180.v:2907$38 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 - assign { } { } - assign $0\main_libresocsim_converter2_skip[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 - assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2919.2-2952.9" - switch \builder_converter2_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } - attribute \src "ls180.v:2922.4-2929.11" - switch \main_libresocsim_converter2_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] - case - end - attribute \src "ls180.v:2930.4-2943.7" - switch $and$ls180.v:2930$39_Y - attribute \src "ls180.v:2930.8-2930.87" - case 1'1 - assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2931$40_Y - assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we - assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2933$41_Y - assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2934$42_Y - attribute \src "ls180.v:2935.5-2942.8" - switch $or$ls180.v:2935$43_Y - attribute \src "ls180.v:2935.9-2935.97" - case 1'1 - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2936$44_Y - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2938.6-2941.9" - switch $eq$ls180.v:2938$45_Y - attribute \src "ls180.v:2938.10-2938.55" - case 1'1 - assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 - assign $0\builder_converter2_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2948.4-2950.7" - switch $and$ls180.v:2948$46_Y - attribute \src "ls180.v:2948.8-2948.87" - case 1'1 - assign $0\builder_converter2_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] - update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] - update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] - update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] - update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] - update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] - update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] - update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] - update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:2956.1-2962.4" - process $proc$ls180.v:2956$47 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2958$50_Y - assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2959$53_Y - assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2960$56_Y - assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2961$59_Y - sync always - update \main_libresocsim_we $0\main_libresocsim_we[3:0] - end - attribute \src "ls180.v:2968.1-2973.4" - process $proc$ls180.v:2968$61 - assign { } { } - assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:2970.2-2972.5" - switch $and$ls180.v:2970$62_Y - attribute \src "ls180.v:2970.6-2970.90" - case 1'1 - assign $0\main_libresocsim_zero_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:298.12-298.46" - process $proc$ls180.v:298$2856 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:299.5-299.44" - process $proc$ls180.v:299$2857 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:300.12-300.48" - process $proc$ls180.v:300$2858 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:301.11-301.43" - process $proc$ls180.v:301$2859 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:3012.1-3066.4" - process $proc$ls180.v:3012$64 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 - assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_master_p0_bank[1:0] 2'00 - assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_master_p0_we_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cke[0:0] 1'0 - assign $0\main_sdram_master_p0_odt[0:0] 1'0 - assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 - attribute \src "ls180.v:3031.2-3065.5" - switch \main_sdram_sel - attribute \src "ls180.v:3031.6-3031.20" - case 1'1 - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en - assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3048.6-3048.10" - case - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en - assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - end - sync always - update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] - update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] - update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] - update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] - update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] - update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] - update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] - update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] - update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] - update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] - update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] - update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] - update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] - update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] - update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] - update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] - update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] - update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:302.5-302.38" - process $proc$ls180.v:302$2860 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:303.5-303.37" - process $proc$ls180.v:303$2861 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:304.5-304.38" - process $proc$ls180.v:304$2862 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:305.5-305.37" - process $proc$ls180.v:305$2863 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:306.5-306.36" - process $proc$ls180.v:306$2864 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:307.5-307.36" - process $proc$ls180.v:307$2865 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:3070.1-3086.4" - process $proc$ls180.v:3070$65 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - attribute \src "ls180.v:3075.2-3085.5" - switch \main_sdram_command_issue_re - attribute \src "ls180.v:3075.6-3075.33" - case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3076$66_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3077$67_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3078$68_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3079$69_Y - attribute \src "ls180.v:3080.6-3080.10" - case - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - end - sync always - update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] - update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] - update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] - update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:308.5-308.40" - process $proc$ls180.v:308$2866 - assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] - end - attribute \src "ls180.v:309.5-309.38" - process $proc$ls180.v:309$2867 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:310.12-310.47" - process $proc$ls180.v:310$2868 - assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] - end - attribute \src "ls180.v:311.5-311.42" - process $proc$ls180.v:311$2869 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:312.11-312.50" - process $proc$ls180.v:312$2870 - assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] - end - attribute \src "ls180.v:3129.1-3159.4" - process $proc$ls180.v:3129$78 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign { } { } - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\main_sdram_cmd_last[0:0] 1'0 - assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3135.2-3158.9" - switch \builder_refresher_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3138.4-3141.7" - switch \main_sdram_cmd_ready - attribute \src "ls180.v:3138.8-3138.28" - case 1'1 - assign $0\main_sdram_sequencer_start0[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3145.4-3149.7" - switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3145.8-3145.34" - case 1'1 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\main_sdram_cmd_last[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3152.4-3156.7" - switch 1'1 - attribute \src "ls180.v:3152.8-3152.12" - case 1'1 - attribute \src "ls180.v:3153.5-3155.8" - switch \main_sdram_wants_refresh - attribute \src "ls180.v:3153.9-3153.33" - case 1'1 - assign $0\builder_refresher_next_state[1:0] 2'01 - case - end - case - end - end - sync always - update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] - update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] - update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] - update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:313.5-313.42" - process $proc$ls180.v:313$2871 - assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:3174.1-3181.4" - process $proc$ls180.v:3174$82 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3176.2-3180.5" - switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3176.6-3176.48" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3178.6-3178.10" - case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3179$84_Y - end - sync always - update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3185.1-3192.4" - process $proc$ls180.v:3185$91 - assign { } { } - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3187.2-3191.5" - switch $and$ls180.v:3187$92_Y - attribute \src "ls180.v:3187.6-3187.115" - case 1'1 - attribute \src "ls180.v:3188.3-3190.6" - switch $ne$ls180.v:3188$93_Y - attribute \src "ls180.v:3188.7-3188.143" - case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3189$94_Y - case - end - case - end - sync always - update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:320.11-320.36" - process $proc$ls180.v:320$2872 - assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:3207.1-3214.4" - process $proc$ls180.v:3207$95 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3209.2-3213.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3209.6-3209.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3210$96_Y - attribute \src "ls180.v:3211.6-3211.10" - case - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:321.5-321.25" - process $proc$ls180.v:321$2873 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:322.11-322.44" - process $proc$ls180.v:322$2874 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] - end - attribute \src "ls180.v:3223.1-3316.4" - process $proc$ls180.v:3223$104 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3239.2-3315.9" - switch \builder_bankmachine0_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3241.4-3249.7" - switch $and$ls180.v:3241$105_Y - attribute \src "ls180.v:3241.8-3241.87" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3243.5-3245.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3243.9-3243.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3253.4-3255.7" - switch $and$ls180.v:3253$106_Y - attribute \src "ls180.v:3253.8-3253.87" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3259.4-3268.7" - switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3259.8-3259.44" - case 1'1 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3264.5-3266.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3264.9-3264.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3271.4-3273.7" - switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3271.8-3271.45" - case 1'1 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3276.4-3278.7" - switch $not$ls180.v:3276$107_Y - attribute \src "ls180.v:3276.8-3276.46" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3287.4-3313.7" - switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3287.8-3287.43" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3289.8-3289.12" - case - attribute \src "ls180.v:3290.5-3312.8" - switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3290.9-3290.56" - case 1'1 - attribute \src "ls180.v:3291.6-3311.9" - switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3291.10-3291.44" - case 1'1 - attribute \src "ls180.v:3292.7-3308.10" - switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3292.11-3292.42" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3294.8-3301.11" - switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3294.12-3294.64" - case 1'1 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3298.12-3298.16" - case - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3303.8-3305.11" - switch $and$ls180.v:3303$108_Y - attribute \src "ls180.v:3303.12-3303.88" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3306.11-3306.15" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3309.10-3309.14" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] - update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] - update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] - update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] - update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:323.5-323.33" - process $proc$ls180.v:323$2875 - assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 - sync always - sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:327.5-327.38" - process $proc$ls180.v:327$2876 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:328.12-328.46" - process $proc$ls180.v:328$2877 - assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:329.5-329.33" - process $proc$ls180.v:329$2878 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:330.11-330.45" - process $proc$ls180.v:330$2879 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:331.5-331.34" - process $proc$ls180.v:331$2880 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 - sync always - sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] - end - attribute \src "ls180.v:332.12-332.45" - process $proc$ls180.v:332$2881 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:333.5-333.32" - process $proc$ls180.v:333$2882 - assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 - sync always - sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] - end - attribute \src "ls180.v:3331.1-3338.4" - process $proc$ls180.v:3331$112 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3333.2-3337.5" - switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3333.6-3333.48" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3335.6-3335.10" - case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3336$114_Y - end - sync always - update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:334.12-334.37" - process $proc$ls180.v:334$2883 - assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_status $1\main_sdram_status[15:0] - end - attribute \src "ls180.v:3342.1-3349.4" - process $proc$ls180.v:3342$121 - assign { } { } - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3344.2-3348.5" - switch $and$ls180.v:3344$122_Y - attribute \src "ls180.v:3344.6-3344.115" - case 1'1 - attribute \src "ls180.v:3345.3-3347.6" - switch $ne$ls180.v:3345$123_Y - attribute \src "ls180.v:3345.7-3345.143" - case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3346$124_Y - case - end - case - end - sync always - update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:3364.1-3371.4" - process $proc$ls180.v:3364$125 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3366.2-3370.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3366.6-3366.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3367$126_Y - attribute \src "ls180.v:3368.6-3368.10" - case - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3380.1-3473.4" - process $proc$ls180.v:3380$134 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3396.2-3472.9" - switch \builder_bankmachine1_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3398.4-3406.7" - switch $and$ls180.v:3398$135_Y - attribute \src "ls180.v:3398.8-3398.87" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3400.5-3402.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3400.9-3400.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3410.4-3412.7" - switch $and$ls180.v:3410$136_Y - attribute \src "ls180.v:3410.8-3410.87" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3416.4-3425.7" - switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3416.8-3416.44" - case 1'1 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3421.5-3423.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3421.9-3421.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3428.4-3430.7" - switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3428.8-3428.45" - case 1'1 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3433.4-3435.7" - switch $not$ls180.v:3433$137_Y - attribute \src "ls180.v:3433.8-3433.46" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3444.4-3470.7" - switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3444.8-3444.43" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3446.8-3446.12" - case - attribute \src "ls180.v:3447.5-3469.8" - switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3447.9-3447.56" - case 1'1 - attribute \src "ls180.v:3448.6-3468.9" - switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3448.10-3448.44" - case 1'1 - attribute \src "ls180.v:3449.7-3465.10" - switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3449.11-3449.42" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3451.8-3458.11" - switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3451.12-3451.64" - case 1'1 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3455.12-3455.16" - case - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3460.8-3462.11" - switch $and$ls180.v:3460$138_Y - attribute \src "ls180.v:3460.12-3460.88" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3463.11-3463.15" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3466.10-3466.14" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] - update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] - update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] - update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] - update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:3488.1-3495.4" - process $proc$ls180.v:3488$142 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3490.2-3494.5" - switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3490.6-3490.48" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3492.6-3492.10" - case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3493$144_Y - end - sync always - update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3499.1-3506.4" - process $proc$ls180.v:3499$151 - assign { } { } - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3501.2-3505.5" - switch $and$ls180.v:3501$152_Y - attribute \src "ls180.v:3501.6-3501.115" - case 1'1 - attribute \src "ls180.v:3502.3-3504.6" - switch $ne$ls180.v:3502$153_Y - attribute \src "ls180.v:3502.7-3502.143" - case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3503$154_Y - case - end - case - end - sync always - update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:3521.1-3528.4" - process $proc$ls180.v:3521$155 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3523.2-3527.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3523.6-3523.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3524$156_Y - attribute \src "ls180.v:3525.6-3525.10" - case - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3537.1-3630.4" - process $proc$ls180.v:3537$164 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3553.2-3629.9" - switch \builder_bankmachine2_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3555.4-3563.7" - switch $and$ls180.v:3555$165_Y - attribute \src "ls180.v:3555.8-3555.87" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3557.5-3559.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3557.9-3557.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3567.4-3569.7" - switch $and$ls180.v:3567$166_Y - attribute \src "ls180.v:3567.8-3567.87" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3573.4-3582.7" - switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3573.8-3573.44" - case 1'1 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3578.5-3580.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3578.9-3578.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3585.4-3587.7" - switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3585.8-3585.45" - case 1'1 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3590.4-3592.7" - switch $not$ls180.v:3590$167_Y - attribute \src "ls180.v:3590.8-3590.46" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3601.4-3627.7" - switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3601.8-3601.43" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3603.8-3603.12" - case - attribute \src "ls180.v:3604.5-3626.8" - switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3604.9-3604.56" - case 1'1 - attribute \src "ls180.v:3605.6-3625.9" - switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3605.10-3605.44" - case 1'1 - attribute \src "ls180.v:3606.7-3622.10" - switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3606.11-3606.42" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3608.8-3615.11" - switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3608.12-3608.64" - case 1'1 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3612.12-3612.16" - case - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3617.8-3619.11" - switch $and$ls180.v:3617$168_Y - attribute \src "ls180.v:3617.12-3617.88" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3620.11-3620.15" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3623.10-3623.14" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] - update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] - update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] - update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] - update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:364.12-364.46" - process $proc$ls180.v:364$2884 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:3645.1-3652.4" - process $proc$ls180.v:3645$172 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3647.2-3651.5" - switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3647.6-3647.48" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3649.6-3649.10" - case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3650$174_Y - end - sync always - update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:365.11-365.47" - process $proc$ls180.v:365$2885 - assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:3656.1-3663.4" - process $proc$ls180.v:3656$181 - assign { } { } - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3658.2-3662.5" - switch $and$ls180.v:3658$182_Y - attribute \src "ls180.v:3658.6-3658.115" - case 1'1 - attribute \src "ls180.v:3659.3-3661.6" - switch $ne$ls180.v:3659$183_Y - attribute \src "ls180.v:3659.7-3659.143" - case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3660$184_Y - case - end - case - end - sync always - update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:367.12-367.45" - process $proc$ls180.v:367$2886 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:3678.1-3685.4" - process $proc$ls180.v:3678$185 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3680.2-3684.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3680.6-3680.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3681$186_Y - attribute \src "ls180.v:3682.6-3682.10" - case - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:368.11-368.40" - process $proc$ls180.v:368$2887 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:369.5-369.35" - process $proc$ls180.v:369$2888 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:3694.1-3787.4" - process $proc$ls180.v:3694$194 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3710.2-3786.9" - switch \builder_bankmachine3_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3712.4-3720.7" - switch $and$ls180.v:3712$195_Y - attribute \src "ls180.v:3712.8-3712.87" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3714.5-3716.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3714.9-3714.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3724.4-3726.7" - switch $and$ls180.v:3724$196_Y - attribute \src "ls180.v:3724.8-3724.87" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3730.4-3739.7" - switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3730.8-3730.44" - case 1'1 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3735.5-3737.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3735.9-3735.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3742.4-3744.7" - switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3742.8-3742.45" - case 1'1 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3747.4-3749.7" - switch $not$ls180.v:3747$197_Y - attribute \src "ls180.v:3747.8-3747.46" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3758.4-3784.7" - switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3758.8-3758.43" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3760.8-3760.12" - case - attribute \src "ls180.v:3761.5-3783.8" - switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3761.9-3761.56" - case 1'1 - attribute \src "ls180.v:3762.6-3782.9" - switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3762.10-3762.44" - case 1'1 - attribute \src "ls180.v:3763.7-3779.10" - switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3763.11-3763.42" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3765.8-3772.11" - switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3765.12-3765.64" - case 1'1 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3769.12-3769.16" - case - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3774.8-3776.11" - switch $and$ls180.v:3774$198_Y - attribute \src "ls180.v:3774.12-3774.88" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3777.11-3777.15" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3780.10-3780.14" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] - update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] - update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] - update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] - update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:370.5-370.34" - process $proc$ls180.v:370$2889 - assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:371.5-371.35" - process $proc$ls180.v:371$2890 - assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:372.5-372.34" - process $proc$ls180.v:372$2891 - assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:376.5-376.35" - process $proc$ls180.v:376$2892 - assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:378.5-378.39" - process $proc$ls180.v:378$2893 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:380.5-380.39" - process $proc$ls180.v:380$2894 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:3807.1-3813.4" - process $proc$ls180.v:3807$237 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3809$250_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3810$263_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3811$276_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3812$289_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:3821.1-3826.4" - process $proc$ls180.v:3821$290 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3823.2-3825.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3823.6-3823.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3827.1-3832.4" - process $proc$ls180.v:3827$291 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3829.2-3831.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3829.6-3829.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:383.5-383.32" - process $proc$ls180.v:383$2895 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:3833.1-3838.4" - process $proc$ls180.v:3833$292 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3835.2-3837.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3835.6-3835.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:384.5-384.32" - process $proc$ls180.v:384$2896 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:3840.1-3846.4" - process $proc$ls180.v:3840$295 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3842$308_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3843$321_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3844$334_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3845$347_Y - sync always - update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:385.5-385.31" - process $proc$ls180.v:385$2897 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:3854.1-3859.4" - process $proc$ls180.v:3854$348 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3856.2-3858.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3856.6-3856.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:386.12-386.44" - process $proc$ls180.v:386$2898 - assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3860.1-3865.4" - process $proc$ls180.v:3860$349 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3862.2-3864.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3862.6-3862.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3866.1-3871.4" - process $proc$ls180.v:3866$350 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3868.2-3870.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3868.6-3868.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:387.11-387.43" - process $proc$ls180.v:387$2899 - assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 - sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] - end - attribute \src "ls180.v:3872.1-3880.4" - process $proc$ls180.v:3872$351 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3874.2-3876.5" - switch $and$ls180.v:3874$354_Y - attribute \src "ls180.v:3874.6-3874.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3877.2-3879.5" - switch $and$ls180.v:3877$357_Y - attribute \src "ls180.v:3877.6-3877.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:388.5-388.38" - process $proc$ls180.v:388$2900 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3881.1-3889.4" - process $proc$ls180.v:3881$358 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3883.2-3885.5" - switch $and$ls180.v:3883$361_Y - attribute \src "ls180.v:3883.6-3883.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3886.2-3888.5" - switch $and$ls180.v:3886$364_Y - attribute \src "ls180.v:3886.6-3886.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:389.5-389.38" - process $proc$ls180.v:389$2901 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3890.1-3898.4" - process $proc$ls180.v:3890$365 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3892.2-3894.5" - switch $and$ls180.v:3892$368_Y - attribute \src "ls180.v:3892.6-3892.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3895.2-3897.5" - switch $and$ls180.v:3895$371_Y - attribute \src "ls180.v:3895.6-3895.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:3899.1-3907.4" - process $proc$ls180.v:3899$372 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3901.2-3903.5" - switch $and$ls180.v:3901$375_Y - attribute \src "ls180.v:3901.6-3901.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3904.2-3906.5" - switch $and$ls180.v:3904$378_Y - attribute \src "ls180.v:3904.6-3904.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:390.5-390.37" - process $proc$ls180.v:390$2902 - assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:391.5-391.42" - process $proc$ls180.v:391$2903 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:3912.1-3984.4" - process $proc$ls180.v:3912$381 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_en0[0:0] 1'0 - assign { } { } - assign $0\main_sdram_en1[0:0] 1'0 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign $0\main_sdram_cmd_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed - assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3924.2-3983.9" - switch \builder_multiplexer_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_en1[0:0] 1'1 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3928.4-3934.7" - switch 1'1 - attribute \src "ls180.v:3928.8-3928.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3929$388_Y - case - end - attribute \src "ls180.v:3936.4-3940.7" - switch \main_sdram_read_available - attribute \src "ls180.v:3936.8-3936.33" - case 1'1 - attribute \src "ls180.v:3937.5-3939.8" - switch $or$ls180.v:3937$390_Y - attribute \src "ls180.v:3937.9-3937.63" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'011 - case - end - case - end - attribute \src "ls180.v:3941.4-3943.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3941.8-3941.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_steerer_sel[1:0] 2'11 - assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:3948.4-3950.7" - switch \main_sdram_cmd_last - attribute \src "ls180.v:3948.8-3948.27" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3953.4-3955.7" - switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:3953.8-3953.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_multiplexer_next_state[2:0] 3'101 - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_multiplexer_next_state[2:0] 3'001 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_en0[0:0] 1'1 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3966.4-3972.7" - switch 1'1 - attribute \src "ls180.v:3966.8-3966.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3967$397_Y - case - end - attribute \src "ls180.v:3974.4-3978.7" - switch \main_sdram_write_available - attribute \src "ls180.v:3974.8-3974.34" - case 1'1 - attribute \src "ls180.v:3975.5-3977.8" - switch $or$ls180.v:3975$399_Y - attribute \src "ls180.v:3975.9-3975.62" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'100 - case - end - case - end - attribute \src "ls180.v:3979.4-3981.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3979.8-3979.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - end - sync always - update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] - update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] - update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] - update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] - update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] - update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] - update \main_sdram_en0 $0\main_sdram_en0[0:0] - update \main_sdram_en1 $0\main_sdram_en1[0:0] - update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:392.5-392.43" - process $proc$ls180.v:392$2904 - assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] - sync init - end - attribute \src "ls180.v:398.11-398.44" - process $proc$ls180.v:398$2905 - assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 - sync always - sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] - end - attribute \src "ls180.v:400.5-400.38" - process $proc$ls180.v:400$2906 - assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] - end - attribute \src "ls180.v:4008.1-4021.4" - process $proc$ls180.v:4008$528 - assign { } { } - assign { } { } - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - attribute \src "ls180.v:4011.2-4020.9" - switch \builder_new_master_wdata_ready - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data - assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - end - sync always - update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] - update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:401.5-401.38" - process $proc$ls180.v:401$2907 - assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] - end - attribute \src "ls180.v:402.5-402.39" - process $proc$ls180.v:402$2908 - assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] - end - attribute \src "ls180.v:4028.1-4038.4" - process $proc$ls180.v:4028$530 - assign { } { } - assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4030.2-4037.9" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] - case - end - sync always - update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:4040.1-4086.4" - process $proc$ls180.v:4040$531 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter_skip[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign $0\main_litedram_wb_cyc[0:0] 1'0 - assign { } { } - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_litedram_wb_we[0:0] 1'0 - assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4052.2-4085.9" - switch \builder_converter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4055.4-4062.11" - switch \main_converter_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] - case - end - attribute \src "ls180.v:4063.4-4076.7" - switch $and$ls180.v:4063$532_Y - attribute \src "ls180.v:4063.8-4063.47" - case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4064$533_Y - assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4066$534_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4067$535_Y - attribute \src "ls180.v:4068.5-4075.8" - switch $or$ls180.v:4068$536_Y - attribute \src "ls180.v:4068.9-4068.53" - case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4069$537_Y - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4071.6-4074.9" - switch $eq$ls180.v:4071$538_Y - attribute \src "ls180.v:4071.10-4071.42" - case 1'1 - assign $0\main_wb_sdram_ack[0:0] 1'1 - assign $0\builder_converter_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4081.4-4083.7" - switch $and$ls180.v:4081$539_Y - attribute \src "ls180.v:4081.8-4081.47" - case 1'1 - assign $0\builder_converter_next_state[0:0] 1'1 - case - end - end - sync always - update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] - update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] - update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] - update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] - update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] - update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] - update \main_converter_skip $0\main_converter_skip[0:0] - update \builder_converter_next_state $0\builder_converter_next_state[0:0] - update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] - update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:405.5-405.38" - process $proc$ls180.v:405$2909 - assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] - end - attribute \src "ls180.v:406.11-406.46" - process $proc$ls180.v:406$2910 - assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 - sync always - sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] - end - attribute \src "ls180.v:407.5-407.38" - process $proc$ls180.v:407$2911 - assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] - end - attribute \src "ls180.v:413.5-413.51" - process $proc$ls180.v:413$2912 - assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - end - attribute \src "ls180.v:4131.1-4136.4" - process $proc$ls180.v:4131$571 - assign { } { } - assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4133.2-4135.5" - switch $and$ls180.v:4133$572_Y - attribute \src "ls180.v:4133.6-4133.79" - case 1'1 - assign $0\main_uart_tx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] - end - attribute \src "ls180.v:4137.1-4141.4" - process $proc$ls180.v:4137$573 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status - assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status - sync always - update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:414.5-414.51" - process $proc$ls180.v:414$2913 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - end - attribute \src "ls180.v:4142.1-4147.4" - process $proc$ls180.v:4142$574 - assign { } { } - assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4144.2-4146.5" - switch $and$ls180.v:4144$575_Y - attribute \src "ls180.v:4144.6-4144.79" - case 1'1 - assign $0\main_uart_rx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] - end - attribute \src "ls180.v:4148.1-4152.4" - process $proc$ls180.v:4148$576 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending - assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending - sync always - update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:416.5-416.47" - process $proc$ls180.v:416$2914 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:417.5-417.45" - process $proc$ls180.v:417$2915 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] - end - attribute \src "ls180.v:4170.1-4177.4" - process $proc$ls180.v:4170$584 - assign { } { } - assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4172.2-4176.5" - switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4172.6-4172.31" - case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4173$585_Y - attribute \src "ls180.v:4174.6-4174.10" - case - assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce - end - sync always - update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:418.5-418.45" - process $proc$ls180.v:418$2916 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:419.12-419.57" - process $proc$ls180.v:419$2917 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:4200.1-4207.4" - process $proc$ls180.v:4200$595 - assign { } { } - assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4202.2-4206.5" - switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4202.6-4202.31" - case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4203$596_Y - attribute \src "ls180.v:4204.6-4204.10" - case - assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce - end - sync always - update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:421.5-421.51" - process $proc$ls180.v:421$2918 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:422.5-422.51" - process $proc$ls180.v:422$2919 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:423.5-423.50" - process $proc$ls180.v:423$2920 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:4230.1-4278.4" - process $proc$ls180.v:4230$606 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_spimaster25_clk_enable[0:0] 1'0 - assign $0\main_spimaster26_cs_enable[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'0 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster29_miso_latch[0:0] 1'0 - assign $0\main_spimaster3_irq[0:0] 1'0 - assign { } { } - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4241.2-4277.9" - switch \builder_spimaster0_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4245.4-4248.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4245.8-4245.33" - case 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spimaster25_clk_enable[0:0] 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4253.4-4259.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4253.8-4253.33" - case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4254$607_Y - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4256.5-4258.8" - switch $eq$ls180.v:4256$609_Y - attribute \src "ls180.v:4256.9-4256.68" - case 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4263.4-4267.7" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4263.8-4263.33" - case 1'1 - assign $0\main_spimaster29_miso_latch[0:0] 1'1 - assign $0\main_spimaster3_irq[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4271.4-4275.7" - switch \main_spimaster0_start - attribute \src "ls180.v:4271.8-4271.29" - case 1'1 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'01 - case - end - end - sync always - update \main_spimaster2_done $0\main_spimaster2_done[0:0] - update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] - update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] - update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] - update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] - update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] - update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] - update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] - update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:424.5-424.54" - process $proc$ls180.v:424$2921 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:425.5-425.55" - process $proc$ls180.v:425$2922 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:426.5-426.56" - process $proc$ls180.v:426$2923 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:427.5-427.50" - process $proc$ls180.v:427$2924 - assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:4289.1-4337.4" - process $proc$ls180.v:4289$614 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_spisdcard_clk_enable[0:0] 1'0 - assign $0\main_spisdcard_cs_enable[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'0 - assign { } { } - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_miso_latch[0:0] 1'0 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_irq[0:0] 1'0 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4300.2-4336.9" - switch \builder_spimaster1_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4304.4-4307.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4304.8-4304.31" - case 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spisdcard_clk_enable[0:0] 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4312.4-4318.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4312.8-4312.31" - case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4313$615_Y - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4315.5-4317.8" - switch $eq$ls180.v:4315$617_Y - attribute \src "ls180.v:4315.9-4315.66" - case 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4322.4-4326.7" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4322.8-4322.31" - case 1'1 - assign $0\main_spisdcard_miso_latch[0:0] 1'1 - assign $0\main_spisdcard_irq[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4330.4-4334.7" - switch \main_spisdcard_start0 - attribute \src "ls180.v:4330.8-4330.29" - case 1'1 - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'01 - case - end - end - sync always - update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] - update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] - update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] - update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] - update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] - update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] - update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] - update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] - update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:430.5-430.67" - process $proc$ls180.v:430$2925 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:431.5-431.66" - process $proc$ls180.v:431$2926 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:4369.1-4397.4" - process $proc$ls180.v:4369$639 - assign { } { } - assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4371.2-4396.9" - switch \main_sdphy_clocker_storage - attribute \src "ls180.v:0.0-0.0" - case 9'000000100 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] - attribute \src "ls180.v:0.0-0.0" - case 9'000001000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] - attribute \src "ls180.v:0.0-0.0" - case 9'000010000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] - attribute \src "ls180.v:0.0-0.0" - case 9'000100000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] - attribute \src "ls180.v:0.0-0.0" - case 9'001000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] - attribute \src "ls180.v:0.0-0.0" - case 9'010000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] - attribute \src "ls180.v:0.0-0.0" - case 9'100000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] - end - sync always - update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:4399.1-4432.4" - process $proc$ls180.v:4399$642 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4409.2-4431.9" - switch \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4416.4-4422.7" - switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4416.8-4416.38" - case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4417$643_Y - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4419.5-4421.8" - switch $eq$ls180.v:4419$644_Y - attribute \src "ls180.v:4419.9-4419.41" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4427.4-4429.7" - switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4427.8-4427.37" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 - case - end - end - sync always - update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] - update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] - update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:4433.1-4509.4" - process $proc$ls180.v:4433$645 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdw_done[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4443.2-4508.9" - switch \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4447.4-4472.11" - switch \main_sdphy_cmdw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] - attribute \src "ls180.v:0.0-0.0" - case 8'00000010 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] - attribute \src "ls180.v:0.0-0.0" - case 8'00000011 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000100 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] - attribute \src "ls180.v:0.0-0.0" - case 8'00000101 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] - attribute \src "ls180.v:0.0-0.0" - case 8'00000110 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] - attribute \src "ls180.v:0.0-0.0" - case 8'00000111 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] - case - end - attribute \src "ls180.v:4473.4-4484.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4473.8-4473.38" - case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4474$646_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4476.5-4483.8" - switch $eq$ls180.v:4476$647_Y - attribute \src "ls180.v:4476.9-4476.40" - case 1'1 - attribute \src "ls180.v:4477.6-4482.9" - switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4477.10-4477.35" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4479.10-4479.14" - case - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4490.4-4497.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4490.8-4490.38" - case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4491$648_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4493.5-4496.8" - switch $eq$ls180.v:4493$649_Y - attribute \src "ls180.v:4493.9-4493.40" - case 1'1 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4502.4-4506.7" - switch $and$ls180.v:4502$650_Y - attribute \src "ls180.v:4502.8-4502.69" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4504.8-4504.12" - case - assign $0\main_sdphy_cmdw_done[0:0] 1'1 - end - end - sync always - update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] - update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] - update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:446.11-446.68" - process $proc$ls180.v:446$2927 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:447.5-447.64" - process $proc$ls180.v:447$2928 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:448.11-448.70" - process $proc$ls180.v:448$2929 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:449.11-449.70" - process $proc$ls180.v:449$2930 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:450.11-450.73" - process $proc$ls180.v:450$2931 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:4543.1-4636.4" - process $proc$ls180.v:4543$659 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4561.2-4635.9" - switch \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4569$660_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4566.4-4568.7" - switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4566.8-4566.49" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4571.4-4574.7" - switch $eq$ls180.v:4571$661_Y - attribute \src "ls180.v:4571.8-4571.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4580$663_Y - assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4597$666_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4582.4-4596.7" - switch $and$ls180.v:4582$664_Y - attribute \src "ls180.v:4582.8-4582.69" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4584$665_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4586.5-4595.8" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4586.9-4586.36" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4588.6-4594.9" - switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4588.10-4588.35" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4592.10-4592.14" - case - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - end - case - end - case - end - attribute \src "ls180.v:4599.4-4602.7" - switch $eq$ls180.v:4599$667_Y - attribute \src "ls180.v:4599.8-4599.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4608.4-4614.7" - switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4608.8-4608.38" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4609$668_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4611.5-4613.8" - switch $eq$ls180.v:4611$669_Y - attribute \src "ls180.v:4611.9-4611.40" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4620.4-4622.7" - switch $and$ls180.v:4620$670_Y - attribute \src "ls180.v:4620.8-4620.69" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4629.4-4633.7" - switch $and$ls180.v:4629$672_Y - attribute \src "ls180.v:4629.8-4629.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] - update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] - update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] - update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] - update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] - update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:4670.1-4697.4" - process $proc$ls180.v:4670$680 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_error[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign { } { } - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4678.2-4696.9" - switch \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4683.4-4687.7" - switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4683.8-4683.50" - case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4684$681_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4685$682_Y - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:4690.4-4694.7" - switch \main_sdphy_dataw_start - attribute \src "ls180.v:4690.8-4690.30" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 - case - end - end - sync always - update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] - update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] - update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:4698.1-4770.4" - process $proc$ls180.v:4698$683 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign { } { } - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4709.2-4769.9" - switch \builder_sdphy_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4714.4-4716.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4714.8-4714.39" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4719$684_Y - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4722.4-4729.11" - switch \main_sdphy_dataw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] - case - end - attribute \src "ls180.v:4730.4-4742.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4730.8-4730.39" - case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4731$685_Y - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4733.5-4741.8" - switch $eq$ls180.v:4733$686_Y - attribute \src "ls180.v:4733.9-4733.41" - case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4736.6-4740.9" - switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4736.10-4736.36" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4738.10-4738.14" - case - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4748.4-4751.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4748.8-4748.39" - case 1'1 - assign $0\main_sdphy_dataw_start[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4755.4-4760.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4755.8-4755.39" - case 1'1 - attribute \src "ls180.v:4756.5-4759.8" - switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4756.9-4756.51" - case 1'1 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4765.4-4767.7" - switch $and$ls180.v:4765$687_Y - attribute \src "ls180.v:4765.8-4765.71" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] - update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] - update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] - update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:471.5-471.59" - process $proc$ls180.v:471$2932 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:473.5-473.59" - process $proc$ls180.v:473$2933 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:474.5-474.58" - process $proc$ls180.v:474$2934 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:475.5-475.64" - process $proc$ls180.v:475$2935 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:476.12-476.74" - process $proc$ls180.v:476$2936 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:477.12-477.47" - process $proc$ls180.v:477$2937 - assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] - end - attribute \src "ls180.v:478.5-478.46" - process $proc$ls180.v:478$2938 - assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] - end - attribute \src "ls180.v:480.5-480.44" - process $proc$ls180.v:480$2939 - assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] - end - attribute \src "ls180.v:4804.1-4905.4" - process $proc$ls180.v:4804$695 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4821.2-4904.9" - switch \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4831$697_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4828.4-4830.7" - switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4828.8-4828.51" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4833.4-4836.7" - switch $eq$ls180.v:4833$698_Y - attribute \src "ls180.v:4833.8-4833.42" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4842$701_Y - assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4863$703_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4844.4-4862.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4844.8-4844.37" - case 1'1 - attribute \src "ls180.v:4845.5-4861.8" - switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4845.9-4845.38" - case 1'1 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4847$702_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4849.6-4858.9" - switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4849.10-4849.38" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4851.7-4857.10" - switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4851.11-4851.37" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4855.11-4855.15" - case - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - end - case - end - attribute \src "ls180.v:4859.9-4859.13" - case - assign $0\main_sdphy_datar_stop[0:0] 1'1 - end - case - end - attribute \src "ls180.v:4865.4-4868.7" - switch $eq$ls180.v:4865$704_Y - attribute \src "ls180.v:4865.8-4865.42" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4872.4-4878.7" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4872.8-4872.39" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4873$705_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4875.5-4877.8" - switch $eq$ls180.v:4875$706_Y - attribute \src "ls180.v:4875.9-4875.42" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_source_valid[0:0] 1'1 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4884.4-4886.7" - switch $and$ls180.v:4884$707_Y - attribute \src "ls180.v:4884.8-4884.71" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4891.4-4902.7" - switch $and$ls180.v:4891$708_Y - attribute \src "ls180.v:4891.8-4891.71" - case 1'1 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4893.5-4901.8" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4893.9-4893.40" - case 1'1 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 - case - end - case - end - end - sync always - update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] - update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] - update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] - update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] - update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] - update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] - update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] - update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] - update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:481.5-481.45" - process $proc$ls180.v:481$2940 - assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] - end - attribute \src "ls180.v:482.5-482.54" - process $proc$ls180.v:482$2941 - assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:484.32-484.76" - process $proc$ls180.v:484$2942 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - end - attribute \src "ls180.v:485.11-485.55" - process $proc$ls180.v:485$2943 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:487.32-487.75" - process $proc$ls180.v:487$2944 - assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:489.32-489.76" - process $proc$ls180.v:489$2945 - assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:495.5-495.51" - process $proc$ls180.v:495$2946 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:496.5-496.51" - process $proc$ls180.v:496$2947 - assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - end - attribute \src "ls180.v:4963.1-4970.4" - process $proc$ls180.v:4963$830 - assign { } { } - assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:4965.2-4969.5" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:4965.6-4965.38" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:4967.6-4967.10" - case - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 - end - sync always - update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:498.5-498.47" - process $proc$ls180.v:498$2948 - assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] - end - attribute \src "ls180.v:4985.1-4992.4" - process $proc$ls180.v:4985$853 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4987.2-4991.5" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:4987.6-4987.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:4989.6-4989.10" - case - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:499.5-499.45" - process $proc$ls180.v:499$2949 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:4995.1-5002.4" - process $proc$ls180.v:4995$864 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:4997.2-5001.5" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:4997.6-4997.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:4999.6-4999.10" - case - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:500.5-500.45" - process $proc$ls180.v:500$2950 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:5005.1-5012.4" - process $proc$ls180.v:5005$875 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5007.2-5011.5" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5007.6-5007.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5009.6-5009.10" - case - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:501.12-501.57" - process $proc$ls180.v:501$2951 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:5015.1-5022.4" - process $proc$ls180.v:5015$886 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5017.2-5021.5" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5017.6-5017.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5019.6-5019.10" - case - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:5023.1-5102.4" - process $proc$ls180.v:5023$887 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5040.2-5101.9" - switch \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5044.4-5046.7" - switch $eq$ls180.v:5044$888_Y - attribute \src "ls180.v:5044.8-5044.48" - case 1'1 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 - case - end - attribute \src "ls180.v:5047.4-5072.11" - switch \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } - case - end - attribute \src "ls180.v:5073.4-5080.7" - switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5073.8-5073.47" - case 1'1 - attribute \src "ls180.v:5074.5-5079.8" - switch $eq$ls180.v:5074$889_Y - attribute \src "ls180.v:5074.9-5074.49" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5076.9-5076.13" - case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5077$890_Y - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5095.4-5099.7" - switch $and$ls180.v:5095$892_Y - attribute \src "ls180.v:5095.8-5095.128" - case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 - case - end - end - sync always - update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] - update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] - update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] - update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:503.5-503.51" - process $proc$ls180.v:503$2952 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:504.5-504.51" - process $proc$ls180.v:504$2953 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:505.5-505.50" - process $proc$ls180.v:505$2954 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - end - attribute \src "ls180.v:506.5-506.54" - process $proc$ls180.v:506$2955 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:507.5-507.55" - process $proc$ls180.v:507$2956 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:508.5-508.56" - process $proc$ls180.v:508$2957 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:509.5-509.50" - process $proc$ls180.v:509$2958 - assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:5103.1-5108.4" - process $proc$ls180.v:5103$893 - assign { } { } - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5105.2-5107.5" - switch $and$ls180.v:5105$900_Y - attribute \src "ls180.v:5105.6-5105.301" - case 1'1 - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 - case - end - sync always - update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:5111.1-5118.4" - process $proc$ls180.v:5111$902 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5113.2-5117.5" - switch $eq$ls180.v:5113$903_Y - attribute \src "ls180.v:5113.6-5113.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5115.6-5115.10" - case - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:512.5-512.67" - process $proc$ls180.v:512$2959 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:5121.1-5128.4" - process $proc$ls180.v:5121$905 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5123.2-5127.5" - switch $eq$ls180.v:5123$906_Y - attribute \src "ls180.v:5123.6-5123.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5125.6-5125.10" - case - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:513.5-513.66" - process $proc$ls180.v:513$2960 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:5131.1-5138.4" - process $proc$ls180.v:5131$908 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5133.2-5137.5" - switch $eq$ls180.v:5133$909_Y - attribute \src "ls180.v:5133.6-5133.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5135.6-5135.10" - case - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:5141.1-5148.4" - process $proc$ls180.v:5141$911 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5143.2-5147.5" - switch $eq$ls180.v:5143$912_Y - attribute \src "ls180.v:5143.6-5143.45" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5145.6-5145.10" - case - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - end - sync always - update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:5150.1-5155.4" - process $proc$ls180.v:5150$913 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5152.2-5154.5" - switch $and$ls180.v:5152$915_Y - attribute \src "ls180.v:5152.6-5152.85" - case 1'1 - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 - case - end - sync always - update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:5156.1-5163.4" - process $proc$ls180.v:5156$916 - assign { } { } - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5158.2-5162.5" - switch $lt$ls180.v:5158$917_Y - attribute \src "ls180.v:5158.6-5158.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5160.6-5160.10" - case - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready - end - sync always - update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:5167.1-5174.4" - process $proc$ls180.v:5167$928 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5169.2-5173.5" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5169.6-5169.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5171.6-5171.10" - case - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:5177.1-5184.4" - process $proc$ls180.v:5177$939 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5179.2-5183.5" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5179.6-5179.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5181.6-5181.10" - case - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:5187.1-5194.4" - process $proc$ls180.v:5187$950 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5189.2-5193.5" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5189.6-5189.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5191.6-5191.10" - case - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:5197.1-5204.4" - process $proc$ls180.v:5197$961 - assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5199.2-5203.5" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5199.6-5199.43" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5201.6-5201.10" - case - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - end - sync always - update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:5205.1-5395.4" - process $proc$ls180.v:5205$962 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 - assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5246.2-5394.9" - switch \builder_sdcore_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5249.4-5269.11" - switch \main_sdcore_cmd_count - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5267$963_Y - case - end - attribute \src "ls180.v:5270.4-5282.7" - switch $and$ls180.v:5270$964_Y - attribute \src "ls180.v:5270.8-5270.65" - case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5271$965_Y - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5273.5-5281.8" - switch $eq$ls180.v:5273$966_Y - attribute \src "ls180.v:5273.9-5273.40" - case 1'1 - attribute \src "ls180.v:5274.6-5280.9" - switch $eq$ls180.v:5274$967_Y - attribute \src "ls180.v:5274.10-5274.40" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5278.10-5278.14" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5286$968_Y - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5287.4-5291.7" - switch $eq$ls180.v:5287$969_Y - attribute \src "ls180.v:5287.8-5287.38" - case 1'1 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5289.8-5289.12" - case - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 - end - attribute \src "ls180.v:5293.4-5314.7" - switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5293.8-5293.36" - case 1'1 - attribute \src "ls180.v:5294.5-5313.8" - switch $eq$ls180.v:5294$970_Y - attribute \src "ls180.v:5294.9-5294.56" - case 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5298.9-5298.13" - case - attribute \src "ls180.v:5299.6-5312.9" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5299.10-5299.37" - case 1'1 - attribute \src "ls180.v:5300.7-5308.10" - switch $eq$ls180.v:5300$971_Y - attribute \src "ls180.v:5300.11-5300.42" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5302.11-5302.15" - case - attribute \src "ls180.v:5303.8-5307.11" - switch $eq$ls180.v:5303$972_Y - attribute \src "ls180.v:5303.12-5303.43" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5305.12-5305.16" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - end - end - attribute \src "ls180.v:5309.10-5309.14" - case - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready - assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first - assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last - assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5322.4-5328.7" - switch $and$ls180.v:5322$974_Y - attribute \src "ls180.v:5322.8-5322.98" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5323$975_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5325.5-5327.8" - switch $eq$ls180.v:5325$977_Y - attribute \src "ls180.v:5325.9-5325.77" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - case - end - attribute \src "ls180.v:5330.4-5335.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5330.8-5330.37" - case 1'1 - attribute \src "ls180.v:5331.5-5334.8" - switch $ne$ls180.v:5331$978_Y - attribute \src "ls180.v:5331.9-5331.57" - case 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5340$980_Y - attribute \src "ls180.v:5341.4-5367.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5341.8-5341.37" - case 1'1 - attribute \src "ls180.v:5342.5-5366.8" - switch $eq$ls180.v:5342$981_Y - attribute \src "ls180.v:5342.9-5342.57" - case 1'1 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid - assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready - assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first - assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5348.6-5356.9" - switch $and$ls180.v:5348$982_Y - attribute \src "ls180.v:5348.10-5348.72" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5349$983_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5351.7-5355.10" - switch $eq$ls180.v:5351$985_Y - attribute \src "ls180.v:5351.11-5351.79" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5353.11-5353.15" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - end - case - end - attribute \src "ls180.v:5357.9-5357.13" - case - attribute \src "ls180.v:5358.6-5365.9" - switch $eq$ls180.v:5358$986_Y - attribute \src "ls180.v:5358.10-5358.58" - case 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5378.4-5392.7" - switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5378.8-5378.31" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 - case - end - end - sync always - update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] - update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] - update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] - update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] - update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] - update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] - update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] - update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] - update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] - update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] - update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] - update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] - update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] - update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] - update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] - update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] - update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] - update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] - update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] - update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:528.11-528.68" - process $proc$ls180.v:528$2961 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:529.5-529.64" - process $proc$ls180.v:529$2962 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:530.11-530.70" - process $proc$ls180.v:530$2963 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:531.11-531.70" - process $proc$ls180.v:531$2964 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:532.11-532.73" - process $proc$ls180.v:532$2965 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:54.5-54.42" - process $proc$ls180.v:54$2775 - assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] - end - attribute \src "ls180.v:5423.1-5430.4" - process $proc$ls180.v:5423$987 - assign { } { } - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5425.2-5429.5" - switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5425.6-5425.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5426$988_Y - attribute \src "ls180.v:5427.6-5427.10" - case - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce - end - sync always - update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:5456.1-5495.4" - process $proc$ls180.v:5456$998 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5466.2-5494.9" - switch \builder_sdblock2memdma_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5470$999_Y - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5472.4-5483.7" - switch $and$ls180.v:5472$1000_Y - attribute \src "ls180.v:5472.8-5472.103" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5473$1001_Y - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5475.5-5482.8" - switch $eq$ls180.v:5475$1003_Y - attribute \src "ls180.v:5475.9-5475.106" - case 1'1 - attribute \src "ls180.v:5476.6-5481.9" - switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5476.10-5476.57" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5479.10-5479.14" - case - assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 - end - sync always - update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] - update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] - update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:55.5-55.37" - process $proc$ls180.v:55$2776 - assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] - end - attribute \src "ls180.v:5515.1-5552.4" - process $proc$ls180.v:5515$1005 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - assign $0\main_interface1_bus_adr[31:0] 0 - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'0000 - assign $0\main_interface1_bus_cyc[0:0] 1'0 - assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5529.2-5551.9" - switch \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5534.4-5537.7" - switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5534.8-5534.41" - case 1'1 - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[3:0] 4'1111 - assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5545.4-5549.7" - switch $and$ls180.v:5545$1006_Y - attribute \src "ls180.v:5545.8-5545.59" - case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 - case - end - end - sync always - update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] - update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] - update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] - update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] - update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] - update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] - update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] - update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:553.5-553.59" - process $proc$ls180.v:553$2966 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:555.5-555.59" - process $proc$ls180.v:555$2967 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:5553.1-5589.4" - process $proc$ls180.v:5553$1007 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5562.2-5588.9" - switch \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5565$1009_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5566$1010_Y - attribute \src "ls180.v:5567.4-5578.7" - switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5567.8-5567.39" - case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5568$1011_Y - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5570.5-5577.8" - switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5570.9-5570.39" - case 1'1 - attribute \src "ls180.v:5571.6-5576.9" - switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5571.10-5571.43" - case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5574.10-5574.14" - case - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 - end - sync always - update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] - update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] - update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] - update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] - update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:556.5-556.58" - process $proc$ls180.v:556$2968 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:557.5-557.64" - process $proc$ls180.v:557$2969 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:558.12-558.74" - process $proc$ls180.v:558$2970 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:559.12-559.47" - process $proc$ls180.v:559$2971 - assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] - end - attribute \src "ls180.v:56.12-56.60" - process $proc$ls180.v:56$2777 - assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 - sync always - sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] - end - attribute \src "ls180.v:560.5-560.46" - process $proc$ls180.v:560$2972 - assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] - end - attribute \src "ls180.v:5601.1-5617.4" - process $proc$ls180.v:5601$1017 - assign { } { } - assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5603.2-5616.9" - switch \main_sdmem2block_converter_mux - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] - end - sync always - update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:562.5-562.44" - process $proc$ls180.v:562$2973 - assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] - end - attribute \src "ls180.v:563.5-563.45" - process $proc$ls180.v:563$2974 - assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] - end - attribute \src "ls180.v:5631.1-5638.4" - process $proc$ls180.v:5631$1018 - assign { } { } - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5633.2-5637.5" - switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5633.6-5633.35" - case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5634$1019_Y - attribute \src "ls180.v:5635.6-5635.10" - case - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce - end - sync always - update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:564.5-564.54" - process $proc$ls180.v:564$2975 - assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:5646.1-5682.4" - process $proc$ls180.v:5646$1025 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign { } { } - assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5657.2-5681.9" - switch \builder_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'10 - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } - assign $0\builder_next_state[1:0] 2'00 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5673.4-5679.7" - switch $and$ls180.v:5673$1026_Y - attribute \src "ls180.v:5673.8-5673.77" - case 1'1 - assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5676$1028_Y - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'01 - case - end - end - sync always - update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] - update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] - update \builder_next_state $0\builder_next_state[1:0] - update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] - update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] - update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] - update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] - update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] - end - attribute \src "ls180.v:566.32-566.76" - process $proc$ls180.v:566$2976 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - end - attribute \src "ls180.v:567.11-567.55" - process $proc$ls180.v:567$2977 - assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] - end - attribute \src "ls180.v:569.32-569.75" - process $proc$ls180.v:569$2978 - assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:57.5-57.39" - process $proc$ls180.v:57$2778 - assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] - end - attribute \src "ls180.v:5707.1-5714.4" - process $proc$ls180.v:5707$1049 - assign { } { } - assign { } { } - assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5709$1050_Y - assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5710$1051_Y - assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5711$1052_Y - assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5712$1053_Y - assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5713$1054_Y - sync always - update \builder_slave_sel $0\builder_slave_sel[4:0] - end - attribute \src "ls180.v:571.32-571.76" - process $proc$ls180.v:571$2979 - assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:5757.1-5768.4" - process $proc$ls180.v:5757$1067 - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_error[0:0] 1'0 - assign { } { } - assign { } { } - assign $0\builder_shared_ack[0:0] $or$ls180.v:5761$1071_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5762$1080_Y - attribute \src "ls180.v:5763.2-5767.5" - switch \builder_done - attribute \src "ls180.v:5763.6-5763.18" - case 1'1 - assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 - assign $0\builder_shared_ack[0:0] 1'1 - assign $0\builder_error[0:0] 1'1 - case - end - sync always - update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] - update \builder_shared_ack $0\builder_shared_ack[0:0] - update \builder_error $0\builder_error[0:0] - end - attribute \src "ls180.v:577.5-577.51" - process $proc$ls180.v:577$2980 - assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - end - attribute \src "ls180.v:578.5-578.51" - process $proc$ls180.v:578$2981 - assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - end - attribute \src "ls180.v:580.5-580.47" - process $proc$ls180.v:580$2982 - assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] - end - attribute \src "ls180.v:581.5-581.45" - process $proc$ls180.v:581$2983 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] - end - attribute \src "ls180.v:582.5-582.45" - process $proc$ls180.v:582$2984 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:583.12-583.57" - process $proc$ls180.v:583$2985 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:585.5-585.51" - process $proc$ls180.v:585$2986 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:586.5-586.51" - process $proc$ls180.v:586$2987 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:587.5-587.50" - process $proc$ls180.v:587$2988 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - end - attribute \src "ls180.v:588.5-588.54" - process $proc$ls180.v:588$2989 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:589.5-589.55" - process $proc$ls180.v:589$2990 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:590.5-590.56" - process $proc$ls180.v:590$2991 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:591.5-591.50" - process $proc$ls180.v:591$2992 - assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:594.5-594.67" - process $proc$ls180.v:594$2993 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:595.5-595.66" - process $proc$ls180.v:595$2994 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:610.11-610.68" - process $proc$ls180.v:610$2995 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:611.5-611.64" - process $proc$ls180.v:611$2996 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:612.11-612.70" - process $proc$ls180.v:612$2997 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:613.11-613.70" - process $proc$ls180.v:613$2998 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:614.11-614.73" - process $proc$ls180.v:614$2999 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:62.12-62.47" - process $proc$ls180.v:62$2779 - assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] - end - attribute \src "ls180.v:6282.1-6287.4" - process $proc$ls180.v:6282$1954 - assign { } { } - assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6284.2-6286.5" - switch \main_spimaster12_re - attribute \src "ls180.v:6284.6-6284.25" - case 1'1 - assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] - case - end - sync always - update \main_spimaster9_start $0\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:6328.1-6333.4" - process $proc$ls180.v:6328$2019 - assign { } { } - assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6330.2-6332.5" - switch \main_spisdcard_control_re - attribute \src "ls180.v:6330.6-6330.31" - case 1'1 - assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] - case - end - sync always - update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:635.5-635.59" - process $proc$ls180.v:635$3000 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:637.5-637.59" - process $proc$ls180.v:637$3001 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:638.5-638.58" - process $proc$ls180.v:638$3002 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:639.5-639.64" - process $proc$ls180.v:639$3003 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:64.12-64.55" - process $proc$ls180.v:64$2780 - assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 - sync always - sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:640.12-640.74" - process $proc$ls180.v:640$3004 - assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:641.12-641.47" - process $proc$ls180.v:641$3005 - assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:642.5-642.46" - process $proc$ls180.v:642$3006 - assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] - end - attribute \src "ls180.v:644.5-644.44" - process $proc$ls180.v:644$3007 - assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] - end - attribute \src "ls180.v:645.5-645.45" - process $proc$ls180.v:645$3008 - assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] - end - attribute \src "ls180.v:646.5-646.54" - process $proc$ls180.v:646$3009 - assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:648.32-648.76" - process $proc$ls180.v:648$3010 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - end - attribute \src "ls180.v:649.11-649.55" - process $proc$ls180.v:649$3011 - assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] - end - attribute \src "ls180.v:651.32-651.75" - process $proc$ls180.v:651$3012 - assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:6517.1-6533.4" - process $proc$ls180.v:6517$2240 - assign { } { } - assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6519.2-6532.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] - end - attribute \src "ls180.v:653.32-653.76" - process $proc$ls180.v:653$3013 - assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:6534.1-6550.4" - process $proc$ls180.v:6534$2241 - assign { } { } - assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6536.2-6549.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:6551.1-6567.4" - process $proc$ls180.v:6551$2242 - assign { } { } - assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6553.2-6566.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] - end - attribute \src "ls180.v:6568.1-6584.4" - process $proc$ls180.v:6568$2243 - assign { } { } - assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6570.2-6583.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:6585.1-6601.4" - process $proc$ls180.v:6585$2244 - assign { } { } - assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6587.2-6600.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:659.5-659.51" - process $proc$ls180.v:659$3014 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - end - attribute \src "ls180.v:660.5-660.51" - process $proc$ls180.v:660$3015 - assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - end - attribute \src "ls180.v:6602.1-6618.4" - process $proc$ls180.v:6602$2245 - assign { } { } - assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6604.2-6617.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:6619.1-6635.4" - process $proc$ls180.v:6619$2246 - assign { } { } - assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6621.2-6634.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:662.5-662.47" - process $proc$ls180.v:662$3016 - assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] - end - attribute \src "ls180.v:663.5-663.45" - process $proc$ls180.v:663$3017 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] - end - attribute \src "ls180.v:6636.1-6652.4" - process $proc$ls180.v:6636$2247 - assign { } { } - assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6638.2-6651.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:664.5-664.45" - process $proc$ls180.v:664$3018 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] - end - attribute \src "ls180.v:665.12-665.57" - process $proc$ls180.v:665$3019 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:6653.1-6669.4" - process $proc$ls180.v:6653$2248 - assign { } { } - assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6655.2-6668.9" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:667.5-667.51" - process $proc$ls180.v:667$3020 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:6670.1-6686.4" - process $proc$ls180.v:6670$2249 - assign { } { } - assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6672.2-6685.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] - end - sync always - update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:668.5-668.51" - process $proc$ls180.v:668$3021 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:6687.1-6703.4" - process $proc$ls180.v:6687$2250 - assign { } { } - assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6689.2-6702.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a - end - sync always - update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] - end - attribute \src "ls180.v:669.5-669.50" - process $proc$ls180.v:669$3022 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - end - attribute \src "ls180.v:670.5-670.54" - process $proc$ls180.v:670$3023 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:6704.1-6720.4" - process $proc$ls180.v:6704$2251 - assign { } { } - assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6706.2-6719.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba - end - sync always - update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:671.5-671.55" - process $proc$ls180.v:671$3024 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:672.5-672.56" - process $proc$ls180.v:672$3025 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:6721.1-6737.4" - process $proc$ls180.v:6721$2252 - assign { } { } - assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6723.2-6736.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read - end - sync always - update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] - end - attribute \src "ls180.v:673.5-673.50" - process $proc$ls180.v:673$3026 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:6738.1-6754.4" - process $proc$ls180.v:6738$2253 - assign { } { } - assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6740.2-6753.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write - end - sync always - update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] - end - attribute \src "ls180.v:6755.1-6771.4" - process $proc$ls180.v:6755$2254 - assign { } { } - assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6757.2-6770.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd - end - sync always - update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] - end - attribute \src "ls180.v:676.5-676.67" - process $proc$ls180.v:676$3027 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:677.5-677.66" - process $proc$ls180.v:677$3028 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - sync init - end - attribute \src "ls180.v:6772.1-6788.4" - process $proc$ls180.v:6772$2255 - assign { } { } - assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6774.2-6787.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas - end - sync always - update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] - end - attribute \src "ls180.v:6789.1-6805.4" - process $proc$ls180.v:6789$2256 - assign { } { } - assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6791.2-6804.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras - end - sync always - update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] - end - attribute \src "ls180.v:6806.1-6822.4" - process $proc$ls180.v:6806$2257 - assign { } { } - assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6808.2-6821.9" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we - end - sync always - update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] - end - attribute \src "ls180.v:6823.1-6830.4" - process $proc$ls180.v:6823$2258 - assign { } { } - assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6825.2-6829.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] - end - attribute \src "ls180.v:6831.1-6838.4" - process $proc$ls180.v:6831$2259 - assign { } { } - assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6833.2-6837.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] - end - attribute \src "ls180.v:6839.1-6846.4" - process $proc$ls180.v:6839$2260 - assign { } { } - assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6841.2-6845.9" - switch \builder_roundrobin0_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6843$2273_Y - end - sync always - update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] - end - attribute \src "ls180.v:6847.1-6854.4" - process $proc$ls180.v:6847$2274 - assign { } { } - assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6849.2-6853.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] - end - attribute \src "ls180.v:6855.1-6862.4" - process $proc$ls180.v:6855$2275 - assign { } { } - assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6857.2-6861.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] - end - attribute \src "ls180.v:6863.1-6870.4" - process $proc$ls180.v:6863$2276 - assign { } { } - assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6865.2-6869.9" - switch \builder_roundrobin1_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6867$2289_Y - end - sync always - update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] - end - attribute \src "ls180.v:6871.1-6878.4" - process $proc$ls180.v:6871$2290 - assign { } { } - assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6873.2-6877.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] - end - attribute \src "ls180.v:6879.1-6886.4" - process $proc$ls180.v:6879$2291 - assign { } { } - assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6881.2-6885.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:6887.1-6894.4" - process $proc$ls180.v:6887$2292 - assign { } { } - assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6889.2-6893.9" - switch \builder_roundrobin2_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6891$2305_Y - end - sync always - update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] - end - attribute \src "ls180.v:6895.1-6902.4" - process $proc$ls180.v:6895$2306 - assign { } { } - assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6897.2-6901.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } - end - sync always - update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] - end - attribute \src "ls180.v:6903.1-6910.4" - process $proc$ls180.v:6903$2307 - assign { } { } - assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:6905.2-6909.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we - end - sync always - update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] - end - attribute \src "ls180.v:6911.1-6918.4" - process $proc$ls180.v:6911$2308 - assign { } { } - assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:6913.2-6917.9" - switch \builder_roundrobin3_grant - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6915$2321_Y - end - sync always - update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] - end - attribute \src "ls180.v:6919.1-6938.4" - process $proc$ls180.v:6919$2322 - assign { } { } - assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:6921.2-6937.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr - end - sync always - update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] - end - attribute \src "ls180.v:692.11-692.68" - process $proc$ls180.v:692$3029 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:693.5-693.64" - process $proc$ls180.v:693$3030 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:6939.1-6958.4" - process $proc$ls180.v:6939$2323 - assign { } { } - assign $0\builder_comb_rhs_array_muxed25[31:0] 0 - attribute \src "ls180.v:6941.2-6957.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w - end - sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] - end - attribute \src "ls180.v:694.11-694.70" - process $proc$ls180.v:694$3031 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:695.11-695.70" - process $proc$ls180.v:695$3032 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:6959.1-6978.4" - process $proc$ls180.v:6959$2324 - assign { } { } - assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 - attribute \src "ls180.v:6961.2-6977.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel - end - sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] - end - attribute \src "ls180.v:696.11-696.73" - process $proc$ls180.v:696$3033 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:6979.1-6998.4" - process $proc$ls180.v:6979$2325 - assign { } { } - assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:6981.2-6997.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc - end - sync always - update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] - end - attribute \src "ls180.v:6999.1-7018.4" - process $proc$ls180.v:6999$2326 - assign { } { } - assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7001.2-7017.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb - end - sync always - update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] - end - attribute \src "ls180.v:7019.1-7038.4" - process $proc$ls180.v:7019$2327 - assign { } { } - assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7021.2-7037.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we - end - sync always - update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] - end - attribute \src "ls180.v:7039.1-7058.4" - process $proc$ls180.v:7039$2328 - assign { } { } - assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7041.2-7057.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti - end - sync always - update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] - end - attribute \src "ls180.v:7059.1-7078.4" - process $proc$ls180.v:7059$2329 - assign { } { } - assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7061.2-7077.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte - end - sync always - update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] - end - attribute \src "ls180.v:7079.1-7095.4" - process $proc$ls180.v:7079$2330 - assign { } { } - assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7081.2-7094.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba - end - sync always - update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] - end - attribute \src "ls180.v:7096.1-7112.4" - process $proc$ls180.v:7096$2331 - assign { } { } - assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7098.2-7111.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a - end - sync always - update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:71.5-71.46" - process $proc$ls180.v:71$2781 - assign { } { } - assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] - end - attribute \src "ls180.v:7113.1-7129.4" - process $proc$ls180.v:7113$2332 - assign { } { } - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7115.2-7128.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7120$2334_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7123$2336_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7126$2338_Y - end - sync always - update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] - end - attribute \src "ls180.v:7130.1-7146.4" - process $proc$ls180.v:7130$2339 - assign { } { } - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7132.2-7145.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7137$2341_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7140$2343_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7143$2345_Y - end - sync always - update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:7147.1-7163.4" - process $proc$ls180.v:7147$2346 - assign { } { } - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7149.2-7162.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7154$2348_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7157$2350_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7160$2352_Y - end - sync always - update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] - end - attribute \src "ls180.v:7164.1-7180.4" - process $proc$ls180.v:7164$2353 - assign { } { } - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7166.2-7179.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7171$2355_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7174$2357_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7177$2359_Y - end - sync always - update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] - end - attribute \src "ls180.v:717.5-717.59" - process $proc$ls180.v:717$3034 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:7181.1-7197.4" - process $proc$ls180.v:7181$2360 - assign { } { } - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7183.2-7196.9" - switch \main_sdram_steerer_sel - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7188$2362_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7191$2364_Y - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7194$2366_Y - end - sync always - update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:719.5-719.59" - process $proc$ls180.v:719$3035 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:7198.1-7226.4" - process $proc$ls180.v:7198$2367 - assign { } { } - assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7200.2-7225.9" - switch \main_spimaster34_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] - end - attribute \src "ls180.v:720.5-720.58" - process $proc$ls180.v:720$3036 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:721.5-721.64" - process $proc$ls180.v:721$3037 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:722.12-722.74" - process $proc$ls180.v:722$3038 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:7227.1-7255.4" - process $proc$ls180.v:7227$2368 - assign { } { } - assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7229.2-7254.9" - switch \main_spisdcard_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] - end - sync always - update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:723.12-723.47" - process $proc$ls180.v:723$3039 - assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] - end - attribute \src "ls180.v:724.5-724.46" - process $proc$ls180.v:724$3040 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] - end - attribute \src "ls180.v:726.5-726.44" - process $proc$ls180.v:726$3041 - assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] - end - attribute \src "ls180.v:727.5-727.45" - process $proc$ls180.v:727$3042 - assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] - end - attribute \src "ls180.v:728.5-728.54" - process $proc$ls180.v:728$3043 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:730.32-730.76" - process $proc$ls180.v:730$3044 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:731.11-731.55" - process $proc$ls180.v:731$3045 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:7313.1-7331.4" - process $proc$ls180.v:7313$2369 - assign { } { } - assign { } { } - assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 - assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 - assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 - assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 - assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 - assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 - assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 - assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 - assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 - assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 - assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 - assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 - assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 - assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 - assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 - assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 - sync always - update \main_gpio_status $0\main_gpio_status[15:0] - end - attribute \src "ls180.v:733.32-733.75" - process $proc$ls180.v:733$3046 - assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:735.32-735.76" - process $proc$ls180.v:735$3047 - assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:7352.1-7354.4" - process $proc$ls180.v:7352$2370 - assign { } { } - assign $0\main_int_rst[0:0] \sys_rst - sync posedge \por_clk - update \main_int_rst $0\main_int_rst[0:0] - end - attribute \src "ls180.v:7356.1-7426.4" - process $proc$ls180.v:7356$2371 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] - assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] - assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] - assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] - assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] - assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] - assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] - assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] - assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] - assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] - assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] - assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] - assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] - assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] - assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] - assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n - assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n - assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n - assign $0\sdram_cke[0:0] \main_dfi_p0_cke - assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n - assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] - assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] - assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] - assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] - assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] - assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] - assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] - assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] - assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] - assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] - assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] - assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] - assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] - assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] - assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] - assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] - assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] - assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] - assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] - assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] - assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] - assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] - assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] - assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] - assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] - assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] - assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] - assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] - assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] - assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] - assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] - assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] - assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] - assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7413$2373_Y - assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe - assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o - assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i - assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe - assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] - assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] - assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] - assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] - assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] - assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] - assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] - assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] - sync posedge \sdrio_clk - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] - update \sdram_a $0\sdram_a[12:0] - update \sdram_dq_o $0\sdram_dq_o[15:0] - update \sdram_dq_oe $0\sdram_dq_oe[0:0] - update \sdram_we_n $0\sdram_we_n[0:0] - update \sdram_ras_n $0\sdram_ras_n[0:0] - update \sdram_cas_n $0\sdram_cas_n[0:0] - update \sdram_cs_n $0\sdram_cs_n[0:0] - update \sdram_cke $0\sdram_cke[0:0] - update \sdram_ba $0\sdram_ba[1:0] - update \sdram_dm $0\sdram_dm[1:0] - update \sdram_clock $0\sdram_clock[0:0] - update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] - update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] - update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:738.5-738.44" - process $proc$ls180.v:738$3048 - assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] - sync init - end - attribute \src "ls180.v:739.5-739.45" - process $proc$ls180.v:739$3049 - assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] - sync init - end - attribute \src "ls180.v:740.5-740.43" - process $proc$ls180.v:740$3050 - assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] - sync init - end - attribute \src "ls180.v:741.5-741.48" - process $proc$ls180.v:741$3051 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] - sync init - end - attribute \src "ls180.v:7428.1-10052.4" - process $proc$ls180.v:7428$2374 - assign $0\uart_tx[0:0] \uart_tx - assign $0\spimaster_clk[0:0] \spimaster_clk - assign $0\spimaster_mosi[0:0] \spimaster_mosi - assign { } { } - assign $0\pwm[1:0] \pwm - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi - assign { } { } - assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage - assign { } { } - assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage - assign { } { } - assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r - assign { } { } - assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage - assign { } { } - assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage - assign { } { } - assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage - assign { } { } - assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage - assign { } { } - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status - assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending - assign { } { } - assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage - assign { } { } - assign $0\main_libresocsim_value[31:0] \main_libresocsim_value - assign { } { } - assign { } { } - assign $0\main_sdram_storage[3:0] \main_sdram_storage - assign { } { } - assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage - assign { } { } - assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage - assign { } { } - assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage - assign { } { } - assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage - assign { } { } - assign $0\main_sdram_status[15:0] \main_sdram_status - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 - assign { } { } - assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count - assign { } { } - assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter - assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row - assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row - assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row - assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row - assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count - assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant - assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant - assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready - assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count - assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready - assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count - assign $0\main_sdram_time0[4:0] \main_sdram_time0 - assign $0\main_sdram_time1[3:0] \main_sdram_time1 - assign $0\main_converter_counter[0:0] \main_converter_counter - assign $0\main_converter_dat_r[31:0] \main_converter_dat_r - assign $0\main_cmd_consumed[0:0] \main_cmd_consumed - assign $0\main_wdata_consumed[0:0] \main_wdata_consumed - assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage - assign { } { } - assign { } { } - assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen - assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg - assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount - assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy - assign { } { } - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data - assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen - assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx - assign { } { } - assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount - assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy - assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending - assign { } { } - assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending - assign { } { } - assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage - assign { } { } - assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable - assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 - assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce - assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume - assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable - assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 - assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce - assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume - assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage - assign { } { } - assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage - assign { } { } - assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso - assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage - assign { } { } - assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage - assign { } { } - assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage - assign { } { } - assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage - assign { } { } - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count - assign { } { } - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data - assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel - assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso - assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage - assign { } { } - assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage - assign { } { } - assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage - assign { } { } - assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage - assign { } { } - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count - assign { } { } - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data - assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel - assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data - assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage - assign { } { } - assign { } { } - assign $0\main_pwm0_counter[31:0] \main_pwm0_counter - assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage - assign { } { } - assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage - assign { } { } - assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage - assign { } { } - assign $0\main_pwm1_counter[31:0] \main_pwm1_counter - assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage - assign { } { } - assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage - assign { } { } - assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage - assign { } { } - assign $0\main_i2c_storage[2:0] \main_i2c_storage - assign { } { } - assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage - assign { } { } - assign { } { } - assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks - assign { } { } - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count - assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count - assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count - assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count - assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset - assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage - assign { } { } - assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage - assign { } { } - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status - assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage - assign { } { } - assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage - assign { } { } - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 - assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val - assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout - assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level - assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce - assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux - assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data - assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage - assign { } { } - assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage - assign { } { } - assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage - assign { } { } - assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage - assign { } { } - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux - assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level - assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce - assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w - assign $0\builder_grant[2:0] \builder_grant - assign { } { } - assign $0\builder_count[19:0] \builder_count - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_dummy[35:0] [0] $or$ls180.v:7429$2375_Y - assign $0\main_dummy[35:0] [1] $or$ls180.v:7430$2376_Y - assign $0\main_dummy[35:0] [2] $or$ls180.v:7431$2377_Y - assign $0\main_dummy[35:0] [3] $or$ls180.v:7432$2378_Y - assign $0\main_dummy[35:0] [4] $or$ls180.v:7433$2379_Y - assign $0\main_dummy[35:0] [5] $or$ls180.v:7434$2380_Y - assign $0\main_dummy[35:0] [6] $or$ls180.v:7435$2381_Y - assign $0\main_dummy[35:0] [7] $or$ls180.v:7436$2382_Y - assign $0\main_dummy[35:0] [8] $or$ls180.v:7437$2383_Y - assign $0\main_dummy[35:0] [9] $or$ls180.v:7438$2384_Y - assign $0\main_dummy[35:0] [10] $or$ls180.v:7439$2385_Y - assign $0\main_dummy[35:0] [11] $or$ls180.v:7440$2386_Y - assign $0\main_dummy[35:0] [12] $or$ls180.v:7441$2387_Y - assign $0\main_dummy[35:0] [13] $or$ls180.v:7442$2388_Y - assign $0\main_dummy[35:0] [14] $or$ls180.v:7443$2389_Y - assign $0\main_dummy[35:0] [15] $or$ls180.v:7444$2390_Y - assign $0\main_dummy[35:0] [16] $or$ls180.v:7445$2391_Y - assign $0\main_dummy[35:0] [17] $or$ls180.v:7446$2392_Y - assign $0\main_dummy[35:0] [18] $or$ls180.v:7447$2393_Y - assign $0\main_dummy[35:0] [19] $or$ls180.v:7448$2394_Y - assign $0\main_dummy[35:0] [20] $or$ls180.v:7449$2395_Y - assign $0\main_dummy[35:0] [21] $or$ls180.v:7450$2396_Y - assign $0\main_dummy[35:0] [22] $or$ls180.v:7451$2397_Y - assign $0\main_dummy[35:0] [23] $or$ls180.v:7452$2398_Y - assign $0\main_dummy[35:0] [24] $or$ls180.v:7453$2399_Y - assign $0\main_dummy[35:0] [25] $or$ls180.v:7454$2400_Y - assign $0\main_dummy[35:0] [26] $or$ls180.v:7455$2401_Y - assign $0\main_dummy[35:0] [27] $or$ls180.v:7456$2402_Y - assign $0\main_dummy[35:0] [28] $or$ls180.v:7457$2403_Y - assign $0\main_dummy[35:0] [29] $or$ls180.v:7458$2404_Y - assign $0\main_dummy[35:0] [30] $or$ls180.v:7459$2405_Y - assign $0\main_dummy[35:0] [31] $or$ls180.v:7460$2406_Y - assign $0\main_dummy[35:0] [32] $or$ls180.v:7461$2407_Y - assign $0\main_dummy[35:0] [33] $or$ls180.v:7462$2408_Y - assign $0\main_dummy[35:0] [34] $or$ls180.v:7463$2409_Y - assign $0\main_dummy[35:0] [35] $or$ls180.v:7464$2410_Y - assign $0\builder_converter0_state[0:0] \builder_converter0_next_state - assign $0\builder_converter1_state[0:0] \builder_converter1_next_state - assign $0\builder_converter2_state[0:0] \builder_converter2_next_state - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger - assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } - assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\builder_refresher_state[1:0] \builder_refresher_next_state - assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state - assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state - assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state - assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 - assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 - assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7906$2507_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7907$2508_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7908$2509_Y - assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 - assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7942$2527_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7943$2539_Y - assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 - assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 - assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 - assign $0\builder_converter_state[0:0] \builder_converter_next_state - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx - assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger - assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8101$2585_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8110$2588_Y - assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8136$2590_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8145$2593_Y - assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state - assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 - assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 - assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state - assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state - assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state - assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state - assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state - assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state - assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state - assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state - assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[4:0] \builder_slave_sel - assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re - assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re - assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re - assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re - assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re - assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re - assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re - assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re - assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re - assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re - assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re - assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re - assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re - assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re - assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re - assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re - assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re - assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re - assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re - assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re - assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re - assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re - assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re - assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re - assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re - assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re - assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re - assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re - assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re - assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re - assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re - assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re - assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re - assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re - assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re - assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re - assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re - assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re - assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re - assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re - assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re - assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re - assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx - assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] - assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] - assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 - assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] - assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 - assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] - assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 - assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] - assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 - assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] - assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 - assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] - assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 - assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] - assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 - assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] - assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 - assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] - assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 - assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] - assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 - assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] - assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 - assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] - assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 - assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] - assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 - assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] - assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 - assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] - assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7465.2-7467.5" - switch $or$ls180.v:7465$2411_Y - attribute \src "ls180.v:7465.6-7465.94" - case 1'1 - assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r - case - end - attribute \src "ls180.v:7469.2-7471.5" - switch \main_libresocsim_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7469.6-7469.66" - case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value - case - end - attribute \src "ls180.v:7472.2-7475.5" - switch \main_libresocsim_converter0_reset - attribute \src "ls180.v:7472.6-7472.39" - case 1'1 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7476.2-7478.5" - switch $or$ls180.v:7476$2412_Y - attribute \src "ls180.v:7476.6-7476.94" - case 1'1 - assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r - case - end - attribute \src "ls180.v:7480.2-7482.5" - switch \main_libresocsim_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7480.6-7480.66" - case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value - case - end - attribute \src "ls180.v:7483.2-7486.5" - switch \main_libresocsim_converter1_reset - attribute \src "ls180.v:7483.6-7483.39" - case 1'1 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7487.2-7489.5" - switch $or$ls180.v:7487$2413_Y - attribute \src "ls180.v:7487.6-7487.94" - case 1'1 - assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r - case - end - attribute \src "ls180.v:7491.2-7493.5" - switch \main_libresocsim_converter2_counter_converter2_next_value_ce - attribute \src "ls180.v:7491.6-7491.66" - case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value - case - end - attribute \src "ls180.v:7494.2-7497.5" - switch \main_libresocsim_converter2_reset - attribute \src "ls180.v:7494.6-7494.39" - case 1'1 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7498.2-7502.5" - switch $ne$ls180.v:7498$2414_Y - attribute \src "ls180.v:7498.6-7498.53" - case 1'1 - attribute \src "ls180.v:7499.3-7501.6" - switch \main_libresocsim_bus_error - attribute \src "ls180.v:7499.7-7499.33" - case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7500$2415_Y - case - end - case - end - attribute \src "ls180.v:7504.2-7506.5" - switch $and$ls180.v:7504$2418_Y - attribute \src "ls180.v:7504.6-7504.103" - case 1'1 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 - case - end - attribute \src "ls180.v:7507.2-7515.5" - switch \main_libresocsim_en_storage - attribute \src "ls180.v:7507.6-7507.33" - case 1'1 - attribute \src "ls180.v:7508.3-7512.6" - switch $eq$ls180.v:7508$2419_Y - attribute \src "ls180.v:7508.7-7508.39" - case 1'1 - assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7510.7-7510.11" - case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7511$2420_Y - end - attribute \src "ls180.v:7513.6-7513.10" - case - assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage - end - attribute \src "ls180.v:7516.2-7518.5" - switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7516.6-7516.38" - case 1'1 - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value - case - end - attribute \src "ls180.v:7519.2-7521.5" - switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7519.6-7519.33" - case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:7523.2-7525.5" - switch $and$ls180.v:7523$2422_Y - attribute \src "ls180.v:7523.6-7523.76" - case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:7528.2-7530.5" - switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7528.6-7528.37" - case 1'1 - assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata - case - end - attribute \src "ls180.v:7531.2-7535.5" - switch $and$ls180.v:7531$2424_Y - attribute \src "ls180.v:7531.6-7531.57" - case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7532$2425_Y - attribute \src "ls180.v:7533.6-7533.10" - case - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - end - attribute \src "ls180.v:7537.2-7543.5" - switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7537.6-7537.32" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7538$2426_Y - attribute \src "ls180.v:7539.3-7542.6" - switch $eq$ls180.v:7539$2427_Y - attribute \src "ls180.v:7539.7-7539.43" - case 1'1 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_postponer_req_o[0:0] 1'1 - case - end - case - end - attribute \src "ls180.v:7544.2-7552.5" - switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7544.6-7544.33" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7546.6-7546.10" - case - attribute \src "ls180.v:7547.3-7551.6" - switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7547.7-7547.33" - case 1'1 - attribute \src "ls180.v:7548.4-7550.7" - switch $ne$ls180.v:7548$2428_Y - attribute \src "ls180.v:7548.8-7548.44" - case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7549$2429_Y - case - end - case - end - end - attribute \src "ls180.v:7559.2-7565.5" - switch $and$ls180.v:7559$2431_Y - attribute \src "ls180.v:7559.6-7559.76" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'1 - case - end - attribute \src "ls180.v:7566.2-7572.5" - switch $eq$ls180.v:7566$2432_Y - attribute \src "ls180.v:7566.6-7566.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - case - end - attribute \src "ls180.v:7573.2-7580.5" - switch $eq$ls180.v:7573$2433_Y - attribute \src "ls180.v:7573.6-7573.44" - case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'1 - case - end - attribute \src "ls180.v:7581.2-7591.5" - switch $eq$ls180.v:7581$2434_Y - attribute \src "ls180.v:7581.6-7581.44" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7583.6-7583.10" - case - attribute \src "ls180.v:7584.3-7590.6" - switch $ne$ls180.v:7584$2435_Y - attribute \src "ls180.v:7584.7-7584.45" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7585$2436_Y - attribute \src "ls180.v:7586.7-7586.11" - case - attribute \src "ls180.v:7587.4-7589.7" - switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7587.8-7587.35" - case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0001 - case - end - end - end - attribute \src "ls180.v:7593.2-7600.5" - switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7593.6-7593.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7595.6-7595.10" - case - attribute \src "ls180.v:7596.3-7599.6" - switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7596.7-7596.39" - case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7601.2-7603.5" - switch $and$ls180.v:7601$2439_Y - attribute \src "ls180.v:7601.6-7601.191" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7602$2440_Y - case - end - attribute \src "ls180.v:7604.2-7606.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7604.6-7604.58" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7605$2441_Y - case - end - attribute \src "ls180.v:7607.2-7615.5" - switch $and$ls180.v:7607$2444_Y - attribute \src "ls180.v:7607.6-7607.191" - case 1'1 - attribute \src "ls180.v:7608.3-7610.6" - switch $not$ls180.v:7608$2445_Y - attribute \src "ls180.v:7608.7-7608.62" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7609$2446_Y - case - end - attribute \src "ls180.v:7611.6-7611.10" - case - attribute \src "ls180.v:7612.3-7614.6" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7612.7-7612.59" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7613$2447_Y - case - end - end - attribute \src "ls180.v:7616.2-7622.5" - switch $or$ls180.v:7616$2449_Y - attribute \src "ls180.v:7616.6-7616.108" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7623.2-7637.5" - switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7623.6-7623.43" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7625.3-7629.6" - switch 1'0 - attribute \src "ls180.v:7627.7-7627.11" - case - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7630.6-7630.10" - case - attribute \src "ls180.v:7631.3-7636.6" - switch $not$ls180.v:7631$2450_Y - attribute \src "ls180.v:7631.7-7631.47" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7632$2451_Y - attribute \src "ls180.v:7633.4-7635.7" - switch $eq$ls180.v:7633$2452_Y - attribute \src "ls180.v:7633.8-7633.55" - case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7639.2-7646.5" - switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7639.6-7639.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7641.6-7641.10" - case - attribute \src "ls180.v:7642.3-7645.6" - switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7642.7-7642.39" - case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7647.2-7649.5" - switch $and$ls180.v:7647$2455_Y - attribute \src "ls180.v:7647.6-7647.191" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7648$2456_Y - case - end - attribute \src "ls180.v:7650.2-7652.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7650.6-7650.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7651$2457_Y - case - end - attribute \src "ls180.v:7653.2-7661.5" - switch $and$ls180.v:7653$2460_Y - attribute \src "ls180.v:7653.6-7653.191" - case 1'1 - attribute \src "ls180.v:7654.3-7656.6" - switch $not$ls180.v:7654$2461_Y - attribute \src "ls180.v:7654.7-7654.62" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7655$2462_Y - case - end - attribute \src "ls180.v:7657.6-7657.10" - case - attribute \src "ls180.v:7658.3-7660.6" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7658.7-7658.59" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7659$2463_Y - case - end - end - attribute \src "ls180.v:7662.2-7668.5" - switch $or$ls180.v:7662$2465_Y - attribute \src "ls180.v:7662.6-7662.108" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7669.2-7683.5" - switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7669.6-7669.43" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7671.3-7675.6" - switch 1'0 - attribute \src "ls180.v:7673.7-7673.11" - case - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7676.6-7676.10" - case - attribute \src "ls180.v:7677.3-7682.6" - switch $not$ls180.v:7677$2466_Y - attribute \src "ls180.v:7677.7-7677.47" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7678$2467_Y - attribute \src "ls180.v:7679.4-7681.7" - switch $eq$ls180.v:7679$2468_Y - attribute \src "ls180.v:7679.8-7679.55" - case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7685.2-7692.5" - switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7685.6-7685.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7687.6-7687.10" - case - attribute \src "ls180.v:7688.3-7691.6" - switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7688.7-7688.39" - case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7693.2-7695.5" - switch $and$ls180.v:7693$2471_Y - attribute \src "ls180.v:7693.6-7693.191" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7694$2472_Y - case - end - attribute \src "ls180.v:7696.2-7698.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7696.6-7696.58" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7697$2473_Y - case - end - attribute \src "ls180.v:7699.2-7707.5" - switch $and$ls180.v:7699$2476_Y - attribute \src "ls180.v:7699.6-7699.191" - case 1'1 - attribute \src "ls180.v:7700.3-7702.6" - switch $not$ls180.v:7700$2477_Y - attribute \src "ls180.v:7700.7-7700.62" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7701$2478_Y - case - end - attribute \src "ls180.v:7703.6-7703.10" - case - attribute \src "ls180.v:7704.3-7706.6" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7704.7-7704.59" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7705$2479_Y - case - end - end - attribute \src "ls180.v:7708.2-7714.5" - switch $or$ls180.v:7708$2481_Y - attribute \src "ls180.v:7708.6-7708.108" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7715.2-7729.5" - switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7715.6-7715.43" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7717.3-7721.6" - switch 1'0 - attribute \src "ls180.v:7719.7-7719.11" - case - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7722.6-7722.10" - case - attribute \src "ls180.v:7723.3-7728.6" - switch $not$ls180.v:7723$2482_Y - attribute \src "ls180.v:7723.7-7723.47" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7724$2483_Y - attribute \src "ls180.v:7725.4-7727.7" - switch $eq$ls180.v:7725$2484_Y - attribute \src "ls180.v:7725.8-7725.55" - case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7731.2-7738.5" - switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7731.6-7731.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7733.6-7733.10" - case - attribute \src "ls180.v:7734.3-7737.6" - switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7734.7-7734.39" - case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - case - end - end - attribute \src "ls180.v:7739.2-7741.5" - switch $and$ls180.v:7739$2487_Y - attribute \src "ls180.v:7739.6-7739.191" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7740$2488_Y - case - end - attribute \src "ls180.v:7742.2-7744.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7742.6-7742.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7743$2489_Y - case - end - attribute \src "ls180.v:7745.2-7753.5" - switch $and$ls180.v:7745$2492_Y - attribute \src "ls180.v:7745.6-7745.191" - case 1'1 - attribute \src "ls180.v:7746.3-7748.6" - switch $not$ls180.v:7746$2493_Y - attribute \src "ls180.v:7746.7-7746.62" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7747$2494_Y - case - end - attribute \src "ls180.v:7749.6-7749.10" - case - attribute \src "ls180.v:7750.3-7752.6" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7750.7-7750.59" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7751$2495_Y - case - end - end - attribute \src "ls180.v:7754.2-7760.5" - switch $or$ls180.v:7754$2497_Y - attribute \src "ls180.v:7754.6-7754.108" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - case - end - attribute \src "ls180.v:7761.2-7775.5" - switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7761.6-7761.43" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7763.3-7767.6" - switch 1'0 - attribute \src "ls180.v:7765.7-7765.11" - case - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7768.6-7768.10" - case - attribute \src "ls180.v:7769.3-7774.6" - switch $not$ls180.v:7769$2498_Y - attribute \src "ls180.v:7769.7-7769.47" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7770$2499_Y - attribute \src "ls180.v:7771.4-7773.7" - switch $eq$ls180.v:7771$2500_Y - attribute \src "ls180.v:7771.8-7771.55" - case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7777.2-7783.5" - switch $not$ls180.v:7777$2501_Y - attribute \src "ls180.v:7777.6-7777.23" - case 1'1 - assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7779.6-7779.10" - case - attribute \src "ls180.v:7780.3-7782.6" - switch $not$ls180.v:7780$2502_Y - attribute \src "ls180.v:7780.7-7780.30" - case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7781$2503_Y - case - end - end - attribute \src "ls180.v:7784.2-7790.5" - switch $not$ls180.v:7784$2504_Y - attribute \src "ls180.v:7784.6-7784.23" - case 1'1 - assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7786.6-7786.10" - case - attribute \src "ls180.v:7787.3-7789.6" - switch $not$ls180.v:7787$2505_Y - attribute \src "ls180.v:7787.7-7787.30" - case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7788$2506_Y - case - end - end - attribute \src "ls180.v:7791.2-7846.5" - switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7791.6-7791.30" - case 1'1 - attribute \src "ls180.v:7792.3-7845.10" - switch \main_sdram_choose_cmd_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:7794.5-7804.8" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7794.9-7794.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7796.9-7796.13" - case - attribute \src "ls180.v:7797.6-7803.9" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7797.10-7797.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7799.10-7799.14" - case - attribute \src "ls180.v:7800.7-7802.10" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7800.11-7800.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:7807.5-7817.8" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7807.9-7807.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7809.9-7809.13" - case - attribute \src "ls180.v:7810.6-7816.9" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7810.10-7810.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7812.10-7812.14" - case - attribute \src "ls180.v:7813.7-7815.10" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7813.11-7813.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:7820.5-7830.8" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7820.9-7820.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7822.9-7822.13" - case - attribute \src "ls180.v:7823.6-7829.9" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7823.10-7823.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7825.10-7825.14" - case - attribute \src "ls180.v:7826.7-7828.10" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7826.11-7826.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:7833.5-7843.8" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7833.9-7833.41" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7835.9-7835.13" - case - attribute \src "ls180.v:7836.6-7842.9" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7836.10-7836.42" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7838.10-7838.14" - case - attribute \src "ls180.v:7839.7-7841.10" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7839.11-7839.43" - case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:7847.2-7902.5" - switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7847.6-7847.30" - case 1'1 - attribute \src "ls180.v:7848.3-7901.10" - switch \main_sdram_choose_req_grant - attribute \src "ls180.v:0.0-0.0" - case 2'00 - attribute \src "ls180.v:7850.5-7860.8" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7850.9-7850.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7852.9-7852.13" - case - attribute \src "ls180.v:7853.6-7859.9" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7853.10-7853.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7855.10-7855.14" - case - attribute \src "ls180.v:7856.7-7858.10" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7856.11-7856.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'01 - attribute \src "ls180.v:7863.5-7873.8" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7863.9-7863.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7865.9-7865.13" - case - attribute \src "ls180.v:7866.6-7872.9" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7866.10-7866.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7868.10-7868.14" - case - attribute \src "ls180.v:7869.7-7871.10" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7869.11-7869.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - attribute \src "ls180.v:7876.5-7886.8" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7876.9-7876.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7878.9-7878.13" - case - attribute \src "ls180.v:7879.6-7885.9" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7879.10-7879.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7881.10-7881.14" - case - attribute \src "ls180.v:7882.7-7884.10" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7882.11-7882.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - case - end - end - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - attribute \src "ls180.v:7889.5-7899.8" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7889.9-7889.41" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7891.9-7891.13" - case - attribute \src "ls180.v:7892.6-7898.9" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7892.10-7892.42" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7894.10-7894.14" - case - attribute \src "ls180.v:7895.7-7897.10" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7895.11-7895.43" - case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - case - end - end - end - case - end - case - end - attribute \src "ls180.v:7911.2-7925.5" - switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:7911.6-7911.30" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:7913.3-7917.6" - switch 1'1 - attribute \src "ls180.v:7913.7-7913.11" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:7918.6-7918.10" - case - attribute \src "ls180.v:7919.3-7924.6" - switch $not$ls180.v:7919$2510_Y - attribute \src "ls180.v:7919.7-7919.34" - case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7920$2511_Y - attribute \src "ls180.v:7921.4-7923.7" - switch $eq$ls180.v:7921$2512_Y - attribute \src "ls180.v:7921.8-7921.42" - case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7926.2-7940.5" - switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:7926.6-7926.30" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:7928.3-7932.6" - switch 1'0 - attribute \src "ls180.v:7930.7-7930.11" - case - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - end - attribute \src "ls180.v:7933.6-7933.10" - case - attribute \src "ls180.v:7934.3-7939.6" - switch $not$ls180.v:7934$2513_Y - attribute \src "ls180.v:7934.7-7934.34" - case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7935$2514_Y - attribute \src "ls180.v:7936.4-7938.7" - switch $eq$ls180.v:7936$2515_Y - attribute \src "ls180.v:7936.8-7936.42" - case 1'1 - assign $0\main_sdram_twtrcon_ready[0:0] 1'1 - case - end - case - end - end - attribute \src "ls180.v:7947.2-7949.5" - switch $or$ls180.v:7947$2540_Y - attribute \src "ls180.v:7947.6-7947.50" - case 1'1 - assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r - case - end - attribute \src "ls180.v:7951.2-7953.5" - switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:7951.6-7951.52" - case 1'1 - assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value - case - end - attribute \src "ls180.v:7954.2-7957.5" - switch \main_converter_reset - attribute \src "ls180.v:7954.6-7954.26" - case 1'1 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7958.2-7968.5" - switch \main_litedram_wb_ack - attribute \src "ls180.v:7958.6-7958.26" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:7961.6-7961.10" - case - attribute \src "ls180.v:7962.3-7964.6" - switch $and$ls180.v:7962$2541_Y - attribute \src "ls180.v:7962.7-7962.50" - case 1'1 - assign $0\main_cmd_consumed[0:0] 1'1 - case - end - attribute \src "ls180.v:7965.3-7967.6" - switch $and$ls180.v:7965$2542_Y - attribute \src "ls180.v:7965.7-7965.54" - case 1'1 - assign $0\main_wdata_consumed[0:0] 1'1 - case - end - end - attribute \src "ls180.v:7970.2-7991.5" - switch $and$ls180.v:7970$2546_Y - attribute \src "ls180.v:7970.6-7970.91" - case 1'1 - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data - assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 - assign $0\main_uart_phy_tx_busy[0:0] 1'1 - assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:7975.6-7975.10" - case - attribute \src "ls180.v:7976.3-7990.6" - switch $and$ls180.v:7976$2547_Y - attribute \src "ls180.v:7976.7-7976.60" - case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7977$2548_Y - attribute \src "ls180.v:7978.4-7989.7" - switch $eq$ls180.v:7978$2549_Y - attribute \src "ls180.v:7978.8-7978.43" - case 1'1 - assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:7980.8-7980.12" - case - attribute \src "ls180.v:7981.5-7988.8" - switch $eq$ls180.v:7981$2550_Y - attribute \src "ls180.v:7981.9-7981.44" - case 1'1 - assign $0\uart_tx[0:0] 1'1 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:7985.9-7985.13" - case - assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] - assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:7992.2-7996.5" - switch \main_uart_phy_tx_busy - attribute \src "ls180.v:7992.6-7992.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7993$2551_Y - attribute \src "ls180.v:7994.6-7994.10" - case - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } - end - attribute \src "ls180.v:7999.2-8023.5" - switch $not$ls180.v:7999$2552_Y - attribute \src "ls180.v:7999.6-7999.30" - case 1'1 - attribute \src "ls180.v:8000.3-8003.6" - switch $and$ls180.v:8000$2554_Y - attribute \src "ls180.v:8000.7-8000.49" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 - case - end - attribute \src "ls180.v:8004.6-8004.10" - case - attribute \src "ls180.v:8005.3-8022.6" - switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8005.7-8005.34" - case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8006$2555_Y - attribute \src "ls180.v:8007.4-8021.7" - switch $eq$ls180.v:8007$2556_Y - attribute \src "ls180.v:8007.8-8007.43" - case 1'1 - attribute \src "ls180.v:8008.5-8010.8" - switch \main_uart_phy_rx - attribute \src "ls180.v:8008.9-8008.25" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - case - end - attribute \src "ls180.v:8011.8-8011.12" - case - attribute \src "ls180.v:8012.5-8020.8" - switch $eq$ls180.v:8012$2557_Y - attribute \src "ls180.v:8012.9-8012.44" - case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8014.6-8017.9" - switch \main_uart_phy_rx - attribute \src "ls180.v:8014.10-8014.26" - case 1'1 - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_source_valid[0:0] 1'1 - case - end - attribute \src "ls180.v:8018.9-8018.13" - case - assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } - end - end - case - end - end - attribute \src "ls180.v:8024.2-8028.5" - switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8024.6-8024.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8025$2558_Y - attribute \src "ls180.v:8026.6-8026.10" - case - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 - end - attribute \src "ls180.v:8029.2-8031.5" - switch \main_uart_tx_clear - attribute \src "ls180.v:8029.6-8029.24" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8033.2-8035.5" - switch $and$ls180.v:8033$2560_Y - attribute \src "ls180.v:8033.6-8033.58" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8036.2-8038.5" - switch \main_uart_rx_clear - attribute \src "ls180.v:8036.6-8036.24" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8040.2-8042.5" - switch $and$ls180.v:8040$2562_Y - attribute \src "ls180.v:8040.6-8040.58" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8043.2-8049.5" - switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8043.6-8043.35" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8045.6-8045.10" - case - attribute \src "ls180.v:8046.3-8048.6" - switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8046.7-8046.27" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8050.2-8052.5" - switch $and$ls180.v:8050$2565_Y - attribute \src "ls180.v:8050.6-8050.108" - case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8051$2566_Y - case - end - attribute \src "ls180.v:8053.2-8055.5" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8053.6-8053.31" - case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8054$2567_Y - case - end - attribute \src "ls180.v:8056.2-8064.5" - switch $and$ls180.v:8056$2570_Y - attribute \src "ls180.v:8056.6-8056.108" - case 1'1 - attribute \src "ls180.v:8057.3-8059.6" - switch $not$ls180.v:8057$2571_Y - attribute \src "ls180.v:8057.7-8057.35" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8058$2572_Y - case - end - attribute \src "ls180.v:8060.6-8060.10" - case - attribute \src "ls180.v:8061.3-8063.6" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8061.7-8061.32" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8062$2573_Y - case - end - end - attribute \src "ls180.v:8065.2-8071.5" - switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8065.6-8065.35" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8067.6-8067.10" - case - attribute \src "ls180.v:8068.3-8070.6" - switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8068.7-8068.27" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8072.2-8074.5" - switch $and$ls180.v:8072$2576_Y - attribute \src "ls180.v:8072.6-8072.108" - case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8073$2577_Y - case - end - attribute \src "ls180.v:8075.2-8077.5" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8075.6-8075.31" - case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8076$2578_Y - case - end - attribute \src "ls180.v:8078.2-8086.5" - switch $and$ls180.v:8078$2581_Y - attribute \src "ls180.v:8078.6-8078.108" - case 1'1 - attribute \src "ls180.v:8079.3-8081.6" - switch $not$ls180.v:8079$2582_Y - attribute \src "ls180.v:8079.7-8079.35" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8080$2583_Y - case - end - attribute \src "ls180.v:8082.6-8082.10" - case - attribute \src "ls180.v:8083.3-8085.6" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8083.7-8083.32" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8084$2584_Y - case - end - end - attribute \src "ls180.v:8087.2-8100.5" - switch \main_uart_reset - attribute \src "ls180.v:8087.6-8087.21" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - case - end - attribute \src "ls180.v:8102.2-8109.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8102.6-8102.31" - case 1'1 - assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8104.6-8104.10" - case - attribute \src "ls180.v:8105.3-8108.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8105.7-8105.32" - case 1'1 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\spisdcard_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8111.2-8121.5" - switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8111.6-8111.33" - case 1'1 - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi - assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8114.6-8114.10" - case - attribute \src "ls180.v:8115.3-8120.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8115.7-8115.32" - case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8119$2589_Y - attribute \src "ls180.v:8116.4-8118.7" - switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8116.8-8116.34" - case 1'1 - assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 - case - end - case - end - end - attribute \src "ls180.v:8122.2-8128.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8122.6-8122.31" - case 1'1 - attribute \src "ls180.v:8123.3-8127.6" - switch \main_spimaster7_loopback - attribute \src "ls180.v:8123.7-8123.31" - case 1'1 - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8125.7-8125.11" - case - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } - end - case - end - attribute \src "ls180.v:8129.2-8131.5" - switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8129.6-8129.33" - case 1'1 - assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data - case - end - attribute \src "ls180.v:8133.2-8135.5" - switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8133.6-8133.53" - case 1'1 - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value - case - end - attribute \src "ls180.v:8137.2-8144.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8137.6-8137.29" - case 1'1 - assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8139.6-8139.10" - case - attribute \src "ls180.v:8140.3-8143.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8140.7-8140.30" - case 1'1 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\spimaster_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8146.2-8156.5" - switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8146.6-8146.31" - case 1'1 - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi - assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8149.6-8149.10" - case - attribute \src "ls180.v:8150.3-8155.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8150.7-8150.30" - case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8154$2594_Y - attribute \src "ls180.v:8151.4-8153.7" - switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8151.8-8151.32" - case 1'1 - assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 - case - end - case - end - end - attribute \src "ls180.v:8157.2-8163.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8157.6-8157.29" - case 1'1 - attribute \src "ls180.v:8158.3-8162.6" - switch \main_spisdcard_loopback - attribute \src "ls180.v:8158.7-8158.30" - case 1'1 - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8160.7-8160.11" - case - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } - end - case - end - attribute \src "ls180.v:8164.2-8166.5" - switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8164.6-8164.31" - case 1'1 - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data - case - end - attribute \src "ls180.v:8168.2-8170.5" - switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8168.6-8168.51" - case 1'1 - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value - case - end - attribute \src "ls180.v:8171.2-8184.5" - switch \main_pwm0_enable - attribute \src "ls180.v:8171.6-8171.22" - case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8172$2595_Y - attribute \src "ls180.v:8173.3-8177.6" - switch $lt$ls180.v:8173$2596_Y - attribute \src "ls180.v:8173.7-8173.44" - case 1'1 - assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8175.7-8175.11" - case - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8178.3-8180.6" - switch $ge$ls180.v:8178$2598_Y - attribute \src "ls180.v:8178.7-8178.55" - case 1'1 - assign $0\main_pwm0_counter[31:0] 0 - case - end - attribute \src "ls180.v:8181.6-8181.10" - case - assign $0\main_pwm0_counter[31:0] 0 - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8185.2-8198.5" - switch \main_pwm1_enable - attribute \src "ls180.v:8185.6-8185.22" - case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8186$2599_Y - attribute \src "ls180.v:8187.3-8191.6" - switch $lt$ls180.v:8187$2600_Y - attribute \src "ls180.v:8187.7-8187.44" - case 1'1 - assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8189.7-8189.11" - case - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8192.3-8194.6" - switch $ge$ls180.v:8192$2602_Y - attribute \src "ls180.v:8192.7-8192.55" - case 1'1 - assign $0\main_pwm1_counter[31:0] 0 - case - end - attribute \src "ls180.v:8195.6-8195.10" - case - assign $0\main_pwm1_counter[31:0] 0 - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8199.2-8201.5" - switch $not$ls180.v:8199$2603_Y - attribute \src "ls180.v:8199.6-8199.32" - case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8200$2604_Y - case - end - attribute \src "ls180.v:8205.2-8207.5" - switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8205.6-8205.57" - case 1'1 - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value - case - end - attribute \src "ls180.v:8209.2-8211.5" - switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8209.6-8209.57" - case 1'1 - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - case - end - attribute \src "ls180.v:8212.2-8214.5" - switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8212.6-8212.40" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8213$2605_Y - case - end - attribute \src "ls180.v:8215.2-8217.5" - switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8215.6-8215.49" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8218.2-8225.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8218.6-8218.46" - case 1'1 - attribute \src "ls180.v:8219.3-8224.6" - switch $or$ls180.v:8219$2607_Y - attribute \src "ls180.v:8219.7-8219.98" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8222.7-8222.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8223$2608_Y - end - case - end - attribute \src "ls180.v:8226.2-8239.5" - switch $and$ls180.v:8226$2609_Y - attribute \src "ls180.v:8226.6-8226.97" - case 1'1 - attribute \src "ls180.v:8227.3-8233.6" - switch $and$ls180.v:8227$2610_Y - attribute \src "ls180.v:8227.7-8227.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8230.7-8230.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8234.6-8234.10" - case - attribute \src "ls180.v:8235.3-8238.6" - switch $and$ls180.v:8235$2611_Y - attribute \src "ls180.v:8235.7-8235.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8236$2612_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8237$2613_Y - case - end - end - attribute \src "ls180.v:8240.2-8267.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8240.6-8240.46" - case 1'1 - attribute \src "ls180.v:8241.3-8266.10" - switch \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8268.2-8270.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8268.6-8268.46" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8269$2614_Y - case - end - attribute \src "ls180.v:8271.2-8276.5" - switch $or$ls180.v:8271$2616_Y - attribute \src "ls180.v:8271.6-8271.88" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8277.2-8282.5" - switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8277.6-8277.32" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8284.2-8286.5" - switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8284.6-8284.58" - case 1'1 - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - case - end - attribute \src "ls180.v:8287.2-8289.5" - switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8287.6-8287.60" - case 1'1 - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - case - end - attribute \src "ls180.v:8290.2-8292.5" - switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8290.6-8290.63" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - case - end - attribute \src "ls180.v:8293.2-8295.5" - switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8293.6-8293.41" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8294$2617_Y - case - end - attribute \src "ls180.v:8296.2-8298.5" - switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8296.6-8296.50" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8299.2-8306.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8299.6-8299.47" - case 1'1 - attribute \src "ls180.v:8300.3-8305.6" - switch $or$ls180.v:8300$2619_Y - attribute \src "ls180.v:8300.7-8300.100" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8303.7-8303.11" - case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8304$2620_Y - end - case - end - attribute \src "ls180.v:8307.2-8320.5" - switch $and$ls180.v:8307$2621_Y - attribute \src "ls180.v:8307.6-8307.99" - case 1'1 - attribute \src "ls180.v:8308.3-8314.6" - switch $and$ls180.v:8308$2622_Y - attribute \src "ls180.v:8308.7-8308.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8311.7-8311.11" - case - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8315.6-8315.10" - case - attribute \src "ls180.v:8316.3-8319.6" - switch $and$ls180.v:8316$2623_Y - attribute \src "ls180.v:8316.7-8316.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8317$2624_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8318$2625_Y - case - end - end - attribute \src "ls180.v:8321.2-8348.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8321.6-8321.47" - case 1'1 - attribute \src "ls180.v:8322.3-8347.10" - switch \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8349.2-8351.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8349.6-8349.47" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8350$2626_Y - case - end - attribute \src "ls180.v:8352.2-8357.5" - switch $or$ls180.v:8352$2628_Y - attribute \src "ls180.v:8352.6-8352.90" - case 1'1 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8358.2-8363.5" - switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8358.6-8358.33" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8365.2-8367.5" - switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8365.6-8365.63" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - case - end - attribute \src "ls180.v:8369.2-8371.5" - switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8369.6-8369.52" - case 1'1 - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value - case - end - attribute \src "ls180.v:8372.2-8374.5" - switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8372.6-8372.42" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8373$2629_Y - case - end - attribute \src "ls180.v:8375.2-8377.5" - switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8375.6-8375.51" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8378.2-8385.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8378.6-8378.48" - case 1'1 - attribute \src "ls180.v:8379.3-8384.6" - switch $or$ls180.v:8379$2631_Y - attribute \src "ls180.v:8379.7-8379.102" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8382.7-8382.11" - case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8383$2632_Y - end - case - end - attribute \src "ls180.v:8386.2-8399.5" - switch $and$ls180.v:8386$2633_Y - attribute \src "ls180.v:8386.6-8386.101" - case 1'1 - attribute \src "ls180.v:8387.3-8393.6" - switch $and$ls180.v:8387$2634_Y - attribute \src "ls180.v:8387.7-8387.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8390.7-8390.11" - case - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8394.6-8394.10" - case - attribute \src "ls180.v:8395.3-8398.6" - switch $and$ls180.v:8395$2635_Y - attribute \src "ls180.v:8395.7-8395.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8396$2636_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8397$2637_Y - case - end - end - attribute \src "ls180.v:8400.2-8409.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8400.6-8400.48" - case 1'1 - attribute \src "ls180.v:8401.3-8408.10" - switch \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8410.2-8412.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8410.6-8410.48" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8411$2638_Y - case - end - attribute \src "ls180.v:8413.2-8418.5" - switch $or$ls180.v:8413$2640_Y - attribute \src "ls180.v:8413.6-8413.92" - case 1'1 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data - case - end - attribute \src "ls180.v:8419.2-8424.5" - switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8419.6-8419.34" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8426.2-8428.5" - switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8426.6-8426.60" - case 1'1 - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - case - end - attribute \src "ls180.v:8429.2-8431.5" - switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8429.6-8429.62" - case 1'1 - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - case - end - attribute \src "ls180.v:8432.2-8434.5" - switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8432.6-8432.66" - case 1'1 - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - case - end - attribute \src "ls180.v:8435.2-8441.5" - switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8435.6-8435.35" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8437.6-8437.10" - case - attribute \src "ls180.v:8438.3-8440.6" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8438.7-8438.39" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 - case - end - end - attribute \src "ls180.v:8442.2-8448.5" - switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8442.6-8442.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8444.6-8444.10" - case - attribute \src "ls180.v:8445.3-8447.6" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8445.7-8445.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8449.2-8455.5" - switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8449.6-8449.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8451.6-8451.10" - case - attribute \src "ls180.v:8452.3-8454.6" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8452.7-8452.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8456.2-8462.5" - switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8456.6-8456.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8458.6-8458.10" - case - attribute \src "ls180.v:8459.3-8461.6" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8459.7-8459.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8463.2-8469.5" - switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8463.6-8463.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8465.6-8465.10" - case - attribute \src "ls180.v:8466.3-8468.6" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8466.7-8466.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8471.2-8473.5" - switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8471.6-8471.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - case - end - attribute \src "ls180.v:8474.2-8476.5" - switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8474.6-8474.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - case - end - attribute \src "ls180.v:8477.2-8479.5" - switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8477.6-8477.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - case - end - attribute \src "ls180.v:8480.2-8482.5" - switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8480.6-8480.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - case - end - attribute \src "ls180.v:8483.2-8485.5" - switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8483.6-8483.78" - case 1'1 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - case - end - attribute \src "ls180.v:8486.2-8488.5" - switch $and$ls180.v:8486$2641_Y - attribute \src "ls180.v:8486.6-8486.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc - case - end - attribute \src "ls180.v:8489.2-8491.5" - switch $and$ls180.v:8489$2642_Y - attribute \src "ls180.v:8489.6-8489.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc - case - end - attribute \src "ls180.v:8492.2-8494.5" - switch $and$ls180.v:8492$2643_Y - attribute \src "ls180.v:8492.6-8492.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc - case - end - attribute \src "ls180.v:8495.2-8497.5" - switch $and$ls180.v:8495$2644_Y - attribute \src "ls180.v:8495.6-8495.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc - case - end - attribute \src "ls180.v:8498.2-8502.5" - switch $and$ls180.v:8498$2645_Y - attribute \src "ls180.v:8498.6-8498.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } - assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] - case - end - attribute \src "ls180.v:8503.2-8507.5" - switch $and$ls180.v:8503$2646_Y - attribute \src "ls180.v:8503.6-8503.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } - assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] - case - end - attribute \src "ls180.v:8508.2-8512.5" - switch $and$ls180.v:8508$2647_Y - attribute \src "ls180.v:8508.6-8508.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } - assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] - case - end - attribute \src "ls180.v:8513.2-8517.5" - switch $and$ls180.v:8513$2648_Y - attribute \src "ls180.v:8513.6-8513.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } - assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] - case - end - attribute \src "ls180.v:8518.2-8526.5" - switch $and$ls180.v:8518$2649_Y - attribute \src "ls180.v:8518.6-8518.83" - case 1'1 - attribute \src "ls180.v:8519.3-8525.6" - switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8519.7-8519.42" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8521.7-8521.11" - case - attribute \src "ls180.v:8522.4-8524.7" - switch $ne$ls180.v:8522$2650_Y - attribute \src "ls180.v:8522.8-8522.48" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8523$2651_Y - case - end - end - case - end - attribute \src "ls180.v:8527.2-8533.5" - switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8527.6-8527.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8529.6-8529.10" - case - attribute \src "ls180.v:8530.3-8532.6" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8530.7-8530.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8534.2-8540.5" - switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8534.6-8534.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8536.6-8536.10" - case - attribute \src "ls180.v:8537.3-8539.6" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8537.7-8537.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8541.2-8547.5" - switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8541.6-8541.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8543.6-8543.10" - case - attribute \src "ls180.v:8544.3-8546.6" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8544.7-8544.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8548.2-8554.5" - switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8548.6-8548.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8550.6-8550.10" - case - attribute \src "ls180.v:8551.3-8553.6" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8551.7-8551.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8556.2-8558.5" - switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8556.6-8556.52" - case 1'1 - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 - case - end - attribute \src "ls180.v:8559.2-8561.5" - switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8559.6-8559.53" - case 1'1 - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 - case - end - attribute \src "ls180.v:8562.2-8564.5" - switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8562.6-8562.53" - case 1'1 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 - case - end - attribute \src "ls180.v:8565.2-8567.5" - switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8565.6-8565.54" - case 1'1 - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 - case - end - attribute \src "ls180.v:8568.2-8570.5" - switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8568.6-8568.53" - case 1'1 - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 - case - end - attribute \src "ls180.v:8571.2-8573.5" - switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8571.6-8571.55" - case 1'1 - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - case - end - attribute \src "ls180.v:8574.2-8576.5" - switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8574.6-8574.54" - case 1'1 - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 - case - end - attribute \src "ls180.v:8577.2-8579.5" - switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8577.6-8577.56" - case 1'1 - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 - case - end - attribute \src "ls180.v:8580.2-8582.5" - switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8580.6-8580.63" - case 1'1 - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - case - end - attribute \src "ls180.v:8583.2-8585.5" - switch $and$ls180.v:8583$2654_Y - attribute \src "ls180.v:8583.6-8583.120" - case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8584$2655_Y - case - end - attribute \src "ls180.v:8586.2-8588.5" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8586.6-8586.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8587$2656_Y - case - end - attribute \src "ls180.v:8589.2-8597.5" - switch $and$ls180.v:8589$2659_Y - attribute \src "ls180.v:8589.6-8589.120" - case 1'1 - attribute \src "ls180.v:8590.3-8592.6" - switch $not$ls180.v:8590$2660_Y - attribute \src "ls180.v:8590.7-8590.39" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8591$2661_Y - case - end - attribute \src "ls180.v:8593.6-8593.10" - case - attribute \src "ls180.v:8594.3-8596.6" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8594.7-8594.36" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8595$2662_Y - case - end - end - attribute \src "ls180.v:8598.2-8600.5" - switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8598.6-8598.45" - case 1'1 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8601.2-8608.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8601.6-8601.42" - case 1'1 - attribute \src "ls180.v:8602.3-8607.6" - switch $or$ls180.v:8602$2664_Y - attribute \src "ls180.v:8602.7-8602.90" - case 1'1 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8605.7-8605.11" - case - assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8606$2665_Y - end - case - end - attribute \src "ls180.v:8609.2-8622.5" - switch $and$ls180.v:8609$2666_Y - attribute \src "ls180.v:8609.6-8609.89" - case 1'1 - attribute \src "ls180.v:8610.3-8616.6" - switch $and$ls180.v:8610$2667_Y - attribute \src "ls180.v:8610.7-8610.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8613.7-8613.11" - case - assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 - assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8617.6-8617.10" - case - attribute \src "ls180.v:8618.3-8621.6" - switch $and$ls180.v:8618$2668_Y - attribute \src "ls180.v:8618.7-8618.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8619$2669_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8620$2670_Y - case - end - end - attribute \src "ls180.v:8623.2-8638.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8623.6-8623.42" - case 1'1 - attribute \src "ls180.v:8624.3-8637.10" - switch \main_sdblock2mem_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8639.2-8641.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8639.6-8639.42" - case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8640$2671_Y - case - end - attribute \src "ls180.v:8643.2-8645.5" - switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8643.6-8643.76" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - case - end - attribute \src "ls180.v:8646.2-8649.5" - switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8646.6-8646.46" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8651.2-8653.5" - switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8651.6-8651.64" - case 1'1 - assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - case - end - attribute \src "ls180.v:8655.2-8657.5" - switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8655.6-8655.76" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - case - end - attribute \src "ls180.v:8658.2-8661.5" - switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8658.6-8658.32" - case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - case - end - attribute \src "ls180.v:8662.2-8668.5" - switch $and$ls180.v:8662$2672_Y - attribute \src "ls180.v:8662.6-8662.89" - case 1'1 - attribute \src "ls180.v:8663.3-8667.6" - switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8663.7-8663.38" - case 1'1 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - attribute \src "ls180.v:8665.7-8665.11" - case - assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8666$2673_Y - end - case - end - attribute \src "ls180.v:8669.2-8671.5" - switch $and$ls180.v:8669$2676_Y - attribute \src "ls180.v:8669.6-8669.120" - case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8670$2677_Y - case - end - attribute \src "ls180.v:8672.2-8674.5" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8672.6-8672.35" - case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8673$2678_Y - case - end - attribute \src "ls180.v:8675.2-8683.5" - switch $and$ls180.v:8675$2681_Y - attribute \src "ls180.v:8675.6-8675.120" - case 1'1 - attribute \src "ls180.v:8676.3-8678.6" - switch $not$ls180.v:8676$2682_Y - attribute \src "ls180.v:8676.7-8676.39" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8677$2683_Y - case - end - attribute \src "ls180.v:8679.6-8679.10" - case - attribute \src "ls180.v:8680.3-8682.6" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8680.7-8680.36" - case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8681$2684_Y - case - end - end - attribute \src "ls180.v:8685.2-8687.5" - switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8685.6-8685.46" - case 1'1 - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 - case - end - attribute \src "ls180.v:8688.2-8690.5" - switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8688.6-8688.44" - case 1'1 - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 - case - end - attribute \src "ls180.v:8691.2-8693.5" - switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8691.6-8691.43" - case 1'1 - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 - case - end - attribute \src "ls180.v:8694.2-8790.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - attribute \src "ls180.v:8696.4-8712.7" - switch $not$ls180.v:8696$2685_Y - attribute \src "ls180.v:8696.8-8696.29" - case 1'1 - attribute \src "ls180.v:8697.5-8711.8" - switch \builder_request [1] - attribute \src "ls180.v:8697.9-8697.27" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8699.9-8699.13" - case - attribute \src "ls180.v:8700.6-8710.9" - switch \builder_request [2] - attribute \src "ls180.v:8700.10-8700.28" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8702.10-8702.14" - case - attribute \src "ls180.v:8703.7-8709.10" - switch \builder_request [3] - attribute \src "ls180.v:8703.11-8703.29" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8705.11-8705.15" - case - attribute \src "ls180.v:8706.8-8708.11" - switch \builder_request [4] - attribute \src "ls180.v:8706.12-8706.30" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'001 - attribute \src "ls180.v:8715.4-8731.7" - switch $not$ls180.v:8715$2686_Y - attribute \src "ls180.v:8715.8-8715.29" - case 1'1 - attribute \src "ls180.v:8716.5-8730.8" - switch \builder_request [2] - attribute \src "ls180.v:8716.9-8716.27" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8718.9-8718.13" - case - attribute \src "ls180.v:8719.6-8729.9" - switch \builder_request [3] - attribute \src "ls180.v:8719.10-8719.28" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8721.10-8721.14" - case - attribute \src "ls180.v:8722.7-8728.10" - switch \builder_request [4] - attribute \src "ls180.v:8722.11-8722.29" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8724.11-8724.15" - case - attribute \src "ls180.v:8725.8-8727.11" - switch \builder_request [0] - attribute \src "ls180.v:8725.12-8725.30" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - attribute \src "ls180.v:8734.4-8750.7" - switch $not$ls180.v:8734$2687_Y - attribute \src "ls180.v:8734.8-8734.29" - case 1'1 - attribute \src "ls180.v:8735.5-8749.8" - switch \builder_request [3] - attribute \src "ls180.v:8735.9-8735.27" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8737.9-8737.13" - case - attribute \src "ls180.v:8738.6-8748.9" - switch \builder_request [4] - attribute \src "ls180.v:8738.10-8738.28" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8740.10-8740.14" - case - attribute \src "ls180.v:8741.7-8747.10" - switch \builder_request [0] - attribute \src "ls180.v:8741.11-8741.29" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8743.11-8743.15" - case - attribute \src "ls180.v:8744.8-8746.11" - switch \builder_request [1] - attribute \src "ls180.v:8744.12-8744.30" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:8753.4-8769.7" - switch $not$ls180.v:8753$2688_Y - attribute \src "ls180.v:8753.8-8753.29" - case 1'1 - attribute \src "ls180.v:8754.5-8768.8" - switch \builder_request [4] - attribute \src "ls180.v:8754.9-8754.27" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8756.9-8756.13" - case - attribute \src "ls180.v:8757.6-8767.9" - switch \builder_request [0] - attribute \src "ls180.v:8757.10-8757.28" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8759.10-8759.14" - case - attribute \src "ls180.v:8760.7-8766.10" - switch \builder_request [1] - attribute \src "ls180.v:8760.11-8760.29" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8762.11-8762.15" - case - attribute \src "ls180.v:8763.8-8765.11" - switch \builder_request [2] - attribute \src "ls180.v:8763.12-8763.30" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - attribute \src "ls180.v:8772.4-8788.7" - switch $not$ls180.v:8772$2689_Y - attribute \src "ls180.v:8772.8-8772.29" - case 1'1 - attribute \src "ls180.v:8773.5-8787.8" - switch \builder_request [0] - attribute \src "ls180.v:8773.9-8773.27" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8775.9-8775.13" - case - attribute \src "ls180.v:8776.6-8786.9" - switch \builder_request [1] - attribute \src "ls180.v:8776.10-8776.28" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8778.10-8778.14" - case - attribute \src "ls180.v:8779.7-8785.10" - switch \builder_request [2] - attribute \src "ls180.v:8779.11-8779.29" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8781.11-8781.15" - case - attribute \src "ls180.v:8782.8-8784.11" - switch \builder_request [3] - attribute \src "ls180.v:8782.12-8782.30" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - case - end - end - end - end - case - end - case - end - attribute \src "ls180.v:8792.2-8798.5" - switch \builder_wait - attribute \src "ls180.v:8792.6-8792.18" - case 1'1 - attribute \src "ls180.v:8793.3-8795.6" - switch $not$ls180.v:8793$2690_Y - attribute \src "ls180.v:8793.7-8793.22" - case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8794$2691_Y - case - end - attribute \src "ls180.v:8796.6-8796.10" - case - assign $0\builder_count[19:0] 20'11110100001001000000 - end - attribute \src "ls180.v:8800.2-8830.5" - switch \builder_csrbank0_sel - attribute \src "ls180.v:8800.6-8800.26" - case 1'1 - attribute \src "ls180.v:8801.3-8829.10" - switch \builder_interface0_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w - case - end - case - end - attribute \src "ls180.v:8831.2-8833.5" - switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8831.6-8831.32" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r - case - end - attribute \src "ls180.v:8835.2-8837.5" - switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8835.6-8835.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r - case - end - attribute \src "ls180.v:8838.2-8840.5" - switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8838.6-8838.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r - case - end - attribute \src "ls180.v:8841.2-8843.5" - switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8841.6-8841.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r - case - end - attribute \src "ls180.v:8844.2-8846.5" - switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8844.6-8844.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r - case - end - attribute \src "ls180.v:8849.2-8870.5" - switch \builder_csrbank1_sel - attribute \src "ls180.v:8849.6-8849.26" - case 1'1 - attribute \src "ls180.v:8850.3-8869.10" - switch \builder_interface1_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w - case - end - case - end - attribute \src "ls180.v:8871.2-8873.5" - switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8871.6-8871.29" - case 1'1 - assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r - case - end - attribute \src "ls180.v:8874.2-8876.5" - switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8874.6-8874.29" - case 1'1 - assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r - case - end - attribute \src "ls180.v:8878.2-8880.5" - switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8878.6-8878.30" - case 1'1 - assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r - case - end - attribute \src "ls180.v:8881.2-8883.5" - switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8881.6-8881.30" - case 1'1 - assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r - case - end - attribute \src "ls180.v:8886.2-8895.5" - switch \builder_csrbank2_sel - attribute \src "ls180.v:8886.6-8886.26" - case 1'1 - attribute \src "ls180.v:8887.3-8894.10" - switch \builder_interface2_bank_bus_adr [0] - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } - case - end - case - end - attribute \src "ls180.v:8896.2-8898.5" - switch \builder_csrbank2_w0_re - attribute \src "ls180.v:8896.6-8896.28" - case 1'1 - assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r - case - end - attribute \src "ls180.v:8901.2-8931.5" - switch \builder_csrbank3_sel - attribute \src "ls180.v:8901.6-8901.26" - case 1'1 - attribute \src "ls180.v:8902.3-8930.10" - switch \builder_interface3_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w - case - end - case - end - attribute \src "ls180.v:8932.2-8934.5" - switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:8932.6-8932.33" - case 1'1 - assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r - case - end - attribute \src "ls180.v:8936.2-8938.5" - switch \builder_csrbank3_width3_re - attribute \src "ls180.v:8936.6-8936.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r - case - end - attribute \src "ls180.v:8939.2-8941.5" - switch \builder_csrbank3_width2_re - attribute \src "ls180.v:8939.6-8939.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r - case - end - attribute \src "ls180.v:8942.2-8944.5" - switch \builder_csrbank3_width1_re - attribute \src "ls180.v:8942.6-8942.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r - case - end - attribute \src "ls180.v:8945.2-8947.5" - switch \builder_csrbank3_width0_re - attribute \src "ls180.v:8945.6-8945.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r - case - end - attribute \src "ls180.v:8949.2-8951.5" - switch \builder_csrbank3_period3_re - attribute \src "ls180.v:8949.6-8949.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r - case - end - attribute \src "ls180.v:8952.2-8954.5" - switch \builder_csrbank3_period2_re - attribute \src "ls180.v:8952.6-8952.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r - case - end - attribute \src "ls180.v:8955.2-8957.5" - switch \builder_csrbank3_period1_re - attribute \src "ls180.v:8955.6-8955.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r - case - end - attribute \src "ls180.v:8958.2-8960.5" - switch \builder_csrbank3_period0_re - attribute \src "ls180.v:8958.6-8958.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r - case - end - attribute \src "ls180.v:8963.2-8993.5" - switch \builder_csrbank4_sel - attribute \src "ls180.v:8963.6-8963.26" - case 1'1 - attribute \src "ls180.v:8964.3-8992.10" - switch \builder_interface4_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w - case - end - case - end - attribute \src "ls180.v:8994.2-8996.5" - switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:8994.6-8994.33" - case 1'1 - assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r - case - end - attribute \src "ls180.v:8998.2-9000.5" - switch \builder_csrbank4_width3_re - attribute \src "ls180.v:8998.6-8998.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r - case - end - attribute \src "ls180.v:9001.2-9003.5" - switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9001.6-9001.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r - case - end - attribute \src "ls180.v:9004.2-9006.5" - switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9004.6-9004.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r - case - end - attribute \src "ls180.v:9007.2-9009.5" - switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9007.6-9007.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r - case - end - attribute \src "ls180.v:9011.2-9013.5" - switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9011.6-9011.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r - case - end - attribute \src "ls180.v:9014.2-9016.5" - switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9014.6-9014.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r - case - end - attribute \src "ls180.v:9017.2-9019.5" - switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9017.6-9017.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r - case - end - attribute \src "ls180.v:9020.2-9022.5" - switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9020.6-9020.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r - case - end - attribute \src "ls180.v:9025.2-9073.5" - switch \builder_csrbank5_sel - attribute \src "ls180.v:9025.6-9025.26" - case 1'1 - attribute \src "ls180.v:9026.3-9072.10" - switch \builder_interface5_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 4'1010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } - case - end - case - end - attribute \src "ls180.v:9074.2-9076.5" - switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9074.6-9074.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r - case - end - attribute \src "ls180.v:9077.2-9079.5" - switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9077.6-9077.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r - case - end - attribute \src "ls180.v:9080.2-9082.5" - switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9080.6-9080.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r - case - end - attribute \src "ls180.v:9083.2-9085.5" - switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9083.6-9083.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r - case - end - attribute \src "ls180.v:9086.2-9088.5" - switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9086.6-9086.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r - case - end - attribute \src "ls180.v:9089.2-9091.5" - switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9089.6-9089.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r - case - end - attribute \src "ls180.v:9092.2-9094.5" - switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9092.6-9092.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r - case - end - attribute \src "ls180.v:9095.2-9097.5" - switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9095.6-9095.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r - case - end - attribute \src "ls180.v:9099.2-9101.5" - switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9099.6-9099.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r - case - end - attribute \src "ls180.v:9102.2-9104.5" - switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9102.6-9102.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r - case - end - attribute \src "ls180.v:9105.2-9107.5" - switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9105.6-9105.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r - case - end - attribute \src "ls180.v:9108.2-9110.5" - switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9108.6-9108.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r - case - end - attribute \src "ls180.v:9112.2-9114.5" - switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9112.6-9112.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r - case - end - attribute \src "ls180.v:9116.2-9118.5" - switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9116.6-9116.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r - case - end - attribute \src "ls180.v:9121.2-9223.5" - switch \builder_csrbank6_sel - attribute \src "ls180.v:9121.6-9121.26" - case 1'1 - attribute \src "ls180.v:9122.3-9222.10" - switch \builder_interface6_bank_bus_adr [5:0] - attribute \src "ls180.v:0.0-0.0" - case 6'000000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:0.0-0.0" - case 6'000100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:0.0-0.0" - case 6'001000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } - attribute \src "ls180.v:0.0-0.0" - case 6'001001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:0.0-0.0" - case 6'001010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:0.0-0.0" - case 6'001011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:0.0-0.0" - case 6'001100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:0.0-0.0" - case 6'001101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:0.0-0.0" - case 6'001110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:0.0-0.0" - case 6'001111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:0.0-0.0" - case 6'010000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:0.0-0.0" - case 6'010001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:0.0-0.0" - case 6'010010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:0.0-0.0" - case 6'010011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:0.0-0.0" - case 6'010100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:0.0-0.0" - case 6'010101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:0.0-0.0" - case 6'010110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:0.0-0.0" - case 6'010111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:0.0-0.0" - case 6'011000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w - attribute \src "ls180.v:0.0-0.0" - case 6'011110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w - attribute \src "ls180.v:0.0-0.0" - case 6'011111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w - attribute \src "ls180.v:0.0-0.0" - case 6'100000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w - case - end - case - end - attribute \src "ls180.v:9224.2-9226.5" - switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9224.6-9224.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r - case - end - attribute \src "ls180.v:9227.2-9229.5" - switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9227.6-9227.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r - case - end - attribute \src "ls180.v:9230.2-9232.5" - switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9230.6-9230.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r - case - end - attribute \src "ls180.v:9233.2-9235.5" - switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9233.6-9233.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r - case - end - attribute \src "ls180.v:9237.2-9239.5" - switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9237.6-9237.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r - case - end - attribute \src "ls180.v:9240.2-9242.5" - switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9240.6-9240.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r - case - end - attribute \src "ls180.v:9243.2-9245.5" - switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9243.6-9243.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r - case - end - attribute \src "ls180.v:9246.2-9248.5" - switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9246.6-9246.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r - case - end - attribute \src "ls180.v:9250.2-9252.5" - switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9250.6-9250.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r - case - end - attribute \src "ls180.v:9253.2-9255.5" - switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9253.6-9253.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r - case - end - attribute \src "ls180.v:9257.2-9259.5" - switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9257.6-9257.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r - case - end - attribute \src "ls180.v:9260.2-9262.5" - switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9260.6-9260.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r - case - end - attribute \src "ls180.v:9263.2-9265.5" - switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9263.6-9263.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r - case - end - attribute \src "ls180.v:9266.2-9268.5" - switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9266.6-9266.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r - case - end - attribute \src "ls180.v:9271.2-9331.5" - switch \builder_csrbank7_sel - attribute \src "ls180.v:9271.6-9271.26" - case 1'1 - attribute \src "ls180.v:9272.3-9330.10" - switch \builder_interface7_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:0.0-0.0" - case 5'10001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:0.0-0.0" - case 5'10010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w - case - end - case - end - attribute \src "ls180.v:9332.2-9334.5" - switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9332.6-9332.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r - case - end - attribute \src "ls180.v:9335.2-9337.5" - switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9335.6-9335.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r - case - end - attribute \src "ls180.v:9338.2-9340.5" - switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9338.6-9338.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r - case - end - attribute \src "ls180.v:9341.2-9343.5" - switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9341.6-9341.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r - case - end - attribute \src "ls180.v:9344.2-9346.5" - switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9344.6-9344.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r - case - end - attribute \src "ls180.v:9347.2-9349.5" - switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9347.6-9347.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r - case - end - attribute \src "ls180.v:9350.2-9352.5" - switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9350.6-9350.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r - case - end - attribute \src "ls180.v:9353.2-9355.5" - switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9353.6-9353.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r - case - end - attribute \src "ls180.v:9357.2-9359.5" - switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9357.6-9357.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r - case - end - attribute \src "ls180.v:9360.2-9362.5" - switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9360.6-9360.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r - case - end - attribute \src "ls180.v:9363.2-9365.5" - switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9363.6-9363.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r - case - end - attribute \src "ls180.v:9366.2-9368.5" - switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9366.6-9366.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r - case - end - attribute \src "ls180.v:9370.2-9372.5" - switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9370.6-9370.37" - case 1'1 - assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r - case - end - attribute \src "ls180.v:9374.2-9376.5" - switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9374.6-9374.35" - case 1'1 - assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r - case - end - attribute \src "ls180.v:9379.2-9394.5" - switch \builder_csrbank8_sel - attribute \src "ls180.v:9379.6-9379.26" - case 1'1 - attribute \src "ls180.v:9380.3-9393.10" - switch \builder_interface8_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } - case - end - case - end - attribute \src "ls180.v:9395.2-9397.5" - switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9395.6-9395.42" - case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r - case - end - attribute \src "ls180.v:9398.2-9400.5" - switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9398.6-9398.42" - case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r - case - end - attribute \src "ls180.v:9403.2-9436.5" - switch \builder_csrbank9_sel - attribute \src "ls180.v:9403.6-9403.26" - case 1'1 - attribute \src "ls180.v:9404.3-9435.10" - switch \builder_interface9_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w - case - end - case - end - attribute \src "ls180.v:9437.2-9439.5" - switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9437.6-9437.39" - case 1'1 - assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r - case - end - attribute \src "ls180.v:9441.2-9443.5" - switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9441.6-9441.43" - case 1'1 - assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r - case - end - attribute \src "ls180.v:9445.2-9447.5" - switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9445.6-9445.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r - case - end - attribute \src "ls180.v:9448.2-9450.5" - switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9448.6-9448.43" - case 1'1 - assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r - case - end - attribute \src "ls180.v:9452.2-9454.5" - switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9452.6-9452.44" - case 1'1 - assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r - case - end - attribute \src "ls180.v:9456.2-9458.5" - switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9456.6-9456.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r - case - end - attribute \src "ls180.v:9459.2-9461.5" - switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9459.6-9459.42" - case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r - case - end - attribute \src "ls180.v:9464.2-9488.5" - switch \builder_csrbank10_sel - attribute \src "ls180.v:9464.6-9464.27" - case 1'1 - attribute \src "ls180.v:9465.3-9487.10" - switch \builder_interface10_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } - case - end - case - end - attribute \src "ls180.v:9489.2-9491.5" - switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9489.6-9489.35" - case 1'1 - assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r - case - end - attribute \src "ls180.v:9492.2-9494.5" - switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9492.6-9492.35" - case 1'1 - assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r - case - end - attribute \src "ls180.v:9496.2-9498.5" - switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9496.6-9496.32" - case 1'1 - assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r - case - end - attribute \src "ls180.v:9500.2-9502.5" - switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9500.6-9500.30" - case 1'1 - assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r - case - end - attribute \src "ls180.v:9504.2-9506.5" - switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9504.6-9504.36" - case 1'1 - assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r - case - end - attribute \src "ls180.v:9509.2-9539.5" - switch \builder_csrbank11_sel - attribute \src "ls180.v:9509.6-9509.27" - case 1'1 - attribute \src "ls180.v:9510.3-9538.10" - switch \builder_interface11_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w - case - end - case - end - attribute \src "ls180.v:9540.2-9542.5" - switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9540.6-9540.35" - case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r - case - end - attribute \src "ls180.v:9543.2-9545.5" - switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9543.6-9543.35" - case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r - case - end - attribute \src "ls180.v:9547.2-9549.5" - switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9547.6-9547.32" - case 1'1 - assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r - case - end - attribute \src "ls180.v:9551.2-9553.5" - switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9551.6-9551.30" - case 1'1 - assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r - case - end - attribute \src "ls180.v:9555.2-9557.5" - switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9555.6-9555.36" - case 1'1 - assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r - case - end - attribute \src "ls180.v:9559.2-9561.5" - switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9559.6-9559.39" - case 1'1 - assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r - case - end - attribute \src "ls180.v:9562.2-9564.5" - switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9562.6-9562.39" - case 1'1 - assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r - case - end - attribute \src "ls180.v:9567.2-9621.5" - switch \builder_csrbank12_sel - attribute \src "ls180.v:9567.6-9567.27" - case 1'1 - attribute \src "ls180.v:9568.3-9620.10" - switch \builder_interface12_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } - case - end - case - end - attribute \src "ls180.v:9622.2-9624.5" - switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9622.6-9622.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r - case - end - attribute \src "ls180.v:9625.2-9627.5" - switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9625.6-9625.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r - case - end - attribute \src "ls180.v:9628.2-9630.5" - switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9628.6-9628.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r - case - end - attribute \src "ls180.v:9631.2-9633.5" - switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9631.6-9631.32" - case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r - case - end - attribute \src "ls180.v:9635.2-9637.5" - switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9635.6-9635.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r - case - end - attribute \src "ls180.v:9638.2-9640.5" - switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9638.6-9638.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r - case - end - attribute \src "ls180.v:9641.2-9643.5" - switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9641.6-9641.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r - case - end - attribute \src "ls180.v:9644.2-9646.5" - switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9644.6-9644.34" - case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r - case - end - attribute \src "ls180.v:9648.2-9650.5" - switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9648.6-9648.30" - case 1'1 - assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r - case - end - attribute \src "ls180.v:9652.2-9654.5" - switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9652.6-9652.40" - case 1'1 - assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r - case - end - attribute \src "ls180.v:9656.2-9658.5" - switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9656.6-9656.37" - case 1'1 - assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r - case - end - attribute \src "ls180.v:9661.2-9688.5" - switch \builder_csrbank13_sel - attribute \src "ls180.v:9661.6-9661.27" - case 1'1 - attribute \src "ls180.v:9662.3-9687.10" - switch \builder_interface13_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } - case - end - case - end - attribute \src "ls180.v:9689.2-9691.5" - switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9689.6-9689.37" - case 1'1 - assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r - case - end - attribute \src "ls180.v:9694.2-9709.5" - switch \builder_csrbank14_sel - attribute \src "ls180.v:9694.6-9694.27" - case 1'1 - attribute \src "ls180.v:9695.3-9708.10" - switch \builder_interface14_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w - case - end - case - end - attribute \src "ls180.v:9710.2-9712.5" - switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:9710.6-9710.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r - case - end - attribute \src "ls180.v:9713.2-9715.5" - switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:9713.6-9713.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r - case - end - attribute \src "ls180.v:9716.2-9718.5" - switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:9716.6-9716.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r - case - end - attribute \src "ls180.v:9719.2-9721.5" - switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:9719.6-9719.39" - case 1'1 - assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r - case - end - attribute \src "ls180.v:9723.2-10017.5" - switch \sys_rst_1 - attribute \src "ls180.v:9723.6-9723.15" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] 1'0 - assign $0\main_libresocsim_reset_re[0:0] 1'0 - assign $0\main_libresocsim_scratch_storage[31:0] 305419896 - assign $0\main_libresocsim_scratch_re[0:0] 1'0 - assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\uart_tx[0:0] 1'1 - assign $0\spimaster_clk[0:0] 1'0 - assign $0\spimaster_mosi[0:0] 1'0 - assign $0\spimaster_cs_n[0:0] 1'0 - assign $0\pwm[1:0] 2'00 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\main_libresocsim_converter0_counter[0:0] 1'0 - assign $0\main_libresocsim_converter1_counter[0:0] 1'0 - assign $0\main_libresocsim_converter2_counter[0:0] 1'0 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_load_storage[31:0] 0 - assign $0\main_libresocsim_load_re[0:0] 1'0 - assign $0\main_libresocsim_reload_storage[31:0] 0 - assign $0\main_libresocsim_reload_re[0:0] 1'0 - assign $0\main_libresocsim_en_storage[0:0] 1'0 - assign $0\main_libresocsim_en_re[0:0] 1'0 - assign $0\main_libresocsim_update_value_storage[0:0] 1'0 - assign $0\main_libresocsim_update_value_re[0:0] 1'0 - assign $0\main_libresocsim_value_status[31:0] 0 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 - assign $0\main_libresocsim_value[31:0] 0 - assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 - assign $0\main_rddata_en[2:0] 3'000 - assign $0\main_sdram_storage[3:0] 4'0001 - assign $0\main_sdram_re[0:0] 1'0 - assign $0\main_sdram_command_storage[5:0] 6'000000 - assign $0\main_sdram_command_re[0:0] 1'0 - assign $0\main_sdram_address_re[0:0] 1'0 - assign $0\main_sdram_baddress_re[0:0] 1'0 - assign $0\main_sdram_wrdata_re[0:0] 1'0 - assign $0\main_sdram_status[15:0] 16'0000000000000000 - assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 - assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - assign $0\main_sdram_tccdcon_ready[0:0] 1'0 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - assign $0\main_sdram_twtrcon_count[2:0] 3'000 - assign $0\main_sdram_time0[4:0] 5'00000 - assign $0\main_sdram_time1[3:0] 4'0000 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - assign $0\main_uart_phy_storage[31:0] 9895604 - assign $0\main_uart_phy_re[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] 1'0 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_eventmanager_storage[1:0] 2'00 - assign $0\main_uart_eventmanager_re[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_oe_re[0:0] 1'0 - assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 - assign $0\main_gpio_out_re[0:0] 1'0 - assign $0\main_spimaster5_miso[7:0] 8'00000000 - assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 - assign $0\main_spimaster12_re[0:0] 1'0 - assign $0\main_spimaster17_re[0:0] 1'0 - assign $0\main_spimaster21_storage[0:0] 1'1 - assign $0\main_spimaster22_re[0:0] 1'0 - assign $0\main_spimaster23_storage[0:0] 1'0 - assign $0\main_spimaster24_re[0:0] 1'0 - assign $0\main_spimaster27_count[2:0] 3'000 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 - assign $0\main_spimaster34_mosi_sel[2:0] 3'000 - assign $0\main_spimaster35_miso_data[7:0] 8'00000000 - assign $0\main_spisdcard_miso[7:0] 8'00000000 - assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 - assign $0\main_spisdcard_control_re[0:0] 1'0 - assign $0\main_spisdcard_mosi_re[0:0] 1'0 - assign $0\main_spisdcard_cs_storage[0:0] 1'1 - assign $0\main_spisdcard_cs_re[0:0] 1'0 - assign $0\main_spisdcard_loopback_storage[0:0] 1'0 - assign $0\main_spisdcard_loopback_re[0:0] 1'0 - assign $0\main_spisdcard_count[2:0] 3'000 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 - assign $0\main_spisdcard_mosi_sel[2:0] 3'000 - assign $0\main_spisdcard_miso_data[7:0] 8'00000000 - assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 - assign $0\main_spimaster1_re[0:0] 1'0 - assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000 - assign $0\main_pwm0_enable_storage[0:0] 1'0 - assign $0\main_pwm0_enable_re[0:0] 1'0 - assign $0\main_pwm0_width_re[0:0] 1'0 - assign $0\main_pwm0_period_re[0:0] 1'0 - assign $0\main_pwm1_enable_storage[0:0] 1'0 - assign $0\main_pwm1_enable_re[0:0] 1'0 - assign $0\main_pwm1_width_re[0:0] 1'0 - assign $0\main_pwm1_period_re[0:0] 1'0 - assign $0\main_i2c_storage[2:0] 3'000 - assign $0\main_i2c_re[0:0] 1'0 - assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 - assign $0\main_sdphy_clocker_re[0:0] 1'0 - assign $0\main_sdphy_clocker_clk0[0:0] 1'0 - assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 - assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 - assign $0\main_sdphy_init_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_timeout[31:0] 500000 - assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - assign $0\main_sdphy_dataw_count[7:0] 8'00000000 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 - assign $0\main_sdphy_datar_timeout[31:0] 500000 - assign $0\main_sdphy_datar_count[9:0] 10'0000000000 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 - assign $0\main_sdcore_cmd_argument_storage[31:0] 0 - assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 - assign $0\main_sdcore_cmd_command_storage[31:0] 0 - assign $0\main_sdcore_cmd_command_re[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 - assign $0\main_sdcore_block_length_re[0:0] 1'0 - assign $0\main_sdcore_block_count_storage[31:0] 0 - assign $0\main_sdcore_block_count_re[0:0] 1'0 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - assign $0\main_sdcore_cmd_count[2:0] 3'000 - assign $0\main_sdcore_cmd_done[0:0] 1'0 - assign $0\main_sdcore_cmd_error[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout[0:0] 1'0 - assign $0\main_sdcore_data_count[31:0] 0 - assign $0\main_sdcore_data_done[0:0] 1'0 - assign $0\main_sdcore_data_error[0:0] 1'0 - assign $0\main_sdcore_data_timeout[0:0] 1'0 - assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 - assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 - assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[31:0] 0 - assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_length_storage[31:0] 0 - assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[1:0] 2'00 - assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 - assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 - assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 - assign $0\builder_converter0_state[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - assign $0\builder_refresher_state[1:0] 2'00 - assign $0\builder_bankmachine0_state[2:0] 3'000 - assign $0\builder_bankmachine1_state[2:0] 3'000 - assign $0\builder_bankmachine2_state[2:0] 3'000 - assign $0\builder_bankmachine3_state[2:0] 3'000 - assign $0\builder_multiplexer_state[2:0] 3'000 - assign $0\builder_new_master_wdata_ready[0:0] 1'0 - assign $0\builder_new_master_rdata_valid0[0:0] 1'0 - assign $0\builder_new_master_rdata_valid1[0:0] 1'0 - assign $0\builder_new_master_rdata_valid2[0:0] 1'0 - assign $0\builder_new_master_rdata_valid3[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - assign $0\builder_spimaster0_state[1:0] 2'00 - assign $0\builder_spimaster1_state[1:0] 2'00 - assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 - assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 - assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 - assign $0\builder_sdphy_fsm_state[2:0] 3'000 - assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - assign $0\builder_sdcore_fsm_state[2:0] 3'000 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - assign $0\builder_libresocsim_we[0:0] 1'0 - assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[4:0] 5'00000 - assign $0\builder_count[19:0] 20'11110100001001000000 - assign $0\builder_state[1:0] 2'00 - case - end - sync posedge \sys_clk_1 - update \uart_tx $0\uart_tx[0:0] - update \spimaster_clk $0\spimaster_clk[0:0] - update \spimaster_mosi $0\spimaster_mosi[0:0] - update \spimaster_cs_n $0\spimaster_cs_n[0:0] - update \pwm $0\pwm[1:0] - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] - update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] - update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] - update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] - update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] - update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] - update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] - update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] - update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] - update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] - update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] - update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] - update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] - update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] - update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] - update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] - update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] - update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] - update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] - update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] - update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] - update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] - update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] - update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] - update \main_libresocsim_value $0\main_libresocsim_value[31:0] - update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] - update \main_rddata_en $0\main_rddata_en[2:0] - update \main_sdram_storage $0\main_sdram_storage[3:0] - update \main_sdram_re $0\main_sdram_re[0:0] - update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] - update \main_sdram_command_re $0\main_sdram_command_re[0:0] - update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] - update \main_sdram_address_re $0\main_sdram_address_re[0:0] - update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] - update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] - update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] - update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] - update \main_sdram_status $0\main_sdram_status[15:0] - update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] - update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] - update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] - update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] - update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] - update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] - update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] - update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] - update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] - update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] - update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] - update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] - update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] - update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] - update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] - update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] - update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] - update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] - update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] - update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] - update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] - update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] - update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] - update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] - update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] - update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] - update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] - update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] - update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] - update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] - update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] - update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] - update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] - update \main_sdram_time0 $0\main_sdram_time0[4:0] - update \main_sdram_time1 $0\main_sdram_time1[3:0] - update \main_converter_counter $0\main_converter_counter[0:0] - update \main_converter_dat_r $0\main_converter_dat_r[31:0] - update \main_cmd_consumed $0\main_cmd_consumed[0:0] - update \main_wdata_consumed $0\main_wdata_consumed[0:0] - update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] - update \main_uart_phy_re $0\main_uart_phy_re[0:0] - update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] - update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] - update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] - update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] - update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] - update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] - update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] - update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] - update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] - update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] - update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] - update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] - update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] - update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] - update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] - update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] - update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] - update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] - update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] - update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] - update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] - update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] - update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] - update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] - update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] - update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] - update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] - update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] - update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] - update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] - update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] - update \main_gpio_out_re $0\main_gpio_out_re[0:0] - update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] - update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] - update \main_spimaster12_re $0\main_spimaster12_re[0:0] - update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] - update \main_spimaster17_re $0\main_spimaster17_re[0:0] - update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] - update \main_spimaster22_re $0\main_spimaster22_re[0:0] - update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] - update \main_spimaster24_re $0\main_spimaster24_re[0:0] - update \main_spimaster27_count $0\main_spimaster27_count[2:0] - update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] - update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] - update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] - update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] - update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] - update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] - update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] - update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] - update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] - update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] - update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] - update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] - update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] - update \main_spisdcard_count $0\main_spisdcard_count[2:0] - update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] - update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] - update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] - update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] - update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] - update \main_spimaster1_re $0\main_spimaster1_re[0:0] - update \main_dummy $0\main_dummy[35:0] - update \main_pwm0_counter $0\main_pwm0_counter[31:0] - update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] - update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] - update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] - update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] - update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] - update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] - update \main_pwm1_counter $0\main_pwm1_counter[31:0] - update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] - update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] - update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] - update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] - update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] - update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] - update \main_i2c_storage $0\main_i2c_storage[2:0] - update \main_i2c_re $0\main_i2c_re[0:0] - update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] - update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] - update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] - update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] - update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] - update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] - update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] - update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] - update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] - update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] - update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] - update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] - update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] - update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] - update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] - update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] - update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] - update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] - update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] - update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] - update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] - update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] - update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] - update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] - update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] - update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] - update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] - update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] - update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] - update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] - update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] - update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] - update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] - update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] - update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] - update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] - update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] - update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] - update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] - update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] - update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] - update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] - update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] - update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] - update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] - update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] - update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] - update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] - update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] - update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] - update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] - update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] - update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] - update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] - update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] - update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] - update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] - update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] - update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] - update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] - update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] - update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] - update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] - update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] - update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] - update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] - update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] - update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] - update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] - update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] - update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] - update \builder_converter0_state $0\builder_converter0_state[0:0] - update \builder_converter1_state $0\builder_converter1_state[0:0] - update \builder_converter2_state $0\builder_converter2_state[0:0] - update \builder_refresher_state $0\builder_refresher_state[1:0] - update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] - update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] - update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] - update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] - update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] - update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] - update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] - update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] - update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] - update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] - update \builder_converter_state $0\builder_converter_state[0:0] - update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] - update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] - update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] - update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] - update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] - update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] - update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] - update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] - update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] - update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] - update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] - update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] - update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] - update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] - update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] - update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] - update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] - update \builder_count $0\builder_count[19:0] - update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] - update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] - update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] - update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] - update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] - update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] - update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] - update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] - update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] - update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] - update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] - update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] - update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] - update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] - update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] - update \builder_state $0\builder_state[1:0] - update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] - update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] - update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] - update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] - update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] - update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] - update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] - update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] - update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] - update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] - update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] - update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] - update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] - update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] - update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] - update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] - update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] - update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] - update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] - update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] - update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] - update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] - update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] - update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] - update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] - update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] - update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] - update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] - update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] - update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] - update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] - update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] - update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] - update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] - end - attribute \src "ls180.v:743.5-743.43" - process $proc$ls180.v:743$3052 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] - sync init - end - attribute \src "ls180.v:746.5-746.49" - process $proc$ls180.v:746$3053 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:747.5-747.49" - process $proc$ls180.v:747$3054 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:748.5-748.48" - process $proc$ls180.v:748$3055 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:75.5-75.46" - process $proc$ls180.v:75$2782 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] - sync init - end - attribute \src "ls180.v:752.11-752.46" - process $proc$ls180.v:752$3056 - assign { } { } - assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:754.11-754.45" - process $proc$ls180.v:754$3057 - assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] - end - attribute \src "ls180.v:756.5-756.44" - process $proc$ls180.v:756$3058 - assign { } { } - assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] - end - attribute \src "ls180.v:757.5-757.45" - process $proc$ls180.v:757$3059 - assign { } { } - assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] - end - attribute \src "ls180.v:759.5-759.48" - process $proc$ls180.v:759$3060 - assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] - end - attribute \src "ls180.v:761.5-761.43" - process $proc$ls180.v:761$3061 - assign { } { } - assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] - end - attribute \src "ls180.v:764.5-764.49" - process $proc$ls180.v:764$3062 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:765.5-765.49" - process $proc$ls180.v:765$3063 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:766.5-766.48" - process $proc$ls180.v:766$3064 - assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:770.11-770.46" - process $proc$ls180.v:770$3065 - assign { } { } - assign $1\main_sdram_choose_req_valids[3:0] 4'0000 - sync always - sync init - update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:772.11-772.45" - process $proc$ls180.v:772$3066 - assign { } { } - assign $1\main_sdram_choose_req_grant[1:0] 2'00 - sync always - sync init - update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] - end - attribute \src "ls180.v:774.12-774.36" - process $proc$ls180.v:774$3067 - assign { } { } - assign $0\main_sdram_nop_a[12:0] 13'0000000000000 - sync always - update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] - sync init - end - attribute \src "ls180.v:775.11-775.35" - process $proc$ls180.v:775$3068 - assign { } { } - assign $0\main_sdram_nop_ba[1:0] 2'00 - sync always - update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] - sync init - end - attribute \src "ls180.v:776.11-776.40" - process $proc$ls180.v:776$3069 - assign { } { } - assign $1\main_sdram_steerer_sel[1:0] 2'00 - sync always - sync init - update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] - end - attribute \src "ls180.v:777.5-777.31" - process $proc$ls180.v:777$3070 - assign { } { } - assign $0\main_sdram_steerer0[0:0] 1'1 - sync always - update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] - sync init - end - attribute \src "ls180.v:778.5-778.31" - process $proc$ls180.v:778$3071 - assign { } { } - assign $0\main_sdram_steerer1[0:0] 1'1 - sync always - update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] - sync init - end - attribute \src "ls180.v:780.32-780.63" - process $proc$ls180.v:780$3072 - assign { } { } - assign $0\main_sdram_trrdcon_ready[0:0] 1'1 - sync always - update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] - sync init - end - attribute \src "ls180.v:782.32-782.63" - process $proc$ls180.v:782$3073 - assign { } { } - assign $0\main_sdram_tfawcon_ready[0:0] 1'1 - sync always - update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] - sync init - end - attribute \src "ls180.v:784.32-784.63" - process $proc$ls180.v:784$3074 - assign { } { } - assign $1\main_sdram_tccdcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] - end - attribute \src "ls180.v:785.5-785.36" - process $proc$ls180.v:785$3075 - assign { } { } - assign $1\main_sdram_tccdcon_count[0:0] 1'0 - sync always - sync init - update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] - end - attribute \src "ls180.v:787.32-787.63" - process $proc$ls180.v:787$3076 - assign { } { } - assign $1\main_sdram_twtrcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] - end - attribute \src "ls180.v:788.11-788.42" - process $proc$ls180.v:788$3077 - assign { } { } - assign $1\main_sdram_twtrcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] - end - attribute \src "ls180.v:791.5-791.26" - process $proc$ls180.v:791$3078 - assign { } { } - assign $1\main_sdram_en0[0:0] 1'0 - sync always - sync init - update \main_sdram_en0 $1\main_sdram_en0[0:0] - end - attribute \src "ls180.v:793.11-793.34" - process $proc$ls180.v:793$3079 - assign { } { } - assign $1\main_sdram_time0[4:0] 5'00000 - sync always - sync init - update \main_sdram_time0 $1\main_sdram_time0[4:0] - end - attribute \src "ls180.v:794.5-794.26" - process $proc$ls180.v:794$3080 - assign { } { } - assign $1\main_sdram_en1[0:0] 1'0 - sync always - sync init - update \main_sdram_en1 $1\main_sdram_en1[0:0] - end - attribute \src "ls180.v:796.11-796.34" - process $proc$ls180.v:796$3081 - assign { } { } - assign $1\main_sdram_time1[3:0] 4'0000 - sync always - sync init - update \main_sdram_time1 $1\main_sdram_time1[3:0] - end - attribute \src "ls180.v:817.5-817.29" - process $proc$ls180.v:817$3082 - assign { } { } - assign $1\main_wb_sdram_ack[0:0] 1'0 - sync always - sync init - update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] - end - attribute \src "ls180.v:82.5-82.46" - process $proc$ls180.v:82$2783 - assign { } { } - assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] - end - attribute \src "ls180.v:821.5-821.29" - process $proc$ls180.v:821$3083 - assign { } { } - assign $0\main_wb_sdram_err[0:0] 1'0 - sync always - update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] - sync init - end - attribute \src "ls180.v:822.12-822.40" - process $proc$ls180.v:822$3084 - assign { } { } - assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - sync always - sync init - update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] - end - attribute \src "ls180.v:823.12-823.42" - process $proc$ls180.v:823$3085 - assign { } { } - assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - sync always - sync init - update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] - end - attribute \src "ls180.v:825.11-825.38" - process $proc$ls180.v:825$3086 - assign { } { } - assign $1\main_litedram_wb_sel[1:0] 2'00 - sync always - sync init - update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] - end - attribute \src "ls180.v:826.5-826.32" - process $proc$ls180.v:826$3087 - assign { } { } - assign $1\main_litedram_wb_cyc[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] - end - attribute \src "ls180.v:827.5-827.32" - process $proc$ls180.v:827$3088 - assign { } { } - assign $1\main_litedram_wb_stb[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] - end - attribute \src "ls180.v:829.5-829.31" - process $proc$ls180.v:829$3089 - assign { } { } - assign $1\main_litedram_wb_we[0:0] 1'0 - sync always - sync init - update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] - end - attribute \src "ls180.v:830.5-830.31" - process $proc$ls180.v:830$3090 - assign { } { } - assign $1\main_converter_skip[0:0] 1'0 - sync always - sync init - update \main_converter_skip $1\main_converter_skip[0:0] - end - attribute \src "ls180.v:831.5-831.34" - process $proc$ls180.v:831$3091 - assign { } { } - assign $1\main_converter_counter[0:0] 1'0 - sync always - sync init - update \main_converter_counter $1\main_converter_counter[0:0] - end - attribute \src "ls180.v:833.12-833.40" - process $proc$ls180.v:833$3092 - assign { } { } - assign $1\main_converter_dat_r[31:0] 0 - sync always - sync init - update \main_converter_dat_r $1\main_converter_dat_r[31:0] - end - attribute \src "ls180.v:834.5-834.29" - process $proc$ls180.v:834$3093 - assign { } { } - assign $1\main_cmd_consumed[0:0] 1'0 - sync always - sync init - update \main_cmd_consumed $1\main_cmd_consumed[0:0] - end - attribute \src "ls180.v:835.5-835.31" - process $proc$ls180.v:835$3094 - assign { } { } - assign $1\main_wdata_consumed[0:0] 1'0 - sync always - sync init - update \main_wdata_consumed $1\main_wdata_consumed[0:0] - end - attribute \src "ls180.v:839.12-839.47" - process $proc$ls180.v:839$3095 - assign { } { } - assign $1\main_uart_phy_storage[31:0] 9895604 - sync always - sync init - update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] - end - attribute \src "ls180.v:840.5-840.28" - process $proc$ls180.v:840$3096 - assign { } { } - assign $1\main_uart_phy_re[0:0] 1'0 - sync always - sync init - update \main_uart_phy_re $1\main_uart_phy_re[0:0] - end - attribute \src "ls180.v:842.5-842.36" - process $proc$ls180.v:842$3097 - assign { } { } - assign $1\main_uart_phy_sink_ready[0:0] 1'0 - sync always - sync init - update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] - end - attribute \src "ls180.v:846.5-846.39" - process $proc$ls180.v:846$3098 - assign { } { } - assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 - sync always - sync init - update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] - end - attribute \src "ls180.v:847.12-847.54" - process $proc$ls180.v:847$3099 - assign { } { } - assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 - sync always - sync init - update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] - end - attribute \src "ls180.v:848.11-848.38" - process $proc$ls180.v:848$3100 - assign { } { } - assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] - end - attribute \src "ls180.v:849.11-849.43" - process $proc$ls180.v:849$3101 - assign { } { } - assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] - end - attribute \src "ls180.v:850.5-850.33" - process $proc$ls180.v:850$3102 - assign { } { } - assign $1\main_uart_phy_tx_busy[0:0] 1'0 - sync always - sync init - update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] - end - attribute \src "ls180.v:851.5-851.38" - process $proc$ls180.v:851$3103 - assign { } { } - assign $1\main_uart_phy_source_valid[0:0] 1'0 - sync always - sync init - update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] - end - attribute \src "ls180.v:853.5-853.38" - process $proc$ls180.v:853$3104 - assign { } { } - assign $0\main_uart_phy_source_first[0:0] 1'0 - sync always - update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] - sync init - end - attribute \src "ls180.v:854.5-854.37" - process $proc$ls180.v:854$3105 - assign { } { } - assign $0\main_uart_phy_source_last[0:0] 1'0 - sync always - update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] - sync init - end - attribute \src "ls180.v:855.11-855.51" - process $proc$ls180.v:855$3106 - assign { } { } - assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] - end - attribute \src "ls180.v:856.5-856.39" - process $proc$ls180.v:856$3107 - assign { } { } - assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 - sync always - sync init - update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] - end - attribute \src "ls180.v:857.12-857.54" - process $proc$ls180.v:857$3108 - assign { } { } - assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 - sync always - sync init - update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] - end - attribute \src "ls180.v:859.5-859.30" - process $proc$ls180.v:859$3109 - assign { } { } - assign $1\main_uart_phy_rx_r[0:0] 1'0 - sync always - sync init - update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] - end - attribute \src "ls180.v:86.5-86.46" - process $proc$ls180.v:86$2784 - assign { } { } - assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] - sync init - end - attribute \src "ls180.v:860.11-860.38" - process $proc$ls180.v:860$3110 - assign { } { } - assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 - sync always - sync init - update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] - end - attribute \src "ls180.v:861.11-861.43" - process $proc$ls180.v:861$3111 - assign { } { } - assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 - sync always - sync init - update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] - end - attribute \src "ls180.v:862.5-862.33" - process $proc$ls180.v:862$3112 - assign { } { } - assign $1\main_uart_phy_rx_busy[0:0] 1'0 - sync always - sync init - update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] - end - attribute \src "ls180.v:873.5-873.32" - process $proc$ls180.v:873$3113 - assign { } { } - assign $1\main_uart_tx_pending[0:0] 1'0 - sync always - sync init - update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] - end - attribute \src "ls180.v:875.5-875.30" - process $proc$ls180.v:875$3114 - assign { } { } - assign $1\main_uart_tx_clear[0:0] 1'0 - sync always - sync init - update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] - end - attribute \src "ls180.v:876.5-876.36" - process $proc$ls180.v:876$3115 - assign { } { } - assign $1\main_uart_tx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] - end - attribute \src "ls180.v:878.5-878.32" - process $proc$ls180.v:878$3116 - assign { } { } - assign $1\main_uart_rx_pending[0:0] 1'0 - sync always - sync init - update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] - end - attribute \src "ls180.v:880.5-880.30" - process $proc$ls180.v:880$3117 - assign { } { } - assign $1\main_uart_rx_clear[0:0] 1'0 - sync always - sync init - update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] - end - attribute \src "ls180.v:881.5-881.36" - process $proc$ls180.v:881$3118 - assign { } { } - assign $1\main_uart_rx_old_trigger[0:0] 1'0 - sync always - sync init - update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] - end - attribute \src "ls180.v:885.11-885.49" - process $proc$ls180.v:885$3119 - assign { } { } - assign $1\main_uart_eventmanager_status_w[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:889.11-889.50" - process $proc$ls180.v:889$3120 - assign { } { } - assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] - end - attribute \src "ls180.v:890.11-890.48" - process $proc$ls180.v:890$3121 - assign { } { } - assign $1\main_uart_eventmanager_storage[1:0] 2'00 - sync always - sync init - update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] - end - attribute \src "ls180.v:891.5-891.37" - process $proc$ls180.v:891$3122 - assign { } { } - assign $1\main_uart_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] - end - attribute \src "ls180.v:908.5-908.40" - process $proc$ls180.v:908$3123 - assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] - sync init - end - attribute \src "ls180.v:909.5-909.39" - process $proc$ls180.v:909$3124 - assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 - sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] - sync init - end - attribute \src "ls180.v:917.5-917.38" - process $proc$ls180.v:917$3125 - assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] - end - attribute \src "ls180.v:924.11-924.42" - process $proc$ls180.v:924$3126 - assign { } { } - assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] - end - attribute \src "ls180.v:925.5-925.37" - process $proc$ls180.v:925$3127 - assign { } { } - assign $0\main_uart_tx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:926.11-926.43" - process $proc$ls180.v:926$3128 - assign { } { } - assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] - end - attribute \src "ls180.v:927.11-927.43" - process $proc$ls180.v:927$3129 - assign { } { } - assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] - end - attribute \src "ls180.v:928.11-928.46" - process $proc$ls180.v:928$3130 - assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:954.5-954.38" - process $proc$ls180.v:954$3131 - assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 - sync always - sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] - end - attribute \src "ls180.v:961.11-961.42" - process $proc$ls180.v:961$3132 - assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 - sync always - sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] - end - attribute \src "ls180.v:962.5-962.37" - process $proc$ls180.v:962$3133 - assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 - sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:963.11-963.43" - process $proc$ls180.v:963$3134 - assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] - end - attribute \src "ls180.v:964.11-964.43" - process $proc$ls180.v:964$3135 - assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] - end - attribute \src "ls180.v:965.11-965.46" - process $proc$ls180.v:965$3136 - assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - sync always - sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:980.5-980.27" - process $proc$ls180.v:980$3137 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:981.12-981.40" - process $proc$ls180.v:981$3138 - assign { } { } - assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] - end - attribute \src "ls180.v:982.5-982.27" - process $proc$ls180.v:982$3139 - assign { } { } - assign $1\main_gpio_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] - end - attribute \src "ls180.v:983.12-983.36" - process $proc$ls180.v:983$3140 - assign { } { } - assign $1\main_gpio_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_status $1\main_gpio_status[15:0] - end - attribute \src "ls180.v:985.12-985.41" - process $proc$ls180.v:985$3141 - assign { } { } - assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] - end - attribute \src "ls180.v:986.5-986.28" - process $proc$ls180.v:986$3142 - assign { } { } - assign $1\main_gpio_out_re[0:0] 1'0 - sync always - sync init - update \main_gpio_out_re $1\main_gpio_out_re[0:0] - end - attribute \src "ls180.v:992.5-992.32" - process $proc$ls180.v:992$3143 - assign { } { } - assign $1\main_spimaster2_done[0:0] 1'0 - sync always - sync init - update \main_spimaster2_done $1\main_spimaster2_done[0:0] - end - attribute \src "ls180.v:993.5-993.31" - process $proc$ls180.v:993$3144 - assign { } { } - assign $1\main_spimaster3_irq[0:0] 1'0 - sync always - sync init - update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] - end - attribute \src "ls180.v:995.11-995.38" - process $proc$ls180.v:995$3145 - assign { } { } - assign $1\main_spimaster5_miso[7:0] 8'00000000 - sync always - sync init - update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] - end - attribute \src "ls180.v:998.12-998.47" - process $proc$ls180.v:998$3146 - assign { } { } - assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 - sync always - update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] - sync init - end - attribute \src "ls180.v:999.5-999.33" - process $proc$ls180.v:999$3147 - assign { } { } - assign $1\main_spimaster9_start[0:0] 1'0 - sync always - sync init - update \main_spimaster9_start $1\main_spimaster9_start[0:0] - end - connect \main_libresocsim_libresoc_reset \main_libresocsim_reset - connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i - connect \sys_pll_48_o \main_libresocsim_libresoc_pll_48_o - connect \main_libresocsim_libresoc_jtag_tck \jtag_tck - connect \main_libresocsim_libresoc_jtag_tms \jtag_tms - connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi - connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo - connect \main_nc \nc - connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid - connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 - connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first - connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last - connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data - connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 - connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready - connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 - connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 - connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 - connect \main_libresocsim_bus_error \builder_error - connect \main_libresocsim_converter0_reset $not$ls180.v:2774$14_Y - connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } - connect \main_libresocsim_converter1_reset $not$ls180.v:2834$25_Y - connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } - connect \main_libresocsim_converter2_reset $not$ls180.v:2894$36_Y - connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } - connect \main_libresocsim_reset \main_libresocsim_reset_re - connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] - connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r - connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:2966$60_Y - connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status - connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:2975$63_Y - connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \sys_clk_1 \sys_clk - connect \por_clk \sys_clk - connect \sys_rst_1 \main_int_rst - connect \main_dfi_p0_address \main_sdram_master_p0_address - connect \main_dfi_p0_bank \main_sdram_master_p0_bank - connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n - connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n - connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n - connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n - connect \main_dfi_p0_cke \main_sdram_master_p0_cke - connect \main_dfi_p0_odt \main_sdram_master_p0_odt - connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n - connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n - connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata - connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en - connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask - connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en - connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata - connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid - connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address - connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank - connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n - connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n - connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n - connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n - connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke - connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt - connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n - connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n - connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata - connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en - connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask - connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en - connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata - connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid - connect \main_sdram_inti_p0_cke \main_sdram_cke - connect \main_sdram_inti_p0_odt \main_sdram_odt - connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n - connect \main_sdram_inti_p0_address \main_sdram_address_storage - connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3089$70_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3090$71_Y - connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage - connect \main_sdram_inti_p0_wrdata_mask 2'00 - connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid - connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready - connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we - connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr - connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock - connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready - connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid - connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid - connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready - connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we - connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr - connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock - connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready - connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid - connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid - connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready - connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we - connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr - connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock - connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready - connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid - connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid - connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready - connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we - connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr - connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock - connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready - connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3121$72_Y - connect \main_sdram_postponer_req_i \main_sdram_timer_done0 - connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3124$73_Y - connect \main_sdram_timer_done0 \main_sdram_timer_done1 - connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3127$75_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3128$77_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid - connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr - connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3170$79_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3171$80_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3172$81_Y - connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3182$86_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3183$88_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3184$90_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3216$98_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3217$99_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3220$100_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3221$101_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3222$103_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid - connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr - connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3327$109_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3328$110_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3329$111_Y - connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3339$116_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3340$118_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3341$120_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3373$128_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3374$129_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3377$130_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3378$131_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3379$133_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid - connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr - connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3484$139_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3485$140_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3486$141_Y - connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3496$146_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3497$148_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3498$150_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3530$158_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3531$159_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3534$160_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3535$161_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3536$163_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid - connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr - connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3641$169_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3642$170_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3643$171_Y - connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3653$176_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3654$178_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3655$180_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3687$188_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3688$189_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3691$190_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3692$191_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3693$193_Y - connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3789$204_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3790$210_Y - connect \main_sdram_ras_allowed $and$ls180.v:3791$211_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3792$214_Y - connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3794$216_Y - connect \main_sdram_read_available $or$ls180.v:3795$223_Y - connect \main_sdram_write_available $or$ls180.v:3796$230_Y - connect \main_sdram_max_time0 $eq$ls180.v:3797$231_Y - connect \main_sdram_max_time1 $eq$ls180.v:3798$232_Y - connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3803$235_Y - connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata - connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3806$236_Y - connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids - connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 - connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 - connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 - connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 - connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 - connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3839$294_Y - connect \main_sdram_choose_req_request \main_sdram_choose_req_valids - connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 - connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 - connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 - connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 - connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 - connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3908$380_Y - connect \main_sdram_dfi_p0_reset_n 1'1 - connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 - connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:3985$412_Y - connect \builder_roundrobin0_ce $and$ls180.v:3986$415_Y - connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 - connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 - connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:3990$428_Y - connect \builder_roundrobin1_ce $and$ls180.v:3991$431_Y - connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 - connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 - connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:3995$444_Y - connect \builder_roundrobin2_ce $and$ls180.v:3996$447_Y - connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 - connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 - connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4000$460_Y - connect \builder_roundrobin3_ce $and$ls180.v:4001$463_Y - connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 - connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 - connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4005$527_Y - connect \main_port_wdata_ready \builder_new_master_wdata_ready - connect \main_port_rdata_valid \builder_new_master_rdata_valid3 - connect \main_port_rdata_payload_data \main_sdram_interface_rdata - connect \builder_roundrobin0_grant 1'0 - connect \builder_roundrobin1_grant 1'0 - connect \builder_roundrobin2_grant 1'0 - connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4027$529_Y - connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4087$540_Y [23:0] - connect \main_port_cmd_payload_we \main_litedram_wb_we - connect \main_port_wdata_payload_data \main_litedram_wb_dat_w - connect \main_port_wdata_payload_we \main_litedram_wb_sel - connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4092$541_Y - connect \main_port_cmd_last $not$ls180.v:4093$542_Y - connect \main_port_cmd_valid $and$ls180.v:4094$545_Y - connect \main_port_wdata_valid $and$ls180.v:4095$549_Y - connect \main_port_rdata_ready $and$ls180.v:4096$552_Y - connect \main_litedram_wb_ack $and$ls180.v:4097$557_Y - connect \main_ack_cmd $or$ls180.v:4098$559_Y - connect \main_ack_wdata $or$ls180.v:4099$561_Y - connect \main_ack_rdata $and$ls180.v:4100$562_Y - connect \main_uart_uart_sink_valid \main_uart_phy_source_valid - connect \main_uart_phy_source_ready \main_uart_uart_sink_ready - connect \main_uart_uart_sink_first \main_uart_phy_source_first - connect \main_uart_uart_sink_last \main_uart_phy_source_last - connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data - connect \main_uart_phy_sink_valid \main_uart_uart_source_valid - connect \main_uart_uart_source_ready \main_uart_phy_sink_ready - connect \main_uart_phy_sink_first \main_uart_uart_source_first - connect \main_uart_phy_sink_last \main_uart_uart_source_last - connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data - connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re - connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4113$563_Y - connect \main_uart_txempty_status $not$ls180.v:4114$564_Y - connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid - connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready - connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first - connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last - connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4120$565_Y - connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid - connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready - connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first - connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last - connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4126$566_Y - connect \main_uart_rxfull_status $not$ls180.v:4127$567_Y - connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4129$569_Y - connect \main_uart_rx_trigger $not$ls180.v:4130$570_Y - connect \main_uart_irq $or$ls180.v:4153$579_Y - connect \main_uart_tx_status \main_uart_tx_trigger - connect \main_uart_rx_status \main_uart_rx_trigger - connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } - connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout - connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable - connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid - connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first - connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last - connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data - connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable - connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first - connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last - connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data - connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4168$582_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4169$583_Y - connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4179$587_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4180$588_Y - connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume - connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r - connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4184$589_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4185$590_Y - connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } - connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout - connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable - connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid - connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first - connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last - connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data - connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable - connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first - connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last - connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data - connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4198$593_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4199$594_Y - connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4209$598_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4210$599_Y - connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume - connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r - connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4214$600_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4215$601_Y - connect \main_gpio_pads_i \gpio_i - connect \gpio_o \main_gpio_pads_o - connect \gpio_oe \main_gpio_pads_oe - connect \main_gpio_pads_oe \main_gpio_oe_storage - connect \main_gpio_pads_o \main_gpio_out_storage - connect \main_spimaster0_start \main_spimaster9_start - connect \main_spimaster1_length \main_spimaster10_length - connect \main_spimaster4_mosi \main_spimaster16_storage - connect \main_spimaster13_done \main_spimaster2_done - connect \main_spimaster18_status \main_spimaster5_miso - connect \main_spimaster6_cs \main_spimaster21_storage - connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4228$603_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4229$605_Y - connect \main_spisdcard_start0 \main_spisdcard_start1 - connect \main_spisdcard_length0 \main_spisdcard_length1 - connect \main_spisdcard_mosi \main_spisdcard_mosi_storage - connect \main_spisdcard_done1 \main_spisdcard_done0 - connect \main_spisdcard_miso_status \main_spisdcard_miso - connect \main_spisdcard_cs \main_spisdcard_cs_storage - connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4286$611_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4287$613_Y - connect \main_spisdcard_clk_divider0 \main_spimaster1_storage - connect \i2c_scl \main_i2c_scl - connect \i2c_sda_oe \main_i2c_oe - connect \i2c_sda_o \main_i2c_sda0 - connect \main_i2c_sda1 \i2c_sda_i - connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4343$621_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4344$625_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4345$629_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4346$633_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4347$637_Y - connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4368$638_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4398$641_Y - connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid - connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready - connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first - connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last - connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4521$651_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4522$653_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 - connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready - connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 - connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 - connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 - connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid - connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 - connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data - connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid - connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 - connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4539$655_Y - connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4541$656_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4542$658_Y - connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid - connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready - connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first - connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last - connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i - connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o - connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4648$673_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4649$674_Y - connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 - connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready - connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 - connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 - connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 - connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid - connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 - connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first - connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data - connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid - connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 - connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first - connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4666$676_Y - connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4668$677_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4669$679_Y - connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid - connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready - connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first - connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last - connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk - connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i - connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o - connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4782$688_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4783$689_Y - connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i - connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 - connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready - connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 - connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 - connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 - connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid - connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 - connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first - connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last - connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data - connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid - connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 - connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first - connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last - connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4800$691_Y - connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4802$692_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4803$694_Y - connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid - connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready - connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first - connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last - connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data - connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid - connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready - connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first - connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last - connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data - connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] - connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] - connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4919$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } - connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } - connect \main_sdcore_crc7_inserter_clr 1'1 - connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4923$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4923$710_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4924$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4924$713_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4925$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4925$716_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4926$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4926$719_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4927$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4927$722_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4928$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4928$725_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4929$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4929$728_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4930$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4930$731_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4931$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4931$734_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4932$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4932$737_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4933$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4933$740_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4934$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4934$743_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4935$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4935$746_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4936$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4936$749_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4937$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4937$752_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4938$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4938$755_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4939$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4939$758_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4940$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4940$761_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4941$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4941$764_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4942$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4942$767_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4943$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4943$770_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4944$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4944$773_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4945$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4945$776_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4946$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4946$779_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4947$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4947$782_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4948$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4948$785_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4949$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4949$788_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4950$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4950$791_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4951$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4951$794_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4952$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4952$797_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4953$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4953$800_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4954$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4954$803_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4955$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4955$806_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4956$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4956$809_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4957$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4957$812_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4958$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4958$815_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4959$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4959$818_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4960$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4960$821_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4961$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4961$824_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4962$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4962$827_Y } - connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4972$832_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4973$833_Y - connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4975$835_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4976$836_Y - connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4978$838_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4979$839_Y - connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4981$841_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4982$842_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4983$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4983$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4983$843_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4984$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4984$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4984$848_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4993$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4993$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4993$854_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4994$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4994$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4994$859_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5003$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5003$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5003$865_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5004$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5004$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5004$870_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5013$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5013$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5013$876_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5014$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5014$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5014$881_Y } - connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5110$901_Y - connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5120$904_Y - connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5130$907_Y - connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5140$910_Y - connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val - connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5165$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5165$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5165$918_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5166$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5166$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5166$923_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5175$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5175$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5175$929_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5176$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5176$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5176$934_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5185$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5185$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5185$940_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5186$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5186$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5186$945_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5195$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5195$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5195$951_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5196$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5196$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5196$956_Y } - connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 - connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready - connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first - connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last - connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 - connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid - connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready - connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first - connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last - connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data - connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid - connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first - connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last - connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data - connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } - connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout - connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable - connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid - connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first - connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last - connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data - connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable - connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first - connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last - connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data - connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready - connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5432$990_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5433$991_Y - connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume - connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5436$992_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5437$993_Y - connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid - connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready - connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first - connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last - connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5443$995_Y - connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5445$996_Y - connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 4'1111 - connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } - connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] - connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5455$997_Y - connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid - connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready - connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first - connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last - connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data - connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 - connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready - connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 - connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 - connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 - connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid - connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 - connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first - connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last - connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] - connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } - connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5514$1004_Y - connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid - connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 - connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first - connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last - connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5595$1012_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5596$1013_Y - connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5598$1014_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5599$1015_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5600$1016_Y - connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last - connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } - connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout - connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable - connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid - connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first - connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last - connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data - connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable - connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first - connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last - connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data - connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready - connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5640$1021_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5641$1022_Y - connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume - connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5644$1023_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5645$1024_Y - connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 - connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 - connect \builder_shared_stb \builder_comb_rhs_array_muxed28 - connect \builder_shared_we \builder_comb_rhs_array_muxed29 - connect \builder_shared_cti \builder_comb_rhs_array_muxed30 - connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r - connect \main_interface0_bus_dat_r \builder_shared_dat_r - connect \main_interface1_bus_dat_r \builder_shared_dat_r - connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5696$1030_Y - connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5697$1032_Y - connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5698$1034_Y - connect \main_interface0_bus_ack $and$ls180.v:5699$1036_Y - connect \main_interface1_bus_ack $and$ls180.v:5700$1038_Y - connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5701$1040_Y - connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5702$1042_Y - connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5703$1044_Y - connect \main_interface0_bus_err $and$ls180.v:5704$1046_Y - connect \main_interface1_bus_err $and$ls180.v:5705$1048_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } - connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w - connect \main_libresocsim_ram_bus_sel \builder_shared_sel - connect \main_libresocsim_ram_bus_stb \builder_shared_stb - connect \main_libresocsim_ram_bus_we \builder_shared_we - connect \main_libresocsim_ram_bus_cti \builder_shared_cti - connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte - connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr - connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w - connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel - connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb - connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we - connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti - connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte - connect \main_wb_sdram_adr \builder_shared_adr - connect \main_wb_sdram_dat_w \builder_shared_dat_w - connect \main_wb_sdram_sel \builder_shared_sel - connect \main_wb_sdram_stb \builder_shared_stb - connect \main_wb_sdram_we \builder_shared_we - connect \main_wb_sdram_cti \builder_shared_cti - connect \main_wb_sdram_bte \builder_shared_bte - connect \builder_libresocsim_wishbone_adr \builder_shared_adr - connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w - connect \builder_libresocsim_wishbone_sel \builder_shared_sel - connect \builder_libresocsim_wishbone_stb \builder_shared_stb - connect \builder_libresocsim_wishbone_we \builder_shared_we - connect \builder_libresocsim_wishbone_cti \builder_shared_cti - connect \builder_libresocsim_wishbone_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5750$1055_Y - connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5751$1056_Y - connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5752$1057_Y - connect \main_wb_sdram_cyc $and$ls180.v:5753$1058_Y - connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5754$1059_Y - connect \builder_shared_err $or$ls180.v:5755$1063_Y - connect \builder_wait $and$ls180.v:5756$1066_Y - connect \builder_done $eq$ls180.v:5769$1081_Y - connect \builder_csrbank0_sel $eq$ls180.v:5770$1082_Y - connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5772$1085_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5773$1089_Y - connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5775$1092_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5776$1096_Y - connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5778$1099_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5779$1103_Y - connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5781$1106_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5782$1110_Y - connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5784$1113_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5785$1117_Y - connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5787$1120_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5788$1124_Y - connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5790$1127_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5791$1131_Y - connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5793$1134_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5794$1138_Y - connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5796$1141_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5797$1145_Y - connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage - connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] - connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] - connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] - connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] - connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] - connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] - connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] - connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] - connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5808$1146_Y - connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5810$1149_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5811$1153_Y - connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5813$1156_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5814$1160_Y - connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5816$1163_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5817$1167_Y - connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5819$1170_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5820$1174_Y - connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5822$1177_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5823$1181_Y - connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5825$1184_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5826$1188_Y - connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] - connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] - connect \builder_csrbank1_in1_w \main_gpio_status [15:8] - connect \builder_csrbank1_in0_w \main_gpio_status [7:0] - connect \main_gpio_we \builder_csrbank1_in0_we - connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] - connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5834$1189_Y - connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:5836$1192_Y - connect \builder_csrbank2_w0_we $and$ls180.v:5837$1196_Y - connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:5839$1199_Y - connect \builder_csrbank2_r_we $and$ls180.v:5840$1203_Y - connect \main_i2c_scl \main_i2c_storage [0] - connect \main_i2c_oe \main_i2c_storage [1] - connect \main_i2c_sda0 \main_i2c_storage [2] - connect \builder_csrbank2_w0_w \main_i2c_storage - connect \main_i2c_status \main_i2c_sda1 - connect \builder_csrbank2_r_w \main_i2c_status - connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:5848$1204_Y - connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5850$1207_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5851$1211_Y - connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5853$1214_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5854$1218_Y - connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5856$1221_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5857$1225_Y - connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5859$1228_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5860$1232_Y - connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5862$1235_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5863$1239_Y - connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5865$1242_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5866$1246_Y - connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5868$1249_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5869$1253_Y - connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5871$1256_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5872$1260_Y - connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5874$1263_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5875$1267_Y - connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage - connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] - connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] - connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] - connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] - connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] - connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] - connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] - connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5885$1268_Y - connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:5887$1271_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:5888$1275_Y - connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:5890$1278_Y - connect \builder_csrbank4_width3_we $and$ls180.v:5891$1282_Y - connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:5893$1285_Y - connect \builder_csrbank4_width2_we $and$ls180.v:5894$1289_Y - connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:5896$1292_Y - connect \builder_csrbank4_width1_we $and$ls180.v:5897$1296_Y - connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:5899$1299_Y - connect \builder_csrbank4_width0_we $and$ls180.v:5900$1303_Y - connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:5902$1306_Y - connect \builder_csrbank4_period3_we $and$ls180.v:5903$1310_Y - connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:5905$1313_Y - connect \builder_csrbank4_period2_we $and$ls180.v:5906$1317_Y - connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:5908$1320_Y - connect \builder_csrbank4_period1_we $and$ls180.v:5909$1324_Y - connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:5911$1327_Y - connect \builder_csrbank4_period0_we $and$ls180.v:5912$1331_Y - connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage - connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] - connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] - connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] - connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] - connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] - connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] - connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] - connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:5922$1332_Y - connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:5924$1335_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:5925$1339_Y - connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:5927$1342_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:5928$1346_Y - connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:5930$1349_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:5931$1353_Y - connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:5933$1356_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:5934$1360_Y - connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:5936$1363_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:5937$1367_Y - connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:5939$1370_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:5940$1374_Y - connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:5942$1377_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:5943$1381_Y - connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:5945$1384_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:5946$1388_Y - connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:5948$1391_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:5949$1395_Y - connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:5951$1398_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:5952$1402_Y - connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:5954$1405_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:5955$1409_Y - connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:5957$1412_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:5958$1416_Y - connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5960$1419_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5961$1423_Y - connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:5963$1426_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:5964$1430_Y - connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5966$1433_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5967$1437_Y - connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] - connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] - connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] - connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] - connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] - connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] - connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] - connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] - connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] - connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] - connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] - connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] - connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status - connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we - connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:5984$1438_Y - connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5986$1441_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5987$1445_Y - connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5989$1448_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5990$1452_Y - connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5992$1455_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5993$1459_Y - connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5995$1462_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5996$1466_Y - connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:5998$1469_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:5999$1473_Y - connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6001$1476_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6002$1480_Y - connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6004$1483_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6005$1487_Y - connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6007$1490_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6008$1494_Y - connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6010$1497_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6011$1501_Y - connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6013$1504_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6014$1508_Y - connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6016$1511_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6017$1515_Y - connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6019$1518_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6020$1522_Y - connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6022$1525_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6023$1529_Y - connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6025$1532_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6026$1536_Y - connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6028$1539_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6029$1543_Y - connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6031$1546_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6032$1550_Y - connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6034$1553_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6035$1557_Y - connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6037$1560_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6038$1564_Y - connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6040$1567_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6041$1571_Y - connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6043$1574_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6044$1578_Y - connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6046$1581_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6047$1585_Y - connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6049$1588_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6050$1592_Y - connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6052$1595_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6053$1599_Y - connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6055$1602_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6056$1606_Y - connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6058$1609_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6059$1613_Y - connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6061$1616_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6062$1620_Y - connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6064$1623_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6065$1627_Y - connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6067$1630_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6068$1634_Y - connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6070$1637_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6071$1641_Y - connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6073$1644_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6074$1648_Y - connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6076$1651_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6077$1655_Y - connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6079$1658_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6080$1662_Y - connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6082$1665_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6083$1669_Y - connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] - connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] - connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] - connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] - connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] - connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] - connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] - connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] - connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] - connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] - connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] - connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] - connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] - connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] - connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] - connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] - connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] - connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] - connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] - connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] - connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] - connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] - connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] - connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] - connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we - connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status - connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we - connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status - connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we - connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] - connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] - connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] - connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] - connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] - connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6119$1670_Y - connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6121$1673_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6122$1677_Y - connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6124$1680_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6125$1684_Y - connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6127$1687_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6128$1691_Y - connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6130$1694_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6131$1698_Y - connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6133$1701_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6134$1705_Y - connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6136$1708_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6137$1712_Y - connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6139$1715_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6140$1719_Y - connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6142$1722_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6143$1726_Y - connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6145$1729_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6146$1733_Y - connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6148$1736_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6149$1740_Y - connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6151$1743_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6152$1747_Y - connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6154$1750_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6155$1754_Y - connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6157$1757_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6158$1761_Y - connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6160$1764_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6161$1768_Y - connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6163$1771_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6164$1775_Y - connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6166$1778_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6167$1782_Y - connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6169$1785_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6170$1789_Y - connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6172$1792_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6173$1796_Y - connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6175$1799_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6176$1803_Y - connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] - connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] - connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] - connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] - connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] - connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] - connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] - connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] - connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] - connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] - connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] - connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] - connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage - connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status - connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we - connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage - connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] - connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] - connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] - connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] - connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6198$1804_Y - connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6200$1807_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6201$1811_Y - connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6203$1814_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6204$1818_Y - connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6206$1821_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6207$1825_Y - connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6209$1828_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6210$1832_Y - connect \builder_csrbank8_card_detect_w \main_sdphy_status - connect \main_sdphy_we \builder_csrbank8_card_detect_we - connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] - connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6215$1833_Y - connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6217$1836_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6218$1840_Y - connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6220$1843_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6221$1847_Y - connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6223$1850_Y - connect \main_sdram_command_issue_we $and$ls180.v:6224$1854_Y - connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6226$1857_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6227$1861_Y - connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6229$1864_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6230$1868_Y - connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6232$1871_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6233$1875_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6235$1878_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6236$1882_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6238$1885_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6239$1889_Y - connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6241$1892_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6242$1896_Y - connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6244$1899_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6245$1903_Y - connect \main_sdram_sel \main_sdram_storage [0] - connect \main_sdram_cke \main_sdram_storage [1] - connect \main_sdram_odt \main_sdram_storage [2] - connect \main_sdram_reset_n \main_sdram_storage [3] - connect \builder_csrbank9_dfii_control0_w \main_sdram_storage - connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage - connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] - connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] - connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage - connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] - connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] - connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] - connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] - connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6260$1904_Y - connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6262$1907_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6263$1911_Y - connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6265$1914_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6266$1918_Y - connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6268$1921_Y - connect \builder_csrbank10_status_we $and$ls180.v:6269$1925_Y - connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6271$1928_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6272$1932_Y - connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6274$1935_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6275$1939_Y - connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6277$1942_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6278$1946_Y - connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6280$1949_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6281$1953_Y - connect \main_spimaster10_length \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] - connect \main_spimaster14_status \main_spimaster13_done - connect \builder_csrbank10_status_w \main_spimaster14_status - connect \main_spimaster15_we \builder_csrbank10_status_we - connect \builder_csrbank10_mosi0_w \main_spimaster16_storage - connect \builder_csrbank10_miso_w \main_spimaster18_status - connect \main_spimaster19_we \builder_csrbank10_miso_we - connect \main_spimaster20_sel \main_spimaster21_storage - connect \builder_csrbank10_cs0_w \main_spimaster21_storage - connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6300$1955_Y - connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6302$1958_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6303$1962_Y - connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6305$1965_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6306$1969_Y - connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6308$1972_Y - connect \builder_csrbank11_status_we $and$ls180.v:6309$1976_Y - connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6311$1979_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6312$1983_Y - connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6314$1986_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6315$1990_Y - connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6317$1993_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6318$1997_Y - connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6320$2000_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6321$2004_Y - connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6323$2007_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6324$2011_Y - connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6326$2014_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6327$2018_Y - connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] - connect \main_spisdcard_status_status \main_spisdcard_done1 - connect \builder_csrbank11_status_w \main_spisdcard_status_status - connect \main_spisdcard_status_we \builder_csrbank11_status_we - connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage - connect \builder_csrbank11_miso_w \main_spisdcard_miso_status - connect \main_spisdcard_miso_we \builder_csrbank11_miso_we - connect \main_spisdcard_sel \main_spisdcard_cs_storage - connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage - connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage - connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] - connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6348$2020_Y - connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6350$2023_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6351$2027_Y - connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6353$2030_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6354$2034_Y - connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6356$2037_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6357$2041_Y - connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6359$2044_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6360$2048_Y - connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6362$2051_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6363$2055_Y - connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6365$2058_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6366$2062_Y - connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6368$2065_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6369$2069_Y - connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6371$2072_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6372$2076_Y - connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6374$2079_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6375$2083_Y - connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6377$2086_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6378$2090_Y - connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6380$2093_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6381$2097_Y - connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6383$2100_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6384$2104_Y - connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6386$2107_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6387$2111_Y - connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6389$2114_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6390$2118_Y - connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6392$2121_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6393$2125_Y - connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6395$2128_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6396$2132_Y - connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6398$2135_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6399$2139_Y - connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] - connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] - connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] - connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] - connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] - connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] - connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] - connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] - connect \builder_csrbank12_en0_w \main_libresocsim_en_storage - connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage - connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] - connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] - connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] - connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] - connect \main_libresocsim_value_we \builder_csrbank12_value0_we - connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6416$2140_Y - connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6418$2143_Y - connect \main_uart_rxtx_we $and$ls180.v:6419$2147_Y - connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6421$2150_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6422$2154_Y - connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6424$2157_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6425$2161_Y - connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6427$2164_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6428$2168_Y - connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6430$2171_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6431$2175_Y - connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6433$2178_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6434$2182_Y - connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6436$2185_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6437$2189_Y - connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6439$2192_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6440$2196_Y - connect \builder_csrbank13_txfull_w \main_uart_txfull_status - connect \main_uart_txfull_we \builder_csrbank13_txfull_we - connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status - connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we - connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage - connect \builder_csrbank13_txempty_w \main_uart_txempty_status - connect \main_uart_txempty_we \builder_csrbank13_txempty_we - connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status - connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6450$2197_Y - connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6452$2200_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6453$2204_Y - connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6455$2207_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6456$2211_Y - connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6458$2214_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6459$2218_Y - connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6461$2221_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6462$2225_Y - connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] - connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] - connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] - connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] - connect \builder_csr_interconnect_adr \builder_libresocsim_adr - connect \builder_csr_interconnect_we \builder_libresocsim_we - connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w - connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r - connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6516$2239_Y - connect \sdrio_clk \sys_clk_1 - connect \sdrio_clk_1 \sys_clk_1 - connect \sdrio_clk_2 \sys_clk_1 - connect \sdrio_clk_3 \sys_clk_1 - connect \sdrio_clk_4 \sys_clk_1 - connect \sdrio_clk_5 \sys_clk_1 - connect \sdrio_clk_6 \sys_clk_1 - connect \sdrio_clk_7 \sys_clk_1 - connect \sdrio_clk_8 \sys_clk_1 - connect \sdrio_clk_9 \sys_clk_1 - connect \sdrio_clk_10 \sys_clk_1 - connect \sdrio_clk_11 \sys_clk_1 - connect \sdrio_clk_12 \sys_clk_1 - connect \sdrio_clk_13 \sys_clk_1 - connect \sdrio_clk_14 \sys_clk_1 - connect \sdrio_clk_15 \sys_clk_1 - connect \sdrio_clk_16 \sys_clk_1 - connect \sdrio_clk_17 \sys_clk_1 - connect \sdrio_clk_18 \sys_clk_1 - connect \sdrio_clk_19 \sys_clk_1 - connect \sdrio_clk_20 \sys_clk_1 - connect \sdrio_clk_21 \sys_clk_1 - connect \sdrio_clk_22 \sys_clk_1 - connect \sdrio_clk_23 \sys_clk_1 - connect \sdrio_clk_24 \sys_clk_1 - connect \sdrio_clk_25 \sys_clk_1 - connect \sdrio_clk_26 \sys_clk_1 - connect \sdrio_clk_27 \sys_clk_1 - connect \sdrio_clk_28 \sys_clk_1 - connect \sdrio_clk_29 \sys_clk_1 - connect \sdrio_clk_30 \sys_clk_1 - connect \sdrio_clk_31 \sys_clk_1 - connect \sdrio_clk_32 \sys_clk_1 - connect \sdrio_clk_33 \sys_clk_1 - connect \sdrio_clk_34 \sys_clk_1 - connect \sdrio_clk_35 \sys_clk_1 - connect \sdrio_clk_36 \sys_clk_1 - connect \sdrio_clk_37 \sys_clk_1 - connect \sdrio_clk_38 \sys_clk_1 - connect \sdrio_clk_39 \sys_clk_1 - connect \sdrio_clk_40 \sys_clk_1 - connect \sdrio_clk_41 \sys_clk_1 - connect \sdrio_clk_42 \sys_clk_1 - connect \sdrio_clk_43 \sys_clk_1 - connect \sdrio_clk_44 \sys_clk_1 - connect \sdrio_clk_45 \sys_clk_1 - connect \sdrio_clk_46 \sys_clk_1 - connect \sdrio_clk_47 \sys_clk_1 - connect \sdrio_clk_48 \sys_clk_1 - connect \sdrio_clk_49 \sys_clk_1 - connect \sdrio_clk_50 \sys_clk_1 - connect \sdrio_clk_51 \sys_clk_1 - connect \sdrio_clk_52 \sys_clk_1 - connect \sdrio_clk_53 \sys_clk_1 - connect \sdrio_clk_54 \sys_clk_1 - connect \sdrio_clk_55 \sys_clk_1 - connect \main_uart_phy_rx \builder_multiregimpl0_regs1 - connect \main_pwm0_enable \main_pwm0_enable_storage - connect \main_pwm0_width \main_pwm0_width_storage - connect \main_pwm0_period \main_pwm0_period_storage - connect \main_pwm1_enable \main_pwm1_enable_storage - connect \main_pwm1_width \main_pwm1_width_storage - connect \main_pwm1_period \main_pwm1_period_storage - connect \sdrio_clk_56 \sys_clk_1 - connect \sdrio_clk_57 \sys_clk_1 - connect \sdrio_clk_58 \sys_clk_1 - connect \sdrio_clk_59 \sys_clk_1 - connect \sdrio_clk_60 \sys_clk_1 - connect \sdrio_clk_61 \sys_clk_1 - connect \sdrio_clk_62 \sys_clk_1 - connect \sdrio_clk_63 \sys_clk_1 - connect \sdrio_clk_64 \sys_clk_1 - connect \sdrio_clk_65 \sys_clk_1 - connect \sdrio_clk_66 \sys_clk_1 - connect \sdrio_clk_67 \sys_clk_1 - connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10068$2705_DATA - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10086$2712_DATA - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10100$2719_DATA - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10114$2726_DATA - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10128$2733_DATA - connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 - connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 - connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 - connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 - connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10176$2754_DATA - connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10190$2761_DATA -end -attribute \src "libresoc.v:135346.1-135404.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" -attribute \generator "nMigen" -module \lsd_l - attribute \src "libresoc.v:135347.7-135347.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:135392.3-135400.6" - wire $0\q_int$next[0:0]$6819 - attribute \src "libresoc.v:135390.3-135391.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:135392.3-135400.6" - wire $1\q_int$next[0:0]$6820 - attribute \src "libresoc.v:135369.7-135369.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:135382.17-135382.96" - wire $and$libresoc.v:135382$6809_Y - attribute \src "libresoc.v:135387.17-135387.96" - wire $and$libresoc.v:135387$6814_Y - attribute \src "libresoc.v:135384.18-135384.93" - wire $not$libresoc.v:135384$6811_Y - attribute \src "libresoc.v:135386.17-135386.92" - wire $not$libresoc.v:135386$6813_Y - attribute \src "libresoc.v:135389.17-135389.92" - wire $not$libresoc.v:135389$6816_Y - attribute \src "libresoc.v:135383.18-135383.98" - wire $or$libresoc.v:135383$6810_Y - attribute \src "libresoc.v:135385.18-135385.99" - wire $or$libresoc.v:135385$6812_Y - attribute \src "libresoc.v:135388.17-135388.97" - wire $or$libresoc.v:135388$6815_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:135347.7-135347.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:135382$6809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:135382$6809_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:135387$6814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:135387$6814_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:135384$6811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \Y $not$libresoc.v:135384$6811_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:135386$6813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $not$libresoc.v:135386$6813_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:135389$6816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $not$libresoc.v:135389$6816_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:135383$6810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_lsd - connect \Y $or$libresoc.v:135383$6810_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:135385$6812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \B \q_int - connect \Y $or$libresoc.v:135385$6812_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:135388$6815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_lsd - connect \Y $or$libresoc.v:135388$6815_Y - end - attribute \src "libresoc.v:135347.7-135347.20" - process $proc$libresoc.v:135347$6821 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:135369.7-135369.19" - process $proc$libresoc.v:135369$6822 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:135390.3-135391.27" - process $proc$libresoc.v:135390$6817 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:135392.3-135400.6" - process $proc$libresoc.v:135392$6818 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$6819 $1\q_int$next[0:0]$6820 - attribute \src "libresoc.v:135393.5-135393.29" - switch \initial - attribute \src "libresoc.v:135393.9-135393.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$6820 1'0 - case - assign $1\q_int$next[0:0]$6820 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$6819 - end - connect \$9 $and$libresoc.v:135382$6809_Y - connect \$11 $or$libresoc.v:135383$6810_Y - connect \$13 $not$libresoc.v:135384$6811_Y - connect \$15 $or$libresoc.v:135385$6812_Y - connect \$1 $not$libresoc.v:135386$6813_Y - connect \$3 $and$libresoc.v:135387$6814_Y - connect \$5 $or$libresoc.v:135388$6815_Y - connect \$7 $not$libresoc.v:135389$6816_Y - connect \qlq_lsd \$15 - connect \qn_lsd \$13 - connect \q_lsd \$11 -end -attribute \src "libresoc.v:135408.1-135942.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" -attribute \generator "nMigen" -module \lsmem - attribute \src "libresoc.v:135796.3-135821.6" - wire width 45 $0\dbus__adr$next[44:0]$6908 - attribute \src "libresoc.v:135646.3-135647.35" - wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:135656.3-135683.6" - wire $0\dbus__cyc$next[0:0]$6882 - attribute \src "libresoc.v:135654.3-135655.35" - wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:135848.3-135873.6" - wire width 64 $0\dbus__dat_w$next[63:0]$6918 - attribute \src "libresoc.v:135642.3-135643.39" - wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:135740.3-135770.6" - wire width 8 $0\dbus__sel$next[7:0]$6896 - attribute \src "libresoc.v:135650.3-135651.35" - wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:135684.3-135711.6" - wire $0\dbus__stb$next[0:0]$6888 - attribute \src "libresoc.v:135652.3-135653.35" - wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:135822.3-135847.6" - wire $0\dbus__we$next[0:0]$6913 - attribute \src "libresoc.v:135644.3-135645.33" - wire $0\dbus__we[0:0] - attribute \src "libresoc.v:135409.7-135409.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:135920.3-135939.6" - wire width 45 $0\m_badaddr_o$next[44:0]$6933 - attribute \src "libresoc.v:135636.3-135637.39" - wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:135722.3-135739.6" - wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:135771.3-135795.6" - wire width 64 $0\m_ld_data_o$next[63:0]$6902 - attribute \src "libresoc.v:135648.3-135649.39" - wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:135874.3-135896.6" - wire $0\m_load_err_o$next[0:0]$6923 - attribute \src "libresoc.v:135640.3-135641.41" - wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:135897.3-135919.6" - wire $0\m_store_err_o$next[0:0]$6928 - attribute \src "libresoc.v:135638.3-135639.43" - wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:135712.3-135721.6" - wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:135796.3-135821.6" - wire width 45 $1\dbus__adr$next[44:0]$6909 - attribute \src "libresoc.v:135514.14-135514.42" - wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:135656.3-135683.6" - wire $1\dbus__cyc$next[0:0]$6883 - attribute \src "libresoc.v:135519.7-135519.23" - wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:135848.3-135873.6" - wire width 64 $1\dbus__dat_w$next[63:0]$6919 - attribute \src "libresoc.v:135526.14-135526.48" - wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:135740.3-135770.6" - wire width 8 $1\dbus__sel$next[7:0]$6897 - attribute \src "libresoc.v:135533.13-135533.30" - wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:135684.3-135711.6" - wire $1\dbus__stb$next[0:0]$6889 - attribute \src "libresoc.v:135538.7-135538.23" - wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:135822.3-135847.6" - wire $1\dbus__we$next[0:0]$6914 - attribute \src "libresoc.v:135543.7-135543.22" - wire $1\dbus__we[0:0] - attribute \src "libresoc.v:135920.3-135939.6" - wire width 45 $1\m_badaddr_o$next[44:0]$6934 - attribute \src "libresoc.v:135547.14-135547.44" - wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:135722.3-135739.6" - wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:135771.3-135795.6" - wire width 64 $1\m_ld_data_o$next[63:0]$6903 - attribute \src "libresoc.v:135554.14-135554.48" - wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:135874.3-135896.6" - wire $1\m_load_err_o$next[0:0]$6924 - attribute \src "libresoc.v:135558.7-135558.26" - wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:135897.3-135919.6" - wire $1\m_store_err_o$next[0:0]$6929 - attribute \src "libresoc.v:135564.7-135564.27" - wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:135712.3-135721.6" - wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:135796.3-135821.6" - wire width 45 $2\dbus__adr$next[44:0]$6910 - attribute \src "libresoc.v:135656.3-135683.6" - wire $2\dbus__cyc$next[0:0]$6884 - attribute \src "libresoc.v:135848.3-135873.6" - wire width 64 $2\dbus__dat_w$next[63:0]$6920 - attribute \src "libresoc.v:135740.3-135770.6" - wire width 8 $2\dbus__sel$next[7:0]$6898 - attribute \src "libresoc.v:135684.3-135711.6" - wire $2\dbus__stb$next[0:0]$6890 - attribute \src "libresoc.v:135822.3-135847.6" - wire $2\dbus__we$next[0:0]$6915 - attribute \src "libresoc.v:135920.3-135939.6" - wire width 45 $2\m_badaddr_o$next[44:0]$6935 - attribute \src "libresoc.v:135722.3-135739.6" - wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:135771.3-135795.6" - wire width 64 $2\m_ld_data_o$next[63:0]$6904 - attribute \src "libresoc.v:135874.3-135896.6" - wire $2\m_load_err_o$next[0:0]$6925 - attribute \src "libresoc.v:135897.3-135919.6" - wire $2\m_store_err_o$next[0:0]$6930 - attribute \src "libresoc.v:135796.3-135821.6" - wire width 45 $3\dbus__adr$next[44:0]$6911 - attribute \src "libresoc.v:135656.3-135683.6" - wire $3\dbus__cyc$next[0:0]$6885 - attribute \src "libresoc.v:135848.3-135873.6" - wire width 64 $3\dbus__dat_w$next[63:0]$6921 - attribute \src "libresoc.v:135740.3-135770.6" - wire width 8 $3\dbus__sel$next[7:0]$6899 - attribute \src "libresoc.v:135684.3-135711.6" - wire $3\dbus__stb$next[0:0]$6891 - attribute \src "libresoc.v:135822.3-135847.6" - wire $3\dbus__we$next[0:0]$6916 - attribute \src "libresoc.v:135920.3-135939.6" - wire width 45 $3\m_badaddr_o$next[44:0]$6936 - attribute \src "libresoc.v:135771.3-135795.6" - wire width 64 $3\m_ld_data_o$next[63:0]$6905 - attribute \src "libresoc.v:135874.3-135896.6" - wire $3\m_load_err_o$next[0:0]$6926 - attribute \src "libresoc.v:135897.3-135919.6" - wire $3\m_store_err_o$next[0:0]$6931 - attribute \src "libresoc.v:135656.3-135683.6" - wire $4\dbus__cyc$next[0:0]$6886 - attribute \src "libresoc.v:135740.3-135770.6" - wire width 8 $4\dbus__sel$next[7:0]$6900 - attribute \src "libresoc.v:135684.3-135711.6" - wire $4\dbus__stb$next[0:0]$6892 - attribute \src "libresoc.v:135771.3-135795.6" - wire width 64 $4\m_ld_data_o$next[63:0]$6906 - attribute \src "libresoc.v:135592.18-135592.116" - wire $and$libresoc.v:135592$6827_Y - attribute \src "libresoc.v:135595.18-135595.111" - wire $and$libresoc.v:135595$6830_Y - attribute \src "libresoc.v:135600.18-135600.116" - wire $and$libresoc.v:135600$6835_Y - attribute \src "libresoc.v:135602.18-135602.111" - wire $and$libresoc.v:135602$6837_Y - attribute \src "libresoc.v:135604.17-135604.114" - wire $and$libresoc.v:135604$6839_Y - attribute \src "libresoc.v:135608.18-135608.116" - wire $and$libresoc.v:135608$6843_Y - attribute \src "libresoc.v:135610.18-135610.111" - wire $and$libresoc.v:135610$6845_Y - attribute \src "libresoc.v:135616.18-135616.116" - wire $and$libresoc.v:135616$6851_Y - attribute \src "libresoc.v:135618.18-135618.111" - wire $and$libresoc.v:135618$6853_Y - attribute \src "libresoc.v:135620.18-135620.116" - wire $and$libresoc.v:135620$6855_Y - attribute \src "libresoc.v:135622.18-135622.111" - wire $and$libresoc.v:135622$6857_Y - attribute \src "libresoc.v:135624.18-135624.116" - wire $and$libresoc.v:135624$6859_Y - attribute \src "libresoc.v:135626.17-135626.108" - wire $and$libresoc.v:135626$6861_Y - attribute \src "libresoc.v:135627.18-135627.111" - wire $and$libresoc.v:135627$6862_Y - attribute \src "libresoc.v:135628.18-135628.120" - wire $and$libresoc.v:135628$6863_Y - attribute \src "libresoc.v:135631.18-135631.120" - wire $and$libresoc.v:135631$6866_Y - attribute \src "libresoc.v:135633.18-135633.120" - wire $and$libresoc.v:135633$6868_Y - attribute \src "libresoc.v:135589.18-135589.110" - wire $not$libresoc.v:135589$6824_Y - attribute \src "libresoc.v:135594.18-135594.110" - wire $not$libresoc.v:135594$6829_Y - attribute \src "libresoc.v:135597.18-135597.110" - wire $not$libresoc.v:135597$6832_Y - attribute \src "libresoc.v:135601.18-135601.110" - wire $not$libresoc.v:135601$6836_Y - attribute \src "libresoc.v:135605.18-135605.110" - wire $not$libresoc.v:135605$6840_Y - attribute \src "libresoc.v:135609.18-135609.110" - wire $not$libresoc.v:135609$6844_Y - attribute \src "libresoc.v:135612.18-135612.110" - wire $not$libresoc.v:135612$6847_Y - attribute \src "libresoc.v:135615.17-135615.109" - wire $not$libresoc.v:135615$6850_Y - attribute \src "libresoc.v:135617.18-135617.110" - wire $not$libresoc.v:135617$6852_Y - attribute \src "libresoc.v:135621.18-135621.110" - wire $not$libresoc.v:135621$6856_Y - attribute \src "libresoc.v:135625.18-135625.110" - wire $not$libresoc.v:135625$6860_Y - attribute \src "libresoc.v:135629.18-135629.110" - wire $not$libresoc.v:135629$6864_Y - attribute \src "libresoc.v:135630.18-135630.109" - wire $not$libresoc.v:135630$6865_Y - attribute \src "libresoc.v:135632.18-135632.110" - wire $not$libresoc.v:135632$6867_Y - attribute \src "libresoc.v:135634.18-135634.110" - wire $not$libresoc.v:135634$6869_Y - attribute \src "libresoc.v:135588.17-135588.119" - wire $or$libresoc.v:135588$6823_Y - attribute \src "libresoc.v:135590.18-135590.110" - wire $or$libresoc.v:135590$6825_Y - attribute \src "libresoc.v:135591.18-135591.114" - wire $or$libresoc.v:135591$6826_Y - attribute \src "libresoc.v:135593.17-135593.113" - wire $or$libresoc.v:135593$6828_Y - attribute \src "libresoc.v:135596.18-135596.120" - wire $or$libresoc.v:135596$6831_Y - attribute \src "libresoc.v:135598.18-135598.111" - wire $or$libresoc.v:135598$6833_Y - attribute \src "libresoc.v:135599.18-135599.114" - wire $or$libresoc.v:135599$6834_Y - attribute \src "libresoc.v:135603.18-135603.120" - wire $or$libresoc.v:135603$6838_Y - attribute \src "libresoc.v:135606.18-135606.111" - wire $or$libresoc.v:135606$6841_Y - attribute \src "libresoc.v:135607.18-135607.114" - wire $or$libresoc.v:135607$6842_Y - attribute \src "libresoc.v:135611.18-135611.120" - wire $or$libresoc.v:135611$6846_Y - attribute \src "libresoc.v:135613.18-135613.111" - wire $or$libresoc.v:135613$6848_Y - attribute \src "libresoc.v:135614.18-135614.114" - wire $or$libresoc.v:135614$6849_Y - attribute \src "libresoc.v:135619.18-135619.114" - wire $or$libresoc.v:135619$6854_Y - attribute \src "libresoc.v:135623.18-135623.114" - wire $or$libresoc.v:135623$6858_Y - attribute \src "libresoc.v:135635.18-135635.127" - wire $or$libresoc.v:135635$6870_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - wire \$83 - attribute \src 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parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:135607$6842_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135611$6846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $or$libresoc.v:135611$6846_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:135613$6848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \$53 - connect \Y $or$libresoc.v:135613$6848_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135614$6849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:135614$6849_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135619$6854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:135619$6854_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:135623$6858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $or$libresoc.v:135623$6858_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:135635$6870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_load_err_o - connect \B \m_store_err_o - connect \Y $or$libresoc.v:135635$6870_Y - end - attribute \src "libresoc.v:135409.7-135409.20" - process $proc$libresoc.v:135409$6937 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:135514.14-135514.42" - process $proc$libresoc.v:135514$6938 - assign { } { } - assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \dbus__adr $1\dbus__adr[44:0] - end - attribute \src "libresoc.v:135519.7-135519.23" - process $proc$libresoc.v:135519$6939 - assign { } { } - assign $1\dbus__cyc[0:0] 1'0 - sync always - sync init - update \dbus__cyc $1\dbus__cyc[0:0] - end - attribute \src "libresoc.v:135526.14-135526.48" - process $proc$libresoc.v:135526$6940 - assign { } { } - assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dbus__dat_w $1\dbus__dat_w[63:0] - end - attribute \src "libresoc.v:135533.13-135533.30" - process $proc$libresoc.v:135533$6941 - assign { } { } - assign $1\dbus__sel[7:0] 8'00000000 - sync always - sync init - update \dbus__sel $1\dbus__sel[7:0] - end - attribute \src "libresoc.v:135538.7-135538.23" - process $proc$libresoc.v:135538$6942 - assign { } { } - assign $1\dbus__stb[0:0] 1'0 - sync always - sync init - update \dbus__stb $1\dbus__stb[0:0] - end - attribute \src "libresoc.v:135543.7-135543.22" - process $proc$libresoc.v:135543$6943 - assign { } { } - assign $1\dbus__we[0:0] 1'0 - sync always - sync init - update \dbus__we $1\dbus__we[0:0] - end - attribute \src "libresoc.v:135547.14-135547.44" - process $proc$libresoc.v:135547$6944 - assign { } { } - assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 - sync always - sync init - update \m_badaddr_o $1\m_badaddr_o[44:0] - end - attribute \src "libresoc.v:135554.14-135554.48" - process $proc$libresoc.v:135554$6945 - assign { } { } - assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \m_ld_data_o $1\m_ld_data_o[63:0] - end - attribute \src "libresoc.v:135558.7-135558.26" - process $proc$libresoc.v:135558$6946 - assign { } { } - assign $1\m_load_err_o[0:0] 1'0 - sync always - sync init - update \m_load_err_o $1\m_load_err_o[0:0] - end - attribute \src "libresoc.v:135564.7-135564.27" - process $proc$libresoc.v:135564$6947 - assign { } { } - assign $1\m_store_err_o[0:0] 1'0 - sync always - sync init - update \m_store_err_o $1\m_store_err_o[0:0] - end - attribute \src "libresoc.v:135636.3-135637.39" - process $proc$libresoc.v:135636$6871 - assign { } { } - assign $0\m_badaddr_o[44:0] \m_badaddr_o$next - sync posedge \coresync_clk - update \m_badaddr_o $0\m_badaddr_o[44:0] - end - attribute \src "libresoc.v:135638.3-135639.43" - process $proc$libresoc.v:135638$6872 - assign { } { } - assign $0\m_store_err_o[0:0] \m_store_err_o$next - sync posedge \coresync_clk - update \m_store_err_o $0\m_store_err_o[0:0] - end - attribute \src "libresoc.v:135640.3-135641.41" - process $proc$libresoc.v:135640$6873 - assign { } { } - assign $0\m_load_err_o[0:0] \m_load_err_o$next - sync posedge \coresync_clk - update \m_load_err_o $0\m_load_err_o[0:0] - end - attribute \src "libresoc.v:135642.3-135643.39" - process $proc$libresoc.v:135642$6874 - assign { } { } - assign $0\dbus__dat_w[63:0] \dbus__dat_w$next - sync posedge \coresync_clk - update \dbus__dat_w $0\dbus__dat_w[63:0] - end - attribute \src "libresoc.v:135644.3-135645.33" - process $proc$libresoc.v:135644$6875 - assign { } { } - assign $0\dbus__we[0:0] \dbus__we$next - sync posedge \coresync_clk - update \dbus__we $0\dbus__we[0:0] - end - attribute \src "libresoc.v:135646.3-135647.35" - process $proc$libresoc.v:135646$6876 - assign { } { } - assign $0\dbus__adr[44:0] \dbus__adr$next - sync posedge \coresync_clk - update \dbus__adr $0\dbus__adr[44:0] - end - attribute \src "libresoc.v:135648.3-135649.39" - process $proc$libresoc.v:135648$6877 - assign { } { } - assign $0\m_ld_data_o[63:0] \m_ld_data_o$next - sync posedge \coresync_clk - update \m_ld_data_o $0\m_ld_data_o[63:0] - end - attribute \src "libresoc.v:135650.3-135651.35" - process $proc$libresoc.v:135650$6878 - assign { } { } - assign $0\dbus__sel[7:0] \dbus__sel$next - sync posedge \coresync_clk - update \dbus__sel $0\dbus__sel[7:0] - end - attribute \src "libresoc.v:135652.3-135653.35" - process $proc$libresoc.v:135652$6879 - assign { } { } - assign $0\dbus__stb[0:0] \dbus__stb$next - sync posedge \coresync_clk - update \dbus__stb $0\dbus__stb[0:0] - end - attribute \src "libresoc.v:135654.3-135655.35" - process $proc$libresoc.v:135654$6880 - assign { } { } - assign $0\dbus__cyc[0:0] \dbus__cyc$next - sync posedge \coresync_clk - update \dbus__cyc $0\dbus__cyc[0:0] - end - attribute \src "libresoc.v:135656.3-135683.6" - process $proc$libresoc.v:135656$6881 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__cyc$next[0:0]$6882 $4\dbus__cyc$next[0:0]$6886 - attribute \src "libresoc.v:135657.5-135657.29" - switch \initial - attribute \src "libresoc.v:135657.9-135657.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__cyc$next[0:0]$6883 $2\dbus__cyc$next[0:0]$6884 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$7 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\dbus__cyc$next[0:0]$6884 $3\dbus__cyc$next[0:0]$6885 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__cyc$next[0:0]$6885 1'0 - case - assign $3\dbus__cyc$next[0:0]$6885 \dbus__cyc - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__cyc$next[0:0]$6884 1'1 - case - assign $2\dbus__cyc$next[0:0]$6884 \dbus__cyc - end - case - assign $1\dbus__cyc$next[0:0]$6883 \dbus__cyc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\dbus__cyc$next[0:0]$6886 1'0 - case - assign $4\dbus__cyc$next[0:0]$6886 $1\dbus__cyc$next[0:0]$6883 - end - sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6882 - end - attribute \src "libresoc.v:135684.3-135711.6" - process $proc$libresoc.v:135684$6887 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__stb$next[0:0]$6888 $4\dbus__stb$next[0:0]$6892 - attribute \src "libresoc.v:135685.5-135685.29" - switch \initial - attribute \src "libresoc.v:135685.9-135685.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__stb$next[0:0]$6889 $2\dbus__stb$next[0:0]$6890 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$21 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\dbus__stb$next[0:0]$6890 $3\dbus__stb$next[0:0]$6891 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$27 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__stb$next[0:0]$6891 1'0 - case - assign $3\dbus__stb$next[0:0]$6891 \dbus__stb - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__stb$next[0:0]$6890 1'1 - case - assign $2\dbus__stb$next[0:0]$6890 \dbus__stb - end - case - assign $1\dbus__stb$next[0:0]$6889 \dbus__stb - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\dbus__stb$next[0:0]$6892 1'0 - case - assign $4\dbus__stb$next[0:0]$6892 $1\dbus__stb$next[0:0]$6889 - end - sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$6888 - end - attribute \src "libresoc.v:135712.3-135721.6" - process $proc$libresoc.v:135712$6893 - assign { } { } - assign { } { } - assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:135713.5-135713.29" - switch \initial - attribute \src "libresoc.v:135713.9-135713.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\x_busy_o[0:0] \dbus__cyc - case - assign $1\x_busy_o[0:0] 1'0 - end - sync always - update \x_busy_o $0\x_busy_o[0:0] - end - attribute \src "libresoc.v:135722.3-135739.6" - process $proc$libresoc.v:135722$6894 - assign { } { } - assign { } { } - assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:135723.5-135723.29" - switch \initial - attribute \src "libresoc.v:135723.9-135723.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\m_busy_o[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\m_busy_o[0:0] \dbus__cyc - end - case - assign $1\m_busy_o[0:0] 1'0 - end - sync always - update \m_busy_o $0\m_busy_o[0:0] - end - attribute \src "libresoc.v:135740.3-135770.6" - process $proc$libresoc.v:135740$6895 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__sel$next[7:0]$6896 $4\dbus__sel$next[7:0]$6900 - attribute \src "libresoc.v:135741.5-135741.29" - switch \initial - attribute \src "libresoc.v:135741.9-135741.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__sel$next[7:0]$6897 $2\dbus__sel$next[7:0]$6898 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$35 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\dbus__sel$next[7:0]$6898 $3\dbus__sel$next[7:0]$6899 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$41 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__sel$next[7:0]$6899 8'00000000 - case - assign $3\dbus__sel$next[7:0]$6899 \dbus__sel - end - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__sel$next[7:0]$6898 \x_mask_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbus__sel$next[7:0]$6898 8'00000000 - end - case - assign $1\dbus__sel$next[7:0]$6897 \dbus__sel - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\dbus__sel$next[7:0]$6900 8'00000000 - case - assign $4\dbus__sel$next[7:0]$6900 $1\dbus__sel$next[7:0]$6897 - end - sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$6896 - end - attribute \src "libresoc.v:135771.3-135795.6" - process $proc$libresoc.v:135771$6901 - assign { } { } - assign { } { } - assign { } { } - assign $0\m_ld_data_o$next[63:0]$6902 $4\m_ld_data_o$next[63:0]$6906 - attribute \src "libresoc.v:135772.5-135772.29" - switch \initial - attribute \src "libresoc.v:135772.9-135772.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_ld_data_o$next[63:0]$6903 $2\m_ld_data_o$next[63:0]$6904 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$49 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\m_ld_data_o$next[63:0]$6904 $3\m_ld_data_o$next[63:0]$6905 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\m_ld_data_o$next[63:0]$6905 \dbus__dat_r - case - assign $3\m_ld_data_o$next[63:0]$6905 \m_ld_data_o - end - case - assign $2\m_ld_data_o$next[63:0]$6904 \m_ld_data_o - end - case - assign $1\m_ld_data_o$next[63:0]$6903 \m_ld_data_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\m_ld_data_o$next[63:0]$6906 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $4\m_ld_data_o$next[63:0]$6906 $1\m_ld_data_o$next[63:0]$6903 - end - sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6902 - end - attribute \src "libresoc.v:135796.3-135821.6" - process $proc$libresoc.v:135796$6907 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__adr$next[44:0]$6908 $3\dbus__adr$next[44:0]$6911 - attribute \src "libresoc.v:135797.5-135797.29" - switch \initial - attribute \src "libresoc.v:135797.9-135797.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__adr$next[44:0]$6909 $2\dbus__adr$next[44:0]$6910 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$63 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\dbus__adr$next[44:0]$6910 \dbus__adr - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__adr$next[44:0]$6910 \x_addr_i [47:3] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbus__adr$next[44:0]$6910 45'000000000000000000000000000000000000000000000 - end - case - assign $1\dbus__adr$next[44:0]$6909 \dbus__adr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__adr$next[44:0]$6911 45'000000000000000000000000000000000000000000000 - case - assign $3\dbus__adr$next[44:0]$6911 $1\dbus__adr$next[44:0]$6909 - end - sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$6908 - end - attribute \src "libresoc.v:135822.3-135847.6" - process $proc$libresoc.v:135822$6912 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__we$next[0:0]$6913 $3\dbus__we$next[0:0]$6916 - attribute \src "libresoc.v:135823.5-135823.29" - switch \initial - attribute \src "libresoc.v:135823.9-135823.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__we$next[0:0]$6914 $2\dbus__we$next[0:0]$6915 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$71 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\dbus__we$next[0:0]$6915 \dbus__we - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__we$next[0:0]$6915 \x_st_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbus__we$next[0:0]$6915 1'0 - end - case - assign $1\dbus__we$next[0:0]$6914 \dbus__we - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__we$next[0:0]$6916 1'0 - case - assign $3\dbus__we$next[0:0]$6916 $1\dbus__we$next[0:0]$6914 - end - sync always - update \dbus__we$next $0\dbus__we$next[0:0]$6913 - end - attribute \src "libresoc.v:135848.3-135873.6" - process $proc$libresoc.v:135848$6917 - assign { } { } - assign { } { } - assign { } { } - assign $0\dbus__dat_w$next[63:0]$6918 $3\dbus__dat_w$next[63:0]$6921 - attribute \src "libresoc.v:135849.5-135849.29" - switch \initial - attribute \src "libresoc.v:135849.9-135849.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbus__dat_w$next[63:0]$6919 $2\dbus__dat_w$next[63:0]$6920 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - switch { \$79 \dbus__cyc } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign $2\dbus__dat_w$next[63:0]$6920 \dbus__dat_w - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\dbus__dat_w$next[63:0]$6920 \x_st_data_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbus__dat_w$next[63:0]$6920 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\dbus__dat_w$next[63:0]$6919 \dbus__dat_w - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\dbus__dat_w$next[63:0]$6921 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dbus__dat_w$next[63:0]$6921 $1\dbus__dat_w$next[63:0]$6919 - end - sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6918 - end - 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assign $1\m_load_err_o$next[0:0]$6924 \m_load_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\m_load_err_o$next[0:0]$6926 1'0 - case - assign $3\m_load_err_o$next[0:0]$6926 $1\m_load_err_o$next[0:0]$6924 - end - sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6923 - end - attribute \src "libresoc.v:135897.3-135919.6" - process $proc$libresoc.v:135897$6927 - assign { } { } - assign { } { } - assign { } { } - assign $0\m_store_err_o$next[0:0]$6928 $3\m_store_err_o$next[0:0]$6931 - attribute \src "libresoc.v:135898.5-135898.29" - switch \initial - attribute \src "libresoc.v:135898.9-135898.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_store_err_o$next[0:0]$6929 $2\m_store_err_o$next[0:0]$6930 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - switch { \$89 \$87 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\m_store_err_o$next[0:0]$6930 \dbus__we - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\m_store_err_o$next[0:0]$6930 1'0 - case - assign $2\m_store_err_o$next[0:0]$6930 \m_store_err_o - end - case - assign $1\m_store_err_o$next[0:0]$6929 \m_store_err_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\m_store_err_o$next[0:0]$6931 1'0 - case - assign $3\m_store_err_o$next[0:0]$6931 $1\m_store_err_o$next[0:0]$6929 - end - sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6928 - end - attribute \src "libresoc.v:135920.3-135939.6" - process $proc$libresoc.v:135920$6932 - assign { } { } - assign { } { } - assign { } { } - assign $0\m_badaddr_o$next[44:0]$6933 $3\m_badaddr_o$next[44:0]$6936 - attribute \src "libresoc.v:135921.5-135921.29" - switch \initial - attribute \src "libresoc.v:135921.9-135921.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" - switch \wb_dcache_en - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\m_badaddr_o$next[44:0]$6934 $2\m_badaddr_o$next[44:0]$6935 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - switch { \$93 \$91 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\m_badaddr_o$next[44:0]$6935 \dbus__adr - case - assign $2\m_badaddr_o$next[44:0]$6935 \m_badaddr_o - end - case - assign $1\m_badaddr_o$next[44:0]$6934 \m_badaddr_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\m_badaddr_o$next[44:0]$6936 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$6936 $1\m_badaddr_o$next[44:0]$6934 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6933 - end - connect \$9 $or$libresoc.v:135588$6823_Y - connect \$11 $not$libresoc.v:135589$6824_Y - connect \$13 $or$libresoc.v:135590$6825_Y - connect \$15 $or$libresoc.v:135591$6826_Y - connect \$17 $and$libresoc.v:135592$6827_Y - connect \$1 $or$libresoc.v:135593$6828_Y - connect \$19 $not$libresoc.v:135594$6829_Y - connect \$21 $and$libresoc.v:135595$6830_Y - connect \$23 $or$libresoc.v:135596$6831_Y - connect \$25 $not$libresoc.v:135597$6832_Y - connect \$27 $or$libresoc.v:135598$6833_Y - connect \$29 $or$libresoc.v:135599$6834_Y - connect \$31 $and$libresoc.v:135600$6835_Y - connect \$33 $not$libresoc.v:135601$6836_Y - connect \$35 $and$libresoc.v:135602$6837_Y - connect \$37 $or$libresoc.v:135603$6838_Y - connect \$3 $and$libresoc.v:135604$6839_Y - connect \$39 $not$libresoc.v:135605$6840_Y - connect \$41 $or$libresoc.v:135606$6841_Y - connect \$43 $or$libresoc.v:135607$6842_Y - connect \$45 $and$libresoc.v:135608$6843_Y - connect \$47 $not$libresoc.v:135609$6844_Y - connect \$49 $and$libresoc.v:135610$6845_Y - connect \$51 $or$libresoc.v:135611$6846_Y - connect \$53 $not$libresoc.v:135612$6847_Y - connect \$55 $or$libresoc.v:135613$6848_Y - connect \$57 $or$libresoc.v:135614$6849_Y - connect \$5 $not$libresoc.v:135615$6850_Y - connect \$59 $and$libresoc.v:135616$6851_Y - connect \$61 $not$libresoc.v:135617$6852_Y - connect \$63 $and$libresoc.v:135618$6853_Y - connect \$65 $or$libresoc.v:135619$6854_Y - connect \$67 $and$libresoc.v:135620$6855_Y - connect \$69 $not$libresoc.v:135621$6856_Y - connect \$71 $and$libresoc.v:135622$6857_Y - connect \$73 $or$libresoc.v:135623$6858_Y - connect \$75 $and$libresoc.v:135624$6859_Y - connect \$77 $not$libresoc.v:135625$6860_Y - connect \$7 $and$libresoc.v:135626$6861_Y - connect \$79 $and$libresoc.v:135627$6862_Y - connect \$81 $and$libresoc.v:135628$6863_Y - connect \$83 $not$libresoc.v:135629$6864_Y - connect \$85 $not$libresoc.v:135630$6865_Y - connect \$87 $and$libresoc.v:135631$6866_Y - connect \$89 $not$libresoc.v:135632$6867_Y - connect \$91 $and$libresoc.v:135633$6868_Y - connect \$93 $not$libresoc.v:135634$6869_Y - connect \$95 $or$libresoc.v:135635$6870_Y - connect \x_stall_i 1'0 - connect \m_stall_i 1'0 -end -attribute \src "libresoc.v:135946.1-136901.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" -attribute \generator "nMigen" -module \main - attribute \src "libresoc.v:136473.3-136495.6" - wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:136572.3-136598.6" - wire $0\a_lt[0:0] - attribute \src "libresoc.v:136853.3-136863.6" - wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:136823.3-136832.6" - wire width 66 $0\add_a[65:0] - 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attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute 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\enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" - wire width 64 \b_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" - wire width 2 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - wire \carry_32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" - wire \carry_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 8 \eqs - attribute \src "libresoc.v:135947.7-135947.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" - wire \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" - wire \msb_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - wire \msb_b - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 42 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 43 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" - wire width 2 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" - wire width 8 \src1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - wire width 5 \tval - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 46 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 50 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" - wire \zerohi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" - wire \zerolo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:136438$6984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 66 - parameter \B_SIGNED 0 - parameter \B_WIDTH 66 - parameter \Y_WIDTH 67 - connect \A \add_a - connect \B \add_b - connect \Y $add$libresoc.v:136438$6984_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:136412$6958 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$113 - connect \B \$115 - connect \Y $and$libresoc.v:136412$6958_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:136416$6962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$121 - connect \B \$123 - connect \Y $and$libresoc.v:136416$6962_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136449$6995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$69 - connect \Y $and$libresoc.v:136449$6995_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136454$7000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$79 - connect \Y $and$libresoc.v:136454$7000_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136457$7003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$85 - connect \Y $and$libresoc.v:136457$7003_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:136460$7006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B \$91 - connect \Y $and$libresoc.v:136460$7006_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:136403$6949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 1'1 - connect \Y $eq$libresoc.v:136403$6949_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:136404$6950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 2'10 - connect \Y $eq$libresoc.v:136404$6950_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:136405$6951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 3'100 - connect \Y $eq$libresoc.v:136405$6951_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136417$6963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:136417$6963_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136418$6964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:136418$6964_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136419$6965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:136419$6965_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136420$6966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:136420$6966_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136421$6967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:136421$6967_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136422$6968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:136422$6968_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136423$6969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:136423$6969_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:136424$6970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:136424$6970_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:136425$6971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:136425$6971_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:136427$6973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:136427$6973_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:136428$6974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:136428$6974_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:136429$6975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$libresoc.v:136429$6975_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:136430$6976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:136430$6976_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:136432$6978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$libresoc.v:136432$6978_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:136433$6979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:136433$6979_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:136435$6981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $eq$libresoc.v:136435$6981_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:136436$6982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - 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\is_32bit - connect \B \zerohi - connect \Y $or$libresoc.v:136459$7005_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:136402$6948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $reduce_or$libresoc.v:136402$6948_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:136406$6952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $reduce_or$libresoc.v:136406$6952_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:136443$6989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \Y $reduce_or$libresoc.v:136443$6989_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:136446$6992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \$65 - connect \Y $reduce_or$libresoc.v:136446$6992_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:136455$7001 - parameter \WIDTH 1 - connect \A \a_n [63] - connect \B \a_n [31] - connect \S \is_32bit - connect \Y $ternary$libresoc.v:136455$7001_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:136458$7004 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \is_32bit - connect \Y $ternary$libresoc.v:136458$7004_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:136462$7008 - parameter \WIDTH 1 - connect \A \carry_64 - connect \B \carry_32 - connect \S \is_32bit - connect \Y $ternary$libresoc.v:136462$7008_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:136407$6953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [32] - connect \B \b_i [32] - connect \Y $xor$libresoc.v:136407$6953_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:136408$6954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B \$109 - connect \Y $xor$libresoc.v:136408$6954_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136409$6955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [0] - connect \B \add_o [64] - connect \Y $xor$libresoc.v:136409$6955_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136410$6956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [63] - connect \B \b_i [63] - connect \Y $xor$libresoc.v:136410$6956_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136413$6959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [1] - connect \B \add_o [32] - connect \Y $xor$libresoc.v:136413$6959_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:136414$6960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [31] - connect \B \b_i [31] - connect \Y $xor$libresoc.v:136414$6960_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:136440$6986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B \ra [32] - connect \Y $xor$libresoc.v:136440$6986_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:136441$6987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \rb [32] - connect \Y $xor$libresoc.v:136441$6987_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:136442$6988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [31:0] - connect \B \rb [31:0] - connect \Y $xor$libresoc.v:136442$6988_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:136445$6991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [63:32] - connect \B \rb [63:32] - connect \Y $xor$libresoc.v:136445$6991_Y - end - attribute \src "libresoc.v:135947.7-135947.20" - process $proc$libresoc.v:135947$7038 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:136463.3-136472.6" - process $proc$libresoc.v:136463$7009 - assign { } { } - assign { } { } - assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:136464.5-136464.29" - switch \initial - attribute \src "libresoc.v:136464.9-136464.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - switch \$22 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\is_32bit[0:0] \$24 - case - assign $1\is_32bit[0:0] 1'0 - end - sync always - update \is_32bit $0\is_32bit[0:0] - end - attribute \src "libresoc.v:136473.3-136495.6" - process $proc$libresoc.v:136473$7010 - assign { } { } - assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:136474.5-136474.29" - switch \initial - attribute \src "libresoc.v:136474.9-136474.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch { \is_32bit \$26 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\a_i[63:0] \ra - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\a_i[63:0] $2\a_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - switch \alu_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a_i[63:0] \ra - end - sync always - update \a_i $0\a_i[63:0] - end - attribute \src "libresoc.v:136496.3-136506.6" - process $proc$libresoc.v:136496$7011 - assign { } { } - assign { } { } - assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:136497.5-136497.29" - switch \initial - attribute \src "libresoc.v:136497.9-136497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\zerohi[0:0] \$63 - case - assign $1\zerohi[0:0] 1'0 - end - sync always - update \zerohi $0\zerohi[0:0] - end - attribute \src "libresoc.v:136507.3-136533.6" - process $proc$libresoc.v:136507$7012 - assign { } { } - assign { } { } - assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:136508.5-136508.29" - switch \initial - attribute \src "libresoc.v:136508.9-136508.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\tval[4:0] $2\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 - assign $2\tval[4:0] [2] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\tval[4:0] $3\tval[4:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - switch \$73 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } - end - end - case - assign $1\tval[4:0] 5'00000 - end - sync always - update \tval $0\tval[4:0] - end - attribute \src "libresoc.v:136534.3-136552.6" - process $proc$libresoc.v:136534$7013 - assign { } { } - assign { } { } - assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:136535.5-136535.29" - switch \initial - attribute \src "libresoc.v:136535.9-136535.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\msb_a[0:0] $2\msb_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\msb_a[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\msb_a[0:0] \$83 - end - case - assign $1\msb_a[0:0] 1'0 - end - sync always - update \msb_a $0\msb_a[0:0] - end - attribute \src "libresoc.v:136553.3-136571.6" - process $proc$libresoc.v:136553$7014 - assign { } { } - assign { } { } - assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:136554.5-136554.29" - switch \initial - attribute \src "libresoc.v:136554.9-136554.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\msb_b[0:0] $2\msb_b[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\msb_b[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\msb_b[0:0] \$89 - end - case - assign $1\msb_b[0:0] 1'0 - end - sync always - update \msb_b $0\msb_b[0:0] - end - attribute \src "libresoc.v:136572.3-136598.6" - process $proc$libresoc.v:136572$7015 - assign { } { } - assign { } { } - assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:136573.5-136573.29" - switch \initial - attribute \src "libresoc.v:136573.9-136573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\a_lt[0:0] $2\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\a_lt[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\a_lt[0:0] $3\a_lt[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $3\a_lt[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\a_lt[0:0] \$97 - end - end - case - assign $1\a_lt[0:0] 1'0 - end - sync always - update \a_lt $0\a_lt[0:0] - end - attribute \src "libresoc.v:136599.3-136624.6" - process $proc$libresoc.v:136599$7016 - assign { } { } - assign { } { } - assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:136600.5-136600.29" - switch \initial - attribute \src "libresoc.v:136600.9-136600.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } - assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" - switch \alu_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a[3:2] \tval [4:3] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\cr_a[3:2] \tval [1:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\cr_a[3:0] { 1'0 \$99 2'00 } - case - assign $1\cr_a[3:0] 4'0000 - end - sync always - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:136625.3-136639.6" - process $proc$libresoc.v:136625$7017 - assign { } { } - assign { } { } - assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:136626.5-136626.29" - switch \initial - attribute \src "libresoc.v:136626.9-136626.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\cr_a_ok[0:0] 1'1 - case - assign $1\cr_a_ok[0:0] 1'0 - end - sync always - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:136640.3-136677.6" - process $proc$libresoc.v:136640$7018 - assign { } { } - assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:136641.5-136641.29" - switch \initial - attribute \src "libresoc.v:136641.9-136641.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\o[63:0] \add_o [64:1] - attribute \src "libresoc.v:0.0-0.0" - case 7'0011111 - assign { } { } - assign { } { } - assign { } { } - assign $1\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } - case - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } - case - assign $3\o[63:0] $2\o[63:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - switch \$105 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - case - assign $4\o[63:0] $3\o[63:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 - assign $1\o[63:0] [0] \$107 - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o $0\o[63:0] - end - attribute \src "libresoc.v:136678.3-136696.6" - process $proc$libresoc.v:136678$7019 - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:136679.5-136679.29" - switch \initial - attribute \src "libresoc.v:136679.9-136679.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0011111 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\o_ok[0:0] 1'0 - case - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:136697.3-136710.6" - process $proc$libresoc.v:136697$7020 - assign { } { } - assign { } { } - assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:136698.5-136698.29" - switch \initial - attribute \src "libresoc.v:136698.9-136698.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\ca[1:0] [0] \add_o [65] - assign $1\ca[1:0] [1] \$111 - case - assign $1\ca[1:0] 2'00 - end - sync always - update \ca $0\ca[1:0] - end - attribute \src "libresoc.v:136711.3-136733.6" - process $proc$libresoc.v:136711$7021 - assign { } { } - assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:136712.5-136712.29" - switch \initial - attribute \src "libresoc.v:136712.9-136712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch { \is_32bit \$28 } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\b_i[63:0] \rb - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\b_i[63:0] $2\b_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" - switch \alu_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\b_i[63:0] \rb - end - sync always - update \b_i $0\b_i[63:0] - end - attribute \src "libresoc.v:136734.3-136744.6" - process $proc$libresoc.v:136734$7022 - assign { } { } - assign { } { } - assign $0\xer_ca$20[1:0]$7023 $1\xer_ca$20[1:0]$7024 - attribute \src "libresoc.v:136735.5-136735.29" - switch \initial - attribute \src "libresoc.v:136735.9-136735.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ca$20[1:0]$7024 \ca - case - assign $1\xer_ca$20[1:0]$7024 2'00 - end - sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$7023 - end - attribute \src "libresoc.v:136745.3-136755.6" - process $proc$libresoc.v:136745$7025 - assign { } { } - assign { } { } - assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:136746.5-136746.29" - switch \initial - attribute \src "libresoc.v:136746.9-136746.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'1 - case - assign $1\xer_ca_ok[0:0] 1'0 - end - sync always - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:136756.3-136769.6" - process $proc$libresoc.v:136756$7026 - assign { } { } - assign { } { } - assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:136757.5-136757.29" - switch \initial - attribute \src "libresoc.v:136757.9-136757.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\ov[1:0] [0] \$119 - assign $1\ov[1:0] [1] \$127 - case - assign $1\ov[1:0] 2'00 - end - sync always - update \ov $0\ov[1:0] - end - attribute \src "libresoc.v:136770.3-136780.6" - process $proc$libresoc.v:136770$7027 - assign { } { } - assign { } { } - assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:136771.5-136771.29" - switch \initial - attribute \src "libresoc.v:136771.9-136771.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ov[1:0] \ov - case - assign $1\xer_ov[1:0] 2'00 - end - sync always - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "libresoc.v:136781.3-136791.6" - process $proc$libresoc.v:136781$7028 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:136782.5-136782.29" - switch \initial - attribute \src "libresoc.v:136782.9-136782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000010 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:136792.3-136802.6" - process $proc$libresoc.v:136792$7029 - assign { } { } - assign { } { } - assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:136793.5-136793.29" - switch \initial - attribute \src "libresoc.v:136793.9-136793.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\src1[7:0] \ra [7:0] - case - assign $1\src1[7:0] 8'00000000 - end - sync always - update \src1 $0\src1[7:0] - end - attribute \src "libresoc.v:136803.3-136822.6" - process $proc$libresoc.v:136803$7030 - assign { } { } - assign { } { } - assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:136804.5-136804.29" - switch \initial - attribute \src "libresoc.v:136804.9-136804.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001100 - assign { } { } - assign $1\eqs[7:0] [0] \$129 - assign $1\eqs[7:0] [1] \$131 - assign $1\eqs[7:0] [2] \$133 - assign $1\eqs[7:0] [3] \$135 - assign $1\eqs[7:0] [4] \$137 - assign $1\eqs[7:0] [5] \$139 - assign $1\eqs[7:0] [6] \$141 - assign $1\eqs[7:0] [7] \$143 - case - assign $1\eqs[7:0] 8'00000000 - end - sync always - update \eqs $0\eqs[7:0] - end - attribute \src "libresoc.v:136823.3-136832.6" - process $proc$libresoc.v:136823$7031 - assign { } { } - assign { } { } - assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:136824.5-136824.29" - switch \initial - attribute \src "libresoc.v:136824.9-136824.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - switch \$34 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } - case - assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \add_a $0\add_a[65:0] - end - attribute \src "libresoc.v:136833.3-136842.6" - process $proc$libresoc.v:136833$7032 - assign { } { } - assign { } { } - assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:136834.5-136834.29" - switch \initial - attribute \src "libresoc.v:136834.9-136834.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - switch \$40 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\add_b[65:0] { 1'0 \b_i 1'1 } - case - assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \add_b $0\add_b[65:0] - end - attribute \src "libresoc.v:136843.3-136852.6" - process $proc$libresoc.v:136843$7033 - assign { } { } - assign { } { } - assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:136844.5-136844.29" - switch \initial - attribute \src "libresoc.v:136844.9-136844.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - switch \$46 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\add_o[65:0] \$48 [65:0] - case - assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \add_o $0\add_o[65:0] - end - attribute \src "libresoc.v:136853.3-136863.6" - process $proc$libresoc.v:136853$7034 - assign { } { } - assign { } { } - assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:136854.5-136854.29" - switch \initial - attribute \src "libresoc.v:136854.9-136854.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" - switch \alu_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001010 - assign { } { } - assign $1\a_n[63:0] \$51 - case - assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \a_n $0\a_n[63:0] - end - attribute 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"OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \br_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute 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\enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 14 \br_op__insn_type$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \br_op__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \br_op__lk$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" - wire \br_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" - wire \cr_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" - wire width 64 \ctr_m - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" - wire width 64 \ctr_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" - wire \ctr_write - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" - wire \ctr_zero_bo1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 21 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 22 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 23 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 24 \fast2_ok - attribute \src "libresoc.v:137318.7-137318.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 27 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 12 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 25 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:137617$7044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \br_imm_addr - connect \B \br_op__cia - connect \Y $add$libresoc.v:137617$7044_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:137632$7060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \br_op__cia - connect \B 3'100 - connect \Y $add$libresoc.v:137632$7060_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:137624$7051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \$29 - connect \Y $and$libresoc.v:137624$7051_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:137625$7052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \cr_bit - connect \Y $and$libresoc.v:137625$7052_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:137631$7059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [10] - connect \B \$44 - connect \Y $and$libresoc.v:137631$7059_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:137615$7042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \br_op__insn_type - connect \B 7'0001000 - connect \Y $eq$libresoc.v:137615$7042_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:137618$7045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \B \bo [3] - connect \Y $eq$libresoc.v:137618$7045_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:137620$7047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'0 - connect \Y $eq$libresoc.v:137620$7047_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:137621$7048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'1 - connect \Y $eq$libresoc.v:137621$7048_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:137622$7049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4] - connect \B 1'1 - connect \Y $eq$libresoc.v:137622$7049_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:137627$7054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:137627$7054_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:137623$7050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \Y $not$libresoc.v:137623$7050_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:137630$7058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:137630$7058_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:137616$7043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \br_op__insn [1] - connect \B \$12 - connect \Y $or$libresoc.v:137616$7043_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:137619$7046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$19 - connect \B \bo [4] - connect \Y $or$libresoc.v:137619$7046_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:137627$7055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:137627$7054_Y - connect \Y $pos$libresoc.v:137627$7055_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:137628$7056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:137628$7056_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:137626$7053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \fast1 - connect \B 1'1 - connect \Y $sub$libresoc.v:137626$7053_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:137629$7057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [1] - connect \B \$40 - connect \Y $xor$libresoc.v:137629$7057_Y - end - attribute \src "libresoc.v:137318.7-137318.20" - process $proc$libresoc.v:137318$7078 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:137633.3-137644.6" - process $proc$libresoc.v:137633$7061 - assign { } { } - assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:137634.5-137634.29" - switch \initial - attribute \src "libresoc.v:137634.9-137634.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - switch \$14 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\br_addr[63:0] \br_imm_addr - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\br_addr[63:0] \$16 [63:0] - end - sync always - update \br_addr $0\br_addr[63:0] - end - attribute \src "libresoc.v:137645.3-137671.6" - process $proc$libresoc.v:137645$7062 - assign { } { } - assign { } { } - assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:137646.5-137646.29" - switch \initial - attribute \src "libresoc.v:137646.9-137646.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000110 - assign { } { } - assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - switch \$46 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } - end - case - assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \br_imm_addr $0\br_imm_addr[63:0] - end - attribute \src "libresoc.v:137672.3-137690.6" - process $proc$libresoc.v:137672$7063 - assign { } { } - assign { } { } - assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:137673.5-137673.29" - switch \initial - attribute \src "libresoc.v:137673.9-137673.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000110 - assign { } { } - assign $1\br_taken[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\br_taken[0:0] \bc_taken - attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\br_taken[0:0] \bc_taken - case - assign $1\br_taken[0:0] 1'0 - end - sync always - update \br_taken $0\br_taken[0:0] - end - attribute \src "libresoc.v:137691.3-137705.6" - process $proc$libresoc.v:137691$7064 - assign { } { } - assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:137692.5-137692.29" - switch \initial - attribute \src "libresoc.v:137692.9-137692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000111 - assign { } { } - assign $1\fast1_ok[0:0] \ctr_write - attribute \src "libresoc.v:0.0-0.0" - case 7'0001000 - assign { } { } - assign $1\fast1_ok[0:0] \ctr_write - case - assign $1\fast1_ok[0:0] 1'0 - end - sync always - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "libresoc.v:137706.3-137715.6" - process $proc$libresoc.v:137706$7065 - assign { } { } - assign { } { } - assign $0\fast2$11[63:0]$7066 $1\fast2$11[63:0]$7067 - attribute \src "libresoc.v:137707.5-137707.29" - switch \initial - attribute \src "libresoc.v:137707.9-137707.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch \br_op__lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast2$11[63:0]$7067 \$48 [63:0] - case - assign $1\fast2$11[63:0]$7067 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast2$11 $0\fast2$11[63:0]$7066 - end - attribute \src "libresoc.v:137716.3-137725.6" - process $proc$libresoc.v:137716$7068 - assign { } { } - assign { } { } - assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:137717.5-137717.29" - switch \initial - attribute \src "libresoc.v:137717.9-137717.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch \br_op__lk - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\fast2_ok[0:0] 1'1 - case - assign $1\fast2_ok[0:0] 1'0 - end - sync always - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "libresoc.v:137726.3-137740.6" - process $proc$libresoc.v:137726$7069 - assign { } { } - assign { } { } - assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:137727.5-137727.29" - switch \initial - attribute \src "libresoc.v:137727.9-137727.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch \bi - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [3] - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [2] - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $1\cr_bit[0:0] \cr_a [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $1\cr_bit[0:0] \cr_a [0] - case - assign $1\cr_bit[0:0] 1'0 - end - sync always - update \cr_bit $0\cr_bit[0:0] - end - attribute \src "libresoc.v:137741.3-137753.6" - process $proc$libresoc.v:137741$7070 - assign { } { } - assign { } { } - assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:137742.5-137742.29" - switch \initial - attribute \src "libresoc.v:137742.9-137742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\ctr_write[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_write[0:0] 1'1 - end - sync always - update \ctr_write $0\ctr_write[0:0] - end - attribute \src "libresoc.v:137754.3-137777.6" - process $proc$libresoc.v:137754$7071 - assign { } { } - assign { } { } - assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:137755.5-137755.29" - switch \initial - attribute \src "libresoc.v:137755.9-137755.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\bc_taken[0:0] \$21 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\bc_taken[0:0] $2\bc_taken[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - switch { \$27 \$25 \$23 } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $2\bc_taken[0:0] \$31 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign $2\bc_taken[0:0] \$33 - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign $2\bc_taken[0:0] \ctr_zero_bo1 - case - assign $2\bc_taken[0:0] 1'0 - end - end - sync always - update \bc_taken $0\bc_taken[0:0] - end - attribute \src "libresoc.v:137778.3-137790.6" - process $proc$libresoc.v:137778$7072 - assign { } { } - assign { } { } - assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:137779.5-137779.29" - switch \initial - attribute \src "libresoc.v:137779.9-137779.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_n[63:0] \$35 [63:0] - end - sync always - update \ctr_n $0\ctr_n[63:0] - end - attribute \src "libresoc.v:137791.3-137803.6" - process $proc$libresoc.v:137791$7073 - assign { } { } - assign { } { } - assign $0\fast1$10[63:0]$7074 $1\fast1$10[63:0]$7075 - attribute \src "libresoc.v:137792.5-137792.29" - switch \initial - attribute \src "libresoc.v:137792.9-137792.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\fast1$10[63:0]$7075 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\fast1$10[63:0]$7075 \ctr_n - end - sync always - update \fast1$10 $0\fast1$10[63:0]$7074 - end - attribute \src "libresoc.v:137804.3-137824.6" - process $proc$libresoc.v:137804$7076 - assign { } { } - assign { } { } - assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:137805.5-137805.29" - switch \initial - attribute \src "libresoc.v:137805.9-137805.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_m[63:0] $2\ctr_m[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - switch \br_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ctr_m[63:0] \$38 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ctr_m[63:0] \fast1 - end - end - sync always - update \ctr_m $0\ctr_m[63:0] - end - attribute \src "libresoc.v:137825.3-137837.6" - process $proc$libresoc.v:137825$7077 - assign { } { } - assign { } { } - assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:137826.5-137826.29" - switch \initial - attribute \src "libresoc.v:137826.9-137826.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch \bo [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\ctr_zero_bo1[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ctr_zero_bo1[0:0] \$42 - end - sync always - update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] - end - connect \$12 $eq$libresoc.v:137615$7042_Y - connect \$14 $or$libresoc.v:137616$7043_Y - connect \$17 $add$libresoc.v:137617$7044_Y - connect \$19 $eq$libresoc.v:137618$7045_Y - connect \$21 $or$libresoc.v:137619$7046_Y - connect \$23 $eq$libresoc.v:137620$7047_Y - connect \$25 $eq$libresoc.v:137621$7048_Y - connect \$27 $eq$libresoc.v:137622$7049_Y - connect \$29 $not$libresoc.v:137623$7050_Y - connect \$31 $and$libresoc.v:137624$7051_Y - connect \$33 $and$libresoc.v:137625$7052_Y - connect \$36 $sub$libresoc.v:137626$7053_Y - connect \$38 $pos$libresoc.v:137627$7055_Y - connect \$40 $reduce_or$libresoc.v:137628$7056_Y - connect \$42 $xor$libresoc.v:137629$7057_Y - connect \$44 $not$libresoc.v:137630$7058_Y - connect \$46 $and$libresoc.v:137631$7059_Y - connect \$49 $add$libresoc.v:137632$7060_Y - connect \$16 \$17 - connect \$35 \$36 - connect \$48 \$49 - connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \muxid$1 \muxid - connect \nia_ok \br_taken - connect \nia \br_addr - connect \bi \br_op__insn [17:16] - connect \bo \br_op__insn [25:21] -end -attribute \src "libresoc.v:137851.1-138795.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" -attribute \generator "nMigen" -module \main$38 - attribute \src "libresoc.v:138760.3-138771.6" - wire width 64 $0\a[63:0] - attribute \src "libresoc.v:138258.3-138269.6" - wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:138772.3-138783.6" - wire width 64 $0\b[63:0] - attribute \src "libresoc.v:138541.3-138552.6" - wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:138334.3-138365.6" - wire width 64 $0\fast1$11[63:0]$7124 - attribute \src "libresoc.v:138366.3-138397.6" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:138398.3-138480.6" - wire width 64 $0\fast2$12[63:0]$7129 - attribute \src "libresoc.v:138481.3-138512.6" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:137852.7-137852.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:138553.3-138721.6" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:138553.3-138721.6" - wire $0\msr_ok[0:0] - attribute \src "libresoc.v:138270.3-138301.6" - wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:138302.3-138333.6" - wire $0\nia_ok[0:0] - attribute \src "libresoc.v:138722.3-138740.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:138741.3-138759.6" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal$60[0:0]$7143 - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal$61[0:0]$7144 - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal$62[0:0]$7145 - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal$67[0:0]$7146 - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal$68[0:0]$7147 - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal$69[0:0]$7148 - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal$70[0:0]$7149 - attribute \src "libresoc.v:138513.3-138540.6" - wire $0\trapexc_$signal[0:0]$7142 - attribute \src "libresoc.v:138398.3-138480.6" - wire $10\fast2$12[19:19]$7139 - attribute \src "libresoc.v:138553.3-138721.6" - wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:138553.3-138721.6" - wire $11\msr[15:15] - attribute \src "libresoc.v:138553.3-138721.6" - wire $12\msr[12:12] - attribute \src "libresoc.v:138553.3-138721.6" - wire $13\msr[60:60] - attribute \src "libresoc.v:138553.3-138721.6" - wire $14\msr[12:12] - attribute \src "libresoc.v:138553.3-138721.6" - wire $15\msr[12:12] - attribute \src "libresoc.v:138553.3-138721.6" - wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:138553.3-138721.6" - wire $17\msr[15:15] - attribute \src "libresoc.v:138553.3-138721.6" - wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:138760.3-138771.6" - wire width 64 $1\a[63:0] - attribute \src "libresoc.v:138258.3-138269.6" - wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:138772.3-138783.6" - wire width 64 $1\b[63:0] - attribute \src "libresoc.v:138541.3-138552.6" - wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:138334.3-138365.6" - wire width 64 $1\fast1$11[63:0]$7125 - attribute \src "libresoc.v:138366.3-138397.6" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:138398.3-138480.6" - wire width 64 $1\fast2$12[63:0]$7130 - attribute \src "libresoc.v:138481.3-138512.6" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:138553.3-138721.6" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:138553.3-138721.6" - wire $1\msr_ok[0:0] - attribute \src "libresoc.v:138270.3-138301.6" - wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:138302.3-138333.6" - wire $1\nia_ok[0:0] - attribute \src "libresoc.v:138722.3-138740.6" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:138741.3-138759.6" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal$60[0:0]$7151 - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal$61[0:0]$7152 - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal$62[0:0]$7153 - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal$67[0:0]$7154 - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal$68[0:0]$7155 - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal$69[0:0]$7156 - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal$70[0:0]$7157 - attribute \src "libresoc.v:138513.3-138540.6" - wire $1\trapexc_$signal[0:0]$7150 - attribute \src "libresoc.v:138334.3-138365.6" - wire width 64 $2\fast1$11[63:0]$7126 - attribute \src "libresoc.v:138366.3-138397.6" - wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:138398.3-138480.6" - wire width 64 $2\fast2$12[63:0]$7131 - attribute \src "libresoc.v:138481.3-138512.6" - wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:138553.3-138721.6" - wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:138553.3-138721.6" - wire $2\msr_ok[0:0] - attribute \src "libresoc.v:138270.3-138301.6" - wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:138302.3-138333.6" - wire $2\nia_ok[0:0] - attribute \src "libresoc.v:138513.3-138540.6" - wire $2\trapexc_$signal$60[0:0]$7159 - attribute \src "libresoc.v:138513.3-138540.6" - wire $2\trapexc_$signal$61[0:0]$7160 - attribute \src "libresoc.v:138513.3-138540.6" - wire $2\trapexc_$signal$62[0:0]$7161 - attribute \src "libresoc.v:138513.3-138540.6" - wire $2\trapexc_$signal$67[0:0]$7162 - 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connect \Y $reduce_or$libresoc.v:138230$7090_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138237$7098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$45 - connect \Y $reduce_or$libresoc.v:138237$7098_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138239$7100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \Y $reduce_or$libresoc.v:138239$7100_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138241$7102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$53 - connect \Y $reduce_or$libresoc.v:138241$7102_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138243$7104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$57 - connect \Y $reduce_or$libresoc.v:138243$7104_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138245$7106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$64 - connect \Y $reduce_or$libresoc.v:138245$7106_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:138247$7108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \$72 - connect \Y $reduce_or$libresoc.v:138247$7108_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:138232$7092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 20 - connect \A \trap_op__trapaddr - connect \B 3'100 - connect \Y $sshl$libresoc.v:138232$7092_Y - end - attribute \src "libresoc.v:137852.7-137852.20" - process $proc$libresoc.v:137852$7180 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:138258.3-138269.6" - process $proc$libresoc.v:138258$7120 - assign { } { } - assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:138259.5-138259.29" - switch \initial - attribute \src "libresoc.v:138259.9-138259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a_s[63:0] \ra - end - sync always - update \a_s $0\a_s[63:0] - end - attribute \src "libresoc.v:138270.3-138301.6" - process $proc$libresoc.v:138270$7121 - assign { } { } - assign { } { } - assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:138271.5-138271.29" - switch \initial - attribute \src "libresoc.v:138271.9-138271.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\nia[63:0] $2\nia[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia[63:0] \$35 - case - assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\nia[63:0] { \fast1 [63:2] 2'00 } - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 - case - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \nia $0\nia[63:0] - end - attribute \src "libresoc.v:138302.3-138333.6" - process $proc$libresoc.v:138302$7122 - assign { } { } - assign { } { } - assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:138303.5-138303.29" - switch \initial - attribute \src "libresoc.v:138303.9-138303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\nia_ok[0:0] $2\nia_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\nia_ok[0:0] 1'1 - case - assign $2\nia_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\nia_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\nia_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { } { } - assign $1\nia_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\nia_ok[0:0] 1'1 - case - assign $1\nia_ok[0:0] 1'0 - end - sync always - update \nia_ok $0\nia_ok[0:0] - end - attribute \src "libresoc.v:138334.3-138365.6" - process $proc$libresoc.v:138334$7123 - assign { } { } - assign { } { } - assign $0\fast1$11[63:0]$7124 $1\fast1$11[63:0]$7125 - attribute \src "libresoc.v:138335.5-138335.29" - switch \initial - attribute \src "libresoc.v:138335.9-138335.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast1$11[63:0]$7125 $2\fast1$11[63:0]$7126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1$11[63:0]$7126 \trap_op__cia - case - assign $2\fast1$11[63:0]$7126 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast1$11[63:0]$7125 \$39 [63:0] - case - assign $1\fast1$11[63:0]$7125 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast1$11 $0\fast1$11[63:0]$7124 - end - attribute \src "libresoc.v:138366.3-138397.6" - process $proc$libresoc.v:138366$7127 - assign { } { } - assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:138367.5-138367.29" - switch \initial - attribute \src "libresoc.v:138367.9-138367.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast1_ok[0:0] 1'1 - case - assign $2\fast1_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast1_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast1_ok[0:0] 1'1 - case - assign $1\fast1_ok[0:0] 1'0 - end - sync always - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "libresoc.v:138398.3-138480.6" - process $proc$libresoc.v:138398$7128 - assign { } { } - assign { } { } - assign $0\fast2$12[63:0]$7129 $1\fast2$12[63:0]$7130 - attribute \src "libresoc.v:138399.5-138399.29" - switch \initial - attribute \src "libresoc.v:138399.9-138399.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast2$12[63:0]$7130 $2\fast2$12[63:0]$7131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { $2\fast2$12[63:0]$7131 [29] $2\fast2$12[63:0]$7131 [27] $2\fast2$12[63:0]$7131 [21] } 3'000 - assign $2\fast2$12[63:0]$7131 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7131 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7131 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7131 [17] $3\fast2$12[17:17]$7132 - assign { } { } - assign $2\fast2$12[63:0]$7131 [20] $5\fast2$12[20:20]$7134 - assign $2\fast2$12[63:0]$7131 [16] $6\fast2$12[16:16]$7135 - assign $2\fast2$12[63:0]$7131 [18] $7\fast2$12[19:18]$7136 [0] - assign $2\fast2$12[63:0]$7131 [28] $8\fast2$12[28:28]$7137 - assign $2\fast2$12[63:0]$7131 [30] $9\fast2$12[30:30]$7138 - assign $2\fast2$12[63:0]$7131 [19] $10\fast2$12[19:19]$7139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - switch \$42 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\fast2$12[17:17]$7132 1'1 - case - assign $3\fast2$12[17:17]$7132 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - switch \$44 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fast2$12[18:18]$7133 1'1 - case - assign $4\fast2$12[18:18]$7133 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - switch \$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\fast2$12[20:20]$7134 1'1 - case - assign $5\fast2$12[20:20]$7134 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - switch \$52 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\fast2$12[16:16]$7135 1'1 - case - assign $6\fast2$12[16:16]$7135 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - switch \$56 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign $9\fast2$12[30:30]$7138 \trapexc_$signal - assign $8\fast2$12[28:28]$7137 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7136 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7136 [0] \trapexc_$signal$62 - case - assign $7\fast2$12[19:18]$7136 { 1'0 $4\fast2$12[18:18]$7133 } - assign $8\fast2$12[28:28]$7137 1'0 - assign $9\fast2$12[30:30]$7138 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $10\fast2$12[19:19]$7139 1'1 - case - assign $10\fast2$12[19:19]$7139 $7\fast2$12[19:18]$7136 [1] - end - case - assign $2\fast2$12[63:0]$7131 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign { $1\fast2$12[63:0]$7130 [30:27] $1\fast2$12[63:0]$7130 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7130 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7130 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7130 [63:31] \trap_op__msr [63:31] - case - assign $1\fast2$12[63:0]$7130 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast2$12 $0\fast2$12[63:0]$7129 - end - attribute \src "libresoc.v:138481.3-138512.6" - process $proc$libresoc.v:138481$7140 - assign { } { } - assign { } { } - assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:138482.5-138482.29" - switch \initial - attribute \src "libresoc.v:138482.9-138482.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fast2_ok[0:0] 1'1 - case - assign $2\fast2_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign $1\fast2_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign $1\fast2_ok[0:0] 1'1 - case - assign $1\fast2_ok[0:0] 1'0 - end - sync always - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "libresoc.v:138513.3-138540.6" - process $proc$libresoc.v:138513$7141 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\trapexc_$signal[0:0]$7142 $1\trapexc_$signal[0:0]$7150 - assign $0\trapexc_$signal$60[0:0]$7143 $1\trapexc_$signal$60[0:0]$7151 - assign $0\trapexc_$signal$61[0:0]$7144 $1\trapexc_$signal$61[0:0]$7152 - assign $0\trapexc_$signal$62[0:0]$7145 $1\trapexc_$signal$62[0:0]$7153 - assign $0\trapexc_$signal$67[0:0]$7146 $1\trapexc_$signal$67[0:0]$7154 - assign $0\trapexc_$signal$68[0:0]$7147 $1\trapexc_$signal$68[0:0]$7155 - assign $0\trapexc_$signal$69[0:0]$7148 $1\trapexc_$signal$69[0:0]$7156 - assign $0\trapexc_$signal$70[0:0]$7149 $1\trapexc_$signal$70[0:0]$7157 - attribute \src "libresoc.v:138514.5-138514.29" - switch \initial - attribute \src "libresoc.v:138514.9-138514.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $1\trapexc_$signal[0:0]$7150 $2\trapexc_$signal[0:0]$7158 - assign $1\trapexc_$signal$60[0:0]$7151 $2\trapexc_$signal$60[0:0]$7159 - assign $1\trapexc_$signal$61[0:0]$7152 $2\trapexc_$signal$61[0:0]$7160 - assign $1\trapexc_$signal$62[0:0]$7153 $2\trapexc_$signal$62[0:0]$7161 - assign $1\trapexc_$signal$67[0:0]$7154 $2\trapexc_$signal$67[0:0]$7162 - assign $1\trapexc_$signal$68[0:0]$7155 $2\trapexc_$signal$68[0:0]$7163 - assign $1\trapexc_$signal$69[0:0]$7156 $2\trapexc_$signal$69[0:0]$7164 - assign $1\trapexc_$signal$70[0:0]$7157 $2\trapexc_$signal$70[0:0]$7165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\trapexc_$signal[0:0]$7158 $3\trapexc_$signal[0:0]$7166 - assign $2\trapexc_$signal$60[0:0]$7159 $3\trapexc_$signal$60[0:0]$7167 - assign $2\trapexc_$signal$61[0:0]$7160 $3\trapexc_$signal$61[0:0]$7168 - assign $2\trapexc_$signal$62[0:0]$7161 $3\trapexc_$signal$62[0:0]$7169 - assign $2\trapexc_$signal$67[0:0]$7162 $3\trapexc_$signal$67[0:0]$7170 - assign $2\trapexc_$signal$68[0:0]$7163 $3\trapexc_$signal$68[0:0]$7171 - assign $2\trapexc_$signal$69[0:0]$7164 $3\trapexc_$signal$69[0:0]$7172 - assign $2\trapexc_$signal$70[0:0]$7165 $3\trapexc_$signal$70[0:0]$7173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - switch \$71 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7173 $3\trapexc_$signal$62[0:0]$7169 $3\trapexc_$signal$60[0:0]$7167 $3\trapexc_$signal$61[0:0]$7168 $3\trapexc_$signal[0:0]$7166 $3\trapexc_$signal$69[0:0]$7172 $3\trapexc_$signal$68[0:0]$7171 $3\trapexc_$signal$67[0:0]$7170 } \trap_op__ldst_exc - case - assign $3\trapexc_$signal[0:0]$7166 1'0 - assign $3\trapexc_$signal$60[0:0]$7167 1'0 - assign $3\trapexc_$signal$61[0:0]$7168 1'0 - assign $3\trapexc_$signal$62[0:0]$7169 1'0 - assign $3\trapexc_$signal$67[0:0]$7170 1'0 - assign $3\trapexc_$signal$68[0:0]$7171 1'0 - assign $3\trapexc_$signal$69[0:0]$7172 1'0 - assign $3\trapexc_$signal$70[0:0]$7173 1'0 - end - case - assign $2\trapexc_$signal[0:0]$7158 1'0 - assign $2\trapexc_$signal$60[0:0]$7159 1'0 - assign $2\trapexc_$signal$61[0:0]$7160 1'0 - assign $2\trapexc_$signal$62[0:0]$7161 1'0 - assign $2\trapexc_$signal$67[0:0]$7162 1'0 - assign $2\trapexc_$signal$68[0:0]$7163 1'0 - assign $2\trapexc_$signal$69[0:0]$7164 1'0 - assign $2\trapexc_$signal$70[0:0]$7165 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7150 1'0 - assign $1\trapexc_$signal$60[0:0]$7151 1'0 - assign $1\trapexc_$signal$61[0:0]$7152 1'0 - assign $1\trapexc_$signal$62[0:0]$7153 1'0 - assign $1\trapexc_$signal$67[0:0]$7154 1'0 - assign $1\trapexc_$signal$68[0:0]$7155 1'0 - assign $1\trapexc_$signal$69[0:0]$7156 1'0 - assign $1\trapexc_$signal$70[0:0]$7157 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7142 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7143 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7144 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7145 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7146 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7147 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7148 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7149 - end - attribute \src "libresoc.v:138541.3-138552.6" - process $proc$libresoc.v:138541$7174 - assign { } { } - assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:138542.5-138542.29" - switch \initial - attribute \src "libresoc.v:138542.9-138542.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\b_s[63:0] \rb - end - sync always - update \b_s $0\b_s[63:0] - end - attribute \src "libresoc.v:138553.3-138721.6" - process $proc$libresoc.v:138553$7175 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\msr[63:0] $1\msr[63:0] - assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:138554.5-138554.29" - switch \initial - attribute \src "libresoc.v:138554.9-138554.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign { } { } - assign { } { } - assign $1\msr[63:0] $2\msr[63:0] - assign $1\msr_ok[0:0] $2\msr_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" - switch \should_trap - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } - assign $2\msr[63:0] [63] 1'1 - assign $2\msr[63:0] [15] 1'0 - assign $2\msr[63:0] [14] 1'0 - assign $2\msr[63:0] [5] 1'0 - assign $2\msr[63:0] [4] 1'0 - assign $2\msr[63:0] [1] 1'0 - assign $2\msr[63:0] [0] 1'1 - assign $2\msr[63:0] [11] 1'0 - assign $2\msr[63:0] [8] 1'0 - assign $2\msr[63:0] [23] 1'0 - assign $2\msr[63:0] [32] 1'0 - assign $2\msr[63:0] [25] 1'0 - assign $2\msr[63:0] [13] 1'0 - assign $2\msr[63:0] [3] 1'0 - assign $2\msr[63:0] [10] 1'0 - assign $2\msr[63:0] [9] 1'0 - assign $2\msr[63:0] [58] 1'0 - assign $2\msr_ok[0:0] 1'1 - case - assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\msr_ok[0:0] 1'0 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign { } { } - assign { } { } - assign $1\msr[63:0] [0] \$75 [0] - assign $1\msr[63:0] [11:1] $3\msr[11:1] - assign $1\msr[63:0] [59:13] $4\msr[59:13] - assign $1\msr[63:0] [63:61] $5\msr[63:61] - assign $1\msr[63:0] [12] $12\msr[12:12] - assign $1\msr[63:0] [60] $13\msr[60:60] - assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" - switch \trap_op__insn [21] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $3\msr[11:1] [10:1] \$75 [11:2] - assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } - assign $5\msr[63:61] \$75 [63:61] - assign $3\msr[11:1] [0] \ra [1] - assign $4\msr[59:13] [2] \ra [15] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } - assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } - assign $5\msr[63:61] $8\msr[63:61] - assign $3\msr[11:1] [4:3] $10\msr[5:4] - assign $4\msr[59:13] [2] $11\msr[15:15] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign $6\msr[11:1] \ra [11:1] - assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } - assign $8\msr[63:61] \ra [63:61] - assign $7\msr[59:13] [21:19] $9\msr[34:32] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - switch \$83 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $9\msr[34:32] \trap_op__msr [34:32] - case - assign $9\msr[34:32] \ra [34:32] - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $7\msr[59:13] [46:19] \$75 [59:32] - assign $8\msr[63:61] \$75 [63:61] - assign $6\msr[11:1] \ra [11:1] - assign $7\msr[59:13] [18:0] \ra [31:13] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" - switch $7\msr[59:13] [1] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $11\msr[15:15] 1'1 - assign $10\msr[5:4] [1] 1'1 - assign $10\msr[5:4] [0] 1'1 - case - assign $10\msr[5:4] $6\msr[11:1] [4:3] - assign $11\msr[15:15] $7\msr[59:13] [2] - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $13\msr[60:60] \trap_op__msr [60] - assign $12\msr[12:12] \trap_op__msr [12] - case - assign $12\msr[12:12] \$75 [12] - assign $13\msr[60:60] \$75 [60] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\msr_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000110 - assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 - assign { } { } - assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } - assign $1\msr[63:0] [26:22] \fast2 [26:22] - assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } - assign $1\msr[63:0] [12] $14\msr[12:12] - assign $1\msr[63:0] [5:4] $16\msr[5:4] - assign $1\msr[63:0] [15] $17\msr[15:15] - assign $1\msr[63:0] [34:32] $18\msr[34:32] - assign $1\msr_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $14\msr[12:12] $15\msr[12:12] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" - switch \trap_op__msr [60] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $15\msr[12:12] \fast2 [12] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $15\msr[12:12] \trap_op__msr [12] - end - case - assign $14\msr[12:12] \fast2 [12] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" - switch \fast2 [14] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign $17\msr[15:15] 1'1 - assign $16\msr[5:4] [1] 1'1 - assign $16\msr[5:4] [0] 1'1 - case - assign $16\msr[5:4] \fast2 [5:4] - assign $17\msr[15:15] \fast2 [15] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $18\msr[34:32] \trap_op__msr [34:32] - case - assign $18\msr[34:32] \fast2 [34:32] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'1001001 - assign { } { } - assign { } { } - assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } - assign $1\msr[63:0] [63] 1'1 - assign $1\msr[63:0] [15] 1'0 - assign $1\msr[63:0] [14] 1'0 - assign $1\msr[63:0] [5] 1'0 - assign $1\msr[63:0] [4] 1'0 - assign $1\msr[63:0] [1] 1'0 - assign $1\msr[63:0] [0] 1'1 - assign $1\msr[63:0] [11] 1'0 - assign $1\msr[63:0] [8] 1'0 - assign $1\msr[63:0] [23] 1'0 - assign $1\msr[63:0] [32] 1'0 - assign $1\msr[63:0] [25] 1'0 - assign $1\msr[63:0] [13] 1'0 - assign $1\msr[63:0] [3] 1'0 - assign $1\msr[63:0] [10] 1'0 - assign $1\msr[63:0] [9] 1'0 - assign $1\msr[63:0] [58] 1'0 - assign $1\msr_ok[0:0] 1'1 - case - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\msr_ok[0:0] 1'0 - end - sync always - update \msr $0\msr[63:0] - update \msr_ok $0\msr_ok[0:0] - end - attribute \src "libresoc.v:138722.3-138740.6" - process $proc$libresoc.v:138722$7176 - assign { } { } - assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:138723.5-138723.29" - switch \initial - attribute \src "libresoc.v:138723.9-138723.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign { } { } - assign $1\o[63:0] \trap_op__msr - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o $0\o[63:0] - end - attribute \src "libresoc.v:138741.3-138759.6" - process $proc$libresoc.v:138741$7177 - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:138742.5-138742.29" - switch \initial - attribute \src "libresoc.v:138742.9-138742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" - switch \trap_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0111111 - assign $1\o_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1001000 , 7'1001010 - assign $1\o_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000111 - assign { } { } - assign $1\o_ok[0:0] 1'1 - case - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:138760.3-138771.6" - process $proc$libresoc.v:138760$7178 - assign { } { } - assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:138761.5-138761.29" - switch \initial - attribute \src "libresoc.v:138761.9-138761.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\a[63:0] \$13 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\a[63:0] \ra - end - sync always - update \a $0\a[63:0] - end - attribute \src "libresoc.v:138772.3-138783.6" - process $proc$libresoc.v:138772$7179 - assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:138773.5-138773.29" - switch \initial - attribute \src "libresoc.v:138773.9-138773.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" - switch \trap_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\b[63:0] \$15 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\b[63:0] \rb - end - sync always - update \b $0\b[63:0] - end - connect \$13 $pos$libresoc.v:138221$7080_Y - connect \$15 $pos$libresoc.v:138222$7082_Y - connect \$17 $lt$libresoc.v:138223$7083_Y - connect \$19 $gt$libresoc.v:138224$7084_Y - connect \$21 $lt$libresoc.v:138225$7085_Y - connect \$23 $gt$libresoc.v:138226$7086_Y - connect \$25 $eq$libresoc.v:138227$7087_Y - connect \$28 $and$libresoc.v:138228$7088_Y - connect \$27 $reduce_or$libresoc.v:138229$7089_Y - connect \$31 $reduce_or$libresoc.v:138230$7090_Y - connect \$33 $or$libresoc.v:138231$7091_Y - connect \$36 $sshl$libresoc.v:138232$7092_Y - connect \$35 $pos$libresoc.v:138233$7094_Y - connect \$40 $add$libresoc.v:138234$7095_Y - connect \$42 $eq$libresoc.v:138235$7096_Y - connect \$45 $and$libresoc.v:138236$7097_Y - connect \$44 $reduce_or$libresoc.v:138237$7098_Y - connect \$49 $and$libresoc.v:138238$7099_Y - connect \$48 $reduce_or$libresoc.v:138239$7100_Y - connect \$53 $and$libresoc.v:138240$7101_Y - connect \$52 $reduce_or$libresoc.v:138241$7102_Y - connect \$57 $and$libresoc.v:138242$7103_Y - connect \$56 $reduce_or$libresoc.v:138243$7104_Y - connect \$64 $and$libresoc.v:138244$7105_Y - connect \$63 $reduce_or$libresoc.v:138245$7106_Y - connect \$72 $and$libresoc.v:138246$7107_Y - connect \$71 $reduce_or$libresoc.v:138247$7108_Y - connect \$75 $pos$libresoc.v:138248$7110_Y - connect \$77 $eq$libresoc.v:138249$7111_Y - connect \$79 $eq$libresoc.v:138250$7112_Y - connect \$81 $eq$libresoc.v:138251$7113_Y - connect \$83 $and$libresoc.v:138252$7114_Y - connect \$85 $not$libresoc.v:138253$7115_Y - connect \$87 $not$libresoc.v:138254$7116_Y - connect \$89 $eq$libresoc.v:138255$7117_Y - connect \$91 $eq$libresoc.v:138256$7118_Y - connect \$93 $and$libresoc.v:138257$7119_Y - connect \$39 \$40 - connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" - wire width 64 \bpermd_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" - wire width 64 \bpermd_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" - wire width 64 \bpermd_rs - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 7 \clz_lz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" - wire width 64 \clz_sig_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" - wire width 64 \cntz_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" - wire \count_right - attribute \src "libresoc.v:138800.7-138800.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 44 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 41 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 42 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" - wire \par0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" - wire \par1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" - wire width 64 \popcount_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" - wire width 64 \popcount_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" - wire width 64 \popcount_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 43 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:139302$7227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $and$libresoc.v:139302$7227_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139261$7181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139261$7181_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139262$7182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139262$7182_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139263$7183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139263$7183_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139264$7184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139264$7184_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139265$7185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139265$7185_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139266$7186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139266$7186_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139267$7187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139267$7187_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139268$7188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139268$7188_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139269$7189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139269$7189_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139270$7190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139270$7190_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139271$7191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139271$7191_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139272$7192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $eq$libresoc.v:139272$7192_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139273$7193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139273$7193_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139274$7194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139274$7194_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139275$7195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139275$7195_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139276$7196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139276$7196_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139277$7197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139277$7197_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139278$7198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139278$7198_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139279$7199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139279$7199_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139280$7200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $eq$libresoc.v:139280$7200_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139281$7201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139281$7201_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139282$7202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139282$7202_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139283$7203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139283$7203_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139284$7204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139284$7204_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139285$7205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139285$7205_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139286$7206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139286$7206_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139287$7207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139287$7207_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139288$7208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $eq$libresoc.v:139288$7208_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:139289$7209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__data_len [3] - connect \B 1'1 - connect \Y $eq$libresoc.v:139289$7209_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139305$7230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139305$7230_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139306$7231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139306$7231_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139307$7232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139307$7232_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139308$7233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139308$7233_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139309$7234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139309$7234_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139310$7235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139310$7235_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139311$7236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139311$7236_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139312$7237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $eq$libresoc.v:139312$7237_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139313$7238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139313$7238_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139314$7239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139314$7239_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139315$7240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139315$7240_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139316$7241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139316$7241_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139317$7242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139317$7242_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139318$7243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139318$7243_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139319$7244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139319$7244_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139320$7245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $eq$libresoc.v:139320$7245_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139321$7246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139321$7246_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139322$7247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139322$7247_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139323$7248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139323$7248_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139324$7249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139324$7249_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139325$7250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139325$7250_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139326$7251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139326$7251_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139327$7252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139327$7252_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139328$7253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $eq$libresoc.v:139328$7253_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139329$7254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139329$7254_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139330$7255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139330$7255_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139331$7256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139331$7256_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139332$7257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139332$7257_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139333$7258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139333$7258_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139334$7259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139334$7259_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139335$7260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139335$7260_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139336$7261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $eq$libresoc.v:139336$7261_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139337$7262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139337$7262_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139338$7263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139338$7263_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139339$7264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139339$7264_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:139340$7265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $eq$libresoc.v:139340$7265_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:139291$7211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 64 - connect \A \$158 - connect \Y $extend$libresoc.v:139291$7211_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $extend$libresoc.v:139293$7214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \Y $extend$libresoc.v:139293$7214_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:139295$7217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A \$166 - connect \Y $extend$libresoc.v:139295$7217_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:139296$7219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 64 - connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:139296$7219_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:139300$7224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \$176 - connect \Y $extend$libresoc.v:139300$7224_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:139303$7228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $or$libresoc.v:139303$7228_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:139291$7212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139291$7211_Y - connect \Y $pos$libresoc.v:139291$7212_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $pos$libresoc.v:139293$7215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:139293$7214_Y - connect \Y $pos$libresoc.v:139293$7215_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:139295$7218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139295$7217_Y - connect \Y $pos$libresoc.v:139295$7218_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:139296$7220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139296$7219_Y - connect \Y $pos$libresoc.v:139296$7220_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:139300$7225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139300$7224_Y - connect \Y $pos$libresoc.v:139300$7225_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:139297$7221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:139297$7221_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:139298$7222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:139298$7222_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:139292$7213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \B 6'100000 - connect \Y $sub$libresoc.v:139292$7213_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:139294$7216 - parameter \WIDTH 8 - connect \A \$164 - connect \B \$162 - connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:139294$7216_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:139299$7223 - parameter \WIDTH 32 - connect \A \a32 - connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } - connect \S \count_right - connect \Y $ternary$libresoc.v:139299$7223_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:139301$7226 - parameter \WIDTH 64 - connect \A \ra - connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } - connect \S \count_right - connect \Y $ternary$libresoc.v:139301$7226_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:139290$7210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \par0 - connect \B \par1 - connect \Y $xor$libresoc.v:139290$7210_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:139304$7229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $xor$libresoc.v:139304$7229_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:139341.10-139345.4" - cell \bpermd \bpermd - connect \ra \bpermd_ra - connect \rb \bpermd_rb - connect \rs \bpermd_rs - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:139346.7-139349.4" - cell \clz \clz - connect \lz \clz_lz - connect \sig_in \clz_sig_in - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:139350.12-139354.4" - cell \popcount \popcount - connect \a \popcount_a - connect \data_len \popcount_data_len - connect \o \popcount_o - end - attribute \src "libresoc.v:138800.7-138800.20" - process $proc$libresoc.v:138800$7278 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:139355.3-139409.6" - process $proc$libresoc.v:139355$7266 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:139356.5-139356.29" - switch \initial - attribute \src "libresoc.v:139356.9-139356.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0000100 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$21 - attribute \src "libresoc.v:0.0-0.0" - case 7'0110101 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$23 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000011 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$25 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001011 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } - attribute \src "libresoc.v:0.0-0.0" - case 7'0110110 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \popcount_o - attribute \src "libresoc.v:0.0-0.0" - case 7'0110111 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - switch \$155 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o[63:0] \$157 - attribute \src "libresoc.v:0.0-0.0" - case - assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 - assign $2\o[63:0] [0] \par0 - assign $2\o[63:0] [32] \par1 - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0001110 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \$161 - attribute \src "libresoc.v:0.0-0.0" - case 7'0001001 - assign $1\o_ok[0:0] 1'1 - assign { } { } - assign $1\o[63:0] \bpermd_ra - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] - end - attribute \src "libresoc.v:139410.3-139420.6" - process $proc$libresoc.v:139410$7267 - assign { } { } - assign { } { } - assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:139411.5-139411.29" - switch \initial - attribute \src "libresoc.v:139411.9-139411.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001110 - assign { } { } - assign $1\clz_sig_in[63:0] \cntz_i - case - assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \clz_sig_in $0\clz_sig_in[63:0] - end - attribute \src "libresoc.v:139421.3-139431.6" - process $proc$libresoc.v:139421$7268 - assign { } { } - assign { } { } - assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:139422.5-139422.29" - switch \initial - attribute \src "libresoc.v:139422.9-139422.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001001 - assign { } { } - assign $1\bpermd_rs[63:0] \ra - case - assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \bpermd_rs $0\bpermd_rs[63:0] - end - attribute \src "libresoc.v:139432.3-139442.6" - process $proc$libresoc.v:139432$7269 - assign { } { } - assign { } { } - assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:139433.5-139433.29" - switch \initial - attribute \src "libresoc.v:139433.9-139433.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0001001 - assign { } { } - assign $1\bpermd_rb[63:0] \rb - case - assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \bpermd_rb $0\bpermd_rb[63:0] - end - attribute \src "libresoc.v:139443.3-139453.6" - process $proc$libresoc.v:139443$7270 - assign { } { } - assign { } { } - assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:139444.5-139444.29" - switch \initial - attribute \src "libresoc.v:139444.9-139444.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\popcount_a[63:0] \ra - case - assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \popcount_a $0\popcount_a[63:0] - end - attribute \src "libresoc.v:139454.3-139464.6" - process $proc$libresoc.v:139454$7271 - assign { } { } - assign { } { } - assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:139455.5-139455.29" - switch \initial - attribute \src "libresoc.v:139455.9-139455.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110110 - assign { } { } - assign $1\b[63:0] \rb - case - assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \b $0\b[63:0] - end - attribute \src "libresoc.v:139465.3-139475.6" - process $proc$libresoc.v:139465$7272 - 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input 3 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \cr_op__insn$4 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute 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"OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \cr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 11 \cr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 6 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 output 16 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 17 \full_cr_ok - attribute \src "libresoc.v:139547.7-139547.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" - wire width 4 \lut - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 20 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 10 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 15 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 4 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 5 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139818$7285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \full_cr - connect \Y $extend$libresoc.v:139818$7285_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:139820$7288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$27 - connect \Y $extend$libresoc.v:139820$7288_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:139821$7290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A \cr_a - connect \Y $extend$libresoc.v:139821$7290_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139818$7286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:139818$7285_Y - connect \Y $pos$libresoc.v:139818$7286_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:139820$7289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:139820$7288_Y - connect \Y $pos$libresoc.v:139820$7289_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:139821$7291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:139821$7290_Y - connect \Y $pos$libresoc.v:139821$7291_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:139812$7279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:139812$7279_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:139813$7280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:139813$7280_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:139814$7281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:139814$7281_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:139815$7282 - parameter \WIDTH 1 - connect \A \lut [1] - connect \B \lut [3] - connect \S \bit_a - connect \Y $ternary$libresoc.v:139815$7282_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:139816$7283 - parameter \WIDTH 1 - connect \A \lut [0] - connect \B \lut [2] - connect \S \bit_a - connect \Y $ternary$libresoc.v:139816$7283_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:139817$7284 - parameter \WIDTH 1 - connect \A \$20 - connect \B \$18 - connect \S \bit_b - connect \Y $ternary$libresoc.v:139817$7284_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:139819$7287 - parameter \WIDTH 64 - connect \A \rb - connect \B \ra - connect \S \cr_bit - connect \Y $ternary$libresoc.v:139819$7287_Y - end - attribute \src "libresoc.v:139547.7-139547.20" - process $proc$libresoc.v:139547$7310 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:139822.3-139856.6" - process $proc$libresoc.v:139822$7292 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7293 $1\cr_a$6[3:0]$7294 - attribute \src "libresoc.v:139823.5-139823.29" - switch \initial - attribute \src "libresoc.v:139823.9-139823.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0101010 - assign { } { } - assign { } { } - assign $1\cr_a$6[3:0]$7294 \$7 [3:0] - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign { } { } - assign { } { } - assign $1\cr_a$6[3:0]$7294 $2\cr_a$6[3:0]$7295 - assign $1\cr_a_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" - switch \bt - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign $2\cr_a$6[3:0]$7295 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7295 [0] \bit_o - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { $2\cr_a$6[3:0]$7295 [3:2] $2\cr_a$6[3:0]$7295 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7295 [1] \bit_o - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { $2\cr_a$6[3:0]$7295 [3] $2\cr_a$6[3:0]$7295 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7295 [2] \bit_o - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign $2\cr_a$6[3:0]$7295 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7295 [3] \bit_o - case - assign $2\cr_a$6[3:0]$7295 \cr_c - end - case - assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7294 4'0000 - end - sync always - update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7293 - end - attribute \src "libresoc.v:139857.3-139867.6" - process $proc$libresoc.v:139857$7296 - assign { } { } - assign { } { } - assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:139858.5-139858.29" - switch \initial - attribute \src "libresoc.v:139858.9-139858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110000 - assign { } { } - assign $1\full_cr_ok[0:0] 1'1 - case - assign $1\full_cr_ok[0:0] 1'0 - end - sync always - update \full_cr_ok $0\full_cr_ok[0:0] - end - attribute \src "libresoc.v:139868.3-139909.6" - process $proc$libresoc.v:139868$7297 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:139869.5-139869.29" - switch \initial - attribute \src "libresoc.v:139869.9-139869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0101101 - assign { } { } - assign { } { } - assign $1\o[63:0] \$24 - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign { } { } - assign $1\o[63:0] \$26 [63:0] - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0111011 - assign { } { } - assign { } { } - assign $1\o[63:0] $2\o[63:0] - assign $1\o_ok[0:0] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" - switch { \cr_a [2] \cr_a [3] } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\o_ok[0:0] 1'0 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] - end - attribute \src "libresoc.v:139910.3-139920.6" - process $proc$libresoc.v:139910$7298 - assign { } { } - assign { } { } - assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:139911.5-139911.29" - switch \initial - attribute \src "libresoc.v:139911.9-139911.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign $1\BC[1:0] \cr_op__insn [7:6] - case - assign $1\BC[1:0] 2'00 - end - sync always - update \BC $0\BC[1:0] - end - attribute \src "libresoc.v:139921.3-139941.6" - process $proc$libresoc.v:139921$7299 - assign { } { } - assign { } { } - assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:139922.5-139922.29" - switch \initial - attribute \src "libresoc.v:139922.9-139922.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0100011 - assign { } { } - assign $1\cr_bit[0:0] $2\cr_bit[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" - switch \BC - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [3] - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [2] - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\cr_bit[0:0] \cr_a [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\cr_bit[0:0] \cr_a [0] - case - assign $2\cr_bit[0:0] 1'0 - end - case - assign $1\cr_bit[0:0] 1'0 - end - sync always - update \cr_bit $0\cr_bit[0:0] - end - attribute \src "libresoc.v:139942.3-139952.6" - process $proc$libresoc.v:139942$7300 - assign { } { } - assign { } { } - assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:139943.5-139943.29" - switch \initial - attribute \src "libresoc.v:139943.9-139943.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\lut[3:0] \cr_op__insn [9:6] - case - assign $1\lut[3:0] 4'0000 - end - sync always - update \lut $0\lut[3:0] - end - attribute \src "libresoc.v:139953.3-139963.6" - process $proc$libresoc.v:139953$7301 - assign { } { } - assign { } { } - assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:139954.5-139954.29" - switch \initial - attribute \src "libresoc.v:139954.9-139954.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bt[1:0] \$9 [1:0] - case - assign $1\bt[1:0] 2'00 - end - sync always - update \bt $0\bt[1:0] - end - attribute \src "libresoc.v:139964.3-139974.6" - process $proc$libresoc.v:139964$7302 - assign { } { } - assign { } { } - assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:139965.5-139965.29" - switch \initial - attribute \src "libresoc.v:139965.9-139965.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\ba[1:0] \$12 [1:0] - case - assign $1\ba[1:0] 2'00 - end - sync always - update \ba $0\ba[1:0] - end - attribute \src "libresoc.v:139975.3-139985.6" - process $proc$libresoc.v:139975$7303 - assign { } { } - assign { } { } - assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:139976.5-139976.29" - switch \initial - attribute \src "libresoc.v:139976.9-139976.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bb[1:0] \$15 [1:0] - case - assign $1\bb[1:0] 2'00 - end - sync always - update \bb $0\bb[1:0] - end - attribute \src "libresoc.v:139986.3-140006.6" - process $proc$libresoc.v:139986$7304 - assign { } { } - assign { } { } - assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:139987.5-139987.29" - switch \initial - attribute \src "libresoc.v:139987.9-139987.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_a[0:0] $2\bit_a[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" - switch \ba - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\bit_a[0:0] \cr_a [0] - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\bit_a[0:0] \cr_a [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\bit_a[0:0] \cr_a [2] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\bit_a[0:0] \cr_a [3] - case - assign $2\bit_a[0:0] 1'0 - end - case - assign $1\bit_a[0:0] 1'0 - end - sync always - update \bit_a $0\bit_a[0:0] - end - attribute \src "libresoc.v:140007.3-140027.6" - process $proc$libresoc.v:140007$7305 - assign { } { } - assign { } { } - assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:140008.5-140008.29" - switch \initial - attribute \src "libresoc.v:140008.9-140008.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_b[0:0] $2\bit_b[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - switch \bb - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $2\bit_b[0:0] \cr_b [0] - attribute \src "libresoc.v:0.0-0.0" - case 2'01 - assign { } { } - assign $2\bit_b[0:0] \cr_b [1] - attribute \src "libresoc.v:0.0-0.0" - case 2'10 - assign { } { } - assign $2\bit_b[0:0] \cr_b [2] - attribute \src "libresoc.v:0.0-0.0" - case 2'-- - assign { } { } - assign $2\bit_b[0:0] \cr_b [3] - case - assign $2\bit_b[0:0] 1'0 - end - case - assign $1\bit_b[0:0] 1'0 - end - sync always - update \bit_b $0\bit_b[0:0] - end - attribute \src "libresoc.v:140028.3-140038.6" - process $proc$libresoc.v:140028$7306 - assign { } { } - assign { } { } - assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:140029.5-140029.29" - switch \initial - attribute \src "libresoc.v:140029.9-140029.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'1000101 - assign { } { } - assign $1\bit_o[0:0] \$22 - case - assign $1\bit_o[0:0] 1'0 - end - sync always - update \bit_o $0\bit_o[0:0] - end - attribute \src "libresoc.v:140039.3-140049.6" - process $proc$libresoc.v:140039$7307 - assign { } { } - assign { } { } - assign $0\full_cr$5[31:0]$7308 $1\full_cr$5[31:0]$7309 - attribute \src "libresoc.v:140040.5-140040.29" - switch \initial - attribute \src "libresoc.v:140040.9-140040.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110000 - assign { } { } - assign $1\full_cr$5[31:0]$7309 \ra [31:0] - case - assign $1\full_cr$5[31:0]$7309 0 - end - sync always - update \full_cr$5 $0\full_cr$5[31:0]$7308 - end - connect \$10 $sub$libresoc.v:139812$7279_Y - connect \$13 $sub$libresoc.v:139813$7280_Y - connect \$16 $sub$libresoc.v:139814$7281_Y - connect \$18 $ternary$libresoc.v:139815$7282_Y - connect \$20 $ternary$libresoc.v:139816$7283_Y - connect \$22 $ternary$libresoc.v:139817$7284_Y - connect \$24 $pos$libresoc.v:139818$7286_Y - connect \$27 $ternary$libresoc.v:139819$7287_Y - connect \$26 $pos$libresoc.v:139820$7289_Y - connect \$7 $pos$libresoc.v:139821$7291_Y - connect \$9 \$10 - connect \$12 \$13 - connect \$15 \$16 - connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - connect \muxid$1 \muxid -end -attribute \src "libresoc.v:140059.1-141214.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" -attribute \generator "nMigen" -module \mul0 - attribute \src "libresoc.v:140785.3-140786.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:140783.3-140784.40" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:141126.3-141134.6" - wire $0\alu_l_r_alu$next[0:0]$7516 - attribute \src "libresoc.v:140711.3-140712.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$7441 - attribute \src "libresoc.v:140739.3-140740.65" - wire width 12 $0\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7442 - attribute \src "libresoc.v:140741.3-140742.79" - wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7443 - attribute \src "libresoc.v:140743.3-140744.75" - wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7444 - attribute \src "libresoc.v:140759.3-140760.59" - wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7445 - attribute \src "libresoc.v:140737.3-140738.69" - wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7446 - attribute \src "libresoc.v:140755.3-140756.67" - wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7447 - attribute \src "libresoc.v:140757.3-140758.69" - wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7448 - attribute \src "libresoc.v:140749.3-140750.63" - wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7449 - attribute \src "libresoc.v:140751.3-140752.63" - wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7450 - attribute \src "libresoc.v:140747.3-140748.63" - wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7451 - attribute \src "libresoc.v:140745.3-140746.63" - wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7452 - attribute \src "libresoc.v:140753.3-140754.69" - wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:141117.3-141125.6" - wire $0\alui_l_r_alui$next[0:0]$7513 - attribute \src "libresoc.v:140713.3-140714.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:140999.3-141020.6" - wire width 64 $0\data_r0__o$next[63:0]$7472 - attribute \src "libresoc.v:140733.3-140734.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:140999.3-141020.6" - wire $0\data_r0__o_ok$next[0:0]$7473 - attribute \src "libresoc.v:140735.3-140736.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:141021.3-141042.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7480 - attribute \src "libresoc.v:140729.3-140730.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:141021.3-141042.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7481 - attribute \src "libresoc.v:140731.3-140732.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:141043.3-141064.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7488 - attribute \src "libresoc.v:140725.3-140726.47" - wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:141043.3-141064.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7489 - attribute \src "libresoc.v:140727.3-140728.53" - wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:141065.3-141086.6" - wire $0\data_r3__xer_so$next[0:0]$7496 - attribute \src "libresoc.v:140721.3-140722.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:141065.3-141086.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7497 - attribute \src "libresoc.v:140723.3-140724.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:141135.3-141144.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:141145.3-141154.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:141155.3-141164.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:141165.3-141174.6" - wire $0\dest4_o[0:0] - attribute \src "libresoc.v:140060.7-140060.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:140921.3-140929.6" - wire $0\opc_l_r_opc$next[0:0]$7426 - attribute \src "libresoc.v:140769.3-140770.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:140912.3-140920.6" - wire $0\opc_l_s_opc$next[0:0]$7423 - attribute \src "libresoc.v:140771.3-140772.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:141175.3-141183.6" - wire width 4 $0\prev_wr_go$next[3:0]$7523 - attribute \src "libresoc.v:140781.3-140782.37" - wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:140866.3-140875.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:140957.3-140965.6" - wire width 4 $0\req_l_r_req$next[3:0]$7438 - attribute \src "libresoc.v:140761.3-140762.39" - wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:140948.3-140956.6" - wire width 4 $0\req_l_s_req$next[3:0]$7435 - attribute \src "libresoc.v:140763.3-140764.39" - wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:140885.3-140893.6" - wire $0\rok_l_r_rdok$next[0:0]$7414 - attribute \src "libresoc.v:140777.3-140778.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:140876.3-140884.6" - wire $0\rok_l_s_rdok$next[0:0]$7411 - attribute \src "libresoc.v:140779.3-140780.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:140903.3-140911.6" - wire $0\rst_l_r_rst$next[0:0]$7420 - attribute \src "libresoc.v:140773.3-140774.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:140894.3-140902.6" - wire $0\rst_l_s_rst$next[0:0]$7417 - attribute \src "libresoc.v:140775.3-140776.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:140939.3-140947.6" - wire width 3 $0\src_l_r_src$next[2:0]$7432 - attribute \src "libresoc.v:140765.3-140766.39" - wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:140930.3-140938.6" - wire width 3 $0\src_l_s_src$next[2:0]$7429 - attribute \src "libresoc.v:140767.3-140768.39" - wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:141087.3-141096.6" - wire width 64 $0\src_r0$next[63:0]$7504 - attribute \src "libresoc.v:140719.3-140720.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:141097.3-141106.6" - wire width 64 $0\src_r1$next[63:0]$7507 - attribute \src "libresoc.v:140717.3-140718.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:141107.3-141116.6" - wire $0\src_r2$next[0:0]$7510 - attribute \src "libresoc.v:140715.3-140716.29" - wire $0\src_r2[0:0] - attribute \src "libresoc.v:140184.7-140184.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:140194.7-140194.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:141126.3-141134.6" - wire $1\alu_l_r_alu$next[0:0]$7517 - attribute \src "libresoc.v:140202.7-140202.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 - attribute \src "libresoc.v:140223.14-140223.48" - wire width 12 $1\alu_mul0_mul_op__fn_unit[11:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 - attribute \src "libresoc.v:140227.14-140227.68" - wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 - attribute \src "libresoc.v:140231.7-140231.43" - wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7456 - attribute \src "libresoc.v:140235.14-140235.43" - wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 - attribute \src "libresoc.v:140313.13-140313.47" - wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:140966.3-140998.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 - attribute \src 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$eq$libresoc.v:140680$7340_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:140682$7342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:140682$7342_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:140663$7323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$libresoc.v:140663$7323_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:140665$7325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$libresoc.v:140665$7325_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not 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$or$libresoc.v:140686$7346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140686$7346_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:140687$7347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:140687$7347_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:140689$7349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140689$7349_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:140690$7350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:140690$7350_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:140693$7353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:140693$7353_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:140699$7359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$5 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:140699$7359_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:140705$7365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$7 - connect \Y $reduce_and$libresoc.v:140705$7365_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:140670$7330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$libresoc.v:140670$7330_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:140674$7334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:140674$7334_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:140675$7335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:140675$7335_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:140698$7358 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:140698$7358_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:140700$7360 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_mul0_mul_op__imm_data__data - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:140700$7360_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:140701$7361 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:140701$7361_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:140702$7362 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:140702$7362_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:140703$7363 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:140703$7363_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140787.15-140793.4" - cell \alu_l$107 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140794.12-140824.4" - cell \alu_mul0 \alu_mul0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_mul0_cr_a - connect \cr_a_ok \cr_a_ok - connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit - connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data - connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok - connect \mul_op__insn \alu_mul0_mul_op__insn - connect \mul_op__insn_type \alu_mul0_mul_op__insn_type - connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit - connect \mul_op__is_signed \alu_mul0_mul_op__is_signed - connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe - connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok - connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok - connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc - connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 - connect \n_ready_i \alu_mul0_n_ready_i - connect \n_valid_o \alu_mul0_n_valid_o - connect \o \alu_mul0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_mul0_p_ready_o - connect \p_valid_i \alu_mul0_p_valid_i - connect \ra \alu_mul0_ra - connect \rb \alu_mul0_rb - connect \xer_ov \alu_mul0_xer_ov - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_mul0_xer_so - connect \xer_so$1 \alu_mul0_xer_so$1 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140825.16-140831.4" - cell \alui_l$106 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140832.15-140838.4" - cell \opc_l$102 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140839.15-140845.4" - cell \req_l$103 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140846.15-140852.4" - cell \rok_l$105 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140853.15-140858.4" - cell \rst_l$104 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:140859.15-140865.4" - cell \src_l$101 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:140060.7-140060.20" - process $proc$libresoc.v:140060$7525 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:140184.7-140184.24" - process $proc$libresoc.v:140184$7526 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:140194.7-140194.26" - process $proc$libresoc.v:140194$7527 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:140202.7-140202.25" - process $proc$libresoc.v:140202$7528 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:140223.14-140223.48" - process $proc$libresoc.v:140223$7529 - assign { } { } - assign $1\alu_mul0_mul_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[11:0] - end - attribute \src "libresoc.v:140227.14-140227.68" - process $proc$libresoc.v:140227$7530 - assign { } { } - assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:140231.7-140231.43" - process $proc$libresoc.v:140231$7531 - assign { } { } - assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:140235.14-140235.43" - process $proc$libresoc.v:140235$7532 - assign { } { } - assign $1\alu_mul0_mul_op__insn[31:0] 0 - sync always - sync init - update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] - end - attribute \src "libresoc.v:140313.13-140313.47" - process $proc$libresoc.v:140313$7533 - assign { } { } - assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] - end - attribute \src "libresoc.v:140317.7-140317.39" - process $proc$libresoc.v:140317$7534 - assign { } { } - assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] - end - attribute \src "libresoc.v:140321.7-140321.40" - process $proc$libresoc.v:140321$7535 - assign { } { } - assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] - end - attribute \src "libresoc.v:140325.7-140325.37" - process $proc$libresoc.v:140325$7536 - assign { } { } - assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] - end - attribute \src "libresoc.v:140329.7-140329.37" - process $proc$libresoc.v:140329$7537 - assign { } { } - assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] - end - attribute \src "libresoc.v:140333.7-140333.37" - process $proc$libresoc.v:140333$7538 - assign { } { } - assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] - end - attribute \src "libresoc.v:140337.7-140337.37" - process $proc$libresoc.v:140337$7539 - assign { } { } - assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] - end - attribute \src "libresoc.v:140341.7-140341.40" - process $proc$libresoc.v:140341$7540 - assign { } { } - assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] - end - attribute \src "libresoc.v:140371.7-140371.27" - process $proc$libresoc.v:140371$7541 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:140405.14-140405.47" - process $proc$libresoc.v:140405$7542 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:140409.7-140409.27" - process $proc$libresoc.v:140409$7543 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:140413.13-140413.33" - process $proc$libresoc.v:140413$7544 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:140417.7-140417.30" - process $proc$libresoc.v:140417$7545 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:140421.13-140421.35" - process $proc$libresoc.v:140421$7546 - assign { } { } - assign $1\data_r2__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] - end - attribute \src "libresoc.v:140425.7-140425.32" - process $proc$libresoc.v:140425$7547 - assign { } { } - assign $1\data_r2__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:140429.7-140429.29" - process $proc$libresoc.v:140429$7548 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:140433.7-140433.32" - process $proc$libresoc.v:140433$7549 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:140453.7-140453.25" - process $proc$libresoc.v:140453$7550 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:140457.7-140457.25" - process $proc$libresoc.v:140457$7551 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:140572.13-140572.30" - process $proc$libresoc.v:140572$7552 - assign { } { } - assign $1\prev_wr_go[3:0] 4'0000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[3:0] - end - attribute \src "libresoc.v:140580.13-140580.31" - process $proc$libresoc.v:140580$7553 - assign { } { } - assign $1\req_l_r_req[3:0] 4'1111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[3:0] - end - attribute \src "libresoc.v:140584.13-140584.31" - process $proc$libresoc.v:140584$7554 - assign { } { } - assign $1\req_l_s_req[3:0] 4'0000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[3:0] - end - attribute \src "libresoc.v:140596.7-140596.26" - process $proc$libresoc.v:140596$7555 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:140600.7-140600.26" - process $proc$libresoc.v:140600$7556 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:140604.7-140604.25" - process $proc$libresoc.v:140604$7557 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:140608.7-140608.25" - process $proc$libresoc.v:140608$7558 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:140622.13-140622.31" - process $proc$libresoc.v:140622$7559 - assign { } { } - assign $1\src_l_r_src[2:0] 3'111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[2:0] - end - attribute \src "libresoc.v:140626.13-140626.31" - process $proc$libresoc.v:140626$7560 - assign { } { } - assign $1\src_l_s_src[2:0] 3'000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[2:0] - end - attribute \src "libresoc.v:140632.14-140632.43" - process $proc$libresoc.v:140632$7561 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:140636.14-140636.43" - process $proc$libresoc.v:140636$7562 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:140640.7-140640.20" - process $proc$libresoc.v:140640$7563 - assign { } { } - assign $1\src_r2[0:0] 1'0 - sync always - sync init - update \src_r2 $1\src_r2[0:0] - end - attribute \src "libresoc.v:140711.3-140712.39" - process $proc$libresoc.v:140711$7371 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:140713.3-140714.43" - process $proc$libresoc.v:140713$7372 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:140715.3-140716.29" - process $proc$libresoc.v:140715$7373 - assign { } { } - assign $0\src_r2[0:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[0:0] - end - attribute \src "libresoc.v:140717.3-140718.29" - process $proc$libresoc.v:140717$7374 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:140719.3-140720.29" - process $proc$libresoc.v:140719$7375 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:140721.3-140722.47" - process $proc$libresoc.v:140721$7376 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:140723.3-140724.53" - process $proc$libresoc.v:140723$7377 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:140725.3-140726.47" - process $proc$libresoc.v:140725$7378 - assign { } { } - assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next - sync posedge \coresync_clk - update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] - end - attribute \src "libresoc.v:140727.3-140728.53" - process $proc$libresoc.v:140727$7379 - assign { } { } - assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:140729.3-140730.43" - process $proc$libresoc.v:140729$7380 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:140731.3-140732.49" - process $proc$libresoc.v:140731$7381 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:140733.3-140734.37" - process $proc$libresoc.v:140733$7382 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:140735.3-140736.43" - process $proc$libresoc.v:140735$7383 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:140737.3-140738.69" - process $proc$libresoc.v:140737$7384 - assign { } { } - assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] - end - attribute \src "libresoc.v:140739.3-140740.65" - process $proc$libresoc.v:140739$7385 - assign { } { } - assign $0\alu_mul0_mul_op__fn_unit[11:0] \alu_mul0_mul_op__fn_unit$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[11:0] - end - attribute \src "libresoc.v:140741.3-140742.79" - process $proc$libresoc.v:140741$7386 - assign { } { } - assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:140743.3-140744.75" - process $proc$libresoc.v:140743$7387 - assign { } { } - assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:140745.3-140746.63" - process $proc$libresoc.v:140745$7388 - assign { } { } - assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] - end - attribute \src "libresoc.v:140747.3-140748.63" - process $proc$libresoc.v:140747$7389 - assign { } { } - assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] - end - attribute \src "libresoc.v:140749.3-140750.63" - process $proc$libresoc.v:140749$7390 - assign { } { } - assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] - end - attribute \src "libresoc.v:140751.3-140752.63" - process $proc$libresoc.v:140751$7391 - assign { } { } - assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] - end - attribute \src "libresoc.v:140753.3-140754.69" - process $proc$libresoc.v:140753$7392 - assign { } { } - assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] - end - attribute \src "libresoc.v:140755.3-140756.67" - process $proc$libresoc.v:140755$7393 - assign { } { } - assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] - end - attribute \src "libresoc.v:140757.3-140758.69" - process $proc$libresoc.v:140757$7394 - assign { } { } - assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] - end - attribute \src "libresoc.v:140759.3-140760.59" - process $proc$libresoc.v:140759$7395 - assign { } { } - assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next - sync posedge \coresync_clk - update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] - end - attribute \src "libresoc.v:140761.3-140762.39" - process $proc$libresoc.v:140761$7396 - assign { } { } - assign $0\req_l_r_req[3:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[3:0] - end - attribute \src "libresoc.v:140763.3-140764.39" - process $proc$libresoc.v:140763$7397 - assign { } { } - assign $0\req_l_s_req[3:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[3:0] - end - attribute \src "libresoc.v:140765.3-140766.39" - process $proc$libresoc.v:140765$7398 - assign { } { } - assign $0\src_l_r_src[2:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[2:0] - end - attribute \src "libresoc.v:140767.3-140768.39" - process $proc$libresoc.v:140767$7399 - assign { } { } - assign $0\src_l_s_src[2:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[2:0] - end - attribute \src "libresoc.v:140769.3-140770.39" - process $proc$libresoc.v:140769$7400 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:140771.3-140772.39" - process $proc$libresoc.v:140771$7401 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:140773.3-140774.39" - process $proc$libresoc.v:140773$7402 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:140775.3-140776.39" - process $proc$libresoc.v:140775$7403 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:140777.3-140778.41" - process $proc$libresoc.v:140777$7404 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:140779.3-140780.41" - process $proc$libresoc.v:140779$7405 - assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:140781.3-140782.37" - process $proc$libresoc.v:140781$7406 - assign { } { } - assign $0\prev_wr_go[3:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[3:0] - end - attribute \src "libresoc.v:140783.3-140784.40" - process $proc$libresoc.v:140783$7407 - assign { } { } - assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:140785.3-140786.25" - process $proc$libresoc.v:140785$7408 - assign { } { } - assign $0\all_rd_dly[0:0] \$10 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] - end - attribute \src "libresoc.v:140866.3-140875.6" - process $proc$libresoc.v:140866$7409 - assign { } { } - assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:140867.5-140867.29" - switch \initial - attribute \src "libresoc.v:140867.9-140867.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_done[0:0] 1'1 - case - assign $1\req_done[0:0] \$46 - end - sync always - update \req_done $0\req_done[0:0] - end - attribute \src "libresoc.v:140876.3-140884.6" - process $proc$libresoc.v:140876$7410 - assign { } { } - assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7411 $1\rok_l_s_rdok$next[0:0]$7412 - attribute \src "libresoc.v:140877.5-140877.29" - switch \initial - attribute \src "libresoc.v:140877.9-140877.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7412 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$7412 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7411 - end - attribute \src "libresoc.v:140885.3-140893.6" - process $proc$libresoc.v:140885$7413 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7414 $1\rok_l_r_rdok$next[0:0]$7415 - attribute \src "libresoc.v:140886.5-140886.29" - switch \initial - attribute \src "libresoc.v:140886.9-140886.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7415 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$7415 \$64 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7414 - end - attribute \src "libresoc.v:140894.3-140902.6" - process $proc$libresoc.v:140894$7416 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7417 $1\rst_l_s_rst$next[0:0]$7418 - attribute \src "libresoc.v:140895.5-140895.29" - switch \initial - attribute \src "libresoc.v:140895.9-140895.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7418 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$7418 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7417 - end - attribute \src "libresoc.v:140903.3-140911.6" - process $proc$libresoc.v:140903$7419 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7420 $1\rst_l_r_rst$next[0:0]$7421 - attribute \src "libresoc.v:140904.5-140904.29" - switch \initial - attribute \src "libresoc.v:140904.9-140904.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7421 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$7421 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7420 - end - attribute \src "libresoc.v:140912.3-140920.6" - process $proc$libresoc.v:140912$7422 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7423 $1\opc_l_s_opc$next[0:0]$7424 - attribute \src "libresoc.v:140913.5-140913.29" - switch \initial - attribute \src "libresoc.v:140913.9-140913.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7424 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$7424 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7423 - end - attribute \src "libresoc.v:140921.3-140929.6" - process $proc$libresoc.v:140921$7425 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7426 $1\opc_l_r_opc$next[0:0]$7427 - attribute \src "libresoc.v:140922.5-140922.29" - switch \initial - attribute \src "libresoc.v:140922.9-140922.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7427 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$7427 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7426 - end - attribute \src "libresoc.v:140930.3-140938.6" - process $proc$libresoc.v:140930$7428 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[2:0]$7429 $1\src_l_s_src$next[2:0]$7430 - attribute \src "libresoc.v:140931.5-140931.29" - switch \initial - attribute \src "libresoc.v:140931.9-140931.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_s_src$next[2:0]$7430 3'000 - case - assign $1\src_l_s_src$next[2:0]$7430 { \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7429 - end - attribute \src "libresoc.v:140939.3-140947.6" - process $proc$libresoc.v:140939$7431 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[2:0]$7432 $1\src_l_r_src$next[2:0]$7433 - attribute \src "libresoc.v:140940.5-140940.29" - switch \initial - attribute \src "libresoc.v:140940.9-140940.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_l_r_src$next[2:0]$7433 3'111 - case - assign $1\src_l_r_src$next[2:0]$7433 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7432 - end - attribute \src "libresoc.v:140948.3-140956.6" - process $proc$libresoc.v:140948$7434 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[3:0]$7435 $1\req_l_s_req$next[3:0]$7436 - attribute \src "libresoc.v:140949.5-140949.29" - switch \initial - attribute \src "libresoc.v:140949.9-140949.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_s_req$next[3:0]$7436 4'0000 - case - assign $1\req_l_s_req$next[3:0]$7436 \$66 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7435 - end - attribute \src "libresoc.v:140957.3-140965.6" - process $proc$libresoc.v:140957$7437 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[3:0]$7438 $1\req_l_r_req$next[3:0]$7439 - attribute \src "libresoc.v:140958.5-140958.29" - switch \initial - attribute \src "libresoc.v:140958.9-140958.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\req_l_r_req$next[3:0]$7439 4'1111 - case - assign $1\req_l_r_req$next[3:0]$7439 \$68 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7438 - end - attribute \src "libresoc.v:140966.3-140998.6" - process $proc$libresoc.v:140966$7440 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$7441 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7444 $1\alu_mul0_mul_op__insn$next[31:0]$7456 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7445 $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7446 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7447 $1\alu_mul0_mul_op__is_signed$next[0:0]$7459 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7452 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7464 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7442 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7465 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7443 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7466 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7448 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7467 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7449 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7468 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7450 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7469 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7451 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7470 - attribute \src "libresoc.v:140967.5-140967.29" - switch \initial - attribute \src "libresoc.v:140967.9-140967.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7456 $1\alu_mul0_mul_op__is_signed$next[0:0]$7459 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7464 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7461 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7460 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7462 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7463 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } - case - assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$7453 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7456 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7457 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7458 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7459 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7460 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7461 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7462 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7463 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7464 \alu_mul0_mul_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7465 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7466 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7470 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7469 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7467 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7468 1'0 - case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7465 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7454 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7466 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7455 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7467 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7460 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7468 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7461 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7469 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7462 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7470 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7463 - end - sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$7441 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7442 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7443 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7444 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7445 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7446 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7447 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7448 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7449 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7450 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7451 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7452 - end - attribute \src "libresoc.v:140999.3-141020.6" - process $proc$libresoc.v:140999$7471 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$7472 $2\data_r0__o$next[63:0]$7476 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7473 $3\data_r0__o_ok$next[0:0]$7478 - attribute \src "libresoc.v:141000.5-141000.29" - switch \initial - attribute \src "libresoc.v:141000.9-141000.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7475 $1\data_r0__o$next[63:0]$7474 } { \o_ok \alu_mul0_o } - case - assign $1\data_r0__o$next[63:0]$7474 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7475 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7477 $2\data_r0__o$next[63:0]$7476 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$7476 $1\data_r0__o$next[63:0]$7474 - assign $2\data_r0__o_ok$next[0:0]$7477 $1\data_r0__o_ok$next[0:0]$7475 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7478 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$7478 $2\data_r0__o_ok$next[0:0]$7477 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7472 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7473 - end - attribute \src "libresoc.v:141021.3-141042.6" - process $proc$libresoc.v:141021$7479 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7480 $2\data_r1__cr_a$next[3:0]$7484 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7481 $3\data_r1__cr_a_ok$next[0:0]$7486 - attribute \src "libresoc.v:141022.5-141022.29" - switch \initial - attribute \src "libresoc.v:141022.9-141022.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7483 $1\data_r1__cr_a$next[3:0]$7482 } { \cr_a_ok \alu_mul0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$7482 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7483 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7485 $2\data_r1__cr_a$next[3:0]$7484 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$7484 $1\data_r1__cr_a$next[3:0]$7482 - assign $2\data_r1__cr_a_ok$next[0:0]$7485 $1\data_r1__cr_a_ok$next[0:0]$7483 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7486 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$7486 $2\data_r1__cr_a_ok$next[0:0]$7485 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7480 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7481 - end - attribute \src "libresoc.v:141043.3-141064.6" - process $proc$libresoc.v:141043$7487 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7488 $2\data_r2__xer_ov$next[1:0]$7492 - assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7489 $3\data_r2__xer_ov_ok$next[0:0]$7494 - attribute \src "libresoc.v:141044.5-141044.29" - switch \initial - attribute \src "libresoc.v:141044.9-141044.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7491 $1\data_r2__xer_ov$next[1:0]$7490 } { \xer_ov_ok \alu_mul0_xer_ov } - case - assign $1\data_r2__xer_ov$next[1:0]$7490 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7491 \data_r2__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7493 $2\data_r2__xer_ov$next[1:0]$7492 } 3'000 - case - assign $2\data_r2__xer_ov$next[1:0]$7492 $1\data_r2__xer_ov$next[1:0]$7490 - assign $2\data_r2__xer_ov_ok$next[0:0]$7493 $1\data_r2__xer_ov_ok$next[0:0]$7491 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7494 1'0 - case - assign $3\data_r2__xer_ov_ok$next[0:0]$7494 $2\data_r2__xer_ov_ok$next[0:0]$7493 - end - sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7488 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7489 - end - attribute \src "libresoc.v:141065.3-141086.6" - process $proc$libresoc.v:141065$7495 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7496 $2\data_r3__xer_so$next[0:0]$7500 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7497 $3\data_r3__xer_so_ok$next[0:0]$7502 - attribute \src "libresoc.v:141066.5-141066.29" - switch \initial - attribute \src "libresoc.v:141066.9-141066.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7499 $1\data_r3__xer_so$next[0:0]$7498 } { \xer_so_ok \alu_mul0_xer_so } - case - assign $1\data_r3__xer_so$next[0:0]$7498 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7499 \data_r3__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7501 $2\data_r3__xer_so$next[0:0]$7500 } 2'00 - case - assign $2\data_r3__xer_so$next[0:0]$7500 $1\data_r3__xer_so$next[0:0]$7498 - assign $2\data_r3__xer_so_ok$next[0:0]$7501 $1\data_r3__xer_so_ok$next[0:0]$7499 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7502 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$7502 $2\data_r3__xer_so_ok$next[0:0]$7501 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7496 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7497 - end - attribute \src "libresoc.v:141087.3-141096.6" - process $proc$libresoc.v:141087$7503 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$7504 $1\src_r0$next[63:0]$7505 - attribute \src "libresoc.v:141088.5-141088.29" - switch \initial - attribute \src "libresoc.v:141088.9-141088.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r0$next[63:0]$7505 \src1_i - case - assign $1\src_r0$next[63:0]$7505 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$7504 - end - attribute \src "libresoc.v:141097.3-141106.6" - process $proc$libresoc.v:141097$7506 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$7507 $1\src_r1$next[63:0]$7508 - attribute \src "libresoc.v:141098.5-141098.29" - switch \initial - attribute \src "libresoc.v:141098.9-141098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r1$next[63:0]$7508 \src_or_imm - case - assign $1\src_r1$next[63:0]$7508 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$7507 - end - attribute \src "libresoc.v:141107.3-141116.6" - process $proc$libresoc.v:141107$7509 - assign { } { } - assign { } { } - assign $0\src_r2$next[0:0]$7510 $1\src_r2$next[0:0]$7511 - attribute \src "libresoc.v:141108.5-141108.29" - switch \initial - attribute \src "libresoc.v:141108.9-141108.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src_r2$next[0:0]$7511 \src3_i - case - assign $1\src_r2$next[0:0]$7511 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[0:0]$7510 - end - attribute \src "libresoc.v:141117.3-141125.6" - process $proc$libresoc.v:141117$7512 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7513 $1\alui_l_r_alui$next[0:0]$7514 - attribute \src "libresoc.v:141118.5-141118.29" - switch \initial - attribute \src "libresoc.v:141118.9-141118.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7514 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$7514 \$88 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7513 - end - attribute \src "libresoc.v:141126.3-141134.6" - process $proc$libresoc.v:141126$7515 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7516 $1\alu_l_r_alu$next[0:0]$7517 - attribute \src "libresoc.v:141127.5-141127.29" - switch \initial - attribute \src "libresoc.v:141127.9-141127.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7517 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$7517 \$90 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7516 - end - attribute \src "libresoc.v:141135.3-141144.6" - process $proc$libresoc.v:141135$7518 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:141136.5-141136.29" - switch \initial - attribute \src "libresoc.v:141136.9-141136.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$114 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:141145.3-141154.6" - process $proc$libresoc.v:141145$7519 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:141146.5-141146.29" - switch \initial - attribute \src "libresoc.v:141146.9-141146.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$116 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "libresoc.v:141155.3-141164.6" - process $proc$libresoc.v:141155$7520 - assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:141156.5-141156.29" - switch \initial - attribute \src "libresoc.v:141156.9-141156.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$118 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ov - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "libresoc.v:141165.3-141174.6" - process $proc$libresoc.v:141165$7521 - assign { } { } - assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:141166.5-141166.29" - switch \initial - attribute \src "libresoc.v:141166.9-141166.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$120 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "libresoc.v:141175.3-141183.6" - process $proc$libresoc.v:141175$7522 - assign { } { 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\src "libresoc.v:142098.18-142098.104" - wire $and$libresoc.v:142098$7595_Y - attribute \src "libresoc.v:142102.18-142102.104" - wire $and$libresoc.v:142102$7599_Y - attribute \src "libresoc.v:142092.18-142092.95" - wire width 130 $extend$libresoc.v:142092$7587_Y - attribute \src "libresoc.v:142093.18-142093.90" - wire width 130 $extend$libresoc.v:142093$7589_Y - attribute \src "libresoc.v:142103.18-142103.95" - wire width 2 $extend$libresoc.v:142103$7600_Y - attribute \src "libresoc.v:142092.18-142092.95" - wire width 130 $neg$libresoc.v:142092$7588_Y - attribute \src "libresoc.v:142097.18-142097.98" - wire $not$libresoc.v:142097$7594_Y - attribute \src "libresoc.v:142101.18-142101.98" - wire $not$libresoc.v:142101$7598_Y - attribute \src "libresoc.v:142093.18-142093.90" - wire width 130 $pos$libresoc.v:142093$7590_Y - attribute \src "libresoc.v:142103.18-142103.95" - wire width 2 $pos$libresoc.v:142103$7601_Y - attribute \src "libresoc.v:142096.18-142096.106" - wire $reduce_and$libresoc.v:142096$7593_Y - attribute \src "libresoc.v:142100.18-142100.107" - wire $reduce_and$libresoc.v:142100$7597_Y - attribute \src "libresoc.v:142095.18-142095.106" - wire $reduce_or$libresoc.v:142095$7592_Y - attribute \src "libresoc.v:142099.18-142099.107" - wire $reduce_or$libresoc.v:142099$7596_Y - attribute \src "libresoc.v:142094.18-142094.114" - wire width 130 $ternary$libresoc.v:142094$7591_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 \$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 \$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 130 \$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \$39 - attribute \src "libresoc.v:141811.7-141811.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" - wire \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" - wire width 129 \mul_o - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 2 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" - wire \mul_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 35 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire input 15 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 29 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 31 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 14 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 34 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:142098$7595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \B \$25 - connect \Y $and$libresoc.v:142098$7595_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:142102$7599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$31 - connect \B \$33 - connect \Y $and$libresoc.v:142102$7599_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:142092$7587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $extend$libresoc.v:142092$7587_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:142093$7589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $extend$libresoc.v:142093$7589_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:142103$7600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \xer_so - connect \Y $extend$libresoc.v:142103$7600_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:142092$7588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 130 - parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:142092$7587_Y - connect \Y $neg$libresoc.v:142092$7588_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:142097$7594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $not$libresoc.v:142097$7594_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:142101$7598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$34 - connect \Y $not$libresoc.v:142101$7598_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:142093$7590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 130 - parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:142093$7589_Y - connect \Y $pos$libresoc.v:142093$7590_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:142103$7601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:142103$7600_Y - connect \Y $pos$libresoc.v:142103$7601_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:142096$7593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 33 - parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:142096$7593_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:142100$7597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:142100$7597_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:142095$7592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 33 - parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:142095$7592_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:142099$7596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:142099$7596_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:142094$7591 - parameter \WIDTH 130 - connect \A \$19 - connect \B \$17 - connect \S \neg_res - connect \Y $ternary$libresoc.v:142094$7591_Y - end - attribute \src "libresoc.v:141811.7-141811.20" - process $proc$libresoc.v:141811$7609 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:142104.3-142122.6" - process $proc$libresoc.v:142104$7602 - assign { } { } - assign { } { } - assign $0\o$14[63:0]$7603 $1\o$14[63:0]$7604 - attribute \src "libresoc.v:142105.5-142105.29" - switch \initial - attribute \src "libresoc.v:142105.9-142105.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110100 - assign { } { } - assign $1\o$14[63:0]$7604 { \mul_o [63:32] \mul_o [63:32] } - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 - assign { } { } - assign $1\o$14[63:0]$7604 \mul_o [127:64] - attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\o$14[63:0]$7604 \mul_o [63:0] - case - assign $1\o$14[63:0]$7604 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o$14 $0\o$14[63:0]$7603 - end - attribute \src "libresoc.v:142123.3-142141.6" - process $proc$libresoc.v:142123$7605 - assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:142124.5-142124.29" - switch \initial - attribute \src "libresoc.v:142124.9-142124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110100 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0110011 - assign { } { } - assign $1\o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\o_ok[0:0] 1'1 - case - assign $1\o_ok[0:0] 1'0 - end - sync always - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:142142.3-142160.6" - process $proc$libresoc.v:142142$7606 - assign { } { } - assign { } { } - assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:142143.5-142143.29" - switch \initial - attribute \src "libresoc.v:142143.9-142143.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\mul_ov[0:0] $2\mul_ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" - switch \is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mul_ov[0:0] \$29 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\mul_ov[0:0] \$37 - end - case - assign $1\mul_ov[0:0] 1'0 - end - sync always - update \mul_ov $0\mul_ov[0:0] - end - attribute \src "libresoc.v:142161.3-142171.6" - process $proc$libresoc.v:142161$7607 - assign { } { } - assign { } { } - assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:142162.5-142162.29" - switch \initial - attribute \src "libresoc.v:142162.9-142162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\xer_ov[1:0] { \mul_ov \mul_ov } - case - assign $1\xer_ov[1:0] 2'00 - end - sync always - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "libresoc.v:142172.3-142182.6" - process $proc$libresoc.v:142172$7608 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:142173.5-142173.29" - switch \initial - attribute \src "libresoc.v:142173.9-142173.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0110010 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - connect \$17 $neg$libresoc.v:142092$7588_Y - connect \$19 $pos$libresoc.v:142093$7590_Y - connect \$21 $ternary$libresoc.v:142094$7591_Y - connect \$23 $reduce_or$libresoc.v:142095$7592_Y - connect \$26 $reduce_and$libresoc.v:142096$7593_Y - connect \$25 $not$libresoc.v:142097$7594_Y - connect \$29 $and$libresoc.v:142098$7595_Y - connect \$31 $reduce_or$libresoc.v:142099$7596_Y - connect \$34 $reduce_and$libresoc.v:142100$7597_Y - connect \$33 $not$libresoc.v:142101$7598_Y - connect \$37 $and$libresoc.v:142102$7599_Y - connect \$39 $pos$libresoc.v:142103$7601_Y - connect \$16 \$21 - connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \muxid$1 \muxid - connect { \xer_so_ok \xer_so$15 } \$39 - connect \mul_o \$21 [128:0] - connect \is_32bit \mul_op__is_32bit -end -attribute \src "libresoc.v:142193.1-143389.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" -attribute \generator "nMigen" -module \mul_pipe1 - attribute \src "libresoc.v:142194.7-142194.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 12 $0\mul_op__fn_unit$next[11:0]$7638 - attribute \src "libresoc.v:143131.3-143132.47" - wire width 12 $0\mul_op__fn_unit[11:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7639 - attribute \src "libresoc.v:143133.3-143134.61" - wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7640 - attribute \src "libresoc.v:143135.3-143136.57" - wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 32 $0\mul_op__insn$next[31:0]$7641 - attribute \src "libresoc.v:143151.3-143152.41" - wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7642 - attribute \src "libresoc.v:143129.3-143130.51" - wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__is_32bit$next[0:0]$7643 - attribute \src "libresoc.v:143147.3-143148.49" - wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__is_signed$next[0:0]$7644 - attribute \src "libresoc.v:143149.3-143150.51" - wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__oe__oe$next[0:0]$7645 - attribute \src "libresoc.v:143141.3-143142.45" - wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__oe__ok$next[0:0]$7646 - attribute \src "libresoc.v:143143.3-143144.45" - wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__rc__ok$next[0:0]$7647 - attribute \src "libresoc.v:143139.3-143140.45" - wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__rc__rc$next[0:0]$7648 - attribute \src "libresoc.v:143137.3-143138.45" - wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $0\mul_op__write_cr0$next[0:0]$7649 - attribute \src "libresoc.v:143145.3-143146.51" - wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:143253.3-143265.6" - wire width 2 $0\muxid$next[1:0]$7635 - attribute \src "libresoc.v:143153.3-143154.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:143341.3-143353.6" - wire $0\neg_res$next[0:0]$7678 - attribute \src "libresoc.v:143354.3-143366.6" - wire $0\neg_res32$next[0:0]$7681 - attribute \src "libresoc.v:143119.3-143120.35" - wire $0\neg_res32[0:0] - attribute \src "libresoc.v:143121.3-143122.31" - wire $0\neg_res[0:0] - attribute \src "libresoc.v:143235.3-143252.6" - wire $0\r_busy$next[0:0]$7631 - attribute \src "libresoc.v:143155.3-143156.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:143302.3-143314.6" - wire width 64 $0\ra$next[63:0]$7669 - attribute \src "libresoc.v:143127.3-143128.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:143315.3-143327.6" - wire width 64 $0\rb$next[63:0]$7672 - attribute \src "libresoc.v:143125.3-143126.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:143328.3-143340.6" - wire $0\xer_so$next[0:0]$7675 - attribute \src "libresoc.v:143123.3-143124.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 12 $1\mul_op__fn_unit$next[11:0]$7650 - attribute \src "libresoc.v:142696.14-142696.39" - wire width 12 $1\mul_op__fn_unit[11:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7651 - attribute \src "libresoc.v:142731.14-142731.59" - wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7652 - attribute \src "libresoc.v:142740.7-142740.34" - wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 32 $1\mul_op__insn$next[31:0]$7653 - attribute \src "libresoc.v:142749.14-142749.34" - wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7654 - attribute \src "libresoc.v:142832.13-142832.38" - wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__is_32bit$next[0:0]$7655 - attribute \src "libresoc.v:142989.7-142989.30" - wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__is_signed$next[0:0]$7656 - attribute \src "libresoc.v:142998.7-142998.31" - wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__oe__oe$next[0:0]$7657 - attribute \src "libresoc.v:143007.7-143007.28" - wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__oe__ok$next[0:0]$7658 - attribute \src "libresoc.v:143016.7-143016.28" - wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__rc__ok$next[0:0]$7659 - attribute \src "libresoc.v:143025.7-143025.28" - wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__rc__rc$next[0:0]$7660 - attribute \src "libresoc.v:143034.7-143034.28" - wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire $1\mul_op__write_cr0$next[0:0]$7661 - attribute \src "libresoc.v:143043.7-143043.31" - wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:143253.3-143265.6" - wire width 2 $1\muxid$next[1:0]$7636 - attribute \src "libresoc.v:143052.13-143052.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:143341.3-143353.6" - wire $1\neg_res$next[0:0]$7679 - attribute \src "libresoc.v:143354.3-143366.6" - wire $1\neg_res32$next[0:0]$7682 - attribute \src "libresoc.v:143074.7-143074.23" - wire $1\neg_res32[0:0] - attribute \src "libresoc.v:143067.7-143067.21" - wire $1\neg_res[0:0] - attribute \src "libresoc.v:143235.3-143252.6" - wire $1\r_busy$next[0:0]$7632 - attribute \src "libresoc.v:143088.7-143088.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:143302.3-143314.6" - wire width 64 $1\ra$next[63:0]$7670 - attribute \src "libresoc.v:143093.14-143093.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:143315.3-143327.6" - wire width 64 $1\rb$next[63:0]$7673 - attribute \src "libresoc.v:143102.14-143102.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:143328.3-143340.6" - wire $1\xer_so$next[0:0]$7676 - attribute \src "libresoc.v:143111.7-143111.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:143266.3-143301.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7662 - attribute \src "libresoc.v:143266.3-143301.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7663 - attribute \src "libresoc.v:143266.3-143301.6" - wire $2\mul_op__oe__oe$next[0:0]$7664 - attribute \src "libresoc.v:143266.3-143301.6" - wire $2\mul_op__oe__ok$next[0:0]$7665 - attribute \src "libresoc.v:143266.3-143301.6" - wire $2\mul_op__rc__ok$next[0:0]$7666 - attribute \src "libresoc.v:143266.3-143301.6" - wire $2\mul_op__rc__rc$next[0:0]$7667 - attribute \src "libresoc.v:143235.3-143252.6" - wire $2\r_busy$next[0:0]$7633 - attribute \src "libresoc.v:143118.18-143118.118" - wire $and$libresoc.v:143118$7610_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:142194.7-142194.15" - wire \initial - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_mul_op__fn_unit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_mul_op__imm_data__data$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__imm_data__ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_mul_op__insn$29 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_mul_op__insn_type$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_32bit$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__is_signed$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__oe$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__oe__ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__rc__rc$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$32 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul1_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul1_mul_op__fn_unit$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul1_mul_op__imm_data__data$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul1_mul_op__imm_data__ok$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn$45 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 34 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 35 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 31 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 32 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 30 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 29 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 33 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire output 20 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \neg_res$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \neg_res$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire output 21 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \neg_res32$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \neg_res32$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 23 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 22 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 17 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 37 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 18 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 38 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 39 \xer_so$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:143118$7610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$49 - connect \B \p_ready_o - connect \Y $and$libresoc.v:143118$7610_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143157.14-143190.4" - cell \input$95 \input - connect \mul_op__fn_unit \input_mul_op__fn_unit - connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 - connect \mul_op__imm_data__data \input_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 - connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 - connect \mul_op__insn \input_mul_op__insn - connect \mul_op__insn$13 \input_mul_op__insn$29 - connect \mul_op__insn_type \input_mul_op__insn_type - connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 - connect \mul_op__is_32bit \input_mul_op__is_32bit - connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 - connect \mul_op__is_signed \input_mul_op__is_signed - connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 - connect \mul_op__oe__oe \input_mul_op__oe__oe - connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 - connect \mul_op__oe__ok \input_mul_op__oe__ok - connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 - connect \mul_op__rc__ok \input_mul_op__rc__ok - connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 - connect \mul_op__rc__rc \input_mul_op__rc__rc - connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 - connect \mul_op__write_cr0 \input_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$17 - connect \ra \input_ra - connect \ra$14 \input_ra$30 - connect \rb \input_rb - connect \rb$15 \input_rb$31 - connect \xer_so \input_xer_so - connect \xer_so$16 \input_xer_so$32 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143191.8-143226.4" - cell \mul1 \mul1 - connect \mul_op__fn_unit \mul1_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 - connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 - connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 - connect \mul_op__insn \mul1_mul_op__insn - connect \mul_op__insn$13 \mul1_mul_op__insn$45 - connect \mul_op__insn_type \mul1_mul_op__insn_type - connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 - connect \mul_op__is_32bit \mul1_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 - connect \mul_op__is_signed \mul1_mul_op__is_signed - connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 - connect \mul_op__oe__oe \mul1_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 - connect \mul_op__oe__ok \mul1_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 - connect \mul_op__rc__ok \mul1_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 - connect \mul_op__rc__rc \mul1_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 - connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 - connect \muxid \mul1_muxid - connect \muxid$1 \mul1_muxid$33 - connect \neg_res \mul1_neg_res - connect \neg_res32 \mul1_neg_res32 - connect \ra \mul1_ra - connect \ra$14 \mul1_ra$46 - connect \rb \mul1_rb - connect \rb$15 \mul1_rb$47 - connect \xer_so \mul1_xer_so - connect \xer_so$16 \mul1_xer_so$48 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143227.10-143230.4" - cell \n$94 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:143231.10-143234.4" - cell \p$93 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:142194.7-142194.20" - process $proc$libresoc.v:142194$7683 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:142696.14-142696.39" - process $proc$libresoc.v:142696$7684 - assign { } { } - assign $1\mul_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \mul_op__fn_unit $1\mul_op__fn_unit[11:0] - end - attribute \src "libresoc.v:142731.14-142731.59" - process $proc$libresoc.v:142731$7685 - assign { } { } - assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:142740.7-142740.34" - process $proc$libresoc.v:142740$7686 - assign { } { } - assign $1\mul_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:142749.14-142749.34" - process $proc$libresoc.v:142749$7687 - assign { } { } - assign $1\mul_op__insn[31:0] 0 - sync always - sync init - update \mul_op__insn $1\mul_op__insn[31:0] - end - attribute \src "libresoc.v:142832.13-142832.38" - process $proc$libresoc.v:142832$7688 - assign { } { } - assign $1\mul_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \mul_op__insn_type $1\mul_op__insn_type[6:0] - end - attribute \src "libresoc.v:142989.7-142989.30" - process $proc$libresoc.v:142989$7689 - assign { } { } - assign $1\mul_op__is_32bit[0:0] 1'0 - sync always - sync init - update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] - end - attribute \src "libresoc.v:142998.7-142998.31" - process $proc$libresoc.v:142998$7690 - assign { } { } - assign $1\mul_op__is_signed[0:0] 1'0 - sync always - sync init - update \mul_op__is_signed $1\mul_op__is_signed[0:0] - end - attribute \src "libresoc.v:143007.7-143007.28" - process $proc$libresoc.v:143007$7691 - assign { } { } - assign $1\mul_op__oe__oe[0:0] 1'0 - sync always - sync init - update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] - end - attribute \src "libresoc.v:143016.7-143016.28" - process $proc$libresoc.v:143016$7692 - assign { } { } - assign $1\mul_op__oe__ok[0:0] 1'0 - sync always - sync init - update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] - end - attribute \src "libresoc.v:143025.7-143025.28" - process $proc$libresoc.v:143025$7693 - assign { } { } - assign $1\mul_op__rc__ok[0:0] 1'0 - sync always - sync init - update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] - end - attribute \src "libresoc.v:143034.7-143034.28" - process $proc$libresoc.v:143034$7694 - assign { } { } - assign $1\mul_op__rc__rc[0:0] 1'0 - sync always - sync init - update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] - end - attribute \src "libresoc.v:143043.7-143043.31" - process $proc$libresoc.v:143043$7695 - assign { } { } - assign $1\mul_op__write_cr0[0:0] 1'0 - sync always - sync init - update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] - end - attribute \src "libresoc.v:143052.13-143052.25" - process $proc$libresoc.v:143052$7696 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:143067.7-143067.21" - process $proc$libresoc.v:143067$7697 - assign { } { } - assign $1\neg_res[0:0] 1'0 - sync always - sync init - update \neg_res $1\neg_res[0:0] - end - attribute \src "libresoc.v:143074.7-143074.23" - process $proc$libresoc.v:143074$7698 - assign { } { } - assign $1\neg_res32[0:0] 1'0 - sync always - sync init - update \neg_res32 $1\neg_res32[0:0] - end - attribute \src "libresoc.v:143088.7-143088.20" - process $proc$libresoc.v:143088$7699 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:143093.14-143093.39" - process $proc$libresoc.v:143093$7700 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] - end - attribute \src "libresoc.v:143102.14-143102.39" - process $proc$libresoc.v:143102$7701 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] - end - attribute \src "libresoc.v:143111.7-143111.20" - process $proc$libresoc.v:143111$7702 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:143119.3-143120.35" - process $proc$libresoc.v:143119$7611 - assign { } { } - assign $0\neg_res32[0:0] \neg_res32$next - sync posedge \coresync_clk - update \neg_res32 $0\neg_res32[0:0] - end - attribute \src "libresoc.v:143121.3-143122.31" - process $proc$libresoc.v:143121$7612 - assign { } { } - assign $0\neg_res[0:0] \neg_res$next - sync posedge \coresync_clk - update \neg_res $0\neg_res[0:0] - end - attribute \src "libresoc.v:143123.3-143124.29" - process $proc$libresoc.v:143123$7613 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:143125.3-143126.21" - process $proc$libresoc.v:143125$7614 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] - end - attribute \src "libresoc.v:143127.3-143128.21" - process $proc$libresoc.v:143127$7615 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] - end - attribute \src "libresoc.v:143129.3-143130.51" - process $proc$libresoc.v:143129$7616 - assign { } { } - assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next - sync posedge \coresync_clk - update \mul_op__insn_type $0\mul_op__insn_type[6:0] - end - attribute \src "libresoc.v:143131.3-143132.47" - process $proc$libresoc.v:143131$7617 - assign { } { } - assign $0\mul_op__fn_unit[11:0] \mul_op__fn_unit$next - sync posedge \coresync_clk - update \mul_op__fn_unit $0\mul_op__fn_unit[11:0] - end - attribute \src "libresoc.v:143133.3-143134.61" - process $proc$libresoc.v:143133$7618 - assign { } { } - assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next - sync posedge \coresync_clk - update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:143135.3-143136.57" - process $proc$libresoc.v:143135$7619 - assign { } { } - assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:143137.3-143138.45" - process $proc$libresoc.v:143137$7620 - assign { } { } - assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next - sync posedge \coresync_clk - update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] - end - attribute \src "libresoc.v:143139.3-143140.45" - process $proc$libresoc.v:143139$7621 - assign { } { } - assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next - sync posedge \coresync_clk - update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] - end - attribute \src "libresoc.v:143141.3-143142.45" - process $proc$libresoc.v:143141$7622 - assign { } { } - assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next - sync posedge \coresync_clk - update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] - end - attribute \src "libresoc.v:143143.3-143144.45" - process $proc$libresoc.v:143143$7623 - assign { } { } - assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next - sync posedge \coresync_clk - update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] - end - attribute \src "libresoc.v:143145.3-143146.51" - process $proc$libresoc.v:143145$7624 - assign { } { } - assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next - sync posedge \coresync_clk - update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] - end - attribute \src "libresoc.v:143147.3-143148.49" - process $proc$libresoc.v:143147$7625 - assign { } { } - assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next - sync posedge \coresync_clk - update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] - end - attribute \src "libresoc.v:143149.3-143150.51" - process $proc$libresoc.v:143149$7626 - assign { } { } - assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next - sync posedge \coresync_clk - update \mul_op__is_signed $0\mul_op__is_signed[0:0] - end - attribute \src "libresoc.v:143151.3-143152.41" - process $proc$libresoc.v:143151$7627 - assign { } { } - assign $0\mul_op__insn[31:0] \mul_op__insn$next - sync posedge \coresync_clk - update \mul_op__insn $0\mul_op__insn[31:0] - end - attribute \src "libresoc.v:143153.3-143154.27" - process $proc$libresoc.v:143153$7628 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:143155.3-143156.29" - process $proc$libresoc.v:143155$7629 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:143235.3-143252.6" - process $proc$libresoc.v:143235$7630 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7631 $2\r_busy$next[0:0]$7633 - attribute \src "libresoc.v:143236.5-143236.29" - switch \initial - attribute \src "libresoc.v:143236.9-143236.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7632 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7632 1'0 - case - assign $1\r_busy$next[0:0]$7632 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7633 1'0 - case - assign $2\r_busy$next[0:0]$7633 $1\r_busy$next[0:0]$7632 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7631 - end - attribute \src "libresoc.v:143253.3-143265.6" - process $proc$libresoc.v:143253$7634 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$7635 $1\muxid$next[1:0]$7636 - attribute \src "libresoc.v:143254.5-143254.29" - switch \initial - attribute \src "libresoc.v:143254.9-143254.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$next[1:0]$7636 \muxid$52 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$next[1:0]$7636 \muxid$52 - case - assign $1\muxid$next[1:0]$7636 \muxid - end - sync always - update \muxid$next $0\muxid$next[1:0]$7635 - end - attribute \src "libresoc.v:143266.3-143301.6" - process $proc$libresoc.v:143266$7637 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__fn_unit$next[11:0]$7638 $1\mul_op__fn_unit$next[11:0]$7650 - assign { } { } - assign { } { } - assign $0\mul_op__insn$next[31:0]$7641 $1\mul_op__insn$next[31:0]$7653 - assign $0\mul_op__insn_type$next[6:0]$7642 $1\mul_op__insn_type$next[6:0]$7654 - assign $0\mul_op__is_32bit$next[0:0]$7643 $1\mul_op__is_32bit$next[0:0]$7655 - assign $0\mul_op__is_signed$next[0:0]$7644 $1\mul_op__is_signed$next[0:0]$7656 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7649 $1\mul_op__write_cr0$next[0:0]$7661 - assign $0\mul_op__imm_data__data$next[63:0]$7639 $2\mul_op__imm_data__data$next[63:0]$7662 - assign $0\mul_op__imm_data__ok$next[0:0]$7640 $2\mul_op__imm_data__ok$next[0:0]$7663 - assign $0\mul_op__oe__oe$next[0:0]$7645 $2\mul_op__oe__oe$next[0:0]$7664 - assign $0\mul_op__oe__ok$next[0:0]$7646 $2\mul_op__oe__ok$next[0:0]$7665 - assign $0\mul_op__rc__ok$next[0:0]$7647 $2\mul_op__rc__ok$next[0:0]$7666 - assign $0\mul_op__rc__rc$next[0:0]$7648 $2\mul_op__rc__rc$next[0:0]$7667 - attribute \src "libresoc.v:143267.5-143267.29" - switch \initial - attribute \src "libresoc.v:143267.9-143267.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$next[31:0]$7653 $1\mul_op__is_signed$next[0:0]$7656 $1\mul_op__is_32bit$next[0:0]$7655 $1\mul_op__write_cr0$next[0:0]$7661 $1\mul_op__oe__ok$next[0:0]$7658 $1\mul_op__oe__oe$next[0:0]$7657 $1\mul_op__rc__ok$next[0:0]$7659 $1\mul_op__rc__rc$next[0:0]$7660 $1\mul_op__imm_data__ok$next[0:0]$7652 $1\mul_op__imm_data__data$next[63:0]$7651 $1\mul_op__fn_unit$next[11:0]$7650 $1\mul_op__insn_type$next[6:0]$7654 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$next[31:0]$7653 $1\mul_op__is_signed$next[0:0]$7656 $1\mul_op__is_32bit$next[0:0]$7655 $1\mul_op__write_cr0$next[0:0]$7661 $1\mul_op__oe__ok$next[0:0]$7658 $1\mul_op__oe__oe$next[0:0]$7657 $1\mul_op__rc__ok$next[0:0]$7659 $1\mul_op__rc__rc$next[0:0]$7660 $1\mul_op__imm_data__ok$next[0:0]$7652 $1\mul_op__imm_data__data$next[63:0]$7651 $1\mul_op__fn_unit$next[11:0]$7650 $1\mul_op__insn_type$next[6:0]$7654 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } - case - assign $1\mul_op__fn_unit$next[11:0]$7650 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7651 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7652 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7653 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7654 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7655 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7656 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7657 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7658 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7659 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7660 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7661 \mul_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7662 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7663 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7667 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7666 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7664 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7665 1'0 - case - assign $2\mul_op__imm_data__data$next[63:0]$7662 $1\mul_op__imm_data__data$next[63:0]$7651 - assign $2\mul_op__imm_data__ok$next[0:0]$7663 $1\mul_op__imm_data__ok$next[0:0]$7652 - assign $2\mul_op__oe__oe$next[0:0]$7664 $1\mul_op__oe__oe$next[0:0]$7657 - assign $2\mul_op__oe__ok$next[0:0]$7665 $1\mul_op__oe__ok$next[0:0]$7658 - assign $2\mul_op__rc__ok$next[0:0]$7666 $1\mul_op__rc__ok$next[0:0]$7659 - assign $2\mul_op__rc__rc$next[0:0]$7667 $1\mul_op__rc__rc$next[0:0]$7660 - end - sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$7638 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7639 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7640 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7641 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7642 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7643 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7644 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7645 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7646 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7647 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7648 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7649 - end - attribute \src "libresoc.v:143302.3-143314.6" - process $proc$libresoc.v:143302$7668 - assign { } { } - assign { } { } - assign $0\ra$next[63:0]$7669 $1\ra$next[63:0]$7670 - attribute \src "libresoc.v:143303.5-143303.29" - switch \initial - attribute \src "libresoc.v:143303.9-143303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\ra$next[63:0]$7670 \ra$65 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\ra$next[63:0]$7670 \ra$65 - case - assign $1\ra$next[63:0]$7670 \ra - end - sync always - update \ra$next $0\ra$next[63:0]$7669 - end - attribute \src "libresoc.v:143315.3-143327.6" - process $proc$libresoc.v:143315$7671 - assign { } { } - assign { } { } - assign $0\rb$next[63:0]$7672 $1\rb$next[63:0]$7673 - attribute \src "libresoc.v:143316.5-143316.29" - switch \initial - attribute \src "libresoc.v:143316.9-143316.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\rb$next[63:0]$7673 \rb$66 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\rb$next[63:0]$7673 \rb$66 - case - assign $1\rb$next[63:0]$7673 \rb - end - sync always - update \rb$next $0\rb$next[63:0]$7672 - end - attribute \src "libresoc.v:143328.3-143340.6" - process $proc$libresoc.v:143328$7674 - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$7675 $1\xer_so$next[0:0]$7676 - attribute \src "libresoc.v:143329.5-143329.29" - switch \initial - attribute \src "libresoc.v:143329.9-143329.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$next[0:0]$7676 \xer_so$67 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\xer_so$next[0:0]$7676 \xer_so$67 - case - assign $1\xer_so$next[0:0]$7676 \xer_so - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$7675 - end - attribute \src "libresoc.v:143341.3-143353.6" - process $proc$libresoc.v:143341$7677 - assign { } { } - assign { } { } - assign $0\neg_res$next[0:0]$7678 $1\neg_res$next[0:0]$7679 - attribute \src "libresoc.v:143342.5-143342.29" - switch \initial - attribute \src "libresoc.v:143342.9-143342.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res$next[0:0]$7679 \neg_res$68 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res$next[0:0]$7679 \neg_res$68 - case - assign $1\neg_res$next[0:0]$7679 \neg_res - end - sync always - update \neg_res$next $0\neg_res$next[0:0]$7678 - end - attribute \src "libresoc.v:143354.3-143366.6" - process $proc$libresoc.v:143354$7680 - assign { } { } - assign { } { } - assign $0\neg_res32$next[0:0]$7681 $1\neg_res32$next[0:0]$7682 - attribute \src "libresoc.v:143355.5-143355.29" - switch \initial - attribute \src "libresoc.v:143355.9-143355.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res32$next[0:0]$7682 \neg_res32$69 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res32$next[0:0]$7682 \neg_res32$69 - case - assign $1\neg_res32$next[0:0]$7682 \neg_res32 - end - sync always - update \neg_res32$next $0\neg_res32$next[0:0]$7681 - end - connect \$50 $and$libresoc.v:143118$7610_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \neg_res32$69 \mul1_neg_res32 - connect \neg_res$68 \mul1_neg_res - connect \xer_so$67 \mul1_xer_so$48 - connect \rb$66 \mul1_rb$47 - connect \ra$65 \mul1_ra$46 - connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } - connect \muxid$52 \mul1_muxid$33 - connect \p_valid_i_p_ready_o \$50 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$49 \p_valid_i - connect \mul1_xer_so \input_xer_so$32 - connect \mul1_rb \input_rb$31 - connect \mul1_ra \input_ra$30 - connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } - connect \mul1_muxid \input_muxid$17 - connect \input_xer_so \xer_so$16 - connect \input_rb \rb$15 - connect \input_ra \ra$14 - connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:143393.1-144298.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" -attribute \generator "nMigen" -module \mul_pipe2 - attribute \src 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wire width 32 $0\mul_op__insn$13$next[31:0]$7749 - attribute \src "libresoc.v:144110.3-144111.49" - wire width 32 $0\mul_op__insn$13[31:0]$7734 - attribute \src "libresoc.v:143715.14-143715.39" - wire width 32 $0\mul_op__insn$13[31:0]$7796 - attribute \src "libresoc.v:144192.3-144227.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$7750 - attribute \src "libresoc.v:144088.3-144089.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$7712 - attribute \src "libresoc.v:143872.13-143872.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$7798 - attribute \src "libresoc.v:144192.3-144227.6" - wire $0\mul_op__is_32bit$11$next[0:0]$7751 - attribute \src "libresoc.v:144106.3-144107.57" - wire $0\mul_op__is_32bit$11[0:0]$7730 - attribute \src "libresoc.v:143955.7-143955.35" - wire $0\mul_op__is_32bit$11[0:0]$7800 - attribute \src "libresoc.v:144192.3-144227.6" - wire $0\mul_op__is_signed$12$next[0:0]$7752 - attribute \src "libresoc.v:144108.3-144109.59" - wire $0\mul_op__is_signed$12[0:0]$7732 - attribute \src "libresoc.v:143964.7-143964.36" - wire $0\mul_op__is_signed$12[0:0]$7802 - attribute \src "libresoc.v:144192.3-144227.6" - wire $0\mul_op__oe__oe$8$next[0:0]$7753 - attribute \src "libresoc.v:144100.3-144101.51" - wire $0\mul_op__oe__oe$8[0:0]$7724 - attribute \src "libresoc.v:143975.7-143975.32" - wire $0\mul_op__oe__oe$8[0:0]$7804 - attribute \src "libresoc.v:144192.3-144227.6" - wire $0\mul_op__oe__ok$9$next[0:0]$7754 - attribute \src "libresoc.v:144102.3-144103.51" - wire $0\mul_op__oe__ok$9[0:0]$7726 - attribute \src "libresoc.v:143984.7-143984.32" - wire $0\mul_op__oe__ok$9[0:0]$7806 - attribute \src "libresoc.v:144192.3-144227.6" - wire $0\mul_op__rc__ok$7$next[0:0]$7755 - attribute \src "libresoc.v:144098.3-144099.51" - wire $0\mul_op__rc__ok$7[0:0]$7722 - attribute \src "libresoc.v:143993.7-143993.32" - wire $0\mul_op__rc__ok$7[0:0]$7808 - attribute \src "libresoc.v:144192.3-144227.6" - wire $0\mul_op__rc__rc$6$next[0:0]$7756 - attribute \src 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$1\muxid$1$next[1:0]$7744 - attribute \src "libresoc.v:144254.3-144266.6" - wire $1\neg_res$15$next[0:0]$7784 - attribute \src "libresoc.v:144267.3-144279.6" - wire $1\neg_res32$16$next[0:0]$7787 - attribute \src "libresoc.v:144228.3-144240.6" - wire width 129 $1\o$next[128:0]$7778 - attribute \src "libresoc.v:144049.15-144049.57" - wire width 129 $1\o[128:0] - attribute \src "libresoc.v:144161.3-144178.6" - wire $1\r_busy$next[0:0]$7740 - attribute \src "libresoc.v:144063.7-144063.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:144241.3-144253.6" - wire $1\xer_so$14$next[0:0]$7781 - attribute \src "libresoc.v:144192.3-144227.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7770 - attribute \src "libresoc.v:144192.3-144227.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$7771 - attribute \src "libresoc.v:144192.3-144227.6" - wire $2\mul_op__oe__oe$8$next[0:0]$7772 - attribute \src "libresoc.v:144192.3-144227.6" - wire $2\mul_op__oe__ok$9$next[0:0]$7773 - attribute \src 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\enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul2_mul_op__insn_type$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__is_32bit$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__is_signed$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__oe__oe$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__oe__ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__rc__ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__rc__rc$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul2_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul2_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul2_muxid$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire \mul2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul2_neg_res$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire \mul2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \mul2_neg_res32$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul2_xer_so$30 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 26 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 27 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 36 \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$48 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 25 \mul_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 23 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 22 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire input 20 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire output 39 \neg_res$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \neg_res$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \neg_res$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire input 21 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire output 40 \neg_res32$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 output 37 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 17 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 38 \xer_so$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:144079$7703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$33 - connect \B \p_ready_o - connect \Y $and$libresoc.v:144079$7703_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:144116.8-144152.4" - cell \mul2 \mul2 - connect \mul_op__fn_unit \mul2_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 - connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 - connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 - connect \mul_op__insn \mul2_mul_op__insn - connect \mul_op__insn$13 \mul2_mul_op__insn$29 - connect \mul_op__insn_type \mul2_mul_op__insn_type - connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 - connect \mul_op__is_32bit \mul2_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 - connect \mul_op__is_signed \mul2_mul_op__is_signed - connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 - connect \mul_op__oe__oe \mul2_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 - connect \mul_op__oe__ok \mul2_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 - connect \mul_op__rc__ok \mul2_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 - connect \mul_op__rc__rc \mul2_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 - connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 - connect \muxid \mul2_muxid - connect \muxid$1 \mul2_muxid$17 - connect \neg_res \mul2_neg_res - connect \neg_res$15 \mul2_neg_res$31 - connect \neg_res32 \mul2_neg_res32 - connect \neg_res32$16 \mul2_neg_res32$32 - connect \o \mul2_o - connect \ra \mul2_ra - connect \rb \mul2_rb - connect \xer_so \mul2_xer_so - connect \xer_so$14 \mul2_xer_so$30 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:144153.10-144156.4" - cell \n$97 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:144157.10-144160.4" - cell \p$96 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:143394.7-143394.20" - process $proc$libresoc.v:143394$7788 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:143675.14-143675.43" - process $proc$libresoc.v:143675$7789 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7790 12'000000000000 - sync always - sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7790 - end - attribute \src "libresoc.v:143699.14-143699.63" - process $proc$libresoc.v:143699$7791 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7792 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7792 - end - attribute \src "libresoc.v:143708.7-143708.38" - process $proc$libresoc.v:143708$7793 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7794 1'0 - sync always - sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7794 - end - attribute \src "libresoc.v:143715.14-143715.39" - process $proc$libresoc.v:143715$7795 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7796 0 - sync always - sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7796 - end - attribute \src "libresoc.v:143872.13-143872.42" - process $proc$libresoc.v:143872$7797 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7798 7'0000000 - sync always - sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7798 - end - attribute \src "libresoc.v:143955.7-143955.35" - process $proc$libresoc.v:143955$7799 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7800 1'0 - sync always - sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7800 - end - attribute \src "libresoc.v:143964.7-143964.36" - process $proc$libresoc.v:143964$7801 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7802 1'0 - sync always - sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7802 - end - attribute \src "libresoc.v:143975.7-143975.32" - process $proc$libresoc.v:143975$7803 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7804 1'0 - sync always - sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7804 - end - attribute \src "libresoc.v:143984.7-143984.32" - process $proc$libresoc.v:143984$7805 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7806 1'0 - sync always - sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7806 - end - attribute \src "libresoc.v:143993.7-143993.32" - process $proc$libresoc.v:143993$7807 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7808 1'0 - sync always - sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7808 - end - attribute \src "libresoc.v:144002.7-144002.32" - process $proc$libresoc.v:144002$7809 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7810 1'0 - sync always - sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7810 - end - attribute \src "libresoc.v:144009.7-144009.36" - process $proc$libresoc.v:144009$7811 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7812 1'0 - sync always - sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7812 - end - attribute \src "libresoc.v:144018.13-144018.29" - process $proc$libresoc.v:144018$7813 - assign { } { } - assign $0\muxid$1[1:0]$7814 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7814 - end - attribute \src "libresoc.v:144033.7-144033.26" - process $proc$libresoc.v:144033$7815 - assign { } { } - assign $0\neg_res$15[0:0]$7816 1'0 - sync always - sync init - update \neg_res$15 $0\neg_res$15[0:0]$7816 - end - attribute \src "libresoc.v:144042.7-144042.28" - process $proc$libresoc.v:144042$7817 - assign { } { } - assign $0\neg_res32$16[0:0]$7818 1'0 - sync always - sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$7818 - end - attribute \src "libresoc.v:144049.15-144049.57" - process $proc$libresoc.v:144049$7819 - assign { } { } - assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[128:0] - end - attribute \src "libresoc.v:144063.7-144063.20" - process $proc$libresoc.v:144063$7820 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:144074.7-144074.25" - process $proc$libresoc.v:144074$7821 - assign { } { } - assign $0\xer_so$14[0:0]$7822 1'0 - sync always - sync init - update \xer_so$14 $0\xer_so$14[0:0]$7822 - end - attribute \src "libresoc.v:144080.3-144081.43" - process $proc$libresoc.v:144080$7704 - assign { } { } - assign $0\neg_res32$16[0:0]$7705 \neg_res32$16$next - sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$7705 - end - attribute \src "libresoc.v:144082.3-144083.39" - process $proc$libresoc.v:144082$7706 - assign { } { } - assign $0\neg_res$15[0:0]$7707 \neg_res$15$next - sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$7707 - end - attribute \src "libresoc.v:144084.3-144085.37" - process $proc$libresoc.v:144084$7708 - assign { } { } - assign $0\xer_so$14[0:0]$7709 \xer_so$14$next - sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$7709 - end - attribute \src "libresoc.v:144086.3-144087.19" - process $proc$libresoc.v:144086$7710 - assign { } { } - assign $0\o[128:0] \o$next - sync posedge \coresync_clk - update \o $0\o[128:0] - end - attribute \src "libresoc.v:144088.3-144089.57" - process $proc$libresoc.v:144088$7711 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7712 \mul_op__insn_type$2$next - sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7712 - end - attribute \src "libresoc.v:144090.3-144091.53" - process $proc$libresoc.v:144090$7713 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7714 \mul_op__fn_unit$3$next - sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7714 - end - attribute \src "libresoc.v:144092.3-144093.67" - process $proc$libresoc.v:144092$7715 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7716 \mul_op__imm_data__data$4$next - sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7716 - end - attribute \src "libresoc.v:144094.3-144095.63" - process $proc$libresoc.v:144094$7717 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7718 \mul_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7718 - end - attribute \src "libresoc.v:144096.3-144097.51" - process $proc$libresoc.v:144096$7719 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7720 \mul_op__rc__rc$6$next - sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7720 - end - attribute \src "libresoc.v:144098.3-144099.51" - process $proc$libresoc.v:144098$7721 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7722 \mul_op__rc__ok$7$next - sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7722 - end - attribute \src "libresoc.v:144100.3-144101.51" - process $proc$libresoc.v:144100$7723 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7724 \mul_op__oe__oe$8$next - sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7724 - end - attribute \src "libresoc.v:144102.3-144103.51" - process $proc$libresoc.v:144102$7725 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7726 \mul_op__oe__ok$9$next - sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7726 - end - attribute \src "libresoc.v:144104.3-144105.59" - process $proc$libresoc.v:144104$7727 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7728 \mul_op__write_cr0$10$next - sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7728 - end - attribute \src "libresoc.v:144106.3-144107.57" - process $proc$libresoc.v:144106$7729 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7730 \mul_op__is_32bit$11$next - sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7730 - end - attribute \src "libresoc.v:144108.3-144109.59" - process $proc$libresoc.v:144108$7731 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7732 \mul_op__is_signed$12$next - sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7732 - end - attribute \src "libresoc.v:144110.3-144111.49" - process $proc$libresoc.v:144110$7733 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7734 \mul_op__insn$13$next - sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7734 - end - attribute \src "libresoc.v:144112.3-144113.33" - process $proc$libresoc.v:144112$7735 - assign { } { } - assign $0\muxid$1[1:0]$7736 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7736 - end - attribute \src "libresoc.v:144114.3-144115.29" - process $proc$libresoc.v:144114$7737 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:144161.3-144178.6" - process $proc$libresoc.v:144161$7738 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7739 $2\r_busy$next[0:0]$7741 - attribute \src "libresoc.v:144162.5-144162.29" - switch \initial - attribute \src "libresoc.v:144162.9-144162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7740 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7740 1'0 - case - assign $1\r_busy$next[0:0]$7740 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7741 1'0 - case - assign $2\r_busy$next[0:0]$7741 $1\r_busy$next[0:0]$7740 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7739 - end - attribute \src "libresoc.v:144179.3-144191.6" - process $proc$libresoc.v:144179$7742 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7743 $1\muxid$1$next[1:0]$7744 - attribute \src "libresoc.v:144180.5-144180.29" - switch \initial - attribute \src "libresoc.v:144180.9-144180.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7744 \muxid$36 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7744 \muxid$36 - case - assign $1\muxid$1$next[1:0]$7744 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7743 - end - attribute \src "libresoc.v:144192.3-144227.6" - process $proc$libresoc.v:144192$7745 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7746 $1\mul_op__fn_unit$3$next[11:0]$7758 - assign { } { } - assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7749 $1\mul_op__insn$13$next[31:0]$7761 - assign $0\mul_op__insn_type$2$next[6:0]$7750 $1\mul_op__insn_type$2$next[6:0]$7762 - assign $0\mul_op__is_32bit$11$next[0:0]$7751 $1\mul_op__is_32bit$11$next[0:0]$7763 - assign $0\mul_op__is_signed$12$next[0:0]$7752 $1\mul_op__is_signed$12$next[0:0]$7764 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7757 $1\mul_op__write_cr0$10$next[0:0]$7769 - assign $0\mul_op__imm_data__data$4$next[63:0]$7747 $2\mul_op__imm_data__data$4$next[63:0]$7770 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7748 $2\mul_op__imm_data__ok$5$next[0:0]$7771 - assign $0\mul_op__oe__oe$8$next[0:0]$7753 $2\mul_op__oe__oe$8$next[0:0]$7772 - assign $0\mul_op__oe__ok$9$next[0:0]$7754 $2\mul_op__oe__ok$9$next[0:0]$7773 - assign $0\mul_op__rc__ok$7$next[0:0]$7755 $2\mul_op__rc__ok$7$next[0:0]$7774 - assign $0\mul_op__rc__rc$6$next[0:0]$7756 $2\mul_op__rc__rc$6$next[0:0]$7775 - attribute \src "libresoc.v:144193.5-144193.29" - switch \initial - attribute \src "libresoc.v:144193.9-144193.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7761 $1\mul_op__is_signed$12$next[0:0]$7764 $1\mul_op__is_32bit$11$next[0:0]$7763 $1\mul_op__write_cr0$10$next[0:0]$7769 $1\mul_op__oe__ok$9$next[0:0]$7766 $1\mul_op__oe__oe$8$next[0:0]$7765 $1\mul_op__rc__ok$7$next[0:0]$7767 $1\mul_op__rc__rc$6$next[0:0]$7768 $1\mul_op__imm_data__ok$5$next[0:0]$7760 $1\mul_op__imm_data__data$4$next[63:0]$7759 $1\mul_op__fn_unit$3$next[11:0]$7758 $1\mul_op__insn_type$2$next[6:0]$7762 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7761 $1\mul_op__is_signed$12$next[0:0]$7764 $1\mul_op__is_32bit$11$next[0:0]$7763 $1\mul_op__write_cr0$10$next[0:0]$7769 $1\mul_op__oe__ok$9$next[0:0]$7766 $1\mul_op__oe__oe$8$next[0:0]$7765 $1\mul_op__rc__ok$7$next[0:0]$7767 $1\mul_op__rc__rc$6$next[0:0]$7768 $1\mul_op__imm_data__ok$5$next[0:0]$7760 $1\mul_op__imm_data__data$4$next[63:0]$7759 $1\mul_op__fn_unit$3$next[11:0]$7758 $1\mul_op__insn_type$2$next[6:0]$7762 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } - case - assign $1\mul_op__fn_unit$3$next[11:0]$7758 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7759 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7760 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7761 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7762 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7763 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7764 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7765 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7766 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7767 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7768 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7769 \mul_op__write_cr0$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7770 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7771 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7775 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7774 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7772 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7773 1'0 - case - assign $2\mul_op__imm_data__data$4$next[63:0]$7770 $1\mul_op__imm_data__data$4$next[63:0]$7759 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7771 $1\mul_op__imm_data__ok$5$next[0:0]$7760 - assign $2\mul_op__oe__oe$8$next[0:0]$7772 $1\mul_op__oe__oe$8$next[0:0]$7765 - assign $2\mul_op__oe__ok$9$next[0:0]$7773 $1\mul_op__oe__ok$9$next[0:0]$7766 - assign $2\mul_op__rc__ok$7$next[0:0]$7774 $1\mul_op__rc__ok$7$next[0:0]$7767 - assign $2\mul_op__rc__rc$6$next[0:0]$7775 $1\mul_op__rc__rc$6$next[0:0]$7768 - end - sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7746 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7747 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7748 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7749 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7750 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7751 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7752 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7753 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7754 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7755 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7756 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7757 - end - attribute \src "libresoc.v:144228.3-144240.6" - process $proc$libresoc.v:144228$7776 - assign { } { } - assign { } { } - assign $0\o$next[128:0]$7777 $1\o$next[128:0]$7778 - attribute \src "libresoc.v:144229.5-144229.29" - switch \initial - attribute \src "libresoc.v:144229.9-144229.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\o$next[128:0]$7778 \o$49 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\o$next[128:0]$7778 \o$49 - case - assign $1\o$next[128:0]$7778 \o - end - sync always - update \o$next $0\o$next[128:0]$7777 - end - attribute \src "libresoc.v:144241.3-144253.6" - process $proc$libresoc.v:144241$7779 - assign { } { } - assign { } { } - assign $0\xer_so$14$next[0:0]$7780 $1\xer_so$14$next[0:0]$7781 - attribute \src "libresoc.v:144242.5-144242.29" - switch \initial - attribute \src "libresoc.v:144242.9-144242.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\xer_so$14$next[0:0]$7781 \xer_so$50 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\xer_so$14$next[0:0]$7781 \xer_so$50 - case - assign $1\xer_so$14$next[0:0]$7781 \xer_so$14 - end - sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$7780 - end - attribute \src "libresoc.v:144254.3-144266.6" - process $proc$libresoc.v:144254$7782 - assign { } { } - assign { } { } - assign $0\neg_res$15$next[0:0]$7783 $1\neg_res$15$next[0:0]$7784 - attribute \src "libresoc.v:144255.5-144255.29" - switch \initial - attribute \src "libresoc.v:144255.9-144255.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res$15$next[0:0]$7784 \neg_res$51 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res$15$next[0:0]$7784 \neg_res$51 - case - assign $1\neg_res$15$next[0:0]$7784 \neg_res$15 - end - sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$7783 - end - attribute \src "libresoc.v:144267.3-144279.6" - process $proc$libresoc.v:144267$7785 - assign { } { } - assign { } { } - assign $0\neg_res32$16$next[0:0]$7786 $1\neg_res32$16$next[0:0]$7787 - attribute \src "libresoc.v:144268.5-144268.29" - switch \initial - attribute \src "libresoc.v:144268.9-144268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\neg_res32$16$next[0:0]$7787 \neg_res32$52 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\neg_res32$16$next[0:0]$7787 \neg_res32$52 - case - assign $1\neg_res32$16$next[0:0]$7787 \neg_res32$16 - end - sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7786 - end - connect \$34 $and$libresoc.v:144079$7703_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \neg_res32$52 \mul2_neg_res32$32 - connect \neg_res$51 \mul2_neg_res$31 - connect \xer_so$50 \mul2_xer_so$30 - connect \o$49 \mul2_o - connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } - connect \muxid$36 \mul2_muxid$17 - connect \p_valid_i_p_ready_o \$34 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$33 \p_valid_i - connect \mul2_neg_res32 \neg_res32 - connect \mul2_neg_res \neg_res - connect \mul2_xer_so \xer_so - connect \mul2_rb \rb - connect \mul2_ra \ra - connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul2_muxid \muxid -end -attribute \src "libresoc.v:144302.1-145577.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" -attribute \generator "nMigen" -module \mul_pipe3 - attribute \src "libresoc.v:145495.3-145513.6" - wire width 4 $0\cr_a$next[3:0]$7906 - attribute \src "libresoc.v:145287.3-145288.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:145495.3-145513.6" - wire $0\cr_a_ok$next[0:0]$7907 - attribute \src "libresoc.v:145289.3-145290.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:144303.7-144303.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:145440.3-145475.6" - wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7869 - attribute \src "libresoc.v:145297.3-145298.53" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7837 - attribute \src "libresoc.v:144604.14-144604.43" - wire width 12 $0\mul_op__fn_unit$3[11:0]$7927 - attribute \src "libresoc.v:145440.3-145475.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7870 - attribute \src "libresoc.v:145299.3-145300.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7839 - attribute \src "libresoc.v:144626.14-144626.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$7929 - attribute \src "libresoc.v:145440.3-145475.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$7871 - attribute \src "libresoc.v:145301.3-145302.63" - wire $0\mul_op__imm_data__ok$5[0:0]$7841 - attribute \src "libresoc.v:144635.7-144635.38" - wire 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__rc__rc$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul3_mul_op__write_cr0$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul3_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul3_muxid$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire \mul3_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \mul3_o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul3_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \mul3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul3_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \mul3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul3_xer_so$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \mul3_xer_so_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 25 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \mul_op__fn_unit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__imm_data__ok$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 35 \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$70 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute 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attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__rc__rc$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \mul_op__write_cr0$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 22 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 21 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire input 19 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire input 20 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire \neg_res32$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 36 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 37 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_mul_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_mul_op__fn_unit$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_mul_op__imm_data__data$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__imm_data__ok$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_mul_op__insn$43 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_mul_op__insn_type$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_32bit$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__is_signed$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__oe$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__oe__ok$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__ok$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__rc__rc$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_mul_op__write_cr0$40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 40 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 41 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 18 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 42 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 43 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:145278$7823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$55 - connect \B \p_ready_o - connect \Y $and$libresoc.v:145278$7823_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:145323.8-145359.4" - cell \mul3 \mul3 - connect \mul_op__fn_unit \mul3_mul_op__fn_unit - connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 - connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 - connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 - connect \mul_op__insn \mul3_mul_op__insn - connect \mul_op__insn$13 \mul3_mul_op__insn$28 - connect \mul_op__insn_type \mul3_mul_op__insn_type - connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 - connect \mul_op__is_32bit \mul3_mul_op__is_32bit - connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 - connect \mul_op__is_signed \mul3_mul_op__is_signed - connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 - connect \mul_op__oe__oe \mul3_mul_op__oe__oe - connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 - connect \mul_op__oe__ok \mul3_mul_op__oe__ok - connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 - connect \mul_op__rc__ok \mul3_mul_op__rc__ok - connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 - connect \mul_op__rc__rc \mul3_mul_op__rc__rc - connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 - connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 - connect \muxid \mul3_muxid - connect \muxid$1 \mul3_muxid$16 - connect \neg_res \mul3_neg_res - connect \o \mul3_o - connect \o$14 \mul3_o$29 - connect \o_ok \mul3_o_ok - connect \xer_ov \mul3_xer_ov - connect \xer_ov_ok \mul3_xer_ov_ok - connect \xer_so \mul3_xer_so - connect \xer_so$15 \mul3_xer_so$30 - connect \xer_so_ok \mul3_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:145360.10-145363.4" - cell \n$99 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:145364.16-145404.4" - cell \output$100 \output - connect \cr_a \output_cr_a - connect \cr_a$16 \output_cr_a$46 - connect \cr_a_ok \output_cr_a_ok - connect \mul_op__fn_unit \output_mul_op__fn_unit - connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 - connect \mul_op__imm_data__data \output_mul_op__imm_data__data - connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 - connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok - connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 - connect \mul_op__insn \output_mul_op__insn - connect \mul_op__insn$13 \output_mul_op__insn$43 - connect \mul_op__insn_type \output_mul_op__insn_type - connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 - connect \mul_op__is_32bit \output_mul_op__is_32bit - connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 - connect \mul_op__is_signed \output_mul_op__is_signed - connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 - connect \mul_op__oe__oe \output_mul_op__oe__oe - connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 - connect \mul_op__oe__ok \output_mul_op__oe__ok - connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 - connect \mul_op__rc__ok \output_mul_op__rc__ok - connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 - connect \mul_op__rc__rc \output_mul_op__rc__rc - connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 - connect \mul_op__write_cr0 \output_mul_op__write_cr0 - connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$31 - connect \o \output_o - connect \o$14 \output_o$44 - connect \o_ok \output_o_ok - connect \o_ok$15 \output_o_ok$45 - connect \xer_ov \output_xer_ov - connect \xer_ov$17 \output_xer_ov$47 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$18 \output_xer_so$48 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:145405.10-145408.4" - cell \p$98 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:144303.7-144303.20" - process $proc$libresoc.v:144303$7923 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:144312.13-144312.24" - process $proc$libresoc.v:144312$7924 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:144321.7-144321.21" - process $proc$libresoc.v:144321$7925 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:144604.14-144604.43" - process $proc$libresoc.v:144604$7926 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7927 12'000000000000 - sync always - sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7927 - end - attribute \src "libresoc.v:144626.14-144626.63" - process $proc$libresoc.v:144626$7928 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7929 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7929 - end - attribute \src "libresoc.v:144635.7-144635.38" - process $proc$libresoc.v:144635$7930 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7931 1'0 - sync always - sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7931 - end - attribute \src "libresoc.v:144644.14-144644.39" - process $proc$libresoc.v:144644$7932 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7933 0 - sync always - sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7933 - end - attribute \src "libresoc.v:144801.13-144801.42" - process $proc$libresoc.v:144801$7934 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7935 7'0000000 - sync always - sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7935 - end - attribute \src "libresoc.v:144884.7-144884.35" - process $proc$libresoc.v:144884$7936 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7937 1'0 - sync always - sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7937 - end - attribute \src "libresoc.v:144893.7-144893.36" - process $proc$libresoc.v:144893$7938 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7939 1'0 - sync always - sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7939 - end - attribute \src "libresoc.v:144904.7-144904.32" - process $proc$libresoc.v:144904$7940 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7941 1'0 - sync always - sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7941 - end - attribute \src "libresoc.v:144913.7-144913.32" - process $proc$libresoc.v:144913$7942 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7943 1'0 - sync always - sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7943 - end - attribute \src "libresoc.v:144922.7-144922.32" - process $proc$libresoc.v:144922$7944 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7945 1'0 - sync always - sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7945 - end - attribute \src "libresoc.v:144929.7-144929.32" - process $proc$libresoc.v:144929$7946 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7947 1'0 - sync always - sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7947 - end - attribute \src "libresoc.v:144938.7-144938.36" - process $proc$libresoc.v:144938$7948 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7949 1'0 - sync always - sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7949 - end - attribute \src "libresoc.v:144947.13-144947.29" - process $proc$libresoc.v:144947$7950 - assign { } { } - assign $0\muxid$1[1:0]$7951 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$7951 - end - attribute \src "libresoc.v:144968.14-144968.43" - process $proc$libresoc.v:144968$7952 - assign { } { } - assign $0\o$14[63:0]$7953 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$14 $0\o$14[63:0]$7953 - end - attribute \src "libresoc.v:144975.7-144975.18" - process $proc$libresoc.v:144975$7954 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:145241.7-145241.20" - process $proc$libresoc.v:145241$7955 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:145246.13-145246.26" - process $proc$libresoc.v:145246$7956 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "libresoc.v:145253.7-145253.23" - process $proc$libresoc.v:145253$7957 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:145264.7-145264.25" - process $proc$libresoc.v:145264$7958 - assign { } { } - assign $0\xer_so$15[0:0]$7959 1'0 - sync always - sync init - update \xer_so$15 $0\xer_so$15[0:0]$7959 - end - attribute \src "libresoc.v:145271.7-145271.23" - process $proc$libresoc.v:145271$7960 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:145279.3-145280.37" - process $proc$libresoc.v:145279$7824 - assign { } { } - assign $0\xer_so$15[0:0]$7825 \xer_so$15$next - sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$7825 - end - attribute \src "libresoc.v:145281.3-145282.35" - process $proc$libresoc.v:145281$7826 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:145283.3-145284.29" - process $proc$libresoc.v:145283$7827 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "libresoc.v:145285.3-145286.35" - process $proc$libresoc.v:145285$7828 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:145287.3-145288.25" - process $proc$libresoc.v:145287$7829 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:145289.3-145290.31" - process $proc$libresoc.v:145289$7830 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:145291.3-145292.27" - process $proc$libresoc.v:145291$7831 - assign { } { } - assign $0\o$14[63:0]$7832 \o$14$next - sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$7832 - end - attribute \src "libresoc.v:145293.3-145294.25" - process $proc$libresoc.v:145293$7833 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:145295.3-145296.57" - process $proc$libresoc.v:145295$7834 - assign { } { } - assign $0\mul_op__insn_type$2[6:0]$7835 \mul_op__insn_type$2$next - sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7835 - end - attribute \src "libresoc.v:145297.3-145298.53" - process $proc$libresoc.v:145297$7836 - assign { } { } - assign $0\mul_op__fn_unit$3[11:0]$7837 \mul_op__fn_unit$3$next - sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7837 - end - attribute \src "libresoc.v:145299.3-145300.67" - process $proc$libresoc.v:145299$7838 - assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$7839 \mul_op__imm_data__data$4$next - sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7839 - end - attribute \src "libresoc.v:145301.3-145302.63" - process $proc$libresoc.v:145301$7840 - assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$7841 \mul_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7841 - end - attribute \src "libresoc.v:145303.3-145304.51" - process $proc$libresoc.v:145303$7842 - assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$7843 \mul_op__rc__rc$6$next - sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7843 - end - attribute \src "libresoc.v:145305.3-145306.51" - process $proc$libresoc.v:145305$7844 - assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$7845 \mul_op__rc__ok$7$next - sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7845 - end - attribute \src "libresoc.v:145307.3-145308.51" - process $proc$libresoc.v:145307$7846 - assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$7847 \mul_op__oe__oe$8$next - sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7847 - end - attribute \src "libresoc.v:145309.3-145310.51" - process $proc$libresoc.v:145309$7848 - assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$7849 \mul_op__oe__ok$9$next - sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7849 - end - attribute \src "libresoc.v:145311.3-145312.59" - process $proc$libresoc.v:145311$7850 - assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$7851 \mul_op__write_cr0$10$next - sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7851 - end - attribute \src "libresoc.v:145313.3-145314.57" - process $proc$libresoc.v:145313$7852 - assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$7853 \mul_op__is_32bit$11$next - sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7853 - end - attribute \src "libresoc.v:145315.3-145316.59" - process $proc$libresoc.v:145315$7854 - assign { } { } - assign $0\mul_op__is_signed$12[0:0]$7855 \mul_op__is_signed$12$next - sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7855 - end - attribute \src "libresoc.v:145317.3-145318.49" - process $proc$libresoc.v:145317$7856 - assign { } { } - assign $0\mul_op__insn$13[31:0]$7857 \mul_op__insn$13$next - sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7857 - end - attribute \src "libresoc.v:145319.3-145320.33" - process $proc$libresoc.v:145319$7858 - assign { } { } - assign $0\muxid$1[1:0]$7859 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7859 - end - attribute \src "libresoc.v:145321.3-145322.29" - process $proc$libresoc.v:145321$7860 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:145409.3-145426.6" - process $proc$libresoc.v:145409$7861 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$7862 $2\r_busy$next[0:0]$7864 - attribute \src "libresoc.v:145410.5-145410.29" - switch \initial - attribute \src "libresoc.v:145410.9-145410.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$7863 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\r_busy$next[0:0]$7863 1'0 - case - assign $1\r_busy$next[0:0]$7863 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r_busy$next[0:0]$7864 1'0 - case - assign $2\r_busy$next[0:0]$7864 $1\r_busy$next[0:0]$7863 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$7862 - end - attribute \src "libresoc.v:145427.3-145439.6" - process $proc$libresoc.v:145427$7865 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$7866 $1\muxid$1$next[1:0]$7867 - attribute \src "libresoc.v:145428.5-145428.29" - switch \initial - attribute \src "libresoc.v:145428.9-145428.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\muxid$1$next[1:0]$7867 \muxid$58 - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign $1\muxid$1$next[1:0]$7867 \muxid$58 - case - assign $1\muxid$1$next[1:0]$7867 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7866 - end - attribute \src "libresoc.v:145440.3-145475.6" - process $proc$libresoc.v:145440$7868 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__fn_unit$3$next[11:0]$7869 $1\mul_op__fn_unit$3$next[11:0]$7881 - assign { } { } - assign { } { } - assign $0\mul_op__insn$13$next[31:0]$7872 $1\mul_op__insn$13$next[31:0]$7884 - assign $0\mul_op__insn_type$2$next[6:0]$7873 $1\mul_op__insn_type$2$next[6:0]$7885 - assign $0\mul_op__is_32bit$11$next[0:0]$7874 $1\mul_op__is_32bit$11$next[0:0]$7886 - assign $0\mul_op__is_signed$12$next[0:0]$7875 $1\mul_op__is_signed$12$next[0:0]$7887 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$7880 $1\mul_op__write_cr0$10$next[0:0]$7892 - assign $0\mul_op__imm_data__data$4$next[63:0]$7870 $2\mul_op__imm_data__data$4$next[63:0]$7893 - assign $0\mul_op__imm_data__ok$5$next[0:0]$7871 $2\mul_op__imm_data__ok$5$next[0:0]$7894 - assign $0\mul_op__oe__oe$8$next[0:0]$7876 $2\mul_op__oe__oe$8$next[0:0]$7895 - assign $0\mul_op__oe__ok$9$next[0:0]$7877 $2\mul_op__oe__ok$9$next[0:0]$7896 - assign $0\mul_op__rc__ok$7$next[0:0]$7878 $2\mul_op__rc__ok$7$next[0:0]$7897 - assign $0\mul_op__rc__rc$6$next[0:0]$7879 $2\mul_op__rc__rc$6$next[0:0]$7898 - attribute \src "libresoc.v:145441.5-145441.29" - switch \initial - attribute \src "libresoc.v:145441.9-145441.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7884 $1\mul_op__is_signed$12$next[0:0]$7887 $1\mul_op__is_32bit$11$next[0:0]$7886 $1\mul_op__write_cr0$10$next[0:0]$7892 $1\mul_op__oe__ok$9$next[0:0]$7889 $1\mul_op__oe__oe$8$next[0:0]$7888 $1\mul_op__rc__ok$7$next[0:0]$7890 $1\mul_op__rc__rc$6$next[0:0]$7891 $1\mul_op__imm_data__ok$5$next[0:0]$7883 $1\mul_op__imm_data__data$4$next[63:0]$7882 $1\mul_op__fn_unit$3$next[11:0]$7881 $1\mul_op__insn_type$2$next[6:0]$7885 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$7884 $1\mul_op__is_signed$12$next[0:0]$7887 $1\mul_op__is_32bit$11$next[0:0]$7886 $1\mul_op__write_cr0$10$next[0:0]$7892 $1\mul_op__oe__ok$9$next[0:0]$7889 $1\mul_op__oe__oe$8$next[0:0]$7888 $1\mul_op__rc__ok$7$next[0:0]$7890 $1\mul_op__rc__rc$6$next[0:0]$7891 $1\mul_op__imm_data__ok$5$next[0:0]$7883 $1\mul_op__imm_data__data$4$next[63:0]$7882 $1\mul_op__fn_unit$3$next[11:0]$7881 $1\mul_op__insn_type$2$next[6:0]$7885 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } - case - assign $1\mul_op__fn_unit$3$next[11:0]$7881 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$7882 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$7883 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$7884 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$7885 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$7886 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$7887 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$7888 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$7889 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$7890 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$7891 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$7892 \mul_op__write_cr0$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$7893 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7894 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$7898 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$7897 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$7895 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$7896 1'0 - case - assign $2\mul_op__imm_data__data$4$next[63:0]$7893 $1\mul_op__imm_data__data$4$next[63:0]$7882 - assign $2\mul_op__imm_data__ok$5$next[0:0]$7894 $1\mul_op__imm_data__ok$5$next[0:0]$7883 - assign $2\mul_op__oe__oe$8$next[0:0]$7895 $1\mul_op__oe__oe$8$next[0:0]$7888 - assign $2\mul_op__oe__ok$9$next[0:0]$7896 $1\mul_op__oe__ok$9$next[0:0]$7889 - assign $2\mul_op__rc__ok$7$next[0:0]$7897 $1\mul_op__rc__ok$7$next[0:0]$7890 - assign $2\mul_op__rc__rc$6$next[0:0]$7898 $1\mul_op__rc__rc$6$next[0:0]$7891 - end - sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7869 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7870 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7871 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7872 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7873 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7874 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7875 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7876 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7877 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7878 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7879 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7880 - end - attribute \src "libresoc.v:145476.3-145494.6" - process $proc$libresoc.v:145476$7899 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$14$next[63:0]$7901 $1\o$14$next[63:0]$7903 - assign $0\o_ok$next[0:0]$7900 $2\o_ok$next[0:0]$7904 - attribute \src "libresoc.v:145477.5-145477.29" - switch \initial - attribute \src "libresoc.v:145477.9-145477.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7902 $1\o$14$next[63:0]$7903 } { \o_ok$72 \o$71 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$7902 $1\o$14$next[63:0]$7903 } { \o_ok$72 \o$71 } - case - assign $1\o_ok$next[0:0]$7902 \o_ok - assign $1\o$14$next[63:0]$7903 \o$14 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$7904 1'0 - case - assign $2\o_ok$next[0:0]$7904 $1\o_ok$next[0:0]$7902 - end - sync always - update \o_ok$next $0\o_ok$next[0:0]$7900 - update \o$14$next $0\o$14$next[63:0]$7901 - end - attribute \src "libresoc.v:145495.3-145513.6" - process $proc$libresoc.v:145495$7905 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$7906 $1\cr_a$next[3:0]$7908 - assign { } { } - assign $0\cr_a_ok$next[0:0]$7907 $2\cr_a_ok$next[0:0]$7910 - attribute \src "libresoc.v:145496.5-145496.29" - switch \initial - attribute \src "libresoc.v:145496.9-145496.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$7909 $1\cr_a$next[3:0]$7908 } { \cr_a_ok$74 \cr_a$73 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$7909 $1\cr_a$next[3:0]$7908 } { \cr_a_ok$74 \cr_a$73 } - case - assign $1\cr_a$next[3:0]$7908 \cr_a - assign $1\cr_a_ok$next[0:0]$7909 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cr_a_ok$next[0:0]$7910 1'0 - case - assign $2\cr_a_ok$next[0:0]$7910 $1\cr_a_ok$next[0:0]$7909 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$7906 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7907 - end - attribute \src "libresoc.v:145514.3-145532.6" - process $proc$libresoc.v:145514$7911 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$next[1:0]$7912 $1\xer_ov$next[1:0]$7914 - assign { } { } - assign $0\xer_ov_ok$next[0:0]$7913 $2\xer_ov_ok$next[0:0]$7916 - attribute \src "libresoc.v:145515.5-145515.29" - switch \initial - attribute \src "libresoc.v:145515.9-145515.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7915 $1\xer_ov$next[1:0]$7914 } { \xer_ov_ok$76 \xer_ov$75 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$7915 $1\xer_ov$next[1:0]$7914 } { \xer_ov_ok$76 \xer_ov$75 } - case - assign $1\xer_ov$next[1:0]$7914 \xer_ov - assign $1\xer_ov_ok$next[0:0]$7915 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_ov_ok$next[0:0]$7916 1'0 - case - assign $2\xer_ov_ok$next[0:0]$7916 $1\xer_ov_ok$next[0:0]$7915 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$7912 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7913 - end - attribute \src "libresoc.v:145533.3-145551.6" - process $proc$libresoc.v:145533$7917 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$15$next[0:0]$7919 $1\xer_so$15$next[0:0]$7921 - assign $0\xer_so_ok$next[0:0]$7918 $2\xer_so_ok$next[0:0]$7922 - attribute \src "libresoc.v:145534.5-145534.29" - switch \initial - attribute \src "libresoc.v:145534.9-145534.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$7920 $1\xer_so$15$next[0:0]$7921 } { \xer_so_ok$78 \xer_so$77 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$7920 $1\xer_so$15$next[0:0]$7921 } { \xer_so_ok$78 \xer_so$77 } - case - assign $1\xer_so_ok$next[0:0]$7920 \xer_so_ok - assign $1\xer_so$15$next[0:0]$7921 \xer_so$15 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so_ok$next[0:0]$7922 1'0 - case - assign $2\xer_so_ok$next[0:0]$7922 $1\xer_so_ok$next[0:0]$7920 - end - sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7918 - update \xer_so$15$next $0\xer_so$15$next[0:0]$7919 - end - connect \$56 $and$libresoc.v:145278$7823_Y - connect \cr_a$51 4'0000 - connect \cr_a_ok$52 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } - connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } - connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } - connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } - connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } - connect \muxid$58 \output_muxid$31 - connect \p_valid_i_p_ready_o \$56 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$55 \p_valid_i - connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } - connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } - connect { \cr_a_ok$50 \output_cr_a } 5'00000 - connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } - connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } - connect \output_muxid \mul3_muxid$16 - connect \neg_res32$49 \neg_res32 - connect \mul3_neg_res \neg_res - connect \mul3_xer_so \xer_so - connect \mul3_o \o - connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } - connect \mul3_muxid \muxid -end -attribute \src "libresoc.v:145581.1-145592.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" -attribute \generator "nMigen" -module \n - attribute \src "libresoc.v:145590.17-145590.111" - wire $and$libresoc.v:145590$7961_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145590$7961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145590$7961_Y - end - connect \$1 $and$libresoc.v:145590$7961_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145596.1-145607.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" -attribute \generator "nMigen" -module \n$109 - attribute \src "libresoc.v:145605.17-145605.111" - wire $and$libresoc.v:145605$7962_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145605$7962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145605$7962_Y - end - connect \$1 $and$libresoc.v:145605$7962_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145611.1-145622.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" -attribute \generator "nMigen" -module \n$112 - attribute \src "libresoc.v:145620.17-145620.111" - wire $and$libresoc.v:145620$7963_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145620$7963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145620$7963_Y - end - connect \$1 $and$libresoc.v:145620$7963_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145626.1-145637.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" -attribute \generator "nMigen" -module \n$117 - attribute \src "libresoc.v:145635.17-145635.111" - wire $and$libresoc.v:145635$7964_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145635$7964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145635$7964_Y - end - connect \$1 $and$libresoc.v:145635$7964_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145641.1-145652.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" -attribute \generator "nMigen" -module \n$18 - attribute \src "libresoc.v:145650.17-145650.111" - wire $and$libresoc.v:145650$7965_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145650$7965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145650$7965_Y - end - connect \$1 $and$libresoc.v:145650$7965_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145656.1-145667.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" -attribute \generator "nMigen" -module \n$2 - attribute \src "libresoc.v:145665.17-145665.111" - wire $and$libresoc.v:145665$7966_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145665$7966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145665$7966_Y - end - connect \$1 $and$libresoc.v:145665$7966_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145671.1-145682.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" -attribute \generator "nMigen" -module \n$21 - attribute \src "libresoc.v:145680.17-145680.111" - wire $and$libresoc.v:145680$7967_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145680$7967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145680$7967_Y - end - connect \$1 $and$libresoc.v:145680$7967_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145686.1-145697.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" -attribute \generator "nMigen" -module \n$31 - attribute \src "libresoc.v:145695.17-145695.111" - wire $and$libresoc.v:145695$7968_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145695$7968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145695$7968_Y - end - connect \$1 $and$libresoc.v:145695$7968_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145701.1-145712.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" -attribute \generator "nMigen" -module \n$34 - attribute \src "libresoc.v:145710.17-145710.111" - wire $and$libresoc.v:145710$7969_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145710$7969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145710$7969_Y - end - connect \$1 $and$libresoc.v:145710$7969_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145716.1-145727.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" -attribute \generator "nMigen" -module \n$37 - attribute \src "libresoc.v:145725.17-145725.111" - wire $and$libresoc.v:145725$7970_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145725$7970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145725$7970_Y - end - connect \$1 $and$libresoc.v:145725$7970_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145731.1-145742.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" -attribute \generator "nMigen" -module \n$4 - attribute \src "libresoc.v:145740.17-145740.111" - wire $and$libresoc.v:145740$7971_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145740$7971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145740$7971_Y - end - connect \$1 $and$libresoc.v:145740$7971_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145746.1-145757.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" -attribute \generator "nMigen" -module \n$47 - attribute \src "libresoc.v:145755.17-145755.111" - wire $and$libresoc.v:145755$7972_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145755$7972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145755$7972_Y - end - connect \$1 $and$libresoc.v:145755$7972_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145761.1-145772.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" -attribute \generator "nMigen" -module \n$49 - attribute \src "libresoc.v:145770.17-145770.111" - wire $and$libresoc.v:145770$7973_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145770$7973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145770$7973_Y - end - connect \$1 $and$libresoc.v:145770$7973_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145776.1-145787.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" -attribute \generator "nMigen" -module \n$53 - attribute \src "libresoc.v:145785.17-145785.111" - wire $and$libresoc.v:145785$7974_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire input 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $and$libresoc.v:145785$7974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:145785$7974_Y - end - connect \$1 $and$libresoc.v:145785$7974_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:145791.1-145802.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" -attribute \generator "nMigen" -module \n$6 - attribute \src "libresoc.v:145800.17-145800.111" - wire $and$libresoc.v:145800$7975_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire \$1 - attribute \src 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attribute \src "libresoc.v:146079.3-146087.6" - wire $0\q_int$next[0:0]$8011 - attribute \src "libresoc.v:146077.3-146078.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:146079.3-146087.6" - wire $1\q_int$next[0:0]$8012 - attribute \src "libresoc.v:146056.7-146056.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:146069.17-146069.96" - wire $and$libresoc.v:146069$8001_Y - attribute \src "libresoc.v:146074.17-146074.96" - wire $and$libresoc.v:146074$8006_Y - attribute \src "libresoc.v:146071.18-146071.93" - wire $not$libresoc.v:146071$8003_Y - attribute \src "libresoc.v:146073.17-146073.92" - wire $not$libresoc.v:146073$8005_Y - attribute \src "libresoc.v:146076.17-146076.92" - wire $not$libresoc.v:146076$8008_Y - attribute \src "libresoc.v:146070.18-146070.98" - wire $or$libresoc.v:146070$8002_Y - attribute \src "libresoc.v:146072.18-146072.99" - wire $or$libresoc.v:146072$8004_Y - attribute \src "libresoc.v:146075.17-146075.97" - wire $or$libresoc.v:146075$8007_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:146034.7-146034.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146069$8001 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:146069$8001_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146074$8006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:146074$8006_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146071$8003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:146071$8003_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146073$8005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146073$8005_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146076$8008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146076$8008_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146070$8002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:146070$8002_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146072$8004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:146072$8004_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146075$8007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:146075$8007_Y - end - attribute \src "libresoc.v:146034.7-146034.20" - process $proc$libresoc.v:146034$8013 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146056.7-146056.19" - process $proc$libresoc.v:146056$8014 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:146077.3-146078.27" - process $proc$libresoc.v:146077$8009 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:146079.3-146087.6" - process $proc$libresoc.v:146079$8010 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8011 $1\q_int$next[0:0]$8012 - attribute \src "libresoc.v:146080.5-146080.29" - switch \initial - attribute \src "libresoc.v:146080.9-146080.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8012 1'0 - case - assign $1\q_int$next[0:0]$8012 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8011 - end - connect \$9 $and$libresoc.v:146069$8001_Y - connect \$11 $or$libresoc.v:146070$8002_Y - connect \$13 $not$libresoc.v:146071$8003_Y - connect \$15 $or$libresoc.v:146072$8004_Y - connect \$1 $not$libresoc.v:146073$8005_Y - connect \$3 $and$libresoc.v:146074$8006_Y - connect \$5 $or$libresoc.v:146075$8007_Y - connect \$7 $not$libresoc.v:146076$8008_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:146095.1-146153.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" -attribute \generator "nMigen" -module \opc_l$11 - attribute \src "libresoc.v:146096.7-146096.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146141.3-146149.6" - wire $0\q_int$next[0:0]$8025 - attribute \src "libresoc.v:146139.3-146140.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:146141.3-146149.6" - wire $1\q_int$next[0:0]$8026 - attribute \src "libresoc.v:146118.7-146118.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:146131.17-146131.96" - wire $and$libresoc.v:146131$8015_Y - attribute \src "libresoc.v:146136.17-146136.96" - wire $and$libresoc.v:146136$8020_Y - attribute \src "libresoc.v:146133.18-146133.93" - wire $not$libresoc.v:146133$8017_Y - attribute \src "libresoc.v:146135.17-146135.92" - wire $not$libresoc.v:146135$8019_Y - attribute \src "libresoc.v:146138.17-146138.92" - wire $not$libresoc.v:146138$8022_Y - attribute \src "libresoc.v:146132.18-146132.98" - wire $or$libresoc.v:146132$8016_Y - attribute \src "libresoc.v:146134.18-146134.99" - wire $or$libresoc.v:146134$8018_Y - attribute \src "libresoc.v:146137.17-146137.97" - wire $or$libresoc.v:146137$8021_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:146096.7-146096.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146131$8015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:146131$8015_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146136$8020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:146136$8020_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146133$8017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:146133$8017_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146135$8019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146135$8019_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146138$8022 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146138$8022_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146132$8016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:146132$8016_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146134$8018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:146134$8018_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146137$8021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:146137$8021_Y - end - attribute \src "libresoc.v:146096.7-146096.20" - process $proc$libresoc.v:146096$8027 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146118.7-146118.19" - process $proc$libresoc.v:146118$8028 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:146139.3-146140.27" - process $proc$libresoc.v:146139$8023 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:146141.3-146149.6" - process $proc$libresoc.v:146141$8024 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8025 $1\q_int$next[0:0]$8026 - attribute \src "libresoc.v:146142.5-146142.29" - switch \initial - attribute \src "libresoc.v:146142.9-146142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8026 1'0 - case - assign $1\q_int$next[0:0]$8026 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8025 - end - connect \$9 $and$libresoc.v:146131$8015_Y - connect \$11 $or$libresoc.v:146132$8016_Y - connect \$13 $not$libresoc.v:146133$8017_Y - connect \$15 $or$libresoc.v:146134$8018_Y - connect \$1 $not$libresoc.v:146135$8019_Y - connect \$3 $and$libresoc.v:146136$8020_Y - connect \$5 $or$libresoc.v:146137$8021_Y - connect \$7 $not$libresoc.v:146138$8022_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:146157.1-146215.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" -attribute \generator "nMigen" -module \opc_l$120 - attribute \src "libresoc.v:146158.7-146158.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146203.3-146211.6" - wire $0\q_int$next[0:0]$8039 - attribute \src "libresoc.v:146201.3-146202.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:146203.3-146211.6" - wire $1\q_int$next[0:0]$8040 - attribute \src "libresoc.v:146180.7-146180.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:146193.17-146193.96" - wire $and$libresoc.v:146193$8029_Y - attribute \src "libresoc.v:146198.17-146198.96" - wire $and$libresoc.v:146198$8034_Y - attribute \src "libresoc.v:146195.18-146195.93" - wire $not$libresoc.v:146195$8031_Y - attribute \src "libresoc.v:146197.17-146197.92" - wire $not$libresoc.v:146197$8033_Y - attribute \src "libresoc.v:146200.17-146200.92" - wire $not$libresoc.v:146200$8036_Y - attribute \src "libresoc.v:146194.18-146194.98" - wire $or$libresoc.v:146194$8030_Y - attribute \src "libresoc.v:146196.18-146196.99" - wire $or$libresoc.v:146196$8032_Y - attribute \src "libresoc.v:146199.17-146199.97" - wire $or$libresoc.v:146199$8035_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:146158.7-146158.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146193$8029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:146193$8029_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146198$8034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:146198$8034_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146195$8031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:146195$8031_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146197$8033 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146197$8033_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146200$8036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146200$8036_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146194$8030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:146194$8030_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146196$8032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:146196$8032_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146199$8035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:146199$8035_Y - end - attribute \src "libresoc.v:146158.7-146158.20" - process $proc$libresoc.v:146158$8041 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146180.7-146180.19" - process $proc$libresoc.v:146180$8042 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:146201.3-146202.27" - process $proc$libresoc.v:146201$8037 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:146203.3-146211.6" - process $proc$libresoc.v:146203$8038 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8039 $1\q_int$next[0:0]$8040 - attribute \src "libresoc.v:146204.5-146204.29" - switch \initial - attribute \src "libresoc.v:146204.9-146204.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8040 1'0 - case - assign $1\q_int$next[0:0]$8040 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8039 - end - connect \$9 $and$libresoc.v:146193$8029_Y - connect \$11 $or$libresoc.v:146194$8030_Y - connect \$13 $not$libresoc.v:146195$8031_Y - connect \$15 $or$libresoc.v:146196$8032_Y - connect \$1 $not$libresoc.v:146197$8033_Y - connect \$3 $and$libresoc.v:146198$8034_Y - connect \$5 $or$libresoc.v:146199$8035_Y - connect \$7 $not$libresoc.v:146200$8036_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:146219.1-146277.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" -attribute \generator "nMigen" -module \opc_l$126 - attribute \src "libresoc.v:146220.7-146220.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146265.3-146273.6" - wire $0\q_int$next[0:0]$8053 - attribute \src "libresoc.v:146263.3-146264.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:146265.3-146273.6" - wire $1\q_int$next[0:0]$8054 - attribute \src "libresoc.v:146242.7-146242.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:146255.17-146255.96" - wire $and$libresoc.v:146255$8043_Y - attribute \src "libresoc.v:146260.17-146260.96" - wire $and$libresoc.v:146260$8048_Y - attribute \src "libresoc.v:146257.18-146257.93" - wire $not$libresoc.v:146257$8045_Y - attribute \src "libresoc.v:146259.17-146259.92" - wire $not$libresoc.v:146259$8047_Y - attribute \src "libresoc.v:146262.17-146262.92" - wire $not$libresoc.v:146262$8050_Y - attribute \src "libresoc.v:146256.18-146256.98" - wire $or$libresoc.v:146256$8044_Y - attribute \src "libresoc.v:146258.18-146258.99" - wire $or$libresoc.v:146258$8046_Y - attribute \src "libresoc.v:146261.17-146261.97" - wire $or$libresoc.v:146261$8049_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:146220.7-146220.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146255$8043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:146255$8043_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146260$8048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:146260$8048_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146257$8045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:146257$8045_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146259$8047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146259$8047_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146262$8050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146262$8050_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146256$8044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:146256$8044_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146258$8046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:146258$8046_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146261$8049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:146261$8049_Y - end - attribute \src "libresoc.v:146220.7-146220.20" - process $proc$libresoc.v:146220$8055 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146242.7-146242.19" - process $proc$libresoc.v:146242$8056 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:146263.3-146264.27" - process $proc$libresoc.v:146263$8051 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:146265.3-146273.6" - process $proc$libresoc.v:146265$8052 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8053 $1\q_int$next[0:0]$8054 - attribute \src "libresoc.v:146266.5-146266.29" - switch \initial - attribute \src "libresoc.v:146266.9-146266.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8054 1'0 - case - assign $1\q_int$next[0:0]$8054 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8053 - end - connect \$9 $and$libresoc.v:146255$8043_Y - connect \$11 $or$libresoc.v:146256$8044_Y - connect \$13 $not$libresoc.v:146257$8045_Y - connect \$15 $or$libresoc.v:146258$8046_Y - connect \$1 $not$libresoc.v:146259$8047_Y - connect \$3 $and$libresoc.v:146260$8048_Y - connect \$5 $or$libresoc.v:146261$8049_Y - connect \$7 $not$libresoc.v:146262$8050_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:146281.1-146339.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" -attribute \generator "nMigen" -module \opc_l$24 - attribute \src "libresoc.v:146282.7-146282.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146327.3-146335.6" - wire $0\q_int$next[0:0]$8067 - attribute \src "libresoc.v:146325.3-146326.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:146327.3-146335.6" - wire $1\q_int$next[0:0]$8068 - attribute \src "libresoc.v:146304.7-146304.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:146317.17-146317.96" - wire $and$libresoc.v:146317$8057_Y - attribute \src "libresoc.v:146322.17-146322.96" - wire $and$libresoc.v:146322$8062_Y - attribute \src "libresoc.v:146319.18-146319.93" - wire $not$libresoc.v:146319$8059_Y - attribute \src "libresoc.v:146321.17-146321.92" - wire $not$libresoc.v:146321$8061_Y - attribute \src "libresoc.v:146324.17-146324.92" - wire $not$libresoc.v:146324$8064_Y - attribute \src "libresoc.v:146318.18-146318.98" - wire $or$libresoc.v:146318$8058_Y - attribute \src "libresoc.v:146320.18-146320.99" - wire $or$libresoc.v:146320$8060_Y - attribute \src "libresoc.v:146323.17-146323.97" - wire $or$libresoc.v:146323$8063_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:146282.7-146282.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146317$8057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:146317$8057_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146322$8062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:146322$8062_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146319$8059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:146319$8059_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146321$8061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146321$8061_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146324$8064 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146324$8064_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146318$8058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:146318$8058_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146320$8060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:146320$8060_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146323$8063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:146323$8063_Y - end - attribute \src "libresoc.v:146282.7-146282.20" - process $proc$libresoc.v:146282$8069 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146304.7-146304.19" - process $proc$libresoc.v:146304$8070 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:146325.3-146326.27" - process $proc$libresoc.v:146325$8065 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:146327.3-146335.6" - process $proc$libresoc.v:146327$8066 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8067 $1\q_int$next[0:0]$8068 - attribute \src "libresoc.v:146328.5-146328.29" - switch \initial - attribute \src "libresoc.v:146328.9-146328.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8068 1'0 - case - assign $1\q_int$next[0:0]$8068 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8067 - end - connect \$9 $and$libresoc.v:146317$8057_Y - connect \$11 $or$libresoc.v:146318$8058_Y - connect \$13 $not$libresoc.v:146319$8059_Y - connect \$15 $or$libresoc.v:146320$8060_Y - connect \$1 $not$libresoc.v:146321$8061_Y - connect \$3 $and$libresoc.v:146322$8062_Y - connect \$5 $or$libresoc.v:146323$8063_Y - connect \$7 $not$libresoc.v:146324$8064_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:146343.1-146401.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" -attribute \generator "nMigen" -module \opc_l$40 - attribute \src "libresoc.v:146344.7-146344.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146389.3-146397.6" - wire $0\q_int$next[0:0]$8081 - attribute \src "libresoc.v:146387.3-146388.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:146389.3-146397.6" - wire $1\q_int$next[0:0]$8082 - attribute \src "libresoc.v:146366.7-146366.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:146379.17-146379.96" - wire $and$libresoc.v:146379$8071_Y - attribute \src "libresoc.v:146384.17-146384.96" - wire $and$libresoc.v:146384$8076_Y - attribute \src "libresoc.v:146381.18-146381.93" - wire $not$libresoc.v:146381$8073_Y - attribute \src "libresoc.v:146383.17-146383.92" - wire $not$libresoc.v:146383$8075_Y - attribute \src "libresoc.v:146386.17-146386.92" - wire $not$libresoc.v:146386$8078_Y - attribute \src "libresoc.v:146380.18-146380.98" - wire $or$libresoc.v:146380$8072_Y - attribute \src "libresoc.v:146382.18-146382.99" - wire $or$libresoc.v:146382$8074_Y - attribute \src "libresoc.v:146385.17-146385.97" - wire $or$libresoc.v:146385$8077_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:146344.7-146344.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146379$8071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:146379$8071_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146384$8076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:146384$8076_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146381$8073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:146381$8073_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146383$8075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146383$8075_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146386$8078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146386$8078_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146380$8072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:146380$8072_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146382$8074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:146382$8074_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146385$8077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:146385$8077_Y - end - attribute \src "libresoc.v:146344.7-146344.20" - process $proc$libresoc.v:146344$8083 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146366.7-146366.19" - process $proc$libresoc.v:146366$8084 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:146387.3-146388.27" - process $proc$libresoc.v:146387$8079 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:146389.3-146397.6" - process $proc$libresoc.v:146389$8080 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8081 $1\q_int$next[0:0]$8082 - attribute \src "libresoc.v:146390.5-146390.29" - switch \initial - attribute \src "libresoc.v:146390.9-146390.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8082 1'0 - case - assign $1\q_int$next[0:0]$8082 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8081 - end - connect \$9 $and$libresoc.v:146379$8071_Y - connect \$11 $or$libresoc.v:146380$8072_Y - connect \$13 $not$libresoc.v:146381$8073_Y - connect \$15 $or$libresoc.v:146382$8074_Y - connect \$1 $not$libresoc.v:146383$8075_Y - connect \$3 $and$libresoc.v:146384$8076_Y - connect \$5 $or$libresoc.v:146385$8077_Y - connect \$7 $not$libresoc.v:146386$8078_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:146405.1-146463.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" -attribute \generator "nMigen" -module \opc_l$56 - attribute \src "libresoc.v:146406.7-146406.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146451.3-146459.6" - wire $0\q_int$next[0:0]$8095 - attribute \src "libresoc.v:146449.3-146450.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:146451.3-146459.6" - wire $1\q_int$next[0:0]$8096 - attribute \src "libresoc.v:146428.7-146428.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:146441.17-146441.96" - wire $and$libresoc.v:146441$8085_Y - attribute \src "libresoc.v:146446.17-146446.96" - wire $and$libresoc.v:146446$8090_Y - attribute \src "libresoc.v:146443.18-146443.93" - wire $not$libresoc.v:146443$8087_Y - attribute \src "libresoc.v:146445.17-146445.92" - wire $not$libresoc.v:146445$8089_Y - attribute \src "libresoc.v:146448.17-146448.92" - wire $not$libresoc.v:146448$8092_Y - attribute \src "libresoc.v:146442.18-146442.98" - wire $or$libresoc.v:146442$8086_Y - attribute \src "libresoc.v:146444.18-146444.99" - wire $or$libresoc.v:146444$8088_Y - attribute \src "libresoc.v:146447.17-146447.97" - wire $or$libresoc.v:146447$8091_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:146406.7-146406.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:146441$8085 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:146441$8085_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:146446$8090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:146446$8090_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:146443$8087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $not$libresoc.v:146443$8087_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:146445$8089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146445$8089_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:146448$8092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $not$libresoc.v:146448$8092_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:146442$8086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_opc - connect \Y $or$libresoc.v:146442$8086_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:146444$8088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $or$libresoc.v:146444$8088_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:146447$8091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_opc - connect \Y $or$libresoc.v:146447$8091_Y - end - attribute \src "libresoc.v:146406.7-146406.20" - process $proc$libresoc.v:146406$8097 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:146428.7-146428.19" - process $proc$libresoc.v:146428$8098 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:146449.3-146450.27" - process $proc$libresoc.v:146449$8093 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:146451.3-146459.6" - process $proc$libresoc.v:146451$8094 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$8095 $1\q_int$next[0:0]$8096 - attribute \src "libresoc.v:146452.5-146452.29" - switch \initial - attribute \src "libresoc.v:146452.9-146452.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\q_int$next[0:0]$8096 1'0 - case - assign $1\q_int$next[0:0]$8096 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$8095 - end - connect \$9 $and$libresoc.v:146441$8085_Y - connect \$11 $or$libresoc.v:146442$8086_Y - connect \$13 $not$libresoc.v:146443$8087_Y - connect \$15 $or$libresoc.v:146444$8088_Y - connect \$1 $not$libresoc.v:146445$8089_Y - connect \$3 $and$libresoc.v:146446$8090_Y - connect \$5 $or$libresoc.v:146447$8091_Y - connect \$7 $not$libresoc.v:146448$8092_Y - connect \qlq_opc \$15 - connect \qn_opc \$13 - connect \q_opc \$11 -end -attribute \src "libresoc.v:146467.1-146525.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" -attribute \generator "nMigen" -module \opc_l$68 - attribute \src "libresoc.v:146468.7-146468.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:146513.3-146521.6" - wire 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attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 27 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 28 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \alu_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src 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attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 26 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 46 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 47 \cr_a_ok - attribute \src "libresoc.v:146592.7-146592.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire \is_negative - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 54 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 25 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 44 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 45 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:146948$8140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:146948$8140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:146941$8133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:146941$8133_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:146942$8134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001100 - connect \Y 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src 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\enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 25 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 33 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire \msb_test - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 51 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 24 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 43 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 44 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire \oe$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire \so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 50 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:148503$8207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:148503$8207_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:148511$8217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B \$40 - connect \Y $and$libresoc.v:148511$8217_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:148514$8220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:148514$8220_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:148507$8213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $eq$libresoc.v:148507$8213_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:148508$8214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $eq$libresoc.v:148508$8214_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:148505$8209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \$29 - connect \Y $extend$libresoc.v:148505$8209_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:148506$8211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $extend$libresoc.v:148506$8211_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:148504$8208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $not$libresoc.v:148504$8208_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:148510$8216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $not$libresoc.v:148510$8216_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:148513$8219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $not$libresoc.v:148513$8219_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:148512$8218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $or$libresoc.v:148512$8218_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:148515$8221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $or$libresoc.v:148515$8221_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:148505$8210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148505$8209_Y - connect \Y $pos$libresoc.v:148505$8210_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:148506$8212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:148506$8211_Y - connect \Y $pos$libresoc.v:148506$8212_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:148509$8215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $reduce_or$libresoc.v:148509$8215_Y - end - attribute \src "libresoc.v:148164.7-148164.20" - process $proc$libresoc.v:148164$8235 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:148516.3-148527.6" - process $proc$libresoc.v:148516$8222 - assign { } { } - assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:148517.5-148517.29" - switch \initial - attribute \src "libresoc.v:148517.9-148517.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch \oe - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\so[0:0] \xer_so$24 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\so[0:0] \xer_so - end - sync always - update \so $0\so[0:0] - end - attribute \src "libresoc.v:148528.3-148539.6" - process $proc$libresoc.v:148528$8223 - assign { } { } - assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:148529.5-148529.29" - switch \initial - attribute \src "libresoc.v:148529.9-148529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch \$44 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\cr0[3:0] \cr_a - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } - end - sync always - update \cr0 $0\cr0[3:0] - end - attribute \src "libresoc.v:148540.3-148551.6" - process $proc$libresoc.v:148540$8224 - assign { } { } - assign $0\o$27[64:0]$8225 $1\o$27[64:0]$8226 - attribute \src "libresoc.v:148541.5-148541.29" - switch \initial - attribute \src "libresoc.v:148541.9-148541.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch \logical_op__invert_out - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o$27[64:0]$8226 \$28 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o$27[64:0]$8226 \$32 - end - sync always - update \o$27 $0\o$27[64:0]$8225 - end - attribute \src "libresoc.v:148552.3-148561.6" - process $proc$libresoc.v:148552$8227 - assign { } { } - assign { } { } - assign $0\xer_so$24[0:0]$8228 $1\xer_so$24[0:0]$8229 - attribute \src "libresoc.v:148553.5-148553.29" - switch \initial - attribute \src "libresoc.v:148553.9-148553.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_so$24[0:0]$8229 \$51 - case - assign $1\xer_so$24[0:0]$8229 1'0 - end - sync always - update \xer_so$24 $0\xer_so$24[0:0]$8228 - end - attribute \src "libresoc.v:148562.3-148571.6" - process $proc$libresoc.v:148562$8230 - assign { } { } - assign { } { } - assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:148563.5-148563.29" - switch \initial - attribute \src "libresoc.v:148563.9-148563.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_so_ok[0:0] 1'1 - case - assign $1\xer_so_ok[0:0] 1'0 - end - sync always - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:148572.3-148581.6" - process $proc$libresoc.v:148572$8231 - assign { } { } - assign { } { } - assign $0\xer_ov$23[1:0]$8232 $1\xer_ov$23[1:0]$8233 - attribute \src "libresoc.v:148573.5-148573.29" - switch \initial - attribute \src "libresoc.v:148573.9-148573.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov$23[1:0]$8233 \xer_ov - case - assign $1\xer_ov$23[1:0]$8233 2'00 - end - sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8232 - end - attribute \src "libresoc.v:148582.3-148591.6" - process $proc$libresoc.v:148582$8234 - assign { } { } - assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148583.5-148583.29" - switch \initial - attribute \src "libresoc.v:148583.9-148583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch \oe$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'1 - case - assign $1\xer_ov_ok[0:0] 1'0 - end - sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - connect \$25 $and$libresoc.v:148503$8207_Y - connect \$29 $not$libresoc.v:148504$8208_Y - connect \$28 $pos$libresoc.v:148505$8210_Y - connect \$32 $pos$libresoc.v:148506$8212_Y - connect \$34 $eq$libresoc.v:148507$8213_Y - connect \$36 $eq$libresoc.v:148508$8214_Y - connect \$38 $reduce_or$libresoc.v:148509$8215_Y - connect \$40 $not$libresoc.v:148510$8216_Y - connect \$42 $and$libresoc.v:148511$8217_Y - connect \$44 $or$libresoc.v:148512$8218_Y - connect \$46 $not$libresoc.v:148513$8219_Y - connect \$49 $and$libresoc.v:148514$8220_Y - connect \$51 $or$libresoc.v:148515$8221_Y - connect \oe$48 \$49 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \cr_a_ok \logical_op__write_cr0 - connect \cr_a$22 \cr0 - connect \o_ok$21 \o_ok - connect \o$20 \o$27 [63:0] - connect \is_positive \$42 - connect \is_negative \msb_test - connect \is_nzero \$38 - connect \msb_test \target [63] - connect \is_cmpeqb \$36 - connect \is_cmp \$34 - connect \target \o$27 [63:0] - connect \oe \$25 -end -attribute \src "libresoc.v:148611.1-149087.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" -attribute \generator "nMigen" -module \output_stage - attribute \src "libresoc.v:148612.7-148612.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:148968.3-149039.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:149040.3-149073.6" - wire $0\ov[0:0] - attribute \src "libresoc.v:148968.3-149039.6" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:149040.3-149073.6" - wire $1\ov[0:0] - attribute \src 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\B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [64] - connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:148958$8248_Y - end - attribute \src "libresoc.v:148612.7-148612.20" - process $proc$libresoc.v:148612$8265 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:148968.3-149039.6" - process $proc$libresoc.v:148968$8263 - assign { } { } - assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:148969.5-148969.29" - switch \initial - attribute \src "libresoc.v:148969.9-148969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - switch \$46 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" - switch \logical_op__insn_type - attribute \src "libresoc.v:0.0-0.0" - case 7'0011110 - assign { } { } - assign $2\o[63:0] $3\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" - switch \logical_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:0] $4\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" - switch \logical_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\o[63:0] \$48 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $4\o[63:0] \$50 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\o[63:0] \quotient_65 [63:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0011101 - assign { } { } - assign $2\o[63:0] $5\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" - switch \logical_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\o[63:0] $6\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" - switch \logical_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\o[63:0] \$52 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $6\o[63:0] \$54 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $5\o[63:0] \quotient_65 [63:0] - end - attribute \src "libresoc.v:0.0-0.0" - case 7'0101111 - assign { } { } - assign $2\o[63:0] $7\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" - switch \logical_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $7\o[63:0] $8\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" - switch \logical_op__is_signed - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $8\o[63:0] \remainder_s32_as_s64 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $8\o[63:0] \$56 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $7\o[63:0] \remainder_64 - end - case - assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o $0\o[63:0] + parameter \Y_WIDTH 3 + connect \A \log_dmi_addr [1:0] + connect \B 1'1 + connect \Y $add$libresoc.v:717$89_Y end - attribute \src "libresoc.v:149040.3-149073.6" - process $proc$libresoc.v:149040$8264 - assign { } { } - assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:149041.5-149041.29" - switch \initial - attribute \src "libresoc.v:149041.9-149041.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - switch { \logical_op__is_signed \$36 \div_by_zero } - attribute \src "libresoc.v:0.0-0.0" - case 3'--1 - assign { } { } - assign $1\ov[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 3'-1- - assign { } { } - assign { } { } - assign $1\ov[0:0] $2\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - switch \$40 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ov[0:0] 1'1 - case - assign $2\ov[0:0] \dive_abs_ov64 - end - attribute \src "libresoc.v:0.0-0.0" - case 3'1-- - assign { } { } - assign { } { } - assign $1\ov[0:0] $3\ov[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - switch \$42 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\ov[0:0] 1'1 - case - assign $3\ov[0:0] \dive_abs_ov32 - end - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\ov[0:0] \dive_abs_ov32 - end - sync always - update \ov $0\ov[0:0] - end - connect \$21 $xor$libresoc.v:148950$8236_Y - connect \$23 $neg$libresoc.v:148951$8238_Y - connect \$25 $pos$libresoc.v:148952$8240_Y - connect \$27 $ternary$libresoc.v:148953$8241_Y - connect \$30 $neg$libresoc.v:148954$8243_Y - connect \$32 $pos$libresoc.v:148955$8245_Y - connect \$34 $ternary$libresoc.v:148956$8246_Y - connect \$36 $not$libresoc.v:148957$8247_Y - connect \$38 $xor$libresoc.v:148958$8248_Y - connect \$40 $and$libresoc.v:148959$8249_Y - connect \$42 $ne$libresoc.v:148960$8250_Y - connect \$44 $pos$libresoc.v:148961$8251_Y - connect \$46 $not$libresoc.v:148962$8252_Y - connect \$48 $pos$libresoc.v:148963$8254_Y - connect \$50 $pos$libresoc.v:148964$8256_Y - connect \$52 $pos$libresoc.v:148965$8258_Y - connect \$54 $pos$libresoc.v:148966$8260_Y - connect \$56 $pos$libresoc.v:148967$8262_Y - connect \$29 \$34 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$20 \xer_so - connect \remainder_s32_as_s64 \$44 - connect \remainder_s32 \remainder_64 [31:0] - connect \o_ok 1'1 - connect \xer_ov { \ov \ov } - connect \xer_ov_ok 1'1 - connect \remainder_64 \$34 [63:0] - connect \quotient_65 \$27 - connect \remainder_neg \dividend_neg - connect \quotient_neg \$21 -end -attribute \src "libresoc.v:149091.1-149102.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" -attribute \generator "nMigen" -module \p - attribute \src "libresoc.v:149100.17-149100.111" - wire $and$libresoc.v:149100$8266_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149100$8266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:708$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149100$8266_Y + connect \A \dmi_read_log_data_1 + connect \B \$7 + connect \Y $and$libresoc.v:708$80_Y end - connect \$1 $and$libresoc.v:149100$8266_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149106.1-149117.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" -attribute \generator "nMigen" -module \p$1 - attribute \src "libresoc.v:149115.17-149115.111" - wire $and$libresoc.v:149115$8267_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149115$8267 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:711$83 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149115$8267_Y + connect \A \dmi_req_i + connect \B \$101 + connect \Y $and$libresoc.v:711$83_Y end - connect \$1 $and$libresoc.v:149115$8267_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149121.1-149132.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" -attribute \generator "nMigen" -module \p$108 - attribute \src "libresoc.v:149130.17-149130.111" - wire $and$libresoc.v:149130$8268_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149130$8268 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:713$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149130$8268_Y + connect \A \dmi_read_log_data_1 + connect \B \$105 + connect \Y $and$libresoc.v:713$85_Y end - connect \$1 $and$libresoc.v:149130$8268_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149136.1-149147.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" -attribute \generator "nMigen" -module \p$111 - attribute \src "libresoc.v:149145.17-149145.111" - wire $and$libresoc.v:149145$8269_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149145$8269 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $and $and$libresoc.v:720$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149145$8269_Y + connect \A \dmi_req_i + connect \B \$118 + connect \Y $and$libresoc.v:720$92_Y end - connect \$1 $and$libresoc.v:149145$8269_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149151.1-149162.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" -attribute \generator "nMigen" -module \p$116 - attribute \src "libresoc.v:149160.17-149160.111" - wire $and$libresoc.v:149160$8270_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149160$8270 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $and $and$libresoc.v:722$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149160$8270_Y + connect \A \stopping + connect \B \$122 + connect \Y $and$libresoc.v:722$94_Y end - connect \$1 $and$libresoc.v:149160$8270_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149166.1-149177.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" -attribute \generator "nMigen" -module \p$17 - attribute \src "libresoc.v:149175.17-149175.111" - wire $and$libresoc.v:149175$8271_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149175$8271 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:727$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149175$8271_Y + connect \A \dmi_req_i + connect \B \$17 + connect \Y $and$libresoc.v:727$99_Y end - connect \$1 $and$libresoc.v:149175$8271_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149181.1-149192.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" -attribute \generator "nMigen" -module \p$20 - attribute \src "libresoc.v:149190.17-149190.111" - wire $and$libresoc.v:149190$8272_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149190$8272 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:729$101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149190$8272_Y + connect \A \dmi_read_log_data_1 + connect \B \$21 + connect \Y $and$libresoc.v:729$101_Y end - connect \$1 $and$libresoc.v:149190$8272_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149196.1-149207.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" -attribute \generator "nMigen" -module \p$3 - attribute \src "libresoc.v:149205.17-149205.111" - wire $and$libresoc.v:149205$8273_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149205$8273 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:734$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149205$8273_Y + connect \A \dmi_req_i + connect \B \$31 + connect \Y $and$libresoc.v:734$106_Y end - connect \$1 $and$libresoc.v:149205$8273_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149211.1-149222.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" -attribute \generator "nMigen" -module \p$30 - attribute \src "libresoc.v:149220.17-149220.111" - wire $and$libresoc.v:149220$8274_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149220$8274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:736$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149220$8274_Y + connect \A \dmi_read_log_data_1 + connect \B \$35 + connect \Y $and$libresoc.v:736$108_Y end - connect \$1 $and$libresoc.v:149220$8274_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149226.1-149237.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" -attribute \generator "nMigen" -module \p$33 - attribute \src "libresoc.v:149235.17-149235.111" - wire $and$libresoc.v:149235$8275_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149235$8275 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:742$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149235$8275_Y + connect \A \dmi_req_i + connect \B \$45 + connect \Y $and$libresoc.v:742$114_Y end - connect \$1 $and$libresoc.v:149235$8275_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149241.1-149252.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" -attribute \generator "nMigen" -module \p$36 - attribute \src "libresoc.v:149250.17-149250.111" - wire $and$libresoc.v:149250$8276_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149250$8276 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:744$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149250$8276_Y + connect \A \dmi_read_log_data_1 + connect \B \$49 + connect \Y $and$libresoc.v:744$116_Y end - connect \$1 $and$libresoc.v:149250$8276_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149256.1-149267.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" -attribute \generator "nMigen" -module \p$46 - attribute \src "libresoc.v:149265.17-149265.111" - wire $and$libresoc.v:149265$8277_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149265$8277 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:748$120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149265$8277_Y + connect \A \dmi_req_i + connect \B \$3 + connect \Y $and$libresoc.v:748$120_Y end - connect \$1 $and$libresoc.v:149265$8277_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149271.1-149282.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" -attribute \generator "nMigen" -module \p$48 - attribute \src "libresoc.v:149280.17-149280.111" - wire $and$libresoc.v:149280$8278_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149280$8278 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:750$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149280$8278_Y + connect \A \dmi_req_i + connect \B \$59 + connect \Y $and$libresoc.v:750$122_Y end - connect \$1 $and$libresoc.v:149280$8278_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149286.1-149297.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" -attribute \generator "nMigen" -module \p$5 - attribute \src "libresoc.v:149295.17-149295.111" - wire $and$libresoc.v:149295$8279_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149295$8279 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:752$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149295$8279_Y + connect \A \dmi_read_log_data_1 + connect \B \$63 + connect \Y $and$libresoc.v:752$124_Y end - connect \$1 $and$libresoc.v:149295$8279_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149301.1-149312.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" -attribute \generator "nMigen" -module \p$52 - attribute \src "libresoc.v:149310.17-149310.111" - wire $and$libresoc.v:149310$8280_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149310$8280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:757$129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149310$8280_Y + connect \A \dmi_req_i + connect \B \$73 + connect \Y $and$libresoc.v:757$129_Y end - connect \$1 $and$libresoc.v:149310$8280_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149316.1-149327.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" -attribute \generator "nMigen" -module \p$62 - attribute \src "libresoc.v:149325.17-149325.111" - wire $and$libresoc.v:149325$8281_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149325$8281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:760$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149325$8281_Y + connect \A \dmi_read_log_data_1 + connect \B \$77 + connect \Y $and$libresoc.v:760$132_Y end - connect \$1 $and$libresoc.v:149325$8281_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149331.1-149342.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" -attribute \generator "nMigen" -module \p$65 - attribute \src "libresoc.v:149340.17-149340.111" - wire $and$libresoc.v:149340$8282_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149340$8282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $and $and$libresoc.v:765$137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149340$8282_Y + connect \A \dmi_req_i + connect \B \$87 + connect \Y $and$libresoc.v:765$137_Y end - connect \$1 $and$libresoc.v:149340$8282_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149346.1-149357.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" -attribute \generator "nMigen" -module \p$7 - attribute \src "libresoc.v:149355.17-149355.111" - wire $and$libresoc.v:149355$8283_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149355$8283 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$libresoc.v:767$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149355$8283_Y + connect \A \dmi_read_log_data_1 + connect \B \$91 + connect \Y $and$libresoc.v:767$139_Y end - connect \$1 $and$libresoc.v:149355$8283_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149361.1-149372.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" -attribute \generator "nMigen" -module \p$74 - attribute \src "libresoc.v:149370.17-149370.111" - wire $and$libresoc.v:149370$8284_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149370$8284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:709$81 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149370$8284_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:709$81_Y end - connect \$1 $and$libresoc.v:149370$8284_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149376.1-149387.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" -attribute \generator "nMigen" -module \p$76 - attribute \src "libresoc.v:149385.17-149385.111" - wire $and$libresoc.v:149385$8285_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149385$8285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:714$86 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149385$8285_Y + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:714$86_Y end - connect \$1 $and$libresoc.v:149385$8285_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149391.1-149402.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" -attribute \generator "nMigen" -module \p$79 - attribute \src "libresoc.v:149400.17-149400.111" - wire $and$libresoc.v:149400$8286_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149400$8286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:715$87 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149400$8286_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:715$87_Y end - connect \$1 $and$libresoc.v:149400$8286_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149406.1-149417.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" -attribute \generator "nMigen" -module \p$81 - attribute \src "libresoc.v:149415.17-149415.111" - wire $and$libresoc.v:149415$8287_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149415$8287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:716$88 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149415$8287_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:716$88_Y end - connect \$1 $and$libresoc.v:149415$8287_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149421.1-149432.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" -attribute \generator "nMigen" -module \p$91 - attribute \src "libresoc.v:149430.17-149430.111" - wire $and$libresoc.v:149430$8288_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149430$8288 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:242" + cell $eq $eq$libresoc.v:718$90 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149430$8288_Y + connect \A \dmi_addr_i + connect \B 3'111 + connect \Y $eq$libresoc.v:718$90_Y end - connect \$1 $and$libresoc.v:149430$8288_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149436.1-149447.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" -attribute \generator "nMigen" -module \p$93 - attribute \src "libresoc.v:149445.17-149445.111" - wire $and$libresoc.v:149445$8289_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149445$8289 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:719$91 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149445$8289_Y + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:719$91_Y end - connect \$1 $and$libresoc.v:149445$8289_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149451.1-149462.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" -attribute \generator "nMigen" -module \p$96 - attribute \src "libresoc.v:149460.17-149460.111" - wire $and$libresoc.v:149460$8290_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149460$8290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:723$95 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149460$8290_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:723$95_Y end - connect \$1 $and$libresoc.v:149460$8290_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149466.1-149477.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" -attribute \generator "nMigen" -module \p$98 - attribute \src "libresoc.v:149475.17-149475.111" - wire $and$libresoc.v:149475$8291_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $and$libresoc.v:149475$8291 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:724$96 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $and$libresoc.v:149475$8291_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:724$96_Y end - connect \$1 $and$libresoc.v:149475$8291_Y - connect \trigger \$1 -end -attribute \src "libresoc.v:149481.1-149504.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" -attribute \generator "nMigen" -module \pick - attribute \src "libresoc.v:149482.7-149482.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:149493.3-149502.6" - wire $0\o[0:0] - attribute \src "libresoc.v:149493.3-149502.6" - wire $1\o[0:0] - attribute \src "libresoc.v:149492.17-149492.95" - wire $eq$libresoc.v:149492$8292_Y - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire input 3 \i - attribute \src "libresoc.v:149482.7-149482.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire output 2 \n - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:149492$8292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:730$102 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \i + connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:149492$8292_Y - end - attribute \src "libresoc.v:149482.7-149482.20" - process $proc$libresoc.v:149482$8294 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:149493.3-149502.6" - process $proc$libresoc.v:149493$8293 - assign { } { } - assign { } { } - assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:149494.5-149494.29" - switch \initial - attribute \src "libresoc.v:149494.9-149494.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch \i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\o[0:0] 1'0 - case - assign $1\o[0:0] 1'0 - end - sync always - update \o $0\o[0:0] - end - connect \$1 $eq$libresoc.v:149492$8292_Y - connect \n \$1 -end -attribute \src "libresoc.v:149508.1-150322.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" -attribute \generator "nMigen" -module \pimem - attribute \src "libresoc.v:150285.3-150300.6" - wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150249.3-150284.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8384 - attribute \src "libresoc.v:149807.3-149808.57" - wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:149899.3-149907.6" - wire $0\busy_delay$next[0:0]$8352 - attribute \src "libresoc.v:149805.3-149806.37" - wire $0\busy_delay[0:0] - attribute \src "libresoc.v:150233.3-150248.6" - wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:150223.3-150232.6" - wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:150213.3-150222.6" - wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:150194.3-150203.6" - wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:150155.3-150193.6" - wire width 2 $0\fsm_state$next[1:0]$8370 - attribute \src "libresoc.v:149797.3-149798.35" - wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:149509.7-149509.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:150095.3-150104.6" - wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:149803.3-149804.35" - wire $0\lds_dly[0:0] - attribute \src "libresoc.v:150028.3-150058.6" - wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:150085.3-150094.6" - wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:150105.3-150114.6" - wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:149934.3-149949.6" - wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149918.3-149933.6" - wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:150204.3-150212.6" - wire $0\lsui_active_dly$next[0:0]$8378 - attribute \src "libresoc.v:149795.3-149796.47" - wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:150135.3-150154.6" - wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:149799.3-149800.36" - wire $0\reset_delay[0:0] - attribute \src "libresoc.v:150075.3-150084.6" - wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:150059.3-150074.6" - wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:149908.3-149917.6" - wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:149889.3-149898.6" - wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:149874.3-149888.6" - wire $0\st_done_s_st_done$next[0:0]$8347 - attribute \src "libresoc.v:149809.3-149810.51" - wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:150115.3-150124.6" - wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:149801.3-149802.35" - wire $0\sts_dly[0:0] - attribute \src "libresoc.v:149950.3-149975.6" - wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:150002.3-150027.6" - wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:149976.3-150001.6" - wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:150125.3-150134.6" - wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:150285.3-150300.6" - wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150249.3-150284.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8385 - attribute \src "libresoc.v:149603.7-149603.34" - wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:149899.3-149907.6" - wire $1\busy_delay$next[0:0]$8353 - attribute \src "libresoc.v:149607.7-149607.24" - wire $1\busy_delay[0:0] - attribute \src "libresoc.v:150233.3-150248.6" - wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:150223.3-150232.6" - wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:150213.3-150222.6" - wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:150194.3-150203.6" - wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:150155.3-150193.6" - wire width 2 $1\fsm_state$next[1:0]$8371 - attribute \src "libresoc.v:149629.13-149629.29" - wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:150095.3-150104.6" - wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:149643.7-149643.21" - wire $1\lds_dly[0:0] - attribute \src "libresoc.v:150028.3-150058.6" - wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:150085.3-150094.6" - wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:150105.3-150114.6" - wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:149934.3-149949.6" - wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149918.3-149933.6" - wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:150204.3-150212.6" - wire $1\lsui_active_dly$next[0:0]$8379 - attribute \src "libresoc.v:149686.7-149686.29" - wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:150135.3-150154.6" - wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:149698.7-149698.25" - wire $1\reset_delay[0:0] - attribute \src "libresoc.v:150075.3-150084.6" - wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:150059.3-150074.6" - wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:149908.3-149917.6" - wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:149889.3-149898.6" - wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:149874.3-149888.6" - wire $1\st_done_s_st_done$next[0:0]$8348 - attribute \src "libresoc.v:149718.7-149718.31" - wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:150115.3-150124.6" - wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:149726.7-149726.21" - wire $1\sts_dly[0:0] - attribute \src "libresoc.v:149950.3-149975.6" - wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:150002.3-150027.6" - wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:149976.3-150001.6" - wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:150125.3-150134.6" - wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:150285.3-150300.6" - wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150249.3-150284.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8386 - attribute \src "libresoc.v:150233.3-150248.6" - wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:150155.3-150193.6" - wire width 2 $2\fsm_state$next[1:0]$8372 - attribute \src "libresoc.v:150028.3-150058.6" - wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149934.3-149949.6" - wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149918.3-149933.6" - wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:150135.3-150154.6" - wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:150059.3-150074.6" - wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:149874.3-149888.6" - wire $2\st_done_s_st_done$next[0:0]$8349 - attribute \src "libresoc.v:149950.3-149975.6" - wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:150002.3-150027.6" - wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:149976.3-150001.6" - wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:150249.3-150284.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8387 - attribute \src "libresoc.v:150155.3-150193.6" - wire width 2 $3\fsm_state$next[1:0]$8373 - attribute \src "libresoc.v:150028.3-150058.6" - wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149950.3-149975.6" - wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:150002.3-150027.6" - wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:149976.3-150001.6" - wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:150249.3-150284.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8388 - attribute \src "libresoc.v:150155.3-150193.6" - wire width 2 $4\fsm_state$next[1:0]$8374 - attribute \src "libresoc.v:150028.3-150058.6" - wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:149950.3-149975.6" - wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:150002.3-150027.6" - wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:149976.3-150001.6" - wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:150249.3-150284.6" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" - wire \busy_edge - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \busy_l_q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \busy_l_r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \cyc_l_q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \cyc_l_r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \cyc_l_s_cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state$next - attribute \src "libresoc.v:149509.7-149509.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \ld_active_q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \ld_active_r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \ld_active_s_ld_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" - wire width 64 \lddata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" - wire \lds - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lds_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lds_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \lds_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 48 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire output 10 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire output 4 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire input 18 \ldst_port0_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire input 2 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 12 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 13 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 15 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 14 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 \lenexp_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 \lenexp_len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 \lenexp_lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 \lenexp_rexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" - wire \lsui_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lsui_active_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \lsui_active_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \lsui_active_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" - wire \lsui_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" - wire width 64 input 11 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" - wire output 21 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" - wire \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" - wire \reset_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \reset_l_q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \st_active_q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \st_active_r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \st_active_s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \st_done_q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \st_done_r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \st_done_s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \st_done_s_st_done$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" - wire width 64 \stdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" - wire \sts - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \sts_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \sts_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \sts_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \valid_l_q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \valid_l_r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \valid_l_s_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 48 output 9 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" - wire input 17 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" - wire output 19 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" - wire width 8 output 8 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire width 64 output 16 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" - wire output 20 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" - wire output 22 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:149755$8296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \B \$9 - connect \Y $and$libresoc.v:149755$8296_Y + connect \Y $eq$libresoc.v:730$102_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:149757$8298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:731$103 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \lds - connect \B \$13 - connect \Y $and$libresoc.v:149757$8298_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:731$103_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:149759$8300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:732$104 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:149759$8300_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:732$104_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:149760$8301 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:738$110 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sts - connect \B \$17 - connect \Y $and$libresoc.v:149760$8301_Y + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:738$110_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149763$8306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:739$111 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149763$8306_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:739$111_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149764$8307 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:740$112 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149764$8307_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:740$112_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149765$8308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:745$117 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149765$8308_Y + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:745$117_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149766$8309 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:746$118 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149766$8309_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:746$118_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:149767$8310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:747$119 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:149767$8310_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:149772$8315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 176 - parameter \Y_WIDTH 176 - connect \A \m_ld_data_o - connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:149772$8315_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:747$119_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:149775$8318 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:753$125 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:149775$8318_Y + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:753$125_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:149776$8319 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:754$126 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:149776$8319_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:754$126_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:149778$8321 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:755$127 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:149778$8321_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:755$127_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:149782$8325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:761$133 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:149782$8325_Y + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:761$133_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:149784$8327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:762$134 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$63 - connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:149784$8327_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:762$134_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:149786$8329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:763$135 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \$67 - connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:149786$8329_Y + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:763$135_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:149790$8333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:768$140 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$73 - connect \B \$75 - connect \Y $and$libresoc.v:149790$8333_Y + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:768$140_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:149791$8334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:769$141 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:149791$8334_Y + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:769$141_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:149794$8337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:710$82 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \lsui_active - connect \B \$81 - connect \Y $and$libresoc.v:149794$8337_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149761$8302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:149761$8302_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149762$8304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:149762$8304_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:149773$8316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $mul$libresoc.v:149773$8316_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:149779$8322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $mul$libresoc.v:149779$8322_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:710$82_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:149754$8295 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:712$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $not$libresoc.v:149754$8295_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:712$84_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:149756$8297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $not $not$libresoc.v:721$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \lds_dly - connect \Y $not$libresoc.v:149756$8297_Y + connect \A \do_step + connect \Y $not$libresoc.v:721$93_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:149758$8299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:725$97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \sts_dly - connect \Y $not$libresoc.v:149758$8299_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:725$97_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:149768$8311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:728$100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $not$libresoc.v:149768$8311_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:728$100_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:149771$8314 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:733$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$38 - connect \Y $not$libresoc.v:149771$8314_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:733$105_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:149777$8320 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:735$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $not$libresoc.v:149777$8320_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:735$107_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:149780$8323 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:737$109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $not$libresoc.v:149780$8323_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:737$109_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:149787$8330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:741$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \Y $not$libresoc.v:149787$8330_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:741$113_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:149788$8331 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:743$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:149788$8331_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:743$115_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:149789$8332 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:749$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:149789$8332_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:749$121_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:149792$8335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:751$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \Y $not$libresoc.v:149792$8335_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:751$123_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:149793$8336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:756$128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \lsui_active_dly - connect \Y $not$libresoc.v:149793$8336_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:756$128_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:149769$8312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:758$130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \B \lsui_busy - connect \Y $or$libresoc.v:149769$8312_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:758$130_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:149770$8313 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:759$131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:149770$8313_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:759$131_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:149783$8326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:764$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:149783$8326_Y + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:764$136_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:149785$8328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:766$138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:149785$8328_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149761$8303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:149761$8302_Y - connect \Y $pos$libresoc.v:149761$8303_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149762$8305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:149762$8304_Y - connect \Y $pos$libresoc.v:149762$8305_Y + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:766$138_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:149781$8324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + cell $pos $pos$libresoc.v:726$98 parameter \A_SIGNED 0 parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 319 - connect \A \ldst_port0_st_data_i - connect \B \$57 - connect \Y $sshl$libresoc.v:149781$8324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:149774$8317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 176 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 176 - connect \A \$42 - connect \B \$44 - connect \Y $sshr$libresoc.v:149774$8317_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149811.11-149818.4" - cell \adrok_l \adrok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_addr_acked \adrok_l_q_addr_acked - connect \qn_addr_acked \adrok_l_qn_addr_acked - connect \r_addr_acked \adrok_l_r_addr_acked - connect \s_addr_acked \adrok_l_s_addr_acked - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149819.10-149825.4" - cell \busy_l \busy_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_busy \busy_l_q_busy - connect \r_busy \busy_l_r_busy - connect \s_busy \busy_l_s_busy - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149826.9-149832.4" - cell \cyc_l \cyc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_cyc \cyc_l_q_cyc - connect \r_cyc \cyc_l_r_cyc - connect \s_cyc \cyc_l_s_cyc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149833.13-149839.4" - cell \ld_active \ld_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_ld_active \ld_active_q_ld_active - connect \r_ld_active \ld_active_r_ld_active - connect \s_ld_active \ld_active_s_ld_active - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149840.10-149845.4" - cell \lenexp \lenexp - connect \addr_i \lenexp_addr_i - connect \len_i \lenexp_len_i - connect \lexp_o \lenexp_lexp_o - connect \rexp_o \lenexp_rexp_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149846.11-149852.4" - cell \reset_l \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_reset \reset_l_q_reset - connect \r_reset \reset_l_r_reset - connect \s_reset \reset_l_s_reset - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149853.13-149859.4" - cell \st_active \st_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_st_active \st_active_q_st_active - connect \r_st_active \st_active_r_st_active - connect \s_st_active \st_active_s_st_active - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149860.11-149866.4" - cell \st_done \st_done - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_st_done \st_done_q_st_done - connect \r_st_done \st_done_r_st_done - connect \s_st_done \st_done_s_st_done - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:149867.11-149873.4" - cell \valid_l \valid_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_valid \valid_l_q_valid - connect \r_valid \valid_l_r_valid - connect \s_valid \valid_l_s_valid - end - attribute \src "libresoc.v:149509.7-149509.20" - process $proc$libresoc.v:149509$8392 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:149603.7-149603.34" - process $proc$libresoc.v:149603$8393 - assign { } { } - assign $1\adrok_l_s_addr_acked[0:0] 1'0 - sync always - sync init - update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] - end - attribute \src "libresoc.v:149607.7-149607.24" - process $proc$libresoc.v:149607$8394 - assign { } { } - assign $1\busy_delay[0:0] 1'0 - sync always - sync init - update \busy_delay $1\busy_delay[0:0] - end - attribute \src "libresoc.v:149629.13-149629.29" - process $proc$libresoc.v:149629$8395 - assign { } { } - assign $1\fsm_state[1:0] 2'00 - sync always - sync init - update \fsm_state $1\fsm_state[1:0] - end - attribute \src "libresoc.v:149643.7-149643.21" - process $proc$libresoc.v:149643$8396 - assign { } { } - assign $1\lds_dly[0:0] 1'0 - sync always - sync init - update \lds_dly $1\lds_dly[0:0] - end - attribute \src "libresoc.v:149686.7-149686.29" - process $proc$libresoc.v:149686$8397 - assign { } { } - assign $1\lsui_active_dly[0:0] 1'0 - sync always - sync init - update \lsui_active_dly $1\lsui_active_dly[0:0] - end - attribute \src "libresoc.v:149698.7-149698.25" - process $proc$libresoc.v:149698$8398 - assign { } { } - assign $1\reset_delay[0:0] 1'0 - sync always - sync init - update \reset_delay $1\reset_delay[0:0] - end - attribute \src "libresoc.v:149718.7-149718.31" - process $proc$libresoc.v:149718$8399 - assign { } { } - assign $1\st_done_s_st_done[0:0] 1'0 - sync always - sync init - update \st_done_s_st_done $1\st_done_s_st_done[0:0] - end - attribute \src "libresoc.v:149726.7-149726.21" - process $proc$libresoc.v:149726$8400 - assign { } { } - assign $1\sts_dly[0:0] 1'0 - sync always - sync init - update \sts_dly $1\sts_dly[0:0] - end - attribute \src "libresoc.v:149795.3-149796.47" - process $proc$libresoc.v:149795$8338 - assign { } { } - assign $0\lsui_active_dly[0:0] \lsui_active_dly$next - sync posedge \coresync_clk - update \lsui_active_dly $0\lsui_active_dly[0:0] - end - attribute \src "libresoc.v:149797.3-149798.35" - process $proc$libresoc.v:149797$8339 - assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \coresync_clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "libresoc.v:149799.3-149800.36" - process $proc$libresoc.v:149799$8340 - assign { } { } - assign $0\reset_delay[0:0] \reset_l_q_reset - sync posedge \coresync_clk - update \reset_delay $0\reset_delay[0:0] - end - attribute \src "libresoc.v:149801.3-149802.35" - process $proc$libresoc.v:149801$8341 - assign { } { } - assign $0\sts_dly[0:0] \ldst_port0_is_st_i - sync posedge \coresync_clk - update \sts_dly $0\sts_dly[0:0] - end - attribute \src "libresoc.v:149803.3-149804.35" - process $proc$libresoc.v:149803$8342 - assign { } { } - assign $0\lds_dly[0:0] \ldst_port0_is_ld_i - sync posedge \coresync_clk - update \lds_dly $0\lds_dly[0:0] - end - attribute \src "libresoc.v:149805.3-149806.37" - process $proc$libresoc.v:149805$8343 - assign { } { } - assign $0\busy_delay[0:0] \busy_delay$next - sync posedge \coresync_clk - update \busy_delay $0\busy_delay[0:0] - end - attribute \src "libresoc.v:149807.3-149808.57" - process $proc$libresoc.v:149807$8344 - assign { } { } - assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next - sync posedge \coresync_clk - update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] - end - attribute \src "libresoc.v:149809.3-149810.51" - process $proc$libresoc.v:149809$8345 - assign { } { } - assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next - sync posedge \coresync_clk - update \st_done_s_st_done $0\st_done_s_st_done[0:0] + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:726$98_Y end - attribute \src "libresoc.v:149874.3-149888.6" - process $proc$libresoc.v:149874$8346 + attribute \src "libresoc.v:1003.3-1012.6" + process $proc$libresoc.v:1003$195 assign { } { } assign { } { } - assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8347 $2\st_done_s_st_done$next[0:0]$8349 - attribute \src "libresoc.v:149875.5-149875.29" + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:1004.5-1004.29" switch \initial - attribute \src "libresoc.v:149875.9-149875.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:1004.9-1004.17" case 1'1 - assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8348 1'1 case - assign $1\st_done_s_st_done$next[0:0]$8348 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'1000 assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8349 1'0 + assign $1\d_cr_req[0:0] \dmi_req_i case - assign $2\st_done_s_st_done$next[0:0]$8349 $1\st_done_s_st_done$next[0:0]$8348 + assign $1\d_cr_req[0:0] 1'0 end sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8347 + update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:149889.3-149898.6" - process $proc$libresoc.v:149889$8350 + attribute \src "libresoc.v:1013.3-1022.6" + process $proc$libresoc.v:1013$196 assign { } { } assign { } { } - assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:149890.5-149890.29" + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:1014.5-1014.29" switch \initial - attribute \src "libresoc.v:149890.9-149890.17" + attribute \src "libresoc.v:1014.9-1014.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'1001 assign { } { } - assign $1\st_done_r_st_done[0:0] 1'1 + assign $1\d_xer_req[0:0] \dmi_req_i case - assign $1\st_done_r_st_done[0:0] 1'0 + assign $1\d_xer_req[0:0] 1'0 end sync always - update \st_done_r_st_done $0\st_done_r_st_done[0:0] + update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:149899.3-149907.6" - process $proc$libresoc.v:149899$8351 + attribute \src "libresoc.v:1023.3-1053.6" + process $proc$libresoc.v:1023$197 assign { } { } assign { } { } - assign $0\busy_delay$next[0:0]$8352 $1\busy_delay$next[0:0]$8353 - attribute \src "libresoc.v:149900.5-149900.29" + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:1024.5-1024.29" switch \initial - attribute \src "libresoc.v:149900.9-149900.17" + attribute \src "libresoc.v:1024.9-1024.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0001 assign { } { } - assign $1\busy_delay$next[0:0]$8353 1'0 - case - assign $1\busy_delay$next[0:0]$8353 \ldst_port0_busy_o - end - sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8352 - end - attribute \src "libresoc.v:149908.3-149917.6" - process $proc$libresoc.v:149908$8354 - assign { } { } - assign { } { } - assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:149909.5-149909.29" - switch \initial - attribute \src "libresoc.v:149909.9-149909.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset + assign $1\dmi_dout[63:0] \stat_reg attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0010 assign { } { } - assign $1\st_active_r_st_active[0:0] 1'1 - case - assign $1\st_active_r_st_active[0:0] 1'0 - end - sync always - update \st_active_r_st_active $0\st_active_r_st_active[0:0] - end - attribute \src "libresoc.v:149918.3-149933.6" - process $proc$libresoc.v:149918$8355 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:149919.5-149919.29" - switch \initial - attribute \src "libresoc.v:149919.9-149919.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + assign $1\dmi_dout[63:0] \core_dbg_pc attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0011 assign { } { } - assign $1\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $1\lenexp_len_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active + assign $1\dmi_dout[63:0] \core_dbg_msr attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0101 assign { } { } - assign $2\lenexp_len_i[3:0] \ldst_port0_data_len - case - assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] - end - sync always - update \lenexp_len_i $0\lenexp_len_i[3:0] - end - attribute \src "libresoc.v:149934.3-149949.6" - process $proc$libresoc.v:149934$8356 - assign { } { } - assign { } { } - assign { } { } - assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:149935.5-149935.29" - switch \initial - attribute \src "libresoc.v:149935.9-149935.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + assign $1\dmi_dout[63:0] \d_gpr_data attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0110 assign { } { } - assign $1\lenexp_addr_i[3:0] \$21 - case - assign $1\lenexp_addr_i[3:0] 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $2\lenexp_addr_i[3:0] \$23 + assign $1\dmi_dout[63:0] \d_xer_data case - assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \lenexp_addr_i $0\lenexp_addr_i[3:0] + update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:149950.3-149975.6" - process $proc$libresoc.v:149950$8357 + attribute \src "libresoc.v:1054.3-1083.6" + process $proc$libresoc.v:1054$198 assign { } { } assign { } { } assign { } { } - assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:149951.5-149951.29" + assign $0\do_step$next[0:0]$199 $5\do_step$next[0:0]$204 + attribute \src "libresoc.v:1055.5-1055.29" switch \initial - attribute \src "libresoc.v:149951.9-149951.17" + attribute \src "libresoc.v:1055.9-1055.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$9 \$5 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$25 + assign $1\do_step$next[0:0]$200 $2\do_step$next[0:0]$201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\valid_l_s_valid[0:0] 1'1 + assign $2\do_step$next[0:0]$201 $3\do_step$next[0:0]$202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$15 \$13 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$202 $4\do_step$next[0:0]$203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$203 1'1 + case + assign $4\do_step$next[0:0]$203 1'0 + end + case + assign $3\do_step$next[0:0]$202 1'0 + end case - assign $2\valid_l_s_valid[0:0] 1'0 + assign $2\do_step$next[0:0]$201 1'0 end case - assign $1\valid_l_s_valid[0:0] 1'0 + assign $1\do_step$next[0:0]$200 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\valid_l_s_valid[0:0] 1'1 - case - assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] - end + assign $5\do_step$next[0:0]$204 1'0 case - assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + assign $5\do_step$next[0:0]$204 $1\do_step$next[0:0]$200 end sync always - update \valid_l_s_valid $0\valid_l_s_valid[0:0] + update \do_step$next $0\do_step$next[0:0]$199 end - attribute \src "libresoc.v:149976.3-150001.6" - process $proc$libresoc.v:149976$8358 + attribute \src "libresoc.v:1084.3-1113.6" + process $proc$libresoc.v:1084$205 assign { } { } assign { } { } assign { } { } - assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:149977.5-149977.29" + assign $0\do_reset$next[0:0]$206 $5\do_reset$next[0:0]$211 + attribute \src "libresoc.v:1085.5-1085.29" switch \initial - attribute \src "libresoc.v:149977.9-149977.17" + attribute \src "libresoc.v:1085.9-1085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$23 \$19 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$27 + assign $1\do_reset$next[0:0]$207 $2\do_reset$next[0:0]$208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + assign $2\do_reset$next[0:0]$208 $3\do_reset$next[0:0]$209 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$29 \$27 \$25 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$209 $4\do_reset$next[0:0]$210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$210 1'1 + case + assign $4\do_reset$next[0:0]$210 1'0 + end + case + assign $3\do_reset$next[0:0]$209 1'0 + end case - assign $2\x_mask_i[7:0] 8'00000000 + assign $2\do_reset$next[0:0]$208 1'0 end case - assign $1\x_mask_i[7:0] 8'00000000 + assign $1\do_reset$next[0:0]$207 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] - case - assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] - end + assign $5\do_reset$next[0:0]$211 1'0 case - assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] + assign $5\do_reset$next[0:0]$211 $1\do_reset$next[0:0]$207 end sync always - update \x_mask_i $0\x_mask_i[7:0] + update \do_reset$next $0\do_reset$next[0:0]$206 end - attribute \src "libresoc.v:150002.3-150027.6" - process $proc$libresoc.v:150002$8359 + attribute \src "libresoc.v:1114.3-1143.6" + process $proc$libresoc.v:1114$212 assign { } { } assign { } { } assign { } { } - assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:150003.5-150003.29" + assign $0\do_icreset$next[0:0]$213 $5\do_icreset$next[0:0]$218 + attribute \src "libresoc.v:1115.5-1115.29" switch \initial - attribute \src "libresoc.v:150003.9-150003.17" + attribute \src "libresoc.v:1115.9-1115.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$37 \$33 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$29 + assign $1\do_icreset$next[0:0]$214 $2\do_icreset$next[0:0]$215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\x_addr_i[47:0] \ldst_port0_addr_i + assign $2\do_icreset$next[0:0]$215 $3\do_icreset$next[0:0]$216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$43 \$41 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$216 $4\do_icreset$next[0:0]$217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$217 1'1 + case + assign $4\do_icreset$next[0:0]$217 1'0 + end + case + assign $3\do_icreset$next[0:0]$216 1'0 + end case - assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + assign $2\do_icreset$next[0:0]$215 1'0 end case - assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + assign $1\do_icreset$next[0:0]$214 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\x_addr_i[47:0] \ldst_port0_addr_i - case - assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] - end + assign $5\do_icreset$next[0:0]$218 1'0 case - assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] + assign $5\do_icreset$next[0:0]$218 $1\do_icreset$next[0:0]$214 end sync always - update \x_addr_i $0\x_addr_i[47:0] + update \do_icreset$next $0\do_icreset$next[0:0]$213 end - attribute \src "libresoc.v:150028.3-150058.6" - process $proc$libresoc.v:150028$8360 + attribute \src "libresoc.v:1144.3-1177.6" + process $proc$libresoc.v:1144$219 assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:150029.5-150029.29" + assign $0\do_dmi_log_rd$next[0:0]$220 $4\do_dmi_log_rd$next[0:0]$224 + attribute \src "libresoc.v:1145.5-1145.29" switch \initial - attribute \src "libresoc.v:150029.9-150029.17" + attribute \src "libresoc.v:1145.9-1145.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$51 \$47 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$31 + assign $1\do_dmi_log_rd$next[0:0]$221 $2\do_dmi_log_rd$next[0:0]$222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + assign $2\do_dmi_log_rd$next[0:0]$222 $3\do_dmi_log_rd$next[0:0]$223 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$57 \$55 \$53 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$223 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$223 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$223 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$223 1'0 + end case - assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + assign $2\do_dmi_log_rd$next[0:0]$222 1'0 end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$221 1'1 case - assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + assign $1\do_dmi_log_rd$next[0:0]$221 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - switch \adrok_l_qn_addr_acked - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\ldst_port0_addr_ok_o[0:0] 1'1 - case - assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end - case - assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - end + assign $4\do_dmi_log_rd$next[0:0]$224 1'0 case - assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + assign $4\do_dmi_log_rd$next[0:0]$224 $1\do_dmi_log_rd$next[0:0]$221 end sync always - update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$220 + end + attribute \src "libresoc.v:474.7-474.20" + process $proc$libresoc.v:474$225 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:647.7-647.31" + process $proc$libresoc.v:647$226 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:651.7-651.33" + process $proc$libresoc.v:651$227 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:657.7-657.25" + process $proc$libresoc.v:657$228 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:663.7-663.27" + process $proc$libresoc.v:663$229 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:667.7-667.24" + process $proc$libresoc.v:667$230 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:671.7-671.22" + process $proc$libresoc.v:671$231 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:675.7-675.21" + process $proc$libresoc.v:675$232 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:150059.3-150074.6" - process $proc$libresoc.v:150059$8361 - assign { } { } + attribute \src "libresoc.v:679.13-679.31" + process $proc$libresoc.v:679$233 assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:685.14-685.34" + process $proc$libresoc.v:685$234 assign { } { } - assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:150060.5-150060.29" - switch \initial - attribute \src "libresoc.v:150060.9-150060.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$33 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_s_reset[0:0] \$35 - case - assign $1\reset_l_s_reset[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" - switch \st_done_q_st_done - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\reset_l_s_reset[0:0] \$37 - case - assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - end + assign $1\log_dmi_addr[31:0] 0 sync always - update \reset_l_s_reset $0\reset_l_s_reset[0:0] + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:150075.3-150084.6" - process $proc$libresoc.v:150075$8362 + attribute \src "libresoc.v:697.7-697.22" + process $proc$libresoc.v:697$235 assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:703.7-703.24" + process $proc$libresoc.v:703$236 assign { } { } - assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:150076.5-150076.29" - switch \initial - attribute \src "libresoc.v:150076.9-150076.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\reset_l_r_reset[0:0] 1'1 - case - assign $1\reset_l_r_reset[0:0] 1'0 - end + assign $1\terminated[0:0] 1'0 sync always - update \reset_l_r_reset $0\reset_l_r_reset[0:0] + sync init + update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:150085.3-150094.6" - process $proc$libresoc.v:150085$8363 + attribute \src "libresoc.v:770.3-771.51" + process $proc$libresoc.v:770$142 assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:772.3-773.55" + process $proc$libresoc.v:772$143 assign { } { } - assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:150086.5-150086.29" - switch \initial - attribute \src "libresoc.v:150086.9-150086.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$48 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ldst_port0_ld_data_o[63:0] \lddata - case - assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:774.3-775.41" + process $proc$libresoc.v:774$144 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:150095.3-150104.6" - process $proc$libresoc.v:150095$8364 + attribute \src "libresoc.v:776.3-777.37" + process $proc$libresoc.v:776$145 assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:778.3-779.33" + process $proc$libresoc.v:778$146 assign { } { } - assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:150096.5-150096.29" - switch \initial - attribute \src "libresoc.v:150096.9-150096.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\ld_active_r_ld_active[0:0] 1'1 - case - assign $1\ld_active_r_ld_active[0:0] 1'0 - end - sync always - update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:780.3-781.37" + process $proc$libresoc.v:780$147 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:782.3-783.39" + process $proc$libresoc.v:782$148 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:784.3-785.43" + process $proc$libresoc.v:784$149 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:786.3-787.37" + process $proc$libresoc.v:786$150 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:788.3-789.33" + process $proc$libresoc.v:788$151 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:150105.3-150114.6" - process $proc$libresoc.v:150105$8365 + attribute \src "libresoc.v:790.3-791.31" + process $proc$libresoc.v:790$152 assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:792.3-809.6" + process $proc$libresoc.v:792$153 assign { } { } - assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:150106.5-150106.29" + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:793.5-793.29" switch \initial - attribute \src "libresoc.v:150106.9-150106.17" + attribute \src "libresoc.v:793.9-793.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" case - assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i end sync always - update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:150115.3-150124.6" - process $proc$libresoc.v:150115$8366 + attribute \src "libresoc.v:810.3-819.6" + process $proc$libresoc.v:810$154 assign { } { } assign { } { } - assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:150116.5-150116.29" + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:811.5-811.29" switch \initial - attribute \src "libresoc.v:150116.9-150116.17" + attribute \src "libresoc.v:811.9-811.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0101 assign { } { } - assign $1\stdata[63:0] \$56 [63:0] + assign $1\d_gpr_req[0:0] \dmi_req_i case - assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\d_gpr_req[0:0] 1'0 end sync always - update \stdata $0\stdata[63:0] + update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:150125.3-150134.6" - process $proc$libresoc.v:150125$8367 + attribute \src "libresoc.v:820.3-828.6" + process $proc$libresoc.v:820$155 assign { } { } assign { } { } - assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:150126.5-150126.29" + assign $0\dmi_req_i_1$next[0:0]$156 $1\dmi_req_i_1$next[0:0]$157 + attribute \src "libresoc.v:821.5-821.29" switch \initial - attribute \src "libresoc.v:150126.9-150126.17" + attribute \src "libresoc.v:821.9-821.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - switch \$61 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\x_st_data_i[63:0] \stdata + assign $1\dmi_req_i_1$next[0:0]$157 1'0 case - assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dmi_req_i_1$next[0:0]$157 \dmi_req_i end sync always - update \x_st_data_i $0\x_st_data_i[63:0] + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$156 end - attribute \src "libresoc.v:150135.3-150154.6" - process $proc$libresoc.v:150135$8368 + attribute \src "libresoc.v:829.3-878.6" + process $proc$libresoc.v:829$158 assign { } { } assign { } { } - assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:150136.5-150136.29" + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$159 $8\terminated$next[0:0]$167 + attribute \src "libresoc.v:830.5-830.29" switch \initial - attribute \src "libresoc.v:150136.9-150136.17" + attribute \src "libresoc.v:830.9-830.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$65 \$61 } attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 2'-1 assign { } { } - assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$65 + assign $1\terminated$next[0:0]$160 $2\terminated$next[0:0]$161 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\lsui_busy[0:0] 1'1 + assign $2\terminated$next[0:0]$161 $3\terminated$next[0:0]$162 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$71 \$69 \$67 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$162 $6\terminated$next[0:0]$165 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$163 1'0 + case + assign $4\terminated$next[0:0]$163 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$164 1'0 + case + assign $5\terminated$next[0:0]$164 $4\terminated$next[0:0]$163 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$165 1'0 + case + assign $6\terminated$next[0:0]$165 $5\terminated$next[0:0]$164 + end + case + assign $3\terminated$next[0:0]$162 \terminated + end case - assign $2\lsui_busy[0:0] 1'0 + assign $2\terminated$next[0:0]$161 \terminated end + case + assign $1\terminated$next[0:0]$160 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$166 1'1 + case + assign $7\terminated$next[0:0]$166 $1\terminated$next[0:0]$160 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 assign { } { } - assign $1\lsui_busy[0:0] 1'1 + assign $8\terminated$next[0:0]$167 1'0 case - assign $1\lsui_busy[0:0] 1'0 + assign $8\terminated$next[0:0]$167 $7\terminated$next[0:0]$166 end sync always - update \lsui_busy $0\lsui_busy[0:0] + update \terminated$next $0\terminated$next[0:0]$159 end - attribute \src "libresoc.v:150155.3-150193.6" - process $proc$libresoc.v:150155$8369 + attribute \src "libresoc.v:879.3-922.6" + process $proc$libresoc.v:879$168 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$8370 $5\fsm_state$next[1:0]$8375 - attribute \src "libresoc.v:150156.5-150156.29" + assign { } { } + assign $0\stopping$next[0:0]$169 $7\stopping$next[0:0]$176 + attribute \src "libresoc.v:880.5-880.29" switch \initial - attribute \src "libresoc.v:150156.9-150156.17" + attribute \src "libresoc.v:880.9-880.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\fsm_state$next[1:0]$8371 $2\fsm_state$next[1:0]$8372 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$8372 2'01 - case - assign $2\fsm_state$next[1:0]$8372 \fsm_state - end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$79 \$75 } attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 2'-1 assign { } { } - assign $1\fsm_state$next[1:0]$8371 $3\fsm_state$next[1:0]$8373 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - switch \$71 + assign $1\stopping$next[0:0]$170 $2\stopping$next[0:0]$171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$8373 2'10 + assign $2\stopping$next[0:0]$171 $3\stopping$next[0:0]$172 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$85 \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$172 $5\stopping$next[0:0]$174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$173 1'1 + case + assign $4\stopping$next[0:0]$173 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$174 1'0 + case + assign $5\stopping$next[0:0]$174 $4\stopping$next[0:0]$173 + end + case + assign $3\stopping$next[0:0]$172 \stopping + end case - assign $3\fsm_state$next[1:0]$8373 \fsm_state + assign $2\stopping$next[0:0]$171 \stopping end + case + assign $1\stopping$next[0:0]$170 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 1'1 assign { } { } - assign $1\fsm_state$next[1:0]$8371 $4\fsm_state$next[1:0]$8374 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - switch \$77 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$8374 2'00 - case - assign $4\fsm_state$next[1:0]$8374 \fsm_state - end + assign $6\stopping$next[0:0]$175 1'1 case - assign $1\fsm_state$next[1:0]$8371 \fsm_state + assign $6\stopping$next[0:0]$175 $1\stopping$next[0:0]$170 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8375 2'00 + assign $7\stopping$next[0:0]$176 1'0 case - assign $5\fsm_state$next[1:0]$8375 $1\fsm_state$next[1:0]$8371 + assign $7\stopping$next[0:0]$176 $6\stopping$next[0:0]$175 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8370 + update \stopping$next $0\stopping$next[0:0]$169 end - attribute \src "libresoc.v:150194.3-150203.6" - process $proc$libresoc.v:150194$8376 + attribute \src "libresoc.v:923.3-950.6" + process $proc$libresoc.v:923$177 + assign { } { } assign { } { } assign { } { } - assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:150195.5-150195.29" + assign $0\gspr_index$next[6:0]$178 $4\gspr_index$next[6:0]$182 + attribute \src "libresoc.v:924.5-924.29" switch \initial - attribute \src "libresoc.v:150195.9-150195.17" + attribute \src "libresoc.v:924.9-924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" - switch \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$93 \$89 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\cyc_l_s_cyc[0:0] 1'1 - case - assign $1\cyc_l_s_cyc[0:0] 1'0 - end - sync always - update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] - end - attribute \src "libresoc.v:150204.3-150212.6" - process $proc$libresoc.v:150204$8377 - assign { } { } - assign { } { } - assign $0\lsui_active_dly$next[0:0]$8378 $1\lsui_active_dly$next[0:0]$8379 - attribute \src "libresoc.v:150205.5-150205.29" - switch \initial - attribute \src "libresoc.v:150205.9-150205.17" - case 1'1 + assign $1\gspr_index$next[6:0]$179 $2\gspr_index$next[6:0]$180 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$180 $3\gspr_index$next[6:0]$181 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$99 \$97 \$95 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$181 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$181 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$181 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$180 \gspr_index + end case + assign $1\gspr_index$next[6:0]$179 \gspr_index end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8379 1'0 + assign $4\gspr_index$next[6:0]$182 7'0000000 case - assign $1\lsui_active_dly$next[0:0]$8379 \lsui_active + assign $4\gspr_index$next[6:0]$182 $1\gspr_index$next[6:0]$179 end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8378 + update \gspr_index$next $0\gspr_index$next[6:0]$178 end - attribute \src "libresoc.v:150213.3-150222.6" - process $proc$libresoc.v:150213$8380 + attribute \src "libresoc.v:951.3-984.6" + process $proc$libresoc.v:951$183 assign { } { } assign { } { } - assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:150214.5-150214.29" + assign { } { } + assign $0\log_dmi_addr$next[31:0]$184 $4\log_dmi_addr$next[31:0]$188 + attribute \src "libresoc.v:952.5-952.29" switch \initial - attribute \src "libresoc.v:150214.9-150214.17" + attribute \src "libresoc.v:952.9-952.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" - switch \cyc_l_q_cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$107 \$103 } attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'-1 assign { } { } - assign $1\cyc_l_r_cyc[0:0] 1'1 - case - assign $1\cyc_l_r_cyc[0:0] 1'0 - end - sync always - update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] - end - attribute \src "libresoc.v:150223.3-150232.6" - process $proc$libresoc.v:150223$8381 - assign { } { } - assign { } { } - assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:150224.5-150224.29" - switch \initial - attribute \src "libresoc.v:150224.9-150224.17" - case 1'1 + assign $1\log_dmi_addr$next[31:0]$185 $2\log_dmi_addr$next[31:0]$186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$186 $3\log_dmi_addr$next[31:0]$187 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$113 \$111 \$109 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$187 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$187 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$186 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$185 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$185 [1:0] \$115 [1:0] case + assign $1\log_dmi_addr$next[31:0]$185 \log_dmi_addr end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch \$3 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_l_s_busy[0:0] \$5 + assign $4\log_dmi_addr$next[31:0]$188 0 case - assign $1\busy_l_s_busy[0:0] 1'0 + assign $4\log_dmi_addr$next[31:0]$188 $1\log_dmi_addr$next[31:0]$185 end sync always - update \busy_l_s_busy $0\busy_l_s_busy[0:0] + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$184 end - attribute \src "libresoc.v:150233.3-150248.6" - process $proc$libresoc.v:150233$8382 - assign { } { } + attribute \src "libresoc.v:985.3-993.6" + process $proc$libresoc.v:985$189 assign { } { } assign { } { } - assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:150234.5-150234.29" + assign $0\dmi_read_log_data_1$next[0:0]$190 $1\dmi_read_log_data_1$next[0:0]$191 + attribute \src "libresoc.v:986.5-986.29" switch \initial - attribute \src "libresoc.v:150234.9-150234.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" - switch \ldst_port0_exc_$signal - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:986.9-986.17" case 1'1 - assign { } { } - assign $1\busy_l_r_busy[0:0] 1'1 case - assign $1\busy_l_r_busy[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" - switch \cyc_l_q_cyc + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\busy_l_r_busy[0:0] 1'1 + assign $1\dmi_read_log_data_1$next[0:0]$191 1'0 case - assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + assign $1\dmi_read_log_data_1$next[0:0]$191 \dmi_read_log_data end sync always - update \busy_l_r_busy $0\busy_l_r_busy[0:0] + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$190 end - attribute \src "libresoc.v:150249.3-150284.6" - process $proc$libresoc.v:150249$8383 - assign { } { } + attribute \src "libresoc.v:994.3-1002.6" + process $proc$libresoc.v:994$192 assign { } { } assign { } { } - assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8384 $6\adrok_l_s_addr_acked$next[0:0]$8390 - attribute \src "libresoc.v:150250.5-150250.29" + assign $0\dmi_read_log_data$next[0:0]$193 $1\dmi_read_log_data$next[0:0]$194 + attribute \src "libresoc.v:995.5-995.29" switch \initial - attribute \src "libresoc.v:150250.9-150250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch \ld_active_q_ld_active - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8385 $2\adrok_l_s_addr_acked$next[0:0]$8386 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - switch \$7 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8386 1'1 - case - assign $2\adrok_l_s_addr_acked$next[0:0]$8386 1'0 - end - case - assign $1\adrok_l_s_addr_acked$next[0:0]$8385 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - switch \st_active_q_st_active - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:995.9-995.17" case 1'1 - assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8387 $4\adrok_l_s_addr_acked$next[0:0]$8388 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" - switch \ldst_port0_addr_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8388 $5\adrok_l_s_addr_acked$next[0:0]$8389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" - switch \adrok_l_qn_addr_acked - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8389 1'1 - case - assign $5\adrok_l_s_addr_acked$next[0:0]$8389 $1\adrok_l_s_addr_acked$next[0:0]$8385 - end - case - assign $4\adrok_l_s_addr_acked$next[0:0]$8388 $1\adrok_l_s_addr_acked$next[0:0]$8385 - end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8387 $1\adrok_l_s_addr_acked$next[0:0]$8385 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8390 1'0 - case - assign $6\adrok_l_s_addr_acked$next[0:0]$8390 $3\adrok_l_s_addr_acked$next[0:0]$8387 - end - sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8384 - end - attribute \src "libresoc.v:150285.3-150300.6" - process $proc$libresoc.v:150285$8391 - assign { } { } - assign { } { } - assign { } { } - assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:150286.5-150286.29" - switch \initial - attribute \src "libresoc.v:150286.9-150286.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" - switch \reset_delay - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\adrok_l_r_addr_acked[0:0] 1'1 - case - assign $1\adrok_l_r_addr_acked[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" - switch \reset_l_q_reset - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\adrok_l_r_addr_acked[0:0] 1'1 - case - assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] - end - sync always - update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] - end - connect \$9 $not$libresoc.v:149754$8295_Y - connect \$11 $and$libresoc.v:149755$8296_Y - connect \$13 $not$libresoc.v:149756$8297_Y - connect \$15 $and$libresoc.v:149757$8298_Y - connect \$17 $not$libresoc.v:149758$8299_Y - connect \$1 $and$libresoc.v:149759$8300_Y - connect \$19 $and$libresoc.v:149760$8301_Y - connect \$21 $pos$libresoc.v:149761$8303_Y - connect \$23 $pos$libresoc.v:149762$8305_Y - connect \$25 $and$libresoc.v:149763$8306_Y - connect \$27 $and$libresoc.v:149764$8307_Y - connect \$29 $and$libresoc.v:149765$8308_Y - connect \$31 $and$libresoc.v:149766$8309_Y - connect \$33 $and$libresoc.v:149767$8310_Y - connect \$35 $not$libresoc.v:149768$8311_Y - connect \$38 $or$libresoc.v:149769$8312_Y - connect \$3 $or$libresoc.v:149770$8313_Y - connect \$37 $not$libresoc.v:149771$8314_Y - connect \$42 $and$libresoc.v:149772$8315_Y - connect \$44 $mul$libresoc.v:149773$8316_Y - connect \$46 $sshr$libresoc.v:149774$8317_Y - connect \$48 $and$libresoc.v:149775$8318_Y - connect \$50 $and$libresoc.v:149776$8319_Y - connect \$52 $not$libresoc.v:149777$8320_Y - connect \$54 $and$libresoc.v:149778$8321_Y - connect \$57 $mul$libresoc.v:149779$8322_Y - connect \$5 $not$libresoc.v:149780$8323_Y - connect \$59 $sshl$libresoc.v:149781$8324_Y - connect \$61 $and$libresoc.v:149782$8325_Y - connect \$63 $or$libresoc.v:149783$8326_Y - connect \$65 $and$libresoc.v:149784$8327_Y - connect \$67 $or$libresoc.v:149785$8328_Y - connect \$69 $and$libresoc.v:149786$8329_Y - connect \$71 $not$libresoc.v:149787$8330_Y - connect \$73 $not$libresoc.v:149788$8331_Y - connect \$75 $not$libresoc.v:149789$8332_Y - connect \$77 $and$libresoc.v:149790$8333_Y - connect \$7 $and$libresoc.v:149791$8334_Y - connect \$79 $not$libresoc.v:149792$8335_Y - connect \$81 $not$libresoc.v:149793$8336_Y - connect \$83 $and$libresoc.v:149794$8337_Y - connect \$41 \$46 - connect \$56 \$59 - connect \valid_l_r_valid \lsui_active_rise - connect \lsui_active_rise \$83 - connect \lsui_active \$79 - connect \x_valid_i \valid_l_q_valid - connect \m_valid_i \valid_l_q_valid - connect \x_st_i \ldst_port0_is_st_i - connect \x_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_busy_o \busy_l_q_busy - connect \reset_delay$next \reset_l_q_reset - connect \lddata \$46 [63:0] - connect \st_active_s_st_active \sts_rise - connect \sts_rise \$19 - connect \sts_dly$next \sts - connect \ld_active_s_ld_active \lds_rise - connect \lds_rise \$15 - connect \lds_dly$next \lds - connect \busy_edge \$11 - connect \sts \ldst_port0_is_st_i - connect \lds \ldst_port0_is_ld_i + assign $1\dmi_read_log_data$next[0:0]$194 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$194 \$120 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$193 + end + connect \$9 $and$libresoc.v:708$80_Y + connect \$99 $eq$libresoc.v:709$81_Y + connect \$101 $not$libresoc.v:710$82_Y + connect \$103 $and$libresoc.v:711$83_Y + connect \$105 $not$libresoc.v:712$84_Y + connect \$107 $and$libresoc.v:713$85_Y + connect \$109 $eq$libresoc.v:714$86_Y + connect \$111 $eq$libresoc.v:715$87_Y + connect \$113 $eq$libresoc.v:716$88_Y + connect \$116 $add$libresoc.v:717$89_Y + connect \$118 $eq$libresoc.v:718$90_Y + connect \$11 $eq$libresoc.v:719$91_Y + connect \$120 $and$libresoc.v:720$92_Y + connect \$122 $not$libresoc.v:721$93_Y + connect \$124 $and$libresoc.v:722$94_Y + connect \$13 $eq$libresoc.v:723$95_Y + connect \$15 $eq$libresoc.v:724$96_Y + connect \$17 $not$libresoc.v:725$97_Y + connect \$1 $pos$libresoc.v:726$98_Y + connect \$19 $and$libresoc.v:727$99_Y + connect \$21 $not$libresoc.v:728$100_Y + connect \$23 $and$libresoc.v:729$101_Y + connect \$25 $eq$libresoc.v:730$102_Y + connect \$27 $eq$libresoc.v:731$103_Y + connect \$29 $eq$libresoc.v:732$104_Y + connect \$31 $not$libresoc.v:733$105_Y + connect \$33 $and$libresoc.v:734$106_Y + connect \$35 $not$libresoc.v:735$107_Y + connect \$37 $and$libresoc.v:736$108_Y + connect \$3 $not$libresoc.v:737$109_Y + connect \$39 $eq$libresoc.v:738$110_Y + connect \$41 $eq$libresoc.v:739$111_Y + connect \$43 $eq$libresoc.v:740$112_Y + connect \$45 $not$libresoc.v:741$113_Y + connect \$47 $and$libresoc.v:742$114_Y + connect \$49 $not$libresoc.v:743$115_Y + connect \$51 $and$libresoc.v:744$116_Y + connect \$53 $eq$libresoc.v:745$117_Y + connect \$55 $eq$libresoc.v:746$118_Y + connect \$57 $eq$libresoc.v:747$119_Y + connect \$5 $and$libresoc.v:748$120_Y + connect \$59 $not$libresoc.v:749$121_Y + connect \$61 $and$libresoc.v:750$122_Y + connect \$63 $not$libresoc.v:751$123_Y + connect \$65 $and$libresoc.v:752$124_Y + connect \$67 $eq$libresoc.v:753$125_Y + connect \$69 $eq$libresoc.v:754$126_Y + connect \$71 $eq$libresoc.v:755$127_Y + connect \$73 $not$libresoc.v:756$128_Y + connect \$75 $and$libresoc.v:757$129_Y + connect \$77 $not$libresoc.v:758$130_Y + connect \$7 $not$libresoc.v:759$131_Y + connect \$79 $and$libresoc.v:760$132_Y + connect \$81 $eq$libresoc.v:761$133_Y + connect \$83 $eq$libresoc.v:762$134_Y + connect \$85 $eq$libresoc.v:763$135_Y + connect \$87 $not$libresoc.v:764$136_Y + connect \$89 $and$libresoc.v:765$137_Y + connect \$91 $not$libresoc.v:766$138_Y + connect \$93 $and$libresoc.v:767$139_Y + connect \$95 $eq$libresoc.v:768$140_Y + connect \$97 $eq$libresoc.v:769$141_Y + connect \$115 \$116 + connect \log_write_addr_o 0 + connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \terminated_o \terminated + connect \icache_rst_o \do_icreset + connect \core_rst_o \do_reset + connect \core_stop_o \$124 + connect \d_gpr_addr \gspr_index + connect \stat_reg \$1 end -attribute \src "libresoc.v:150326.1-151091.10" +attribute \src "libresoc.v:1191.1-7124.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" -module \pipe - attribute \src "libresoc.v:151054.3-151072.6" - wire width 4 $0\cr_a$6$next[3:0]$8447 - attribute \src "libresoc.v:150918.3-150919.31" - wire width 4 $0\cr_a$6[3:0]$8403 - attribute \src "libresoc.v:150340.13-150340.28" - wire width 4 $0\cr_a$6[3:0]$8453 - attribute \src "libresoc.v:151054.3-151072.6" - wire $0\cr_a_ok$next[0:0]$8446 - attribute \src "libresoc.v:150920.3-150921.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:151001.3-151015.6" - wire width 12 $0\cr_op__fn_unit$3$next[11:0]$8427 - attribute \src "libresoc.v:150932.3-150933.51" - wire width 12 $0\cr_op__fn_unit$3[11:0]$8413 - attribute \src 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wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 output 27 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 11 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 23 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 20 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 21 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 18 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 output 19 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire output 22 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 output 31 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 output 35 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 16 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire input 36 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec19_dec19_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -313729,18 +4233,39 @@ module \pipe attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 18 \cr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \cr_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 19 \cr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313815,8 +4340,162 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec19_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec19_dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec19_dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec19_dec19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec30_dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec30_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec30_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec30_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec30_dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec30_dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec30_dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec30_dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec30_dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313891,8 +4570,162 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec30_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec30_dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec30_dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec30_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec30_dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec30_dec30_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec30_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec31_dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec31_dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec31_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec31_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec31_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -313967,36 +4800,116 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \cr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 10 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 \full_cr$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 output 22 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 \full_cr$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 23 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \full_cr_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \full_cr_ok$next - attribute \src "libresoc.v:150327.7-150327.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \main_cr_a$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \main_cr_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec31_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec31_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec31_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec58_dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec58_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec58_dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec58_dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec58_dec58_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -314010,8 +4923,223 @@ module \pipe attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_cr_op__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec58_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec58_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec58_dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec58_dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec58_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec58_dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec58_dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec58_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec58_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec58_dec58_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec58_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec62_dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec62_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec62_dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \dec62_dec62_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -314025,12 +5153,39 @@ module \pipe attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \main_cr_op__fn_unit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_cr_op__insn$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec62_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec62_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec62_dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -314105,8 +5260,134 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec62_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec62_dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec62_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec62_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec62_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 \form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 7 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \in3_sel + attribute \src "libresoc.v:1192.7-1192.15" + wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -314181,12439 +5462,5590 @@ module \pipe attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_cr_op__insn_type$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \main_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 32 \main_full_cr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 15 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 14 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 21 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 8 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:150917$8401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$13 - connect \B \p_ready_o - connect \Y $and$libresoc.v:150917$8401_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 9 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 15 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 1 \raw_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 17 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:485" + cell $mux $ternary$libresoc.v:3249$237 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:3249$237_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3250.9-3276.4" + cell \dec19 \dec19 + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:3277.9-3303.4" + cell \dec30 \dec30 + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:150940.12-150961.4" - cell \main$9 \main - connect \cr_a \main_cr_a - connect \cr_a$6 \main_cr_a$12 - connect \cr_a_ok \main_cr_a_ok - connect \cr_b \main_cr_b - connect \cr_c \main_cr_c - connect \cr_op__fn_unit \main_cr_op__fn_unit - connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 - connect \cr_op__insn \main_cr_op__insn - connect \cr_op__insn$4 \main_cr_op__insn$10 - connect \cr_op__insn_type \main_cr_op__insn_type - connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 - connect \full_cr \main_full_cr - connect \full_cr$5 \main_full_cr$11 - connect \full_cr_ok \main_full_cr_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$7 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb + attribute \src "libresoc.v:3304.9-3330.4" + cell \dec31 \dec31 + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:150962.9-150965.4" - cell \n$8 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o + attribute \src "libresoc.v:3331.9-3357.4" + cell \dec58 \dec58 + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:150966.9-150969.4" - cell \p$7 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i + attribute \src "libresoc.v:3358.9-3384.4" + cell \dec62 \dec62 + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:150327.7-150327.20" - process $proc$libresoc.v:150327$8451 + attribute \src "libresoc.v:1192.7-1192.20" + process $proc$libresoc.v:1192$262 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:150340.13-150340.28" - process $proc$libresoc.v:150340$8452 - assign { } { } - assign $0\cr_a$6[3:0]$8453 4'0000 - sync always - sync init - update \cr_a$6 $0\cr_a$6[3:0]$8453 - end - attribute \src "libresoc.v:150345.7-150345.21" - process $proc$libresoc.v:150345$8454 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:150399.14-150399.42" - process $proc$libresoc.v:150399$8455 + attribute \src "libresoc.v:3385.3-3523.6" + process $proc$libresoc.v:3385$238 assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$8456 12'000000000000 - sync always - sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8456 - end - attribute \src "libresoc.v:150408.14-150408.37" - process $proc$libresoc.v:150408$8457 assign { } { } - assign $0\cr_op__insn$4[31:0]$8458 0 - sync always - sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8458 - end - attribute \src "libresoc.v:150639.13-150639.41" - process $proc$libresoc.v:150639$8459 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8460 7'0000000 + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:3386.5-3386.29" + switch \initial + attribute \src "libresoc.v:3386.9-3386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011100 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end sync always - sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8460 + update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:150648.14-150648.33" - process $proc$libresoc.v:150648$8461 + attribute \src "libresoc.v:3524.3-3665.6" + process $proc$libresoc.v:3524$239 assign { } { } - assign $0\full_cr$5[31:0]$8462 0 - sync always - sync init - update \full_cr$5 $0\full_cr$5[31:0]$8462 - end - attribute \src "libresoc.v:150653.7-150653.24" - process $proc$libresoc.v:150653$8463 assign { } { } - assign $1\full_cr_ok[0:0] 1'0 - sync always - sync init - update \full_cr_ok $1\full_cr_ok[0:0] - end - attribute \src "libresoc.v:150876.13-150876.29" - process $proc$libresoc.v:150876$8464 assign { } { } - assign $0\muxid$1[1:0]$8465 2'00 + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:3525.5-3525.29" + switch \initial + attribute \src "libresoc.v:3525.9-3525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8465 + update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:150889.14-150889.38" - process $proc$libresoc.v:150889$8466 + attribute \src "libresoc.v:3666.3-3807.6" + process $proc$libresoc.v:3666$240 assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:150896.7-150896.18" - process $proc$libresoc.v:150896$8467 assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:150910.7-150910.20" - process $proc$libresoc.v:150910$8468 assign { } { } - assign $1\r_busy[0:0] 1'0 + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:3667.5-3667.29" + switch \initial + attribute \src "libresoc.v:3667.9-3667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:150918.3-150919.31" - process $proc$libresoc.v:150918$8402 - assign { } { } - assign $0\cr_a$6[3:0]$8403 \cr_a$6$next - sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8403 - end - attribute \src "libresoc.v:150920.3-150921.31" - process $proc$libresoc.v:150920$8404 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:150922.3-150923.37" - process $proc$libresoc.v:150922$8405 - assign { } { } - assign $0\full_cr$5[31:0]$8406 \full_cr$5$next - sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8406 - end - attribute \src "libresoc.v:150924.3-150925.37" - process $proc$libresoc.v:150924$8407 - assign { } { } - assign $0\full_cr_ok[0:0] \full_cr_ok$next - sync posedge \coresync_clk - update \full_cr_ok $0\full_cr_ok[0:0] - end - attribute \src "libresoc.v:150926.3-150927.19" - process $proc$libresoc.v:150926$8408 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:150928.3-150929.25" - process $proc$libresoc.v:150928$8409 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:150930.3-150931.55" - process $proc$libresoc.v:150930$8410 - assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8411 \cr_op__insn_type$2$next - sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8411 - end - attribute \src "libresoc.v:150932.3-150933.51" - process $proc$libresoc.v:150932$8412 - assign { } { } - assign $0\cr_op__fn_unit$3[11:0]$8413 \cr_op__fn_unit$3$next - sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$8413 - end - attribute \src "libresoc.v:150934.3-150935.45" - process $proc$libresoc.v:150934$8414 - assign { } { } - assign $0\cr_op__insn$4[31:0]$8415 \cr_op__insn$4$next - sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8415 - end - attribute \src "libresoc.v:150936.3-150937.33" - process $proc$libresoc.v:150936$8416 - assign { } { } - assign $0\muxid$1[1:0]$8417 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8417 - end - attribute \src "libresoc.v:150938.3-150939.29" - process $proc$libresoc.v:150938$8418 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:150970.3-150987.6" - process $proc$libresoc.v:150970$8419 + attribute \src "libresoc.v:3808.3-3949.6" + process $proc$libresoc.v:3808$241 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8420 $2\r_busy$next[0:0]$8422 - attribute \src "libresoc.v:150971.5-150971.29" + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:3809.5-3809.29" switch \initial - attribute \src "libresoc.v:150971.9-150971.17" + attribute \src "libresoc.v:3809.9-3809.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } - assign $1\r_busy$next[0:0]$8421 1'1 + assign $2\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1610612736 assign { } { } - assign $1\r_busy$next[0:0]$8421 1'0 - case - assign $1\r_busy$next[0:0]$8421 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $2\in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000001---------------0000000011- assign { } { } - assign $2\r_busy$next[0:0]$8422 1'0 + assign $2\in3_sel[1:0] 2'00 case - assign $2\r_busy$next[0:0]$8422 $1\r_busy$next[0:0]$8421 + assign $2\in3_sel[1:0] $1\in3_sel[1:0] end sync always - update \r_busy$next $0\r_busy$next[0:0]$8420 + update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:150988.3-151000.6" - process $proc$libresoc.v:150988$8423 + attribute \src "libresoc.v:3950.3-4091.6" + process $proc$libresoc.v:3950$242 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8424 $1\muxid$1$next[1:0]$8425 - attribute \src "libresoc.v:150989.5-150989.29" + assign { } { } + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "libresoc.v:3951.5-3951.29" switch \initial - attribute \src "libresoc.v:150989.9-150989.17" + attribute \src "libresoc.v:3951.9-3951.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } - assign $1\muxid$1$next[1:0]$8425 \muxid$16 + assign $1\out_sel[1:0] \dec19_dec19_out_sel attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011110 assign { } { } - assign $1\muxid$1$next[1:0]$8425 \muxid$16 - case - assign $1\muxid$1$next[1:0]$8425 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8424 - end - attribute \src "libresoc.v:151001.3-151015.6" - process $proc$libresoc.v:151001$8426 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_op__fn_unit$3$next[11:0]$8427 $1\cr_op__fn_unit$3$next[11:0]$8430 - assign $0\cr_op__insn$4$next[31:0]$8428 $1\cr_op__insn$4$next[31:0]$8431 - assign $0\cr_op__insn_type$2$next[6:0]$8429 $1\cr_op__insn_type$2$next[6:0]$8432 - attribute \src "libresoc.v:151002.5-151002.29" - switch \initial - attribute \src "libresoc.v:151002.9-151002.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\out_sel[1:0] \dec30_dec30_out_sel attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'011111 assign { } { } + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8431 $1\cr_op__fn_unit$3$next[11:0]$8430 $1\cr_op__insn_type$2$next[6:0]$8432 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign $1\out_sel[1:0] \dec62_dec62_out_sel attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'001100 assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8431 $1\cr_op__fn_unit$3$next[11:0]$8430 $1\cr_op__insn_type$2$next[6:0]$8432 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } - case - assign $1\cr_op__fn_unit$3$next[11:0]$8430 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8431 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8432 \cr_op__insn_type$2 - end - sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$8427 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8428 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8429 - end - attribute \src "libresoc.v:151016.3-151034.6" - process $proc$libresoc.v:151016$8433 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8434 $1\o$next[63:0]$8436 - assign { } { } - assign $0\o_ok$next[0:0]$8435 $2\o_ok$next[0:0]$8438 - attribute \src "libresoc.v:151017.5-151017.29" - switch \initial - attribute \src "libresoc.v:151017.9-151017.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'001111 assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign { $1\o_ok$next[0:0]$8437 $1\o$next[63:0]$8436 } { \o_ok$21 \o$20 } + assign $1\out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011100 assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign { $1\o_ok$next[0:0]$8437 $1\o$next[63:0]$8436 } { \o_ok$21 \o$20 } - case - assign $1\o$next[63:0]$8436 \o - assign $1\o_ok$next[0:0]$8437 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\out_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'010010 assign { } { } - assign $2\o_ok$next[0:0]$8438 1'0 - case - assign $2\o_ok$next[0:0]$8438 $1\o_ok$next[0:0]$8437 - end - sync always - update \o$next $0\o$next[63:0]$8434 - update \o_ok$next $0\o_ok$next[0:0]$8435 - end - attribute \src "libresoc.v:151035.3-151053.6" - process $proc$libresoc.v:151035$8439 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\full_cr$5$next[31:0]$8440 $1\full_cr$5$next[31:0]$8442 - assign { } { } - assign $0\full_cr_ok$next[0:0]$8441 $2\full_cr_ok$next[0:0]$8444 - attribute \src "libresoc.v:151036.5-151036.29" - switch \initial - attribute \src "libresoc.v:151036.9-151036.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010000 assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign { $1\full_cr_ok$next[0:0]$8443 $1\full_cr$5$next[31:0]$8442 } { \full_cr_ok$23 \full_cr$22 } + assign $1\out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'001010 assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign { $1\full_cr_ok$next[0:0]$8443 $1\full_cr$5$next[31:0]$8442 } { \full_cr_ok$23 \full_cr$22 } - case - assign $1\full_cr$5$next[31:0]$8442 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8443 \full_cr_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100011 assign { } { } - assign $2\full_cr_ok$next[0:0]$8444 1'0 - case - assign $2\full_cr_ok$next[0:0]$8444 $1\full_cr_ok$next[0:0]$8443 - end - sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8440 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8441 - end - attribute \src "libresoc.v:151054.3-151072.6" - process $proc$libresoc.v:151054$8445 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$6$next[3:0]$8447 $1\cr_a$6$next[3:0]$8449 - assign $0\cr_a_ok$next[0:0]$8446 $2\cr_a_ok$next[0:0]$8450 - attribute \src "libresoc.v:151055.5-151055.29" - switch \initial - attribute \src "libresoc.v:151055.9-151055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign { $1\cr_a_ok$next[0:0]$8448 $1\cr_a$6$next[3:0]$8449 } { \cr_a_ok$25 \cr_a$24 } + assign $1\out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign { $1\cr_a_ok$next[0:0]$8448 $1\cr_a$6$next[3:0]$8449 } { \cr_a_ok$25 \cr_a$24 } + assign $1\out_sel[1:0] 2'10 case - assign $1\cr_a_ok$next[0:0]$8448 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8449 \cr_a$6 + assign $1\out_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $2\cr_a_ok$next[0:0]$8450 1'0 + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 case - assign $2\cr_a_ok$next[0:0]$8450 $1\cr_a_ok$next[0:0]$8448 + assign $2\out_sel[1:0] $1\out_sel[1:0] end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8446 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8447 - end - connect \$14 $and$libresoc.v:150917$8401_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } - connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } - connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } - connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } - connect \muxid$16 \main_muxid$7 - connect \p_valid_i_p_ready_o \$14 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$13 \p_valid_i - connect \main_cr_c \cr_c - connect \main_cr_b \cr_b - connect \main_cr_a \cr_a - connect \main_full_cr \full_cr - connect \main_rb \rb - connect \main_ra \ra - connect { \main_cr_op__insn \main_cr_op__fn_unit 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 17 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 16 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 31 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \nia_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:151739$8469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 - connect \B \p_ready_o - connect \Y $and$libresoc.v:151739$8469_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:151772.13-151800.4" - cell \main$22 \main - connect \br_op__cia \main_br_op__cia - connect \br_op__cia$2 \main_br_op__cia$13 - connect \br_op__fn_unit \main_br_op__fn_unit - connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 - connect \br_op__imm_data__data \main_br_op__imm_data__data - connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 - connect \br_op__imm_data__ok \main_br_op__imm_data__ok - connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 - connect \br_op__insn \main_br_op__insn - connect \br_op__insn$5 \main_br_op__insn$16 - connect \br_op__insn_type \main_br_op__insn_type - connect \br_op__insn_type$3 \main_br_op__insn_type$14 - connect \br_op__is_32bit \main_br_op__is_32bit - connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 - connect \br_op__lk \main_br_op__lk - connect \br_op__lk$8 \main_br_op__lk$19 - connect \cr_a \main_cr_a - connect \fast1 \main_fast1 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2 \main_fast2 - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$12 - connect \nia \main_nia - connect \nia_ok \main_nia_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:151801.10-151804.4" - cell \n$21 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:151805.10-151808.4" - cell \p$20 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:151096.7-151096.20" - process $proc$libresoc.v:151096$8541 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:151103.14-151103.51" - process $proc$libresoc.v:151103$8542 - assign { } { } - assign $0\br_op__cia$2[63:0]$8543 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8543 - end - attribute \src "libresoc.v:151153.14-151153.42" - process $proc$libresoc.v:151153$8544 - assign { } { } - assign $0\br_op__fn_unit$4[11:0]$8545 12'000000000000 - sync always - sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8545 - end - attribute \src "libresoc.v:151162.14-151162.62" - process $proc$libresoc.v:151162$8546 - assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8547 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8547 - end - attribute \src "libresoc.v:151171.7-151171.37" - process $proc$libresoc.v:151171$8548 - assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8549 1'0 - sync always - sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8549 - end - attribute \src "libresoc.v:151180.14-151180.37" - process $proc$libresoc.v:151180$8550 - assign { } { } - assign $0\br_op__insn$5[31:0]$8551 0 - sync always - sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8551 - end - attribute \src "libresoc.v:151411.13-151411.41" - process $proc$libresoc.v:151411$8552 - assign { } { } - assign $0\br_op__insn_type$3[6:0]$8553 7'0000000 - sync always - sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8553 - end - attribute \src "libresoc.v:151420.7-151420.33" - process $proc$libresoc.v:151420$8554 - assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8555 1'0 - sync always - sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8555 - end - attribute \src "libresoc.v:151429.7-151429.27" - process $proc$libresoc.v:151429$8556 - assign { } { } - assign $0\br_op__lk$8[0:0]$8557 1'0 - sync always - sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8557 - end - attribute \src "libresoc.v:151442.14-151442.47" - process $proc$libresoc.v:151442$8558 - assign { } { } - assign $0\fast1$10[63:0]$8559 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$10 $0\fast1$10[63:0]$8559 - end - attribute \src "libresoc.v:151449.7-151449.22" - process $proc$libresoc.v:151449$8560 - assign { } { } - assign $1\fast1_ok[0:0] 1'0 - sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] - end - attribute \src "libresoc.v:151458.14-151458.47" - process $proc$libresoc.v:151458$8561 - assign { } { } - assign $0\fast2$11[63:0]$8562 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast2$11 $0\fast2$11[63:0]$8562 - end - attribute \src "libresoc.v:151465.7-151465.22" - process $proc$libresoc.v:151465$8563 - assign { } { } - assign $1\fast2_ok[0:0] 1'0 - sync always - sync init - update \fast2_ok $1\fast2_ok[0:0] - end - attribute \src "libresoc.v:151702.13-151702.29" - process $proc$libresoc.v:151702$8564 - assign { } { } - assign $0\muxid$1[1:0]$8565 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8565 - end - attribute \src "libresoc.v:151715.14-151715.40" - process $proc$libresoc.v:151715$8566 - assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \nia $1\nia[63:0] - end - attribute \src "libresoc.v:151722.7-151722.20" - process $proc$libresoc.v:151722$8567 - assign { } { } - assign $1\nia_ok[0:0] 1'0 - sync always - sync init - update \nia_ok $1\nia_ok[0:0] - end - attribute \src "libresoc.v:151736.7-151736.20" - process $proc$libresoc.v:151736$8568 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:151740.3-151741.23" - process $proc$libresoc.v:151740$8470 - assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] - end - attribute \src "libresoc.v:151742.3-151743.29" - process $proc$libresoc.v:151742$8471 - assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next - sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] - end - attribute \src "libresoc.v:151744.3-151745.35" - process $proc$libresoc.v:151744$8472 - assign { } { } - assign $0\fast2$11[63:0]$8473 \fast2$11$next - sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8473 - end - attribute \src "libresoc.v:151746.3-151747.33" - process $proc$libresoc.v:151746$8474 - assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next - sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "libresoc.v:151748.3-151749.35" - process $proc$libresoc.v:151748$8475 - assign { } { } - assign $0\fast1$10[63:0]$8476 \fast1$10$next - sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8476 - end - attribute \src "libresoc.v:151750.3-151751.33" - process $proc$libresoc.v:151750$8477 - assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "libresoc.v:151752.3-151753.43" - process $proc$libresoc.v:151752$8478 - assign { } { } - assign $0\br_op__cia$2[63:0]$8479 \br_op__cia$2$next - sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8479 - end - attribute \src "libresoc.v:151754.3-151755.55" - process $proc$libresoc.v:151754$8480 - assign { } { } - assign $0\br_op__insn_type$3[6:0]$8481 \br_op__insn_type$3$next - sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8481 - end - attribute \src "libresoc.v:151756.3-151757.51" - process $proc$libresoc.v:151756$8482 - assign { } { } - assign $0\br_op__fn_unit$4[11:0]$8483 \br_op__fn_unit$4$next - sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$8483 - end - attribute \src "libresoc.v:151758.3-151759.45" - process $proc$libresoc.v:151758$8484 - assign { } { } - assign $0\br_op__insn$5[31:0]$8485 \br_op__insn$5$next - sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8485 - end - attribute \src "libresoc.v:151760.3-151761.65" - process $proc$libresoc.v:151760$8486 - assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8487 \br_op__imm_data__data$6$next - sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8487 - end - attribute \src "libresoc.v:151762.3-151763.61" - process $proc$libresoc.v:151762$8488 - assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8489 \br_op__imm_data__ok$7$next - sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8489 - end - attribute \src "libresoc.v:151764.3-151765.41" - process $proc$libresoc.v:151764$8490 - assign { } { } - assign $0\br_op__lk$8[0:0]$8491 \br_op__lk$8$next - sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8491 - end - attribute \src "libresoc.v:151766.3-151767.53" - process $proc$libresoc.v:151766$8492 - assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8493 \br_op__is_32bit$9$next - sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8493 - end - attribute \src "libresoc.v:151768.3-151769.33" - process $proc$libresoc.v:151768$8494 - assign { } { } - assign $0\muxid$1[1:0]$8495 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8495 - end - attribute \src "libresoc.v:151770.3-151771.29" - process $proc$libresoc.v:151770$8496 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + update \out_sel $0\out_sel[1:0] end - attribute \src "libresoc.v:151809.3-151826.6" - process $proc$libresoc.v:151809$8497 + attribute \src "libresoc.v:4092.3-4233.6" + process $proc$libresoc.v:4092$243 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8498 $2\r_busy$next[0:0]$8500 - attribute \src "libresoc.v:151810.5-151810.29" + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:4093.5-4093.29" switch \initial - attribute \src "libresoc.v:151810.9-151810.17" + attribute \src "libresoc.v:4093.9-4093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } - assign $1\r_busy$next[0:0]$8499 1'1 + assign $1\cr_in[2:0] \dec19_dec19_cr_in attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011110 assign { } { } - assign $1\r_busy$next[0:0]$8499 1'0 - case - assign $1\r_busy$next[0:0]$8499 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\cr_in[2:0] \dec30_dec30_cr_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'011111 assign { } { } - assign $2\r_busy$next[0:0]$8500 1'0 - case - assign $2\r_busy$next[0:0]$8500 $1\r_busy$next[0:0]$8499 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8498 - end - attribute \src "libresoc.v:151827.3-151839.6" - process $proc$libresoc.v:151827$8501 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8502 $1\muxid$1$next[1:0]$8503 - attribute \src "libresoc.v:151828.5-151828.29" - switch \initial - attribute \src "libresoc.v:151828.9-151828.17" - case 1'1 + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 case + assign $1\cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 1610612736 assign { } { } - assign $1\muxid$1$next[1:0]$8503 \muxid$26 + assign $2\cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 32'000001---------------0000000011- assign { } { } - assign $1\muxid$1$next[1:0]$8503 \muxid$26 + assign $2\cr_in[2:0] 3'000 case - assign $1\muxid$1$next[1:0]$8503 \muxid$1 + assign $2\cr_in[2:0] $1\cr_in[2:0] end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8502 + update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:151840.3-151867.6" - process $proc$libresoc.v:151840$8504 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:4234.3-4375.6" + process $proc$libresoc.v:4234$244 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\br_op__cia$2$next[63:0]$8505 $1\br_op__cia$2$next[63:0]$8513 - assign $0\br_op__fn_unit$4$next[11:0]$8506 $1\br_op__fn_unit$4$next[11:0]$8514 - assign { } { } - assign { } { } - assign $0\br_op__insn$5$next[31:0]$8509 $1\br_op__insn$5$next[31:0]$8517 - assign $0\br_op__insn_type$3$next[6:0]$8510 $1\br_op__insn_type$3$next[6:0]$8518 - assign $0\br_op__is_32bit$9$next[0:0]$8511 $1\br_op__is_32bit$9$next[0:0]$8519 - assign $0\br_op__lk$8$next[0:0]$8512 $1\br_op__lk$8$next[0:0]$8520 - assign $0\br_op__imm_data__data$6$next[63:0]$8507 $2\br_op__imm_data__data$6$next[63:0]$8521 - assign $0\br_op__imm_data__ok$7$next[0:0]$8508 $2\br_op__imm_data__ok$7$next[0:0]$8522 - attribute \src "libresoc.v:151841.5-151841.29" + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:4235.5-4235.29" switch \initial - attribute \src "libresoc.v:151841.9-151841.17" + attribute \src "libresoc.v:4235.9-4235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8519 $1\br_op__lk$8$next[0:0]$8520 $1\br_op__imm_data__ok$7$next[0:0]$8516 $1\br_op__imm_data__data$6$next[63:0]$8515 $1\br_op__insn$5$next[31:0]$8517 $1\br_op__fn_unit$4$next[11:0]$8514 $1\br_op__insn_type$3$next[6:0]$8518 $1\br_op__cia$2$next[63:0]$8513 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'001111 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8519 $1\br_op__lk$8$next[0:0]$8520 $1\br_op__imm_data__ok$7$next[0:0]$8516 $1\br_op__imm_data__data$6$next[63:0]$8515 $1\br_op__insn$5$next[31:0]$8517 $1\br_op__fn_unit$4$next[11:0]$8514 $1\br_op__insn_type$3$next[6:0]$8518 $1\br_op__cia$2$next[63:0]$8513 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } - case - assign $1\br_op__cia$2$next[63:0]$8513 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[11:0]$8514 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8515 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8516 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8517 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8518 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8519 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8520 \br_op__lk$8 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\cr_out[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100010 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8521 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8522 1'0 - case - assign $2\br_op__imm_data__data$6$next[63:0]$8521 $1\br_op__imm_data__data$6$next[63:0]$8515 - assign $2\br_op__imm_data__ok$7$next[0:0]$8522 $1\br_op__imm_data__ok$7$next[0:0]$8516 - end - sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8505 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$8506 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8507 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8508 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8509 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8510 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8511 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8512 - end - attribute \src "libresoc.v:151868.3-151886.6" - process $proc$libresoc.v:151868$8523 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$10$next[63:0]$8524 $1\fast1$10$next[63:0]$8526 - assign { } { } - assign $0\fast1_ok$next[0:0]$8525 $2\fast1_ok$next[0:0]$8528 - attribute \src "libresoc.v:151869.5-151869.29" - switch \initial - attribute \src "libresoc.v:151869.9-151869.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'101010 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign { $1\fast1_ok$next[0:0]$8527 $1\fast1$10$next[63:0]$8526 } { \fast1_ok$36 \fast1$35 } + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101000 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } - assign { $1\fast1_ok$next[0:0]$8527 $1\fast1$10$next[63:0]$8526 } { \fast1_ok$36 \fast1$35 } - case - assign $1\fast1$10$next[63:0]$8526 \fast1$10 - assign $1\fast1_ok$next[0:0]$8527 \fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100000 assign { } { } - assign $2\fast1_ok$next[0:0]$8528 1'0 - case - assign $2\fast1_ok$next[0:0]$8528 $1\fast1_ok$next[0:0]$8527 - end - sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8524 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8525 - end - attribute \src "libresoc.v:151887.3-151905.6" - process $proc$libresoc.v:151887$8529 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast2$11$next[63:0]$8530 $1\fast2$11$next[63:0]$8532 - assign { } { } - assign $0\fast2_ok$next[0:0]$8531 $2\fast2_ok$next[0:0]$8534 - attribute \src "libresoc.v:151888.5-151888.29" - switch \initial - attribute \src "libresoc.v:151888.9-151888.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'100001 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign { $1\fast2_ok$next[0:0]$8533 $1\fast2$11$next[63:0]$8532 } { \fast2_ok$38 \fast2$37 } + assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011000 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } - assign { $1\fast2_ok$next[0:0]$8533 $1\fast2$11$next[63:0]$8532 } { \fast2_ok$38 \fast2$37 } - case - assign $1\fast2$11$next[63:0]$8532 \fast2$11 - assign $1\fast2_ok$next[0:0]$8533 \fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'010100 assign { } { } - assign $2\fast2_ok$next[0:0]$8534 1'0 - case - assign $2\fast2_ok$next[0:0]$8534 $1\fast2_ok$next[0:0]$8533 - end - sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8530 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8531 - end - attribute \src "libresoc.v:151906.3-151924.6" - process $proc$libresoc.v:151906$8535 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\nia$next[63:0]$8536 $1\nia$next[63:0]$8538 - assign { } { } - assign $0\nia_ok$next[0:0]$8537 $2\nia_ok$next[0:0]$8540 - attribute \src "libresoc.v:151907.5-151907.29" - switch \initial - attribute \src "libresoc.v:151907.9-151907.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010101 assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign { $1\nia_ok$next[0:0]$8539 $1\nia$next[63:0]$8538 } { \nia_ok$40 \nia$39 } + assign $1\cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'100110 assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } - assign { $1\nia_ok$next[0:0]$8539 $1\nia$next[63:0]$8538 } { \nia_ok$40 \nia$39 } - case - assign $1\nia$next[63:0]$8538 \nia - assign $1\nia_ok$next[0:0]$8539 \nia_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'101100 assign { } { } - assign $2\nia_ok$next[0:0]$8540 1'0 - case - assign $2\nia_ok$next[0:0]$8540 $1\nia_ok$next[0:0]$8539 - end - sync always - update \nia$next $0\nia$next[63:0]$8536 - update \nia_ok$next $0\nia_ok$next[0:0]$8537 - end - connect \$24 $and$libresoc.v:151739$8469_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } - connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } - connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } - connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } - connect \muxid$26 \main_muxid$12 - connect \p_valid_i_p_ready_o \$24 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$23 \p_valid_i - connect \main_cr_a \cr_a - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - connect \main_muxid \muxid -end -attribute \src "libresoc.v:151944.1-152859.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" -attribute \generator "nMigen" -module \pipe$64 - attribute \src "libresoc.v:152762.3-152780.6" - wire width 64 $0\fast1$7$next[63:0]$8628 - attribute \src "libresoc.v:152615.3-152616.33" - wire width 64 $0\fast1$7[63:0]$8580 - attribute \src "libresoc.v:151958.14-151958.46" - wire width 64 $0\fast1$7[63:0]$8652 - attribute \src "libresoc.v:152762.3-152780.6" - wire $0\fast1_ok$next[0:0]$8627 - attribute \src "libresoc.v:152617.3-152618.33" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:151945.7-151945.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:152695.3-152707.6" - wire width 2 $0\muxid$1$next[1:0]$8603 - attribute \src "libresoc.v:152635.3-152636.33" - wire width 2 $0\muxid$1[1:0]$8596 - attribute \src "libresoc.v:151972.13-151972.29" - wire width 2 $0\muxid$1[1:0]$8655 - attribute \src "libresoc.v:152724.3-152742.6" - wire width 64 $0\o$next[63:0]$8615 - attribute \src "libresoc.v:152623.3-152624.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:152724.3-152742.6" - wire $0\o_ok$next[0:0]$8616 - attribute \src "libresoc.v:152625.3-152626.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:152677.3-152694.6" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:152602$8569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$21 - connect \B \p_ready_o - connect \Y $and$libresoc.v:152602$8569_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:152639.10-152642.4" - cell \n$66 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:152643.10-152646.4" - cell \p$65 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:152647.12-152676.4" - cell \spr_main \spr_main - connect \fast1 \spr_main_fast1 - connect \fast1$7 \spr_main_fast1$17 - connect \fast1_ok \spr_main_fast1_ok - connect \muxid \spr_main_muxid - connect \muxid$1 \spr_main_muxid$11 - connect \o \spr_main_o - connect \o_ok \spr_main_o_ok - connect \ra \spr_main_ra - connect \spr1 \spr_main_spr1 - connect \spr1$6 \spr_main_spr1$16 - connect \spr1_ok \spr_main_spr1_ok - connect \spr_op__fn_unit \spr_main_spr_op__fn_unit - connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 - connect \spr_op__insn \spr_main_spr_op__insn - connect \spr_op__insn$4 \spr_main_spr_op__insn$14 - connect \spr_op__insn_type \spr_main_spr_op__insn_type - connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 - connect \spr_op__is_32bit \spr_main_spr_op__is_32bit - connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 - connect \xer_ca \spr_main_xer_ca - connect \xer_ca$10 \spr_main_xer_ca$20 - connect \xer_ca_ok \spr_main_xer_ca_ok - connect \xer_ov \spr_main_xer_ov - connect \xer_ov$9 \spr_main_xer_ov$19 - connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_so \spr_main_xer_so - connect \xer_so$8 \spr_main_xer_so$18 - connect \xer_so_ok \spr_main_xer_so_ok - end - attribute \src "libresoc.v:151945.7-151945.20" - process $proc$libresoc.v:151945$8650 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:151958.14-151958.46" - process $proc$libresoc.v:151958$8651 - assign { } { } - assign $0\fast1$7[63:0]$8652 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1$7 $0\fast1$7[63:0]$8652 - end - attribute \src "libresoc.v:151963.7-151963.22" - process $proc$libresoc.v:151963$8653 - assign { } { } - assign $1\fast1_ok[0:0] 1'0 - sync always - sync init - update \fast1_ok $1\fast1_ok[0:0] - end - attribute \src "libresoc.v:151972.13-151972.29" - process $proc$libresoc.v:151972$8654 - assign { } { } - assign $0\muxid$1[1:0]$8655 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$8655 - end - attribute \src "libresoc.v:151985.14-151985.38" - process $proc$libresoc.v:151985$8656 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:151992.7-151992.18" - process $proc$libresoc.v:151992$8657 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:152006.7-152006.20" - process $proc$libresoc.v:152006$8658 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:152017.14-152017.45" - process $proc$libresoc.v:152017$8659 - assign { } { } - assign $0\spr1$6[63:0]$8660 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \spr1$6 $0\spr1$6[63:0]$8660 - end - attribute \src "libresoc.v:152022.7-152022.21" - process $proc$libresoc.v:152022$8661 - assign { } { } - assign $1\spr1_ok[0:0] 1'0 - sync always - sync init - update \spr1_ok $1\spr1_ok[0:0] - end - attribute \src "libresoc.v:152302.14-152302.43" - process $proc$libresoc.v:152302$8662 - assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$8663 12'000000000000 - sync always - sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8663 - end - attribute \src "libresoc.v:152311.14-152311.38" - process $proc$libresoc.v:152311$8664 - assign { } { } - assign $0\spr_op__insn$4[31:0]$8665 0 - sync always - sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8665 - end - attribute \src "libresoc.v:152466.13-152466.42" - process $proc$libresoc.v:152466$8666 - assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8667 7'0000000 - sync always - sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8667 - end - attribute \src "libresoc.v:152551.7-152551.34" - process $proc$libresoc.v:152551$8668 - assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8669 1'0 - sync always - sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8669 - end - attribute \src "libresoc.v:152558.13-152558.31" - process $proc$libresoc.v:152558$8670 - assign { } { } - assign $0\xer_ca$10[1:0]$8671 2'00 - sync always - sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$8671 - end - attribute \src "libresoc.v:152565.7-152565.23" - process $proc$libresoc.v:152565$8672 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:152576.13-152576.30" - process $proc$libresoc.v:152576$8673 - assign { } { } - assign $0\xer_ov$9[1:0]$8674 2'00 - sync always - sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$8674 - end - attribute \src "libresoc.v:152581.7-152581.23" - process $proc$libresoc.v:152581$8675 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:152592.7-152592.24" - process $proc$libresoc.v:152592$8676 - assign { } { } - assign $0\xer_so$8[0:0]$8677 1'0 - sync always - sync init - update \xer_so$8 $0\xer_so$8[0:0]$8677 - end - attribute \src "libresoc.v:152597.7-152597.23" - process $proc$libresoc.v:152597$8678 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:152603.3-152604.37" - process $proc$libresoc.v:152603$8570 - assign { } { } - assign $0\xer_ca$10[1:0]$8571 \xer_ca$10$next - sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8571 - end - attribute \src "libresoc.v:152605.3-152606.35" - process $proc$libresoc.v:152605$8572 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:152607.3-152608.35" - process $proc$libresoc.v:152607$8573 - assign { } { } - assign $0\xer_ov$9[1:0]$8574 \xer_ov$9$next - sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8574 - end - attribute \src "libresoc.v:152609.3-152610.35" - process $proc$libresoc.v:152609$8575 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:152611.3-152612.35" - process $proc$libresoc.v:152611$8576 - assign { } { } - assign $0\xer_so$8[0:0]$8577 \xer_so$8$next - sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8577 - end - attribute \src "libresoc.v:152613.3-152614.35" - process $proc$libresoc.v:152613$8578 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:152615.3-152616.33" - process $proc$libresoc.v:152615$8579 - assign { } { } - assign $0\fast1$7[63:0]$8580 \fast1$7$next - sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8580 - end - attribute \src "libresoc.v:152617.3-152618.33" - process $proc$libresoc.v:152617$8581 - assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "libresoc.v:152619.3-152620.31" - process $proc$libresoc.v:152619$8582 - assign { } { } - assign $0\spr1$6[63:0]$8583 \spr1$6$next - sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8583 - end - attribute \src "libresoc.v:152621.3-152622.31" - process $proc$libresoc.v:152621$8584 - assign { } { } - assign $0\spr1_ok[0:0] \spr1_ok$next - sync posedge \coresync_clk - update \spr1_ok $0\spr1_ok[0:0] - end - attribute \src "libresoc.v:152623.3-152624.19" - process $proc$libresoc.v:152623$8585 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:152625.3-152626.25" - process $proc$libresoc.v:152625$8586 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:152627.3-152628.57" - process $proc$libresoc.v:152627$8587 - assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8588 \spr_op__insn_type$2$next - sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8588 - end - attribute \src "libresoc.v:152629.3-152630.53" - process $proc$libresoc.v:152629$8589 - assign { } { } - assign $0\spr_op__fn_unit$3[11:0]$8590 \spr_op__fn_unit$3$next - sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8590 - end - attribute \src "libresoc.v:152631.3-152632.47" - process $proc$libresoc.v:152631$8591 - assign { } { } - assign $0\spr_op__insn$4[31:0]$8592 \spr_op__insn$4$next - sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8592 - end - attribute \src "libresoc.v:152633.3-152634.55" - process $proc$libresoc.v:152633$8593 - assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8594 \spr_op__is_32bit$5$next - sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8594 - end - attribute \src "libresoc.v:152635.3-152636.33" - process $proc$libresoc.v:152635$8595 - assign { } { } - assign $0\muxid$1[1:0]$8596 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8596 - end - attribute \src "libresoc.v:152637.3-152638.29" - process $proc$libresoc.v:152637$8597 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:152677.3-152694.6" - process $proc$libresoc.v:152677$8598 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8599 $2\r_busy$next[0:0]$8601 - attribute \src "libresoc.v:152678.5-152678.29" - switch \initial - attribute \src "libresoc.v:152678.9-152678.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'101101 assign { } { } - assign $1\r_busy$next[0:0]$8600 1'1 + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'100100 assign { } { } - assign $1\r_busy$next[0:0]$8600 1'0 - case - assign $1\r_busy$next[0:0]$8600 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100101 assign { } { } - assign $2\r_busy$next[0:0]$8601 1'0 - case - assign $2\r_busy$next[0:0]$8601 $1\r_busy$next[0:0]$8600 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8599 - end - attribute \src "libresoc.v:152695.3-152707.6" - process $proc$libresoc.v:152695$8602 - assign { } { } - assign { } { } - assign $0\muxid$1$next[1:0]$8603 $1\muxid$1$next[1:0]$8604 - attribute \src "libresoc.v:152696.5-152696.29" - switch \initial - attribute \src "libresoc.v:152696.9-152696.17" - case 1'1 + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 case + assign $1\cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\muxid$1$next[1:0]$8604 \muxid$24 + assign $2\cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 32'000001---------------0000000011- assign { } { } - assign $1\muxid$1$next[1:0]$8604 \muxid$24 + assign $2\cr_out[2:0] 3'000 case - assign $1\muxid$1$next[1:0]$8604 \muxid$1 + assign $2\cr_out[2:0] $1\cr_out[2:0] end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8603 + update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:152708.3-152723.6" - process $proc$libresoc.v:152708$8605 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:4376.3-4517.6" + process $proc$libresoc.v:4376$245 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\spr_op__fn_unit$3$next[11:0]$8606 $1\spr_op__fn_unit$3$next[11:0]$8610 - assign $0\spr_op__insn$4$next[31:0]$8607 $1\spr_op__insn$4$next[31:0]$8611 - assign $0\spr_op__insn_type$2$next[6:0]$8608 $1\spr_op__insn_type$2$next[6:0]$8612 - assign $0\spr_op__is_32bit$5$next[0:0]$8609 $1\spr_op__is_32bit$5$next[0:0]$8613 - attribute \src "libresoc.v:152709.5-152709.29" + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:4377.5-4377.29" switch \initial - attribute \src "libresoc.v:152709.9-152709.17" + attribute \src "libresoc.v:4377.9-4377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8613 $1\spr_op__insn$4$next[31:0]$8611 $1\spr_op__fn_unit$3$next[11:0]$8610 $1\spr_op__insn_type$2$next[6:0]$8612 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'111110 assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8613 $1\spr_op__insn$4$next[31:0]$8611 $1\spr_op__fn_unit$3$next[11:0]$8610 $1\spr_op__insn_type$2$next[6:0]$8612 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } - case - assign $1\spr_op__fn_unit$3$next[11:0]$8610 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8611 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8612 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8613 \spr_op__is_32bit$5 - end - sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$8606 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8607 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8608 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8609 - end - attribute \src "libresoc.v:152724.3-152742.6" - process $proc$libresoc.v:152724$8614 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8615 $1\o$next[63:0]$8617 - assign { } { } - assign $0\o_ok$next[0:0]$8616 $2\o_ok$next[0:0]$8619 - attribute \src "libresoc.v:152725.5-152725.29" - switch \initial - attribute \src "libresoc.v:152725.9-152725.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'001111 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign { $1\o_ok$next[0:0]$8618 $1\o$next[63:0]$8617 } { \o_ok$30 \o$29 } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011100 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } - assign { $1\o_ok$next[0:0]$8618 $1\o$next[63:0]$8617 } { \o_ok$30 \o$29 } - case - assign $1\o$next[63:0]$8617 \o - assign $1\o_ok$next[0:0]$8618 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'010010 assign { } { } - assign $2\o_ok$next[0:0]$8619 1'0 - case - assign $2\o_ok$next[0:0]$8619 $1\o_ok$next[0:0]$8618 - end - sync always - update \o$next $0\o$next[63:0]$8615 - update \o_ok$next $0\o_ok$next[0:0]$8616 - end - attribute \src "libresoc.v:152743.3-152761.6" - process $proc$libresoc.v:152743$8620 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\spr1$6$next[63:0]$8621 $1\spr1$6$next[63:0]$8623 - assign { } { } - assign $0\spr1_ok$next[0:0]$8622 $2\spr1_ok$next[0:0]$8625 - attribute \src "libresoc.v:152744.5-152744.29" - switch \initial - attribute \src "libresoc.v:152744.9-152744.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010000 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign { $1\spr1_ok$next[0:0]$8624 $1\spr1$6$next[63:0]$8623 } { \spr1_ok$32 \spr1$31 } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'001010 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } - assign { $1\spr1_ok$next[0:0]$8624 $1\spr1$6$next[63:0]$8623 } { \spr1_ok$32 \spr1$31 } - case - assign $1\spr1$6$next[63:0]$8623 \spr1$6 - assign $1\spr1_ok$next[0:0]$8624 \spr1_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100011 assign { } { } - assign $2\spr1_ok$next[0:0]$8625 1'0 - case - assign $2\spr1_ok$next[0:0]$8625 $1\spr1_ok$next[0:0]$8624 - end - sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8621 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8622 - end - attribute \src "libresoc.v:152762.3-152780.6" - process $proc$libresoc.v:152762$8626 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$7$next[63:0]$8628 $1\fast1$7$next[63:0]$8630 - assign $0\fast1_ok$next[0:0]$8627 $2\fast1_ok$next[0:0]$8631 - attribute \src "libresoc.v:152763.5-152763.29" - switch \initial - attribute \src "libresoc.v:152763.9-152763.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'101010 assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } - assign { $1\fast1_ok$next[0:0]$8629 $1\fast1$7$next[63:0]$8630 } { \fast1_ok$34 \fast1$33 } + assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign { $1\fast1_ok$next[0:0]$8629 $1\fast1$7$next[63:0]$8630 } { \fast1_ok$34 \fast1$33 } - case - assign $1\fast1_ok$next[0:0]$8629 \fast1_ok - assign $1\fast1$7$next[63:0]$8630 \fast1$7 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'011000 assign { } { } - assign $2\fast1_ok$next[0:0]$8631 1'0 - case - assign $2\fast1_ok$next[0:0]$8631 $1\fast1_ok$next[0:0]$8629 - end - sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8627 - update \fast1$7$next $0\fast1$7$next[63:0]$8628 - end - attribute \src "libresoc.v:152781.3-152799.6" - process $proc$libresoc.v:152781$8632 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$8$next[0:0]$8634 $1\xer_so$8$next[0:0]$8636 - assign $0\xer_so_ok$next[0:0]$8633 $2\xer_so_ok$next[0:0]$8637 - attribute \src "libresoc.v:152782.5-152782.29" - switch \initial - attribute \src "libresoc.v:152782.9-152782.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'011001 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8635 $1\xer_so$8$next[0:0]$8636 } { \xer_so_ok$36 \xer_so$35 } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'010101 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8635 $1\xer_so$8$next[0:0]$8636 } { \xer_so_ok$36 \xer_so$35 } - case - assign $1\xer_so_ok$next[0:0]$8635 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8636 \xer_so$8 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100110 assign { } { } - assign $2\xer_so_ok$next[0:0]$8637 1'0 - case - assign $2\xer_so_ok$next[0:0]$8637 $1\xer_so_ok$next[0:0]$8635 - end - sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8633 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8634 - end - attribute \src "libresoc.v:152800.3-152818.6" - process $proc$libresoc.v:152800$8638 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$9$next[1:0]$8640 $1\xer_ov$9$next[1:0]$8642 - assign $0\xer_ov_ok$next[0:0]$8639 $2\xer_ov_ok$next[0:0]$8643 - attribute \src "libresoc.v:152801.5-152801.29" - switch \initial - attribute \src "libresoc.v:152801.9-152801.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'100111 assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8641 $1\xer_ov$9$next[1:0]$8642 } { \xer_ov_ok$38 \xer_ov$37 } + assign $1\ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101101 assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8641 $1\xer_ov$9$next[1:0]$8642 } { \xer_ov_ok$38 \xer_ov$37 } - case - assign $1\xer_ov_ok$next[0:0]$8641 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8642 \xer_ov$9 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100101 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8643 1'0 - case - assign $2\xer_ov_ok$next[0:0]$8643 $1\xer_ov_ok$next[0:0]$8641 - end - sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8639 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8640 - end - attribute \src "libresoc.v:152819.3-152837.6" - process $proc$libresoc.v:152819$8644 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$10$next[1:0]$8645 $1\xer_ca$10$next[1:0]$8647 - assign { } { } - assign $0\xer_ca_ok$next[0:0]$8646 $2\xer_ca_ok$next[0:0]$8649 - attribute \src "libresoc.v:152820.5-152820.29" - switch \initial - attribute \src "libresoc.v:152820.9-152820.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\ldst_len[3:0] 4'0100 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'001000 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8648 $1\xer_ca$10$next[1:0]$8647 } { \xer_ca_ok$40 \xer_ca$39 } + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'000011 assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8648 $1\xer_ca$10$next[1:0]$8647 } { \xer_ca_ok$40 \xer_ca$39 } - case - assign $1\xer_ca$10$next[1:0]$8647 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8648 \xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'011011 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8649 1'0 - case - assign $2\xer_ca_ok$next[0:0]$8649 $1\xer_ca_ok$next[0:0]$8648 - end - sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8645 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8646 - end - connect \$22 $and$libresoc.v:152602$8569_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } - connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } - connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } - connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } - connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } - connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } - connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } - connect \muxid$24 \spr_main_muxid$11 - connect \p_valid_i_p_ready_o \$22 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$21 \p_valid_i - connect \spr_main_xer_ca \xer_ca - connect \spr_main_xer_ov \xer_ov - connect \spr_main_xer_so \xer_so - connect \spr_main_fast1 \fast1 - connect \spr_main_spr1 \spr1 - connect \spr_main_ra \ra - connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \spr_main_muxid \muxid -end -attribute \src "libresoc.v:152863.1-154334.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" -attribute \generator "nMigen" -module \pipe1 - attribute \src "libresoc.v:154248.3-154289.6" - wire width 4 $0\alu_op__data_len$next[3:0]$8742 - attribute \src "libresoc.v:154024.3-154025.49" - wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 12 $0\alu_op__fn_unit$next[11:0]$8743 - attribute \src "libresoc.v:153994.3-153995.47" - wire width 12 $0\alu_op__fn_unit[11:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$8744 - attribute \src "libresoc.v:153996.3-153997.61" - wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__imm_data__ok$next[0:0]$8745 - attribute \src "libresoc.v:153998.3-153999.57" - wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$8746 - attribute \src "libresoc.v:154016.3-154017.55" - wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 32 $0\alu_op__insn$next[31:0]$8747 - attribute \src "libresoc.v:154026.3-154027.41" - wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$8748 - attribute \src "libresoc.v:153992.3-153993.51" - wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__invert_in$next[0:0]$8749 - attribute \src "libresoc.v:154008.3-154009.51" - wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__invert_out$next[0:0]$8750 - attribute \src "libresoc.v:154012.3-154013.53" - wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__is_32bit$next[0:0]$8751 - attribute \src "libresoc.v:154020.3-154021.49" - wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__is_signed$next[0:0]$8752 - attribute \src "libresoc.v:154022.3-154023.51" - wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__oe__oe$next[0:0]$8753 - attribute \src "libresoc.v:154004.3-154005.45" - wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__oe__ok$next[0:0]$8754 - attribute \src "libresoc.v:154006.3-154007.45" - wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__output_carry$next[0:0]$8755 - attribute \src "libresoc.v:154018.3-154019.57" - wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__rc__ok$next[0:0]$8756 - attribute \src "libresoc.v:154002.3-154003.45" - wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__rc__rc$next[0:0]$8757 - attribute \src "libresoc.v:154000.3-154001.45" - wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__write_cr0$next[0:0]$8758 - attribute \src "libresoc.v:154014.3-154015.51" - wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $0\alu_op__zero_a$next[0:0]$8759 - attribute \src "libresoc.v:154010.3-154011.45" - wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:154141.3-154159.6" - wire width 4 $0\cr_a$next[3:0]$8711 - attribute \src "libresoc.v:153984.3-153985.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:154141.3-154159.6" - wire $0\cr_a_ok$next[0:0]$8712 - attribute \src "libresoc.v:153986.3-153987.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:152864.7-152864.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:154235.3-154247.6" - wire width 2 $0\muxid$next[1:0]$8739 - attribute \src "libresoc.v:154028.3-154029.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:154290.3-154308.6" - wire width 64 $0\o$next[63:0]$8785 - attribute \src "libresoc.v:153988.3-153989.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:154290.3-154308.6" - wire $0\o_ok$next[0:0]$8786 - attribute \src "libresoc.v:153990.3-153991.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:154217.3-154234.6" - wire $0\r_busy$next[0:0]$8735 - attribute \src "libresoc.v:154030.3-154031.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:154160.3-154178.6" - wire width 2 $0\xer_ca$next[1:0]$8718 - attribute \src "libresoc.v:153980.3-153981.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:154160.3-154178.6" - wire $0\xer_ca_ok$next[0:0]$8717 - attribute \src "libresoc.v:153982.3-153983.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:154179.3-154197.6" - wire width 2 $0\xer_ov$next[1:0]$8723 - attribute \src "libresoc.v:153976.3-153977.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:154179.3-154197.6" - wire $0\xer_ov_ok$next[0:0]$8724 - attribute \src "libresoc.v:153978.3-153979.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:154198.3-154216.6" - wire $0\xer_so$next[0:0]$8729 - attribute \src "libresoc.v:153972.3-153973.29" - wire $0\xer_so[0:0] - attribute \src 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$1\alu_op__input_carry$next[1:0]$8764 - attribute \src "libresoc.v:152948.13-152948.39" - wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 32 $1\alu_op__insn$next[31:0]$8765 - attribute \src "libresoc.v:152965.14-152965.34" - wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$8766 - attribute \src "libresoc.v:153048.13-153048.38" - wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__invert_in$next[0:0]$8767 - attribute \src "libresoc.v:153205.7-153205.31" - wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__invert_out$next[0:0]$8768 - attribute \src "libresoc.v:153214.7-153214.32" - wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__is_32bit$next[0:0]$8769 - attribute \src "libresoc.v:153223.7-153223.30" - wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__is_signed$next[0:0]$8770 - attribute \src "libresoc.v:153232.7-153232.31" - wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__oe__oe$next[0:0]$8771 - attribute \src "libresoc.v:153241.7-153241.28" - wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__oe__ok$next[0:0]$8772 - attribute \src "libresoc.v:153250.7-153250.28" - wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__output_carry$next[0:0]$8773 - attribute \src "libresoc.v:153259.7-153259.34" - wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__rc__ok$next[0:0]$8774 - attribute \src "libresoc.v:153268.7-153268.28" - wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire $1\alu_op__rc__rc$next[0:0]$8775 - attribute \src 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$1\xer_ov_ok[0:0] - attribute \src "libresoc.v:154198.3-154216.6" - wire $1\xer_so$next[0:0]$8731 - attribute \src "libresoc.v:153955.7-153955.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:154198.3-154216.6" - wire $1\xer_so_ok$next[0:0]$8732 - attribute \src "libresoc.v:153964.7-153964.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:154248.3-154289.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$8778 - attribute \src "libresoc.v:154248.3-154289.6" - wire $2\alu_op__imm_data__ok$next[0:0]$8779 - attribute \src "libresoc.v:154248.3-154289.6" - wire $2\alu_op__oe__oe$next[0:0]$8780 - attribute \src "libresoc.v:154248.3-154289.6" - wire $2\alu_op__oe__ok$next[0:0]$8781 - attribute \src "libresoc.v:154248.3-154289.6" - wire $2\alu_op__rc__ok$next[0:0]$8782 - attribute \src "libresoc.v:154248.3-154289.6" - wire $2\alu_op__rc__rc$next[0:0]$8783 - attribute \src "libresoc.v:154141.3-154159.6" - wire $2\cr_a_ok$next[0:0]$8715 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute 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attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 39 \alu_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 17 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 48 \alu_op__input_carry$14 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 53 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 36 \alu_op__insn_type$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 47 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "libresoc.v:152864.7-152864.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_alu_op__data_len$39 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_alu_op__fn_unit$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_alu_op__imm_data__data$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_32bit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__is_signed$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__oe$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__oe__ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__output_carry$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__ok$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__rc__rc$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__write_cr0$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \main_alu_op__zero_a$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \main_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ca$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \main_xer_so$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 34 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 33 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 54 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 57 \xer_ca$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 56 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 32 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:153971$8679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$66 - connect \B \p_ready_o - connect \Y $and$libresoc.v:153971$8679_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154032.11-154079.4" - cell \input \input - connect \alu_op__data_len \input_alu_op__data_len - connect \alu_op__data_len$18 \input_alu_op__data_len$39 - connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__data \input_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 - connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 - connect \alu_op__input_carry \input_alu_op__input_carry - connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 - connect \alu_op__insn \input_alu_op__insn - connect \alu_op__insn$19 \input_alu_op__insn$40 - connect \alu_op__insn_type \input_alu_op__insn_type - connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 - connect \alu_op__invert_in \input_alu_op__invert_in - connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 - connect \alu_op__invert_out \input_alu_op__invert_out - connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 - connect \alu_op__is_32bit \input_alu_op__is_32bit - connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 - connect \alu_op__is_signed \input_alu_op__is_signed - connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 - connect \alu_op__oe__oe \input_alu_op__oe__oe - connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 - connect \alu_op__oe__ok \input_alu_op__oe__ok - connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 - connect \alu_op__output_carry \input_alu_op__output_carry - connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 - connect \alu_op__rc__ok \input_alu_op__rc__ok - connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 - connect \alu_op__rc__rc \input_alu_op__rc__rc - connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__write_cr0 \input_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 - connect \alu_op__zero_a \input_alu_op__zero_a - connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$22 - connect \ra \input_ra - connect \ra$20 \input_ra$41 - connect \rb \input_rb - connect \rb$21 \input_rb$42 - connect \xer_ca \input_xer_ca - connect \xer_ca$23 \input_xer_ca$44 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$43 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154080.8-154132.4" - cell \main \main - connect \alu_op__data_len \main_alu_op__data_len - connect \alu_op__data_len$18 \main_alu_op__data_len$62 - connect \alu_op__fn_unit \main_alu_op__fn_unit - connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 - connect \alu_op__imm_data__data \main_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 - connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 - connect \alu_op__input_carry \main_alu_op__input_carry - connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 - connect \alu_op__insn \main_alu_op__insn - connect \alu_op__insn$19 \main_alu_op__insn$63 - connect \alu_op__insn_type \main_alu_op__insn_type - connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 - connect \alu_op__invert_in \main_alu_op__invert_in - connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 - connect \alu_op__invert_out \main_alu_op__invert_out - connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 - connect \alu_op__is_32bit \main_alu_op__is_32bit - connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 - connect \alu_op__is_signed \main_alu_op__is_signed - connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 - connect \alu_op__oe__oe \main_alu_op__oe__oe - connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 - connect \alu_op__oe__ok \main_alu_op__oe__ok - connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 - connect \alu_op__output_carry \main_alu_op__output_carry - connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 - connect \alu_op__rc__ok \main_alu_op__rc__ok - connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 - connect \alu_op__rc__rc \main_alu_op__rc__rc - connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 - connect \alu_op__write_cr0 \main_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 - connect \alu_op__zero_a \main_alu_op__zero_a - connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 - connect \cr_a \main_cr_a - connect \cr_a_ok \main_cr_a_ok - connect \muxid \main_muxid - connect \muxid$1 \main_muxid$45 - connect \o \main_o - connect \o_ok \main_o_ok - connect \ra \main_ra - connect \rb \main_rb - connect \xer_ca \main_xer_ca - connect \xer_ca$20 \main_xer_ca$64 - connect \xer_ca_ok \main_xer_ca_ok - connect \xer_ov \main_xer_ov - connect \xer_ov_ok \main_xer_ov_ok - connect \xer_so \main_xer_so - connect \xer_so$21 \main_xer_so$65 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154133.9-154136.4" - cell \n$2 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:154137.9-154140.4" - cell \p$1 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:152864.7-152864.20" - process $proc$libresoc.v:152864$8790 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:152869.13-152869.36" - process $proc$libresoc.v:152869$8791 - assign { } { } - assign $1\alu_op__data_len[3:0] 4'0000 - sync always - sync init - update \alu_op__data_len $1\alu_op__data_len[3:0] - end - attribute \src "libresoc.v:152891.14-152891.39" - process $proc$libresoc.v:152891$8792 - assign { } { } - assign $1\alu_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:152926.14-152926.59" - process $proc$libresoc.v:152926$8793 - assign { } { } - assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:152935.7-152935.34" - process $proc$libresoc.v:152935$8794 - assign { } { } - assign $1\alu_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:152948.13-152948.39" - process $proc$libresoc.v:152948$8795 - assign { } { } - assign $1\alu_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_op__input_carry $1\alu_op__input_carry[1:0] - end - attribute \src "libresoc.v:152965.14-152965.34" - process $proc$libresoc.v:152965$8796 - assign { } { } - assign $1\alu_op__insn[31:0] 0 - sync always - sync init - update \alu_op__insn $1\alu_op__insn[31:0] - end - attribute \src "libresoc.v:153048.13-153048.38" - process $proc$libresoc.v:153048$8797 - assign { } { } - assign $1\alu_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_op__insn_type $1\alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:153205.7-153205.31" - process $proc$libresoc.v:153205$8798 - assign { } { } - assign $1\alu_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_op__invert_in $1\alu_op__invert_in[0:0] - end - attribute \src "libresoc.v:153214.7-153214.32" - process $proc$libresoc.v:153214$8799 - assign { } { } - assign $1\alu_op__invert_out[0:0] 1'0 - sync always - sync init - update \alu_op__invert_out $1\alu_op__invert_out[0:0] - end - attribute \src "libresoc.v:153223.7-153223.30" - process $proc$libresoc.v:153223$8800 - assign { } { } - assign $1\alu_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] - end - attribute \src "libresoc.v:153232.7-153232.31" - process $proc$libresoc.v:153232$8801 - assign { } { } - assign $1\alu_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_op__is_signed $1\alu_op__is_signed[0:0] - end - attribute \src "libresoc.v:153241.7-153241.28" - process $proc$libresoc.v:153241$8802 - assign { } { } - assign $1\alu_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] - end - attribute \src "libresoc.v:153250.7-153250.28" - process $proc$libresoc.v:153250$8803 - assign { } { } - assign $1\alu_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] - end - attribute \src "libresoc.v:153259.7-153259.34" - process $proc$libresoc.v:153259$8804 - assign { } { } - assign $1\alu_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_op__output_carry $1\alu_op__output_carry[0:0] - end - attribute \src "libresoc.v:153268.7-153268.28" - process $proc$libresoc.v:153268$8805 - assign { } { } - assign $1\alu_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] - end - attribute \src "libresoc.v:153277.7-153277.28" - process $proc$libresoc.v:153277$8806 - assign { } { } - assign $1\alu_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] - end - attribute \src "libresoc.v:153286.7-153286.31" - process $proc$libresoc.v:153286$8807 - assign { } { } - assign $1\alu_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] - end - attribute \src "libresoc.v:153295.7-153295.28" - process $proc$libresoc.v:153295$8808 - assign { } { } - assign $1\alu_op__zero_a[0:0] 1'0 - sync always - sync init - update \alu_op__zero_a $1\alu_op__zero_a[0:0] - end - attribute \src "libresoc.v:153308.13-153308.24" - process $proc$libresoc.v:153308$8809 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:153315.7-153315.21" - process $proc$libresoc.v:153315$8810 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:153880.13-153880.25" - process $proc$libresoc.v:153880$8811 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:153895.14-153895.38" - process $proc$libresoc.v:153895$8812 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:153902.7-153902.18" - process $proc$libresoc.v:153902$8813 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:153916.7-153916.20" - process $proc$libresoc.v:153916$8814 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:153925.13-153925.26" - process $proc$libresoc.v:153925$8815 - assign { } { } - assign $1\xer_ca[1:0] 2'00 - sync always - sync init - update \xer_ca $1\xer_ca[1:0] - end - attribute \src "libresoc.v:153934.7-153934.23" - process $proc$libresoc.v:153934$8816 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:153941.13-153941.26" - process $proc$libresoc.v:153941$8817 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "libresoc.v:153948.7-153948.23" - process $proc$libresoc.v:153948$8818 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:153955.7-153955.20" - process $proc$libresoc.v:153955$8819 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:153964.7-153964.23" - process $proc$libresoc.v:153964$8820 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:153972.3-153973.29" - process $proc$libresoc.v:153972$8680 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:153974.3-153975.35" - process $proc$libresoc.v:153974$8681 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:153976.3-153977.29" - process $proc$libresoc.v:153976$8682 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "libresoc.v:153978.3-153979.35" - process $proc$libresoc.v:153978$8683 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:153980.3-153981.29" - process $proc$libresoc.v:153980$8684 - assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next - sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] - end - attribute \src "libresoc.v:153982.3-153983.35" - process $proc$libresoc.v:153982$8685 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:153984.3-153985.25" - process $proc$libresoc.v:153984$8686 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:153986.3-153987.31" - process $proc$libresoc.v:153986$8687 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:153988.3-153989.19" - process $proc$libresoc.v:153988$8688 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:153990.3-153991.25" - process $proc$libresoc.v:153990$8689 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:153992.3-153993.51" - process $proc$libresoc.v:153992$8690 - assign { } { } - assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next - sync posedge \coresync_clk - update \alu_op__insn_type $0\alu_op__insn_type[6:0] - end - attribute \src "libresoc.v:153994.3-153995.47" - process $proc$libresoc.v:153994$8691 - assign { } { } - assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next - sync posedge \coresync_clk - update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] - end - attribute \src "libresoc.v:153996.3-153997.61" - process $proc$libresoc.v:153996$8692 - assign { } { } - assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:153998.3-153999.57" - process $proc$libresoc.v:153998$8693 - assign { } { } - assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:154000.3-154001.45" - process $proc$libresoc.v:154000$8694 - assign { } { } - assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next - sync posedge \coresync_clk - update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] - end - attribute \src "libresoc.v:154002.3-154003.45" - process $proc$libresoc.v:154002$8695 - assign { } { } - assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next - sync posedge \coresync_clk - update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] - end - attribute \src "libresoc.v:154004.3-154005.45" - process $proc$libresoc.v:154004$8696 - assign { } { } - assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next - sync posedge \coresync_clk - update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] - end - attribute \src "libresoc.v:154006.3-154007.45" - process $proc$libresoc.v:154006$8697 - assign { } { } - assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next - sync posedge \coresync_clk - update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] - end - attribute \src "libresoc.v:154008.3-154009.51" - process $proc$libresoc.v:154008$8698 - assign { } { } - assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next - sync posedge \coresync_clk - update \alu_op__invert_in $0\alu_op__invert_in[0:0] - end - attribute \src "libresoc.v:154010.3-154011.45" - process $proc$libresoc.v:154010$8699 - assign { } { } - assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next - sync posedge \coresync_clk - update \alu_op__zero_a $0\alu_op__zero_a[0:0] - end - attribute \src "libresoc.v:154012.3-154013.53" - process $proc$libresoc.v:154012$8700 - assign { } { } - assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next - sync posedge \coresync_clk - update \alu_op__invert_out $0\alu_op__invert_out[0:0] - end - attribute \src "libresoc.v:154014.3-154015.51" - process $proc$libresoc.v:154014$8701 - assign { } { } - assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next - sync posedge \coresync_clk - update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] - end - attribute \src "libresoc.v:154016.3-154017.55" - process $proc$libresoc.v:154016$8702 - assign { } { } - assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next - sync posedge \coresync_clk - update \alu_op__input_carry $0\alu_op__input_carry[1:0] - end - attribute \src "libresoc.v:154018.3-154019.57" - process $proc$libresoc.v:154018$8703 - assign { } { } - assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next - sync posedge \coresync_clk - update \alu_op__output_carry $0\alu_op__output_carry[0:0] - end - attribute \src "libresoc.v:154020.3-154021.49" - process $proc$libresoc.v:154020$8704 - assign { } { } - assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next - sync posedge \coresync_clk - update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] - end - attribute \src "libresoc.v:154022.3-154023.51" - process $proc$libresoc.v:154022$8705 - assign { } { } - assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next - sync posedge \coresync_clk - update \alu_op__is_signed $0\alu_op__is_signed[0:0] - end - attribute \src "libresoc.v:154024.3-154025.49" - process $proc$libresoc.v:154024$8706 - assign { } { } - assign $0\alu_op__data_len[3:0] \alu_op__data_len$next - sync posedge \coresync_clk - update \alu_op__data_len $0\alu_op__data_len[3:0] - end - attribute \src "libresoc.v:154026.3-154027.41" - process $proc$libresoc.v:154026$8707 - assign { } { } - assign $0\alu_op__insn[31:0] \alu_op__insn$next - sync posedge \coresync_clk - update \alu_op__insn $0\alu_op__insn[31:0] - end - attribute \src "libresoc.v:154028.3-154029.27" - process $proc$libresoc.v:154028$8708 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:154030.3-154031.29" - process $proc$libresoc.v:154030$8709 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:154141.3-154159.6" - process $proc$libresoc.v:154141$8710 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$8711 $1\cr_a$next[3:0]$8713 - assign { } { } - assign $0\cr_a_ok$next[0:0]$8712 $2\cr_a_ok$next[0:0]$8715 - attribute \src "libresoc.v:154142.5-154142.29" - switch \initial - attribute \src "libresoc.v:154142.9-154142.17" - case 1'1 + assign $1\ldst_len[3:0] 4'0000 case + assign $1\ldst_len[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } + case 32'000000---------------0100000000- assign { } { } - assign { $1\cr_a_ok$next[0:0]$8714 $1\cr_a$next[3:0]$8713 } { \cr_a_ok$91 \cr_a$90 } + assign $2\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1610612736 assign { } { } - assign { $1\cr_a_ok$next[0:0]$8714 $1\cr_a$next[3:0]$8713 } { \cr_a_ok$91 \cr_a$90 } - case - assign $1\cr_a$next[3:0]$8713 \cr_a - assign $1\cr_a_ok$next[0:0]$8714 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $2\ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000001---------------0000000011- assign { } { } - assign $2\cr_a_ok$next[0:0]$8715 1'0 + assign $2\ldst_len[3:0] 4'0000 case - assign $2\cr_a_ok$next[0:0]$8715 $1\cr_a_ok$next[0:0]$8714 + assign $2\ldst_len[3:0] $1\ldst_len[3:0] end sync always - update \cr_a$next $0\cr_a$next[3:0]$8711 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8712 + update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:154160.3-154178.6" - process $proc$libresoc.v:154160$8716 + attribute \src "libresoc.v:4518.3-4659.6" + process $proc$libresoc.v:4518$246 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$next[1:0]$8718 $1\xer_ca$next[1:0]$8720 - assign $0\xer_ca_ok$next[0:0]$8717 $2\xer_ca_ok$next[0:0]$8721 - attribute \src "libresoc.v:154161.5-154161.29" + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:4519.5-4519.29" switch \initial - attribute \src "libresoc.v:154161.9-154161.17" + attribute \src "libresoc.v:4519.9-4519.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8719 $1\xer_ca$next[1:0]$8720 } { \xer_ca_ok$93 \xer_ca$92 } + assign $1\upd[1:0] \dec30_dec30_upd attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8719 $1\xer_ca$next[1:0]$8720 } { \xer_ca_ok$93 \xer_ca$92 } + assign $1\upd[1:0] 2'00 case - assign $1\xer_ca_ok$next[0:0]$8719 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8720 \xer_ca + assign $1\upd[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000000---------------0100000000- assign { } { } - assign $2\xer_ca_ok$next[0:0]$8721 1'0 + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 case - assign $2\xer_ca_ok$next[0:0]$8721 $1\xer_ca_ok$next[0:0]$8719 + assign $2\upd[1:0] $1\upd[1:0] end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8717 - update \xer_ca$next $0\xer_ca$next[1:0]$8718 + update \upd $0\upd[1:0] end - attribute \src "libresoc.v:154179.3-154197.6" - process $proc$libresoc.v:154179$8722 - assign { } { } + attribute \src "libresoc.v:4660.3-4801.6" + process $proc$libresoc.v:4660$247 assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8723 $1\xer_ov$next[1:0]$8725 - assign { } { } - assign $0\xer_ov_ok$next[0:0]$8724 $2\xer_ov_ok$next[0:0]$8727 - attribute \src "libresoc.v:154180.5-154180.29" + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:4661.5-4661.29" switch \initial - attribute \src "libresoc.v:154180.9-154180.17" + attribute \src "libresoc.v:4661.9-4661.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8726 $1\xer_ov$next[1:0]$8725 } { \xer_ov_ok$95 \xer_ov$94 } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8726 $1\xer_ov$next[1:0]$8725 } { \xer_ov_ok$95 \xer_ov$94 } + assign $1\rc_sel[1:0] 2'00 case - assign $1\xer_ov$next[1:0]$8725 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8726 \xer_ov_ok + assign $1\rc_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $2\xer_ov_ok$next[0:0]$8727 1'0 + assign $2\rc_sel[1:0] 2'00 case - assign $2\xer_ov_ok$next[0:0]$8727 $1\xer_ov_ok$next[0:0]$8726 + assign $2\rc_sel[1:0] $1\rc_sel[1:0] end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8723 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8724 + update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:154198.3-154216.6" - process $proc$libresoc.v:154198$8728 - assign { } { } - assign { } { } + attribute \src "libresoc.v:4802.3-4943.6" + process $proc$libresoc.v:4802$248 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8729 $1\xer_so$next[0:0]$8731 assign { } { } - assign $0\xer_so_ok$next[0:0]$8730 $2\xer_so_ok$next[0:0]$8733 - attribute \src "libresoc.v:154199.5-154199.29" + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:4803.5-4803.29" switch \initial - attribute \src "libresoc.v:154199.9-154199.17" + attribute \src "libresoc.v:4803.9-4803.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8732 $1\xer_so$next[0:0]$8731 } { \xer_so_ok$97 \xer_so$96 } + assign $1\cry_in[1:0] \dec30_dec30_cry_in attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8732 $1\xer_so$next[0:0]$8731 } { \xer_so_ok$97 \xer_so$96 } + assign $1\cry_in[1:0] 2'00 case - assign $1\xer_so$next[0:0]$8731 \xer_so - assign $1\xer_so_ok$next[0:0]$8732 \xer_so_ok + assign $1\cry_in[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $2\xer_so_ok$next[0:0]$8733 1'0 + assign $2\cry_in[1:0] 2'00 case - assign $2\xer_so_ok$next[0:0]$8733 $1\xer_so_ok$next[0:0]$8732 + assign $2\cry_in[1:0] $1\cry_in[1:0] end sync always - update \xer_so$next $0\xer_so$next[0:0]$8729 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8730 + update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:154217.3-154234.6" - process $proc$libresoc.v:154217$8734 + attribute \src "libresoc.v:4944.3-5085.6" + process $proc$libresoc.v:4944$249 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8735 $2\r_busy$next[0:0]$8737 - attribute \src "libresoc.v:154218.5-154218.29" + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:4945.5-4945.29" switch \initial - attribute \src "libresoc.v:154218.9-154218.17" + attribute \src "libresoc.v:4945.9-4945.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } - assign $1\r_busy$next[0:0]$8736 1'1 + assign $1\inv_a[0:0] \dec19_dec19_inv_a attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign $1\r_busy$next[0:0]$8736 1'0 + assign $1\inv_a[0:0] 1'0 case - assign $1\r_busy$next[0:0]$8736 \r_busy + assign $1\inv_a[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $2\r_busy$next[0:0]$8737 1'0 + assign $2\inv_a[0:0] 1'0 case - assign $2\r_busy$next[0:0]$8737 $1\r_busy$next[0:0]$8736 + assign $2\inv_a[0:0] $1\inv_a[0:0] end sync always - update \r_busy$next $0\r_busy$next[0:0]$8735 + update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:154235.3-154247.6" - process $proc$libresoc.v:154235$8738 + attribute \src "libresoc.v:5086.3-5227.6" + process $proc$libresoc.v:5086$250 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$8739 $1\muxid$next[1:0]$8740 - attribute \src "libresoc.v:154236.5-154236.29" + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:5087.5-5087.29" switch \initial - attribute \src "libresoc.v:154236.9-154236.17" + attribute \src "libresoc.v:5087.9-5087.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } - assign $1\muxid$next[1:0]$8740 \muxid$69 + assign $1\inv_out[0:0] \dec19_dec19_inv_out attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\muxid$next[1:0]$8740 \muxid$69 + assign $2\inv_out[0:0] 1'0 case - assign $1\muxid$next[1:0]$8740 \muxid + assign $2\inv_out[0:0] $1\inv_out[0:0] end sync always - update \muxid$next $0\muxid$next[1:0]$8739 + update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:154248.3-154289.6" - process $proc$libresoc.v:154248$8741 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:5228.3-5369.6" + process $proc$libresoc.v:5228$251 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_op__data_len$next[3:0]$8742 $1\alu_op__data_len$next[3:0]$8760 - assign $0\alu_op__fn_unit$next[11:0]$8743 $1\alu_op__fn_unit$next[11:0]$8761 - assign { } { } - assign { } { } - assign $0\alu_op__input_carry$next[1:0]$8746 $1\alu_op__input_carry$next[1:0]$8764 - assign $0\alu_op__insn$next[31:0]$8747 $1\alu_op__insn$next[31:0]$8765 - assign $0\alu_op__insn_type$next[6:0]$8748 $1\alu_op__insn_type$next[6:0]$8766 - assign $0\alu_op__invert_in$next[0:0]$8749 $1\alu_op__invert_in$next[0:0]$8767 - assign $0\alu_op__invert_out$next[0:0]$8750 $1\alu_op__invert_out$next[0:0]$8768 - assign $0\alu_op__is_32bit$next[0:0]$8751 $1\alu_op__is_32bit$next[0:0]$8769 - assign $0\alu_op__is_signed$next[0:0]$8752 $1\alu_op__is_signed$next[0:0]$8770 - assign { } { } - assign { } { } - assign $0\alu_op__output_carry$next[0:0]$8755 $1\alu_op__output_carry$next[0:0]$8773 - assign { } { } - assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$8758 $1\alu_op__write_cr0$next[0:0]$8776 - assign $0\alu_op__zero_a$next[0:0]$8759 $1\alu_op__zero_a$next[0:0]$8777 - assign $0\alu_op__imm_data__data$next[63:0]$8744 $2\alu_op__imm_data__data$next[63:0]$8778 - assign $0\alu_op__imm_data__ok$next[0:0]$8745 $2\alu_op__imm_data__ok$next[0:0]$8779 - assign $0\alu_op__oe__oe$next[0:0]$8753 $2\alu_op__oe__oe$next[0:0]$8780 - assign $0\alu_op__oe__ok$next[0:0]$8754 $2\alu_op__oe__ok$next[0:0]$8781 - assign $0\alu_op__rc__ok$next[0:0]$8756 $2\alu_op__rc__ok$next[0:0]$8782 - assign $0\alu_op__rc__rc$next[0:0]$8757 $2\alu_op__rc__rc$next[0:0]$8783 - attribute \src "libresoc.v:154249.5-154249.29" + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:5229.5-5229.29" switch \initial - attribute \src "libresoc.v:154249.9-154249.17" + attribute \src "libresoc.v:5229.9-5229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign { $1\alu_op__insn$next[31:0]$8765 $1\alu_op__data_len$next[3:0]$8760 $1\alu_op__is_signed$next[0:0]$8770 $1\alu_op__is_32bit$next[0:0]$8769 $1\alu_op__output_carry$next[0:0]$8773 $1\alu_op__input_carry$next[1:0]$8764 $1\alu_op__write_cr0$next[0:0]$8776 $1\alu_op__invert_out$next[0:0]$8768 $1\alu_op__zero_a$next[0:0]$8777 $1\alu_op__invert_in$next[0:0]$8767 $1\alu_op__oe__ok$next[0:0]$8772 $1\alu_op__oe__oe$next[0:0]$8771 $1\alu_op__rc__ok$next[0:0]$8774 $1\alu_op__rc__rc$next[0:0]$8775 $1\alu_op__imm_data__ok$next[0:0]$8763 $1\alu_op__imm_data__data$next[63:0]$8762 $1\alu_op__fn_unit$next[11:0]$8761 $1\alu_op__insn_type$next[6:0]$8766 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign $1\cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'100001 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign { $1\alu_op__insn$next[31:0]$8765 $1\alu_op__data_len$next[3:0]$8760 $1\alu_op__is_signed$next[0:0]$8770 $1\alu_op__is_32bit$next[0:0]$8769 $1\alu_op__output_carry$next[0:0]$8773 $1\alu_op__input_carry$next[1:0]$8764 $1\alu_op__write_cr0$next[0:0]$8776 $1\alu_op__invert_out$next[0:0]$8768 $1\alu_op__zero_a$next[0:0]$8777 $1\alu_op__invert_in$next[0:0]$8767 $1\alu_op__oe__ok$next[0:0]$8772 $1\alu_op__oe__oe$next[0:0]$8771 $1\alu_op__rc__ok$next[0:0]$8774 $1\alu_op__rc__rc$next[0:0]$8775 $1\alu_op__imm_data__ok$next[0:0]$8763 $1\alu_op__imm_data__data$next[63:0]$8762 $1\alu_op__fn_unit$next[11:0]$8761 $1\alu_op__insn_type$next[6:0]$8766 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign $1\cry_out[0:0] 1'0 case - assign $1\alu_op__data_len$next[3:0]$8760 \alu_op__data_len - assign $1\alu_op__fn_unit$next[11:0]$8761 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$8762 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$8763 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$8764 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$8765 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$8766 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$8767 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$8768 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$8769 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$8770 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$8771 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$8772 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$8773 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$8774 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$8775 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$8776 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$8777 \alu_op__zero_a + assign $1\cry_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } + case 32'000000---------------0100000000- assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$8778 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$8779 1'0 - assign $2\alu_op__rc__rc$next[0:0]$8783 1'0 - assign $2\alu_op__rc__ok$next[0:0]$8782 1'0 - assign $2\alu_op__oe__oe$next[0:0]$8780 1'0 - assign $2\alu_op__oe__ok$next[0:0]$8781 1'0 + assign $2\cry_out[0:0] 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$8778 $1\alu_op__imm_data__data$next[63:0]$8762 - assign $2\alu_op__imm_data__ok$next[0:0]$8779 $1\alu_op__imm_data__ok$next[0:0]$8763 - assign $2\alu_op__oe__oe$next[0:0]$8780 $1\alu_op__oe__oe$next[0:0]$8771 - assign $2\alu_op__oe__ok$next[0:0]$8781 $1\alu_op__oe__ok$next[0:0]$8772 - assign $2\alu_op__rc__ok$next[0:0]$8782 $1\alu_op__rc__ok$next[0:0]$8774 - assign $2\alu_op__rc__rc$next[0:0]$8783 $1\alu_op__rc__rc$next[0:0]$8775 + assign $2\cry_out[0:0] $1\cry_out[0:0] end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8742 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8743 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8744 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8745 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8746 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8747 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8748 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8749 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8750 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8751 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8752 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8753 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8754 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8755 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8756 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8757 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8758 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8759 + update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:154290.3-154308.6" - process $proc$libresoc.v:154290$8784 - assign { } { } - assign { } { } + attribute \src "libresoc.v:5370.3-5511.6" + process $proc$libresoc.v:5370$252 assign { } { } assign { } { } - assign $0\o$next[63:0]$8785 $1\o$next[63:0]$8787 assign { } { } - assign $0\o_ok$next[0:0]$8786 $2\o_ok$next[0:0]$8789 - attribute \src "libresoc.v:154291.5-154291.29" + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:5371.5-5371.29" switch \initial - attribute \src "libresoc.v:154291.9-154291.17" + attribute \src "libresoc.v:5371.9-5371.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign { $1\o_ok$next[0:0]$8788 $1\o$next[63:0]$8787 } { \o_ok$89 \o$88 } + assign $1\br[0:0] \dec30_dec30_br attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011111 assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign { $1\o_ok$next[0:0]$8788 $1\o$next[63:0]$8787 } { \o_ok$89 \o$88 } - case - assign $1\o$next[63:0]$8787 \o - assign $1\o_ok$next[0:0]$8788 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\br[0:0] \dec58_dec58_br attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'111110 assign { } { } - assign $2\o_ok$next[0:0]$8789 1'0 - case - assign $2\o_ok$next[0:0]$8789 $1\o_ok$next[0:0]$8788 - end - sync always - update \o$next $0\o$next[63:0]$8785 - update \o_ok$next $0\o_ok$next[0:0]$8786 - end - connect \$67 $and$libresoc.v:153971$8679_Y - connect \xer_so_ok$98 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } - connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } - connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } - connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } - connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } - connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } - connect \muxid$69 \main_muxid$45 - connect \p_valid_i_p_ready_o \$67 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$66 \p_valid_i - connect \main_xer_ca \input_xer_ca$44 - connect \main_xer_so \input_xer_so$43 - connect \main_rb \input_rb$42 - connect \main_ra \input_ra$41 - connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } - connect \main_muxid \input_muxid$22 - connect \input_xer_ca \xer_ca$21 - connect \input_xer_so \xer_so$20 - connect \input_rb \rb - connect \input_ra \ra - connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:154338.1-155753.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" -attribute \generator "nMigen" -module \pipe1$110 - attribute \src "libresoc.v:155686.3-155704.6" - wire width 4 $0\cr_a$next[3:0]$8910 - attribute \src "libresoc.v:155428.3-155429.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:155686.3-155704.6" - wire $0\cr_a_ok$next[0:0]$8911 - attribute \src "libresoc.v:155430.3-155431.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:154339.7-154339.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:155613.3-155625.6" - wire width 2 $0\muxid$next[1:0]$8860 - attribute \src "libresoc.v:155470.3-155471.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:155667.3-155685.6" - wire width 64 $0\o$next[63:0]$8904 - attribute \src "libresoc.v:155432.3-155433.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:155667.3-155685.6" - wire $0\o_ok$next[0:0]$8905 - attribute \src "libresoc.v:155434.3-155435.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:155595.3-155612.6" - wire $0\r_busy$next[0:0]$8856 - attribute \src "libresoc.v:155472.3-155473.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 12 $0\sr_op__fn_unit$next[11:0]$8863 - attribute \src "libresoc.v:155438.3-155439.45" - wire width 12 $0\sr_op__fn_unit[11:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$8864 - attribute \src "libresoc.v:155440.3-155441.59" - wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__imm_data__ok$next[0:0]$8865 - attribute \src "libresoc.v:155442.3-155443.55" - wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$8866 - attribute \src "libresoc.v:155456.3-155457.53" - wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__input_cr$next[0:0]$8867 - attribute \src "libresoc.v:155460.3-155461.47" - wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 32 $0\sr_op__insn$next[31:0]$8868 - attribute \src "libresoc.v:155468.3-155469.39" - wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$8869 - attribute \src "libresoc.v:155436.3-155437.49" - wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__invert_in$next[0:0]$8870 - attribute \src "libresoc.v:155454.3-155455.49" - wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__is_32bit$next[0:0]$8871 - attribute \src "libresoc.v:155464.3-155465.47" - wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__is_signed$next[0:0]$8872 - attribute \src "libresoc.v:155466.3-155467.49" - wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__oe__oe$next[0:0]$8873 - attribute \src "libresoc.v:155448.3-155449.43" - wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__oe__ok$next[0:0]$8874 - attribute \src "libresoc.v:155450.3-155451.43" - wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__output_carry$next[0:0]$8875 - attribute \src "libresoc.v:155458.3-155459.55" - wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__output_cr$next[0:0]$8876 - attribute \src "libresoc.v:155462.3-155463.49" - wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__rc__ok$next[0:0]$8877 - attribute \src "libresoc.v:155446.3-155447.43" - wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__rc__rc$next[0:0]$8878 - attribute \src "libresoc.v:155444.3-155445.43" - wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $0\sr_op__write_cr0$next[0:0]$8879 - attribute \src "libresoc.v:155452.3-155453.49" - wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:155576.3-155594.6" - wire width 2 $0\xer_ca$next[1:0]$8851 - attribute \src "libresoc.v:155420.3-155421.29" - wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:155576.3-155594.6" - wire $0\xer_ca_ok$next[0:0]$8850 - attribute \src "libresoc.v:155422.3-155423.35" - wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:155705.3-155723.6" - wire $0\xer_so$next[0:0]$8916 - attribute \src "libresoc.v:155424.3-155425.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:155705.3-155723.6" - wire $0\xer_so_ok$next[0:0]$8917 - attribute \src "libresoc.v:155426.3-155427.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:155686.3-155704.6" - wire width 4 $1\cr_a$next[3:0]$8912 - attribute \src "libresoc.v:154348.13-154348.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:155686.3-155704.6" - wire $1\cr_a_ok$next[0:0]$8913 - attribute \src "libresoc.v:154357.7-154357.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:155613.3-155625.6" - wire width 2 $1\muxid$next[1:0]$8861 - attribute \src "libresoc.v:154910.13-154910.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:155667.3-155685.6" - wire width 64 $1\o$next[63:0]$8906 - attribute \src "libresoc.v:154925.14-154925.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:155667.3-155685.6" - wire $1\o_ok$next[0:0]$8907 - attribute \src "libresoc.v:154932.7-154932.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:155595.3-155612.6" - wire $1\r_busy$next[0:0]$8857 - attribute \src "libresoc.v:154946.7-154946.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 12 $1\sr_op__fn_unit$next[11:0]$8880 - attribute \src "libresoc.v:154970.14-154970.38" - wire width 12 $1\sr_op__fn_unit[11:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$8881 - attribute \src "libresoc.v:155005.14-155005.58" - wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__imm_data__ok$next[0:0]$8882 - attribute \src "libresoc.v:155014.7-155014.33" - wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$8883 - attribute \src "libresoc.v:155027.13-155027.38" - wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__input_cr$next[0:0]$8884 - attribute \src "libresoc.v:155044.7-155044.29" - wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 32 $1\sr_op__insn$next[31:0]$8885 - attribute \src "libresoc.v:155053.14-155053.33" - wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$8886 - attribute \src "libresoc.v:155136.13-155136.37" - wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__invert_in$next[0:0]$8887 - attribute \src "libresoc.v:155293.7-155293.30" - wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__is_32bit$next[0:0]$8888 - attribute \src "libresoc.v:155302.7-155302.29" - wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__is_signed$next[0:0]$8889 - attribute \src "libresoc.v:155311.7-155311.30" - wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__oe__oe$next[0:0]$8890 - attribute \src "libresoc.v:155320.7-155320.27" - wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__oe__ok$next[0:0]$8891 - attribute \src "libresoc.v:155329.7-155329.27" - wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__output_carry$next[0:0]$8892 - attribute \src "libresoc.v:155338.7-155338.33" - wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__output_cr$next[0:0]$8893 - attribute \src "libresoc.v:155347.7-155347.30" - wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__rc__ok$next[0:0]$8894 - attribute \src "libresoc.v:155356.7-155356.27" - wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__rc__rc$next[0:0]$8895 - attribute \src "libresoc.v:155365.7-155365.27" - wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:155626.3-155666.6" - wire $1\sr_op__write_cr0$next[0:0]$8896 - attribute \src "libresoc.v:155374.7-155374.30" - wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:155576.3-155594.6" - wire width 2 $1\xer_ca$next[1:0]$8853 - attribute \src "libresoc.v:155383.13-155383.26" - wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:155576.3-155594.6" - wire $1\xer_ca_ok$next[0:0]$8852 - attribute \src "libresoc.v:155394.7-155394.23" - wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:155705.3-155723.6" - wire $1\xer_so$next[0:0]$8918 - attribute \src "libresoc.v:155403.7-155403.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:155705.3-155723.6" - wire $1\xer_so_ok$next[0:0]$8919 - attribute \src "libresoc.v:155412.7-155412.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:155686.3-155704.6" - wire $2\cr_a_ok$next[0:0]$8914 - attribute \src "libresoc.v:155667.3-155685.6" - wire $2\o_ok$next[0:0]$8908 - attribute \src "libresoc.v:155595.3-155612.6" - wire $2\r_busy$next[0:0]$8858 - attribute \src "libresoc.v:155626.3-155666.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$8897 - attribute \src "libresoc.v:155626.3-155666.6" - wire $2\sr_op__imm_data__ok$next[0:0]$8898 - attribute \src "libresoc.v:155626.3-155666.6" - wire $2\sr_op__oe__oe$next[0:0]$8899 - attribute \src "libresoc.v:155626.3-155666.6" - wire $2\sr_op__oe__ok$next[0:0]$8900 - attribute \src "libresoc.v:155626.3-155666.6" - wire $2\sr_op__rc__ok$next[0:0]$8901 - attribute \src "libresoc.v:155626.3-155666.6" - wire $2\sr_op__rc__rc$next[0:0]$8902 - attribute \src "libresoc.v:155576.3-155594.6" - wire $2\xer_ca_ok$next[0:0]$8854 - attribute \src "libresoc.v:155705.3-155723.6" - wire $2\xer_so_ok$next[0:0]$8920 - attribute \src "libresoc.v:155419.18-155419.118" - wire $and$libresoc.v:155419$8821_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next - 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wire \sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$next - attribute \src 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\xer_so \main_xer_so - connect \xer_so$19 \main_xer_so$62 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:155568.11-155571.4" - cell \n$112 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:155572.11-155575.4" - cell \p$111 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:154339.7-154339.20" - process $proc$libresoc.v:154339$8921 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:154348.13-154348.24" - process $proc$libresoc.v:154348$8922 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:154357.7-154357.21" - process $proc$libresoc.v:154357$8923 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:154910.13-154910.25" - process $proc$libresoc.v:154910$8924 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:154925.14-154925.38" - process $proc$libresoc.v:154925$8925 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:154932.7-154932.18" - process $proc$libresoc.v:154932$8926 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:154946.7-154946.20" - process $proc$libresoc.v:154946$8927 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:154970.14-154970.38" - process $proc$libresoc.v:154970$8928 - assign { } { } - assign $1\sr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:155005.14-155005.58" - process $proc$libresoc.v:155005$8929 - assign { } { } - assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:155014.7-155014.33" - process $proc$libresoc.v:155014$8930 - assign { } { } - assign $1\sr_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:155027.13-155027.38" - process $proc$libresoc.v:155027$8931 - assign { } { } - assign $1\sr_op__input_carry[1:0] 2'00 - sync always - sync init - update \sr_op__input_carry $1\sr_op__input_carry[1:0] - end - attribute \src "libresoc.v:155044.7-155044.29" - process $proc$libresoc.v:155044$8932 - assign { } { } - assign $1\sr_op__input_cr[0:0] 1'0 - sync always - sync init - update \sr_op__input_cr $1\sr_op__input_cr[0:0] - end - attribute \src "libresoc.v:155053.14-155053.33" - process $proc$libresoc.v:155053$8933 - assign { } { } - assign $1\sr_op__insn[31:0] 0 - sync always - sync init - update \sr_op__insn $1\sr_op__insn[31:0] - end - attribute \src "libresoc.v:155136.13-155136.37" - process $proc$libresoc.v:155136$8934 - assign { } { } - assign $1\sr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \sr_op__insn_type $1\sr_op__insn_type[6:0] - end - attribute \src "libresoc.v:155293.7-155293.30" - process $proc$libresoc.v:155293$8935 - assign { } { } - assign $1\sr_op__invert_in[0:0] 1'0 - sync always - sync init - update \sr_op__invert_in $1\sr_op__invert_in[0:0] - end - attribute \src "libresoc.v:155302.7-155302.29" - process $proc$libresoc.v:155302$8936 - assign { } { } - assign $1\sr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:155311.7-155311.30" - process $proc$libresoc.v:155311$8937 - assign { } { } - assign $1\sr_op__is_signed[0:0] 1'0 - sync always - sync init - update \sr_op__is_signed $1\sr_op__is_signed[0:0] - end - attribute \src "libresoc.v:155320.7-155320.27" - process $proc$libresoc.v:155320$8938 - assign { } { } - assign $1\sr_op__oe__oe[0:0] 1'0 - sync always - sync init - update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] - end - attribute \src "libresoc.v:155329.7-155329.27" - process $proc$libresoc.v:155329$8939 - assign { } { } - assign $1\sr_op__oe__ok[0:0] 1'0 - sync always - sync init - update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] - end - attribute \src "libresoc.v:155338.7-155338.33" - process $proc$libresoc.v:155338$8940 - assign { } { } - assign $1\sr_op__output_carry[0:0] 1'0 - sync always - sync init - update \sr_op__output_carry $1\sr_op__output_carry[0:0] - end - attribute \src "libresoc.v:155347.7-155347.30" - process $proc$libresoc.v:155347$8941 - assign { } { } - assign $1\sr_op__output_cr[0:0] 1'0 - sync always - sync init - update \sr_op__output_cr $1\sr_op__output_cr[0:0] - end - attribute \src "libresoc.v:155356.7-155356.27" - process $proc$libresoc.v:155356$8942 - assign { } { } - assign $1\sr_op__rc__ok[0:0] 1'0 - sync always - sync init - update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] - end - attribute \src "libresoc.v:155365.7-155365.27" - process $proc$libresoc.v:155365$8943 - assign { } { } - assign $1\sr_op__rc__rc[0:0] 1'0 - sync always - sync init - update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] - end - attribute \src "libresoc.v:155374.7-155374.30" - process $proc$libresoc.v:155374$8944 - assign { } { } - assign $1\sr_op__write_cr0[0:0] 1'0 - sync always - sync init - update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] - end - attribute \src "libresoc.v:155383.13-155383.26" - process $proc$libresoc.v:155383$8945 - assign { } { } - assign $1\xer_ca[1:0] 2'00 - sync always - sync init - update \xer_ca $1\xer_ca[1:0] - end - attribute \src "libresoc.v:155394.7-155394.23" - process $proc$libresoc.v:155394$8946 - assign { } { } - assign $1\xer_ca_ok[0:0] 1'0 - sync always - sync init - update \xer_ca_ok $1\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:155403.7-155403.20" - process $proc$libresoc.v:155403$8947 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:155412.7-155412.23" - process $proc$libresoc.v:155412$8948 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:155420.3-155421.29" - process $proc$libresoc.v:155420$8822 - assign { } { } - assign $0\xer_ca[1:0] \xer_ca$next - sync posedge \coresync_clk - update \xer_ca $0\xer_ca[1:0] - end - attribute \src "libresoc.v:155422.3-155423.35" - process $proc$libresoc.v:155422$8823 - assign { } { } - assign $0\xer_ca_ok[0:0] \xer_ca_ok$next - sync posedge \coresync_clk - update \xer_ca_ok $0\xer_ca_ok[0:0] - end - attribute \src "libresoc.v:155424.3-155425.29" - process $proc$libresoc.v:155424$8824 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:155426.3-155427.35" - process $proc$libresoc.v:155426$8825 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:155428.3-155429.25" - process $proc$libresoc.v:155428$8826 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:155430.3-155431.31" - process $proc$libresoc.v:155430$8827 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:155432.3-155433.19" - process $proc$libresoc.v:155432$8828 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:155434.3-155435.25" - process $proc$libresoc.v:155434$8829 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:155436.3-155437.49" - process $proc$libresoc.v:155436$8830 - assign { } { } - assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next - sync posedge \coresync_clk - update \sr_op__insn_type $0\sr_op__insn_type[6:0] - end - attribute \src "libresoc.v:155438.3-155439.45" - process $proc$libresoc.v:155438$8831 - assign { } { } - assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next - sync posedge \coresync_clk - update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:155440.3-155441.59" - process $proc$libresoc.v:155440$8832 - assign { } { } - assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next - sync posedge \coresync_clk - update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:155442.3-155443.55" - process $proc$libresoc.v:155442$8833 - assign { } { } - assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next - sync posedge \coresync_clk - update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:155444.3-155445.43" - process $proc$libresoc.v:155444$8834 - assign { } { } - assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next - sync posedge \coresync_clk - update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] - end - attribute \src "libresoc.v:155446.3-155447.43" - process $proc$libresoc.v:155446$8835 - assign { } { } - assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next - sync posedge \coresync_clk - update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] - end - attribute \src "libresoc.v:155448.3-155449.43" - process $proc$libresoc.v:155448$8836 - assign { } { } - assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next - sync posedge \coresync_clk - update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] - end - attribute \src "libresoc.v:155450.3-155451.43" - process $proc$libresoc.v:155450$8837 - assign { } { } - assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next - sync posedge \coresync_clk - update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] - end - attribute \src "libresoc.v:155452.3-155453.49" - process $proc$libresoc.v:155452$8838 - assign { } { } - assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next - sync posedge \coresync_clk - update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] - end - attribute \src "libresoc.v:155454.3-155455.49" - process $proc$libresoc.v:155454$8839 - assign { } { } - assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next - sync posedge \coresync_clk - update \sr_op__invert_in $0\sr_op__invert_in[0:0] - end - attribute \src "libresoc.v:155456.3-155457.53" - process $proc$libresoc.v:155456$8840 - assign { } { } - assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next - sync posedge \coresync_clk - update \sr_op__input_carry $0\sr_op__input_carry[1:0] - end - attribute \src "libresoc.v:155458.3-155459.55" - process $proc$libresoc.v:155458$8841 - assign { } { } - assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next - sync posedge \coresync_clk - update \sr_op__output_carry $0\sr_op__output_carry[0:0] - end - attribute \src "libresoc.v:155460.3-155461.47" - process $proc$libresoc.v:155460$8842 - assign { } { } - assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next - sync posedge \coresync_clk - update \sr_op__input_cr $0\sr_op__input_cr[0:0] - end - attribute \src "libresoc.v:155462.3-155463.49" - process $proc$libresoc.v:155462$8843 - assign { } { } - assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next - sync posedge \coresync_clk - update \sr_op__output_cr $0\sr_op__output_cr[0:0] - end - attribute \src "libresoc.v:155464.3-155465.47" - process $proc$libresoc.v:155464$8844 - assign { } { } - assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next - sync posedge \coresync_clk - update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:155466.3-155467.49" - process $proc$libresoc.v:155466$8845 - assign { } { } - assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next - sync posedge \coresync_clk - update \sr_op__is_signed $0\sr_op__is_signed[0:0] - end - attribute \src "libresoc.v:155468.3-155469.39" - process $proc$libresoc.v:155468$8846 - assign { } { } - assign $0\sr_op__insn[31:0] \sr_op__insn$next - sync posedge \coresync_clk - update \sr_op__insn $0\sr_op__insn[31:0] - end - attribute \src "libresoc.v:155470.3-155471.27" - process $proc$libresoc.v:155470$8847 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:155472.3-155473.29" - process $proc$libresoc.v:155472$8848 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:155576.3-155594.6" - process $proc$libresoc.v:155576$8849 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$next[1:0]$8851 $1\xer_ca$next[1:0]$8853 - assign $0\xer_ca_ok$next[0:0]$8850 $2\xer_ca_ok$next[0:0]$8854 - attribute \src "libresoc.v:155577.5-155577.29" - switch \initial - attribute \src "libresoc.v:155577.9-155577.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'001101 assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8852 $1\xer_ca$next[1:0]$8853 } { \xer_ca_ok$95 \xer_ca$94 } + assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'001111 assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8852 $1\xer_ca$next[1:0]$8853 } { \xer_ca_ok$95 \xer_ca$94 } - case - assign $1\xer_ca_ok$next[0:0]$8852 \xer_ca_ok - assign $1\xer_ca$next[1:0]$8853 \xer_ca - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'011100 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8854 1'0 - case - assign $2\xer_ca_ok$next[0:0]$8854 $1\xer_ca_ok$next[0:0]$8852 - end - sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8850 - update \xer_ca$next $0\xer_ca$next[1:0]$8851 - end - attribute \src "libresoc.v:155595.3-155612.6" - process $proc$libresoc.v:155595$8855 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8856 $2\r_busy$next[0:0]$8858 - attribute \src "libresoc.v:155596.5-155596.29" - switch \initial - attribute \src "libresoc.v:155596.9-155596.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'011101 assign { } { } - assign $1\r_busy$next[0:0]$8857 1'1 + assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'010010 assign { } { } - assign $1\r_busy$next[0:0]$8857 1'0 - case - assign $1\r_busy$next[0:0]$8857 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'010000 assign { } { } - assign $2\r_busy$next[0:0]$8858 1'0 - case - assign $2\r_busy$next[0:0]$8858 $1\r_busy$next[0:0]$8857 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8856 - end - attribute \src "libresoc.v:155613.3-155625.6" - process $proc$libresoc.v:155613$8859 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$8860 $1\muxid$next[1:0]$8861 - attribute \src "libresoc.v:155614.5-155614.29" - switch \initial - attribute \src "libresoc.v:155614.9-155614.17" - case 1'1 + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 case + assign $1\br[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 32'000000---------------0100000000- assign { } { } - assign $1\muxid$next[1:0]$8861 \muxid$67 + assign $2\br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\muxid$next[1:0]$8861 \muxid$67 + assign $2\br[0:0] 1'0 case - assign $1\muxid$next[1:0]$8861 \muxid + assign $2\br[0:0] $1\br[0:0] end sync always - update \muxid$next $0\muxid$next[1:0]$8860 + update \br $0\br[0:0] end - attribute \src "libresoc.v:155626.3-155666.6" - process $proc$libresoc.v:155626$8862 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:5512.3-5653.6" + process $proc$libresoc.v:5512$253 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr_op__fn_unit$next[11:0]$8863 $1\sr_op__fn_unit$next[11:0]$8880 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$next[1:0]$8866 $1\sr_op__input_carry$next[1:0]$8883 - assign $0\sr_op__input_cr$next[0:0]$8867 $1\sr_op__input_cr$next[0:0]$8884 - assign $0\sr_op__insn$next[31:0]$8868 $1\sr_op__insn$next[31:0]$8885 - assign $0\sr_op__insn_type$next[6:0]$8869 $1\sr_op__insn_type$next[6:0]$8886 - assign $0\sr_op__invert_in$next[0:0]$8870 $1\sr_op__invert_in$next[0:0]$8887 - assign $0\sr_op__is_32bit$next[0:0]$8871 $1\sr_op__is_32bit$next[0:0]$8888 - assign $0\sr_op__is_signed$next[0:0]$8872 $1\sr_op__is_signed$next[0:0]$8889 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$next[0:0]$8875 $1\sr_op__output_carry$next[0:0]$8892 - assign $0\sr_op__output_cr$next[0:0]$8876 $1\sr_op__output_cr$next[0:0]$8893 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$8879 $1\sr_op__write_cr0$next[0:0]$8896 - assign $0\sr_op__imm_data__data$next[63:0]$8864 $2\sr_op__imm_data__data$next[63:0]$8897 - assign $0\sr_op__imm_data__ok$next[0:0]$8865 $2\sr_op__imm_data__ok$next[0:0]$8898 - assign $0\sr_op__oe__oe$next[0:0]$8873 $2\sr_op__oe__oe$next[0:0]$8899 - assign $0\sr_op__oe__ok$next[0:0]$8874 $2\sr_op__oe__ok$next[0:0]$8900 - assign $0\sr_op__rc__ok$next[0:0]$8877 $2\sr_op__rc__ok$next[0:0]$8901 - assign $0\sr_op__rc__rc$next[0:0]$8878 $2\sr_op__rc__rc$next[0:0]$8902 - attribute \src "libresoc.v:155627.5-155627.29" + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:5513.5-5513.29" switch \initial - attribute \src "libresoc.v:155627.9-155627.17" + attribute \src "libresoc.v:5513.9-5513.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign { $1\sr_op__insn$next[31:0]$8885 $1\sr_op__is_signed$next[0:0]$8889 $1\sr_op__is_32bit$next[0:0]$8888 $1\sr_op__output_cr$next[0:0]$8893 $1\sr_op__input_cr$next[0:0]$8884 $1\sr_op__output_carry$next[0:0]$8892 $1\sr_op__input_carry$next[1:0]$8883 $1\sr_op__invert_in$next[0:0]$8887 $1\sr_op__write_cr0$next[0:0]$8896 $1\sr_op__oe__ok$next[0:0]$8891 $1\sr_op__oe__oe$next[0:0]$8890 $1\sr_op__rc__ok$next[0:0]$8894 $1\sr_op__rc__rc$next[0:0]$8895 $1\sr_op__imm_data__ok$next[0:0]$8882 $1\sr_op__imm_data__data$next[63:0]$8881 $1\sr_op__fn_unit$next[11:0]$8880 $1\sr_op__insn_type$next[6:0]$8886 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101010 assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign { $1\sr_op__insn$next[31:0]$8885 $1\sr_op__is_signed$next[0:0]$8889 $1\sr_op__is_32bit$next[0:0]$8888 $1\sr_op__output_cr$next[0:0]$8893 $1\sr_op__input_cr$next[0:0]$8884 $1\sr_op__output_carry$next[0:0]$8892 $1\sr_op__input_carry$next[1:0]$8883 $1\sr_op__invert_in$next[0:0]$8887 $1\sr_op__write_cr0$next[0:0]$8896 $1\sr_op__oe__ok$next[0:0]$8891 $1\sr_op__oe__oe$next[0:0]$8890 $1\sr_op__rc__ok$next[0:0]$8894 $1\sr_op__rc__rc$next[0:0]$8895 $1\sr_op__imm_data__ok$next[0:0]$8882 $1\sr_op__imm_data__data$next[63:0]$8881 $1\sr_op__fn_unit$next[11:0]$8880 $1\sr_op__insn_type$next[6:0]$8886 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } - case - assign $1\sr_op__fn_unit$next[11:0]$8880 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$8881 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$8882 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$8883 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$8884 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$8885 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$8886 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$8887 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$8888 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$8889 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$8890 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$8891 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$8892 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$8893 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$8894 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$8895 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$8896 \sr_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100101 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$8897 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$8898 1'0 - assign $2\sr_op__rc__rc$next[0:0]$8902 1'0 - assign $2\sr_op__rc__ok$next[0:0]$8901 1'0 - assign $2\sr_op__oe__oe$next[0:0]$8899 1'0 - assign $2\sr_op__oe__ok$next[0:0]$8900 1'0 - case - assign $2\sr_op__imm_data__data$next[63:0]$8897 $1\sr_op__imm_data__data$next[63:0]$8881 - assign $2\sr_op__imm_data__ok$next[0:0]$8898 $1\sr_op__imm_data__ok$next[0:0]$8882 - assign $2\sr_op__oe__oe$next[0:0]$8899 $1\sr_op__oe__oe$next[0:0]$8890 - assign $2\sr_op__oe__ok$next[0:0]$8900 $1\sr_op__oe__ok$next[0:0]$8891 - assign $2\sr_op__rc__ok$next[0:0]$8901 $1\sr_op__rc__ok$next[0:0]$8894 - assign $2\sr_op__rc__rc$next[0:0]$8902 $1\sr_op__rc__rc$next[0:0]$8895 - end - sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8863 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8864 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8865 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8866 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8867 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8868 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8869 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$8870 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8871 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8872 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8873 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8874 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8875 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8876 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8877 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8878 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8879 - end - attribute \src "libresoc.v:155667.3-155685.6" - process $proc$libresoc.v:155667$8903 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$8904 $1\o$next[63:0]$8906 - assign { } { } - assign $0\o_ok$next[0:0]$8905 $2\o_ok$next[0:0]$8908 - attribute \src "libresoc.v:155668.5-155668.29" - switch \initial - attribute \src "libresoc.v:155668.9-155668.17" - case 1'1 + assign $1\sgn_ext[0:0] 1'0 case + assign $1\sgn_ext[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } + case 32'000000---------------0100000000- assign { } { } - assign { $1\o_ok$next[0:0]$8907 $1\o$next[63:0]$8906 } { \o_ok$86 \o$85 } + assign $2\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1610612736 assign { } { } - assign { $1\o_ok$next[0:0]$8907 $1\o$next[63:0]$8906 } { \o_ok$86 \o$85 } - case - assign $1\o$next[63:0]$8906 \o - assign $1\o_ok$next[0:0]$8907 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $2\sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000001---------------0000000011- assign { } { } - assign $2\o_ok$next[0:0]$8908 1'0 + assign $2\sgn_ext[0:0] 1'0 case - assign $2\o_ok$next[0:0]$8908 $1\o_ok$next[0:0]$8907 + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] end sync always - update \o$next $0\o$next[63:0]$8904 - update \o_ok$next $0\o_ok$next[0:0]$8905 + update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:155686.3-155704.6" - process $proc$libresoc.v:155686$8909 - assign { } { } + attribute \src "libresoc.v:5654.3-5795.6" + process $proc$libresoc.v:5654$254 assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8910 $1\cr_a$next[3:0]$8912 - assign { } { } - assign $0\cr_a_ok$next[0:0]$8911 $2\cr_a_ok$next[0:0]$8914 - attribute \src "libresoc.v:155687.5-155687.29" + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:5655.5-5655.29" switch \initial - attribute \src "libresoc.v:155687.9-155687.17" + attribute \src "libresoc.v:5655.9-5655.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } - assign { $1\cr_a_ok$next[0:0]$8913 $1\cr_a$next[3:0]$8912 } { \cr_a_ok$88 \cr_a$87 } + assign $1\rsrv[0:0] \dec30_dec30_rsrv attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011111 assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } - assign { $1\cr_a_ok$next[0:0]$8913 $1\cr_a$next[3:0]$8912 } { \cr_a_ok$88 \cr_a$87 } - case - assign $1\cr_a$next[3:0]$8912 \cr_a - assign $1\cr_a_ok$next[0:0]$8913 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\rsrv[0:0] \dec58_dec58_rsrv attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'111110 assign { } { } - assign $2\cr_a_ok$next[0:0]$8914 1'0 - case - assign $2\cr_a_ok$next[0:0]$8914 $1\cr_a_ok$next[0:0]$8913 - end - sync always - update \cr_a$next $0\cr_a$next[3:0]$8910 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8911 - end - attribute \src "libresoc.v:155705.3-155723.6" - process $proc$libresoc.v:155705$8915 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$next[0:0]$8916 $1\xer_so$next[0:0]$8918 - assign { } { } - assign $0\xer_so_ok$next[0:0]$8917 $2\xer_so_ok$next[0:0]$8920 - attribute \src "libresoc.v:155706.5-155706.29" - switch \initial - attribute \src "libresoc.v:155706.9-155706.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\rsrv[0:0] \dec62_dec62_rsrv attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'001100 assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8919 $1\xer_so$next[0:0]$8918 } { \xer_so_ok$92 \xer_so$91 } + assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'001110 assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign { $1\xer_so_ok$next[0:0]$8919 $1\xer_so$next[0:0]$8918 } { \xer_so_ok$92 \xer_so$91 } - case - assign $1\xer_so$next[0:0]$8918 \xer_so - assign $1\xer_so_ok$next[0:0]$8919 \xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'010001 assign { } { } - assign $2\xer_so_ok$next[0:0]$8920 1'0 - case - assign $2\xer_so_ok$next[0:0]$8920 $1\xer_so_ok$next[0:0]$8919 - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$8916 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8917 - end - connect \$65 $and$libresoc.v:155419$8821_Y - connect \cr_a$89 4'0000 - connect \cr_a_ok$90 1'0 - connect \xer_so_ok$93 1'0 - connect \xer_ca_ok$96 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } - connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } - connect { \cr_a_ok$88 \cr_a$87 } 5'00000 - connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } - connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } - connect \muxid$67 \main_muxid$44 - connect \p_valid_i_p_ready_o \$65 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$64 \p_valid_i - connect \xer_ca$63 \input_xer_ca$43 - connect \main_xer_so \input_xer_so$42 - connect \main_rc \input_rc$41 - connect \main_rb \input_rb$40 - connect \main_ra \input_ra$39 - connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } - connect \main_muxid \input_muxid$21 - connect \input_xer_ca \xer_ca$20 - connect \input_xer_so \xer_so$19 - connect \input_rc \rc - connect \input_rb \rb - connect \input_ra \ra - connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:155757.1-156590.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" -attribute \generator "nMigen" -module \pipe1$32 - attribute \src "libresoc.v:156547.3-156559.6" - wire width 64 $0\fast1$next[63:0]$8998 - attribute \src "libresoc.v:156401.3-156402.27" - wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:156560.3-156572.6" - wire width 64 $0\fast2$next[63:0]$9001 - attribute \src "libresoc.v:156429.3-156430.27" - wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:155758.7-155758.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:156487.3-156499.6" - wire width 2 $0\muxid$next[1:0]$8970 - attribute \src "libresoc.v:156425.3-156426.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:156469.3-156486.6" - wire $0\r_busy$next[0:0]$8966 - attribute \src "libresoc.v:156427.3-156428.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:156521.3-156533.6" - wire width 64 $0\ra$next[63:0]$8992 - attribute \src "libresoc.v:156405.3-156406.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:156534.3-156546.6" - wire width 64 $0\rb$next[63:0]$8995 - attribute \src "libresoc.v:156403.3-156404.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 64 $0\trap_op__cia$next[63:0]$8973 - attribute \src "libresoc.v:156415.3-156416.41" - wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 12 $0\trap_op__fn_unit$next[11:0]$8974 - attribute \src "libresoc.v:156409.3-156410.49" - wire width 12 $0\trap_op__fn_unit[11:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 32 $0\trap_op__insn$next[31:0]$8975 - attribute \src "libresoc.v:156411.3-156412.43" - wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$8976 - attribute \src "libresoc.v:156407.3-156408.53" - wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire $0\trap_op__is_32bit$next[0:0]$8977 - attribute \src "libresoc.v:156417.3-156418.51" - wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$8978 - attribute \src "libresoc.v:156423.3-156424.51" - wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 64 $0\trap_op__msr$next[63:0]$8979 - attribute \src "libresoc.v:156413.3-156414.41" - wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$8980 - attribute \src "libresoc.v:156421.3-156422.51" - wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 8 $0\trap_op__traptype$next[7:0]$8981 - attribute \src "libresoc.v:156419.3-156420.51" - wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:156547.3-156559.6" - wire width 64 $1\fast1$next[63:0]$8999 - attribute \src "libresoc.v:155997.14-155997.42" - wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:156560.3-156572.6" - wire width 64 $1\fast2$next[63:0]$9002 - attribute \src "libresoc.v:156006.14-156006.42" - wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:156487.3-156499.6" - wire width 2 $1\muxid$next[1:0]$8971 - attribute \src "libresoc.v:156015.13-156015.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:156469.3-156486.6" - wire $1\r_busy$next[0:0]$8967 - attribute \src "libresoc.v:156037.7-156037.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:156521.3-156533.6" - wire width 64 $1\ra$next[63:0]$8993 - attribute \src "libresoc.v:156042.14-156042.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:156534.3-156546.6" - wire width 64 $1\rb$next[63:0]$8996 - attribute \src "libresoc.v:156051.14-156051.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 64 $1\trap_op__cia$next[63:0]$8982 - attribute \src "libresoc.v:156060.14-156060.49" - wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 12 $1\trap_op__fn_unit$next[11:0]$8983 - attribute \src "libresoc.v:156082.14-156082.40" - wire width 12 $1\trap_op__fn_unit[11:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 32 $1\trap_op__insn$next[31:0]$8984 - attribute \src "libresoc.v:156117.14-156117.35" - wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$8985 - attribute \src "libresoc.v:156200.13-156200.39" - wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire $1\trap_op__is_32bit$next[0:0]$8986 - attribute \src "libresoc.v:156357.7-156357.31" - wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$8987 - attribute \src "libresoc.v:156366.13-156366.38" - wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 64 $1\trap_op__msr$next[63:0]$8988 - attribute \src "libresoc.v:156375.14-156375.49" - wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$8989 - attribute \src "libresoc.v:156384.14-156384.42" - wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:156500.3-156520.6" - wire width 8 $1\trap_op__traptype$next[7:0]$8990 - attribute \src "libresoc.v:156393.13-156393.38" - wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:156469.3-156486.6" - wire $2\r_busy$next[0:0]$8968 - attribute \src "libresoc.v:156400.18-156400.118" - wire $and$libresoc.v:156400$8949_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast1$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_fast2$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \dummy_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \dummy_muxid$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_ra$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \dummy_rb$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dummy_trap_op__cia$20 - attribute \enum_base_type "Function" - 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"OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 21 \trap_op__insn_type$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 26 \trap_op__is_32bit$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \trap_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 13 \trap_op__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 29 \trap_op__ldst_exc$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__ldst_exc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 8 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 24 \trap_op__msr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 output 12 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 28 \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 output 11 \trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 27 \trap_op__traptype$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \trap_op__traptype$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:156400$8949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$29 - connect \B \p_ready_o - connect \Y $and$libresoc.v:156400$8949_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:156431.9-156460.4" - cell \dummy \dummy - connect \fast1 \dummy_fast1 - connect \fast1$13 \dummy_fast1$27 - connect \fast2 \dummy_fast2 - connect \fast2$14 \dummy_fast2$28 - connect \muxid \dummy_muxid - connect \muxid$1 \dummy_muxid$15 - connect \ra \dummy_ra - connect \ra$11 \dummy_ra$25 - connect \rb \dummy_rb - connect \rb$12 \dummy_rb$26 - connect \trap_op__cia \dummy_trap_op__cia - connect \trap_op__cia$6 \dummy_trap_op__cia$20 - connect \trap_op__fn_unit \dummy_trap_op__fn_unit - connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 - connect \trap_op__insn \dummy_trap_op__insn - connect \trap_op__insn$4 \dummy_trap_op__insn$18 - connect \trap_op__insn_type \dummy_trap_op__insn_type - connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 - connect \trap_op__is_32bit \dummy_trap_op__is_32bit - connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 - connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc - connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 - connect \trap_op__msr \dummy_trap_op__msr - connect \trap_op__msr$5 \dummy_trap_op__msr$19 - connect \trap_op__trapaddr \dummy_trap_op__trapaddr - connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 - connect \trap_op__traptype \dummy_trap_op__traptype - connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:156461.10-156464.4" - cell \n$34 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:156465.10-156468.4" - cell \p$33 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:155758.7-155758.20" - process $proc$libresoc.v:155758$9003 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:155997.14-155997.42" - process $proc$libresoc.v:155997$9004 - assign { } { } - assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast1 $1\fast1[63:0] - end - attribute \src "libresoc.v:156006.14-156006.42" - process $proc$libresoc.v:156006$9005 - assign { } { } - assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast2 $1\fast2[63:0] - end - attribute \src "libresoc.v:156015.13-156015.25" - process $proc$libresoc.v:156015$9006 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:156037.7-156037.20" - process $proc$libresoc.v:156037$9007 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:156042.14-156042.39" - process $proc$libresoc.v:156042$9008 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] - end - attribute \src "libresoc.v:156051.14-156051.39" - process $proc$libresoc.v:156051$9009 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] - end - attribute \src "libresoc.v:156060.14-156060.49" - process $proc$libresoc.v:156060$9010 - assign { } { } - assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \trap_op__cia $1\trap_op__cia[63:0] - end - attribute \src "libresoc.v:156082.14-156082.40" - process $proc$libresoc.v:156082$9011 - assign { } { } - assign $1\trap_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \trap_op__fn_unit $1\trap_op__fn_unit[11:0] - end - attribute \src "libresoc.v:156117.14-156117.35" - process $proc$libresoc.v:156117$9012 - assign { } { } - assign $1\trap_op__insn[31:0] 0 - sync always - sync init - update \trap_op__insn $1\trap_op__insn[31:0] - end - attribute \src "libresoc.v:156200.13-156200.39" - process $proc$libresoc.v:156200$9013 - assign { } { } - assign $1\trap_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \trap_op__insn_type $1\trap_op__insn_type[6:0] - end - attribute \src "libresoc.v:156357.7-156357.31" - process $proc$libresoc.v:156357$9014 - assign { } { } - assign $1\trap_op__is_32bit[0:0] 1'0 - sync always - sync init - update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] - end - attribute \src "libresoc.v:156366.13-156366.38" - process $proc$libresoc.v:156366$9015 - assign { } { } - assign $1\trap_op__ldst_exc[7:0] 8'00000000 - sync always - sync init - update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] - end - attribute \src "libresoc.v:156375.14-156375.49" - process $proc$libresoc.v:156375$9016 - assign { } { } - assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \trap_op__msr $1\trap_op__msr[63:0] - end - attribute \src "libresoc.v:156384.14-156384.42" - process $proc$libresoc.v:156384$9017 - assign { } { } - assign $1\trap_op__trapaddr[12:0] 13'0000000000000 - sync always - sync init - update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] - end - attribute \src "libresoc.v:156393.13-156393.38" - process $proc$libresoc.v:156393$9018 - assign { } { } - assign $1\trap_op__traptype[7:0] 8'00000000 - sync always - sync init - update \trap_op__traptype $1\trap_op__traptype[7:0] - end - attribute \src "libresoc.v:156401.3-156402.27" - process $proc$libresoc.v:156401$8950 - assign { } { } - assign $0\fast1[63:0] \fast1$next - sync posedge \coresync_clk - update \fast1 $0\fast1[63:0] - end - attribute \src "libresoc.v:156403.3-156404.21" - process $proc$libresoc.v:156403$8951 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] - end - attribute \src "libresoc.v:156405.3-156406.21" - process $proc$libresoc.v:156405$8952 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] - end - attribute \src "libresoc.v:156407.3-156408.53" - process $proc$libresoc.v:156407$8953 - assign { } { } - assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next - sync posedge \coresync_clk - update \trap_op__insn_type $0\trap_op__insn_type[6:0] - end - attribute \src "libresoc.v:156409.3-156410.49" - process $proc$libresoc.v:156409$8954 - assign { } { } - assign $0\trap_op__fn_unit[11:0] \trap_op__fn_unit$next - sync posedge \coresync_clk - update \trap_op__fn_unit $0\trap_op__fn_unit[11:0] - end - attribute \src "libresoc.v:156411.3-156412.43" - process $proc$libresoc.v:156411$8955 - assign { } { } - assign $0\trap_op__insn[31:0] \trap_op__insn$next - sync posedge \coresync_clk - update \trap_op__insn $0\trap_op__insn[31:0] - end - attribute \src "libresoc.v:156413.3-156414.41" - process $proc$libresoc.v:156413$8956 - assign { } { } - assign $0\trap_op__msr[63:0] \trap_op__msr$next - sync posedge \coresync_clk - update \trap_op__msr $0\trap_op__msr[63:0] - end - attribute \src "libresoc.v:156415.3-156416.41" - process $proc$libresoc.v:156415$8957 - assign { } { } - assign $0\trap_op__cia[63:0] \trap_op__cia$next - sync posedge \coresync_clk - update \trap_op__cia $0\trap_op__cia[63:0] - end - attribute \src "libresoc.v:156417.3-156418.51" - process $proc$libresoc.v:156417$8958 - assign { } { } - assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next - sync posedge \coresync_clk - update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] - end - attribute \src "libresoc.v:156419.3-156420.51" - process $proc$libresoc.v:156419$8959 - assign { } { } - assign $0\trap_op__traptype[7:0] \trap_op__traptype$next - sync posedge \coresync_clk - update \trap_op__traptype $0\trap_op__traptype[7:0] - end - attribute \src "libresoc.v:156421.3-156422.51" - process $proc$libresoc.v:156421$8960 - assign { } { } - assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next - sync posedge \coresync_clk - update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] - end - attribute \src "libresoc.v:156423.3-156424.51" - process $proc$libresoc.v:156423$8961 - assign { } { } - assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next - sync posedge \coresync_clk - update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] - end - attribute \src "libresoc.v:156425.3-156426.27" - process $proc$libresoc.v:156425$8962 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:156427.3-156428.29" - process $proc$libresoc.v:156427$8963 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] - end - attribute \src "libresoc.v:156429.3-156430.27" - process $proc$libresoc.v:156429$8964 - assign { } { } - assign $0\fast2[63:0] \fast2$next - sync posedge \coresync_clk - update \fast2 $0\fast2[63:0] - end - attribute \src "libresoc.v:156469.3-156486.6" - process $proc$libresoc.v:156469$8965 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$8966 $2\r_busy$next[0:0]$8968 - attribute \src "libresoc.v:156470.5-156470.29" - switch \initial - attribute \src "libresoc.v:156470.9-156470.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'100010 assign { } { } - assign $1\r_busy$next[0:0]$8967 1'1 + assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'100011 assign { } { } - assign $1\r_busy$next[0:0]$8967 1'0 - case - assign $1\r_busy$next[0:0]$8967 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'101010 assign { } { } - assign $2\r_busy$next[0:0]$8968 1'0 - case - assign $2\r_busy$next[0:0]$8968 $1\r_busy$next[0:0]$8967 - end - sync always - update \r_busy$next $0\r_busy$next[0:0]$8966 - end - attribute \src "libresoc.v:156487.3-156499.6" - process $proc$libresoc.v:156487$8969 - assign { } { } - assign { } { } - assign $0\muxid$next[1:0]$8970 $1\muxid$next[1:0]$8971 - attribute \src "libresoc.v:156488.5-156488.29" - switch \initial - attribute \src "libresoc.v:156488.9-156488.17" - case 1'1 + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 case + assign $1\rsrv[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 32'000000---------------0100000000- assign { } { } - assign $1\muxid$next[1:0]$8971 \muxid$32 + assign $2\rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $1\muxid$next[1:0]$8971 \muxid$32 + assign $2\rsrv[0:0] 1'0 case - assign $1\muxid$next[1:0]$8971 \muxid + assign $2\rsrv[0:0] $1\rsrv[0:0] end sync always - update \muxid$next $0\muxid$next[1:0]$8970 + update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:156500.3-156520.6" - process $proc$libresoc.v:156500$8972 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:5796.3-5937.6" + process $proc$libresoc.v:5796$255 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\trap_op__cia$next[63:0]$8973 $1\trap_op__cia$next[63:0]$8982 - assign $0\trap_op__fn_unit$next[11:0]$8974 $1\trap_op__fn_unit$next[11:0]$8983 - assign $0\trap_op__insn$next[31:0]$8975 $1\trap_op__insn$next[31:0]$8984 - assign $0\trap_op__insn_type$next[6:0]$8976 $1\trap_op__insn_type$next[6:0]$8985 - assign $0\trap_op__is_32bit$next[0:0]$8977 $1\trap_op__is_32bit$next[0:0]$8986 - assign $0\trap_op__ldst_exc$next[7:0]$8978 $1\trap_op__ldst_exc$next[7:0]$8987 - assign $0\trap_op__msr$next[63:0]$8979 $1\trap_op__msr$next[63:0]$8988 - assign $0\trap_op__trapaddr$next[12:0]$8980 $1\trap_op__trapaddr$next[12:0]$8989 - assign $0\trap_op__traptype$next[7:0]$8981 $1\trap_op__traptype$next[7:0]$8990 - attribute \src "libresoc.v:156501.5-156501.29" + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:5797.5-5797.29" switch \initial - attribute \src "libresoc.v:156501.9-156501.17" + attribute \src "libresoc.v:5797.9-5797.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$8987 $1\trap_op__trapaddr$next[12:0]$8989 $1\trap_op__traptype$next[7:0]$8990 $1\trap_op__is_32bit$next[0:0]$8986 $1\trap_op__cia$next[63:0]$8982 $1\trap_op__msr$next[63:0]$8988 $1\trap_op__insn$next[31:0]$8984 $1\trap_op__fn_unit$next[11:0]$8983 $1\trap_op__insn_type$next[6:0]$8985 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'010001 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$8987 $1\trap_op__trapaddr$next[12:0]$8989 $1\trap_op__traptype$next[7:0]$8990 $1\trap_op__is_32bit$next[0:0]$8986 $1\trap_op__cia$next[63:0]$8982 $1\trap_op__msr$next[63:0]$8988 $1\trap_op__insn$next[31:0]$8984 $1\trap_op__fn_unit$next[11:0]$8983 $1\trap_op__insn_type$next[6:0]$8985 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } - case - assign $1\trap_op__cia$next[63:0]$8982 \trap_op__cia - assign $1\trap_op__fn_unit$next[11:0]$8983 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$8984 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$8985 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$8986 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$8987 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$8988 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$8989 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$8990 \trap_op__traptype - end - sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$8973 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[11:0]$8974 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$8975 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$8976 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$8977 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$8978 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$8979 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$8980 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$8981 - end - attribute \src "libresoc.v:156521.3-156533.6" - process $proc$libresoc.v:156521$8991 - assign { } { } - assign { } { } - assign $0\ra$next[63:0]$8992 $1\ra$next[63:0]$8993 - attribute \src "libresoc.v:156522.5-156522.29" - switch \initial - attribute \src "libresoc.v:156522.9-156522.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'101010 assign { } { } - assign $1\ra$next[63:0]$8993 \ra$42 + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101011 assign { } { } - assign $1\ra$next[63:0]$8993 \ra$42 - case - assign $1\ra$next[63:0]$8993 \ra - end - sync always - update \ra$next $0\ra$next[63:0]$8992 - end - attribute \src "libresoc.v:156534.3-156546.6" - process $proc$libresoc.v:156534$8994 - assign { } { } - assign { } { } - assign $0\rb$next[63:0]$8995 $1\rb$next[63:0]$8996 - attribute \src "libresoc.v:156535.5-156535.29" - switch \initial - attribute \src "libresoc.v:156535.9-156535.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'101000 assign { } { } - assign $1\rb$next[63:0]$8996 \rb$43 + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101001 assign { } { } - assign $1\rb$next[63:0]$8996 \rb$43 - case - assign $1\rb$next[63:0]$8996 \rb - end - sync always - update \rb$next $0\rb$next[63:0]$8995 - end - attribute \src "libresoc.v:156547.3-156559.6" - process $proc$libresoc.v:156547$8997 - assign { } { } - assign { } { } - assign $0\fast1$next[63:0]$8998 $1\fast1$next[63:0]$8999 - attribute \src "libresoc.v:156548.5-156548.29" - switch \initial - attribute \src "libresoc.v:156548.9-156548.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'100000 assign { } { } - assign $1\fast1$next[63:0]$8999 \fast1$44 + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'100001 assign { } { } - assign $1\fast1$next[63:0]$8999 \fast1$44 - case - assign $1\fast1$next[63:0]$8999 \fast1 - end - sync always - update \fast1$next $0\fast1$next[63:0]$8998 - end - attribute \src "libresoc.v:156560.3-156572.6" - process $proc$libresoc.v:156560$9000 - assign { } { } - assign { } { } - assign $0\fast2$next[63:0]$9001 $1\fast2$next[63:0]$9002 - attribute \src "libresoc.v:156561.5-156561.29" - switch \initial - attribute \src "libresoc.v:156561.9-156561.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'000111 assign { } { } - assign $1\fast2$next[63:0]$9002 \fast2$45 + assign $1\is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011000 assign { } { } - assign $1\fast2$next[63:0]$9002 \fast2$45 - case - assign $1\fast2$next[63:0]$9002 \fast2 - end - sync always - update \fast2$next $0\fast2$next[63:0]$9001 - end - connect \$30 $and$libresoc.v:156400$8949_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \fast2$45 \dummy_fast2$28 - connect \fast1$44 \dummy_fast1$27 - connect \rb$43 \dummy_rb$26 - connect \ra$42 \dummy_ra$25 - connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } - connect \muxid$32 \dummy_muxid$15 - connect \p_valid_i_p_ready_o \$30 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$29 \p_valid_i - connect \dummy_fast2 \fast2$14 - connect \dummy_fast1 \fast1$13 - connect \dummy_rb \rb$12 - connect \dummy_ra \ra$11 - connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } - connect \dummy_muxid \muxid$1 -end -attribute \src "libresoc.v:156594.1-157764.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" -attribute \generator "nMigen" -module \pipe2 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9087 - attribute \src "libresoc.v:157505.3-157506.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9073 - attribute \src "libresoc.v:156602.13-156602.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9161 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 12 $0\alu_op__fn_unit$3$next[11:0]$9088 - attribute \src "libresoc.v:157475.3-157476.53" - wire width 12 $0\alu_op__fn_unit$3[11:0]$9043 - attribute \src "libresoc.v:156637.14-156637.43" - wire width 12 $0\alu_op__fn_unit$3[11:0]$9163 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9089 - attribute \src "libresoc.v:157477.3-157478.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9045 - attribute \src "libresoc.v:156659.14-156659.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9165 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9090 - attribute \src "libresoc.v:157479.3-157480.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9047 - attribute \src "libresoc.v:156668.7-156668.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9167 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9091 - attribute \src "libresoc.v:157497.3-157498.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9065 - attribute \src "libresoc.v:156685.13-156685.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9169 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9092 - attribute \src "libresoc.v:157507.3-157508.49" - wire width 32 $0\alu_op__insn$19[31:0]$9075 - attribute \src "libresoc.v:156698.14-156698.39" - wire width 32 $0\alu_op__insn$19[31:0]$9171 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9093 - attribute \src "libresoc.v:157473.3-157474.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9041 - attribute \src "libresoc.v:156855.13-156855.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9173 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__invert_in$10$next[0:0]$9094 - attribute \src "libresoc.v:157489.3-157490.59" - wire $0\alu_op__invert_in$10[0:0]$9057 - attribute \src "libresoc.v:156938.7-156938.36" - wire $0\alu_op__invert_in$10[0:0]$9175 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__invert_out$12$next[0:0]$9095 - attribute \src "libresoc.v:157493.3-157494.61" - wire $0\alu_op__invert_out$12[0:0]$9061 - attribute \src "libresoc.v:156947.7-156947.37" - wire $0\alu_op__invert_out$12[0:0]$9177 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9096 - attribute \src "libresoc.v:157501.3-157502.57" - wire $0\alu_op__is_32bit$16[0:0]$9069 - attribute \src "libresoc.v:156956.7-156956.35" - wire $0\alu_op__is_32bit$16[0:0]$9179 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__is_signed$17$next[0:0]$9097 - attribute \src "libresoc.v:157503.3-157504.59" - wire $0\alu_op__is_signed$17[0:0]$9071 - attribute \src "libresoc.v:156965.7-156965.36" - wire $0\alu_op__is_signed$17[0:0]$9181 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9098 - attribute \src "libresoc.v:157485.3-157486.51" - wire $0\alu_op__oe__oe$8[0:0]$9053 - attribute \src "libresoc.v:156976.7-156976.32" - wire $0\alu_op__oe__oe$8[0:0]$9183 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9099 - attribute \src "libresoc.v:157487.3-157488.51" - wire $0\alu_op__oe__ok$9[0:0]$9055 - attribute \src "libresoc.v:156985.7-156985.32" - wire $0\alu_op__oe__ok$9[0:0]$9185 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__output_carry$15$next[0:0]$9100 - attribute \src "libresoc.v:157499.3-157500.65" - wire $0\alu_op__output_carry$15[0:0]$9067 - attribute \src "libresoc.v:156992.7-156992.39" - wire $0\alu_op__output_carry$15[0:0]$9187 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9101 - attribute \src "libresoc.v:157483.3-157484.51" - wire $0\alu_op__rc__ok$7[0:0]$9051 - attribute \src "libresoc.v:157003.7-157003.32" - wire $0\alu_op__rc__ok$7[0:0]$9189 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9102 - attribute \src "libresoc.v:157481.3-157482.51" - wire $0\alu_op__rc__rc$6[0:0]$9049 - attribute \src "libresoc.v:157010.7-157010.32" - wire $0\alu_op__rc__rc$6[0:0]$9191 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9103 - attribute \src "libresoc.v:157495.3-157496.59" - wire $0\alu_op__write_cr0$13[0:0]$9063 - attribute \src "libresoc.v:157019.7-157019.36" - wire $0\alu_op__write_cr0$13[0:0]$9193 - attribute \src "libresoc.v:157608.3-157649.6" - wire $0\alu_op__zero_a$11$next[0:0]$9104 - attribute \src "libresoc.v:157491.3-157492.53" - wire $0\alu_op__zero_a$11[0:0]$9059 - attribute \src "libresoc.v:157028.7-157028.33" - wire $0\alu_op__zero_a$11[0:0]$9195 - attribute \src "libresoc.v:157669.3-157687.6" - wire width 4 $0\cr_a$22$next[3:0]$9136 - attribute \src "libresoc.v:157465.3-157466.33" - wire width 4 $0\cr_a$22[3:0]$9033 - attribute \src "libresoc.v:157041.13-157041.29" - wire width 4 $0\cr_a$22[3:0]$9197 - attribute \src "libresoc.v:157669.3-157687.6" - wire $0\cr_a_ok$23$next[0:0]$9137 - attribute \src "libresoc.v:157467.3-157468.39" - wire $0\cr_a_ok$23[0:0]$9035 - attribute \src "libresoc.v:157050.7-157050.26" - wire $0\cr_a_ok$23[0:0]$9199 - attribute \src "libresoc.v:156595.7-156595.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:157595.3-157607.6" - wire width 2 $0\muxid$1$next[1:0]$9084 - attribute \src "libresoc.v:157509.3-157510.33" - wire width 2 $0\muxid$1[1:0]$9077 - attribute \src "libresoc.v:157061.13-157061.29" - wire width 2 $0\muxid$1[1:0]$9201 - attribute \src "libresoc.v:157650.3-157668.6" - wire width 64 $0\o$20$next[63:0]$9130 - attribute \src "libresoc.v:157469.3-157470.27" - wire width 64 $0\o$20[63:0]$9037 - attribute \src "libresoc.v:157076.14-157076.43" - wire width 64 $0\o$20[63:0]$9203 - attribute \src "libresoc.v:157650.3-157668.6" - wire $0\o_ok$21$next[0:0]$9131 - attribute \src "libresoc.v:157471.3-157472.33" - wire $0\o_ok$21[0:0]$9039 - attribute \src "libresoc.v:157085.7-157085.23" - wire $0\o_ok$21[0:0]$9205 - attribute \src "libresoc.v:157577.3-157594.6" - wire $0\r_busy$next[0:0]$9080 - attribute \src "libresoc.v:157511.3-157512.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:157688.3-157706.6" - wire width 2 $0\xer_ca$24$next[1:0]$9142 - attribute \src "libresoc.v:157461.3-157462.37" - wire width 2 $0\xer_ca$24[1:0]$9029 - attribute \src "libresoc.v:157396.13-157396.31" - wire width 2 $0\xer_ca$24[1:0]$9208 - attribute \src "libresoc.v:157688.3-157706.6" - wire $0\xer_ca_ok$25$next[0:0]$9143 - attribute \src "libresoc.v:157463.3-157464.43" - wire $0\xer_ca_ok$25[0:0]$9031 - attribute \src "libresoc.v:157405.7-157405.28" - wire $0\xer_ca_ok$25[0:0]$9210 - attribute \src "libresoc.v:157707.3-157725.6" - wire width 2 $0\xer_ov$26$next[1:0]$9148 - attribute \src "libresoc.v:157457.3-157458.37" - wire width 2 $0\xer_ov$26[1:0]$9025 - attribute \src "libresoc.v:157416.13-157416.31" - wire width 2 $0\xer_ov$26[1:0]$9212 - attribute \src "libresoc.v:157707.3-157725.6" - wire $0\xer_ov_ok$27$next[0:0]$9149 - attribute \src "libresoc.v:157459.3-157460.43" - wire $0\xer_ov_ok$27[0:0]$9027 - attribute \src "libresoc.v:157425.7-157425.28" - wire $0\xer_ov_ok$27[0:0]$9214 - attribute \src "libresoc.v:157726.3-157744.6" - wire $0\xer_so$28$next[0:0]$9154 - attribute \src "libresoc.v:157453.3-157454.37" - wire $0\xer_so$28[0:0]$9021 - attribute \src "libresoc.v:157436.7-157436.25" - wire $0\xer_so$28[0:0]$9216 - attribute \src "libresoc.v:157726.3-157744.6" - wire $0\xer_so_ok$29$next[0:0]$9155 - attribute \src "libresoc.v:157455.3-157456.43" - wire $0\xer_so_ok$29[0:0]$9023 - attribute \src "libresoc.v:157445.7-157445.28" - wire $0\xer_so_ok$29[0:0]$9218 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9105 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 12 $1\alu_op__fn_unit$3$next[11:0]$9106 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9107 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9108 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9109 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9110 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9111 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__invert_in$10$next[0:0]$9112 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__invert_out$12$next[0:0]$9113 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9114 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__is_signed$17$next[0:0]$9115 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9116 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9117 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__output_carry$15$next[0:0]$9118 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9119 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9120 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9121 - attribute \src "libresoc.v:157608.3-157649.6" - wire $1\alu_op__zero_a$11$next[0:0]$9122 - attribute \src "libresoc.v:157669.3-157687.6" - wire width 4 $1\cr_a$22$next[3:0]$9138 - attribute \src "libresoc.v:157669.3-157687.6" - wire $1\cr_a_ok$23$next[0:0]$9139 - attribute \src "libresoc.v:157595.3-157607.6" - wire width 2 $1\muxid$1$next[1:0]$9085 - attribute \src "libresoc.v:157650.3-157668.6" - wire width 64 $1\o$20$next[63:0]$9132 - attribute \src "libresoc.v:157650.3-157668.6" - wire $1\o_ok$21$next[0:0]$9133 - attribute \src "libresoc.v:157577.3-157594.6" - wire $1\r_busy$next[0:0]$9081 - attribute \src "libresoc.v:157389.7-157389.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:157688.3-157706.6" - wire width 2 $1\xer_ca$24$next[1:0]$9144 - attribute \src "libresoc.v:157688.3-157706.6" - wire $1\xer_ca_ok$25$next[0:0]$9145 - attribute \src "libresoc.v:157707.3-157725.6" - wire width 2 $1\xer_ov$26$next[1:0]$9150 - attribute \src "libresoc.v:157707.3-157725.6" - wire $1\xer_ov_ok$27$next[0:0]$9151 - attribute \src "libresoc.v:157726.3-157744.6" - wire $1\xer_so$28$next[0:0]$9156 - attribute \src "libresoc.v:157726.3-157744.6" - wire $1\xer_so_ok$29$next[0:0]$9157 - attribute \src "libresoc.v:157608.3-157649.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9123 - attribute \src "libresoc.v:157608.3-157649.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9124 - attribute \src "libresoc.v:157608.3-157649.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9125 - attribute \src "libresoc.v:157608.3-157649.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9126 - attribute \src "libresoc.v:157608.3-157649.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9127 - attribute \src "libresoc.v:157608.3-157649.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9128 - attribute \src "libresoc.v:157669.3-157687.6" - wire $2\cr_a_ok$23$next[0:0]$9140 - attribute \src "libresoc.v:157650.3-157668.6" - wire $2\o_ok$21$next[0:0]$9134 - attribute \src "libresoc.v:157577.3-157594.6" - wire $2\r_busy$next[0:0]$9082 - attribute \src "libresoc.v:157688.3-157706.6" - wire $2\xer_ca_ok$25$next[0:0]$9146 - attribute \src "libresoc.v:157707.3-157725.6" - wire $2\xer_ov_ok$27$next[0:0]$9152 - attribute \src "libresoc.v:157726.3-157744.6" - wire $2\xer_so_ok$29$next[0:0]$9158 - attribute \src "libresoc.v:157452.18-157452.118" - wire $and$libresoc.v:157452$9019_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$79 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \alu_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 37 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_op__fn_unit$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \alu_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__imm_data__ok$66 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 17 \alu_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 48 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$14$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$80 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \alu_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \alu_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$2$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__invert_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_32bit$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__is_signed$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__output_carry$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__rc__rc$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \alu_op__write_cr0$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__write_cr0$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 56 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 57 \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$84 - attribute \src "libresoc.v:156595.7-156595.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 33 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 54 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len$47 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:157452$9019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$59 - connect \B \p_ready_o - connect \Y $and$libresoc.v:157452$9019_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:157513.9-157516.4" - cell \n$4 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:157517.12-157572.4" - cell \output \output - connect \alu_op__data_len \output_alu_op__data_len - connect \alu_op__data_len$18 \output_alu_op__data_len$47 - connect \alu_op__fn_unit \output_alu_op__fn_unit - connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 - connect \alu_op__imm_data__data \output_alu_op__imm_data__data - connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 - connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok - connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 - connect \alu_op__input_carry \output_alu_op__input_carry - connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 - connect \alu_op__insn \output_alu_op__insn - connect \alu_op__insn$19 \output_alu_op__insn$48 - connect \alu_op__insn_type \output_alu_op__insn_type - connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 - connect \alu_op__invert_in \output_alu_op__invert_in - connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 - connect \alu_op__invert_out \output_alu_op__invert_out - connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 - connect \alu_op__is_32bit \output_alu_op__is_32bit - connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 - connect \alu_op__is_signed \output_alu_op__is_signed - connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 - connect \alu_op__oe__oe \output_alu_op__oe__oe - connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 - connect \alu_op__oe__ok \output_alu_op__oe__ok - connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 - connect \alu_op__output_carry \output_alu_op__output_carry - connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 - connect \alu_op__rc__ok \output_alu_op__rc__ok - connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 - connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 - connect \alu_op__write_cr0 \output_alu_op__write_cr0 - connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 - connect \alu_op__zero_a \output_alu_op__zero_a - connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$51 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$30 - connect \o \output_o - connect \o$20 \output_o$49 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$50 - connect \xer_ca \output_xer_ca - connect \xer_ca$23 \output_xer_ca$52 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_ov \output_xer_ov - connect \xer_ov$24 \output_xer_ov$53 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$25 \output_xer_so$54 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:157573.9-157576.4" - cell \p$3 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:156595.7-156595.20" - process $proc$libresoc.v:156595$9159 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:156602.13-156602.41" - process $proc$libresoc.v:156602$9160 - assign { } { } - assign $0\alu_op__data_len$18[3:0]$9161 4'0000 - sync always - sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9161 - end - attribute \src "libresoc.v:156637.14-156637.43" - process $proc$libresoc.v:156637$9162 - assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$9163 12'000000000000 - sync always - sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9163 - end - attribute \src "libresoc.v:156659.14-156659.63" - process $proc$libresoc.v:156659$9164 - assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9165 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9165 - end - attribute \src "libresoc.v:156668.7-156668.38" - process $proc$libresoc.v:156668$9166 - assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9167 1'0 - sync always - sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9167 - end - attribute \src "libresoc.v:156685.13-156685.44" - process $proc$libresoc.v:156685$9168 - assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9169 2'00 - sync always - sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9169 - end - attribute \src "libresoc.v:156698.14-156698.39" - process $proc$libresoc.v:156698$9170 - assign { } { } - assign $0\alu_op__insn$19[31:0]$9171 0 - sync always - sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9171 - end - attribute \src "libresoc.v:156855.13-156855.42" - process $proc$libresoc.v:156855$9172 - assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9173 7'0000000 - sync always - sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9173 - end - attribute \src "libresoc.v:156938.7-156938.36" - process $proc$libresoc.v:156938$9174 - assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9175 1'0 - sync always - sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9175 - end - attribute \src "libresoc.v:156947.7-156947.37" - process $proc$libresoc.v:156947$9176 - assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9177 1'0 - sync always - sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9177 - end - attribute \src "libresoc.v:156956.7-156956.35" - process $proc$libresoc.v:156956$9178 - assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9179 1'0 - sync always - sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9179 - end - attribute \src "libresoc.v:156965.7-156965.36" - process $proc$libresoc.v:156965$9180 - assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9181 1'0 - sync always - sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9181 - end - attribute \src "libresoc.v:156976.7-156976.32" - process $proc$libresoc.v:156976$9182 - assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9183 1'0 - sync always - sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9183 - end - attribute \src "libresoc.v:156985.7-156985.32" - process $proc$libresoc.v:156985$9184 - assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9185 1'0 - sync always - sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9185 - end - attribute \src "libresoc.v:156992.7-156992.39" - process $proc$libresoc.v:156992$9186 - assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9187 1'0 - sync always - sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9187 - end - attribute \src "libresoc.v:157003.7-157003.32" - process $proc$libresoc.v:157003$9188 - assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9189 1'0 - sync always - sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9189 - end - attribute \src "libresoc.v:157010.7-157010.32" - process $proc$libresoc.v:157010$9190 - assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9191 1'0 - sync always - sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9191 - end - attribute \src "libresoc.v:157019.7-157019.36" - process $proc$libresoc.v:157019$9192 - assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9193 1'0 - sync always - sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9193 - end - attribute \src "libresoc.v:157028.7-157028.33" - process $proc$libresoc.v:157028$9194 - assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9195 1'0 - sync always - sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9195 - end - attribute \src "libresoc.v:157041.13-157041.29" - process $proc$libresoc.v:157041$9196 - assign { } { } - assign $0\cr_a$22[3:0]$9197 4'0000 - sync always - sync init - update \cr_a$22 $0\cr_a$22[3:0]$9197 - end - attribute \src "libresoc.v:157050.7-157050.26" - process $proc$libresoc.v:157050$9198 - assign { } { } - assign $0\cr_a_ok$23[0:0]$9199 1'0 - sync always - sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9199 - end - attribute \src "libresoc.v:157061.13-157061.29" - process $proc$libresoc.v:157061$9200 - assign { } { } - assign $0\muxid$1[1:0]$9201 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$9201 - end - attribute \src "libresoc.v:157076.14-157076.43" - process $proc$libresoc.v:157076$9202 - assign { } { } - assign $0\o$20[63:0]$9203 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$20 $0\o$20[63:0]$9203 - end - attribute \src "libresoc.v:157085.7-157085.23" - process $proc$libresoc.v:157085$9204 - assign { } { } - assign $0\o_ok$21[0:0]$9205 1'0 - sync always - sync init - update \o_ok$21 $0\o_ok$21[0:0]$9205 - end - attribute \src "libresoc.v:157389.7-157389.20" - process $proc$libresoc.v:157389$9206 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:157396.13-157396.31" - process $proc$libresoc.v:157396$9207 - assign { } { } - assign $0\xer_ca$24[1:0]$9208 2'00 - sync always - sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9208 - end - attribute \src "libresoc.v:157405.7-157405.28" - process $proc$libresoc.v:157405$9209 - assign { } { } - assign $0\xer_ca_ok$25[0:0]$9210 1'0 - sync always - sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9210 - end - attribute \src "libresoc.v:157416.13-157416.31" - process $proc$libresoc.v:157416$9211 - assign { } { } - assign $0\xer_ov$26[1:0]$9212 2'00 - sync always - sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9212 - end - attribute \src "libresoc.v:157425.7-157425.28" - process $proc$libresoc.v:157425$9213 - assign { } { } - assign $0\xer_ov_ok$27[0:0]$9214 1'0 - sync always - sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9214 - end - attribute \src "libresoc.v:157436.7-157436.25" - process $proc$libresoc.v:157436$9215 - assign { } { } - assign $0\xer_so$28[0:0]$9216 1'0 - sync always - sync init - update \xer_so$28 $0\xer_so$28[0:0]$9216 - end - attribute \src "libresoc.v:157445.7-157445.28" - process $proc$libresoc.v:157445$9217 - assign { } { } - assign $0\xer_so_ok$29[0:0]$9218 1'0 - sync always - sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9218 - end - attribute \src "libresoc.v:157453.3-157454.37" - process $proc$libresoc.v:157453$9020 - assign { } { } - assign $0\xer_so$28[0:0]$9021 \xer_so$28$next - sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$9021 - end - attribute \src "libresoc.v:157455.3-157456.43" - process $proc$libresoc.v:157455$9022 - assign { } { } - assign $0\xer_so_ok$29[0:0]$9023 \xer_so_ok$29$next - sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9023 - end - attribute \src "libresoc.v:157457.3-157458.37" - process $proc$libresoc.v:157457$9024 - assign { } { } - assign $0\xer_ov$26[1:0]$9025 \xer_ov$26$next - sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$9025 - end - attribute \src "libresoc.v:157459.3-157460.43" - process $proc$libresoc.v:157459$9026 - assign { } { } - assign $0\xer_ov_ok$27[0:0]$9027 \xer_ov_ok$27$next - sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9027 - end - attribute \src "libresoc.v:157461.3-157462.37" - process $proc$libresoc.v:157461$9028 - assign { } { } - assign $0\xer_ca$24[1:0]$9029 \xer_ca$24$next - sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$9029 - end - attribute \src "libresoc.v:157463.3-157464.43" - process $proc$libresoc.v:157463$9030 - assign { } { } - assign $0\xer_ca_ok$25[0:0]$9031 \xer_ca_ok$25$next - sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9031 - end - attribute \src "libresoc.v:157465.3-157466.33" - process $proc$libresoc.v:157465$9032 - assign { } { } - assign $0\cr_a$22[3:0]$9033 \cr_a$22$next - sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$9033 - end - attribute \src "libresoc.v:157467.3-157468.39" - process $proc$libresoc.v:157467$9034 - assign { } { } - assign $0\cr_a_ok$23[0:0]$9035 \cr_a_ok$23$next - sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9035 - end - attribute \src "libresoc.v:157469.3-157470.27" - process $proc$libresoc.v:157469$9036 - assign { } { } - assign $0\o$20[63:0]$9037 \o$20$next - sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$9037 - end - attribute \src "libresoc.v:157471.3-157472.33" - process $proc$libresoc.v:157471$9038 - assign { } { } - assign $0\o_ok$21[0:0]$9039 \o_ok$21$next - sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$9039 - end - attribute \src "libresoc.v:157473.3-157474.57" - process $proc$libresoc.v:157473$9040 - assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9041 \alu_op__insn_type$2$next - sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9041 - end - attribute \src "libresoc.v:157475.3-157476.53" - process $proc$libresoc.v:157475$9042 - assign { } { } - assign $0\alu_op__fn_unit$3[11:0]$9043 \alu_op__fn_unit$3$next - sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$9043 - end - attribute \src "libresoc.v:157477.3-157478.67" - process $proc$libresoc.v:157477$9044 - assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9045 \alu_op__imm_data__data$4$next - sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9045 - end - attribute \src "libresoc.v:157479.3-157480.63" - process $proc$libresoc.v:157479$9046 - assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9047 \alu_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9047 - end - attribute \src "libresoc.v:157481.3-157482.51" - process $proc$libresoc.v:157481$9048 - assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9049 \alu_op__rc__rc$6$next - sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9049 - end - attribute \src "libresoc.v:157483.3-157484.51" - process $proc$libresoc.v:157483$9050 - assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9051 \alu_op__rc__ok$7$next - sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9051 - end - attribute \src "libresoc.v:157485.3-157486.51" - process $proc$libresoc.v:157485$9052 - assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9053 \alu_op__oe__oe$8$next - sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9053 - end - attribute \src "libresoc.v:157487.3-157488.51" - process $proc$libresoc.v:157487$9054 - assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9055 \alu_op__oe__ok$9$next - sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9055 - end - attribute \src "libresoc.v:157489.3-157490.59" - process $proc$libresoc.v:157489$9056 - assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9057 \alu_op__invert_in$10$next - sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9057 - end - attribute \src "libresoc.v:157491.3-157492.53" - process $proc$libresoc.v:157491$9058 - assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9059 \alu_op__zero_a$11$next - sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9059 - end - attribute \src "libresoc.v:157493.3-157494.61" - process $proc$libresoc.v:157493$9060 - assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9061 \alu_op__invert_out$12$next - sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9061 - end - attribute \src "libresoc.v:157495.3-157496.59" - process $proc$libresoc.v:157495$9062 - assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9063 \alu_op__write_cr0$13$next - sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9063 - end - attribute \src "libresoc.v:157497.3-157498.63" - process $proc$libresoc.v:157497$9064 - assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9065 \alu_op__input_carry$14$next - sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9065 - end - attribute \src "libresoc.v:157499.3-157500.65" - process $proc$libresoc.v:157499$9066 - assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9067 \alu_op__output_carry$15$next - sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9067 + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:157501.3-157502.57" - process $proc$libresoc.v:157501$9068 + attribute \src "libresoc.v:5938.3-6079.6" + process $proc$libresoc.v:5938$256 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9069 \alu_op__is_32bit$16$next - sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9069 - end - attribute \src "libresoc.v:157503.3-157504.59" - process $proc$libresoc.v:157503$9070 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9071 \alu_op__is_signed$17$next - sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9071 - end - attribute \src "libresoc.v:157505.3-157506.57" - process $proc$libresoc.v:157505$9072 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9073 \alu_op__data_len$18$next - sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9073 + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:5939.5-5939.29" + switch \initial + attribute \src "libresoc.v:5939.9-5939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:157507.3-157508.49" - process $proc$libresoc.v:157507$9074 + attribute \src "libresoc.v:6080.3-6221.6" + process $proc$libresoc.v:6080$257 assign { } { } - assign $0\alu_op__insn$19[31:0]$9075 \alu_op__insn$19$next - sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9075 - end - attribute \src "libresoc.v:157509.3-157510.33" - process $proc$libresoc.v:157509$9076 assign { } { } - assign $0\muxid$1[1:0]$9077 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9077 - end - attribute \src "libresoc.v:157511.3-157512.29" - process $proc$libresoc.v:157511$9078 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:6081.5-6081.29" + switch \initial + attribute \src "libresoc.v:6081.9-6081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] end - attribute \src "libresoc.v:157577.3-157594.6" - process $proc$libresoc.v:157577$9079 + attribute \src "libresoc.v:6222.3-6363.6" + process $proc$libresoc.v:6222$258 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9080 $2\r_busy$next[0:0]$9082 - attribute \src "libresoc.v:157578.5-157578.29" + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:6223.5-6223.29" switch \initial - attribute \src "libresoc.v:157578.9-157578.17" + attribute \src "libresoc.v:6223.9-6223.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } - assign $1\r_busy$next[0:0]$9081 1'1 + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } - assign $1\r_busy$next[0:0]$9081 1'0 + assign $1\sgl_pipe[0:0] 1'0 case - assign $1\r_busy$next[0:0]$9081 \r_busy + assign $1\sgl_pipe[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign $2\r_busy$next[0:0]$9082 1'0 + assign $2\sgl_pipe[0:0] 1'1 case - assign $2\r_busy$next[0:0]$9082 $1\r_busy$next[0:0]$9081 + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] end sync always - update \r_busy$next $0\r_busy$next[0:0]$9080 + update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:157595.3-157607.6" - process $proc$libresoc.v:157595$9083 + attribute \src "libresoc.v:6364.3-6505.6" + process $proc$libresoc.v:6364$259 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9084 $1\muxid$1$next[1:0]$9085 - attribute \src "libresoc.v:157596.5-157596.29" + assign { } { } + assign $0\function_unit[11:0] $2\function_unit[11:0] + attribute \src "libresoc.v:6365.5-6365.29" switch \initial - attribute \src "libresoc.v:157596.9-157596.17" + attribute \src "libresoc.v:6365.9-6365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 assign { } { } - assign $1\muxid$1$next[1:0]$9085 \muxid$62 + assign $1\function_unit[11:0] \dec19_dec19_function_unit attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'011110 + assign { } { } + assign $1\function_unit[11:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[11:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[11:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[11:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + case + assign $1\function_unit[11:0] 12'000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } - assign $1\muxid$1$next[1:0]$9085 \muxid$62 + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 case - assign $1\muxid$1$next[1:0]$9085 \muxid$1 + assign $2\function_unit[11:0] $1\function_unit[11:0] end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9084 + update \function_unit $0\function_unit[11:0] end - attribute \src "libresoc.v:157608.3-157649.6" - process $proc$libresoc.v:157608$9086 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:6506.3-6647.6" + process $proc$libresoc.v:6506$260 assign { } { } assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9087 $1\alu_op__data_len$18$next[3:0]$9105 - assign $0\alu_op__fn_unit$3$next[11:0]$9088 $1\alu_op__fn_unit$3$next[11:0]$9106 - assign { } { } - assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9091 $1\alu_op__input_carry$14$next[1:0]$9109 - assign $0\alu_op__insn$19$next[31:0]$9092 $1\alu_op__insn$19$next[31:0]$9110 - assign $0\alu_op__insn_type$2$next[6:0]$9093 $1\alu_op__insn_type$2$next[6:0]$9111 - assign $0\alu_op__invert_in$10$next[0:0]$9094 $1\alu_op__invert_in$10$next[0:0]$9112 - assign $0\alu_op__invert_out$12$next[0:0]$9095 $1\alu_op__invert_out$12$next[0:0]$9113 - assign $0\alu_op__is_32bit$16$next[0:0]$9096 $1\alu_op__is_32bit$16$next[0:0]$9114 - assign $0\alu_op__is_signed$17$next[0:0]$9097 $1\alu_op__is_signed$17$next[0:0]$9115 - assign { } { } - assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9100 $1\alu_op__output_carry$15$next[0:0]$9118 - assign { } { } - assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9103 $1\alu_op__write_cr0$13$next[0:0]$9121 - assign $0\alu_op__zero_a$11$next[0:0]$9104 $1\alu_op__zero_a$11$next[0:0]$9122 - assign $0\alu_op__imm_data__data$4$next[63:0]$9089 $2\alu_op__imm_data__data$4$next[63:0]$9123 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9090 $2\alu_op__imm_data__ok$5$next[0:0]$9124 - assign $0\alu_op__oe__oe$8$next[0:0]$9098 $2\alu_op__oe__oe$8$next[0:0]$9125 - assign $0\alu_op__oe__ok$9$next[0:0]$9099 $2\alu_op__oe__ok$9$next[0:0]$9126 - assign $0\alu_op__rc__ok$7$next[0:0]$9101 $2\alu_op__rc__ok$7$next[0:0]$9127 - assign $0\alu_op__rc__rc$6$next[0:0]$9102 $2\alu_op__rc__rc$6$next[0:0]$9128 - attribute \src "libresoc.v:157609.5-157609.29" + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:6507.5-6507.29" switch \initial - attribute \src "libresoc.v:157609.9-157609.17" + attribute \src "libresoc.v:6507.9-6507.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9110 $1\alu_op__data_len$18$next[3:0]$9105 $1\alu_op__is_signed$17$next[0:0]$9115 $1\alu_op__is_32bit$16$next[0:0]$9114 $1\alu_op__output_carry$15$next[0:0]$9118 $1\alu_op__input_carry$14$next[1:0]$9109 $1\alu_op__write_cr0$13$next[0:0]$9121 $1\alu_op__invert_out$12$next[0:0]$9113 $1\alu_op__zero_a$11$next[0:0]$9122 $1\alu_op__invert_in$10$next[0:0]$9112 $1\alu_op__oe__ok$9$next[0:0]$9117 $1\alu_op__oe__oe$8$next[0:0]$9116 $1\alu_op__rc__ok$7$next[0:0]$9119 $1\alu_op__rc__rc$6$next[0:0]$9120 $1\alu_op__imm_data__ok$5$next[0:0]$9108 $1\alu_op__imm_data__data$4$next[63:0]$9107 $1\alu_op__fn_unit$3$next[11:0]$9106 $1\alu_op__insn_type$2$next[6:0]$9111 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + attribute \src "libresoc.v:6648.3-6789.6" + process $proc$libresoc.v:6648$261 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:6649.5-6649.29" + switch \initial + attribute \src "libresoc.v:6649.9-6649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { } { } + case 6'010011 assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9110 $1\alu_op__data_len$18$next[3:0]$9105 $1\alu_op__is_signed$17$next[0:0]$9115 $1\alu_op__is_32bit$16$next[0:0]$9114 $1\alu_op__output_carry$15$next[0:0]$9118 $1\alu_op__input_carry$14$next[1:0]$9109 $1\alu_op__write_cr0$13$next[0:0]$9121 $1\alu_op__invert_out$12$next[0:0]$9113 $1\alu_op__zero_a$11$next[0:0]$9122 $1\alu_op__invert_in$10$next[0:0]$9112 $1\alu_op__oe__ok$9$next[0:0]$9117 $1\alu_op__oe__oe$8$next[0:0]$9116 $1\alu_op__rc__ok$7$next[0:0]$9119 $1\alu_op__rc__rc$6$next[0:0]$9120 $1\alu_op__imm_data__ok$5$next[0:0]$9108 $1\alu_op__imm_data__data$4$next[63:0]$9107 $1\alu_op__fn_unit$3$next[11:0]$9106 $1\alu_op__insn_type$2$next[6:0]$9111 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } - case - assign $1\alu_op__data_len$18$next[3:0]$9105 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[11:0]$9106 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9107 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9108 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9109 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9110 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9111 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9112 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9113 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9114 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9115 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9116 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9117 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9118 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9119 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9120 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9121 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9122 \alu_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'001010 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9123 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9124 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9128 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9127 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9125 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9126 1'0 - case - assign $2\alu_op__imm_data__data$4$next[63:0]$9123 $1\alu_op__imm_data__data$4$next[63:0]$9107 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9124 $1\alu_op__imm_data__ok$5$next[0:0]$9108 - assign $2\alu_op__oe__oe$8$next[0:0]$9125 $1\alu_op__oe__oe$8$next[0:0]$9116 - assign $2\alu_op__oe__ok$9$next[0:0]$9126 $1\alu_op__oe__ok$9$next[0:0]$9117 - assign $2\alu_op__rc__ok$7$next[0:0]$9127 $1\alu_op__rc__ok$7$next[0:0]$9119 - assign $2\alu_op__rc__rc$6$next[0:0]$9128 $1\alu_op__rc__rc$6$next[0:0]$9120 - end - sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9087 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$9088 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9089 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9090 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9091 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9092 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9093 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9094 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9095 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9096 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9097 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9098 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9099 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9100 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9101 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9102 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9103 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9104 - end - attribute \src "libresoc.v:157650.3-157668.6" - process $proc$libresoc.v:157650$9129 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$20$next[63:0]$9130 $1\o$20$next[63:0]$9132 - assign { } { } - assign $0\o_ok$21$next[0:0]$9131 $2\o_ok$21$next[0:0]$9134 - attribute \src "libresoc.v:157651.5-157651.29" - switch \initial - attribute \src "libresoc.v:157651.9-157651.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'101001 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 assign { } { } - assign { $1\o_ok$21$next[0:0]$9133 $1\o$20$next[63:0]$9132 } { \o_ok$82 \o$81 } + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'100001 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 assign { } { } - assign { $1\o_ok$21$next[0:0]$9133 $1\o$20$next[63:0]$9132 } { \o_ok$82 \o$81 } - case - assign $1\o$20$next[63:0]$9132 \o$20 - assign $1\o_ok$21$next[0:0]$9133 \o_ok$21 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'011000 assign { } { } - assign $2\o_ok$21$next[0:0]$9134 1'0 - case - assign $2\o_ok$21$next[0:0]$9134 $1\o_ok$21$next[0:0]$9133 - end - sync always - update \o$20$next $0\o$20$next[63:0]$9130 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9131 - end - attribute \src "libresoc.v:157669.3-157687.6" - process $proc$libresoc.v:157669$9135 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$22$next[3:0]$9136 $1\cr_a$22$next[3:0]$9138 - assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9137 $2\cr_a_ok$23$next[0:0]$9140 - attribute \src "libresoc.v:157670.5-157670.29" - switch \initial - attribute \src "libresoc.v:157670.9-157670.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'011001 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9139 $1\cr_a$22$next[3:0]$9138 } { \cr_a_ok$84 \cr_a$83 } + assign $1\form[4:0] 5'10011 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'010101 assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9139 $1\cr_a$22$next[3:0]$9138 } { \cr_a_ok$84 \cr_a$83 } - case - assign $1\cr_a$22$next[3:0]$9138 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9139 \cr_a_ok$23 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\form[4:0] 5'10011 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100110 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9140 1'0 - case - assign $2\cr_a_ok$23$next[0:0]$9140 $1\cr_a_ok$23$next[0:0]$9139 - end - sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9136 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9137 - end - attribute \src "libresoc.v:157688.3-157706.6" - process $proc$libresoc.v:157688$9141 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ca$24$next[1:0]$9142 $1\xer_ca$24$next[1:0]$9144 - assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9143 $2\xer_ca_ok$25$next[0:0]$9146 - attribute \src "libresoc.v:157689.5-157689.29" - switch \initial - attribute \src "libresoc.v:157689.9-157689.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'100111 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9145 $1\xer_ca$24$next[1:0]$9144 } { \xer_ca_ok$86 \xer_ca$85 } + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'101101 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9145 $1\xer_ca$24$next[1:0]$9144 } { \xer_ca_ok$86 \xer_ca$85 } - case - assign $1\xer_ca$24$next[1:0]$9144 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9145 \xer_ca_ok$25 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'100101 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9146 1'0 - case - assign $2\xer_ca_ok$25$next[0:0]$9146 $1\xer_ca_ok$25$next[0:0]$9145 - end - sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9142 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9143 - end - attribute \src "libresoc.v:157707.3-157725.6" - process $proc$libresoc.v:157707$9147 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_ov$26$next[1:0]$9148 $1\xer_ov$26$next[1:0]$9150 - assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9149 $2\xer_ov_ok$27$next[0:0]$9152 - attribute \src "libresoc.v:157708.5-157708.29" - switch \initial - attribute \src "libresoc.v:157708.9-157708.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 6'001000 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9151 $1\xer_ov$26$next[1:0]$9150 } { \xer_ov_ok$88 \xer_ov$87 } + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 6'000011 assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9151 $1\xer_ov$26$next[1:0]$9150 } { \xer_ov_ok$88 \xer_ov$87 } - case - assign $1\xer_ov$26$next[1:0]$9150 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9151 \xer_ov_ok$27 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 6'011011 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9152 1'0 - case - assign $2\xer_ov_ok$27$next[0:0]$9152 $1\xer_ov_ok$27$next[0:0]$9151 - end - sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9148 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9149 - end - attribute \src "libresoc.v:157726.3-157744.6" - process $proc$libresoc.v:157726$9153 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$28$next[0:0]$9154 $1\xer_so$28$next[0:0]$9156 - assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9155 $2\xer_so_ok$29$next[0:0]$9158 - attribute \src "libresoc.v:157727.5-157727.29" - switch \initial - attribute \src "libresoc.v:157727.9-157727.17" - case 1'1 + assign $1\form[4:0] 5'00100 case + assign $1\form[4:0] 5'00000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch$1 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } + case 32'000000---------------0100000000- assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9157 $1\xer_so$28$next[0:0]$9156 } { \xer_so_ok$90 \xer_so$89 } + assign $2\form[4:0] 5'00000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } + case 1610612736 assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9157 $1\xer_so$28$next[0:0]$9156 } { \xer_so_ok$90 \xer_so$89 } - case - assign $1\xer_so$28$next[0:0]$9156 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9157 \xer_so_ok$29 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $2\form[4:0] 5'00100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 32'000001---------------0000000011- assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9158 1'0 + assign $2\form[4:0] 5'00000 case - assign $2\xer_so_ok$29$next[0:0]$9158 $1\xer_so_ok$29$next[0:0]$9157 + assign $2\form[4:0] $1\form[4:0] end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9154 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9155 + update \form $0\form[4:0] end - connect \$60 $and$libresoc.v:157452$9019_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } - connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } - connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } - connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } - connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } - connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } - connect \muxid$62 \output_muxid$30 - connect \p_valid_i_p_ready_o \$60 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$59 \p_valid_i - connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } - connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } - connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } - connect \output_muxid \muxid + connect \$2 $ternary$libresoc.v:3249$237_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:157768.1-158822.10" +attribute \src "libresoc.v:7128.1-8635.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" -module \pipe2$115 - attribute \src "libresoc.v:158768.3-158786.6" - wire width 4 $0\cr_a$21$next[3:0]$9324 - attribute \src "libresoc.v:158574.3-158575.33" - wire width 4 $0\cr_a$21[3:0]$9225 - attribute \src "libresoc.v:157780.13-157780.29" - wire width 4 $0\cr_a$21[3:0]$9337 - attribute \src "libresoc.v:158768.3-158786.6" - wire $0\cr_a_ok$22$next[0:0]$9325 - attribute \src "libresoc.v:158576.3-158577.39" - wire $0\cr_a_ok$22[0:0]$9227 - attribute \src "libresoc.v:157789.7-157789.26" - wire $0\cr_a_ok$22[0:0]$9339 - attribute \src "libresoc.v:157769.7-157769.20" +module \dec19 + attribute \src "libresoc.v:7646.3-7697.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "libresoc.v:7854.3-7905.6" + wire $0\dec19_br[0:0] + attribute \src "libresoc.v:8530.3-8581.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "libresoc.v:8582.3-8633.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "libresoc.v:7594.3-7645.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "libresoc.v:7802.3-7853.6" + wire $0\dec19_cry_out[0:0] + attribute \src "libresoc.v:8270.3-8321.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "libresoc.v:7386.3-7437.6" + wire width 12 $0\dec19_function_unit[11:0] + attribute \src "libresoc.v:8322.3-8373.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8374.3-8425.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8426.3-8477.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "libresoc.v:7958.3-8009.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "libresoc.v:7698.3-7749.6" + wire $0\dec19_inv_a[0:0] + attribute \src "libresoc.v:7750.3-7801.6" + wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:8062.3-8113.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:7438.3-7489.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8166.3-8217.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:8478.3-8529.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "libresoc.v:7542.3-7593.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8010.3-8061.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:8218.3-8269.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8114.3-8165.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:7906.3-7957.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7490.3-7541.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:7129.7-7129.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158695.3-158707.6" - wire width 2 $0\muxid$1$next[1:0]$9274 - attribute \src "libresoc.v:158616.3-158617.33" - wire width 2 $0\muxid$1[1:0]$9267 - attribute \src "libresoc.v:157800.13-157800.29" - wire width 2 $0\muxid$1[1:0]$9341 - attribute \src "libresoc.v:158749.3-158767.6" - wire width 64 $0\o$19$next[63:0]$9318 - attribute \src "libresoc.v:158578.3-158579.27" - wire width 64 $0\o$19[63:0]$9229 - attribute \src "libresoc.v:157815.14-157815.43" - wire width 64 $0\o$19[63:0]$9343 - attribute \src "libresoc.v:158749.3-158767.6" - wire $0\o_ok$20$next[0:0]$9319 - attribute \src "libresoc.v:158580.3-158581.33" - wire $0\o_ok$20[0:0]$9231 - attribute \src "libresoc.v:157824.7-157824.23" - wire $0\o_ok$20[0:0]$9345 - attribute \src "libresoc.v:158677.3-158694.6" - wire $0\r_busy$next[0:0]$9270 - attribute \src "libresoc.v:158618.3-158619.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:158708.3-158748.6" - wire width 12 $0\sr_op__fn_unit$3$next[11:0]$9277 - attribute \src "libresoc.v:158584.3-158585.51" - wire width 12 $0\sr_op__fn_unit$3[11:0]$9235 - attribute \src "libresoc.v:158147.14-158147.42" - wire width 12 $0\sr_op__fn_unit$3[11:0]$9348 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9278 - attribute \src "libresoc.v:158586.3-158587.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9237 - attribute \src "libresoc.v:158169.14-158169.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9350 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9279 - attribute \src "libresoc.v:158588.3-158589.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9239 - attribute \src "libresoc.v:158178.7-158178.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9352 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9280 - attribute \src "libresoc.v:158602.3-158603.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9253 - attribute \src "libresoc.v:158195.13-158195.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9354 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__input_cr$14$next[0:0]$9281 - attribute \src "libresoc.v:158606.3-158607.55" - wire $0\sr_op__input_cr$14[0:0]$9257 - attribute \src "libresoc.v:158208.7-158208.34" - wire $0\sr_op__input_cr$14[0:0]$9356 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9282 - attribute \src "libresoc.v:158614.3-158615.47" - wire width 32 $0\sr_op__insn$18[31:0]$9265 - attribute \src "libresoc.v:158217.14-158217.38" - wire width 32 $0\sr_op__insn$18[31:0]$9358 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9283 - attribute \src "libresoc.v:158582.3-158583.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$9233 - attribute \src "libresoc.v:158374.13-158374.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9360 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__invert_in$11$next[0:0]$9284 - attribute \src "libresoc.v:158600.3-158601.57" - wire $0\sr_op__invert_in$11[0:0]$9251 - attribute \src "libresoc.v:158457.7-158457.35" - wire $0\sr_op__invert_in$11[0:0]$9362 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__is_32bit$16$next[0:0]$9285 - attribute \src "libresoc.v:158610.3-158611.55" - wire $0\sr_op__is_32bit$16[0:0]$9261 - attribute \src "libresoc.v:158466.7-158466.34" - wire $0\sr_op__is_32bit$16[0:0]$9364 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__is_signed$17$next[0:0]$9286 - attribute \src "libresoc.v:158612.3-158613.57" - wire $0\sr_op__is_signed$17[0:0]$9263 - attribute \src "libresoc.v:158475.7-158475.35" - wire $0\sr_op__is_signed$17[0:0]$9366 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__oe__oe$8$next[0:0]$9287 - attribute \src "libresoc.v:158594.3-158595.49" - wire $0\sr_op__oe__oe$8[0:0]$9245 - attribute \src "libresoc.v:158486.7-158486.31" - wire $0\sr_op__oe__oe$8[0:0]$9368 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__oe__ok$9$next[0:0]$9288 - attribute \src "libresoc.v:158596.3-158597.49" - wire $0\sr_op__oe__ok$9[0:0]$9247 - attribute \src "libresoc.v:158495.7-158495.31" - wire $0\sr_op__oe__ok$9[0:0]$9370 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__output_carry$13$next[0:0]$9289 - attribute \src "libresoc.v:158604.3-158605.63" - wire $0\sr_op__output_carry$13[0:0]$9255 - attribute \src "libresoc.v:158502.7-158502.38" - wire $0\sr_op__output_carry$13[0:0]$9372 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__output_cr$15$next[0:0]$9290 - attribute \src "libresoc.v:158608.3-158609.57" - wire $0\sr_op__output_cr$15[0:0]$9259 - attribute \src "libresoc.v:158511.7-158511.35" - wire $0\sr_op__output_cr$15[0:0]$9374 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__rc__ok$7$next[0:0]$9291 - attribute \src "libresoc.v:158592.3-158593.49" - wire $0\sr_op__rc__ok$7[0:0]$9243 - attribute \src "libresoc.v:158522.7-158522.31" - wire $0\sr_op__rc__ok$7[0:0]$9376 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__rc__rc$6$next[0:0]$9292 - attribute \src "libresoc.v:158590.3-158591.49" - wire $0\sr_op__rc__rc$6[0:0]$9241 - attribute \src "libresoc.v:158531.7-158531.31" - wire $0\sr_op__rc__rc$6[0:0]$9378 - attribute \src "libresoc.v:158708.3-158748.6" - wire $0\sr_op__write_cr0$10$next[0:0]$9293 - attribute \src "libresoc.v:158598.3-158599.57" - wire $0\sr_op__write_cr0$10[0:0]$9249 - attribute \src "libresoc.v:158538.7-158538.35" - wire $0\sr_op__write_cr0$10[0:0]$9380 - attribute \src "libresoc.v:158787.3-158805.6" - wire width 2 $0\xer_ca$23$next[1:0]$9330 - attribute \src "libresoc.v:158570.3-158571.37" - wire width 2 $0\xer_ca$23[1:0]$9221 - attribute \src "libresoc.v:158547.13-158547.31" - wire width 2 $0\xer_ca$23[1:0]$9382 - attribute \src "libresoc.v:158787.3-158805.6" - wire $0\xer_ca_ok$24$next[0:0]$9331 - attribute \src "libresoc.v:158572.3-158573.43" - wire $0\xer_ca_ok$24[0:0]$9223 - attribute \src "libresoc.v:158556.7-158556.28" - wire $0\xer_ca_ok$24[0:0]$9384 - attribute \src "libresoc.v:158768.3-158786.6" - wire width 4 $1\cr_a$21$next[3:0]$9326 - attribute \src "libresoc.v:158768.3-158786.6" - wire $1\cr_a_ok$22$next[0:0]$9327 - attribute \src "libresoc.v:158695.3-158707.6" - wire width 2 $1\muxid$1$next[1:0]$9275 - attribute \src "libresoc.v:158749.3-158767.6" - wire width 64 $1\o$19$next[63:0]$9320 - attribute \src "libresoc.v:158749.3-158767.6" - wire $1\o_ok$20$next[0:0]$9321 - attribute \src "libresoc.v:158677.3-158694.6" - wire $1\r_busy$next[0:0]$9271 - attribute \src "libresoc.v:158114.7-158114.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:158708.3-158748.6" - wire width 12 $1\sr_op__fn_unit$3$next[11:0]$9294 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9295 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$9296 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 2 $1\sr_op__input_carry$12$next[1:0]$9297 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__input_cr$14$next[0:0]$9298 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 32 $1\sr_op__insn$18$next[31:0]$9299 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$9300 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__invert_in$11$next[0:0]$9301 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__is_32bit$16$next[0:0]$9302 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__is_signed$17$next[0:0]$9303 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__oe__oe$8$next[0:0]$9304 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__oe__ok$9$next[0:0]$9305 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__output_carry$13$next[0:0]$9306 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__output_cr$15$next[0:0]$9307 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__rc__ok$7$next[0:0]$9308 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__rc__rc$6$next[0:0]$9309 - attribute \src "libresoc.v:158708.3-158748.6" - wire $1\sr_op__write_cr0$10$next[0:0]$9310 - attribute \src "libresoc.v:158787.3-158805.6" - wire width 2 $1\xer_ca$23$next[1:0]$9332 - attribute \src "libresoc.v:158787.3-158805.6" - wire $1\xer_ca_ok$24$next[0:0]$9333 - attribute \src "libresoc.v:158768.3-158786.6" - wire $2\cr_a_ok$22$next[0:0]$9328 - attribute \src "libresoc.v:158749.3-158767.6" - wire $2\o_ok$20$next[0:0]$9322 - attribute \src "libresoc.v:158677.3-158694.6" - wire $2\r_busy$next[0:0]$9272 - attribute \src "libresoc.v:158708.3-158748.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9311 - attribute \src "libresoc.v:158708.3-158748.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$9312 - attribute \src "libresoc.v:158708.3-158748.6" - wire $2\sr_op__oe__oe$8$next[0:0]$9313 - attribute \src "libresoc.v:158708.3-158748.6" - wire $2\sr_op__oe__ok$9$next[0:0]$9314 - attribute \src "libresoc.v:158708.3-158748.6" - wire $2\sr_op__rc__ok$7$next[0:0]$9315 - attribute \src "libresoc.v:158708.3-158748.6" - wire $2\sr_op__rc__rc$6$next[0:0]$9316 - attribute \src "libresoc.v:158787.3-158805.6" - wire $2\xer_ca_ok$24$next[0:0]$9334 - attribute \src "libresoc.v:158569.18-158569.118" - wire $and$libresoc.v:158569$9219_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 input 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 output 52 \cr_a$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$21$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 25 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 53 \cr_a_ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$22$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$74 - attribute \src "libresoc.v:157769.7-157769.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 32 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 31 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 30 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 50 \o$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 51 \o_ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_muxid$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_o_ok$44 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_sr_op__fn_unit$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \output_sr_op__imm_data__data$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__imm_data__ok$29 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \output_sr_op__input_carry$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__input_cr$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_sr_op__insn$42 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_sr_op__insn_type$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__invert_in$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_32bit$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__is_signed$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__oe$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__oe__ok$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_carry$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__output_cr$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__ok$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__rc__rc$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_sr_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ca$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \sr_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 34 \sr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$3$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \sr_op__fn_unit$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 35 \sr_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \sr_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__imm_data__ok$57 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \sr_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 43 \sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__input_cr$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 21 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 49 \sr_op__insn$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$70 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \sr_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 33 \sr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$2$next + attribute \src "libresoc.v:7646.3-7697.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:7854.3-7905.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:8530.3-8581.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8582.3-8633.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:7594.3-7645.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:7802.3-7853.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:8270.3-8321.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:7386.3-7437.6" + wire width 12 $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:8322.3-8373.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8374.3-8425.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8426.3-8477.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:7958.3-8009.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:7698.3-7749.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7750.3-7801.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:8062.3-8113.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:7438.3-7489.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:8166.3-8217.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:8478.3-8529.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:7542.3-7593.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:8010.3-8061.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8218.3-8269.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8114.3-8165.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:7906.3-7957.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7490.3-7541.6" + wire width 2 $1\dec19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec19_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -326688,2920 +11120,2981 @@ module \pipe2$115 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \sr_op__invert_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__invert_in$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \sr_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_carry$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__output_cr$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \sr_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \sr_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \sr_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \sr_op__write_cr0$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 input 28 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 54 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$23$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ca$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 29 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \xer_ca_ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$24$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ca_ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 26 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 27 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:158569$9219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$50 - connect \B \p_ready_o - connect \Y $and$libresoc.v:158569$9219_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:158620.11-158623.4" - cell \n$117 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:158624.16-158672.4" - cell \output$118 \output - connect \cr_a \output_cr_a - connect \cr_a$21 \output_cr_a$45 - connect \cr_a_ok \output_cr_a_ok - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$25 - connect \o \output_o - connect \o$19 \output_o$43 - connect \o_ok \output_o_ok - connect \o_ok$20 \output_o_ok$44 - connect \sr_op__fn_unit \output_sr_op__fn_unit - connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 - connect \sr_op__imm_data__data \output_sr_op__imm_data__data - connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 - connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok - connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 - connect \sr_op__input_carry \output_sr_op__input_carry - connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 - connect \sr_op__input_cr \output_sr_op__input_cr - connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 - connect \sr_op__insn \output_sr_op__insn - connect \sr_op__insn$18 \output_sr_op__insn$42 - connect \sr_op__insn_type \output_sr_op__insn_type - connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 - connect \sr_op__invert_in \output_sr_op__invert_in - connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 - connect \sr_op__is_32bit \output_sr_op__is_32bit - connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 - connect \sr_op__is_signed \output_sr_op__is_signed - connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 - connect \sr_op__oe__oe \output_sr_op__oe__oe - connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 - connect \sr_op__oe__ok \output_sr_op__oe__ok - connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 - connect \sr_op__output_carry \output_sr_op__output_carry - connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 - connect \sr_op__output_cr \output_sr_op__output_cr - connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 - connect \sr_op__rc__ok \output_sr_op__rc__ok - connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 - connect \sr_op__rc__rc \output_sr_op__rc__rc - connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 - connect \sr_op__write_cr0 \output_sr_op__write_cr0 - connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 - connect \xer_ca \output_xer_ca - connect \xer_ca$22 \output_xer_ca$46 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_so \output_xer_so - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:158673.11-158676.4" - cell \p$116 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:157769.7-157769.20" - process $proc$libresoc.v:157769$9335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec19_upd + attribute \src "libresoc.v:7129.7-7129.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \src "libresoc.v:7129.7-7129.20" + process $proc$libresoc.v:7129$287 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157780.13-157780.29" - process $proc$libresoc.v:157780$9336 - assign { } { } - assign $0\cr_a$21[3:0]$9337 4'0000 - sync always - sync init - update \cr_a$21 $0\cr_a$21[3:0]$9337 - end - attribute \src "libresoc.v:157789.7-157789.26" - process $proc$libresoc.v:157789$9338 - assign { } { } - assign $0\cr_a_ok$22[0:0]$9339 1'0 - sync always - sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9339 - end - attribute \src "libresoc.v:157800.13-157800.29" - process $proc$libresoc.v:157800$9340 - assign { } { } - assign $0\muxid$1[1:0]$9341 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$9341 - end - attribute \src "libresoc.v:157815.14-157815.43" - process $proc$libresoc.v:157815$9342 - assign { } { } - assign $0\o$19[63:0]$9343 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o$19 $0\o$19[63:0]$9343 - end - attribute \src "libresoc.v:157824.7-157824.23" - process $proc$libresoc.v:157824$9344 - assign { } { } - assign $0\o_ok$20[0:0]$9345 1'0 - sync always - sync init - update \o_ok$20 $0\o_ok$20[0:0]$9345 - end - attribute \src "libresoc.v:158114.7-158114.20" - process $proc$libresoc.v:158114$9346 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:158147.14-158147.42" - process $proc$libresoc.v:158147$9347 - assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$9348 12'000000000000 - sync always - sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9348 - end - attribute \src "libresoc.v:158169.14-158169.62" - process $proc$libresoc.v:158169$9349 + attribute \src "libresoc.v:7386.3-7437.6" + process $proc$libresoc.v:7386$263 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9350 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9350 - end - attribute \src "libresoc.v:158178.7-158178.37" - process $proc$libresoc.v:158178$9351 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9352 1'0 + assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] + attribute \src "libresoc.v:7387.5-7387.29" + switch \initial + attribute \src "libresoc.v:7387.9-7387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + case + assign $1\dec19_function_unit[11:0] 12'000000000000 + end sync always - sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9352 + update \dec19_function_unit $0\dec19_function_unit[11:0] end - attribute \src "libresoc.v:158195.13-158195.43" - process $proc$libresoc.v:158195$9353 + attribute \src "libresoc.v:7438.3-7489.6" + process $proc$libresoc.v:7438$264 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9354 2'00 - sync always - sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9354 - end - attribute \src "libresoc.v:158208.7-158208.34" - process $proc$libresoc.v:158208$9355 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9356 1'0 + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:7439.5-7439.29" + switch \initial + attribute \src "libresoc.v:7439.9-7439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end sync always - sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9356 + update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:158217.14-158217.38" - process $proc$libresoc.v:158217$9357 + attribute \src "libresoc.v:7490.3-7541.6" + process $proc$libresoc.v:7490$265 assign { } { } - assign $0\sr_op__insn$18[31:0]$9358 0 - sync always - sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9358 - end - attribute \src "libresoc.v:158374.13-158374.41" - process $proc$libresoc.v:158374$9359 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9360 7'0000000 + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:7491.5-7491.29" + switch \initial + attribute \src "libresoc.v:7491.9-7491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end sync always - sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9360 + update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:158457.7-158457.35" - process $proc$libresoc.v:158457$9361 + attribute \src "libresoc.v:7542.3-7593.6" + process $proc$libresoc.v:7542$266 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9362 1'0 - sync always - sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9362 - end - attribute \src "libresoc.v:158466.7-158466.34" - process $proc$libresoc.v:158466$9363 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9364 1'0 + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:7543.5-7543.29" + switch \initial + attribute \src "libresoc.v:7543.9-7543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end sync always - sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9364 + update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:158475.7-158475.35" - process $proc$libresoc.v:158475$9365 + attribute \src "libresoc.v:7594.3-7645.6" + process $proc$libresoc.v:7594$267 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9366 1'0 - sync always - sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9366 - end - attribute \src "libresoc.v:158486.7-158486.31" - process $proc$libresoc.v:158486$9367 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9368 1'0 + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:7595.5-7595.29" + switch \initial + attribute \src "libresoc.v:7595.9-7595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end sync always - sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9368 + update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:158495.7-158495.31" - process $proc$libresoc.v:158495$9369 + attribute \src "libresoc.v:7646.3-7697.6" + process $proc$libresoc.v:7646$268 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9370 1'0 - sync always - sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9370 - end - attribute \src "libresoc.v:158502.7-158502.38" - process $proc$libresoc.v:158502$9371 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9372 1'0 + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:7647.5-7647.29" + switch \initial + attribute \src "libresoc.v:7647.9-7647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end sync always - sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9372 + update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:158511.7-158511.35" - process $proc$libresoc.v:158511$9373 + attribute \src "libresoc.v:7698.3-7749.6" + process $proc$libresoc.v:7698$269 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9374 1'0 - sync always - sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9374 - end - attribute \src "libresoc.v:158522.7-158522.31" - process $proc$libresoc.v:158522$9375 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9376 1'0 + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:7699.5-7699.29" + switch \initial + attribute \src "libresoc.v:7699.9-7699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end sync always - sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9376 + update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:158531.7-158531.31" - process $proc$libresoc.v:158531$9377 + attribute \src "libresoc.v:7750.3-7801.6" + process $proc$libresoc.v:7750$270 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9378 1'0 - sync always - sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9378 - end - attribute \src "libresoc.v:158538.7-158538.35" - process $proc$libresoc.v:158538$9379 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9380 1'0 + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:7751.5-7751.29" + switch \initial + attribute \src "libresoc.v:7751.9-7751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end sync always - sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9380 + update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:158547.13-158547.31" - process $proc$libresoc.v:158547$9381 + attribute \src "libresoc.v:7802.3-7853.6" + process $proc$libresoc.v:7802$271 assign { } { } - assign $0\xer_ca$23[1:0]$9382 2'00 - sync always - sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9382 - end - attribute \src "libresoc.v:158556.7-158556.28" - process $proc$libresoc.v:158556$9383 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9384 1'0 + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:7803.5-7803.29" + switch \initial + attribute \src "libresoc.v:7803.9-7803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end sync always - sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9384 - end - attribute \src "libresoc.v:158570.3-158571.37" - process $proc$libresoc.v:158570$9220 - assign { } { } - assign $0\xer_ca$23[1:0]$9221 \xer_ca$23$next - sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9221 - end - attribute \src "libresoc.v:158572.3-158573.43" - process $proc$libresoc.v:158572$9222 - assign { } { } - assign $0\xer_ca_ok$24[0:0]$9223 \xer_ca_ok$24$next - sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9223 - end - attribute \src "libresoc.v:158574.3-158575.33" - process $proc$libresoc.v:158574$9224 - assign { } { } - assign $0\cr_a$21[3:0]$9225 \cr_a$21$next - sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9225 - end - attribute \src "libresoc.v:158576.3-158577.39" - process $proc$libresoc.v:158576$9226 - assign { } { } - assign $0\cr_a_ok$22[0:0]$9227 \cr_a_ok$22$next - sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9227 - end - attribute \src "libresoc.v:158578.3-158579.27" - process $proc$libresoc.v:158578$9228 - assign { } { } - assign $0\o$19[63:0]$9229 \o$19$next - sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9229 - end - attribute \src "libresoc.v:158580.3-158581.33" - process $proc$libresoc.v:158580$9230 - assign { } { } - assign $0\o_ok$20[0:0]$9231 \o_ok$20$next - sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9231 - end - attribute \src "libresoc.v:158582.3-158583.55" - process $proc$libresoc.v:158582$9232 - assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9233 \sr_op__insn_type$2$next - sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9233 - end - attribute \src "libresoc.v:158584.3-158585.51" - process $proc$libresoc.v:158584$9234 - assign { } { } - assign $0\sr_op__fn_unit$3[11:0]$9235 \sr_op__fn_unit$3$next - sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$9235 - end - attribute \src "libresoc.v:158586.3-158587.65" - process $proc$libresoc.v:158586$9236 - assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9237 \sr_op__imm_data__data$4$next - sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9237 - end - attribute \src "libresoc.v:158588.3-158589.61" - process $proc$libresoc.v:158588$9238 - assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9239 \sr_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9239 - end - attribute \src "libresoc.v:158590.3-158591.49" - process $proc$libresoc.v:158590$9240 - assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9241 \sr_op__rc__rc$6$next - sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9241 - end - attribute \src "libresoc.v:158592.3-158593.49" - process $proc$libresoc.v:158592$9242 - assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9243 \sr_op__rc__ok$7$next - sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9243 - end - attribute \src "libresoc.v:158594.3-158595.49" - process $proc$libresoc.v:158594$9244 - assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9245 \sr_op__oe__oe$8$next - sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9245 - end - attribute \src "libresoc.v:158596.3-158597.49" - process $proc$libresoc.v:158596$9246 - assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9247 \sr_op__oe__ok$9$next - sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9247 - end - attribute \src "libresoc.v:158598.3-158599.57" - process $proc$libresoc.v:158598$9248 - assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9249 \sr_op__write_cr0$10$next - sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9249 - end - attribute \src "libresoc.v:158600.3-158601.57" - process $proc$libresoc.v:158600$9250 - assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9251 \sr_op__invert_in$11$next - sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9251 - end - attribute \src "libresoc.v:158602.3-158603.61" - process $proc$libresoc.v:158602$9252 - assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9253 \sr_op__input_carry$12$next - sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9253 - end - attribute \src "libresoc.v:158604.3-158605.63" - process $proc$libresoc.v:158604$9254 - assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9255 \sr_op__output_carry$13$next - sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9255 - end - attribute \src "libresoc.v:158606.3-158607.55" - process $proc$libresoc.v:158606$9256 - assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9257 \sr_op__input_cr$14$next - sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9257 - end - attribute \src "libresoc.v:158608.3-158609.57" - process $proc$libresoc.v:158608$9258 - assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9259 \sr_op__output_cr$15$next - sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9259 - end - attribute \src "libresoc.v:158610.3-158611.55" - process $proc$libresoc.v:158610$9260 - assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9261 \sr_op__is_32bit$16$next - sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9261 - end - attribute \src "libresoc.v:158612.3-158613.57" - process $proc$libresoc.v:158612$9262 - assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9263 \sr_op__is_signed$17$next - sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9263 - end - attribute \src "libresoc.v:158614.3-158615.47" - process $proc$libresoc.v:158614$9264 - assign { } { } - assign $0\sr_op__insn$18[31:0]$9265 \sr_op__insn$18$next - sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9265 - end - attribute \src "libresoc.v:158616.3-158617.33" - process $proc$libresoc.v:158616$9266 - assign { } { } - assign $0\muxid$1[1:0]$9267 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9267 - end - attribute \src "libresoc.v:158618.3-158619.29" - process $proc$libresoc.v:158618$9268 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:158677.3-158694.6" - process $proc$libresoc.v:158677$9269 + attribute \src "libresoc.v:7854.3-7905.6" + process $proc$libresoc.v:7854$272 assign { } { } assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$9270 $2\r_busy$next[0:0]$9272 - attribute \src "libresoc.v:158678.5-158678.29" + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:7855.5-7855.29" switch \initial - attribute \src "libresoc.v:158678.9-158678.17" + attribute \src "libresoc.v:7855.9-7855.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'1000110000 assign { } { } - assign $1\r_busy$next[0:0]$9271 1'1 + assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010010110 assign { } { } - assign $1\r_busy$next[0:0]$9271 1'0 - case - assign $1\r_busy$next[0:0]$9271 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\r_busy$next[0:0]$9272 1'0 + assign $1\dec19_br[0:0] 1'0 case - assign $2\r_busy$next[0:0]$9272 $1\r_busy$next[0:0]$9271 + assign $1\dec19_br[0:0] 1'0 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9270 + update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:158695.3-158707.6" - process $proc$libresoc.v:158695$9273 + attribute \src "libresoc.v:7906.3-7957.6" + process $proc$libresoc.v:7906$273 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9274 $1\muxid$1$next[1:0]$9275 - attribute \src "libresoc.v:158696.5-158696.29" + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:7907.5-7907.29" switch \initial - attribute \src "libresoc.v:158696.9-158696.17" + attribute \src "libresoc.v:7907.9-7907.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 assign { } { } - assign $1\muxid$1$next[1:0]$9275 \muxid$53 + assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0100000001 assign { } { } - assign $1\muxid$1$next[1:0]$9275 \muxid$53 - case - assign $1\muxid$1$next[1:0]$9275 \muxid$1 - end - sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9274 - end - attribute \src "libresoc.v:158708.3-158748.6" - process $proc$libresoc.v:158708$9276 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sr_op__fn_unit$3$next[11:0]$9277 $1\sr_op__fn_unit$3$next[11:0]$9294 - assign { } { } - assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9280 $1\sr_op__input_carry$12$next[1:0]$9297 - assign $0\sr_op__input_cr$14$next[0:0]$9281 $1\sr_op__input_cr$14$next[0:0]$9298 - assign $0\sr_op__insn$18$next[31:0]$9282 $1\sr_op__insn$18$next[31:0]$9299 - assign $0\sr_op__insn_type$2$next[6:0]$9283 $1\sr_op__insn_type$2$next[6:0]$9300 - assign $0\sr_op__invert_in$11$next[0:0]$9284 $1\sr_op__invert_in$11$next[0:0]$9301 - assign $0\sr_op__is_32bit$16$next[0:0]$9285 $1\sr_op__is_32bit$16$next[0:0]$9302 - assign $0\sr_op__is_signed$17$next[0:0]$9286 $1\sr_op__is_signed$17$next[0:0]$9303 - assign { } { } - assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9289 $1\sr_op__output_carry$13$next[0:0]$9306 - assign $0\sr_op__output_cr$15$next[0:0]$9290 $1\sr_op__output_cr$15$next[0:0]$9307 - assign { } { } - assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9293 $1\sr_op__write_cr0$10$next[0:0]$9310 - assign $0\sr_op__imm_data__data$4$next[63:0]$9278 $2\sr_op__imm_data__data$4$next[63:0]$9311 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9279 $2\sr_op__imm_data__ok$5$next[0:0]$9312 - assign $0\sr_op__oe__oe$8$next[0:0]$9287 $2\sr_op__oe__oe$8$next[0:0]$9313 - assign $0\sr_op__oe__ok$9$next[0:0]$9288 $2\sr_op__oe__ok$9$next[0:0]$9314 - assign $0\sr_op__rc__ok$7$next[0:0]$9291 $2\sr_op__rc__ok$7$next[0:0]$9315 - assign $0\sr_op__rc__rc$6$next[0:0]$9292 $2\sr_op__rc__rc$6$next[0:0]$9316 - attribute \src "libresoc.v:158709.5-158709.29" - switch \initial - attribute \src "libresoc.v:158709.9-158709.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec19_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:7958.3-8009.6" + process $proc$libresoc.v:7958$274 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:7959.5-7959.29" + switch \initial + attribute \src "libresoc.v:7959.9-7959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9299 $1\sr_op__is_signed$17$next[0:0]$9303 $1\sr_op__is_32bit$16$next[0:0]$9302 $1\sr_op__output_cr$15$next[0:0]$9307 $1\sr_op__input_cr$14$next[0:0]$9298 $1\sr_op__output_carry$13$next[0:0]$9306 $1\sr_op__input_carry$12$next[1:0]$9297 $1\sr_op__invert_in$11$next[0:0]$9301 $1\sr_op__write_cr0$10$next[0:0]$9310 $1\sr_op__oe__ok$9$next[0:0]$9305 $1\sr_op__oe__oe$8$next[0:0]$9304 $1\sr_op__rc__ok$7$next[0:0]$9308 $1\sr_op__rc__rc$6$next[0:0]$9309 $1\sr_op__imm_data__ok$5$next[0:0]$9296 $1\sr_op__imm_data__data$4$next[63:0]$9295 $1\sr_op__fn_unit$3$next[11:0]$9294 $1\sr_op__insn_type$2$next[6:0]$9300 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign $1\dec19_internal_op[6:0] 7'1000101 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0110100001 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "libresoc.v:8010.3-8061.6" + process $proc$libresoc.v:8010$275 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:8011.5-8011.29" + switch \initial + attribute \src "libresoc.v:8011.9-8011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9299 $1\sr_op__is_signed$17$next[0:0]$9303 $1\sr_op__is_32bit$16$next[0:0]$9302 $1\sr_op__output_cr$15$next[0:0]$9307 $1\sr_op__input_cr$14$next[0:0]$9298 $1\sr_op__output_carry$13$next[0:0]$9306 $1\sr_op__input_carry$12$next[1:0]$9297 $1\sr_op__invert_in$11$next[0:0]$9301 $1\sr_op__write_cr0$10$next[0:0]$9310 $1\sr_op__oe__ok$9$next[0:0]$9305 $1\sr_op__oe__oe$8$next[0:0]$9304 $1\sr_op__rc__ok$7$next[0:0]$9308 $1\sr_op__rc__rc$6$next[0:0]$9309 $1\sr_op__imm_data__ok$5$next[0:0]$9296 $1\sr_op__imm_data__data$4$next[63:0]$9295 $1\sr_op__fn_unit$3$next[11:0]$9294 $1\sr_op__insn_type$2$next[6:0]$9300 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } - case - assign $1\sr_op__fn_unit$3$next[11:0]$9294 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9295 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9296 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9297 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9298 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9299 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9300 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9301 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9302 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9303 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9304 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9305 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9306 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9307 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9308 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9309 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9310 \sr_op__write_cr0$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1000010000 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9311 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9312 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9316 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9315 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9313 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9314 1'0 + assign $1\dec19_rsrv[0:0] 1'0 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9311 $1\sr_op__imm_data__data$4$next[63:0]$9295 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9312 $1\sr_op__imm_data__ok$5$next[0:0]$9296 - assign $2\sr_op__oe__oe$8$next[0:0]$9313 $1\sr_op__oe__oe$8$next[0:0]$9304 - assign $2\sr_op__oe__ok$9$next[0:0]$9314 $1\sr_op__oe__ok$9$next[0:0]$9305 - assign $2\sr_op__rc__ok$7$next[0:0]$9315 $1\sr_op__rc__ok$7$next[0:0]$9308 - assign $2\sr_op__rc__rc$6$next[0:0]$9316 $1\sr_op__rc__rc$6$next[0:0]$9309 + assign $1\dec19_rsrv[0:0] 1'0 end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$9277 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9278 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9279 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9280 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9281 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9282 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9283 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9284 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9285 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9286 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9287 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9288 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9289 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9290 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9291 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9292 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9293 + update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:158749.3-158767.6" - process $proc$libresoc.v:158749$9317 + attribute \src "libresoc.v:8062.3-8113.6" + process $proc$libresoc.v:8062$276 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\o$19$next[63:0]$9318 $1\o$19$next[63:0]$9320 - assign { } { } - assign $0\o_ok$20$next[0:0]$9319 $2\o_ok$20$next[0:0]$9322 - attribute \src "libresoc.v:158750.5-158750.29" + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:8063.5-8063.29" switch \initial - attribute \src "libresoc.v:158750.9-158750.17" + attribute \src "libresoc.v:8063.9-8063.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign { $1\o_ok$20$next[0:0]$9321 $1\o$19$next[63:0]$9320 } { \o_ok$72 \o$71 } + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0100100001 assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign { $1\o_ok$20$next[0:0]$9321 $1\o$19$next[63:0]$9320 } { \o_ok$72 \o$71 } - case - assign $1\o$19$next[63:0]$9320 \o$19 - assign $1\o_ok$20$next[0:0]$9321 \o_ok$20 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000100001 assign { } { } - assign $2\o_ok$20$next[0:0]$9322 1'0 - case - assign $2\o_ok$20$next[0:0]$9322 $1\o_ok$20$next[0:0]$9321 - end - sync always - update \o$19$next $0\o$19$next[63:0]$9318 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9319 - end - attribute \src "libresoc.v:158768.3-158786.6" - process $proc$libresoc.v:158768$9323 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$21$next[3:0]$9324 $1\cr_a$21$next[3:0]$9326 - assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9325 $2\cr_a_ok$22$next[0:0]$9328 - attribute \src "libresoc.v:158769.5-158769.29" - switch \initial - attribute \src "libresoc.v:158769.9-158769.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0111000001 assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9327 $1\cr_a$21$next[3:0]$9326 } { \cr_a_ok$74 \cr_a$73 } + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0011000001 assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9327 $1\cr_a$21$next[3:0]$9326 } { \cr_a_ok$74 \cr_a$73 } - case - assign $1\cr_a$21$next[3:0]$9326 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9327 \cr_a_ok$22 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9328 1'0 + assign $1\dec19_is_32b[0:0] 1'0 case - assign $2\cr_a_ok$22$next[0:0]$9328 $1\cr_a_ok$22$next[0:0]$9327 + assign $1\dec19_is_32b[0:0] 1'0 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9324 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9325 + update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:158787.3-158805.6" - process $proc$libresoc.v:158787$9329 - assign { } { } + attribute \src "libresoc.v:8114.3-8165.6" + process $proc$libresoc.v:8114$277 assign { } { } assign { } { } - assign { } { } - assign $0\xer_ca$23$next[1:0]$9330 $1\xer_ca$23$next[1:0]$9332 - assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9331 $2\xer_ca_ok$24$next[0:0]$9334 - attribute \src "libresoc.v:158788.5-158788.29" + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:8115.5-8115.29" switch \initial - attribute \src "libresoc.v:158788.9-158788.17" + attribute \src "libresoc.v:8115.9-8115.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9333 $1\xer_ca$23$next[1:0]$9332 } { \xer_ca_ok$76 \xer_ca$75 } + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010000001 assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9333 $1\xer_ca$23$next[1:0]$9332 } { \xer_ca_ok$76 \xer_ca$75 } - case - assign $1\xer_ca$23$next[1:0]$9332 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9333 \xer_ca_ok$24 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0011100001 assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9334 1'0 - case - assign $2\xer_ca_ok$24$next[0:0]$9334 $1\xer_ca_ok$24$next[0:0]$9333 - end - sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9330 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9331 - end - connect \$51 $and$libresoc.v:158569$9219_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } - connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } - connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } - connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } - connect \muxid$53 \output_muxid$25 - connect \p_valid_i_p_ready_o \$51 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$50 \p_valid_i - connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } - connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } - connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } - connect { \output_o_ok \output_o } { \o_ok \o } - connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } - connect \output_muxid \muxid -end -attribute \src "libresoc.v:158826.1-159775.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" -attribute \generator "nMigen" -module \pipe2$35 - attribute \src "libresoc.v:159681.3-159699.6" - wire width 64 $0\fast1$11$next[63:0]$9453 - attribute \src "libresoc.v:159536.3-159537.35" - wire width 64 $0\fast1$11[63:0]$9394 - attribute \src "libresoc.v:158838.14-158838.47" - wire width 64 $0\fast1$11[63:0]$9477 - attribute \src "libresoc.v:159681.3-159699.6" - wire $0\fast1_ok$next[0:0]$9452 - attribute \src "libresoc.v:159538.3-159539.33" - wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:159700.3-159718.6" - wire width 64 $0\fast2$12$next[63:0]$9459 - attribute \src "libresoc.v:159532.3-159533.35" - wire width 64 $0\fast2$12[63:0]$9391 - attribute \src "libresoc.v:158854.14-158854.47" - wire width 64 $0\fast2$12[63:0]$9480 - attribute \src "libresoc.v:159700.3-159718.6" - wire $0\fast2_ok$next[0:0]$9458 - attribute \src "libresoc.v:159534.3-159535.33" - wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:158827.7-158827.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:159738.3-159756.6" - wire width 64 $0\msr$next[63:0]$9470 - attribute \src "libresoc.v:159524.3-159525.23" - wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:159738.3-159756.6" - wire $0\msr_ok$next[0:0]$9471 - attribute \src "libresoc.v:159526.3-159527.29" - wire $0\msr_ok[0:0] - attribute \src "libresoc.v:159628.3-159640.6" - wire width 2 $0\muxid$1$next[1:0]$9424 - attribute \src "libresoc.v:159562.3-159563.33" - wire width 2 $0\muxid$1[1:0]$9417 - attribute \src "libresoc.v:159126.13-159126.29" - wire width 2 $0\muxid$1[1:0]$9485 - attribute \src "libresoc.v:159719.3-159737.6" - wire width 64 $0\nia$next[63:0]$9464 - attribute \src "libresoc.v:159528.3-159529.23" - wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:159719.3-159737.6" - wire $0\nia_ok$next[0:0]$9465 - attribute \src "libresoc.v:159530.3-159531.29" - wire $0\nia_ok[0:0] - attribute \src "libresoc.v:159662.3-159680.6" - wire width 64 $0\o$next[63:0]$9446 - attribute \src "libresoc.v:159540.3-159541.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:159662.3-159680.6" - wire $0\o_ok$next[0:0]$9447 - attribute \src "libresoc.v:159542.3-159543.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:159610.3-159627.6" - wire $0\r_busy$next[0:0]$9420 - attribute \src "libresoc.v:159564.3-159565.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:159641.3-159661.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9427 - attribute \src "libresoc.v:159552.3-159553.47" - wire width 64 $0\trap_op__cia$6[63:0]$9407 - attribute \src "libresoc.v:159187.14-159187.53" - wire width 64 $0\trap_op__cia$6[63:0]$9492 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 12 $0\trap_op__fn_unit$3$next[11:0]$9428 - attribute \src "libresoc.v:159546.3-159547.55" - wire width 12 $0\trap_op__fn_unit$3[11:0]$9401 - attribute \src "libresoc.v:159220.14-159220.44" - wire width 12 $0\trap_op__fn_unit$3[11:0]$9494 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$9429 - attribute \src "libresoc.v:159548.3-159549.49" - wire width 32 $0\trap_op__insn$4[31:0]$9403 - attribute \src "libresoc.v:159244.14-159244.39" - wire width 32 $0\trap_op__insn$4[31:0]$9496 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$9430 - attribute \src "libresoc.v:159544.3-159545.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$9399 - attribute \src "libresoc.v:159399.13-159399.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$9498 - attribute \src "libresoc.v:159641.3-159661.6" - wire $0\trap_op__is_32bit$7$next[0:0]$9431 - attribute \src "libresoc.v:159554.3-159555.57" - wire $0\trap_op__is_32bit$7[0:0]$9409 - attribute \src "libresoc.v:159484.7-159484.35" - wire $0\trap_op__is_32bit$7[0:0]$9500 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9432 - attribute \src "libresoc.v:159560.3-159561.59" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9415 - attribute \src "libresoc.v:159491.13-159491.43" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9502 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$9433 - attribute \src "libresoc.v:159550.3-159551.47" - wire width 64 $0\trap_op__msr$5[63:0]$9405 - attribute \src "libresoc.v:159502.14-159502.53" - wire width 64 $0\trap_op__msr$5[63:0]$9504 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9434 - attribute \src "libresoc.v:159558.3-159559.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9413 - attribute \src "libresoc.v:159511.14-159511.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9506 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 8 $0\trap_op__traptype$8$next[7:0]$9435 - attribute \src "libresoc.v:159556.3-159557.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9411 - attribute \src "libresoc.v:159520.13-159520.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9508 - attribute \src "libresoc.v:159681.3-159699.6" - wire width 64 $1\fast1$11$next[63:0]$9455 - attribute \src "libresoc.v:159681.3-159699.6" - wire $1\fast1_ok$next[0:0]$9454 - attribute \src "libresoc.v:158845.7-158845.22" - wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:159700.3-159718.6" - wire width 64 $1\fast2$12$next[63:0]$9461 - attribute \src "libresoc.v:159700.3-159718.6" - wire $1\fast2_ok$next[0:0]$9460 - attribute \src "libresoc.v:158861.7-158861.22" - wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:159738.3-159756.6" - wire width 64 $1\msr$next[63:0]$9472 - attribute \src "libresoc.v:159110.14-159110.40" - wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:159738.3-159756.6" - wire $1\msr_ok$next[0:0]$9473 - attribute \src "libresoc.v:159117.7-159117.20" - wire $1\msr_ok[0:0] - attribute \src "libresoc.v:159628.3-159640.6" - wire width 2 $1\muxid$1$next[1:0]$9425 - attribute \src "libresoc.v:159719.3-159737.6" - wire width 64 $1\nia$next[63:0]$9466 - attribute \src "libresoc.v:159139.14-159139.40" - wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:159719.3-159737.6" - wire $1\nia_ok$next[0:0]$9467 - attribute \src "libresoc.v:159146.7-159146.20" - wire $1\nia_ok[0:0] - attribute \src "libresoc.v:159662.3-159680.6" - wire width 64 $1\o$next[63:0]$9448 - attribute \src "libresoc.v:159153.14-159153.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:159662.3-159680.6" - wire $1\o_ok$next[0:0]$9449 - attribute \src "libresoc.v:159160.7-159160.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:159610.3-159627.6" - wire $1\r_busy$next[0:0]$9421 - attribute \src "libresoc.v:159174.7-159174.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:159641.3-159661.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$9436 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 12 $1\trap_op__fn_unit$3$next[11:0]$9437 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$9438 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$9439 - attribute \src "libresoc.v:159641.3-159661.6" - wire $1\trap_op__is_32bit$7$next[0:0]$9440 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9441 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$9442 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9443 - attribute \src "libresoc.v:159641.3-159661.6" - wire width 8 $1\trap_op__traptype$8$next[7:0]$9444 - attribute \src "libresoc.v:159681.3-159699.6" - wire $2\fast1_ok$next[0:0]$9456 - attribute \src "libresoc.v:159700.3-159718.6" - wire $2\fast2_ok$next[0:0]$9462 - attribute \src "libresoc.v:159738.3-159756.6" - wire $2\msr_ok$next[0:0]$9474 - attribute \src "libresoc.v:159719.3-159737.6" - wire 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$0\fast2$12[63:0]$9480 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \fast2$12 $0\fast2$12[63:0]$9480 - end - attribute \src "libresoc.v:158861.7-158861.22" - process $proc$libresoc.v:158861$9481 - assign { } { } - assign $1\fast2_ok[0:0] 1'0 - sync always - sync init - update \fast2_ok $1\fast2_ok[0:0] - end - attribute \src "libresoc.v:159110.14-159110.40" - process $proc$libresoc.v:159110$9482 - assign { } { } - assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr $1\msr[63:0] - end - attribute \src "libresoc.v:159117.7-159117.20" - process $proc$libresoc.v:159117$9483 - assign { } { } - assign $1\msr_ok[0:0] 1'0 - sync always - sync init - update \msr_ok $1\msr_ok[0:0] - end - attribute \src "libresoc.v:159126.13-159126.29" - process $proc$libresoc.v:159126$9484 - assign { } { } - assign $0\muxid$1[1:0]$9485 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$9485 - end - attribute \src "libresoc.v:159139.14-159139.40" - process $proc$libresoc.v:159139$9486 - assign { } { } - assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \nia $1\nia[63:0] - end - attribute \src "libresoc.v:159146.7-159146.20" - process $proc$libresoc.v:159146$9487 - assign { } { } - assign $1\nia_ok[0:0] 1'0 - sync always - sync init - update \nia_ok $1\nia_ok[0:0] - end - attribute \src "libresoc.v:159153.14-159153.38" - process $proc$libresoc.v:159153$9488 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:159160.7-159160.18" - process $proc$libresoc.v:159160$9489 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:159174.7-159174.20" - process $proc$libresoc.v:159174$9490 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:159187.14-159187.53" - process $proc$libresoc.v:159187$9491 - assign { } { } - assign $0\trap_op__cia$6[63:0]$9492 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9492 - end - attribute \src "libresoc.v:159220.14-159220.44" - process $proc$libresoc.v:159220$9493 - assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$9494 12'000000000000 - sync always - sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9494 - end - attribute \src "libresoc.v:159244.14-159244.39" - process $proc$libresoc.v:159244$9495 - assign { } { } - assign $0\trap_op__insn$4[31:0]$9496 0 - sync always - sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9496 - end - attribute \src "libresoc.v:159399.13-159399.43" - process $proc$libresoc.v:159399$9497 - assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9498 7'0000000 - sync always - sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9498 - end - attribute \src "libresoc.v:159484.7-159484.35" - process $proc$libresoc.v:159484$9499 - assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9500 1'0 - sync always - sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9500 - end - attribute \src "libresoc.v:159491.13-159491.43" - process $proc$libresoc.v:159491$9501 - assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9502 8'00000000 - sync always - sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9502 - end - attribute \src "libresoc.v:159502.14-159502.53" - process $proc$libresoc.v:159502$9503 - assign { } { } - assign $0\trap_op__msr$5[63:0]$9504 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9504 - end - attribute \src "libresoc.v:159511.14-159511.46" - process $proc$libresoc.v:159511$9505 - assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9506 13'0000000000000 - sync always - sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9506 - end - attribute \src "libresoc.v:159520.13-159520.42" - process $proc$libresoc.v:159520$9507 - assign { } { } - assign $0\trap_op__traptype$8[7:0]$9508 8'00000000 - sync always - sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9508 - end - attribute \src "libresoc.v:159524.3-159525.23" - process $proc$libresoc.v:159524$9386 - assign { } { } - assign $0\msr[63:0] \msr$next - sync posedge \coresync_clk - update \msr $0\msr[63:0] - end - attribute \src "libresoc.v:159526.3-159527.29" - process $proc$libresoc.v:159526$9387 - assign { } { } - assign $0\msr_ok[0:0] \msr_ok$next - sync posedge \coresync_clk - update \msr_ok $0\msr_ok[0:0] - end - attribute \src "libresoc.v:159528.3-159529.23" - process $proc$libresoc.v:159528$9388 - assign { } { } - assign $0\nia[63:0] \nia$next - sync posedge \coresync_clk - update \nia $0\nia[63:0] - end - attribute \src "libresoc.v:159530.3-159531.29" - process $proc$libresoc.v:159530$9389 - assign { } { } - assign $0\nia_ok[0:0] \nia_ok$next - sync posedge \coresync_clk - update \nia_ok $0\nia_ok[0:0] - end - attribute \src "libresoc.v:159532.3-159533.35" - process $proc$libresoc.v:159532$9390 - assign { } { } - assign $0\fast2$12[63:0]$9391 \fast2$12$next - sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9391 - end - attribute \src "libresoc.v:159534.3-159535.33" - process $proc$libresoc.v:159534$9392 - assign { } { } - assign $0\fast2_ok[0:0] \fast2_ok$next - sync posedge \coresync_clk - update \fast2_ok $0\fast2_ok[0:0] - end - attribute \src "libresoc.v:159536.3-159537.35" - process $proc$libresoc.v:159536$9393 - assign { } { } - assign $0\fast1$11[63:0]$9394 \fast1$11$next - sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9394 - end - attribute \src "libresoc.v:159538.3-159539.33" - process $proc$libresoc.v:159538$9395 - assign { } { } - assign $0\fast1_ok[0:0] \fast1_ok$next - sync posedge \coresync_clk - update \fast1_ok $0\fast1_ok[0:0] - end - attribute \src "libresoc.v:159540.3-159541.19" - process $proc$libresoc.v:159540$9396 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:159542.3-159543.25" - process $proc$libresoc.v:159542$9397 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] - end - attribute \src "libresoc.v:159544.3-159545.59" - process $proc$libresoc.v:159544$9398 - assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9399 \trap_op__insn_type$2$next - sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9399 - end - attribute \src "libresoc.v:159546.3-159547.55" - process $proc$libresoc.v:159546$9400 - assign { } { } - assign $0\trap_op__fn_unit$3[11:0]$9401 \trap_op__fn_unit$3$next - sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$9401 - end - attribute \src "libresoc.v:159548.3-159549.49" - process $proc$libresoc.v:159548$9402 - assign { } { } - assign $0\trap_op__insn$4[31:0]$9403 \trap_op__insn$4$next - sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9403 - end - attribute \src "libresoc.v:159550.3-159551.47" - process $proc$libresoc.v:159550$9404 - assign { } { } - assign $0\trap_op__msr$5[63:0]$9405 \trap_op__msr$5$next - sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9405 - end - attribute \src "libresoc.v:159552.3-159553.47" - process $proc$libresoc.v:159552$9406 - assign { } { } - assign $0\trap_op__cia$6[63:0]$9407 \trap_op__cia$6$next - sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9407 - end - attribute \src "libresoc.v:159554.3-159555.57" - process $proc$libresoc.v:159554$9408 - assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9409 \trap_op__is_32bit$7$next - sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9409 - end - attribute \src "libresoc.v:159556.3-159557.57" - process $proc$libresoc.v:159556$9410 - assign { } { } - assign $0\trap_op__traptype$8[7:0]$9411 \trap_op__traptype$8$next - sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9411 - end - attribute \src "libresoc.v:159558.3-159559.57" - process $proc$libresoc.v:159558$9412 - assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9413 \trap_op__trapaddr$9$next - sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9413 - end - attribute \src "libresoc.v:159560.3-159561.59" - process $proc$libresoc.v:159560$9414 - assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9415 \trap_op__ldst_exc$10$next - sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9415 - end - attribute \src "libresoc.v:159562.3-159563.33" - process $proc$libresoc.v:159562$9416 - assign { } { } - assign $0\muxid$1[1:0]$9417 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9417 - end - attribute \src "libresoc.v:159564.3-159565.29" - process $proc$libresoc.v:159564$9418 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:159610.3-159627.6" - process $proc$libresoc.v:159610$9419 - assign { } { } + attribute \src "libresoc.v:8166.3-8217.6" + process $proc$libresoc.v:8166$278 assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9420 $2\r_busy$next[0:0]$9422 - attribute \src "libresoc.v:159611.5-159611.29" + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:8167.5-8167.29" switch \initial - attribute \src "libresoc.v:159611.9-159611.17" + attribute \src "libresoc.v:8167.9-8167.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign $1\r_busy$next[0:0]$9421 1'1 + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010000001 assign { } { } - assign $1\r_busy$next[0:0]$9421 1'0 - case - assign $1\r_busy$next[0:0]$9421 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\r_busy$next[0:0]$9422 1'0 + assign $1\dec19_lk[0:0] 1'0 case - assign $2\r_busy$next[0:0]$9422 $1\r_busy$next[0:0]$9421 + assign $1\dec19_lk[0:0] 1'0 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9420 + update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:159628.3-159640.6" - process $proc$libresoc.v:159628$9423 + attribute \src "libresoc.v:8218.3-8269.6" + process $proc$libresoc.v:8218$279 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9424 $1\muxid$1$next[1:0]$9425 - attribute \src "libresoc.v:159629.5-159629.29" + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:8219.5-8219.29" switch \initial - attribute \src "libresoc.v:159629.9-159629.17" + attribute \src "libresoc.v:8219.9-8219.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 assign { } { } - assign $1\muxid$1$next[1:0]$9425 \muxid$28 + assign $1\dec19_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } - assign $1\muxid$1$next[1:0]$9425 \muxid$28 + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 case - assign $1\muxid$1$next[1:0]$9425 \muxid$1 + assign $1\dec19_sgl_pipe[0:0] 1'0 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9424 + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:159641.3-159661.6" - process $proc$libresoc.v:159641$9426 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:8270.3-8321.6" + process $proc$libresoc.v:8270$280 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9427 $1\trap_op__cia$6$next[63:0]$9436 - assign $0\trap_op__fn_unit$3$next[11:0]$9428 $1\trap_op__fn_unit$3$next[11:0]$9437 - assign $0\trap_op__insn$4$next[31:0]$9429 $1\trap_op__insn$4$next[31:0]$9438 - assign $0\trap_op__insn_type$2$next[6:0]$9430 $1\trap_op__insn_type$2$next[6:0]$9439 - assign $0\trap_op__is_32bit$7$next[0:0]$9431 $1\trap_op__is_32bit$7$next[0:0]$9440 - assign $0\trap_op__ldst_exc$10$next[7:0]$9432 $1\trap_op__ldst_exc$10$next[7:0]$9441 - assign $0\trap_op__msr$5$next[63:0]$9433 $1\trap_op__msr$5$next[63:0]$9442 - assign $0\trap_op__trapaddr$9$next[12:0]$9434 $1\trap_op__trapaddr$9$next[12:0]$9443 - assign $0\trap_op__traptype$8$next[7:0]$9435 $1\trap_op__traptype$8$next[7:0]$9444 - attribute \src "libresoc.v:159642.5-159642.29" + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:8271.5-8271.29" switch \initial - attribute \src "libresoc.v:159642.9-159642.17" + attribute \src "libresoc.v:8271.9-8271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9441 $1\trap_op__trapaddr$9$next[12:0]$9443 $1\trap_op__traptype$8$next[7:0]$9444 $1\trap_op__is_32bit$7$next[0:0]$9440 $1\trap_op__cia$6$next[63:0]$9436 $1\trap_op__msr$5$next[63:0]$9442 $1\trap_op__insn$4$next[31:0]$9438 $1\trap_op__fn_unit$3$next[11:0]$9437 $1\trap_op__insn_type$2$next[6:0]$9439 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign $1\dec19_form[4:0] 5'01001 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "libresoc.v:8322.3-8373.6" + process $proc$libresoc.v:8322$281 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:8323.5-8323.29" + switch \initial + attribute \src "libresoc.v:8323.9-8323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9441 $1\trap_op__trapaddr$9$next[12:0]$9443 $1\trap_op__traptype$8$next[7:0]$9444 $1\trap_op__is_32bit$7$next[0:0]$9440 $1\trap_op__cia$6$next[63:0]$9436 $1\trap_op__msr$5$next[63:0]$9442 $1\trap_op__insn$4$next[31:0]$9438 $1\trap_op__fn_unit$3$next[11:0]$9437 $1\trap_op__insn_type$2$next[6:0]$9439 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign $1\dec19_in1_sel[2:0] 3'011 case - assign $1\trap_op__cia$6$next[63:0]$9436 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[11:0]$9437 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9438 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9439 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9440 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9441 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9442 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9443 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9444 \trap_op__traptype$8 + assign $1\dec19_in1_sel[2:0] 3'000 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9427 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$9428 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9429 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9430 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9431 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9432 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9433 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9434 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9435 + update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:159662.3-159680.6" - process $proc$libresoc.v:159662$9445 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:8374.3-8425.6" + process $proc$libresoc.v:8374$282 assign { } { } - assign $0\o$next[63:0]$9446 $1\o$next[63:0]$9448 assign { } { } - assign $0\o_ok$next[0:0]$9447 $2\o_ok$next[0:0]$9450 - attribute \src "libresoc.v:159663.5-159663.29" + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:8375.5-8375.29" switch \initial - attribute \src "libresoc.v:159663.9-159663.17" + attribute \src "libresoc.v:8375.9-8375.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } - assign { $1\o_ok$next[0:0]$9449 $1\o$next[63:0]$9448 } { \o_ok$39 \o$38 } + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0100100001 assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign { $1\o_ok$next[0:0]$9449 $1\o$next[63:0]$9448 } { \o_ok$39 \o$38 } - case - assign $1\o$next[63:0]$9448 \o - assign $1\o_ok$next[0:0]$9449 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\o_ok$next[0:0]$9450 1'0 + assign $1\dec19_in2_sel[3:0] 4'1100 case - assign $2\o_ok$next[0:0]$9450 $1\o_ok$next[0:0]$9449 + assign $1\dec19_in2_sel[3:0] 4'0000 end sync always - update \o$next $0\o$next[63:0]$9446 - update \o_ok$next $0\o_ok$next[0:0]$9447 + update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:159681.3-159699.6" - process $proc$libresoc.v:159681$9451 + attribute \src "libresoc.v:8426.3-8477.6" + process $proc$libresoc.v:8426$283 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\fast1$11$next[63:0]$9453 $1\fast1$11$next[63:0]$9455 - assign $0\fast1_ok$next[0:0]$9452 $2\fast1_ok$next[0:0]$9456 - attribute \src "libresoc.v:159682.5-159682.29" + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:8427.5-8427.29" switch \initial - attribute \src "libresoc.v:159682.9-159682.17" + attribute \src "libresoc.v:8427.9-8427.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign { $1\fast1_ok$next[0:0]$9454 $1\fast1$11$next[63:0]$9455 } { \fast1_ok$41 \fast1$40 } + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010000001 assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign { $1\fast1_ok$next[0:0]$9454 $1\fast1$11$next[63:0]$9455 } { \fast1_ok$41 \fast1$40 } - case - assign $1\fast1_ok$next[0:0]$9454 \fast1_ok - assign $1\fast1$11$next[63:0]$9455 \fast1$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0011100001 assign { } { } - assign $2\fast1_ok$next[0:0]$9456 1'0 + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 case - assign $2\fast1_ok$next[0:0]$9456 $1\fast1_ok$next[0:0]$9454 + assign $1\dec19_in3_sel[1:0] 2'00 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9452 - update \fast1$11$next $0\fast1$11$next[63:0]$9453 + update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:159700.3-159718.6" - process $proc$libresoc.v:159700$9457 - assign { } { } + attribute \src "libresoc.v:8478.3-8529.6" + process $proc$libresoc.v:8478$284 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\fast2$12$next[63:0]$9459 $1\fast2$12$next[63:0]$9461 - assign $0\fast2_ok$next[0:0]$9458 $2\fast2_ok$next[0:0]$9462 - attribute \src "libresoc.v:159701.5-159701.29" + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:8479.5-8479.29" switch \initial - attribute \src "libresoc.v:159701.9-159701.17" + attribute \src "libresoc.v:8479.9-8479.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign { $1\fast2_ok$next[0:0]$9460 $1\fast2$12$next[63:0]$9461 } { \fast2_ok$43 \fast2$42 } + assign $1\dec19_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010000001 assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign { $1\fast2_ok$next[0:0]$9460 $1\fast2$12$next[63:0]$9461 } { \fast2_ok$43 \fast2$42 } - case - assign $1\fast2_ok$next[0:0]$9460 \fast2_ok - assign $1\fast2$12$next[63:0]$9461 \fast2$12 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\fast2_ok$next[0:0]$9462 1'0 + assign $1\dec19_out_sel[1:0] 2'00 case - assign $2\fast2_ok$next[0:0]$9462 $1\fast2_ok$next[0:0]$9460 + assign $1\dec19_out_sel[1:0] 2'00 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9458 - update \fast2$12$next $0\fast2$12$next[63:0]$9459 + update \dec19_out_sel $0\dec19_out_sel[1:0] end - attribute \src "libresoc.v:159719.3-159737.6" - process $proc$libresoc.v:159719$9463 - assign { } { } - assign { } { } + attribute \src "libresoc.v:8530.3-8581.6" + process $proc$libresoc.v:8530$285 assign { } { } assign { } { } - assign $0\nia$next[63:0]$9464 $1\nia$next[63:0]$9466 - assign { } { } - assign $0\nia_ok$next[0:0]$9465 $2\nia_ok$next[0:0]$9468 - attribute \src "libresoc.v:159720.5-159720.29" + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:8531.5-8531.29" switch \initial - attribute \src "libresoc.v:159720.9-159720.17" + attribute \src "libresoc.v:8531.9-8531.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign { $1\nia_ok$next[0:0]$9467 $1\nia$next[63:0]$9466 } { \nia_ok$45 \nia$44 } + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010000001 assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } - assign { $1\nia_ok$next[0:0]$9467 $1\nia$next[63:0]$9466 } { \nia_ok$45 \nia$44 } - case - assign $1\nia$next[63:0]$9466 \nia - assign $1\nia_ok$next[0:0]$9467 \nia_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_cr_in[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\nia_ok$next[0:0]$9468 1'0 + assign $1\dec19_cr_in[2:0] 3'000 case - assign $2\nia_ok$next[0:0]$9468 $1\nia_ok$next[0:0]$9467 + assign $1\dec19_cr_in[2:0] 3'000 end sync always - update \nia$next $0\nia$next[63:0]$9464 - update \nia_ok$next $0\nia_ok$next[0:0]$9465 + update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:159738.3-159756.6" - process $proc$libresoc.v:159738$9469 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:8582.3-8633.6" + process $proc$libresoc.v:8582$286 assign { } { } - assign $0\msr$next[63:0]$9470 $1\msr$next[63:0]$9472 assign { } { } - assign $0\msr_ok$next[0:0]$9471 $2\msr_ok$next[0:0]$9474 - attribute \src "libresoc.v:159739.5-159739.29" + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:8583.5-8583.29" switch \initial - attribute \src "libresoc.v:159739.9-159739.17" + attribute \src "libresoc.v:8583.9-8583.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 10'0000000000 assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 assign { } { } - assign { $1\msr_ok$next[0:0]$9473 $1\msr$next[63:0]$9472 } { \msr_ok$47 \msr$46 } + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 assign { } { } - assign { $1\msr_ok$next[0:0]$9473 $1\msr$next[63:0]$9472 } { \msr_ok$47 \msr$46 } - case - assign $1\msr$next[63:0]$9472 \msr - assign $1\msr_ok$next[0:0]$9473 \msr_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec19_cr_out[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } - assign $2\msr_ok$next[0:0]$9474 1'0 + assign $1\dec19_cr_out[2:0] 3'000 case - assign $2\msr_ok$next[0:0]$9474 $1\msr_ok$next[0:0]$9473 + assign $1\dec19_cr_out[2:0] 3'000 end sync always - update \msr$next $0\msr$next[63:0]$9470 - update \msr_ok$next $0\msr_ok$next[0:0]$9471 + update \dec19_cr_out $0\dec19_cr_out[2:0] end - connect \$26 $and$libresoc.v:159523$9385_Y - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } - connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } - connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } - connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } - connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } - connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } - connect \muxid$28 \main_muxid$13 - connect \p_valid_i_p_ready_o \$26 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$25 \p_valid_i - connect \main_fast2 \fast2 - connect \main_fast1 \fast1 - connect \main_rb \rb - connect \main_ra \ra - connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - connect \main_muxid \muxid + connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:159779.1-161261.10" +attribute \src "libresoc.v:8639.1-10676.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" +attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" -module \pipe_end - attribute \src "libresoc.v:161099.3-161117.6" - wire width 4 $0\cr_a$next[3:0]$9565 - attribute \src "libresoc.v:160918.3-160919.25" - wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:161099.3-161117.6" - wire $0\cr_a_ok$next[0:0]$9566 - attribute \src "libresoc.v:160920.3-160921.31" - wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:159780.7-159780.20" +module \dec2 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_in2$1[2:0]$306 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_in2_ok$2[0:0]$307 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$3[0:0]$309 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$4[0:0]$310 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$5[0:0]$311 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$6[0:0]$312 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$7[0:0]$313 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$8[0:0]$314 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal$9[0:0]$315 + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\exc_$signal[0:0]$308 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $0\fn_unit[11:0] + attribute \src "libresoc.v:8640.7-8640.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161187.3-161228.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9590 - attribute \src "libresoc.v:160958.3-160959.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9552 - attribute \src "libresoc.v:159821.13-159821.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9636 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 12 $0\logical_op__fn_unit$3$next[11:0]$9591 - attribute \src "libresoc.v:160928.3-160929.61" - wire width 12 $0\logical_op__fn_unit$3[11:0]$9522 - attribute \src "libresoc.v:159856.14-159856.47" - wire width 12 $0\logical_op__fn_unit$3[11:0]$9638 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9592 - attribute \src "libresoc.v:160930.3-160931.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9524 - attribute \src "libresoc.v:159878.14-159878.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9640 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9593 - attribute \src "libresoc.v:160932.3-160933.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9526 - attribute \src "libresoc.v:159887.7-159887.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9642 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9594 - attribute \src "libresoc.v:160946.3-160947.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9540 - attribute \src "libresoc.v:159904.13-159904.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9644 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9595 - attribute \src "libresoc.v:160960.3-160961.57" - wire width 32 $0\logical_op__insn$19[31:0]$9554 - attribute \src "libresoc.v:159917.14-159917.43" - wire width 32 $0\logical_op__insn$19[31:0]$9646 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9596 - attribute \src "libresoc.v:160926.3-160927.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9520 - attribute \src "libresoc.v:160074.13-160074.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9648 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__invert_in$10$next[0:0]$9597 - attribute \src "libresoc.v:160942.3-160943.67" - wire $0\logical_op__invert_in$10[0:0]$9536 - attribute \src "libresoc.v:160157.7-160157.40" - wire $0\logical_op__invert_in$10[0:0]$9650 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__invert_out$13$next[0:0]$9598 - attribute \src "libresoc.v:160948.3-160949.69" - wire $0\logical_op__invert_out$13[0:0]$9542 - attribute \src "libresoc.v:160166.7-160166.41" - wire $0\logical_op__invert_out$13[0:0]$9652 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9599 - attribute \src "libresoc.v:160954.3-160955.65" - wire $0\logical_op__is_32bit$16[0:0]$9548 - attribute \src "libresoc.v:160175.7-160175.39" - wire $0\logical_op__is_32bit$16[0:0]$9654 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__is_signed$17$next[0:0]$9600 - attribute \src "libresoc.v:160956.3-160957.67" - wire $0\logical_op__is_signed$17[0:0]$9550 - attribute \src "libresoc.v:160184.7-160184.40" - wire $0\logical_op__is_signed$17[0:0]$9656 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9601 - attribute \src "libresoc.v:160938.3-160939.59" - wire $0\logical_op__oe__oe$8[0:0]$9532 - attribute \src "libresoc.v:160193.7-160193.36" - wire $0\logical_op__oe__oe$8[0:0]$9658 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9602 - attribute \src "libresoc.v:160940.3-160941.59" - wire $0\logical_op__oe__ok$9[0:0]$9534 - attribute \src "libresoc.v:160204.7-160204.36" - wire $0\logical_op__oe__ok$9[0:0]$9660 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__output_carry$15$next[0:0]$9603 - attribute \src "libresoc.v:160952.3-160953.73" - wire $0\logical_op__output_carry$15[0:0]$9546 - attribute \src "libresoc.v:160211.7-160211.43" - wire $0\logical_op__output_carry$15[0:0]$9662 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9604 - attribute \src "libresoc.v:160936.3-160937.59" - wire $0\logical_op__rc__ok$7[0:0]$9530 - attribute \src "libresoc.v:160220.7-160220.36" - wire $0\logical_op__rc__ok$7[0:0]$9664 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9605 - attribute \src "libresoc.v:160934.3-160935.59" - wire $0\logical_op__rc__rc$6[0:0]$9528 - attribute \src "libresoc.v:160229.7-160229.36" - wire $0\logical_op__rc__rc$6[0:0]$9666 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9606 - attribute \src "libresoc.v:160950.3-160951.67" - wire $0\logical_op__write_cr0$14[0:0]$9544 - attribute \src "libresoc.v:160238.7-160238.40" - wire $0\logical_op__write_cr0$14[0:0]$9668 - attribute \src "libresoc.v:161187.3-161228.6" - wire $0\logical_op__zero_a$11$next[0:0]$9607 - attribute \src "libresoc.v:160944.3-160945.61" - wire $0\logical_op__zero_a$11[0:0]$9538 - attribute \src "libresoc.v:160247.7-160247.37" - wire $0\logical_op__zero_a$11[0:0]$9670 - attribute \src "libresoc.v:161174.3-161186.6" - wire width 2 $0\muxid$1$next[1:0]$9587 - attribute \src "libresoc.v:160962.3-160963.33" - wire width 2 $0\muxid$1[1:0]$9556 - attribute \src "libresoc.v:160256.13-160256.29" - wire width 2 $0\muxid$1[1:0]$9672 - attribute \src "libresoc.v:161080.3-161098.6" - wire width 64 $0\o$next[63:0]$9559 - attribute \src "libresoc.v:160922.3-160923.19" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:161080.3-161098.6" - wire $0\o_ok$next[0:0]$9560 - attribute \src "libresoc.v:160924.3-160925.25" - wire $0\o_ok[0:0] - attribute \src "libresoc.v:161156.3-161173.6" - wire $0\r_busy$next[0:0]$9583 - attribute \src "libresoc.v:160964.3-160965.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:161118.3-161136.6" - wire width 2 $0\xer_ov$next[1:0]$9571 - attribute \src "libresoc.v:160914.3-160915.29" - wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:161118.3-161136.6" - wire $0\xer_ov_ok$next[0:0]$9572 - attribute \src "libresoc.v:160916.3-160917.35" - wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:161137.3-161155.6" - wire $0\xer_so$20$next[0:0]$9578 - attribute \src "libresoc.v:160910.3-160911.37" - wire $0\xer_so$20[0:0]$9511 - attribute \src "libresoc.v:160895.7-160895.25" - wire $0\xer_so$20[0:0]$9679 - attribute \src "libresoc.v:161137.3-161155.6" - wire $0\xer_so_ok$next[0:0]$9577 - attribute \src "libresoc.v:160912.3-160913.35" - wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:161099.3-161117.6" - wire width 4 $1\cr_a$next[3:0]$9567 - attribute \src "libresoc.v:159789.13-159789.24" - wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:161099.3-161117.6" - wire $1\cr_a_ok$next[0:0]$9568 - attribute \src "libresoc.v:159798.7-159798.21" - wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:161187.3-161228.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9608 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 12 $1\logical_op__fn_unit$3$next[11:0]$9609 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9610 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9611 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9612 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9613 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9614 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__invert_in$10$next[0:0]$9615 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__invert_out$13$next[0:0]$9616 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9617 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__is_signed$17$next[0:0]$9618 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9619 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9620 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__output_carry$15$next[0:0]$9621 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9622 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9623 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9624 - attribute \src "libresoc.v:161187.3-161228.6" - wire $1\logical_op__zero_a$11$next[0:0]$9625 - attribute \src "libresoc.v:161174.3-161186.6" - wire width 2 $1\muxid$1$next[1:0]$9588 - attribute \src "libresoc.v:161080.3-161098.6" - wire width 64 $1\o$next[63:0]$9561 - attribute \src "libresoc.v:160269.14-160269.38" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:161080.3-161098.6" - wire $1\o_ok$next[0:0]$9562 - attribute \src "libresoc.v:160276.7-160276.18" - wire $1\o_ok[0:0] - attribute \src "libresoc.v:161156.3-161173.6" - wire $1\r_busy$next[0:0]$9584 - attribute \src "libresoc.v:160860.7-160860.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:161118.3-161136.6" - wire width 2 $1\xer_ov$next[1:0]$9573 - attribute \src "libresoc.v:160875.13-160875.26" - wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:161118.3-161136.6" - wire $1\xer_ov_ok$next[0:0]$9574 - attribute \src "libresoc.v:160882.7-160882.23" - wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:161137.3-161155.6" - wire $1\xer_so$20$next[0:0]$9580 - attribute \src "libresoc.v:161137.3-161155.6" - wire $1\xer_so_ok$next[0:0]$9579 - attribute \src "libresoc.v:160900.7-160900.23" - wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:161099.3-161117.6" - wire $2\cr_a_ok$next[0:0]$9569 - attribute \src "libresoc.v:161187.3-161228.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9626 - attribute \src "libresoc.v:161187.3-161228.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9627 - attribute \src "libresoc.v:161187.3-161228.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9628 - attribute \src "libresoc.v:161187.3-161228.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9629 - attribute \src "libresoc.v:161187.3-161228.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9630 - attribute \src "libresoc.v:161187.3-161228.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9631 - attribute \src "libresoc.v:161080.3-161098.6" - wire $2\o_ok$next[0:0]$9563 - attribute \src "libresoc.v:161156.3-161173.6" - wire $2\r_busy$next[0:0]$9585 - attribute \src "libresoc.v:161118.3-161136.6" - wire $2\xer_ov_ok$next[0:0]$9575 - attribute \src "libresoc.v:161137.3-161155.6" - wire $2\xer_so_ok$next[0:0]$9581 - attribute \src "libresoc.v:160909.18-160909.118" - wire $and$libresoc.v:160909$9509_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:10430.3-10449.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\reg1[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\reg2[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\reg3[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $0\rego[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:10384.3-10393.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10420.3-10429.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10394.3-10409.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:10410.3-10419.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $0\traptype[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_in2$1[2:0]$316 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_in2_ok$2[0:0]$317 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$3[0:0]$319 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$4[0:0]$320 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$5[0:0]$321 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$6[0:0]$322 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$7[0:0]$323 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$8[0:0]$324 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal$9[0:0]$325 + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\exc_$signal[0:0]$318 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $1\fn_unit[11:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:10430.3-10449.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\reg1[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\reg2[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\reg3[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $1\rego[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\rego_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $1\spr1[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $1\spro[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\spro_ok[0:0] + attribute \src "libresoc.v:10384.3-10393.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10420.3-10429.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10394.3-10409.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "libresoc.v:10410.3-10419.6" + wire $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $1\traptype[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $1\xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $1\xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $2\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_in2$1[2:0]$326 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_in2_ok$2[0:0]$327 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$3[0:0]$329 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$4[0:0]$330 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$5[0:0]$331 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$6[0:0]$332 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$7[0:0]$333 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$8[0:0]$334 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal$9[0:0]$335 + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\exc_$signal[0:0]$328 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $2\fn_unit[11:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $2\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $2\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $2\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\is_32bit[0:0] + attribute \src "libresoc.v:10430.3-10449.6" + wire $2\is_priv_insn[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $2\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\oe_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\rc[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\rc_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\reg1[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\reg1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\reg2[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\reg2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\reg3[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\reg3_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $2\rego[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\rego_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $2\spr1[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\spr1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $2\spro[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\spro_ok[0:0] + attribute \src "libresoc.v:10394.3-10409.6" + wire width 3 $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 13 $2\trapaddr[12:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $2\traptype[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $2\xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $2\xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $3\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $3\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_in2$1[2:0]$336 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_in2_ok$2[0:0]$337 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $3\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $3\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $3\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal$3[0:0]$339 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal$4[0:0]$340 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal$5[0:0]$341 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal$6[0:0]$342 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal$7[0:0]$343 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal$8[0:0]$344 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal$9[0:0]$345 + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\exc_$signal[0:0]$338 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $3\fn_unit[11:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $3\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $3\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $3\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\is_32bit[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $3\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\oe[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\oe_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\rc[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\rc_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $3\reg1[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\reg1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $3\reg2[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\reg2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $3\reg3[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\reg3_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $3\rego[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\rego_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $3\spr1[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\spr1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 10 $3\spro[9:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\spro_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 13 $3\trapaddr[12:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $3\traptype[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $3\xer_in[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $3\xer_out[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $4\asmcode[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $4\cia[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\cr_in1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\cr_in1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\cr_in2$1[2:0]$346 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\cr_in2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\cr_in2_ok$2[0:0]$347 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\cr_in2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\cr_out[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\cr_out_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $4\cr_rd[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\cr_rd_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 8 $4\cr_wr[7:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\cr_wr_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 5 $4\ea[4:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\ea_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal$3[0:0]$349 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal$4[0:0]$350 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal$5[0:0]$351 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal$6[0:0]$352 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal$7[0:0]$353 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal$8[0:0]$354 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal$9[0:0]$355 + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\exc_$signal[0:0]$348 + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\fast1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\fast1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\fast2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\fast2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\fasto1[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\fasto1_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 3 $4\fasto2[2:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\fasto2_ok[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 12 $4\fn_unit[11:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 2 $4\input_carry[1:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 32 $4\insn[31:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 7 $4\insn_type[6:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\is_32bit[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\lk[0:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire width 64 $4\msr[63:0] + attribute \src "libresoc.v:10450.3-10607.6" + wire $4\oe[0:0] + attribute \src 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attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178" + wire width 4 \dec_b_sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$97 + wire width 5 \dec_c_reg_c attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \cr_a$next + wire \dec_c_reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" + wire width 2 \dec_c_sel_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec_cr_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 57 \cr_a_ok + wire width 3 \dec_cr_in_cr_bitfield attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$67 + wire width 3 \dec_cr_in_cr_bitfield_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$69 + wire \dec_cr_in_cr_bitfield_b_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$98 + wire width 3 \dec_cr_in_cr_bitfield_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "libresoc.v:159780.7-159780.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$93 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 37 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$3$next + wire \dec_cr_in_cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_in_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \dec_cr_in_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_in_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:488" + wire width 3 \dec_cr_in_sel_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec_cr_out_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \dec_cr_out_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_cry_in attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -329615,128 +14108,39 @@ module \pipe_end attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 38 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 39 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$80 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 46 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$12$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$19$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$94 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 \dec_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 \dec_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -329811,10 +14215,275 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 36 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:904" + wire \dec_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec_o2_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o2_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" + wire \dec_o2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec_o2_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o2_reg_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec_o_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec_o_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311" + wire width 2 \dec_o_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 50 \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 51 \exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 52 \exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 53 \exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 54 \exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 55 \exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 56 \exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 57 \exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:903" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 12 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:906" + wire \illeg_ok + attribute \src "libresoc.v:8640.7-8640.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:409" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:446" + wire width 32 \insn_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 32 \insn_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" + wire width 32 \insn_in$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:283" + wire width 32 \insn_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312" + wire width 32 \insn_in$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367" + wire width 32 \insn_in$41 attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -329889,423 +14558,591 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 47 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$13$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$14$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 35 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 34 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire output 63 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:905" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 2 \sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_in2$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \tmp_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \tmp_reg2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 output 54 \o + wire \tmp_reg2_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$95 + wire width 5 \tmp_reg3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \o$next + wire \tmp_reg3_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 55 \o_ok + wire width 5 \tmp_rego attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$96 + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \o_ok$next + wire width 10 \tmp_spr1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a + wire \tmp_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 4 \output_cr_a$62 + wire width 10 \tmp_spro attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_cr_a_ok - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__output_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__ok$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__rc__rc$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_logical_op__write_cr0$54 - attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \tmp_tmp_exc_$signal$27 attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -330319,108 +15156,16 @@ module \pipe_end attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \output_stage_logical_op__fn_unit$23 - attribute \src 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\enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 \tmp_tmp_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 \tmp_tmp_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -330495,943 +15240,481 @@ module \pipe_end attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \output_stage_logical_op__insn_type$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_in$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__output_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \output_stage_logical_op__zero_a$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \output_stage_muxid$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \output_stage_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \output_stage_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \output_stage_remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_stage_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \output_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_stage_xer_so$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \output_xer_ov$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \output_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 31 \quotient_root - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 32 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 output 58 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 59 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 60 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 61 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 \tmp_tmp_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_msr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$102 + wire \tmp_tmp_oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$71 + wire \tmp_tmp_oe_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$72 + wire \tmp_tmp_rc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:160909$9509 + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 output 58 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 output 20 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire output 21 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:909" + cell $and $and$libresoc.v:10239$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \p_valid_i$73 - connect \B \p_ready_o - connect \Y $and$libresoc.v:160909$9509_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:160966.10-160969.4" - cell \n$82 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:160970.15-161022.4" - cell \output$83 \output - connect \cr_a \output_cr_a - connect \cr_a$22 \output_cr_a$62 - connect \cr_a_ok \output_cr_a_ok - connect \logical_op__data_len \output_logical_op__data_len - connect \logical_op__data_len$18 \output_logical_op__data_len$58 - connect \logical_op__fn_unit \output_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 - connect \logical_op__imm_data__data \output_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 - connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 - connect \logical_op__input_carry \output_logical_op__input_carry - connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 - connect \logical_op__insn \output_logical_op__insn - connect \logical_op__insn$19 \output_logical_op__insn$59 - connect \logical_op__insn_type \output_logical_op__insn_type - connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 - connect \logical_op__invert_in \output_logical_op__invert_in - connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 - connect \logical_op__invert_out \output_logical_op__invert_out - connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 - connect \logical_op__is_32bit \output_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 - connect \logical_op__is_signed \output_logical_op__is_signed - connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 - connect \logical_op__oe__oe \output_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 - connect \logical_op__oe__ok \output_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 - connect \logical_op__output_carry \output_logical_op__output_carry - connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 - connect \logical_op__rc__ok \output_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 - connect \logical_op__rc__rc \output_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 - connect \logical_op__write_cr0 \output_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 - connect \logical_op__zero_a \output_logical_op__zero_a - connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 - connect \muxid \output_muxid - connect \muxid$1 \output_muxid$41 - connect \o \output_o - connect \o$20 \output_o$60 - connect \o_ok \output_o_ok - connect \o_ok$21 \output_o_ok$61 - connect \xer_ov \output_xer_ov - connect \xer_ov$23 \output_xer_ov$63 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so \output_xer_so - connect \xer_so$24 \output_xer_so$64 - connect \xer_so_ok \output_xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:161023.16-161075.4" - cell \output_stage \output_stage - connect \div_by_zero \output_stage_div_by_zero - connect \dive_abs_ov32 \output_stage_dive_abs_ov32 - connect \dive_abs_ov64 \output_stage_dive_abs_ov64 - connect \dividend_neg \output_stage_dividend_neg - connect \divisor_neg \output_stage_divisor_neg - connect \logical_op__data_len \output_stage_logical_op__data_len - connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 - connect \logical_op__fn_unit \output_stage_logical_op__fn_unit - connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 - connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 - connect \logical_op__input_carry \output_stage_logical_op__input_carry - connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 - connect \logical_op__insn \output_stage_logical_op__insn - connect \logical_op__insn$19 \output_stage_logical_op__insn$39 - connect \logical_op__insn_type \output_stage_logical_op__insn_type - connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 - connect \logical_op__invert_in \output_stage_logical_op__invert_in - connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 - connect \logical_op__invert_out \output_stage_logical_op__invert_out - connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 - connect \logical_op__is_32bit \output_stage_logical_op__is_32bit - connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 - connect \logical_op__is_signed \output_stage_logical_op__is_signed - connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 - connect \logical_op__oe__oe \output_stage_logical_op__oe__oe - connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 - connect \logical_op__oe__ok \output_stage_logical_op__oe__ok - connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 - connect \logical_op__output_carry \output_stage_logical_op__output_carry - connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 - connect \logical_op__rc__ok \output_stage_logical_op__rc__ok - connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 - connect \logical_op__rc__rc \output_stage_logical_op__rc__rc - connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 - connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 - connect \logical_op__zero_a \output_stage_logical_op__zero_a - connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 - connect \muxid \output_stage_muxid - connect \muxid$1 \output_stage_muxid$21 - connect \o \output_stage_o - connect \o_ok \output_stage_o_ok - connect \quotient_root \output_stage_quotient_root - connect \remainder \output_stage_remainder - connect \xer_ov \output_stage_xer_ov - connect \xer_ov_ok \output_stage_xer_ov_ok - connect \xer_so \output_stage_xer_so - connect \xer_so$20 \output_stage_xer_so$40 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:161076.10-161079.4" - cell \p$81 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:159780.7-159780.20" - process $proc$libresoc.v:159780$9632 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:159789.13-159789.24" - process $proc$libresoc.v:159789$9633 - assign { } { } - assign $1\cr_a[3:0] 4'0000 - sync always - sync init - update \cr_a $1\cr_a[3:0] - end - attribute \src "libresoc.v:159798.7-159798.21" - process $proc$libresoc.v:159798$9634 - assign { } { } - assign $1\cr_a_ok[0:0] 1'0 - sync always - sync init - update \cr_a_ok $1\cr_a_ok[0:0] - end - attribute \src "libresoc.v:159821.13-159821.45" - process $proc$libresoc.v:159821$9635 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$9636 4'0000 - sync always - sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9636 - end - attribute \src "libresoc.v:159856.14-159856.47" - process $proc$libresoc.v:159856$9637 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$9638 12'000000000000 - sync always - sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9638 - end - attribute \src "libresoc.v:159878.14-159878.67" - process $proc$libresoc.v:159878$9639 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9640 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9640 - end - attribute \src "libresoc.v:159887.7-159887.42" - process $proc$libresoc.v:159887$9641 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9642 1'0 - sync always - sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9642 - end - attribute \src "libresoc.v:159904.13-159904.48" - process $proc$libresoc.v:159904$9643 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9644 2'00 - sync always - sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9644 - end - attribute \src "libresoc.v:159917.14-159917.43" - process $proc$libresoc.v:159917$9645 - assign { } { } - assign $0\logical_op__insn$19[31:0]$9646 0 - sync always - sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9646 - end - attribute \src "libresoc.v:160074.13-160074.46" - process $proc$libresoc.v:160074$9647 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9648 7'0000000 - sync always - sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9648 - end - attribute \src "libresoc.v:160157.7-160157.40" - process $proc$libresoc.v:160157$9649 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9650 1'0 - sync always - sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9650 - end - attribute \src "libresoc.v:160166.7-160166.41" - process $proc$libresoc.v:160166$9651 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9652 1'0 - sync always - sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9652 - end - attribute \src "libresoc.v:160175.7-160175.39" - process $proc$libresoc.v:160175$9653 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9654 1'0 - sync always - sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9654 - end - attribute \src "libresoc.v:160184.7-160184.40" - process $proc$libresoc.v:160184$9655 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9656 1'0 - sync always - sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9656 - end - attribute \src "libresoc.v:160193.7-160193.36" - process $proc$libresoc.v:160193$9657 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9658 1'0 - sync always - sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9658 - end - attribute \src "libresoc.v:160204.7-160204.36" - process $proc$libresoc.v:160204$9659 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9660 1'0 - sync always - sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9660 - end - attribute \src "libresoc.v:160211.7-160211.43" - process $proc$libresoc.v:160211$9661 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9662 1'0 - sync always - sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9662 - end - attribute \src "libresoc.v:160220.7-160220.36" - process $proc$libresoc.v:160220$9663 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9664 1'0 - sync always - sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9664 - end - attribute \src "libresoc.v:160229.7-160229.36" - process $proc$libresoc.v:160229$9665 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9666 1'0 - sync always - sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9666 - end - attribute \src "libresoc.v:160238.7-160238.40" - process $proc$libresoc.v:160238$9667 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9668 1'0 - sync always - sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9668 - end - attribute \src "libresoc.v:160247.7-160247.37" - process $proc$libresoc.v:160247$9669 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9670 1'0 - sync always - sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9670 - end - attribute \src "libresoc.v:160256.13-160256.29" - process $proc$libresoc.v:160256$9671 - assign { } { } - assign $0\muxid$1[1:0]$9672 2'00 - sync always - sync init - update \muxid$1 $0\muxid$1[1:0]$9672 - end - attribute \src "libresoc.v:160269.14-160269.38" - process $proc$libresoc.v:160269$9673 - assign { } { } - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \o $1\o[63:0] - end - attribute \src "libresoc.v:160276.7-160276.18" - process $proc$libresoc.v:160276$9674 - assign { } { } - assign $1\o_ok[0:0] 1'0 - sync always - sync init - update \o_ok $1\o_ok[0:0] - end - attribute \src "libresoc.v:160860.7-160860.20" - process $proc$libresoc.v:160860$9675 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:160875.13-160875.26" - process $proc$libresoc.v:160875$9676 - assign { } { } - assign $1\xer_ov[1:0] 2'00 - sync always - sync init - update \xer_ov $1\xer_ov[1:0] - end - attribute \src "libresoc.v:160882.7-160882.23" - process $proc$libresoc.v:160882$9677 - assign { } { } - assign $1\xer_ov_ok[0:0] 1'0 - sync always - sync init - update \xer_ov_ok $1\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:160895.7-160895.25" - process $proc$libresoc.v:160895$9678 - assign { } { } - assign $0\xer_so$20[0:0]$9679 1'0 - sync always - sync init - update \xer_so$20 $0\xer_so$20[0:0]$9679 - end - attribute \src "libresoc.v:160900.7-160900.23" - process $proc$libresoc.v:160900$9680 - assign { } { } - assign $1\xer_so_ok[0:0] 1'0 - sync always - sync init - update \xer_so_ok $1\xer_so_ok[0:0] - end - attribute \src "libresoc.v:160910.3-160911.37" - process $proc$libresoc.v:160910$9510 - assign { } { } - assign $0\xer_so$20[0:0]$9511 \xer_so$20$next - sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9511 - end - attribute \src "libresoc.v:160912.3-160913.35" - process $proc$libresoc.v:160912$9512 - assign { } { } - assign $0\xer_so_ok[0:0] \xer_so_ok$next - sync posedge \coresync_clk - update \xer_so_ok $0\xer_so_ok[0:0] - end - attribute \src "libresoc.v:160914.3-160915.29" - process $proc$libresoc.v:160914$9513 - assign { } { } - assign $0\xer_ov[1:0] \xer_ov$next - sync posedge \coresync_clk - update \xer_ov $0\xer_ov[1:0] - end - attribute \src "libresoc.v:160916.3-160917.35" - process $proc$libresoc.v:160916$9514 - assign { } { } - assign $0\xer_ov_ok[0:0] \xer_ov_ok$next - sync posedge \coresync_clk - update \xer_ov_ok $0\xer_ov_ok[0:0] - end - attribute \src "libresoc.v:160918.3-160919.25" - process $proc$libresoc.v:160918$9515 - assign { } { } - assign $0\cr_a[3:0] \cr_a$next - sync posedge \coresync_clk - update \cr_a $0\cr_a[3:0] - end - attribute \src "libresoc.v:160920.3-160921.31" - process $proc$libresoc.v:160920$9516 - assign { } { } - assign $0\cr_a_ok[0:0] \cr_a_ok$next - sync posedge \coresync_clk - update \cr_a_ok $0\cr_a_ok[0:0] - end - attribute \src "libresoc.v:160922.3-160923.19" - process $proc$libresoc.v:160922$9517 - assign { } { } - assign $0\o[63:0] \o$next - sync posedge \coresync_clk - update \o $0\o[63:0] - end - attribute \src "libresoc.v:160924.3-160925.25" - process $proc$libresoc.v:160924$9518 - assign { } { } - assign $0\o_ok[0:0] \o_ok$next - sync posedge \coresync_clk - update \o_ok $0\o_ok[0:0] + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10239$296_Y end - attribute \src "libresoc.v:160926.3-160927.65" - process $proc$libresoc.v:160926$9519 - assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9520 \logical_op__insn_type$2$next - sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + cell $and $and$libresoc.v:10240$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:10240$297_Y end - attribute \src "libresoc.v:160928.3-160929.61" - process $proc$libresoc.v:160928$9521 - assign { } { } - assign $0\logical_op__fn_unit$3[11:0]$9522 \logical_op__fn_unit$3$next - sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$9522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:911" + cell $and $and$libresoc.v:10241$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:10241$298_Y end - attribute \src "libresoc.v:160930.3-160931.75" - process $proc$libresoc.v:160930$9523 - assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9524 \logical_op__imm_data__data$4$next - sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:960" + cell $eq $eq$libresoc.v:10231$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10231$288_Y end - attribute \src "libresoc.v:160932.3-160933.71" - process $proc$libresoc.v:160932$9525 - assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9526 \logical_op__imm_data__ok$5$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9526 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $eq $eq$libresoc.v:10232$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:10232$289_Y end - attribute \src "libresoc.v:160934.3-160935.59" - process $proc$libresoc.v:160934$9527 - assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9528 \logical_op__rc__rc$6$next - sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + cell $eq $eq$libresoc.v:10234$291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:10234$291_Y end - attribute \src "libresoc.v:160936.3-160937.59" - process $proc$libresoc.v:160936$9529 - assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9530 \logical_op__rc__ok$7$next - sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + cell $eq $eq$libresoc.v:10235$292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:10235$292_Y end - attribute \src "libresoc.v:160938.3-160939.59" - process $proc$libresoc.v:160938$9531 - assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9532 \logical_op__oe__oe$8$next - sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9532 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + cell $eq $eq$libresoc.v:10236$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:10236$293_Y end - attribute \src "libresoc.v:160940.3-160941.59" - process $proc$libresoc.v:160940$9533 - assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9534 \logical_op__oe__ok$9$next - sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + cell $eq $eq$libresoc.v:10237$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:10237$294_Y end - attribute \src "libresoc.v:160942.3-160943.67" - process $proc$libresoc.v:160942$9535 - assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9536 \logical_op__invert_in$10$next - sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + cell $eq $eq$libresoc.v:10238$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:10238$295_Y end - attribute \src "libresoc.v:160944.3-160945.61" - process $proc$libresoc.v:160944$9537 - assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9538 \logical_op__zero_a$11$next - sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9538 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:912" + cell $eq $eq$libresoc.v:10242$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:10242$299_Y end - attribute \src "libresoc.v:160946.3-160947.71" - process $proc$libresoc.v:160946$9539 - assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9540 \logical_op__input_carry$12$next - sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9540 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + cell $or $or$libresoc.v:10233$290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \B \$30 + connect \Y $or$libresoc.v:10233$290_Y end - attribute \src "libresoc.v:160948.3-160949.69" - process $proc$libresoc.v:160948$9541 - assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9542 \logical_op__invert_out$13$next - sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9542 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10243.7-10280.4" + cell \dec \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd end - attribute \src "libresoc.v:160950.3-160951.67" - process $proc$libresoc.v:160950$9543 - assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9544 \logical_op__write_cr0$14$next - sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9544 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10281.9-10295.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok end - attribute \src "libresoc.v:160952.3-160953.73" - process $proc$libresoc.v:160952$9545 - assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9546 \logical_op__output_carry$15$next - sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9546 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10296.9-10306.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in end - attribute \src "libresoc.v:160954.3-160955.65" - process $proc$libresoc.v:160954$9547 - assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9548 \logical_op__is_32bit$16$next - sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9548 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10307.9-10313.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in end - attribute \src "libresoc.v:160956.3-160957.67" - process $proc$libresoc.v:160956$9549 - assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9550 \logical_op__is_signed$17$next - sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9550 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10314.13-10333.4" + cell \dec_cr_in \dec_cr_in$10 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in end - attribute \src "libresoc.v:160958.3-160959.65" - process $proc$libresoc.v:160958$9551 - assign { } { } - assign $0\logical_op__data_len$18[3:0]$9552 \logical_op__data_len$18$next - sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9552 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10334.14-10346.4" + cell \dec_cr_out \dec_cr_out$11 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in end - attribute \src "libresoc.v:160960.3-160961.57" - process $proc$libresoc.v:160960$9553 - assign { } { } - assign $0\logical_op__insn$19[31:0]$9554 \logical_op__insn$19$next - sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9554 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10347.9-10360.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok end - attribute \src "libresoc.v:160962.3-160963.33" - process $proc$libresoc.v:160962$9555 - assign { } { } - assign $0\muxid$1[1:0]$9556 \muxid$1$next - sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9556 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10361.10-10370.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \upd \dec_upd end - attribute \src "libresoc.v:160964.3-160965.29" - process $proc$libresoc.v:160964$9557 - assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:10371.10-10377.4" + cell \dec_oe \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in end - attribute \src "libresoc.v:161080.3-161098.6" - process $proc$libresoc.v:161080$9558 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\o$next[63:0]$9559 $1\o$next[63:0]$9561 - assign { } { } - assign $0\o_ok$next[0:0]$9560 $2\o_ok$next[0:0]$9563 - attribute \src "libresoc.v:161081.5-161081.29" - switch \initial - attribute \src "libresoc.v:161081.9-161081.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$9562 $1\o$next[63:0]$9561 } { \o_ok$96 \o$95 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\o_ok$next[0:0]$9562 $1\o$next[63:0]$9561 } { \o_ok$96 \o$95 } - case - assign $1\o$next[63:0]$9561 \o - assign $1\o_ok$next[0:0]$9562 \o_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\o_ok$next[0:0]$9563 1'0 - case - assign $2\o_ok$next[0:0]$9563 $1\o_ok$next[0:0]$9562 - end - sync always - update \o$next $0\o$next[63:0]$9559 - update \o_ok$next $0\o_ok$next[0:0]$9560 + attribute \module_not_derived 1 + attribute \src "libresoc.v:10378.10-10383.4" + cell \dec_rc \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:161099.3-161117.6" - process $proc$libresoc.v:161099$9564 + attribute \src "libresoc.v:10384.3-10393.6" + process $proc$libresoc.v:10384$300 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\cr_a$next[3:0]$9565 $1\cr_a$next[3:0]$9567 - assign { } { } - assign $0\cr_a_ok$next[0:0]$9566 $2\cr_a_ok$next[0:0]$9569 - attribute \src "libresoc.v:161100.5-161100.29" + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:10385.5-10385.29" switch \initial - attribute \src "libresoc.v:161100.9-161100.17" + attribute \src "libresoc.v:10385.9-10385.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9568 $1\cr_a$next[3:0]$9567 } { \cr_a_ok$98 \cr_a$97 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\cr_a_ok$next[0:0]$9568 $1\cr_a$next[3:0]$9567 } { \cr_a_ok$98 \cr_a$97 } - case - assign $1\cr_a$next[3:0]$9567 \cr_a - assign $1\cr_a_ok$next[0:0]$9568 \cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:762" + switch \dec_lk attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9569 1'0 + assign $1\tmp_tmp_lk[0:0] \dec_LK case - assign $2\cr_a_ok$next[0:0]$9569 $1\cr_a_ok$next[0:0]$9568 + assign $1\tmp_tmp_lk[0:0] 1'0 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9565 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9566 + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:161118.3-161136.6" - process $proc$libresoc.v:161118$9570 - assign { } { } + attribute \src "libresoc.v:10394.3-10409.6" + process $proc$libresoc.v:10394$301 assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9571 $1\xer_ov$next[1:0]$9573 - assign { } { } - assign $0\xer_ov_ok$next[0:0]$9572 $2\xer_ov_ok$next[0:0]$9575 - attribute \src "libresoc.v:161119.5-161119.29" + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:10395.5-10395.29" switch \initial - attribute \src "libresoc.v:161119.9-161119.17" + attribute \src "libresoc.v:10395.9-10395.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9574 $1\xer_ov$next[1:0]$9573 } { \xer_ov_ok$100 \xer_ov$99 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9574 $1\xer_ov$next[1:0]$9573 } { \xer_ov_ok$100 \xer_ov$99 } - case - assign $1\xer_ov$next[1:0]$9573 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9574 \xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:878" + switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9575 1'0 - case - assign $2\xer_ov_ok$next[0:0]$9575 $1\xer_ov_ok$next[0:0]$9574 - end - sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9571 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9572 - end - attribute \src "libresoc.v:161137.3-161155.6" - process $proc$libresoc.v:161137$9576 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\xer_so$20$next[0:0]$9578 $1\xer_so$20$next[0:0]$9580 - assign $0\xer_so_ok$next[0:0]$9577 $2\xer_so_ok$next[0:0]$9581 - attribute \src "libresoc.v:161138.5-161138.29" - switch \initial - attribute \src "libresoc.v:161138.9-161138.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$9579 $1\xer_so$20$next[0:0]$9580 } { \xer_so_ok$102 \xer_so$101 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- - assign { } { } - assign { } { } - assign { $1\xer_so_ok$next[0:0]$9579 $1\xer_so$20$next[0:0]$9580 } { \xer_so_ok$102 \xer_so$101 } + assign $1\tmp_xer_in[2:0] 3'111 case - assign $1\xer_so_ok$next[0:0]$9579 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9580 \xer_so$20 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:880" + switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9581 1'0 + assign $2\tmp_xer_in[2:0] 3'001 case - assign $2\xer_so_ok$next[0:0]$9581 $1\xer_so_ok$next[0:0]$9579 + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9577 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9578 + update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:161156.3-161173.6" - process $proc$libresoc.v:161156$9582 + attribute \src "libresoc.v:10410.3-10419.6" + process $proc$libresoc.v:10410$302 assign { } { } assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$9583 $2\r_busy$next[0:0]$9585 - attribute \src "libresoc.v:161157.5-161157.29" + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:10411.5-10411.29" switch \initial - attribute \src "libresoc.v:161157.9-161157.17" + attribute \src "libresoc.v:10411.9-10411.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign $1\r_busy$next[0:0]$9584 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + switch \$46 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 1'1 assign { } { } - assign $1\r_busy$next[0:0]$9584 1'0 + assign $1\tmp_xer_out[0:0] 1'1 case - assign $1\r_busy$next[0:0]$9584 \r_busy + assign $1\tmp_xer_out[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "libresoc.v:10420.3-10429.6" + process $proc$libresoc.v:10420$303 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:10421.5-10421.29" + switch \initial + attribute \src "libresoc.v:10421.9-10421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9585 1'0 + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 case - assign $2\r_busy$next[0:0]$9585 $1\r_busy$next[0:0]$9584 + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9583 + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:161174.3-161186.6" - process $proc$libresoc.v:161174$9586 + attribute \src "libresoc.v:10430.3-10449.6" + process $proc$libresoc.v:10430$304 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9587 $1\muxid$1$next[1:0]$9588 - attribute \src "libresoc.v:161175.5-161175.29" + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:10431.5-10431.29" switch \initial - attribute \src "libresoc.v:161175.9-161175.17" + attribute \src "libresoc.v:10431.9-10431.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45" + switch \dec_internal_op attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 assign { } { } - assign $1\muxid$1$next[1:0]$9588 \muxid$76 + assign $1\is_priv_insn[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 7'0101110 , 7'0110001 assign { } { } - assign $1\muxid$1$next[1:0]$9588 \muxid$76 + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:52" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end case - assign $1\muxid$1$next[1:0]$9588 \muxid$1 + assign $1\is_priv_insn[0:0] 1'0 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9587 + update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:161187.3-161228.6" - process $proc$libresoc.v:161187$9589 + attribute \src "libresoc.v:10450.3-10607.6" + process $proc$libresoc.v:10450$305 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -331468,40 +15751,1027 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9590 $1\logical_op__data_len$18$next[3:0]$9608 - assign $0\logical_op__fn_unit$3$next[11:0]$9591 $1\logical_op__fn_unit$3$next[11:0]$9609 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9594 $1\logical_op__input_carry$12$next[1:0]$9612 - assign $0\logical_op__insn$19$next[31:0]$9595 $1\logical_op__insn$19$next[31:0]$9613 - assign $0\logical_op__insn_type$2$next[6:0]$9596 $1\logical_op__insn_type$2$next[6:0]$9614 - assign $0\logical_op__invert_in$10$next[0:0]$9597 $1\logical_op__invert_in$10$next[0:0]$9615 - assign $0\logical_op__invert_out$13$next[0:0]$9598 $1\logical_op__invert_out$13$next[0:0]$9616 - assign $0\logical_op__is_32bit$16$next[0:0]$9599 $1\logical_op__is_32bit$16$next[0:0]$9617 - assign $0\logical_op__is_signed$17$next[0:0]$9600 $1\logical_op__is_signed$17$next[0:0]$9618 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9603 $1\logical_op__output_carry$15$next[0:0]$9621 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9606 $1\logical_op__write_cr0$14$next[0:0]$9624 - assign $0\logical_op__zero_a$11$next[0:0]$9607 $1\logical_op__zero_a$11$next[0:0]$9625 - assign $0\logical_op__imm_data__data$4$next[63:0]$9592 $2\logical_op__imm_data__data$4$next[63:0]$9626 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9593 $2\logical_op__imm_data__ok$5$next[0:0]$9627 - assign $0\logical_op__oe__oe$8$next[0:0]$9601 $2\logical_op__oe__oe$8$next[0:0]$9628 - assign $0\logical_op__oe__ok$9$next[0:0]$9602 $2\logical_op__oe__ok$9$next[0:0]$9629 - assign $0\logical_op__rc__ok$7$next[0:0]$9604 $2\logical_op__rc__ok$7$next[0:0]$9630 - assign $0\logical_op__rc__rc$6$next[0:0]$9605 $2\logical_op__rc__rc$6$next[0:0]$9631 - attribute \src "libresoc.v:161188.5-161188.29" + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[2:0] $1\cr_in2[2:0] + assign $0\cr_in2$1[2:0]$306 $1\cr_in2$1[2:0]$316 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$307 $1\cr_in2_ok$2[0:0]$317 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\ea[4:0] $1\ea[4:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign $0\exc_$signal[0:0]$308 $1\exc_$signal[0:0]$318 + assign $0\exc_$signal$3[0:0]$309 $1\exc_$signal$3[0:0]$319 + assign $0\exc_$signal$4[0:0]$310 $1\exc_$signal$4[0:0]$320 + assign $0\exc_$signal$5[0:0]$311 $1\exc_$signal$5[0:0]$321 + assign $0\exc_$signal$6[0:0]$312 $1\exc_$signal$6[0:0]$322 + assign $0\exc_$signal$7[0:0]$313 $1\exc_$signal$7[0:0]$323 + assign $0\exc_$signal$8[0:0]$314 $1\exc_$signal$8[0:0]$324 + assign $0\exc_$signal$9[0:0]$315 $1\exc_$signal$9[0:0]$325 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc[0:0] $1\rc[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[7:0] $1\traptype[7:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $5\fasto1[2:0] + assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] + assign $0\fasto2[2:0] $5\fasto2[2:0] + assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] + assign $0\fast1[2:0] $5\fast1[2:0] + assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] + assign $0\fast2[2:0] $5\fast2[2:0] + assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:10451.5-10451.29" switch \initial - attribute \src "libresoc.v:161188.9-161188.17" + attribute \src "libresoc.v:10451.9-10451.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:916" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'----1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\asmcode[7:0] $2\asmcode[7:0] + assign $1\cr_out[2:0] $2\cr_out[2:0] + assign $1\lk[0:0] $2\lk[0:0] + assign $1\cia[63:0] $2\cia[63:0] + assign $1\cr_in1[2:0] $2\cr_in1[2:0] + assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] + assign $1\cr_in2[2:0] $2\cr_in2[2:0] + assign $1\cr_in2$1[2:0]$316 $2\cr_in2$1[2:0]$326 + assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] + assign $1\cr_in2_ok$2[0:0]$317 $2\cr_in2_ok$2[0:0]$327 + assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] + assign $1\cr_rd[7:0] $2\cr_rd[7:0] + assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] + assign $1\cr_wr[7:0] $2\cr_wr[7:0] + assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] + assign $1\ea[4:0] $2\ea[4:0] + assign $1\ea_ok[0:0] $2\ea_ok[0:0] + assign $1\exc_$signal[0:0]$318 $2\exc_$signal[0:0]$328 + assign $1\exc_$signal$3[0:0]$319 $2\exc_$signal$3[0:0]$329 + assign $1\exc_$signal$4[0:0]$320 $2\exc_$signal$4[0:0]$330 + assign $1\exc_$signal$5[0:0]$321 $2\exc_$signal$5[0:0]$331 + assign $1\exc_$signal$6[0:0]$322 $2\exc_$signal$6[0:0]$332 + assign $1\exc_$signal$7[0:0]$323 $2\exc_$signal$7[0:0]$333 + assign $1\exc_$signal$8[0:0]$324 $2\exc_$signal$8[0:0]$334 + assign $1\exc_$signal$9[0:0]$325 $2\exc_$signal$9[0:0]$335 + assign $1\fast1[2:0] $2\fast1[2:0] + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $1\fast2[2:0] $2\fast2[2:0] + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $1\fasto1[2:0] $2\fasto1[2:0] + assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $1\fasto2[2:0] $2\fasto2[2:0] + assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $1\fn_unit[11:0] $2\fn_unit[11:0] + assign $1\input_carry[1:0] $2\input_carry[1:0] + assign $1\insn[31:0] $2\insn[31:0] + assign $1\insn_type[6:0] $2\insn_type[6:0] + assign $1\is_32bit[0:0] $2\is_32bit[0:0] + assign $1\msr[63:0] $2\msr[63:0] + assign $1\oe[0:0] $2\oe[0:0] + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + assign $1\rc[0:0] $2\rc[0:0] + assign $1\rc_ok[0:0] $2\rc_ok[0:0] + assign $1\reg1[4:0] $2\reg1[4:0] + assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] + assign $1\reg2[4:0] $2\reg2[4:0] + assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] + assign $1\reg3[4:0] $2\reg3[4:0] + assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] + assign $1\rego[4:0] $2\rego[4:0] + assign $1\rego_ok[0:0] $2\rego_ok[0:0] + assign $1\spr1[9:0] $2\spr1[9:0] + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + assign $1\spro[9:0] $2\spro[9:0] + assign $1\spro_ok[0:0] $2\spro_ok[0:0] + assign $1\trapaddr[12:0] $2\trapaddr[12:0] + assign $1\traptype[7:0] $2\traptype[7:0] + assign $1\xer_in[2:0] $2\xer_in[2:0] + assign $1\xer_out[0:0] $2\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$335 $2\exc_$signal$8[0:0]$334 $2\exc_$signal$7[0:0]$333 $2\exc_$signal$6[0:0]$332 $2\exc_$signal$5[0:0]$331 $2\exc_$signal$4[0:0]$330 $2\exc_$signal$3[0:0]$329 $2\exc_$signal[0:0]$328 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[2:0] $2\cr_in2_ok$2[0:0]$327 $2\cr_in2$1[2:0]$326 $2\cr_in2_ok[0:0] $2\cr_in2[2:0] $2\cr_in1_ok[0:0] $2\cr_in1[2:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[4:0] $2\reg2_ok[0:0] $2\reg2[4:0] $2\reg1_ok[0:0] $2\reg1[4:0] $2\ea_ok[0:0] $2\ea[4:0] $2\rego_ok[0:0] $2\rego[4:0] $2\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\insn[31:0] \dec_opcode_in + assign $2\insn_type[6:0] 7'0111111 + assign $2\fn_unit[11:0] 12'000010000000 + assign $2\trapaddr[12:0] 13'0000001100000 + assign $2\traptype[7:0] 8'00000010 + assign $2\msr[63:0] \cur_msr + assign $2\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\asmcode[7:0] $3\asmcode[7:0] + assign $2\cr_out[2:0] $3\cr_out[2:0] + assign $2\lk[0:0] $3\lk[0:0] + assign $2\cia[63:0] $3\cia[63:0] + assign $2\cr_in1[2:0] $3\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $3\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$326 $3\cr_in2$1[2:0]$336 + assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$327 $3\cr_in2_ok$2[0:0]$337 + assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $3\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $3\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] + assign $2\ea[4:0] $3\ea[4:0] + assign $2\ea_ok[0:0] $3\ea_ok[0:0] + assign $2\exc_$signal[0:0]$328 $3\exc_$signal[0:0]$338 + assign $2\exc_$signal$3[0:0]$329 $3\exc_$signal$3[0:0]$339 + assign $2\exc_$signal$4[0:0]$330 $3\exc_$signal$4[0:0]$340 + assign $2\exc_$signal$5[0:0]$331 $3\exc_$signal$5[0:0]$341 + assign $2\exc_$signal$6[0:0]$332 $3\exc_$signal$6[0:0]$342 + assign $2\exc_$signal$7[0:0]$333 $3\exc_$signal$7[0:0]$343 + assign $2\exc_$signal$8[0:0]$334 $3\exc_$signal$8[0:0]$344 + assign $2\exc_$signal$9[0:0]$335 $3\exc_$signal$9[0:0]$345 + assign $2\fast1[2:0] $3\fast1[2:0] + assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] + assign $2\fast2[2:0] $3\fast2[2:0] + assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] + assign $2\fasto1[2:0] $3\fasto1[2:0] + assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] + assign $2\fasto2[2:0] $3\fasto2[2:0] + assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $3\fn_unit[11:0] + assign $2\input_carry[1:0] $3\input_carry[1:0] + assign $2\insn[31:0] $3\insn[31:0] + assign $2\insn_type[6:0] $3\insn_type[6:0] + assign $2\is_32bit[0:0] $3\is_32bit[0:0] + assign $2\msr[63:0] $3\msr[63:0] + assign $2\oe[0:0] $3\oe[0:0] + assign $2\oe_ok[0:0] $3\oe_ok[0:0] + assign $2\rc[0:0] $3\rc[0:0] + assign $2\rc_ok[0:0] $3\rc_ok[0:0] + assign $2\reg1[4:0] $3\reg1[4:0] + assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] + assign $2\reg2[4:0] $3\reg2[4:0] + assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] + assign $2\reg3[4:0] $3\reg3[4:0] + assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] + assign $2\rego[4:0] $3\rego[4:0] + assign $2\rego_ok[0:0] $3\rego_ok[0:0] + assign $2\spr1[9:0] $3\spr1[9:0] + assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] + assign $2\spro[9:0] $3\spro[9:0] + assign $2\spro_ok[0:0] $3\spro_ok[0:0] + assign $2\trapaddr[12:0] $3\trapaddr[12:0] + assign $2\traptype[7:0] $3\traptype[7:0] + assign $2\xer_in[2:0] $3\xer_in[2:0] + assign $2\xer_out[0:0] $3\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001001000 + assign $3\traptype[7:0] 8'00000010 + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[2:0] $3\cr_in2_ok$2[0:0]$337 $3\cr_in2$1[2:0]$336 $3\cr_in2_ok[0:0] $3\cr_in2[2:0] $3\cr_in1_ok[0:0] $3\cr_in1[2:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[4:0] $3\reg2_ok[0:0] $3\reg2[4:0] $3\reg1_ok[0:0] $3\reg1[4:0] $3\ea_ok[0:0] $3\ea[4:0] $3\rego_ok[0:0] $3\rego[4:0] $3\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[11:0] 12'000010000000 + assign $3\trapaddr[12:0] 13'0000001000000 + assign $3\traptype[7:0] 8'01000000 + assign { $3\exc_$signal$9[0:0]$345 $3\exc_$signal$8[0:0]$344 $3\exc_$signal$7[0:0]$343 $3\exc_$signal$6[0:0]$342 $3\exc_$signal$5[0:0]$341 $3\exc_$signal$4[0:0]$340 $3\exc_$signal$3[0:0]$339 $3\exc_$signal[0:0]$338 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\asmcode[7:0] $4\asmcode[7:0] + assign $2\cr_out[2:0] $4\cr_out[2:0] + assign $2\lk[0:0] $4\lk[0:0] + assign $2\cia[63:0] $4\cia[63:0] + assign $2\cr_in1[2:0] $4\cr_in1[2:0] + assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] + assign $2\cr_in2[2:0] $4\cr_in2[2:0] + assign $2\cr_in2$1[2:0]$326 $4\cr_in2$1[2:0]$346 + assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$327 $4\cr_in2_ok$2[0:0]$347 + assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $4\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $4\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] + assign $2\ea[4:0] $4\ea[4:0] + assign $2\ea_ok[0:0] $4\ea_ok[0:0] + assign $2\exc_$signal[0:0]$328 $4\exc_$signal[0:0]$348 + assign $2\exc_$signal$3[0:0]$329 $4\exc_$signal$3[0:0]$349 + assign $2\exc_$signal$4[0:0]$330 $4\exc_$signal$4[0:0]$350 + assign $2\exc_$signal$5[0:0]$331 $4\exc_$signal$5[0:0]$351 + assign $2\exc_$signal$6[0:0]$332 $4\exc_$signal$6[0:0]$352 + assign $2\exc_$signal$7[0:0]$333 $4\exc_$signal$7[0:0]$353 + assign $2\exc_$signal$8[0:0]$334 $4\exc_$signal$8[0:0]$354 + assign $2\exc_$signal$9[0:0]$335 $4\exc_$signal$9[0:0]$355 + assign $2\fast1[2:0] $4\fast1[2:0] + assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] + assign $2\fast2[2:0] $4\fast2[2:0] + assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] + assign $2\fasto1[2:0] $4\fasto1[2:0] + assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] + assign $2\fasto2[2:0] $4\fasto2[2:0] + assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] + assign $2\fn_unit[11:0] $4\fn_unit[11:0] + assign $2\input_carry[1:0] $4\input_carry[1:0] + assign $2\insn[31:0] $4\insn[31:0] + assign $2\insn_type[6:0] $4\insn_type[6:0] + assign $2\is_32bit[0:0] $4\is_32bit[0:0] + assign $2\msr[63:0] $4\msr[63:0] + assign $2\oe[0:0] $4\oe[0:0] + assign $2\oe_ok[0:0] $4\oe_ok[0:0] + assign $2\rc[0:0] $4\rc[0:0] + assign $2\rc_ok[0:0] $4\rc_ok[0:0] + assign $2\reg1[4:0] $4\reg1[4:0] + assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] + assign $2\reg2[4:0] $4\reg2[4:0] + assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] + assign $2\reg3[4:0] $4\reg3[4:0] + assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] + assign $2\rego[4:0] $4\rego[4:0] + assign $2\rego_ok[0:0] $4\rego_ok[0:0] + assign $2\spr1[9:0] $4\spr1[9:0] + assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] + assign $2\spro[9:0] $4\spro[9:0] + assign $2\spro_ok[0:0] $4\spro_ok[0:0] + assign $2\trapaddr[12:0] $4\trapaddr[12:0] + assign $2\traptype[7:0] $4\traptype[7:0] + assign $2\xer_in[2:0] $4\xer_in[2:0] + assign $2\xer_out[0:0] $4\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:926" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000111000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$355 $4\exc_$signal$8[0:0]$354 $4\exc_$signal$7[0:0]$353 $4\exc_$signal$6[0:0]$352 $4\exc_$signal$5[0:0]$351 $4\exc_$signal$4[0:0]$350 $4\exc_$signal$3[0:0]$349 $4\exc_$signal[0:0]$348 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[2:0] $4\cr_in2_ok$2[0:0]$347 $4\cr_in2$1[2:0]$346 $4\cr_in2_ok[0:0] $4\cr_in2[2:0] $4\cr_in1_ok[0:0] $4\cr_in1[2:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[4:0] $4\reg2_ok[0:0] $4\reg2[4:0] $4\reg1_ok[0:0] $4\reg1[4:0] $4\ea_ok[0:0] $4\ea[4:0] $4\rego_ok[0:0] $4\rego[4:0] $4\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[11:0] 12'000010000000 + assign $4\trapaddr[12:0] 13'0000000110000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + end + end + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[7:0] 8'00100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[7:0] 8'00010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'00000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } assign { } { } @@ -331520,9 +16790,6 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9613 $1\logical_op__data_len$18$next[3:0]$9608 $1\logical_op__is_signed$17$next[0:0]$9618 $1\logical_op__is_32bit$16$next[0:0]$9617 $1\logical_op__output_carry$15$next[0:0]$9621 $1\logical_op__write_cr0$14$next[0:0]$9624 $1\logical_op__invert_out$13$next[0:0]$9616 $1\logical_op__input_carry$12$next[1:0]$9612 $1\logical_op__zero_a$11$next[0:0]$9625 $1\logical_op__invert_in$10$next[0:0]$9615 $1\logical_op__oe__ok$9$next[0:0]$9620 $1\logical_op__oe__oe$8$next[0:0]$9619 $1\logical_op__rc__ok$7$next[0:0]$9622 $1\logical_op__rc__rc$6$next[0:0]$9623 $1\logical_op__imm_data__ok$5$next[0:0]$9611 $1\logical_op__imm_data__data$4$next[63:0]$9610 $1\logical_op__fn_unit$3$next[11:0]$9609 $1\logical_op__insn_type$2$next[6:0]$9614 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } - attribute \src "libresoc.v:0.0-0.0" - case 2'1- assign { } { } assign { } { } assign { } { } @@ -331541,1919 +16808,34 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9613 $1\logical_op__data_len$18$next[3:0]$9608 $1\logical_op__is_signed$17$next[0:0]$9618 $1\logical_op__is_32bit$16$next[0:0]$9617 $1\logical_op__output_carry$15$next[0:0]$9621 $1\logical_op__write_cr0$14$next[0:0]$9624 $1\logical_op__invert_out$13$next[0:0]$9616 $1\logical_op__input_carry$12$next[1:0]$9612 $1\logical_op__zero_a$11$next[0:0]$9625 $1\logical_op__invert_in$10$next[0:0]$9615 $1\logical_op__oe__ok$9$next[0:0]$9620 $1\logical_op__oe__oe$8$next[0:0]$9619 $1\logical_op__rc__ok$7$next[0:0]$9622 $1\logical_op__rc__rc$6$next[0:0]$9623 $1\logical_op__imm_data__ok$5$next[0:0]$9611 $1\logical_op__imm_data__data$4$next[63:0]$9610 $1\logical_op__fn_unit$3$next[11:0]$9609 $1\logical_op__insn_type$2$next[6:0]$9614 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } - case - assign $1\logical_op__data_len$18$next[3:0]$9608 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[11:0]$9609 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9610 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9611 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9612 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9613 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9614 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9615 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9616 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9617 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9618 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9619 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9620 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9621 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9622 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9623 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9624 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9625 \logical_op__zero_a$11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9626 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9627 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9631 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9630 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9628 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9629 1'0 - case - assign $2\logical_op__imm_data__data$4$next[63:0]$9626 $1\logical_op__imm_data__data$4$next[63:0]$9610 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9627 $1\logical_op__imm_data__ok$5$next[0:0]$9611 - assign $2\logical_op__oe__oe$8$next[0:0]$9628 $1\logical_op__oe__oe$8$next[0:0]$9619 - assign $2\logical_op__oe__ok$9$next[0:0]$9629 $1\logical_op__oe__ok$9$next[0:0]$9620 - assign $2\logical_op__rc__ok$7$next[0:0]$9630 $1\logical_op__rc__ok$7$next[0:0]$9622 - assign $2\logical_op__rc__rc$6$next[0:0]$9631 $1\logical_op__rc__rc$6$next[0:0]$9623 - end - sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9590 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$9591 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9592 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9593 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9594 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9595 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9596 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9597 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9598 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9599 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9600 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9601 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9602 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9603 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9604 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9605 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9606 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9607 - end - connect \$74 $and$libresoc.v:160909$9509_Y - connect \cr_a$68 4'0000 - connect \cr_a_ok$69 1'0 - connect \xer_so_ok$72 1'0 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } - connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } - connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } - connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } - connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } - connect \muxid$76 \output_muxid$41 - connect \p_valid_i_p_ready_o \$74 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$73 \p_valid_i - connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } - connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } - connect { \cr_a_ok$67 \output_cr_a } 5'00000 - connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } - connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } - connect \output_muxid \output_stage_muxid$21 - connect \output_stage_remainder \remainder - connect \output_stage_quotient_root \quotient_root - connect \output_stage_div_by_zero \div_by_zero - connect \output_stage_dive_abs_ov64 \dive_abs_ov64 - connect \output_stage_dive_abs_ov32 \dive_abs_ov32 - connect \output_stage_dividend_neg \dividend_neg - connect \output_stage_divisor_neg \divisor_neg - connect \output_stage_xer_so \xer_so - connect \rb$66 \rb - connect \ra$65 \ra - connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \output_stage_muxid \muxid -end -attribute \src "libresoc.v:161265.1-162243.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" -attribute \generator "nMigen" -module \pipe_middle_0 - attribute \src "libresoc.v:162168.3-162182.6" - wire $0\div_by_zero$54$next[0:0]$9860 - attribute \src "libresoc.v:161842.3-161843.47" - wire $0\div_by_zero$54[0:0]$9695 - attribute \src "libresoc.v:161288.7-161288.30" - wire $0\div_by_zero$54[0:0]$9877 - attribute \src "libresoc.v:161964.3-161975.6" - wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:161952.3-161963.6" - wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:161940.3-161951.6" - wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:162138.3-162152.6" - wire $0\dive_abs_ov32$52$next[0:0]$9852 - attribute \src "libresoc.v:161846.3-161847.51" - wire $0\dive_abs_ov32$52[0:0]$9699 - attribute \src "libresoc.v:161312.7-161312.32" - wire $0\dive_abs_ov32$52[0:0]$9879 - attribute \src "libresoc.v:162153.3-162167.6" - wire $0\dive_abs_ov64$53$next[0:0]$9856 - attribute \src "libresoc.v:161844.3-161845.51" - wire $0\dive_abs_ov64$53[0:0]$9697 - attribute \src "libresoc.v:161320.7-161320.32" - wire $0\dive_abs_ov64$53[0:0]$9881 - attribute \src "libresoc.v:162183.3-162197.6" - wire width 128 $0\dividend$68$next[127:0]$9864 - attribute \src "libresoc.v:161840.3-161841.41" - wire width 128 $0\dividend$68[127:0]$9693 - attribute \src "libresoc.v:161326.15-161326.68" - wire width 128 $0\dividend$68[127:0]$9883 - attribute \src "libresoc.v:162123.3-162137.6" - wire $0\dividend_neg$51$next[0:0]$9848 - attribute \src "libresoc.v:161848.3-161849.49" - wire $0\dividend_neg$51[0:0]$9701 - attribute \src "libresoc.v:161334.7-161334.31" - wire $0\dividend_neg$51[0:0]$9885 - attribute \src "libresoc.v:162108.3-162122.6" - wire $0\divisor_neg$50$next[0:0]$9844 - attribute \src "libresoc.v:161850.3-161851.47" - wire $0\divisor_neg$50[0:0]$9703 - attribute \src "libresoc.v:161342.7-161342.30" - wire $0\divisor_neg$50[0:0]$9887 - attribute \src "libresoc.v:162198.3-162212.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$9868 - attribute \src "libresoc.v:161838.3-161839.57" - wire width 64 $0\divisor_radicand$65[63:0]$9691 - attribute \src "libresoc.v:161348.14-161348.58" - wire width 64 $0\divisor_radicand$65[63:0]$9889 - attribute \src "libresoc.v:161976.3-162003.6" - wire $0\empty$next[0:0]$9761 - attribute \src "libresoc.v:161896.3-161897.27" - wire $0\empty[0:0] - attribute \src "libresoc.v:161266.7-161266.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:162019.3-162062.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$9771 - attribute \src "libresoc.v:161890.3-161891.65" - wire width 4 $0\logical_op__data_len$45[3:0]$9743 - attribute \src "libresoc.v:161360.13-161360.45" - wire width 4 $0\logical_op__data_len$45[3:0]$9892 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 12 $0\logical_op__fn_unit$30$next[11:0]$9772 - attribute \src "libresoc.v:161860.3-161861.63" - wire width 12 $0\logical_op__fn_unit$30[11:0]$9713 - attribute \src "libresoc.v:161407.14-161407.48" - wire width 12 $0\logical_op__fn_unit$30[11:0]$9894 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$9773 - attribute \src "libresoc.v:161862.3-161863.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9715 - attribute \src "libresoc.v:161413.14-161413.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$9896 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$9774 - attribute \src "libresoc.v:161864.3-161865.73" - wire $0\logical_op__imm_data__ok$32[0:0]$9717 - attribute \src "libresoc.v:161421.7-161421.43" - wire $0\logical_op__imm_data__ok$32[0:0]$9898 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$9775 - attribute \src "libresoc.v:161878.3-161879.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$9731 - attribute \src "libresoc.v:161443.13-161443.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$9900 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$9776 - attribute \src "libresoc.v:161892.3-161893.57" - wire width 32 $0\logical_op__insn$46[31:0]$9745 - attribute \src "libresoc.v:161451.14-161451.43" - wire width 32 $0\logical_op__insn$46[31:0]$9902 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$9777 - attribute \src "libresoc.v:161858.3-161859.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$9711 - attribute \src "libresoc.v:161681.13-161681.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$9904 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__invert_in$37$next[0:0]$9778 - attribute \src "libresoc.v:161874.3-161875.67" - wire $0\logical_op__invert_in$37[0:0]$9727 - attribute \src "libresoc.v:161689.7-161689.40" - wire $0\logical_op__invert_in$37[0:0]$9906 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__invert_out$40$next[0:0]$9779 - attribute \src "libresoc.v:161880.3-161881.69" - wire $0\logical_op__invert_out$40[0:0]$9733 - attribute \src "libresoc.v:161697.7-161697.41" - wire $0\logical_op__invert_out$40[0:0]$9908 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__is_32bit$43$next[0:0]$9780 - attribute \src "libresoc.v:161886.3-161887.65" - wire $0\logical_op__is_32bit$43[0:0]$9739 - attribute \src "libresoc.v:161705.7-161705.39" - wire $0\logical_op__is_32bit$43[0:0]$9910 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__is_signed$44$next[0:0]$9781 - attribute \src "libresoc.v:161888.3-161889.67" - wire $0\logical_op__is_signed$44[0:0]$9741 - attribute \src "libresoc.v:161713.7-161713.40" - wire $0\logical_op__is_signed$44[0:0]$9912 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__oe__oe$35$next[0:0]$9782 - attribute \src "libresoc.v:161870.3-161871.61" - wire $0\logical_op__oe__oe$35[0:0]$9723 - attribute \src "libresoc.v:161719.7-161719.37" - wire $0\logical_op__oe__oe$35[0:0]$9914 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__oe__ok$36$next[0:0]$9783 - attribute \src "libresoc.v:161872.3-161873.61" - wire $0\logical_op__oe__ok$36[0:0]$9725 - attribute \src "libresoc.v:161727.7-161727.37" - wire $0\logical_op__oe__ok$36[0:0]$9916 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__output_carry$42$next[0:0]$9784 - attribute \src "libresoc.v:161884.3-161885.73" - wire $0\logical_op__output_carry$42[0:0]$9737 - attribute \src "libresoc.v:161737.7-161737.43" - wire $0\logical_op__output_carry$42[0:0]$9918 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__rc__ok$34$next[0:0]$9785 - attribute \src "libresoc.v:161868.3-161869.61" - wire $0\logical_op__rc__ok$34[0:0]$9721 - attribute \src "libresoc.v:161743.7-161743.37" - wire $0\logical_op__rc__ok$34[0:0]$9920 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__rc__rc$33$next[0:0]$9786 - attribute \src "libresoc.v:161866.3-161867.61" - wire $0\logical_op__rc__rc$33[0:0]$9719 - attribute \src "libresoc.v:161751.7-161751.37" - wire $0\logical_op__rc__rc$33[0:0]$9922 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__write_cr0$41$next[0:0]$9787 - attribute \src "libresoc.v:161882.3-161883.67" - wire $0\logical_op__write_cr0$41[0:0]$9735 - attribute \src "libresoc.v:161761.7-161761.40" - wire $0\logical_op__write_cr0$41[0:0]$9924 - attribute \src "libresoc.v:162019.3-162062.6" - wire $0\logical_op__zero_a$38$next[0:0]$9788 - attribute \src "libresoc.v:161876.3-161877.61" - wire $0\logical_op__zero_a$38[0:0]$9729 - attribute \src "libresoc.v:161769.7-161769.37" - wire $0\logical_op__zero_a$38[0:0]$9926 - attribute \src "libresoc.v:162004.3-162018.6" - wire width 2 $0\muxid$28$next[1:0]$9767 - attribute \src "libresoc.v:161894.3-161895.35" - wire width 2 $0\muxid$28[1:0]$9747 - attribute \src "libresoc.v:161777.13-161777.30" - wire width 2 $0\muxid$28[1:0]$9928 - attribute \src "libresoc.v:162213.3-162227.6" - wire width 2 $0\operation$69$next[1:0]$9872 - attribute \src "libresoc.v:161836.3-161837.43" - wire width 2 $0\operation$69[1:0]$9689 - attribute \src "libresoc.v:161787.13-161787.34" - wire width 2 $0\operation$69[1:0]$9930 - attribute \src "libresoc.v:162063.3-162077.6" - wire width 64 $0\ra$47$next[63:0]$9832 - attribute \src "libresoc.v:161856.3-161857.29" - wire width 64 $0\ra$47[63:0]$9709 - attribute \src "libresoc.v:161801.14-161801.44" - wire width 64 $0\ra$47[63:0]$9932 - attribute \src "libresoc.v:162078.3-162092.6" - wire width 64 $0\rb$48$next[63:0]$9836 - attribute \src "libresoc.v:161854.3-161855.29" - wire width 64 $0\rb$48[63:0]$9707 - attribute \src "libresoc.v:161809.14-161809.44" - wire width 64 $0\rb$48[63:0]$9934 - attribute \src "libresoc.v:161931.3-161939.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$9755 - attribute \src "libresoc.v:161898.3-161899.75" - wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:161922.3-161930.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$9752 - attribute \src "libresoc.v:161900.3-161901.65" - wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:162093.3-162107.6" - wire $0\xer_so$49$next[0:0]$9840 - attribute \src "libresoc.v:161852.3-161853.37" - wire $0\xer_so$49[0:0]$9705 - attribute \src "libresoc.v:161827.7-161827.25" - wire $0\xer_so$49[0:0]$9938 - attribute \src "libresoc.v:162168.3-162182.6" - wire $1\div_by_zero$54$next[0:0]$9861 - attribute \src "libresoc.v:161964.3-161975.6" - wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:161952.3-161963.6" - wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:161940.3-161951.6" - wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:162138.3-162152.6" - wire $1\dive_abs_ov32$52$next[0:0]$9853 - attribute \src "libresoc.v:162153.3-162167.6" - wire $1\dive_abs_ov64$53$next[0:0]$9857 - attribute \src "libresoc.v:162183.3-162197.6" - wire width 128 $1\dividend$68$next[127:0]$9865 - attribute \src "libresoc.v:162123.3-162137.6" - wire $1\dividend_neg$51$next[0:0]$9849 - attribute \src "libresoc.v:162108.3-162122.6" - wire $1\divisor_neg$50$next[0:0]$9845 - attribute \src "libresoc.v:162198.3-162212.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$9869 - attribute \src "libresoc.v:161976.3-162003.6" - wire $1\empty$next[0:0]$9762 - attribute \src "libresoc.v:161352.7-161352.19" - wire $1\empty[0:0] - attribute \src "libresoc.v:162019.3-162062.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$9789 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 12 $1\logical_op__fn_unit$30$next[11:0]$9790 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$9791 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$9792 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$9793 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$9794 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$9795 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__invert_in$37$next[0:0]$9796 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__invert_out$40$next[0:0]$9797 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__is_32bit$43$next[0:0]$9798 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__is_signed$44$next[0:0]$9799 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__oe__oe$35$next[0:0]$9800 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__oe__ok$36$next[0:0]$9801 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__output_carry$42$next[0:0]$9802 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__rc__ok$34$next[0:0]$9803 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__rc__rc$33$next[0:0]$9804 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__write_cr0$41$next[0:0]$9805 - attribute \src "libresoc.v:162019.3-162062.6" - wire $1\logical_op__zero_a$38$next[0:0]$9806 - attribute \src "libresoc.v:162004.3-162018.6" - wire width 2 $1\muxid$28$next[1:0]$9768 - attribute \src "libresoc.v:162213.3-162227.6" - wire width 2 $1\operation$69$next[1:0]$9873 - attribute \src "libresoc.v:162063.3-162077.6" - wire width 64 $1\ra$47$next[63:0]$9833 - attribute \src "libresoc.v:162078.3-162092.6" - wire width 64 $1\rb$48$next[63:0]$9837 - attribute \src "libresoc.v:161931.3-161939.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$9756 - attribute \src "libresoc.v:161815.15-161815.84" - wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:161922.3-161930.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$9753 - attribute \src "libresoc.v:161819.13-161819.45" - wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:162093.3-162107.6" - wire $1\xer_so$49$next[0:0]$9841 - attribute \src "libresoc.v:162168.3-162182.6" - wire $2\div_by_zero$54$next[0:0]$9862 - attribute \src "libresoc.v:162138.3-162152.6" - wire $2\dive_abs_ov32$52$next[0:0]$9854 - attribute \src "libresoc.v:162153.3-162167.6" - wire $2\dive_abs_ov64$53$next[0:0]$9858 - attribute \src "libresoc.v:162183.3-162197.6" - wire width 128 $2\dividend$68$next[127:0]$9866 - attribute \src "libresoc.v:162123.3-162137.6" - wire $2\dividend_neg$51$next[0:0]$9850 - attribute \src "libresoc.v:162108.3-162122.6" - wire $2\divisor_neg$50$next[0:0]$9846 - attribute \src "libresoc.v:162198.3-162212.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$9870 - attribute \src "libresoc.v:161976.3-162003.6" - wire $2\empty$next[0:0]$9763 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$9807 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 12 $2\logical_op__fn_unit$30$next[11:0]$9808 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$9809 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$9810 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$9811 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$9812 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$9813 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__invert_in$37$next[0:0]$9814 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__invert_out$40$next[0:0]$9815 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__is_32bit$43$next[0:0]$9816 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__is_signed$44$next[0:0]$9817 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__oe__oe$35$next[0:0]$9818 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__oe__ok$36$next[0:0]$9819 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__output_carry$42$next[0:0]$9820 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__rc__ok$34$next[0:0]$9821 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__rc__rc$33$next[0:0]$9822 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__write_cr0$41$next[0:0]$9823 - attribute \src "libresoc.v:162019.3-162062.6" - wire $2\logical_op__zero_a$38$next[0:0]$9824 - attribute \src "libresoc.v:162004.3-162018.6" - wire width 2 $2\muxid$28$next[1:0]$9769 - attribute \src "libresoc.v:162213.3-162227.6" - wire width 2 $2\operation$69$next[1:0]$9874 - attribute \src "libresoc.v:162063.3-162077.6" - wire width 64 $2\ra$47$next[63:0]$9834 - attribute \src "libresoc.v:162078.3-162092.6" - wire width 64 $2\rb$48$next[63:0]$9838 - attribute \src "libresoc.v:162093.3-162107.6" - wire $2\xer_so$49$next[0:0]$9842 - attribute \src "libresoc.v:161976.3-162003.6" - wire $3\empty$next[0:0]$9764 - attribute \src "libresoc.v:162019.3-162062.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$9825 - attribute \src "libresoc.v:162019.3-162062.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$9826 - attribute \src "libresoc.v:162019.3-162062.6" - wire $3\logical_op__oe__oe$35$next[0:0]$9827 - attribute \src "libresoc.v:162019.3-162062.6" - wire $3\logical_op__oe__ok$36$next[0:0]$9828 - attribute \src "libresoc.v:162019.3-162062.6" - wire $3\logical_op__rc__ok$34$next[0:0]$9829 - attribute \src "libresoc.v:162019.3-162062.6" - wire $3\logical_op__rc__rc$33$next[0:0]$9830 - attribute \src "libresoc.v:161976.3-162003.6" - wire $4\empty$next[0:0]$9765 - attribute \src "libresoc.v:161834.18-161834.98" - wire $and$libresoc.v:161834$9686_Y - attribute \src "libresoc.v:161835.18-161835.107" - wire $and$libresoc.v:161835$9687_Y - attribute \src "libresoc.v:161831.18-161831.92" - wire width 192 $extend$libresoc.v:161831$9682_Y - attribute \src "libresoc.v:161833.18-161833.119" - wire $ge$libresoc.v:161833$9685_Y - attribute \src "libresoc.v:161832.18-161832.93" - wire $not$libresoc.v:161832$9684_Y - attribute \src "libresoc.v:161831.18-161831.92" - wire width 192 $pos$libresoc.v:161831$9683_Y - attribute \src "libresoc.v:161830.18-161830.138" - wire width 191 $sshl$libresoc.v:161830$9681_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - wire width 192 \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - wire width 191 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire input 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 62 \div_by_zero$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$54$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" - wire width 128 \div_state_init_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_init_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_init_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" - wire width 64 \div_state_next_divisor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_next_i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_next_i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \div_state_next_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \div_state_next_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire input 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 60 \dive_abs_ov32$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$52$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire input 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 61 \dive_abs_ov64$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$53$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 input 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire input 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 59 \dividend_neg$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$51$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire input 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 58 \divisor_neg$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$50$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 input 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" - wire \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" - wire \empty$next - attribute \src "libresoc.v:161266.7-161266.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 53 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 38 \logical_op__fn_unit$3 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$30$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 39 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 40 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 47 \logical_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 54 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 37 \logical_op__insn_type$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$37$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$40$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$43$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$44$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$35$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$36$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 44 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 50 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$42$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$34$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 42 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$33$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 41 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 49 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$41$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 46 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$38$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 36 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$28$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 35 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 34 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 input 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 output 63 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 55 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 56 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 output 64 \remainder - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \saved_state_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" - wire width 128 \saved_state_dividend_quotient$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \saved_state_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" - wire width 7 \saved_state_q_bits_known$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 57 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$49$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:161834$9686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$59 - connect \B \$61 - connect \Y $and$libresoc.v:161834$9686_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:161835$9687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $and$libresoc.v:161835$9687_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:161831$9682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 191 - parameter \Y_WIDTH 192 - connect \A \$56 - connect \Y $extend$libresoc.v:161831$9682_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:161833$9685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \saved_state_q_bits_known - connect \B 6'111111 - connect \Y $ge$libresoc.v:161833$9685_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:161832$9684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \empty - connect \Y $not$libresoc.v:161832$9684_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:161831$9683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 192 - parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:161831$9682_Y - connect \Y $pos$libresoc.v:161831$9683_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:161830$9681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \div_state_next_o_dividend_quotient [127:64] - connect \B 7'1000000 - connect \Y $sshl$libresoc.v:161830$9681_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:161902.18-161906.4" - cell \div_state_init \div_state_init - connect \dividend \div_state_init_dividend - connect \o_dividend_quotient \div_state_init_o_dividend_quotient - connect \o_q_bits_known \div_state_init_o_q_bits_known - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:161907.18-161913.4" - cell \div_state_next \div_state_next - connect \divisor \div_state_next_divisor - connect \i_dividend_quotient \div_state_next_i_dividend_quotient - connect \i_q_bits_known \div_state_next_i_q_bits_known - connect \o_dividend_quotient \div_state_next_o_dividend_quotient - connect \o_q_bits_known \div_state_next_o_q_bits_known - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:161914.10-161917.4" - cell \n$80 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:161918.10-161921.4" - cell \p$79 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \src "libresoc.v:161266.7-161266.20" - process $proc$libresoc.v:161266$9875 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync 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always - sync init - update \dividend$68 $0\dividend$68[127:0]$9883 - end - attribute \src "libresoc.v:161334.7-161334.31" - process $proc$libresoc.v:161334$9884 - assign { } { } - assign $0\dividend_neg$51[0:0]$9885 1'0 - sync always - sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9885 - end - attribute \src "libresoc.v:161342.7-161342.30" - process $proc$libresoc.v:161342$9886 - assign { } { } - assign $0\divisor_neg$50[0:0]$9887 1'0 - sync always - sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9887 - end - attribute \src "libresoc.v:161348.14-161348.58" - process $proc$libresoc.v:161348$9888 - assign { } { } - assign $0\divisor_radicand$65[63:0]$9889 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9889 - end - attribute \src "libresoc.v:161352.7-161352.19" - process $proc$libresoc.v:161352$9890 - assign { } { } - assign $1\empty[0:0] 1'1 - sync always - sync init - update \empty $1\empty[0:0] - end - attribute \src "libresoc.v:161360.13-161360.45" - process $proc$libresoc.v:161360$9891 - assign { } { } - assign $0\logical_op__data_len$45[3:0]$9892 4'0000 - sync always - sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9892 - end - attribute \src "libresoc.v:161407.14-161407.48" - process $proc$libresoc.v:161407$9893 - assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$9894 12'000000000000 - sync always - sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9894 - end - attribute \src "libresoc.v:161413.14-161413.68" - process $proc$libresoc.v:161413$9895 - assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9896 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9896 - end - attribute \src "libresoc.v:161421.7-161421.43" - process $proc$libresoc.v:161421$9897 - assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9898 1'0 - sync always - sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9898 - end - attribute \src "libresoc.v:161443.13-161443.48" - process $proc$libresoc.v:161443$9899 - assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9900 2'00 - sync always - sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9900 - end - attribute \src "libresoc.v:161451.14-161451.43" - process $proc$libresoc.v:161451$9901 - assign { } { } - assign $0\logical_op__insn$46[31:0]$9902 0 - sync always - sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9902 - end - attribute \src "libresoc.v:161681.13-161681.47" - process $proc$libresoc.v:161681$9903 - assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9904 7'0000000 - sync always - sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9904 - end - attribute \src "libresoc.v:161689.7-161689.40" - process $proc$libresoc.v:161689$9905 - assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9906 1'0 - sync always - sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9906 - end - attribute \src "libresoc.v:161697.7-161697.41" - process $proc$libresoc.v:161697$9907 - assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9908 1'0 - sync always - sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9908 - end - attribute \src "libresoc.v:161705.7-161705.39" - process $proc$libresoc.v:161705$9909 - assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9910 1'0 - sync always - sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9910 - end - attribute \src "libresoc.v:161713.7-161713.40" - process $proc$libresoc.v:161713$9911 - assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9912 1'0 - sync always - sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9912 - end - attribute \src "libresoc.v:161719.7-161719.37" - process $proc$libresoc.v:161719$9913 - assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9914 1'0 - sync always - sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9914 - end - attribute \src "libresoc.v:161727.7-161727.37" - process $proc$libresoc.v:161727$9915 - assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9916 1'0 - sync always - sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9916 - end - attribute \src "libresoc.v:161737.7-161737.43" - process $proc$libresoc.v:161737$9917 - assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9918 1'0 - sync always - sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9918 - end - attribute \src "libresoc.v:161743.7-161743.37" - process $proc$libresoc.v:161743$9919 - assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9920 1'0 - sync always - sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9920 - end - attribute \src "libresoc.v:161751.7-161751.37" - process $proc$libresoc.v:161751$9921 - assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9922 1'0 - sync always - sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9922 - end - attribute \src "libresoc.v:161761.7-161761.40" - process $proc$libresoc.v:161761$9923 - assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9924 1'0 - sync always - sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9924 - end - attribute \src "libresoc.v:161769.7-161769.37" - process $proc$libresoc.v:161769$9925 - assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9926 1'0 - sync always - sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9926 - end - attribute \src "libresoc.v:161777.13-161777.30" - process $proc$libresoc.v:161777$9927 - assign { } { } - assign $0\muxid$28[1:0]$9928 2'00 - sync always - sync init - update \muxid$28 $0\muxid$28[1:0]$9928 - end - attribute \src "libresoc.v:161787.13-161787.34" - process $proc$libresoc.v:161787$9929 - assign { } { } - assign $0\operation$69[1:0]$9930 2'00 - sync always - sync init - update \operation$69 $0\operation$69[1:0]$9930 - end - attribute \src "libresoc.v:161801.14-161801.44" - process $proc$libresoc.v:161801$9931 - assign { } { } - assign $0\ra$47[63:0]$9932 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra$47 $0\ra$47[63:0]$9932 - end - attribute \src "libresoc.v:161809.14-161809.44" - process $proc$libresoc.v:161809$9933 - assign { } { } - assign $0\rb$48[63:0]$9934 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb$48 $0\rb$48[63:0]$9934 - end - attribute \src "libresoc.v:161815.15-161815.84" - process $proc$libresoc.v:161815$9935 - assign { } { } - assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] - end - attribute \src "libresoc.v:161819.13-161819.45" - process $proc$libresoc.v:161819$9936 - assign { } { } - assign $1\saved_state_q_bits_known[6:0] 7'0000000 - sync always - sync init - update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] - end - attribute \src "libresoc.v:161827.7-161827.25" - process $proc$libresoc.v:161827$9937 - assign { } { } - assign $0\xer_so$49[0:0]$9938 1'0 - sync always - sync init - update \xer_so$49 $0\xer_so$49[0:0]$9938 - end - attribute \src "libresoc.v:161836.3-161837.43" - process $proc$libresoc.v:161836$9688 - assign { } { } - assign $0\operation$69[1:0]$9689 \operation$69$next - sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$9689 - end - attribute \src "libresoc.v:161838.3-161839.57" - process $proc$libresoc.v:161838$9690 - assign { } { } - assign $0\divisor_radicand$65[63:0]$9691 \divisor_radicand$65$next - sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9691 - end - attribute \src "libresoc.v:161840.3-161841.41" - process $proc$libresoc.v:161840$9692 - assign { } { } - assign $0\dividend$68[127:0]$9693 \dividend$68$next - sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$9693 - end - attribute \src "libresoc.v:161842.3-161843.47" - process $proc$libresoc.v:161842$9694 - assign { } { } - assign $0\div_by_zero$54[0:0]$9695 \div_by_zero$54$next - sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$9695 - end - attribute \src "libresoc.v:161844.3-161845.51" - process $proc$libresoc.v:161844$9696 - assign { } { } - assign $0\dive_abs_ov64$53[0:0]$9697 \dive_abs_ov64$53$next - sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9697 - end - attribute \src "libresoc.v:161846.3-161847.51" - process $proc$libresoc.v:161846$9698 - assign { } { } - assign $0\dive_abs_ov32$52[0:0]$9699 \dive_abs_ov32$52$next - sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9699 - end - attribute \src "libresoc.v:161848.3-161849.49" - process $proc$libresoc.v:161848$9700 - assign { } { } - assign $0\dividend_neg$51[0:0]$9701 \dividend_neg$51$next - sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$9701 - end - attribute \src "libresoc.v:161850.3-161851.47" - process $proc$libresoc.v:161850$9702 - assign { } { } - assign $0\divisor_neg$50[0:0]$9703 \divisor_neg$50$next - sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$9703 - end - attribute \src "libresoc.v:161852.3-161853.37" - process $proc$libresoc.v:161852$9704 - assign { } { } - assign $0\xer_so$49[0:0]$9705 \xer_so$49$next - sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$9705 - end - attribute \src "libresoc.v:161854.3-161855.29" - process $proc$libresoc.v:161854$9706 - assign { } { } - assign $0\rb$48[63:0]$9707 \rb$48$next - sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$9707 - end - attribute \src "libresoc.v:161856.3-161857.29" - process $proc$libresoc.v:161856$9708 - assign { } { } - assign $0\ra$47[63:0]$9709 \ra$47$next - sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$9709 - end - attribute \src "libresoc.v:161858.3-161859.67" - process $proc$libresoc.v:161858$9710 - assign { } { } - assign $0\logical_op__insn_type$29[6:0]$9711 \logical_op__insn_type$29$next - sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9711 - end - attribute \src "libresoc.v:161860.3-161861.63" - process $proc$libresoc.v:161860$9712 - assign { } { } - assign $0\logical_op__fn_unit$30[11:0]$9713 \logical_op__fn_unit$30$next - sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9713 - end - attribute \src "libresoc.v:161862.3-161863.77" - process $proc$libresoc.v:161862$9714 - assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$9715 \logical_op__imm_data__data$31$next - sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9715 - end - attribute \src "libresoc.v:161864.3-161865.73" - process $proc$libresoc.v:161864$9716 - assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$9717 \logical_op__imm_data__ok$32$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9717 - end - attribute \src "libresoc.v:161866.3-161867.61" - process $proc$libresoc.v:161866$9718 - assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$9719 \logical_op__rc__rc$33$next - sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9719 - end - attribute \src "libresoc.v:161868.3-161869.61" - process $proc$libresoc.v:161868$9720 - assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$9721 \logical_op__rc__ok$34$next - sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9721 - end - attribute \src "libresoc.v:161870.3-161871.61" - process $proc$libresoc.v:161870$9722 - assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$9723 \logical_op__oe__oe$35$next - sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9723 - end - attribute \src "libresoc.v:161872.3-161873.61" - process $proc$libresoc.v:161872$9724 - assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$9725 \logical_op__oe__ok$36$next - sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9725 - end - attribute \src "libresoc.v:161874.3-161875.67" - process $proc$libresoc.v:161874$9726 - assign { } { } - assign $0\logical_op__invert_in$37[0:0]$9727 \logical_op__invert_in$37$next - sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9727 - end - attribute \src "libresoc.v:161876.3-161877.61" - process $proc$libresoc.v:161876$9728 - assign { } { } - assign $0\logical_op__zero_a$38[0:0]$9729 \logical_op__zero_a$38$next - sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9729 - end - attribute \src "libresoc.v:161878.3-161879.71" - process $proc$libresoc.v:161878$9730 - assign { } { } - assign $0\logical_op__input_carry$39[1:0]$9731 \logical_op__input_carry$39$next - sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9731 - end - attribute \src "libresoc.v:161880.3-161881.69" - process $proc$libresoc.v:161880$9732 - assign { } { } - assign $0\logical_op__invert_out$40[0:0]$9733 \logical_op__invert_out$40$next - sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9733 - end - attribute \src "libresoc.v:161882.3-161883.67" - process $proc$libresoc.v:161882$9734 - assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$9735 \logical_op__write_cr0$41$next - sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9735 - end - attribute \src "libresoc.v:161884.3-161885.73" - process $proc$libresoc.v:161884$9736 - assign { } { } - assign $0\logical_op__output_carry$42[0:0]$9737 \logical_op__output_carry$42$next - sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9737 - end - attribute \src "libresoc.v:161886.3-161887.65" - process $proc$libresoc.v:161886$9738 - assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$9739 \logical_op__is_32bit$43$next - sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9739 - end - attribute \src "libresoc.v:161888.3-161889.67" - process $proc$libresoc.v:161888$9740 - assign { } { } - assign $0\logical_op__is_signed$44[0:0]$9741 \logical_op__is_signed$44$next - sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9741 - end - attribute \src "libresoc.v:161890.3-161891.65" - process $proc$libresoc.v:161890$9742 - assign { } { } - assign $0\logical_op__data_len$45[3:0]$9743 \logical_op__data_len$45$next - sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9743 - end - attribute \src "libresoc.v:161892.3-161893.57" - process $proc$libresoc.v:161892$9744 - assign { } { } - assign $0\logical_op__insn$46[31:0]$9745 \logical_op__insn$46$next - sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9745 - end - attribute \src "libresoc.v:161894.3-161895.35" - process $proc$libresoc.v:161894$9746 - assign { } { } - assign $0\muxid$28[1:0]$9747 \muxid$28$next - sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$9747 - end - attribute \src "libresoc.v:161896.3-161897.27" - process $proc$libresoc.v:161896$9748 - assign { } { } - assign $0\empty[0:0] \empty$next - sync posedge \coresync_clk - update \empty $0\empty[0:0] - end - attribute \src "libresoc.v:161898.3-161899.75" - process $proc$libresoc.v:161898$9749 - assign { } { } - assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next - sync posedge \coresync_clk - update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] - end - attribute \src "libresoc.v:161900.3-161901.65" - process $proc$libresoc.v:161900$9750 - assign { } { } - assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next - sync posedge \coresync_clk - update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] - end - attribute \src "libresoc.v:161922.3-161930.6" - process $proc$libresoc.v:161922$9751 - assign { } { } - assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$9752 $1\saved_state_q_bits_known$next[6:0]$9753 - attribute \src "libresoc.v:161923.5-161923.29" - switch \initial - attribute \src "libresoc.v:161923.9-161923.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$9753 7'0000000 - case - assign $1\saved_state_q_bits_known$next[6:0]$9753 \div_state_next_o_q_bits_known - end - sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$9752 - end - attribute \src "libresoc.v:161931.3-161939.6" - process $proc$libresoc.v:161931$9754 - assign { } { } - assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$9755 $1\saved_state_dividend_quotient$next[127:0]$9756 - attribute \src "libresoc.v:161932.5-161932.29" - switch \initial - attribute \src "libresoc.v:161932.9-161932.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$9756 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\saved_state_dividend_quotient$next[127:0]$9756 \div_state_next_o_dividend_quotient - end - sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$9755 - end - attribute \src "libresoc.v:161940.3-161951.6" - process $proc$libresoc.v:161940$9757 - assign { } { } - assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:161941.5-161941.29" - switch \initial - attribute \src "libresoc.v:161941.9-161941.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known - attribute \src "libresoc.v:0.0-0.0" - case assign { } { } - assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known - end - sync always - update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] - end - attribute \src "libresoc.v:161952.3-161963.6" - process $proc$libresoc.v:161952$9758 - assign { } { } - assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:161953.5-161953.29" - switch \initial - attribute \src "libresoc.v:161953.9-161953.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient - attribute \src "libresoc.v:0.0-0.0" - case assign { } { } - assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient - end - sync always - update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] - end - attribute \src "libresoc.v:161964.3-161975.6" - process $proc$libresoc.v:161964$9759 - assign { } { } - assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:161965.5-161965.29" - switch \initial - attribute \src "libresoc.v:161965.9-161965.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand - attribute \src "libresoc.v:0.0-0.0" - case assign { } { } - assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 - end - sync always - update \div_state_next_divisor $0\div_state_next_divisor[63:0] - end - attribute \src "libresoc.v:161976.3-162003.6" - process $proc$libresoc.v:161976$9760 - assign { } { } - assign { } { } - assign { } { } - assign $0\empty$next[0:0]$9761 $4\empty$next[0:0]$9765 - attribute \src "libresoc.v:161977.5-161977.29" - switch \initial - attribute \src "libresoc.v:161977.9-161977.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\empty$next[0:0]$9762 $2\empty$next[0:0]$9763 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\empty$next[0:0]$9763 1'0 - case - assign $2\empty$next[0:0]$9763 \empty - end + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'10000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\empty$next[0:0]$9762 $3\empty$next[0:0]$9764 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch \$66 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\empty$next[0:0]$9764 1'1 - case - assign $3\empty$next[0:0]$9764 \empty - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $4\empty$next[0:0]$9765 1'1 - case - assign $4\empty$next[0:0]$9765 $1\empty$next[0:0]$9762 - end - sync always - update \empty$next $0\empty$next[0:0]$9761 - end - attribute \src "libresoc.v:162004.3-162018.6" - process $proc$libresoc.v:162004$9766 - assign { } { } - assign { } { } - assign $0\muxid$28$next[1:0]$9767 $1\muxid$28$next[1:0]$9768 - attribute \src "libresoc.v:162005.5-162005.29" - switch \initial - attribute \src "libresoc.v:162005.9-162005.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\muxid$28$next[1:0]$9768 $2\muxid$28$next[1:0]$9769 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\muxid$28$next[1:0]$9769 \muxid - case - assign $2\muxid$28$next[1:0]$9769 \muxid$28 - end - case - assign $1\muxid$28$next[1:0]$9768 \muxid$28 - end - sync always - update \muxid$28$next $0\muxid$28$next[1:0]$9767 - end - attribute \src "libresoc.v:162019.3-162062.6" - process $proc$libresoc.v:162019$9770 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$9771 $1\logical_op__data_len$45$next[3:0]$9789 - assign $0\logical_op__fn_unit$30$next[11:0]$9772 $1\logical_op__fn_unit$30$next[11:0]$9790 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$9775 $1\logical_op__input_carry$39$next[1:0]$9793 - assign $0\logical_op__insn$46$next[31:0]$9776 $1\logical_op__insn$46$next[31:0]$9794 - assign $0\logical_op__insn_type$29$next[6:0]$9777 $1\logical_op__insn_type$29$next[6:0]$9795 - assign $0\logical_op__invert_in$37$next[0:0]$9778 $1\logical_op__invert_in$37$next[0:0]$9796 - assign $0\logical_op__invert_out$40$next[0:0]$9779 $1\logical_op__invert_out$40$next[0:0]$9797 - assign $0\logical_op__is_32bit$43$next[0:0]$9780 $1\logical_op__is_32bit$43$next[0:0]$9798 - assign $0\logical_op__is_signed$44$next[0:0]$9781 $1\logical_op__is_signed$44$next[0:0]$9799 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$9784 $1\logical_op__output_carry$42$next[0:0]$9802 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$9787 $1\logical_op__write_cr0$41$next[0:0]$9805 - assign $0\logical_op__zero_a$38$next[0:0]$9788 $1\logical_op__zero_a$38$next[0:0]$9806 - assign $0\logical_op__imm_data__data$31$next[63:0]$9773 $3\logical_op__imm_data__data$31$next[63:0]$9825 - assign $0\logical_op__imm_data__ok$32$next[0:0]$9774 $3\logical_op__imm_data__ok$32$next[0:0]$9826 - assign $0\logical_op__oe__oe$35$next[0:0]$9782 $3\logical_op__oe__oe$35$next[0:0]$9827 - assign $0\logical_op__oe__ok$36$next[0:0]$9783 $3\logical_op__oe__ok$36$next[0:0]$9828 - assign $0\logical_op__rc__ok$34$next[0:0]$9785 $3\logical_op__rc__ok$34$next[0:0]$9829 - assign $0\logical_op__rc__rc$33$next[0:0]$9786 $3\logical_op__rc__rc$33$next[0:0]$9830 - attribute \src "libresoc.v:162020.5-162020.29" - switch \initial - attribute \src "libresoc.v:162020.9-162020.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } @@ -333472,1134 +16854,397 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$9789 $2\logical_op__data_len$45$next[3:0]$9807 - assign $1\logical_op__fn_unit$30$next[11:0]$9790 $2\logical_op__fn_unit$30$next[11:0]$9808 - assign $1\logical_op__imm_data__data$31$next[63:0]$9791 $2\logical_op__imm_data__data$31$next[63:0]$9809 - assign $1\logical_op__imm_data__ok$32$next[0:0]$9792 $2\logical_op__imm_data__ok$32$next[0:0]$9810 - assign $1\logical_op__input_carry$39$next[1:0]$9793 $2\logical_op__input_carry$39$next[1:0]$9811 - assign $1\logical_op__insn$46$next[31:0]$9794 $2\logical_op__insn$46$next[31:0]$9812 - assign $1\logical_op__insn_type$29$next[6:0]$9795 $2\logical_op__insn_type$29$next[6:0]$9813 - assign $1\logical_op__invert_in$37$next[0:0]$9796 $2\logical_op__invert_in$37$next[0:0]$9814 - assign $1\logical_op__invert_out$40$next[0:0]$9797 $2\logical_op__invert_out$40$next[0:0]$9815 - assign $1\logical_op__is_32bit$43$next[0:0]$9798 $2\logical_op__is_32bit$43$next[0:0]$9816 - assign $1\logical_op__is_signed$44$next[0:0]$9799 $2\logical_op__is_signed$44$next[0:0]$9817 - assign $1\logical_op__oe__oe$35$next[0:0]$9800 $2\logical_op__oe__oe$35$next[0:0]$9818 - assign $1\logical_op__oe__ok$36$next[0:0]$9801 $2\logical_op__oe__ok$36$next[0:0]$9819 - assign $1\logical_op__output_carry$42$next[0:0]$9802 $2\logical_op__output_carry$42$next[0:0]$9820 - assign $1\logical_op__rc__ok$34$next[0:0]$9803 $2\logical_op__rc__ok$34$next[0:0]$9821 - assign $1\logical_op__rc__rc$33$next[0:0]$9804 $2\logical_op__rc__rc$33$next[0:0]$9822 - assign $1\logical_op__write_cr0$41$next[0:0]$9805 $2\logical_op__write_cr0$41$next[0:0]$9823 - assign $1\logical_op__zero_a$38$next[0:0]$9806 $2\logical_op__zero_a$38$next[0:0]$9824 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$9812 $2\logical_op__data_len$45$next[3:0]$9807 $2\logical_op__is_signed$44$next[0:0]$9817 $2\logical_op__is_32bit$43$next[0:0]$9816 $2\logical_op__output_carry$42$next[0:0]$9820 $2\logical_op__write_cr0$41$next[0:0]$9823 $2\logical_op__invert_out$40$next[0:0]$9815 $2\logical_op__input_carry$39$next[1:0]$9811 $2\logical_op__zero_a$38$next[0:0]$9824 $2\logical_op__invert_in$37$next[0:0]$9814 $2\logical_op__oe__ok$36$next[0:0]$9819 $2\logical_op__oe__oe$35$next[0:0]$9818 $2\logical_op__rc__ok$34$next[0:0]$9821 $2\logical_op__rc__rc$33$next[0:0]$9822 $2\logical_op__imm_data__ok$32$next[0:0]$9810 $2\logical_op__imm_data__data$31$next[63:0]$9809 $2\logical_op__fn_unit$30$next[11:0]$9808 $2\logical_op__insn_type$29$next[6:0]$9813 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - case - assign $2\logical_op__data_len$45$next[3:0]$9807 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[11:0]$9808 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$9809 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$9810 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$9811 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$9812 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$9813 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$9814 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$9815 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$9816 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$9817 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$9818 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$9819 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$9820 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$9821 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$9822 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$9823 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$9824 \logical_op__zero_a$38 - end - case - assign $1\logical_op__data_len$45$next[3:0]$9789 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[11:0]$9790 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$9791 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$9792 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$9793 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$9794 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$9795 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$9796 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$9797 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$9798 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$9799 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$9800 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$9801 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$9802 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$9803 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$9804 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$9805 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$9806 \logical_op__zero_a$38 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$9825 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9826 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$9830 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$9829 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$9827 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$9828 1'0 - case - assign $3\logical_op__imm_data__data$31$next[63:0]$9825 $1\logical_op__imm_data__data$31$next[63:0]$9791 - assign $3\logical_op__imm_data__ok$32$next[0:0]$9826 $1\logical_op__imm_data__ok$32$next[0:0]$9792 - assign $3\logical_op__oe__oe$35$next[0:0]$9827 $1\logical_op__oe__oe$35$next[0:0]$9800 - assign $3\logical_op__oe__ok$36$next[0:0]$9828 $1\logical_op__oe__ok$36$next[0:0]$9801 - assign $3\logical_op__rc__ok$34$next[0:0]$9829 $1\logical_op__rc__ok$34$next[0:0]$9803 - assign $3\logical_op__rc__rc$33$next[0:0]$9830 $1\logical_op__rc__rc$33$next[0:0]$9804 - end - sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$9771 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$9772 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$9773 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$9774 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$9775 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$9776 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$9777 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$9778 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$9779 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$9780 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$9781 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$9782 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$9783 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$9784 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$9785 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$9786 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$9787 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$9788 - end - attribute \src "libresoc.v:162063.3-162077.6" - process $proc$libresoc.v:162063$9831 - assign { } { } - assign { } { } - assign $0\ra$47$next[63:0]$9832 $1\ra$47$next[63:0]$9833 - attribute \src "libresoc.v:162064.5-162064.29" - switch \initial - attribute \src "libresoc.v:162064.9-162064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\ra$47$next[63:0]$9833 $2\ra$47$next[63:0]$9834 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\ra$47$next[63:0]$9834 \ra - case - assign $2\ra$47$next[63:0]$9834 \ra$47 - end - case - assign $1\ra$47$next[63:0]$9833 \ra$47 - end - sync always - update \ra$47$next $0\ra$47$next[63:0]$9832 - end - attribute \src "libresoc.v:162078.3-162092.6" - process $proc$libresoc.v:162078$9835 - assign { } { } - assign { } { } - assign $0\rb$48$next[63:0]$9836 $1\rb$48$next[63:0]$9837 - attribute \src "libresoc.v:162079.5-162079.29" - switch \initial - attribute \src "libresoc.v:162079.9-162079.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\rb$48$next[63:0]$9837 $2\rb$48$next[63:0]$9838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\rb$48$next[63:0]$9838 \rb - case - assign $2\rb$48$next[63:0]$9838 \rb$48 - end - case - assign $1\rb$48$next[63:0]$9837 \rb$48 - end - sync always - update \rb$48$next $0\rb$48$next[63:0]$9836 - end - attribute \src "libresoc.v:162093.3-162107.6" - process $proc$libresoc.v:162093$9839 - assign { } { } - assign { } { } - assign $0\xer_so$49$next[0:0]$9840 $1\xer_so$49$next[0:0]$9841 - attribute \src "libresoc.v:162094.5-162094.29" - switch \initial - attribute \src "libresoc.v:162094.9-162094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$9841 $2\xer_so$49$next[0:0]$9842 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\xer_so$49$next[0:0]$9842 \xer_so - case - assign $2\xer_so$49$next[0:0]$9842 \xer_so$49 - end - case - assign $1\xer_so$49$next[0:0]$9841 \xer_so$49 - end - sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$9840 - end - attribute \src "libresoc.v:162108.3-162122.6" - process $proc$libresoc.v:162108$9843 - assign { } { } - assign { } { } - assign $0\divisor_neg$50$next[0:0]$9844 $1\divisor_neg$50$next[0:0]$9845 - attribute \src "libresoc.v:162109.5-162109.29" - switch \initial - attribute \src "libresoc.v:162109.9-162109.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$9845 $2\divisor_neg$50$next[0:0]$9846 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_neg$50$next[0:0]$9846 \divisor_neg - case - assign $2\divisor_neg$50$next[0:0]$9846 \divisor_neg$50 - end - case - assign $1\divisor_neg$50$next[0:0]$9845 \divisor_neg$50 - end - sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9844 - end - attribute \src "libresoc.v:162123.3-162137.6" - process $proc$libresoc.v:162123$9847 - assign { } { } - assign { } { } - assign $0\dividend_neg$51$next[0:0]$9848 $1\dividend_neg$51$next[0:0]$9849 - attribute \src "libresoc.v:162124.5-162124.29" - switch \initial - attribute \src "libresoc.v:162124.9-162124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$9849 $2\dividend_neg$51$next[0:0]$9850 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend_neg$51$next[0:0]$9850 \dividend_neg - case - assign $2\dividend_neg$51$next[0:0]$9850 \dividend_neg$51 - end - case - assign $1\dividend_neg$51$next[0:0]$9849 \dividend_neg$51 - end - sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9848 - end - attribute \src "libresoc.v:162138.3-162152.6" - process $proc$libresoc.v:162138$9851 - assign { } { } - assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$9852 $1\dive_abs_ov32$52$next[0:0]$9853 - attribute \src "libresoc.v:162139.5-162139.29" - switch \initial - attribute \src "libresoc.v:162139.9-162139.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$9853 $2\dive_abs_ov32$52$next[0:0]$9854 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$9854 \dive_abs_ov32 - case - assign $2\dive_abs_ov32$52$next[0:0]$9854 \dive_abs_ov32$52 - end - case - assign $1\dive_abs_ov32$52$next[0:0]$9853 \dive_abs_ov32$52 - end - sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9852 - end - attribute \src "libresoc.v:162153.3-162167.6" - process $proc$libresoc.v:162153$9855 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$9856 $1\dive_abs_ov64$53$next[0:0]$9857 - attribute \src "libresoc.v:162154.5-162154.29" - switch \initial - attribute \src "libresoc.v:162154.9-162154.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$9857 $2\dive_abs_ov64$53$next[0:0]$9858 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$9858 \dive_abs_ov64 - case - assign $2\dive_abs_ov64$53$next[0:0]$9858 \dive_abs_ov64$53 - end - case - assign $1\dive_abs_ov64$53$next[0:0]$9857 \dive_abs_ov64$53 - end - sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9856 - end - attribute \src "libresoc.v:162168.3-162182.6" - process $proc$libresoc.v:162168$9859 - assign { } { } - assign { } { } - assign $0\div_by_zero$54$next[0:0]$9860 $1\div_by_zero$54$next[0:0]$9861 - attribute \src "libresoc.v:162169.5-162169.29" - switch \initial - attribute \src "libresoc.v:162169.9-162169.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$9861 $2\div_by_zero$54$next[0:0]$9862 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\div_by_zero$54$next[0:0]$9862 \div_by_zero - case - assign $2\div_by_zero$54$next[0:0]$9862 \div_by_zero$54 - end - case - assign $1\div_by_zero$54$next[0:0]$9861 \div_by_zero$54 - end - sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9860 - end - attribute \src "libresoc.v:162183.3-162197.6" - process $proc$libresoc.v:162183$9863 - assign { } { } - assign { } { } - assign $0\dividend$68$next[127:0]$9864 $1\dividend$68$next[127:0]$9865 - attribute \src "libresoc.v:162184.5-162184.29" - switch \initial - attribute \src "libresoc.v:162184.9-162184.17" - case 1'1 - case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$325 $1\exc_$signal$8[0:0]$324 $1\exc_$signal$7[0:0]$323 $1\exc_$signal$6[0:0]$322 $1\exc_$signal$5[0:0]$321 $1\exc_$signal$4[0:0]$320 $1\exc_$signal$3[0:0]$319 $1\exc_$signal[0:0]$318 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$317 $1\cr_in2$1[2:0]$316 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:961" + switch \$32 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$9865 $2\dividend$68$next[127:0]$9866 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend$68$next[127:0]$9866 \dividend - case - assign $2\dividend$68$next[127:0]$9866 \dividend$68 - end - case - assign $1\dividend$68$next[127:0]$9865 \dividend$68 - end - sync always - update \dividend$68$next $0\dividend$68$next[127:0]$9864 - end - attribute \src "libresoc.v:162198.3-162212.6" - process $proc$libresoc.v:162198$9867 - assign { } { } - assign { } { } - assign $0\divisor_radicand$65$next[63:0]$9868 $1\divisor_radicand$65$next[63:0]$9869 - attribute \src "libresoc.v:162199.5-162199.29" - switch \initial - attribute \src "libresoc.v:162199.9-162199.17" - case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $5\fasto1[2:0] 3'011 + assign $5\fasto1_ok[0:0] 1'1 + assign $5\fasto2[2:0] 3'100 + assign $5\fasto2_ok[0:0] 1'1 case + assign $5\fasto1[2:0] $1\fasto1[2:0] + assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $5\fasto2[2:0] $1\fasto2[2:0] + assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:970" + switch \$34 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$9869 $2\divisor_radicand$65$next[63:0]$9870 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\divisor_radicand$65$next[63:0]$9870 \divisor_radicand - case - assign $2\divisor_radicand$65$next[63:0]$9870 \divisor_radicand$65 - end + assign { } { } + assign { } { } + assign { } { } + assign $5\fast1[2:0] 3'011 + assign $5\fast1_ok[0:0] 1'1 + assign $5\fast2[2:0] 3'100 + assign $5\fast2_ok[0:0] 1'1 case - assign $1\divisor_radicand$65$next[63:0]$9869 \divisor_radicand$65 + assign $5\fast1[2:0] $1\fast1[2:0] + assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $5\fast2[2:0] $1\fast2[2:0] + assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] end sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9868 + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[2:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[2:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[2:0] + update \cr_in2$1 $0\cr_in2$1[2:0]$306 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$307 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \ea $0\ea[4:0] + update \ea_ok $0\ea_ok[0:0] + update \exc_$signal $0\exc_$signal[0:0]$308 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$309 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$310 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$311 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$312 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$313 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$314 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$315 + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[11:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \msr $0\msr[63:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc $0\rc[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[4:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[4:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[4:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[4:0] + update \rego_ok $0\rego_ok[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[7:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] end - attribute \src "libresoc.v:162213.3-162227.6" - process $proc$libresoc.v:162213$9871 + attribute \src "libresoc.v:8640.7-8640.20" + process $proc$libresoc.v:8640$356 assign { } { } - assign { } { } - assign $0\operation$69$next[1:0]$9872 $1\operation$69$next[1:0]$9873 - attribute \src "libresoc.v:162214.5-162214.29" - switch \initial - attribute \src "libresoc.v:162214.9-162214.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" - switch \empty - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\operation$69$next[1:0]$9873 $2\operation$69$next[1:0]$9874 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" - switch \p_valid_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\operation$69$next[1:0]$9874 \operation - case - assign $2\operation$69$next[1:0]$9874 \operation$69 - end - case - assign $1\operation$69$next[1:0]$9873 \operation$69 - end - sync always - update \operation$69$next $0\operation$69$next[1:0]$9872 - end - connect \$56 $sshl$libresoc.v:161830$9681_Y - connect \$55 $pos$libresoc.v:161831$9683_Y - connect \$59 $not$libresoc.v:161832$9684_Y - connect \$61 $ge$libresoc.v:161833$9685_Y - connect \$63 $and$libresoc.v:161834$9686_Y - connect \$66 $and$libresoc.v:161835$9687_Y - connect \p_ready_o \empty - connect \n_valid_o \$63 - connect \remainder \$55 - connect \quotient_root \div_state_next_o_dividend_quotient [63:0] - connect \div_by_zero$27 \div_by_zero$54 - connect \dive_abs_ov64$26 \dive_abs_ov64$53 - connect \dive_abs_ov32$25 \dive_abs_ov32$52 - connect \dividend_neg$24 \dividend_neg$51 - connect \divisor_neg$23 \divisor_neg$50 - connect \xer_so$22 \xer_so$49 - connect \rb$21 \rb$48 - connect \ra$20 \ra$47 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } - connect \muxid$1 \muxid$28 - connect \div_state_init_dividend \dividend + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \$28 $eq$libresoc.v:10231$288_Y + connect \$30 $eq$libresoc.v:10232$289_Y + connect \$32 $or$libresoc.v:10233$290_Y + connect \$34 $eq$libresoc.v:10234$291_Y + connect \$42 $eq$libresoc.v:10235$292_Y + connect \$44 $eq$libresoc.v:10236$293_Y + connect \$46 $eq$libresoc.v:10237$294_Y + connect \$48 $eq$libresoc.v:10238$295_Y + connect \$50 $and$libresoc.v:10239$296_Y + connect \$52 $and$libresoc.v:10240$297_Y + connect \$54 $and$libresoc.v:10241$298_Y + connect \$56 $eq$libresoc.v:10242$299_Y + connect \dec2_exc_$signal 1'0 + connect \dec2_exc_$signal$12 1'0 + connect \dec2_exc_$signal$13 1'0 + connect \dec2_exc_$signal$14 1'0 + connect \dec2_exc_$signal$15 1'0 + connect \dec2_exc_$signal$16 1'0 + connect \dec2_exc_$signal$17 1'0 + connect \dec2_exc_$signal$18 1'0 + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 8'00000000 + connect \tmp_tmp_exc_$signal 1'0 + connect \tmp_tmp_exc_$signal$21 1'0 + connect \tmp_tmp_exc_$signal$22 1'0 + connect \tmp_tmp_exc_$signal$23 1'0 + connect \tmp_tmp_exc_$signal$24 1'0 + connect \tmp_tmp_exc_$signal$25 1'0 + connect \tmp_tmp_exc_$signal$26 1'0 + connect \tmp_tmp_exc_$signal$27 1'0 + connect \illeg_ok \$56 + connect \priv_ok \$54 + connect \dec_irq_ok \$52 + connect \ext_irq_ok \$50 + connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + connect { \tmp_cr_in2_ok$20 \tmp_cr_in2$19 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \insn_in$41 \dec_opcode_in + connect \insn_in$40 \dec_opcode_in + connect \insn_in$39 \dec_opcode_in + connect \insn_in$38 \dec_opcode_in + connect \insn_in$37 \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \tmp_tmp_fn_unit \dec_function_unit + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$36 \dec_opcode_in + connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:162247.1-163771.10" +attribute \src "libresoc.v:10680.1-11827.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" -module \pipe_start - attribute \src "libresoc.v:163577.3-163589.6" - wire $0\div_by_zero$next[0:0]$9984 - attribute \src "libresoc.v:163363.3-163364.39" - wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:163551.3-163563.6" - wire $0\dive_abs_ov32$next[0:0]$9978 - attribute \src "libresoc.v:163367.3-163368.43" - wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:163564.3-163576.6" - wire $0\dive_abs_ov64$next[0:0]$9981 - attribute \src "libresoc.v:163365.3-163366.43" - wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:163590.3-163602.6" - wire width 128 $0\dividend$next[127:0]$9987 - attribute \src "libresoc.v:163361.3-163362.33" - wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:163538.3-163550.6" - wire $0\dividend_neg$next[0:0]$9975 - attribute \src "libresoc.v:163369.3-163370.41" - wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:163525.3-163537.6" - wire $0\divisor_neg$next[0:0]$9972 - attribute \src "libresoc.v:163371.3-163372.39" - wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:163603.3-163615.6" - wire width 64 $0\divisor_radicand$next[63:0]$9990 - attribute \src "libresoc.v:163359.3-163360.49" - wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:162248.7-162248.20" +module \dec30 + attribute \src "libresoc.v:11123.3-11159.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:11271.3-11307.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:11752.3-11788.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:11789.3-11825.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:11086.3-11122.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:11234.3-11270.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:11567.3-11603.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:10938.3-10974.6" + wire width 12 $0\dec30_function_unit[11:0] + attribute \src "libresoc.v:11604.3-11640.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11641.3-11677.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11678.3-11714.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11345.3-11381.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:11160.3-11196.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:11197.3-11233.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:11419.3-11455.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:10975.3-11011.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11493.3-11529.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:11715.3-11751.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "libresoc.v:11049.3-11085.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11382.3-11418.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:11530.3-11566.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11456.3-11492.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:11308.3-11344.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11012.3-11048.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:10681.7-10681.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 4 $0\logical_op__data_len$next[3:0]$10003 - attribute \src "libresoc.v:163411.3-163412.57" - wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 12 $0\logical_op__fn_unit$next[11:0]$10004 - attribute \src "libresoc.v:163381.3-163382.55" - wire width 12 $0\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$10005 - attribute \src "libresoc.v:163383.3-163384.69" - wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__imm_data__ok$next[0:0]$10006 - attribute \src "libresoc.v:163385.3-163386.65" - wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$10007 - attribute \src "libresoc.v:163399.3-163400.63" - wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 32 $0\logical_op__insn$next[31:0]$10008 - attribute \src "libresoc.v:163413.3-163414.49" - wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$10009 - attribute \src "libresoc.v:163379.3-163380.59" - wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__invert_in$next[0:0]$10010 - attribute \src "libresoc.v:163395.3-163396.59" - wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__invert_out$next[0:0]$10011 - attribute \src "libresoc.v:163401.3-163402.61" - wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__is_32bit$next[0:0]$10012 - attribute \src "libresoc.v:163407.3-163408.57" - wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__is_signed$next[0:0]$10013 - attribute \src "libresoc.v:163409.3-163410.59" - wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__oe__oe$next[0:0]$10014 - attribute \src "libresoc.v:163391.3-163392.53" - wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__oe__ok$next[0:0]$10015 - attribute \src "libresoc.v:163393.3-163394.53" - wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__output_carry$next[0:0]$10016 - attribute \src "libresoc.v:163405.3-163406.65" - wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__rc__ok$next[0:0]$10017 - attribute \src "libresoc.v:163389.3-163390.53" - wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__rc__rc$next[0:0]$10018 - attribute \src "libresoc.v:163387.3-163388.53" - wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__write_cr0$next[0:0]$10019 - attribute \src "libresoc.v:163403.3-163404.59" - wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $0\logical_op__zero_a$next[0:0]$10020 - attribute \src "libresoc.v:163397.3-163398.53" - wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:163647.3-163659.6" - wire width 2 $0\muxid$next[1:0]$10000 - attribute \src "libresoc.v:163415.3-163416.27" - wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:163616.3-163628.6" - wire width 2 $0\operation$next[1:0]$9993 - attribute \src "libresoc.v:163357.3-163358.35" - wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:163629.3-163646.6" - wire $0\r_busy$next[0:0]$9996 - attribute \src "libresoc.v:163417.3-163418.29" - wire $0\r_busy[0:0] - attribute \src "libresoc.v:163702.3-163714.6" - wire width 64 $0\ra$next[63:0]$10046 - attribute \src "libresoc.v:163377.3-163378.21" - wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:163715.3-163727.6" - wire width 64 $0\rb$next[63:0]$10049 - attribute \src "libresoc.v:163375.3-163376.21" - wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:163728.3-163740.6" - wire $0\xer_so$next[0:0]$10052 - attribute \src "libresoc.v:163373.3-163374.29" - wire $0\xer_so[0:0] - attribute \src "libresoc.v:163577.3-163589.6" - wire $1\div_by_zero$next[0:0]$9985 - attribute \src "libresoc.v:162257.7-162257.25" - wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:163551.3-163563.6" - wire $1\dive_abs_ov32$next[0:0]$9979 - attribute \src "libresoc.v:162264.7-162264.27" - wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:163564.3-163576.6" - wire $1\dive_abs_ov64$next[0:0]$9982 - attribute \src "libresoc.v:162271.7-162271.27" - wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:163590.3-163602.6" - wire width 128 $1\dividend$next[127:0]$9988 - attribute \src "libresoc.v:162278.15-162278.63" - wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:163538.3-163550.6" - wire $1\dividend_neg$next[0:0]$9976 - attribute \src "libresoc.v:162285.7-162285.26" - wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:163525.3-163537.6" - wire $1\divisor_neg$next[0:0]$9973 - attribute \src "libresoc.v:162292.7-162292.25" - wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:163603.3-163615.6" - wire width 64 $1\divisor_radicand$next[63:0]$9991 - attribute \src "libresoc.v:162299.14-162299.53" - wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 4 $1\logical_op__data_len$next[3:0]$10021 - attribute \src "libresoc.v:162576.13-162576.40" - wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 12 $1\logical_op__fn_unit$next[11:0]$10022 - attribute \src "libresoc.v:162598.14-162598.43" - wire width 12 $1\logical_op__fn_unit[11:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$10023 - attribute \src "libresoc.v:162633.14-162633.63" - wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__imm_data__ok$next[0:0]$10024 - attribute \src "libresoc.v:162642.7-162642.38" - wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$10025 - attribute \src "libresoc.v:162655.13-162655.43" - wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 32 $1\logical_op__insn$next[31:0]$10026 - attribute \src "libresoc.v:162672.14-162672.38" - wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$10027 - attribute \src "libresoc.v:162755.13-162755.42" - wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__invert_in$next[0:0]$10028 - attribute \src "libresoc.v:162912.7-162912.35" - wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__invert_out$next[0:0]$10029 - attribute \src "libresoc.v:162921.7-162921.36" - wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__is_32bit$next[0:0]$10030 - attribute \src "libresoc.v:162930.7-162930.34" - wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__is_signed$next[0:0]$10031 - attribute \src "libresoc.v:162939.7-162939.35" - wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__oe__oe$next[0:0]$10032 - attribute \src "libresoc.v:162948.7-162948.32" - wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__oe__ok$next[0:0]$10033 - attribute \src "libresoc.v:162957.7-162957.32" - wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__output_carry$next[0:0]$10034 - attribute \src "libresoc.v:162966.7-162966.38" - wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__rc__ok$next[0:0]$10035 - attribute \src "libresoc.v:162975.7-162975.32" - wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__rc__rc$next[0:0]$10036 - attribute \src "libresoc.v:162984.7-162984.32" - wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__write_cr0$next[0:0]$10037 - attribute \src "libresoc.v:162993.7-162993.35" - wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire $1\logical_op__zero_a$next[0:0]$10038 - attribute \src "libresoc.v:163002.7-163002.32" - wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:163647.3-163659.6" - wire width 2 $1\muxid$next[1:0]$10001 - attribute \src "libresoc.v:163011.13-163011.25" - wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:163616.3-163628.6" - wire width 2 $1\operation$next[1:0]$9994 - attribute \src "libresoc.v:163026.13-163026.29" - wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:163629.3-163646.6" - wire $1\r_busy$next[0:0]$9997 - attribute \src "libresoc.v:163040.7-163040.20" - wire $1\r_busy[0:0] - attribute \src "libresoc.v:163702.3-163714.6" - wire width 64 $1\ra$next[63:0]$10047 - attribute \src "libresoc.v:163045.14-163045.39" - wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:163715.3-163727.6" - wire width 64 $1\rb$next[63:0]$10050 - attribute \src "libresoc.v:163056.14-163056.39" - wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:163728.3-163740.6" - wire $1\xer_so$next[0:0]$10053 - attribute \src "libresoc.v:163349.7-163349.20" - wire $1\xer_so[0:0] - attribute \src "libresoc.v:163660.3-163701.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$10039 - attribute \src "libresoc.v:163660.3-163701.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10040 - attribute \src "libresoc.v:163660.3-163701.6" - wire $2\logical_op__oe__oe$next[0:0]$10041 - attribute \src "libresoc.v:163660.3-163701.6" - wire $2\logical_op__oe__ok$next[0:0]$10042 - attribute \src "libresoc.v:163660.3-163701.6" - wire $2\logical_op__rc__ok$next[0:0]$10043 - attribute \src "libresoc.v:163660.3-163701.6" - wire $2\logical_op__rc__rc$next[0:0]$10044 - attribute \src "libresoc.v:163629.3-163646.6" - wire $2\r_busy$next[0:0]$9998 - attribute \src "libresoc.v:163356.18-163356.118" - wire $and$libresoc.v:163356$9939_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 30 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \div_by_zero$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 28 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \dive_abs_ov32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 29 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \dive_abs_ov64$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 31 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 27 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \dividend_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 26 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \divisor_neg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 32 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:162248.7-162248.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \input_logical_op__data_len$40 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \input_logical_op__fn_unit$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \input_logical_op__imm_data__data$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__imm_data__ok$27 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry + attribute \src "libresoc.v:11123.3-11159.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:11271.3-11307.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:11752.3-11788.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11789.3-11825.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:11086.3-11122.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:11234.3-11270.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11567.3-11603.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:10938.3-10974.6" + wire width 12 $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:11604.3-11640.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11641.3-11677.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11678.3-11714.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11345.3-11381.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11160.3-11196.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11197.3-11233.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11419.3-11455.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:10975.3-11011.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:11493.3-11529.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:11715.3-11751.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:11049.3-11085.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11382.3-11418.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11530.3-11566.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11456.3-11492.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11308.3-11344.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11012.3-11048.6" + wire width 2 $1\dec30_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec30_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \input_logical_op__input_carry$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \input_logical_op__insn$41 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \input_logical_op__insn_type$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_in$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__invert_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_32bit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__is_signed$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__oe$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__oe__ok$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__output_carry$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__rc__rc$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__write_cr0$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \input_logical_op__zero_a$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \input_muxid$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \input_xer_so$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 53 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$next - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 6 \logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 38 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec30_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -334613,206 +17258,39 @@ module \pipe_start attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \logical_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 39 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 40 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__imm_data__ok$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 15 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 47 \logical_op__input_carry$12 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 54 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 37 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec30_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -334887,32246 +17365,35764 @@ module \pipe_start attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 45 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 48 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 51 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 52 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 43 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 44 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 50 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 42 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 41 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 49 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 46 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \logical_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 36 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire \n_i_rdy_data - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 33 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire output 35 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire input 34 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire \p_valid_i$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire \r_busy$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 23 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 55 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 24 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 56 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire \setup_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire \setup_stage_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire \setup_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \setup_stage_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire \setup_stage_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire \setup_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \setup_stage_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len$62 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \setup_stage_logical_op__fn_unit - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \setup_stage_logical_op__fn_unit$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__imm_data__ok$49 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn$63 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__invert_out$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_32bit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__is_signed$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__oe$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__oe__ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__output_carry$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__ok$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__rc__rc$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__write_cr0$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \setup_stage_logical_op__zero_a$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \setup_stage_muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \setup_stage_muxid$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \setup_stage_operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \setup_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \setup_stage_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 25 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 57 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \xer_so$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $and$libresoc.v:163356$9939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$65 - connect \B \p_ready_o - connect \Y $and$libresoc.v:163356$9939_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163419.14-163464.4" - cell \input$78 \input - connect \logical_op__data_len \input_logical_op__data_len - connect \logical_op__data_len$18 \input_logical_op__data_len$40 - connect \logical_op__fn_unit \input_logical_op__fn_unit - connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 - connect \logical_op__imm_data__data \input_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 - connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 - connect \logical_op__input_carry \input_logical_op__input_carry - connect \logical_op__input_carry$12 \input_logical_op__input_carry$34 - connect \logical_op__insn \input_logical_op__insn - connect \logical_op__insn$19 \input_logical_op__insn$41 - connect \logical_op__insn_type \input_logical_op__insn_type - connect \logical_op__insn_type$2 \input_logical_op__insn_type$24 - connect \logical_op__invert_in \input_logical_op__invert_in - connect \logical_op__invert_in$10 \input_logical_op__invert_in$32 - connect \logical_op__invert_out \input_logical_op__invert_out - connect \logical_op__invert_out$13 \input_logical_op__invert_out$35 - connect \logical_op__is_32bit \input_logical_op__is_32bit - connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38 - connect \logical_op__is_signed \input_logical_op__is_signed - connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 - connect \logical_op__oe__oe \input_logical_op__oe__oe - connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 - connect \logical_op__oe__ok \input_logical_op__oe__ok - connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 - connect \logical_op__output_carry \input_logical_op__output_carry - connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 - connect \logical_op__rc__ok \input_logical_op__rc__ok - connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 - connect \logical_op__rc__rc \input_logical_op__rc__rc - connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 - connect \logical_op__write_cr0 \input_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 - connect \logical_op__zero_a \input_logical_op__zero_a - connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 - connect \muxid \input_muxid - connect \muxid$1 \input_muxid$23 - connect \ra \input_ra - connect \ra$20 \input_ra$42 - connect \rb \input_rb - connect \rb$21 \input_rb$43 - connect \xer_so \input_xer_so - connect \xer_so$22 \input_xer_so$44 - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163465.10-163468.4" - cell \n$77 \n - connect \n_ready_i \n_ready_i - connect \n_valid_o \n_valid_o - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163469.10-163472.4" - cell \p$76 \p - connect \p_ready_o \p_ready_o - connect \p_valid_i \p_valid_i - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:163473.15-163524.4" - cell \setup_stage \setup_stage - connect \div_by_zero \setup_stage_div_by_zero - connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 - connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 - connect \dividend \setup_stage_dividend - connect \dividend_neg \setup_stage_dividend_neg - connect \divisor_neg \setup_stage_divisor_neg - connect \divisor_radicand \setup_stage_divisor_radicand - connect \logical_op__data_len \setup_stage_logical_op__data_len - connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 - connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit - connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 - connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data - connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 - connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok - connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 - connect \logical_op__input_carry \setup_stage_logical_op__input_carry - connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 - connect \logical_op__insn \setup_stage_logical_op__insn - connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 - connect \logical_op__insn_type \setup_stage_logical_op__insn_type - connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 - connect \logical_op__invert_in \setup_stage_logical_op__invert_in - connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 - connect \logical_op__invert_out \setup_stage_logical_op__invert_out - connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 - connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit - connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 - connect \logical_op__is_signed \setup_stage_logical_op__is_signed - connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 - connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe - connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 - connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok - connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 - connect \logical_op__output_carry \setup_stage_logical_op__output_carry - connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 - connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok - connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 - connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc - connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 - connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 - connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 - connect \logical_op__zero_a \setup_stage_logical_op__zero_a - connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 - connect \muxid \setup_stage_muxid - connect \muxid$1 \setup_stage_muxid$45 - connect \operation \setup_stage_operation - connect \ra \setup_stage_ra - connect \rb \setup_stage_rb - connect \xer_so \setup_stage_xer_so - connect \xer_so$20 \setup_stage_xer_so$64 - end - attribute \src "libresoc.v:162248.7-162248.20" - process $proc$libresoc.v:162248$10054 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:162257.7-162257.25" - process $proc$libresoc.v:162257$10055 - assign { } { } - assign $1\div_by_zero[0:0] 1'0 - sync always - sync init - update \div_by_zero $1\div_by_zero[0:0] - end - attribute \src "libresoc.v:162264.7-162264.27" - process $proc$libresoc.v:162264$10056 - assign { } { } - assign $1\dive_abs_ov32[0:0] 1'0 - sync always - sync init - update \dive_abs_ov32 $1\dive_abs_ov32[0:0] - end - attribute \src "libresoc.v:162271.7-162271.27" - process $proc$libresoc.v:162271$10057 - assign { } { } - assign $1\dive_abs_ov64[0:0] 1'0 - sync always - sync init - update \dive_abs_ov64 $1\dive_abs_ov64[0:0] - end - attribute \src "libresoc.v:162278.15-162278.63" - process $proc$libresoc.v:162278$10058 - assign { } { } - assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \dividend $1\dividend[127:0] - end - attribute \src "libresoc.v:162285.7-162285.26" - process $proc$libresoc.v:162285$10059 - assign { } { } - assign $1\dividend_neg[0:0] 1'0 - sync always - sync init - update \dividend_neg $1\dividend_neg[0:0] - end - attribute \src "libresoc.v:162292.7-162292.25" - process $proc$libresoc.v:162292$10060 - assign { } { } - assign $1\divisor_neg[0:0] 1'0 - sync always - sync init - update \divisor_neg $1\divisor_neg[0:0] - end - attribute \src "libresoc.v:162299.14-162299.53" - process $proc$libresoc.v:162299$10061 - assign { } { } - assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \divisor_radicand $1\divisor_radicand[63:0] - end - attribute \src "libresoc.v:162576.13-162576.40" - process $proc$libresoc.v:162576$10062 - assign { } { } - assign $1\logical_op__data_len[3:0] 4'0000 - sync always - sync init - update \logical_op__data_len $1\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:162598.14-162598.43" - process $proc$libresoc.v:162598$10063 - assign { } { } - assign $1\logical_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:162633.14-162633.63" - process $proc$libresoc.v:162633$10064 - assign { } { } - assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:162642.7-162642.38" - process $proc$libresoc.v:162642$10065 - assign { } { } - assign $1\logical_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:162655.13-162655.43" - process $proc$libresoc.v:162655$10066 - assign { } { } - assign $1\logical_op__input_carry[1:0] 2'00 - sync always - sync init - update \logical_op__input_carry $1\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:162672.14-162672.38" - process $proc$libresoc.v:162672$10067 - assign { } { } - assign $1\logical_op__insn[31:0] 0 - sync always - sync init - update \logical_op__insn $1\logical_op__insn[31:0] - end - attribute \src "libresoc.v:162755.13-162755.42" - process $proc$libresoc.v:162755$10068 - assign { } { } - assign $1\logical_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \logical_op__insn_type $1\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:162912.7-162912.35" - process $proc$libresoc.v:162912$10069 - assign { } { } - assign $1\logical_op__invert_in[0:0] 1'0 - sync always - sync init - update \logical_op__invert_in $1\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:162921.7-162921.36" - process $proc$libresoc.v:162921$10070 - assign { } { } - assign $1\logical_op__invert_out[0:0] 1'0 - sync always - sync init - update \logical_op__invert_out $1\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:162930.7-162930.34" - process $proc$libresoc.v:162930$10071 - assign { } { } - assign $1\logical_op__is_32bit[0:0] 1'0 - sync always - sync init - update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:162939.7-162939.35" - process $proc$libresoc.v:162939$10072 - assign { } { } - assign $1\logical_op__is_signed[0:0] 1'0 - sync always - sync init - update \logical_op__is_signed $1\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:162948.7-162948.32" - process $proc$libresoc.v:162948$10073 - assign { } { } - assign $1\logical_op__oe__oe[0:0] 1'0 - sync always - sync init - update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:162957.7-162957.32" - process $proc$libresoc.v:162957$10074 - assign { } { } - assign $1\logical_op__oe__ok[0:0] 1'0 - sync always - sync init - update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:162966.7-162966.38" - process $proc$libresoc.v:162966$10075 - assign { } { } - assign $1\logical_op__output_carry[0:0] 1'0 - sync always - sync init - update \logical_op__output_carry $1\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:162975.7-162975.32" - process $proc$libresoc.v:162975$10076 - assign { } { } - assign $1\logical_op__rc__ok[0:0] 1'0 - sync always - sync init - update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:162984.7-162984.32" - process $proc$libresoc.v:162984$10077 - assign { } { } - assign $1\logical_op__rc__rc[0:0] 1'0 - sync always - sync init - update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:162993.7-162993.35" - process $proc$libresoc.v:162993$10078 - assign { } { } - assign $1\logical_op__write_cr0[0:0] 1'0 - sync always - sync init - update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:163002.7-163002.32" - process $proc$libresoc.v:163002$10079 - assign { } { } - assign $1\logical_op__zero_a[0:0] 1'0 - sync always - sync init - update \logical_op__zero_a $1\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:163011.13-163011.25" - process $proc$libresoc.v:163011$10080 - assign { } { } - assign $1\muxid[1:0] 2'00 - sync always - sync init - update \muxid $1\muxid[1:0] - end - attribute \src "libresoc.v:163026.13-163026.29" - process $proc$libresoc.v:163026$10081 - assign { } { } - assign $1\operation[1:0] 2'00 - sync always - sync init - update \operation $1\operation[1:0] - end - attribute \src "libresoc.v:163040.7-163040.20" - process $proc$libresoc.v:163040$10082 - assign { } { } - assign $1\r_busy[0:0] 1'0 - sync always - sync init - update \r_busy $1\r_busy[0:0] - end - attribute \src "libresoc.v:163045.14-163045.39" - process $proc$libresoc.v:163045$10083 - assign { } { } - assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \ra $1\ra[63:0] - end - attribute \src "libresoc.v:163056.14-163056.39" - process $proc$libresoc.v:163056$10084 - assign { } { } - assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \rb $1\rb[63:0] - end - attribute \src "libresoc.v:163349.7-163349.20" - process $proc$libresoc.v:163349$10085 - assign { } { } - assign $1\xer_so[0:0] 1'0 - sync always - sync init - update \xer_so $1\xer_so[0:0] - end - attribute \src "libresoc.v:163357.3-163358.35" - process $proc$libresoc.v:163357$9940 - assign { } { } - assign $0\operation[1:0] \operation$next - sync posedge \coresync_clk - update \operation $0\operation[1:0] - end - attribute \src "libresoc.v:163359.3-163360.49" - process $proc$libresoc.v:163359$9941 - assign { } { } - assign $0\divisor_radicand[63:0] \divisor_radicand$next - sync posedge \coresync_clk - update \divisor_radicand $0\divisor_radicand[63:0] - end - attribute \src "libresoc.v:163361.3-163362.33" - process $proc$libresoc.v:163361$9942 - assign { } { } - assign $0\dividend[127:0] \dividend$next - sync posedge \coresync_clk - update \dividend $0\dividend[127:0] - end - attribute \src "libresoc.v:163363.3-163364.39" - process $proc$libresoc.v:163363$9943 - assign { } { } - assign $0\div_by_zero[0:0] \div_by_zero$next - sync posedge \coresync_clk - update \div_by_zero $0\div_by_zero[0:0] - end - attribute \src "libresoc.v:163365.3-163366.43" - process $proc$libresoc.v:163365$9944 - assign { } { } - assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next - sync posedge \coresync_clk - update \dive_abs_ov64 $0\dive_abs_ov64[0:0] - end - attribute \src "libresoc.v:163367.3-163368.43" - process $proc$libresoc.v:163367$9945 - assign { } { } - assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next - sync posedge \coresync_clk - update \dive_abs_ov32 $0\dive_abs_ov32[0:0] - end - attribute \src "libresoc.v:163369.3-163370.41" - process $proc$libresoc.v:163369$9946 - assign { } { } - assign $0\dividend_neg[0:0] \dividend_neg$next - sync posedge \coresync_clk - update \dividend_neg $0\dividend_neg[0:0] - end - attribute \src "libresoc.v:163371.3-163372.39" - process $proc$libresoc.v:163371$9947 - assign { } { } - assign $0\divisor_neg[0:0] \divisor_neg$next - sync posedge \coresync_clk - update \divisor_neg $0\divisor_neg[0:0] - end - attribute \src "libresoc.v:163373.3-163374.29" - process $proc$libresoc.v:163373$9948 - assign { } { } - assign $0\xer_so[0:0] \xer_so$next - sync posedge \coresync_clk - update \xer_so $0\xer_so[0:0] - end - attribute \src "libresoc.v:163375.3-163376.21" - process $proc$libresoc.v:163375$9949 - assign { } { } - assign $0\rb[63:0] \rb$next - sync posedge \coresync_clk - update \rb $0\rb[63:0] - end - attribute \src "libresoc.v:163377.3-163378.21" - process $proc$libresoc.v:163377$9950 - assign { } { } - assign $0\ra[63:0] \ra$next - sync posedge \coresync_clk - update \ra $0\ra[63:0] - end - attribute \src "libresoc.v:163379.3-163380.59" - process $proc$libresoc.v:163379$9951 - assign { } { } - assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next - sync posedge \coresync_clk - update \logical_op__insn_type $0\logical_op__insn_type[6:0] - end - attribute \src "libresoc.v:163381.3-163382.55" - process $proc$libresoc.v:163381$9952 - assign { } { } - assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next - sync posedge \coresync_clk - update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] - end - attribute \src "libresoc.v:163383.3-163384.69" - process $proc$libresoc.v:163383$9953 - assign { } { } - assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next - sync posedge \coresync_clk - update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:163385.3-163386.65" - process $proc$libresoc.v:163385$9954 - assign { } { } - assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next - sync posedge \coresync_clk - update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:163387.3-163388.53" - process $proc$libresoc.v:163387$9955 - assign { } { } - assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next - sync posedge \coresync_clk - update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] - end - attribute \src "libresoc.v:163389.3-163390.53" - process $proc$libresoc.v:163389$9956 - assign { } { } - assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next - sync posedge \coresync_clk - update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] - end - attribute \src "libresoc.v:163391.3-163392.53" - process $proc$libresoc.v:163391$9957 - assign { } { } - assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next - sync posedge \coresync_clk - update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] - end - attribute \src "libresoc.v:163393.3-163394.53" - process $proc$libresoc.v:163393$9958 - assign { } { } - assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next - sync posedge \coresync_clk - update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] - end - attribute \src "libresoc.v:163395.3-163396.59" - process $proc$libresoc.v:163395$9959 - assign { } { } - assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next - sync posedge \coresync_clk - update \logical_op__invert_in $0\logical_op__invert_in[0:0] - end - attribute \src "libresoc.v:163397.3-163398.53" - process $proc$libresoc.v:163397$9960 - assign { } { } - assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next - sync posedge \coresync_clk - update \logical_op__zero_a $0\logical_op__zero_a[0:0] - end - attribute \src "libresoc.v:163399.3-163400.63" - process $proc$libresoc.v:163399$9961 - assign { } { } - assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next - sync posedge \coresync_clk - update \logical_op__input_carry $0\logical_op__input_carry[1:0] - end - attribute \src "libresoc.v:163401.3-163402.61" - process $proc$libresoc.v:163401$9962 - assign { } { } - assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next - sync posedge \coresync_clk - update \logical_op__invert_out $0\logical_op__invert_out[0:0] - end - attribute \src "libresoc.v:163403.3-163404.59" - process $proc$libresoc.v:163403$9963 - assign { } { } - assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next - sync posedge \coresync_clk - update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] - end - attribute \src "libresoc.v:163405.3-163406.65" - process $proc$libresoc.v:163405$9964 - assign { } { } - assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next - sync posedge \coresync_clk - update \logical_op__output_carry $0\logical_op__output_carry[0:0] - end - attribute \src "libresoc.v:163407.3-163408.57" - process $proc$libresoc.v:163407$9965 - assign { } { } - assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next - sync posedge \coresync_clk - update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] - end - attribute \src "libresoc.v:163409.3-163410.59" - process $proc$libresoc.v:163409$9966 - assign { } { } - assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next - sync posedge \coresync_clk - update \logical_op__is_signed $0\logical_op__is_signed[0:0] - end - attribute \src "libresoc.v:163411.3-163412.57" - process $proc$libresoc.v:163411$9967 - assign { } { } - assign $0\logical_op__data_len[3:0] \logical_op__data_len$next - sync posedge \coresync_clk - update \logical_op__data_len $0\logical_op__data_len[3:0] - end - attribute \src "libresoc.v:163413.3-163414.49" - process $proc$libresoc.v:163413$9968 - assign { } { } - assign $0\logical_op__insn[31:0] \logical_op__insn$next - sync posedge \coresync_clk - update \logical_op__insn $0\logical_op__insn[31:0] - end - attribute \src "libresoc.v:163415.3-163416.27" - process $proc$libresoc.v:163415$9969 - assign { } { } - assign $0\muxid[1:0] \muxid$next - sync posedge \coresync_clk - update \muxid $0\muxid[1:0] - end - attribute \src "libresoc.v:163417.3-163418.29" - process $proc$libresoc.v:163417$9970 + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec30_upd + attribute \src "libresoc.v:10681.7-10681.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 4 \opcode_switch + attribute \src "libresoc.v:10681.7-10681.20" + process $proc$libresoc.v:10681$381 assign { } { } - assign $0\r_busy[0:0] \r_busy$next - sync posedge \coresync_clk - update \r_busy $0\r_busy[0:0] + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:163525.3-163537.6" - process $proc$libresoc.v:163525$9971 + attribute \src "libresoc.v:10938.3-10974.6" + process $proc$libresoc.v:10938$357 assign { } { } assign { } { } - assign $0\divisor_neg$next[0:0]$9972 $1\divisor_neg$next[0:0]$9973 - attribute \src "libresoc.v:163526.5-163526.29" + assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] + attribute \src "libresoc.v:10939.5-10939.29" switch \initial - attribute \src "libresoc.v:163526.9-163526.17" + attribute \src "libresoc.v:10939.9-10939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0100 assign { } { } - assign $1\divisor_neg$next[0:0]$9973 \divisor_neg$92 + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0101 assign { } { } - assign $1\divisor_neg$next[0:0]$9973 \divisor_neg$92 - case - assign $1\divisor_neg$next[0:0]$9973 \divisor_neg - end - sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$9972 - end - attribute \src "libresoc.v:163538.3-163550.6" - process $proc$libresoc.v:163538$9974 - assign { } { } - assign { } { } - assign $0\dividend_neg$next[0:0]$9975 $1\dividend_neg$next[0:0]$9976 - attribute \src "libresoc.v:163539.5-163539.29" - switch \initial - attribute \src "libresoc.v:163539.9-163539.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0000 assign { } { } - assign $1\dividend_neg$next[0:0]$9976 \dividend_neg$93 + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0001 assign { } { } - assign $1\dividend_neg$next[0:0]$9976 \dividend_neg$93 - case - assign $1\dividend_neg$next[0:0]$9976 \dividend_neg - end - sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$9975 - end - attribute \src "libresoc.v:163551.3-163563.6" - process $proc$libresoc.v:163551$9977 - assign { } { } - assign { } { } - assign $0\dive_abs_ov32$next[0:0]$9978 $1\dive_abs_ov32$next[0:0]$9979 - attribute \src "libresoc.v:163552.5-163552.29" - switch \initial - attribute \src "libresoc.v:163552.9-163552.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0010 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9979 \dive_abs_ov32$94 + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0011 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$9979 \dive_abs_ov32$94 - case - assign $1\dive_abs_ov32$next[0:0]$9979 \dive_abs_ov32 - end - sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9978 - end - attribute \src "libresoc.v:163564.3-163576.6" - process $proc$libresoc.v:163564$9980 - assign { } { } - assign { } { } - assign $0\dive_abs_ov64$next[0:0]$9981 $1\dive_abs_ov64$next[0:0]$9982 - attribute \src "libresoc.v:163565.5-163565.29" - switch \initial - attribute \src "libresoc.v:163565.9-163565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0110 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9982 \dive_abs_ov64$95 + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0111 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$9982 \dive_abs_ov64$95 - case - assign $1\dive_abs_ov64$next[0:0]$9982 \dive_abs_ov64 - end - sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9981 - end - attribute \src "libresoc.v:163577.3-163589.6" - process $proc$libresoc.v:163577$9983 - assign { } { } - assign { } { } - assign $0\div_by_zero$next[0:0]$9984 $1\div_by_zero$next[0:0]$9985 - attribute \src "libresoc.v:163578.5-163578.29" - switch \initial - attribute \src "libresoc.v:163578.9-163578.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'1000 assign { } { } - assign $1\div_by_zero$next[0:0]$9985 \div_by_zero$96 + assign $1\dec30_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'1001 assign { } { } - assign $1\div_by_zero$next[0:0]$9985 \div_by_zero$96 + assign $1\dec30_function_unit[11:0] 12'000000001000 case - assign $1\div_by_zero$next[0:0]$9985 \div_by_zero + assign $1\dec30_function_unit[11:0] 12'000000000000 end sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$9984 + update \dec30_function_unit $0\dec30_function_unit[11:0] end - attribute \src "libresoc.v:163590.3-163602.6" - process $proc$libresoc.v:163590$9986 + attribute \src "libresoc.v:10975.3-11011.6" + process $proc$libresoc.v:10975$358 assign { } { } assign { } { } - assign $0\dividend$next[127:0]$9987 $1\dividend$next[127:0]$9988 - attribute \src "libresoc.v:163591.5-163591.29" + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:10976.5-10976.29" switch \initial - attribute \src "libresoc.v:163591.9-163591.17" + attribute \src "libresoc.v:10976.9-10976.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0100 assign { } { } - assign $1\dividend$next[127:0]$9988 \dividend$97 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0101 assign { } { } - assign $1\dividend$next[127:0]$9988 \dividend$97 - case - assign $1\dividend$next[127:0]$9988 \dividend - end - sync always - update \dividend$next $0\dividend$next[127:0]$9987 - end - attribute \src "libresoc.v:163603.3-163615.6" - process $proc$libresoc.v:163603$9989 - assign { } { } - assign { } { } - assign $0\divisor_radicand$next[63:0]$9990 $1\divisor_radicand$next[63:0]$9991 - attribute \src "libresoc.v:163604.5-163604.29" - switch \initial - attribute \src "libresoc.v:163604.9-163604.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0000 assign { } { } - assign $1\divisor_radicand$next[63:0]$9991 \divisor_radicand$98 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0001 assign { } { } - assign $1\divisor_radicand$next[63:0]$9991 \divisor_radicand$98 - case - assign $1\divisor_radicand$next[63:0]$9991 \divisor_radicand - end - sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9990 - end - attribute \src "libresoc.v:163616.3-163628.6" - process $proc$libresoc.v:163616$9992 - assign { } { } - assign { } { } - assign $0\operation$next[1:0]$9993 $1\operation$next[1:0]$9994 - attribute \src "libresoc.v:163617.5-163617.29" - switch \initial - attribute \src "libresoc.v:163617.9-163617.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0010 assign { } { } - assign $1\operation$next[1:0]$9994 \operation$99 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0011 assign { } { } - assign $1\operation$next[1:0]$9994 \operation$99 - case - assign $1\operation$next[1:0]$9994 \operation - end - sync always - update \operation$next $0\operation$next[1:0]$9993 - end - attribute \src "libresoc.v:163629.3-163646.6" - process $proc$libresoc.v:163629$9995 - assign { } { } - assign { } { } - assign { } { } - assign $0\r_busy$next[0:0]$9996 $2\r_busy$next[0:0]$9998 - attribute \src "libresoc.v:163630.5-163630.29" - switch \initial - attribute \src "libresoc.v:163630.9-163630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0110 assign { } { } - assign $1\r_busy$next[0:0]$9997 1'1 + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0111 assign { } { } - assign $1\r_busy$next[0:0]$9997 1'0 - case - assign $1\r_busy$next[0:0]$9997 \r_busy - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec30_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $2\r_busy$next[0:0]$9998 1'0 + assign $1\dec30_ldst_len[3:0] 4'0000 case - assign $2\r_busy$next[0:0]$9998 $1\r_busy$next[0:0]$9997 + assign $1\dec30_ldst_len[3:0] 4'0000 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9996 + update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:163647.3-163659.6" - process $proc$libresoc.v:163647$9999 + attribute \src "libresoc.v:11012.3-11048.6" + process $proc$libresoc.v:11012$359 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$10000 $1\muxid$next[1:0]$10001 - attribute \src "libresoc.v:163648.5-163648.29" + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:11013.5-11013.29" switch \initial - attribute \src "libresoc.v:163648.9-163648.17" + attribute \src "libresoc.v:11013.9-11013.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0100 assign { } { } - assign $1\muxid$next[1:0]$10001 \muxid$68 + assign $1\dec30_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\muxid$next[1:0]$10001 \muxid$68 + assign $1\dec30_upd[1:0] 2'00 case - assign $1\muxid$next[1:0]$10001 \muxid + assign $1\dec30_upd[1:0] 2'00 end sync always - update \muxid$next $0\muxid$next[1:0]$10000 + update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:163660.3-163701.6" - process $proc$libresoc.v:163660$10002 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:11049.3-11085.6" + process $proc$libresoc.v:11049$360 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\logical_op__data_len$next[3:0]$10003 $1\logical_op__data_len$next[3:0]$10021 - assign $0\logical_op__fn_unit$next[11:0]$10004 $1\logical_op__fn_unit$next[11:0]$10022 - assign { } { } - assign { } { } - assign $0\logical_op__input_carry$next[1:0]$10007 $1\logical_op__input_carry$next[1:0]$10025 - assign $0\logical_op__insn$next[31:0]$10008 $1\logical_op__insn$next[31:0]$10026 - assign $0\logical_op__insn_type$next[6:0]$10009 $1\logical_op__insn_type$next[6:0]$10027 - assign $0\logical_op__invert_in$next[0:0]$10010 $1\logical_op__invert_in$next[0:0]$10028 - assign $0\logical_op__invert_out$next[0:0]$10011 $1\logical_op__invert_out$next[0:0]$10029 - assign $0\logical_op__is_32bit$next[0:0]$10012 $1\logical_op__is_32bit$next[0:0]$10030 - assign $0\logical_op__is_signed$next[0:0]$10013 $1\logical_op__is_signed$next[0:0]$10031 - assign { } { } - assign { } { } - assign $0\logical_op__output_carry$next[0:0]$10016 $1\logical_op__output_carry$next[0:0]$10034 - assign { } { } - assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$10019 $1\logical_op__write_cr0$next[0:0]$10037 - assign $0\logical_op__zero_a$next[0:0]$10020 $1\logical_op__zero_a$next[0:0]$10038 - assign $0\logical_op__imm_data__data$next[63:0]$10005 $2\logical_op__imm_data__data$next[63:0]$10039 - assign $0\logical_op__imm_data__ok$next[0:0]$10006 $2\logical_op__imm_data__ok$next[0:0]$10040 - assign $0\logical_op__oe__oe$next[0:0]$10014 $2\logical_op__oe__oe$next[0:0]$10041 - assign $0\logical_op__oe__ok$next[0:0]$10015 $2\logical_op__oe__ok$next[0:0]$10042 - assign $0\logical_op__rc__ok$next[0:0]$10017 $2\logical_op__rc__ok$next[0:0]$10043 - assign $0\logical_op__rc__rc$next[0:0]$10018 $2\logical_op__rc__rc$next[0:0]$10044 - attribute \src "libresoc.v:163661.5-163661.29" + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:11050.5-11050.29" switch \initial - attribute \src "libresoc.v:163661.9-163661.17" + attribute \src "libresoc.v:11050.9-11050.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 - assign { } { } - assign { } { } + case 4'0100 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:11086.3-11122.6" + process $proc$libresoc.v:11086$361 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:11087.5-11087.29" + switch \initial + attribute \src "libresoc.v:11087.9-11087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 assign { } { } - assign { $1\logical_op__insn$next[31:0]$10026 $1\logical_op__data_len$next[3:0]$10021 $1\logical_op__is_signed$next[0:0]$10031 $1\logical_op__is_32bit$next[0:0]$10030 $1\logical_op__output_carry$next[0:0]$10034 $1\logical_op__write_cr0$next[0:0]$10037 $1\logical_op__invert_out$next[0:0]$10029 $1\logical_op__input_carry$next[1:0]$10025 $1\logical_op__zero_a$next[0:0]$10038 $1\logical_op__invert_in$next[0:0]$10028 $1\logical_op__oe__ok$next[0:0]$10033 $1\logical_op__oe__oe$next[0:0]$10032 $1\logical_op__rc__ok$next[0:0]$10035 $1\logical_op__rc__rc$next[0:0]$10036 $1\logical_op__imm_data__ok$next[0:0]$10024 $1\logical_op__imm_data__data$next[63:0]$10023 $1\logical_op__fn_unit$next[11:0]$10022 $1\logical_op__insn_type$next[6:0]$10027 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign $1\dec30_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0110 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "libresoc.v:11123.3-11159.6" + process $proc$libresoc.v:11123$362 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:11124.5-11124.29" + switch \initial + attribute \src "libresoc.v:11124.9-11124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "libresoc.v:11160.3-11196.6" + process $proc$libresoc.v:11160$363 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:11161.5-11161.29" + switch \initial + attribute \src "libresoc.v:11161.9-11161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 assign { } { } - assign { $1\logical_op__insn$next[31:0]$10026 $1\logical_op__data_len$next[3:0]$10021 $1\logical_op__is_signed$next[0:0]$10031 $1\logical_op__is_32bit$next[0:0]$10030 $1\logical_op__output_carry$next[0:0]$10034 $1\logical_op__write_cr0$next[0:0]$10037 $1\logical_op__invert_out$next[0:0]$10029 $1\logical_op__input_carry$next[1:0]$10025 $1\logical_op__zero_a$next[0:0]$10038 $1\logical_op__invert_in$next[0:0]$10028 $1\logical_op__oe__ok$next[0:0]$10033 $1\logical_op__oe__oe$next[0:0]$10032 $1\logical_op__rc__ok$next[0:0]$10035 $1\logical_op__rc__rc$next[0:0]$10036 $1\logical_op__imm_data__ok$next[0:0]$10024 $1\logical_op__imm_data__data$next[63:0]$10023 $1\logical_op__fn_unit$next[11:0]$10022 $1\logical_op__insn_type$next[6:0]$10027 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } - case - assign $1\logical_op__data_len$next[3:0]$10021 \logical_op__data_len - assign $1\logical_op__fn_unit$next[11:0]$10022 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$10023 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$10024 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$10025 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$10026 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$10027 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$10028 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$10029 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$10030 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$10031 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$10032 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$10033 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$10034 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$10035 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$10036 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$10037 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$10038 \logical_op__zero_a - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec30_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 4'0010 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$10039 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10040 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10044 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10043 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10041 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10042 1'0 + assign $1\dec30_inv_a[0:0] 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$10039 $1\logical_op__imm_data__data$next[63:0]$10023 - assign $2\logical_op__imm_data__ok$next[0:0]$10040 $1\logical_op__imm_data__ok$next[0:0]$10024 - assign $2\logical_op__oe__oe$next[0:0]$10041 $1\logical_op__oe__oe$next[0:0]$10032 - assign $2\logical_op__oe__ok$next[0:0]$10042 $1\logical_op__oe__ok$next[0:0]$10033 - assign $2\logical_op__rc__ok$next[0:0]$10043 $1\logical_op__rc__ok$next[0:0]$10035 - assign $2\logical_op__rc__rc$next[0:0]$10044 $1\logical_op__rc__rc$next[0:0]$10036 + assign $1\dec30_inv_a[0:0] 1'0 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10003 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$10004 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10005 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10006 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10007 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10008 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10009 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10010 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10011 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10012 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10013 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10014 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10015 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10016 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10017 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10018 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10019 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10020 + update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:163702.3-163714.6" - process $proc$libresoc.v:163702$10045 + attribute \src "libresoc.v:11197.3-11233.6" + process $proc$libresoc.v:11197$364 assign { } { } assign { } { } - assign $0\ra$next[63:0]$10046 $1\ra$next[63:0]$10047 - attribute \src "libresoc.v:163703.5-163703.29" + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:11198.5-11198.29" switch \initial - attribute \src "libresoc.v:163703.9-163703.17" + attribute \src "libresoc.v:11198.9-11198.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0100 assign { } { } - assign $1\ra$next[63:0]$10047 \ra$87 + assign $1\dec30_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 assign { } { } - assign $1\ra$next[63:0]$10047 \ra$87 + assign $1\dec30_inv_out[0:0] 1'0 case - assign $1\ra$next[63:0]$10047 \ra + assign $1\dec30_inv_out[0:0] 1'0 end sync always - update \ra$next $0\ra$next[63:0]$10046 + update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:163715.3-163727.6" - process $proc$libresoc.v:163715$10048 + attribute \src "libresoc.v:11234.3-11270.6" + process $proc$libresoc.v:11234$365 assign { } { } assign { } { } - assign $0\rb$next[63:0]$10049 $1\rb$next[63:0]$10050 - attribute \src "libresoc.v:163716.5-163716.29" + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:11235.5-11235.29" switch \initial - attribute \src "libresoc.v:163716.9-163716.17" + attribute \src "libresoc.v:11235.9-11235.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0100 assign { } { } - assign $1\rb$next[63:0]$10050 \rb$89 + assign $1\dec30_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 assign { } { } - assign $1\rb$next[63:0]$10050 \rb$89 + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 case - assign $1\rb$next[63:0]$10050 \rb + assign $1\dec30_cry_out[0:0] 1'0 end sync always - update \rb$next $0\rb$next[63:0]$10049 + update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:163728.3-163740.6" - process $proc$libresoc.v:163728$10051 + attribute \src "libresoc.v:11271.3-11307.6" + process $proc$libresoc.v:11271$366 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$10052 $1\xer_so$next[0:0]$10053 - attribute \src "libresoc.v:163729.5-163729.29" + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:11272.5-11272.29" switch \initial - attribute \src "libresoc.v:163729.9-163729.17" + attribute \src "libresoc.v:11272.9-11272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0100 assign { } { } - assign $1\xer_so$next[0:0]$10053 \xer_so$91 + assign $1\dec30_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0101 assign { } { } - assign $1\xer_so$next[0:0]$10053 \xer_so$91 - case - assign $1\xer_so$next[0:0]$10053 \xer_so - end - sync always - update \xer_so$next $0\xer_so$next[0:0]$10052 - end - connect \$66 $and$libresoc.v:163356$9939_Y - connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \p_ready_o \n_i_rdy_data - connect \n_valid_o \r_busy - connect \operation$99 \setup_stage_operation - connect \divisor_radicand$98 \setup_stage_divisor_radicand - connect \dividend$97 \setup_stage_dividend - connect \div_by_zero$96 \setup_stage_div_by_zero - connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 - connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 - connect \dividend_neg$93 \setup_stage_dividend_neg - connect \divisor_neg$92 \setup_stage_divisor_neg - connect \xer_so$91 \setup_stage_xer_so$64 - connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 - connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } - connect \muxid$68 \setup_stage_muxid$45 - connect \p_valid_i_p_ready_o \$66 - connect \n_i_rdy_data \n_ready_i - connect \p_valid_i$65 \p_valid_i - connect \setup_stage_xer_so \input_xer_so$44 - connect \setup_stage_rb \input_rb$43 - connect \setup_stage_ra \input_ra$42 - connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } - connect \setup_stage_muxid \input_muxid$23 - connect \input_xer_so \xer_so$22 - connect \input_rb \rb$21 - connect \input_ra \ra$20 - connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } - connect \input_muxid \muxid$1 -end -attribute \src "libresoc.v:163775.1-163781.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.pll" -attribute \generator "nMigen" -module \pll - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:78" - wire input 1 \clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:79" - wire output 2 \clk_pll_o - connect \clk_pll_o \clk_24_i -end -attribute \src "libresoc.v:163785.1-164427.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" -attribute \generator "nMigen" -module \popcount - attribute \src "libresoc.v:163786.7-163786.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:164274.3-164300.6" - wire width 64 $0\o[63:0] - attribute \src "libresoc.v:164274.3-164300.6" - wire width 64 $1\o[63:0] - attribute \src "libresoc.v:164198.19-164198.132" - wire width 4 $add$libresoc.v:164198$10086_Y - attribute \src "libresoc.v:164199.19-164199.132" - wire width 4 $add$libresoc.v:164199$10087_Y - attribute \src "libresoc.v:164200.19-164200.132" - wire width 4 $add$libresoc.v:164200$10088_Y - attribute \src "libresoc.v:164201.19-164201.132" - wire width 4 $add$libresoc.v:164201$10089_Y - attribute \src "libresoc.v:164202.19-164202.134" - wire width 4 $add$libresoc.v:164202$10090_Y - attribute \src "libresoc.v:164203.19-164203.134" - wire width 4 $add$libresoc.v:164203$10091_Y - attribute \src "libresoc.v:164204.18-164204.125" - wire width 3 $add$libresoc.v:164204$10092_Y - attribute \src "libresoc.v:164205.19-164205.134" - wire width 4 $add$libresoc.v:164205$10093_Y - attribute \src "libresoc.v:164206.19-164206.134" - wire width 4 $add$libresoc.v:164206$10094_Y - attribute \src "libresoc.v:164207.19-164207.134" - wire width 4 $add$libresoc.v:164207$10095_Y - attribute \src "libresoc.v:164208.19-164208.134" - wire width 4 $add$libresoc.v:164208$10096_Y - attribute \src "libresoc.v:164209.19-164209.134" - wire width 4 $add$libresoc.v:164209$10097_Y - attribute \src "libresoc.v:164210.19-164210.134" - wire width 4 $add$libresoc.v:164210$10098_Y - attribute \src "libresoc.v:164211.19-164211.134" - wire width 4 $add$libresoc.v:164211$10099_Y - attribute \src "libresoc.v:164212.19-164212.134" - wire width 4 $add$libresoc.v:164212$10100_Y - attribute \src "libresoc.v:164213.19-164213.134" - wire width 4 $add$libresoc.v:164213$10101_Y - attribute \src "libresoc.v:164214.19-164214.132" - wire width 5 $add$libresoc.v:164214$10102_Y - attribute \src "libresoc.v:164215.18-164215.125" - wire width 3 $add$libresoc.v:164215$10103_Y - attribute \src "libresoc.v:164216.19-164216.132" - wire width 5 $add$libresoc.v:164216$10104_Y - attribute \src "libresoc.v:164217.19-164217.132" - wire width 5 $add$libresoc.v:164217$10105_Y - attribute \src "libresoc.v:164218.19-164218.132" - wire width 5 $add$libresoc.v:164218$10106_Y - attribute \src "libresoc.v:164219.19-164219.132" - wire width 5 $add$libresoc.v:164219$10107_Y - attribute \src "libresoc.v:164220.19-164220.134" - wire width 5 $add$libresoc.v:164220$10108_Y - attribute \src "libresoc.v:164221.19-164221.134" - wire width 5 $add$libresoc.v:164221$10109_Y - attribute \src "libresoc.v:164222.19-164222.134" - wire width 5 $add$libresoc.v:164222$10110_Y - attribute \src "libresoc.v:164223.19-164223.132" - wire width 6 $add$libresoc.v:164223$10111_Y - attribute \src "libresoc.v:164224.19-164224.132" - wire width 6 $add$libresoc.v:164224$10112_Y - attribute \src "libresoc.v:164225.19-164225.132" - wire width 6 $add$libresoc.v:164225$10113_Y - attribute \src "libresoc.v:164226.18-164226.127" - wire width 3 $add$libresoc.v:164226$10114_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_15 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 6 \pop_6_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 6 \pop_6_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 7 \pop_7_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164198$10086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_2 } - connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:164198$10086_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164199$10087 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_4 } - connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:164199$10087_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164200$10088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_6 } - connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:164200$10088_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164201$10089 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_8 } - connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:164201$10089_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" 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connect \Y $add$libresoc.v:164207$10095_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164208$10096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_20 } - connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:164208$10096_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164209$10097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_22 } - connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:164209$10097_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164210$10098 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_24 } - connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:164210$10098_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164211$10099 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_26 } - connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:164211$10099_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164212$10100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_28 } - connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:164212$10100_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164213$10101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_30 } - connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:164213$10101_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164214$10102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_0 } - connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:164214$10102_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164215$10103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [8] } - connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:164215$10103_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164216$10104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_2 } - connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:164216$10104_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164217$10105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_4 } - connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:164217$10105_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164218$10106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_6 } - connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:164218$10106_Y - end - attribute \src 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\Y $add$libresoc.v:164221$10109_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164222$10110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { 2'00 \pop_3_14 } - connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:164222$10110_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164223$10111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_0 } - connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:164223$10111_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164224$10112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_2 } - connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:164224$10112_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164225$10113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_4 } - connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:164225$10113_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164226$10114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [10] } - connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:164226$10114_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164227$10115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { 2'00 \pop_4_6 } - connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:164227$10115_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164228$10116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_0 } - connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:164228$10116_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164229$10117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A { 2'00 \pop_5_2 } - connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:164229$10117_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164230$10118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { 2'00 \pop_6_0 } - connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:164230$10118_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164241$10137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [12] } - connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:164241$10137_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164245$10144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [14] } - connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:164245$10144_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164246$10145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [16] } - connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:164246$10145_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164247$10146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [0] } - connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:164247$10146_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164248$10147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [18] } - connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:164248$10147_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164249$10148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [20] } - connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:164249$10148_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164250$10149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [22] } - connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:164250$10149_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164251$10150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [24] } - connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:164251$10150_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164252$10151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [26] } - connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:164252$10151_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164253$10152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [28] } - connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:164253$10152_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164254$10153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [30] } - connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:164254$10153_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164255$10154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [32] } - connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:164255$10154_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164256$10155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [34] } - connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:164256$10155_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164257$10156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [36] } - connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:164257$10156_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164258$10157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [2] } - connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:164258$10157_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164259$10158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [38] } - connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:164259$10158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164260$10159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [40] } - connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:164260$10159_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164261$10160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [42] } - connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:164261$10160_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164262$10161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [44] } - connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:164262$10161_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164263$10162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [46] } - connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:164263$10162_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164264$10163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [48] } - connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:164264$10163_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164265$10164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [50] } - connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:164265$10164_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164266$10165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [52] } - connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:164266$10165_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164267$10166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [54] } - connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:164267$10166_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164268$10167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [56] } - connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:164268$10167_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164269$10168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [4] } - connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:164269$10168_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164270$10169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [58] } - connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:164270$10169_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164271$10170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [60] } - connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:164271$10170_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164272$10171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { 2'00 \a [62] } - connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:164272$10171_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:164273$10172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { 2'00 \pop_2_0 } - connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:164273$10172_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:164231$10119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 1'1 - connect \Y $eq$libresoc.v:164231$10119_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:164232$10120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 3'100 - connect \Y $eq$libresoc.v:164232$10120_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164233$10121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_0 - connect \Y $extend$libresoc.v:164233$10121_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164234$10123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_1 - connect \Y $extend$libresoc.v:164234$10123_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164235$10125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_2 - connect \Y $extend$libresoc.v:164235$10125_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164236$10127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_3 - connect \Y $extend$libresoc.v:164236$10127_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164237$10129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_4 - connect \Y $extend$libresoc.v:164237$10129_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164238$10131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_5 - connect \Y $extend$libresoc.v:164238$10131_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164239$10133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_6 - connect \Y $extend$libresoc.v:164239$10133_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164240$10135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_7 - connect \Y $extend$libresoc.v:164240$10135_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164242$10138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_0 - connect \Y $extend$libresoc.v:164242$10138_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164243$10140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_1 - connect \Y $extend$libresoc.v:164243$10140_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:164244$10142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \pop_7_0 - connect \Y $extend$libresoc.v:164244$10142_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164233$10122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164233$10121_Y - connect \Y $pos$libresoc.v:164233$10122_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164234$10124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164234$10123_Y - connect \Y $pos$libresoc.v:164234$10124_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164235$10126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164235$10125_Y - connect \Y $pos$libresoc.v:164235$10126_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164236$10128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164236$10127_Y - connect \Y $pos$libresoc.v:164236$10128_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164237$10130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164237$10129_Y - connect \Y $pos$libresoc.v:164237$10130_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164238$10132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164238$10131_Y - connect \Y $pos$libresoc.v:164238$10132_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164239$10134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164239$10133_Y - connect \Y $pos$libresoc.v:164239$10134_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164240$10136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:164240$10135_Y - connect \Y $pos$libresoc.v:164240$10136_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164242$10139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:164242$10138_Y - connect \Y $pos$libresoc.v:164242$10139_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164243$10141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:164243$10140_Y - connect \Y $pos$libresoc.v:164243$10141_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:164244$10143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:164244$10142_Y - connect \Y $pos$libresoc.v:164244$10143_Y + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:163786.7-163786.20" - process $proc$libresoc.v:163786$10174 + attribute \src "libresoc.v:11308.3-11344.6" + process $proc$libresoc.v:11308$367 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:11309.5-11309.29" + switch \initial + attribute \src "libresoc.v:11309.9-11309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:164274.3-164300.6" - process $proc$libresoc.v:164274$10173 + attribute \src "libresoc.v:11345.3-11381.6" + process $proc$libresoc.v:11345$368 assign { } { } - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:164275.5-164275.29" + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:11346.5-11346.29" switch \initial - attribute \src "libresoc.v:164275.9-164275.17" + attribute \src "libresoc.v:11346.9-11346.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - switch { \$192 \$190 } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 4'0100 assign { } { } - assign $1\o[63:0] [7:0] \$194 - assign $1\o[63:0] [15:8] \$196 - assign $1\o[63:0] [23:16] \$198 - assign $1\o[63:0] [31:24] \$200 - assign $1\o[63:0] [39:32] \$202 - assign $1\o[63:0] [47:40] \$204 - assign $1\o[63:0] [55:48] \$206 - assign $1\o[63:0] [63:56] \$208 + assign $1\dec30_internal_op[6:0] 7'0111000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 4'0101 assign { } { } - assign $1\o[63:0] [31:0] \$210 - assign $1\o[63:0] [63:32] \$212 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\o[63:0] \$214 - end - sync always - update \o $0\o[63:0] - end - connect \$101 $add$libresoc.v:164198$10086_Y - connect \$104 $add$libresoc.v:164199$10087_Y - connect \$107 $add$libresoc.v:164200$10088_Y - connect \$110 $add$libresoc.v:164201$10089_Y - connect \$113 $add$libresoc.v:164202$10090_Y - connect \$116 $add$libresoc.v:164203$10091_Y - connect \$11 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$not$libresoc.v:164492$10179_Y - attribute \src "libresoc.v:164493.17-164493.138" - wire width 8 $not$libresoc.v:164493$10180_Y - attribute \src "libresoc.v:164495.18-164495.93" - wire $not$libresoc.v:164495$10182_Y - attribute \src "libresoc.v:164497.18-164497.93" - wire $not$libresoc.v:164497$10184_Y - attribute \src "libresoc.v:164499.18-164499.93" - wire $not$libresoc.v:164499$10186_Y - attribute \src "libresoc.v:164502.17-164502.91" - wire $not$libresoc.v:164502$10189_Y - attribute \src "libresoc.v:164489.18-164489.116" - wire $reduce_or$libresoc.v:164489$10176_Y - attribute \src "libresoc.v:164491.18-164491.122" - wire $reduce_or$libresoc.v:164491$10178_Y - attribute \src "libresoc.v:164494.18-164494.128" - wire $reduce_or$libresoc.v:164494$10181_Y - attribute \src "libresoc.v:164496.18-164496.134" - wire $reduce_or$libresoc.v:164496$10183_Y - attribute \src "libresoc.v:164498.18-164498.140" - wire $reduce_or$libresoc.v:164498$10185_Y - attribute \src "libresoc.v:164500.18-164500.90" - wire $reduce_or$libresoc.v:164500$10187_Y - attribute \src "libresoc.v:164501.17-164501.103" - wire $reduce_or$libresoc.v:164501$10188_Y - attribute \src "libresoc.v:164503.17-164503.109" - wire $reduce_or$libresoc.v:164503$10190_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src 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$not$libresoc.v:164488$10175_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164490$10177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164490$10177_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164492$10179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164492$10179_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164493$10180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164493$10180_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164495$10182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164495$10182_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164497$10184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164497$10184_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164499$10186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164499$10186_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164502$10189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164502$10189_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164489$10176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164489$10176_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164491$10178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164491$10178_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164494$10181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164494$10181_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164496$10183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164496$10183_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164498$10185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164498$10185_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164500$10187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164500$10187_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164501$10188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164501$10188_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164503$10190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164503$10190_Y - end - connect \$7 $not$libresoc.v:164488$10175_Y - connect \$12 $reduce_or$libresoc.v:164489$10176_Y - connect \$11 $not$libresoc.v:164490$10177_Y - connect \$16 $reduce_or$libresoc.v:164491$10178_Y - connect \$15 $not$libresoc.v:164492$10179_Y - connect \$1 $not$libresoc.v:164493$10180_Y - connect \$20 $reduce_or$libresoc.v:164494$10181_Y - connect \$19 $not$libresoc.v:164495$10182_Y - connect \$24 $reduce_or$libresoc.v:164496$10183_Y - connect \$23 $not$libresoc.v:164497$10184_Y - connect \$28 $reduce_or$libresoc.v:164498$10185_Y - connect \$27 $not$libresoc.v:164499$10186_Y - connect \$31 $reduce_or$libresoc.v:164500$10187_Y - connect \$4 $reduce_or$libresoc.v:164501$10188_Y - connect \$3 $not$libresoc.v:164502$10189_Y - connect \$8 $reduce_or$libresoc.v:164503$10190_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164519.1-164603.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$139 - attribute \src "libresoc.v:164576.17-164576.91" - wire $not$libresoc.v:164576$10191_Y - attribute \src "libresoc.v:164578.18-164578.93" - wire $not$libresoc.v:164578$10193_Y - attribute \src "libresoc.v:164580.18-164580.93" - wire $not$libresoc.v:164580$10195_Y - attribute \src "libresoc.v:164581.17-164581.138" - wire width 8 $not$libresoc.v:164581$10196_Y - attribute \src "libresoc.v:164583.18-164583.93" - wire $not$libresoc.v:164583$10198_Y - attribute \src "libresoc.v:164585.18-164585.93" - wire $not$libresoc.v:164585$10200_Y - attribute \src "libresoc.v:164587.18-164587.93" - wire $not$libresoc.v:164587$10202_Y - attribute \src "libresoc.v:164590.17-164590.91" - wire $not$libresoc.v:164590$10205_Y - attribute \src "libresoc.v:164577.18-164577.116" - wire $reduce_or$libresoc.v:164577$10192_Y - attribute \src "libresoc.v:164579.18-164579.122" - wire $reduce_or$libresoc.v:164579$10194_Y - attribute \src "libresoc.v:164582.18-164582.128" - wire $reduce_or$libresoc.v:164582$10197_Y - attribute \src "libresoc.v:164584.18-164584.134" - wire $reduce_or$libresoc.v:164584$10199_Y - attribute \src "libresoc.v:164586.18-164586.140" - wire $reduce_or$libresoc.v:164586$10201_Y - attribute \src "libresoc.v:164588.18-164588.90" - wire $reduce_or$libresoc.v:164588$10203_Y - attribute \src "libresoc.v:164589.17-164589.103" - wire $reduce_or$libresoc.v:164589$10204_Y - attribute \src "libresoc.v:164591.17-164591.109" - wire $reduce_or$libresoc.v:164591$10206_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164576$10191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164576$10191_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164578$10193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164578$10193_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164580$10195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164580$10195_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164581$10196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164581$10196_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164583$10198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164583$10198_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164585$10200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164585$10200_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164587$10202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164587$10202_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164590$10205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164590$10205_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164577$10192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164577$10192_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164579$10194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164579$10194_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164582$10197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164582$10197_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164584$10199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164584$10199_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164586$10201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164586$10201_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164588$10203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164588$10203_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164589$10204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164589$10204_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164591$10206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164591$10206_Y - end - connect \$7 $not$libresoc.v:164576$10191_Y - connect \$12 $reduce_or$libresoc.v:164577$10192_Y - connect \$11 $not$libresoc.v:164578$10193_Y - connect \$16 $reduce_or$libresoc.v:164579$10194_Y - connect \$15 $not$libresoc.v:164580$10195_Y - connect \$1 $not$libresoc.v:164581$10196_Y - connect \$20 $reduce_or$libresoc.v:164582$10197_Y - connect \$19 $not$libresoc.v:164583$10198_Y - connect \$24 $reduce_or$libresoc.v:164584$10199_Y - connect \$23 $not$libresoc.v:164585$10200_Y - connect \$28 $reduce_or$libresoc.v:164586$10201_Y - connect \$27 $not$libresoc.v:164587$10202_Y - connect \$31 $reduce_or$libresoc.v:164588$10203_Y - connect \$4 $reduce_or$libresoc.v:164589$10204_Y - connect \$3 $not$libresoc.v:164590$10205_Y - connect \$8 $reduce_or$libresoc.v:164591$10206_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164607.1-164691.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$144 - attribute \src "libresoc.v:164664.17-164664.91" - wire $not$libresoc.v:164664$10207_Y - attribute \src "libresoc.v:164666.18-164666.93" - wire $not$libresoc.v:164666$10209_Y - attribute \src "libresoc.v:164668.18-164668.93" - wire $not$libresoc.v:164668$10211_Y - attribute \src "libresoc.v:164669.17-164669.138" - wire width 8 $not$libresoc.v:164669$10212_Y - attribute \src "libresoc.v:164671.18-164671.93" - wire $not$libresoc.v:164671$10214_Y - attribute \src "libresoc.v:164673.18-164673.93" - wire $not$libresoc.v:164673$10216_Y - attribute \src "libresoc.v:164675.18-164675.93" - wire $not$libresoc.v:164675$10218_Y - attribute \src "libresoc.v:164678.17-164678.91" - wire $not$libresoc.v:164678$10221_Y - attribute \src "libresoc.v:164665.18-164665.116" - wire $reduce_or$libresoc.v:164665$10208_Y - attribute \src "libresoc.v:164667.18-164667.122" - wire $reduce_or$libresoc.v:164667$10210_Y - attribute \src "libresoc.v:164670.18-164670.128" - wire $reduce_or$libresoc.v:164670$10213_Y - attribute \src "libresoc.v:164672.18-164672.134" - wire $reduce_or$libresoc.v:164672$10215_Y - attribute \src "libresoc.v:164674.18-164674.140" - wire $reduce_or$libresoc.v:164674$10217_Y - attribute \src "libresoc.v:164676.18-164676.90" - wire $reduce_or$libresoc.v:164676$10219_Y - attribute \src "libresoc.v:164677.17-164677.103" - wire $reduce_or$libresoc.v:164677$10220_Y - attribute \src "libresoc.v:164679.17-164679.109" - wire $reduce_or$libresoc.v:164679$10222_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164664$10207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164664$10207_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164666$10209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164666$10209_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164668$10211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164668$10211_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164669$10212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164669$10212_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164671$10214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164671$10214_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164673$10216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164673$10216_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164675$10218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164675$10218_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164678$10221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164678$10221_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164665$10208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164665$10208_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164667$10210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164667$10210_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164670$10213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164670$10213_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164672$10215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164672$10215_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164674$10217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164674$10217_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164676$10219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164676$10219_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164677$10220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164677$10220_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164679$10222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164679$10222_Y - end - connect \$7 $not$libresoc.v:164664$10207_Y - connect \$12 $reduce_or$libresoc.v:164665$10208_Y - connect \$11 $not$libresoc.v:164666$10209_Y - connect \$16 $reduce_or$libresoc.v:164667$10210_Y - connect \$15 $not$libresoc.v:164668$10211_Y - connect \$1 $not$libresoc.v:164669$10212_Y - connect \$20 $reduce_or$libresoc.v:164670$10213_Y - connect \$19 $not$libresoc.v:164671$10214_Y - connect \$24 $reduce_or$libresoc.v:164672$10215_Y - connect \$23 $not$libresoc.v:164673$10216_Y - connect \$28 $reduce_or$libresoc.v:164674$10217_Y - connect \$27 $not$libresoc.v:164675$10218_Y - connect \$31 $reduce_or$libresoc.v:164676$10219_Y - connect \$4 $reduce_or$libresoc.v:164677$10220_Y - connect \$3 $not$libresoc.v:164678$10221_Y - connect \$8 $reduce_or$libresoc.v:164679$10222_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164695.1-164779.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$146 - attribute \src "libresoc.v:164752.17-164752.91" - wire $not$libresoc.v:164752$10223_Y - attribute \src "libresoc.v:164754.18-164754.93" - wire $not$libresoc.v:164754$10225_Y - attribute \src "libresoc.v:164756.18-164756.93" - wire $not$libresoc.v:164756$10227_Y - attribute \src "libresoc.v:164757.17-164757.138" - wire width 8 $not$libresoc.v:164757$10228_Y - attribute \src "libresoc.v:164759.18-164759.93" - wire $not$libresoc.v:164759$10230_Y - attribute \src "libresoc.v:164761.18-164761.93" - wire $not$libresoc.v:164761$10232_Y - attribute \src "libresoc.v:164763.18-164763.93" - wire $not$libresoc.v:164763$10234_Y - attribute \src "libresoc.v:164766.17-164766.91" - wire $not$libresoc.v:164766$10237_Y - attribute \src "libresoc.v:164753.18-164753.116" - wire $reduce_or$libresoc.v:164753$10224_Y - attribute \src "libresoc.v:164755.18-164755.122" - wire $reduce_or$libresoc.v:164755$10226_Y - attribute \src "libresoc.v:164758.18-164758.128" - wire $reduce_or$libresoc.v:164758$10229_Y - attribute \src "libresoc.v:164760.18-164760.134" - wire $reduce_or$libresoc.v:164760$10231_Y - attribute \src "libresoc.v:164762.18-164762.140" - wire $reduce_or$libresoc.v:164762$10233_Y - attribute \src "libresoc.v:164764.18-164764.90" - wire $reduce_or$libresoc.v:164764$10235_Y - attribute \src "libresoc.v:164765.17-164765.103" - wire $reduce_or$libresoc.v:164765$10236_Y - attribute \src "libresoc.v:164767.17-164767.109" - wire $reduce_or$libresoc.v:164767$10238_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164752$10223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164752$10223_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164754$10225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164754$10225_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164756$10227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164756$10227_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164757$10228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164757$10228_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164759$10230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164759$10230_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164761$10232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164761$10232_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164763$10234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164763$10234_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164766$10237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164766$10237_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164753$10224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164753$10224_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164755$10226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164755$10226_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164758$10229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164758$10229_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164760$10231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164760$10231_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164762$10233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164762$10233_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164764$10235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164764$10235_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164765$10236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164765$10236_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164767$10238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164767$10238_Y - end - connect \$7 $not$libresoc.v:164752$10223_Y - connect \$12 $reduce_or$libresoc.v:164753$10224_Y - connect \$11 $not$libresoc.v:164754$10225_Y - connect \$16 $reduce_or$libresoc.v:164755$10226_Y - connect \$15 $not$libresoc.v:164756$10227_Y - connect \$1 $not$libresoc.v:164757$10228_Y - connect \$20 $reduce_or$libresoc.v:164758$10229_Y - connect \$19 $not$libresoc.v:164759$10230_Y - connect \$24 $reduce_or$libresoc.v:164760$10231_Y - connect \$23 $not$libresoc.v:164761$10232_Y - connect \$28 $reduce_or$libresoc.v:164762$10233_Y - connect \$27 $not$libresoc.v:164763$10234_Y - connect \$31 $reduce_or$libresoc.v:164764$10235_Y - connect \$4 $reduce_or$libresoc.v:164765$10236_Y - connect \$3 $not$libresoc.v:164766$10237_Y - connect \$8 $reduce_or$libresoc.v:164767$10238_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164783.1-164867.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$151 - attribute \src "libresoc.v:164840.17-164840.91" - wire $not$libresoc.v:164840$10239_Y - attribute \src "libresoc.v:164842.18-164842.93" - wire $not$libresoc.v:164842$10241_Y - attribute \src "libresoc.v:164844.18-164844.93" - wire $not$libresoc.v:164844$10243_Y - attribute \src "libresoc.v:164845.17-164845.138" - wire width 8 $not$libresoc.v:164845$10244_Y - attribute \src "libresoc.v:164847.18-164847.93" - wire $not$libresoc.v:164847$10246_Y - attribute \src "libresoc.v:164849.18-164849.93" - wire $not$libresoc.v:164849$10248_Y - attribute \src "libresoc.v:164851.18-164851.93" - wire $not$libresoc.v:164851$10250_Y - attribute \src "libresoc.v:164854.17-164854.91" - wire $not$libresoc.v:164854$10253_Y - attribute \src "libresoc.v:164841.18-164841.116" - wire $reduce_or$libresoc.v:164841$10240_Y - attribute \src "libresoc.v:164843.18-164843.122" - wire $reduce_or$libresoc.v:164843$10242_Y - attribute \src "libresoc.v:164846.18-164846.128" - wire $reduce_or$libresoc.v:164846$10245_Y - attribute \src "libresoc.v:164848.18-164848.134" - wire $reduce_or$libresoc.v:164848$10247_Y - attribute \src "libresoc.v:164850.18-164850.140" - wire $reduce_or$libresoc.v:164850$10249_Y - attribute \src "libresoc.v:164852.18-164852.90" - wire $reduce_or$libresoc.v:164852$10251_Y - attribute \src "libresoc.v:164853.17-164853.103" - wire $reduce_or$libresoc.v:164853$10252_Y - attribute \src "libresoc.v:164855.17-164855.109" - wire $reduce_or$libresoc.v:164855$10254_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164840$10239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164840$10239_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164842$10241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164842$10241_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164844$10243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164844$10243_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164845$10244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164845$10244_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164847$10246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164847$10246_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164849$10248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164849$10248_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164851$10250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164851$10250_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164854$10253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164854$10253_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164841$10240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164841$10240_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164843$10242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164843$10242_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164846$10245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164846$10245_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164848$10247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164848$10247_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164850$10249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164850$10249_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164852$10251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164852$10251_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164853$10252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164853$10252_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164855$10254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164855$10254_Y - end - connect \$7 $not$libresoc.v:164840$10239_Y - connect \$12 $reduce_or$libresoc.v:164841$10240_Y - connect \$11 $not$libresoc.v:164842$10241_Y - connect \$16 $reduce_or$libresoc.v:164843$10242_Y - connect \$15 $not$libresoc.v:164844$10243_Y - connect \$1 $not$libresoc.v:164845$10244_Y - connect \$20 $reduce_or$libresoc.v:164846$10245_Y - connect \$19 $not$libresoc.v:164847$10246_Y - connect \$24 $reduce_or$libresoc.v:164848$10247_Y - connect \$23 $not$libresoc.v:164849$10248_Y - connect \$28 $reduce_or$libresoc.v:164850$10249_Y - connect \$27 $not$libresoc.v:164851$10250_Y - connect \$31 $reduce_or$libresoc.v:164852$10251_Y - connect \$4 $reduce_or$libresoc.v:164853$10252_Y - connect \$3 $not$libresoc.v:164854$10253_Y - connect \$8 $reduce_or$libresoc.v:164855$10254_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:164871.1-164955.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$153 - attribute \src "libresoc.v:164928.17-164928.91" - wire $not$libresoc.v:164928$10255_Y - attribute \src "libresoc.v:164930.18-164930.93" - wire $not$libresoc.v:164930$10257_Y - attribute \src "libresoc.v:164932.18-164932.93" - wire $not$libresoc.v:164932$10259_Y - attribute \src "libresoc.v:164933.17-164933.138" - wire width 8 $not$libresoc.v:164933$10260_Y - attribute \src "libresoc.v:164935.18-164935.93" - wire $not$libresoc.v:164935$10262_Y - attribute \src "libresoc.v:164937.18-164937.93" - wire $not$libresoc.v:164937$10264_Y - attribute \src "libresoc.v:164939.18-164939.93" - wire $not$libresoc.v:164939$10266_Y - attribute \src "libresoc.v:164942.17-164942.91" - wire $not$libresoc.v:164942$10269_Y - attribute \src "libresoc.v:164929.18-164929.116" - wire $reduce_or$libresoc.v:164929$10256_Y - attribute \src "libresoc.v:164931.18-164931.122" - wire $reduce_or$libresoc.v:164931$10258_Y - attribute \src "libresoc.v:164934.18-164934.128" - wire $reduce_or$libresoc.v:164934$10261_Y - attribute \src "libresoc.v:164936.18-164936.134" - wire $reduce_or$libresoc.v:164936$10263_Y - attribute \src "libresoc.v:164938.18-164938.140" - wire $reduce_or$libresoc.v:164938$10265_Y - attribute \src "libresoc.v:164940.18-164940.90" - wire $reduce_or$libresoc.v:164940$10267_Y - attribute \src "libresoc.v:164941.17-164941.103" - wire $reduce_or$libresoc.v:164941$10268_Y - attribute \src "libresoc.v:164943.17-164943.109" - wire $reduce_or$libresoc.v:164943$10270_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164928$10255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:164928$10255_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164930$10257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:164930$10257_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164932$10259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:164932$10259_Y + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:164933$10260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:164933$10260_Y + attribute \src "libresoc.v:11382.3-11418.6" + process $proc$libresoc.v:11382$369 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:11383.5-11383.29" + switch \initial + attribute \src "libresoc.v:11383.9-11383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164935$10262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:164935$10262_Y + attribute \src "libresoc.v:11419.3-11455.6" + process $proc$libresoc.v:11419$370 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:11420.5-11420.29" + switch \initial + attribute \src "libresoc.v:11420.9-11420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164937$10264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:164937$10264_Y + attribute \src "libresoc.v:11456.3-11492.6" + process $proc$libresoc.v:11456$371 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:11457.5-11457.29" + switch \initial + attribute \src "libresoc.v:11457.9-11457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164939$10266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:164939$10266_Y + attribute \src "libresoc.v:11493.3-11529.6" + process $proc$libresoc.v:11493$372 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:11494.5-11494.29" + switch \initial + attribute \src "libresoc.v:11494.9-11494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:164942$10269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:164942$10269_Y + attribute \src "libresoc.v:11530.3-11566.6" + process $proc$libresoc.v:11530$373 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:11531.5-11531.29" + switch \initial + attribute \src "libresoc.v:11531.9-11531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164929$10256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:164929$10256_Y + attribute \src "libresoc.v:11567.3-11603.6" + process $proc$libresoc.v:11567$374 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:11568.5-11568.29" + switch \initial + attribute \src "libresoc.v:11568.9-11568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164931$10258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:164931$10258_Y + attribute \src "libresoc.v:11604.3-11640.6" + process $proc$libresoc.v:11604$375 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:11605.5-11605.29" + switch \initial + attribute \src "libresoc.v:11605.9-11605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164934$10261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:164934$10261_Y + attribute \src "libresoc.v:11641.3-11677.6" + process $proc$libresoc.v:11641$376 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:11642.5-11642.29" + switch \initial + attribute \src "libresoc.v:11642.9-11642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164936$10263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:164936$10263_Y + attribute \src "libresoc.v:11678.3-11714.6" + process $proc$libresoc.v:11678$377 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:11679.5-11679.29" + switch \initial + attribute \src "libresoc.v:11679.9-11679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164938$10265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:164938$10265_Y + attribute \src "libresoc.v:11715.3-11751.6" + process $proc$libresoc.v:11715$378 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:11716.5-11716.29" + switch \initial + attribute \src "libresoc.v:11716.9-11716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + case + assign $1\dec30_out_sel[1:0] 2'00 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:164940$10267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:164940$10267_Y + attribute \src "libresoc.v:11752.3-11788.6" + process $proc$libresoc.v:11752$379 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:11753.5-11753.29" + switch \initial + attribute \src "libresoc.v:11753.9-11753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164941$10268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:164941$10268_Y + attribute \src "libresoc.v:11789.3-11825.6" + process $proc$libresoc.v:11789$380 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:11790.5-11790.29" + switch \initial + attribute \src "libresoc.v:11790.9-11790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:164943$10270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:164943$10270_Y - end - connect \$7 $not$libresoc.v:164928$10255_Y - connect \$12 $reduce_or$libresoc.v:164929$10256_Y - connect \$11 $not$libresoc.v:164930$10257_Y - connect \$16 $reduce_or$libresoc.v:164931$10258_Y - connect \$15 $not$libresoc.v:164932$10259_Y - connect \$1 $not$libresoc.v:164933$10260_Y - connect \$20 $reduce_or$libresoc.v:164934$10261_Y - connect \$19 $not$libresoc.v:164935$10262_Y - connect \$24 $reduce_or$libresoc.v:164936$10263_Y - connect \$23 $not$libresoc.v:164937$10264_Y - connect \$28 $reduce_or$libresoc.v:164938$10265_Y - connect \$27 $not$libresoc.v:164939$10266_Y - connect \$31 $reduce_or$libresoc.v:164940$10267_Y - connect \$4 $reduce_or$libresoc.v:164941$10268_Y - connect \$3 $not$libresoc.v:164942$10269_Y - connect \$8 $reduce_or$libresoc.v:164943$10270_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:164959.1-165043.10" +attribute \src "libresoc.v:11831.1-18201.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator 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$reduce_or$libresoc.v:165022$10277_Y - attribute \src "libresoc.v:165024.18-165024.134" - wire $reduce_or$libresoc.v:165024$10279_Y - attribute \src "libresoc.v:165026.18-165026.140" - wire $reduce_or$libresoc.v:165026$10281_Y - attribute \src "libresoc.v:165028.18-165028.90" - wire $reduce_or$libresoc.v:165028$10283_Y - attribute \src "libresoc.v:165029.17-165029.103" - wire $reduce_or$libresoc.v:165029$10284_Y - attribute \src "libresoc.v:165031.17-165031.109" - wire $reduce_or$libresoc.v:165031$10286_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165016$10271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165016$10271_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165018$10273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165018$10273_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165020$10275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165020$10275_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165021$10276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165021$10276_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165023$10278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165023$10278_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165025$10280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165025$10280_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165027$10282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165027$10282_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165030$10285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165030$10285_Y +module \dec31 + attribute \src "libresoc.v:16900.3-16960.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:17754.3-17814.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:17205.3-17265.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:17266.3-17326.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:17510.3-17570.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:17693.3-17753.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:16839.3-16899.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:16717.3-16777.6" + wire width 12 $0\dec31_function_unit[11:0] + attribute \src "libresoc.v:16961.3-17021.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:17022.3-17082.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17083.3-17143.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16778.3-16838.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:17571.3-17631.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:17632.3-17692.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:17937.3-17997.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:17327.3-17387.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:18059.3-18119.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:17144.3-17204.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "libresoc.v:17449.3-17509.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17876.3-17936.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:18120.3-18180.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:17998.3-18058.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:17815.3-17875.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17388.3-17448.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:11832.7-11832.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16900.3-16960.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:17754.3-17814.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:17205.3-17265.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17266.3-17326.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17510.3-17570.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17693.3-17753.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:16839.3-16899.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:16717.3-16777.6" + wire width 12 $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:16961.3-17021.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:17022.3-17082.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17083.3-17143.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:16778.3-16838.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:17571.3-17631.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17632.3-17692.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17937.3-17997.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17327.3-17387.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:18059.3-18119.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:17144.3-17204.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17449.3-17509.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17876.3-17936.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:18120.3-18180.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:17998.3-18058.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:17815.3-17875.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17388.3-17448.6" + wire width 2 $1\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 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\enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_upd + attribute \src "libresoc.v:11832.7-11832.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:16231.18-16257.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165017$10272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165017$10272_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16258.19-16284.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165019$10274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165019$10274_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16285.19-16311.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165022$10277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165022$10277_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16312.19-16338.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165024$10279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165024$10279_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16339.19-16365.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165026$10281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165026$10281_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16366.19-16392.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165028$10283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165028$10283_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16393.19-16419.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165029$10284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165029$10284_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16420.19-16446.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165031$10286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165031$10286_Y - end - connect \$7 $not$libresoc.v:165016$10271_Y - connect \$12 $reduce_or$libresoc.v:165017$10272_Y - connect \$11 $not$libresoc.v:165018$10273_Y - connect \$16 $reduce_or$libresoc.v:165019$10274_Y - connect \$15 $not$libresoc.v:165020$10275_Y - connect \$1 $not$libresoc.v:165021$10276_Y - connect \$20 $reduce_or$libresoc.v:165022$10277_Y - connect \$19 $not$libresoc.v:165023$10278_Y - connect \$24 $reduce_or$libresoc.v:165024$10279_Y - connect \$23 $not$libresoc.v:165025$10280_Y - connect \$28 $reduce_or$libresoc.v:165026$10281_Y - connect \$27 $not$libresoc.v:165027$10282_Y - connect \$31 $reduce_or$libresoc.v:165028$10283_Y - connect \$4 $reduce_or$libresoc.v:165029$10284_Y - connect \$3 $not$libresoc.v:165030$10285_Y - connect \$8 $reduce_or$libresoc.v:165031$10286_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165047.1-165131.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$161 - attribute \src "libresoc.v:165104.17-165104.91" - wire $not$libresoc.v:165104$10287_Y - attribute \src "libresoc.v:165106.18-165106.93" - wire $not$libresoc.v:165106$10289_Y - attribute \src "libresoc.v:165108.18-165108.93" - wire $not$libresoc.v:165108$10291_Y - attribute \src "libresoc.v:165109.17-165109.138" - wire width 8 $not$libresoc.v:165109$10292_Y - attribute \src "libresoc.v:165111.18-165111.93" - wire $not$libresoc.v:165111$10294_Y - attribute \src "libresoc.v:165113.18-165113.93" - wire $not$libresoc.v:165113$10296_Y - attribute \src "libresoc.v:165115.18-165115.93" - wire $not$libresoc.v:165115$10298_Y - attribute \src "libresoc.v:165118.17-165118.91" - wire $not$libresoc.v:165118$10301_Y - attribute \src "libresoc.v:165105.18-165105.116" - wire $reduce_or$libresoc.v:165105$10288_Y - attribute \src "libresoc.v:165107.18-165107.122" - wire $reduce_or$libresoc.v:165107$10290_Y - attribute \src "libresoc.v:165110.18-165110.128" - wire $reduce_or$libresoc.v:165110$10293_Y - attribute \src "libresoc.v:165112.18-165112.134" - wire $reduce_or$libresoc.v:165112$10295_Y - attribute \src "libresoc.v:165114.18-165114.140" - wire $reduce_or$libresoc.v:165114$10297_Y - attribute \src "libresoc.v:165116.18-165116.90" - wire $reduce_or$libresoc.v:165116$10299_Y - attribute \src "libresoc.v:165117.17-165117.103" - wire $reduce_or$libresoc.v:165117$10300_Y - attribute \src "libresoc.v:165119.17-165119.109" - wire $reduce_or$libresoc.v:165119$10302_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165104$10287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165104$10287_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16447.19-16473.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165106$10289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165106$10289_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16474.19-16500.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165108$10291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165108$10291_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16501.19-16527.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165109$10292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165109$10292_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16528.19-16554.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165111$10294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165111$10294_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16555.19-16581.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165113$10296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165113$10296_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16582.19-16608.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165115$10298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165115$10298_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16609.19-16635.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165118$10301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165118$10301_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16636.18-16662.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165105$10288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165105$10288_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16663.18-16689.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165107$10290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165107$10290_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:16690.18-16716.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165110$10293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165110$10293_Y + attribute \src "libresoc.v:11832.7-11832.20" + process $proc$libresoc.v:11832$406 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165112$10295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165112$10295_Y + attribute \src "libresoc.v:16717.3-16777.6" + process $proc$libresoc.v:16717$382 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] + attribute \src "libresoc.v:16718.5-16718.29" + switch \initial + attribute \src "libresoc.v:16718.9-16718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165114$10297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165114$10297_Y + attribute \src "libresoc.v:16778.3-16838.6" + process $proc$libresoc.v:16778$383 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:16779.5-16779.29" + switch \initial + attribute \src "libresoc.v:16779.9-16779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165116$10299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165116$10299_Y + attribute \src "libresoc.v:16839.3-16899.6" + process $proc$libresoc.v:16839$384 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:16840.5-16840.29" + switch \initial + attribute \src "libresoc.v:16840.9-16840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165117$10300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165117$10300_Y + attribute \src "libresoc.v:16900.3-16960.6" + process $proc$libresoc.v:16900$385 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:16901.5-16901.29" + switch \initial + attribute \src "libresoc.v:16901.9-16901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165119$10302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165119$10302_Y - end - connect \$7 $not$libresoc.v:165104$10287_Y - connect \$12 $reduce_or$libresoc.v:165105$10288_Y - connect \$11 $not$libresoc.v:165106$10289_Y - connect \$16 $reduce_or$libresoc.v:165107$10290_Y - connect \$15 $not$libresoc.v:165108$10291_Y - connect \$1 $not$libresoc.v:165109$10292_Y - connect \$20 $reduce_or$libresoc.v:165110$10293_Y - connect \$19 $not$libresoc.v:165111$10294_Y - connect \$24 $reduce_or$libresoc.v:165112$10295_Y - connect \$23 $not$libresoc.v:165113$10296_Y - connect \$28 $reduce_or$libresoc.v:165114$10297_Y - connect \$27 $not$libresoc.v:165115$10298_Y - connect \$31 $reduce_or$libresoc.v:165116$10299_Y - connect \$4 $reduce_or$libresoc.v:165117$10300_Y - connect \$3 $not$libresoc.v:165118$10301_Y - connect \$8 $reduce_or$libresoc.v:165119$10302_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165135.1-165219.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$168 - attribute \src "libresoc.v:165192.17-165192.91" - wire $not$libresoc.v:165192$10303_Y - attribute \src "libresoc.v:165194.18-165194.93" - wire $not$libresoc.v:165194$10305_Y - attribute \src "libresoc.v:165196.18-165196.93" - wire $not$libresoc.v:165196$10307_Y - attribute \src "libresoc.v:165197.17-165197.138" - wire width 8 $not$libresoc.v:165197$10308_Y - attribute \src "libresoc.v:165199.18-165199.93" - wire $not$libresoc.v:165199$10310_Y - attribute \src "libresoc.v:165201.18-165201.93" - wire $not$libresoc.v:165201$10312_Y - attribute \src "libresoc.v:165203.18-165203.93" - wire $not$libresoc.v:165203$10314_Y - attribute \src "libresoc.v:165206.17-165206.91" - wire $not$libresoc.v:165206$10317_Y - attribute \src "libresoc.v:165193.18-165193.116" - wire $reduce_or$libresoc.v:165193$10304_Y - attribute \src "libresoc.v:165195.18-165195.122" - wire $reduce_or$libresoc.v:165195$10306_Y - attribute \src "libresoc.v:165198.18-165198.128" - wire $reduce_or$libresoc.v:165198$10309_Y - attribute \src "libresoc.v:165200.18-165200.134" - wire $reduce_or$libresoc.v:165200$10311_Y - attribute \src "libresoc.v:165202.18-165202.140" - wire $reduce_or$libresoc.v:165202$10313_Y - attribute \src "libresoc.v:165204.18-165204.90" - wire $reduce_or$libresoc.v:165204$10315_Y - attribute \src "libresoc.v:165205.17-165205.103" - wire $reduce_or$libresoc.v:165205$10316_Y - attribute \src "libresoc.v:165207.17-165207.109" - wire $reduce_or$libresoc.v:165207$10318_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165192$10303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165192$10303_Y + attribute \src "libresoc.v:16961.3-17021.6" + process $proc$libresoc.v:16961$386 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:16962.5-16962.29" + switch \initial + attribute \src "libresoc.v:16962.9-16962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165194$10305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165194$10305_Y + attribute \src "libresoc.v:17022.3-17082.6" + process $proc$libresoc.v:17022$387 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:17023.5-17023.29" + switch \initial + attribute \src "libresoc.v:17023.9-17023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165196$10307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165196$10307_Y + attribute \src "libresoc.v:17083.3-17143.6" + process $proc$libresoc.v:17083$388 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:17084.5-17084.29" + switch \initial + attribute \src "libresoc.v:17084.9-17084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165197$10308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165197$10308_Y + attribute \src "libresoc.v:17144.3-17204.6" + process $proc$libresoc.v:17144$389 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:17145.5-17145.29" + switch \initial + attribute \src "libresoc.v:17145.9-17145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165199$10310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165199$10310_Y + attribute \src "libresoc.v:17205.3-17265.6" + process $proc$libresoc.v:17205$390 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:17206.5-17206.29" + switch \initial + attribute \src "libresoc.v:17206.9-17206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165201$10312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165201$10312_Y + attribute \src "libresoc.v:17266.3-17326.6" + process $proc$libresoc.v:17266$391 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:17267.5-17267.29" + switch \initial + attribute \src "libresoc.v:17267.9-17267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165203$10314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165203$10314_Y + attribute \src "libresoc.v:17327.3-17387.6" + process $proc$libresoc.v:17327$392 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:17328.5-17328.29" + switch \initial + attribute \src "libresoc.v:17328.9-17328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165206$10317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165206$10317_Y + attribute \src "libresoc.v:17388.3-17448.6" + process $proc$libresoc.v:17388$393 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:17389.5-17389.29" + switch \initial + attribute \src "libresoc.v:17389.9-17389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165193$10304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165193$10304_Y + attribute \src "libresoc.v:17449.3-17509.6" + process $proc$libresoc.v:17449$394 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:17450.5-17450.29" + switch \initial + attribute \src "libresoc.v:17450.9-17450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165195$10306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165195$10306_Y + attribute \src "libresoc.v:17510.3-17570.6" + process $proc$libresoc.v:17510$395 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:17511.5-17511.29" + switch \initial + attribute \src "libresoc.v:17511.9-17511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165198$10309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165198$10309_Y + attribute \src "libresoc.v:17571.3-17631.6" + process $proc$libresoc.v:17571$396 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:17572.5-17572.29" + switch \initial + attribute \src "libresoc.v:17572.9-17572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165200$10311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165200$10311_Y + attribute \src "libresoc.v:17632.3-17692.6" + process $proc$libresoc.v:17632$397 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:17633.5-17633.29" + switch \initial + attribute \src "libresoc.v:17633.9-17633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165202$10313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165202$10313_Y + attribute \src "libresoc.v:17693.3-17753.6" + process $proc$libresoc.v:17693$398 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:17694.5-17694.29" + switch \initial + attribute \src "libresoc.v:17694.9-17694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165204$10315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165204$10315_Y + attribute \src "libresoc.v:17754.3-17814.6" + process $proc$libresoc.v:17754$399 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:17755.5-17755.29" + switch \initial + attribute \src "libresoc.v:17755.9-17755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165205$10316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165205$10316_Y + attribute \src "libresoc.v:17815.3-17875.6" + process $proc$libresoc.v:17815$400 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:17816.5-17816.29" + switch \initial + attribute \src "libresoc.v:17816.9-17816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165207$10318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165207$10318_Y - end - connect \$7 $not$libresoc.v:165192$10303_Y - connect \$12 $reduce_or$libresoc.v:165193$10304_Y - connect \$11 $not$libresoc.v:165194$10305_Y - connect \$16 $reduce_or$libresoc.v:165195$10306_Y - connect \$15 $not$libresoc.v:165196$10307_Y - connect \$1 $not$libresoc.v:165197$10308_Y - connect \$20 $reduce_or$libresoc.v:165198$10309_Y - connect \$19 $not$libresoc.v:165199$10310_Y - connect \$24 $reduce_or$libresoc.v:165200$10311_Y - connect \$23 $not$libresoc.v:165201$10312_Y - connect \$28 $reduce_or$libresoc.v:165202$10313_Y - connect \$27 $not$libresoc.v:165203$10314_Y - connect \$31 $reduce_or$libresoc.v:165204$10315_Y - connect \$4 $reduce_or$libresoc.v:165205$10316_Y - connect \$3 $not$libresoc.v:165206$10317_Y - connect \$8 $reduce_or$libresoc.v:165207$10318_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165223.1-165307.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$170 - attribute \src "libresoc.v:165280.17-165280.91" - wire $not$libresoc.v:165280$10319_Y - attribute \src "libresoc.v:165282.18-165282.93" - wire $not$libresoc.v:165282$10321_Y - attribute \src "libresoc.v:165284.18-165284.93" - wire $not$libresoc.v:165284$10323_Y - attribute \src "libresoc.v:165285.17-165285.138" - wire width 8 $not$libresoc.v:165285$10324_Y - attribute \src "libresoc.v:165287.18-165287.93" - wire $not$libresoc.v:165287$10326_Y - attribute \src "libresoc.v:165289.18-165289.93" - wire $not$libresoc.v:165289$10328_Y - attribute \src "libresoc.v:165291.18-165291.93" - wire $not$libresoc.v:165291$10330_Y - attribute \src "libresoc.v:165294.17-165294.91" - wire $not$libresoc.v:165294$10333_Y - attribute \src "libresoc.v:165281.18-165281.116" - wire $reduce_or$libresoc.v:165281$10320_Y - attribute \src "libresoc.v:165283.18-165283.122" - wire $reduce_or$libresoc.v:165283$10322_Y - attribute \src "libresoc.v:165286.18-165286.128" - wire $reduce_or$libresoc.v:165286$10325_Y - attribute \src "libresoc.v:165288.18-165288.134" - wire $reduce_or$libresoc.v:165288$10327_Y - attribute \src "libresoc.v:165290.18-165290.140" - wire $reduce_or$libresoc.v:165290$10329_Y - attribute \src "libresoc.v:165292.18-165292.90" - wire $reduce_or$libresoc.v:165292$10331_Y - attribute \src "libresoc.v:165293.17-165293.103" - wire $reduce_or$libresoc.v:165293$10332_Y - attribute \src "libresoc.v:165295.17-165295.109" - wire $reduce_or$libresoc.v:165295$10334_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165280$10319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165280$10319_Y + attribute \src "libresoc.v:17876.3-17936.6" + process $proc$libresoc.v:17876$401 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:17877.5-17877.29" + switch \initial + attribute \src "libresoc.v:17877.9-17877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165282$10321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165282$10321_Y + attribute \src "libresoc.v:17937.3-17997.6" + process $proc$libresoc.v:17937$402 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:17938.5-17938.29" + switch \initial + attribute \src "libresoc.v:17938.9-17938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165284$10323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165284$10323_Y + attribute \src "libresoc.v:17998.3-18058.6" + process $proc$libresoc.v:17998$403 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:17999.5-17999.29" + switch \initial + attribute \src "libresoc.v:17999.9-17999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165285$10324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165285$10324_Y + attribute \src "libresoc.v:18059.3-18119.6" + process $proc$libresoc.v:18059$404 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:18060.5-18060.29" + switch \initial + attribute \src "libresoc.v:18060.9-18060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165287$10326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165287$10326_Y + attribute \src "libresoc.v:18120.3-18180.6" + process $proc$libresoc.v:18120$405 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:18121.5-18121.29" + switch \initial + attribute \src "libresoc.v:18121.9-18121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165289$10328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165289$10328_Y + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:18205.1-18920.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "libresoc.v:18558.3-18576.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18634.3-18652.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18881.3-18899.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18900.3-18918.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18539.3-18557.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18615.3-18633.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18786.3-18804.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18463.3-18481.6" + wire width 12 $0\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18805.3-18823.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18824.3-18842.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18843.3-18861.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18672.3-18690.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18577.3-18595.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18596.3-18614.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18710.3-18728.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18482.3-18500.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18748.3-18766.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18862.3-18880.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18520.3-18538.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18691.3-18709.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18767.3-18785.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18729.3-18747.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18653.3-18671.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18501.3-18519.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18206.7-18206.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18558.3-18576.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18634.3-18652.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18881.3-18899.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18900.3-18918.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18539.3-18557.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18615.3-18633.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18786.3-18804.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18463.3-18481.6" + wire width 12 $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18805.3-18823.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18824.3-18842.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18843.3-18861.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18672.3-18690.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18577.3-18595.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18596.3-18614.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18710.3-18728.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18482.3-18500.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18748.3-18766.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18862.3-18880.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18520.3-18538.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18691.3-18709.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18767.3-18785.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18729.3-18747.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18653.3-18671.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18501.3-18519.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub0_upd + attribute \src "libresoc.v:18206.7-18206.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18206.7-18206.20" + process $proc$libresoc.v:18206$431 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165291$10330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165291$10330_Y + attribute \src "libresoc.v:18463.3-18481.6" + process $proc$libresoc.v:18463$407 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "libresoc.v:18464.5-18464.29" + switch \initial + attribute \src "libresoc.v:18464.9-18464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165294$10333 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165294$10333_Y + attribute \src "libresoc.v:18482.3-18500.6" + process $proc$libresoc.v:18482$408 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:18483.5-18483.29" + switch \initial + attribute \src "libresoc.v:18483.9-18483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165281$10320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165281$10320_Y + attribute \src "libresoc.v:18501.3-18519.6" + process $proc$libresoc.v:18501$409 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:18502.5-18502.29" + switch \initial + attribute \src "libresoc.v:18502.9-18502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165283$10322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165283$10322_Y + attribute \src "libresoc.v:18520.3-18538.6" + process $proc$libresoc.v:18520$410 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:18521.5-18521.29" + switch \initial + attribute \src "libresoc.v:18521.9-18521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165286$10325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165286$10325_Y + attribute \src "libresoc.v:18539.3-18557.6" + process $proc$libresoc.v:18539$411 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:18540.5-18540.29" + switch \initial + attribute \src "libresoc.v:18540.9-18540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165288$10327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165288$10327_Y + attribute \src "libresoc.v:18558.3-18576.6" + process $proc$libresoc.v:18558$412 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:18559.5-18559.29" + switch \initial + attribute \src "libresoc.v:18559.9-18559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165290$10329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165290$10329_Y + attribute \src "libresoc.v:18577.3-18595.6" + process $proc$libresoc.v:18577$413 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:18578.5-18578.29" + switch \initial + attribute \src "libresoc.v:18578.9-18578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165292$10331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165292$10331_Y + attribute \src "libresoc.v:18596.3-18614.6" + process $proc$libresoc.v:18596$414 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:18597.5-18597.29" + switch \initial + attribute \src "libresoc.v:18597.9-18597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165293$10332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165293$10332_Y + attribute \src "libresoc.v:18615.3-18633.6" + process $proc$libresoc.v:18615$415 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:18616.5-18616.29" + switch \initial + attribute \src "libresoc.v:18616.9-18616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165295$10334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165295$10334_Y - end - connect \$7 $not$libresoc.v:165280$10319_Y - connect \$12 $reduce_or$libresoc.v:165281$10320_Y - connect \$11 $not$libresoc.v:165282$10321_Y - connect \$16 $reduce_or$libresoc.v:165283$10322_Y - connect \$15 $not$libresoc.v:165284$10323_Y - connect \$1 $not$libresoc.v:165285$10324_Y - connect \$20 $reduce_or$libresoc.v:165286$10325_Y - connect \$19 $not$libresoc.v:165287$10326_Y - connect \$24 $reduce_or$libresoc.v:165288$10327_Y - connect \$23 $not$libresoc.v:165289$10328_Y - connect \$28 $reduce_or$libresoc.v:165290$10329_Y - connect \$27 $not$libresoc.v:165291$10330_Y - connect \$31 $reduce_or$libresoc.v:165292$10331_Y - connect \$4 $reduce_or$libresoc.v:165293$10332_Y - connect \$3 $not$libresoc.v:165294$10333_Y - connect \$8 $reduce_or$libresoc.v:165295$10334_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165311.1-165395.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$175 - attribute \src "libresoc.v:165368.17-165368.91" - wire $not$libresoc.v:165368$10335_Y - attribute \src "libresoc.v:165370.18-165370.93" - wire $not$libresoc.v:165370$10337_Y - attribute \src "libresoc.v:165372.18-165372.93" - wire $not$libresoc.v:165372$10339_Y - attribute \src "libresoc.v:165373.17-165373.138" - wire width 8 $not$libresoc.v:165373$10340_Y - attribute \src "libresoc.v:165375.18-165375.93" - wire $not$libresoc.v:165375$10342_Y - attribute \src "libresoc.v:165377.18-165377.93" - wire $not$libresoc.v:165377$10344_Y - attribute \src "libresoc.v:165379.18-165379.93" - wire $not$libresoc.v:165379$10346_Y - attribute \src "libresoc.v:165382.17-165382.91" - wire $not$libresoc.v:165382$10349_Y - attribute \src "libresoc.v:165369.18-165369.116" - wire $reduce_or$libresoc.v:165369$10336_Y - attribute \src "libresoc.v:165371.18-165371.122" - wire $reduce_or$libresoc.v:165371$10338_Y - attribute \src "libresoc.v:165374.18-165374.128" - wire $reduce_or$libresoc.v:165374$10341_Y - attribute \src "libresoc.v:165376.18-165376.134" - wire $reduce_or$libresoc.v:165376$10343_Y - attribute \src "libresoc.v:165378.18-165378.140" - wire $reduce_or$libresoc.v:165378$10345_Y - attribute \src "libresoc.v:165380.18-165380.90" - wire $reduce_or$libresoc.v:165380$10347_Y - attribute \src "libresoc.v:165381.17-165381.103" - wire $reduce_or$libresoc.v:165381$10348_Y - attribute \src "libresoc.v:165383.17-165383.109" - wire $reduce_or$libresoc.v:165383$10350_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165368$10335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165368$10335_Y + attribute \src "libresoc.v:18634.3-18652.6" + process $proc$libresoc.v:18634$416 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:18635.5-18635.29" + switch \initial + attribute \src "libresoc.v:18635.9-18635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165370$10337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165370$10337_Y + attribute \src "libresoc.v:18653.3-18671.6" + process $proc$libresoc.v:18653$417 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:18654.5-18654.29" + switch \initial + attribute \src "libresoc.v:18654.9-18654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165372$10339 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165372$10339_Y + attribute \src "libresoc.v:18672.3-18690.6" + process $proc$libresoc.v:18672$418 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:18673.5-18673.29" + switch \initial + attribute \src "libresoc.v:18673.9-18673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165373$10340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165373$10340_Y + attribute \src "libresoc.v:18691.3-18709.6" + process $proc$libresoc.v:18691$419 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:18692.5-18692.29" + switch \initial + attribute \src "libresoc.v:18692.9-18692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165375$10342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165375$10342_Y + attribute \src "libresoc.v:18710.3-18728.6" + process $proc$libresoc.v:18710$420 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:18711.5-18711.29" + switch \initial + attribute \src "libresoc.v:18711.9-18711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165377$10344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165377$10344_Y + attribute \src "libresoc.v:18729.3-18747.6" + process $proc$libresoc.v:18729$421 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:18730.5-18730.29" + switch \initial + attribute \src "libresoc.v:18730.9-18730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165379$10346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165379$10346_Y + attribute \src "libresoc.v:18748.3-18766.6" + process $proc$libresoc.v:18748$422 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:18749.5-18749.29" + switch \initial + attribute \src "libresoc.v:18749.9-18749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165382$10349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165382$10349_Y + attribute \src "libresoc.v:18767.3-18785.6" + process $proc$libresoc.v:18767$423 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:18768.5-18768.29" + switch \initial + attribute \src "libresoc.v:18768.9-18768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165369$10336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165369$10336_Y + attribute \src "libresoc.v:18786.3-18804.6" + process $proc$libresoc.v:18786$424 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:18787.5-18787.29" + switch \initial + attribute \src "libresoc.v:18787.9-18787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165371$10338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165371$10338_Y + attribute \src "libresoc.v:18805.3-18823.6" + process $proc$libresoc.v:18805$425 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:18806.5-18806.29" + switch \initial + attribute \src "libresoc.v:18806.9-18806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165374$10341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165374$10341_Y + attribute \src "libresoc.v:18824.3-18842.6" + process $proc$libresoc.v:18824$426 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:18825.5-18825.29" + switch \initial + attribute \src "libresoc.v:18825.9-18825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165376$10343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165376$10343_Y + attribute \src "libresoc.v:18843.3-18861.6" + process $proc$libresoc.v:18843$427 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:18844.5-18844.29" + switch \initial + attribute \src "libresoc.v:18844.9-18844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165378$10345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165378$10345_Y + attribute \src "libresoc.v:18862.3-18880.6" + process $proc$libresoc.v:18862$428 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:18863.5-18863.29" + switch \initial + attribute \src "libresoc.v:18863.9-18863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165380$10347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165380$10347_Y + attribute \src "libresoc.v:18881.3-18899.6" + process $proc$libresoc.v:18881$429 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:18882.5-18882.29" + switch \initial + attribute \src "libresoc.v:18882.9-18882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165381$10348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165381$10348_Y + attribute \src "libresoc.v:18900.3-18918.6" + process $proc$libresoc.v:18900$430 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:18901.5-18901.29" + switch \initial + attribute \src "libresoc.v:18901.9-18901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165383$10350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165383$10350_Y - end - connect \$7 $not$libresoc.v:165368$10335_Y - connect \$12 $reduce_or$libresoc.v:165369$10336_Y - connect \$11 $not$libresoc.v:165370$10337_Y - connect \$16 $reduce_or$libresoc.v:165371$10338_Y - connect \$15 $not$libresoc.v:165372$10339_Y - connect \$1 $not$libresoc.v:165373$10340_Y - connect \$20 $reduce_or$libresoc.v:165374$10341_Y - connect \$19 $not$libresoc.v:165375$10342_Y - connect \$24 $reduce_or$libresoc.v:165376$10343_Y - connect \$23 $not$libresoc.v:165377$10344_Y - connect \$28 $reduce_or$libresoc.v:165378$10345_Y - connect \$27 $not$libresoc.v:165379$10346_Y - connect \$31 $reduce_or$libresoc.v:165380$10347_Y - connect \$4 $reduce_or$libresoc.v:165381$10348_Y - connect \$3 $not$libresoc.v:165382$10349_Y - connect \$8 $reduce_or$libresoc.v:165383$10350_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:165399.1-165483.10" +attribute \src "libresoc.v:18924.1-20071.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" -module \ppick$177 - attribute \src "libresoc.v:165456.17-165456.91" - wire $not$libresoc.v:165456$10351_Y - attribute \src "libresoc.v:165458.18-165458.93" - wire $not$libresoc.v:165458$10353_Y - attribute \src "libresoc.v:165460.18-165460.93" - wire $not$libresoc.v:165460$10355_Y - attribute \src "libresoc.v:165461.17-165461.138" - wire width 8 $not$libresoc.v:165461$10356_Y - attribute \src "libresoc.v:165463.18-165463.93" - wire $not$libresoc.v:165463$10358_Y - attribute \src "libresoc.v:165465.18-165465.93" - wire $not$libresoc.v:165465$10360_Y - attribute \src "libresoc.v:165467.18-165467.93" - wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165456$10351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165456$10351_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165458$10353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165458$10353_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165460$10355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165460$10355_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165461$10356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165461$10356_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165463$10358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165463$10358_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165465$10360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165465$10360_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165467$10362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165467$10362_Y +module \dec31_dec_sub10 + attribute \src "libresoc.v:19367.3-19403.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19515.3-19551.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19996.3-20032.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:20033.3-20069.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19330.3-19366.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19478.3-19514.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19811.3-19847.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19182.3-19218.6" + wire width 12 $0\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19848.3-19884.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19885.3-19921.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19922.3-19958.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19589.3-19625.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19404.3-19440.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19441.3-19477.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19663.3-19699.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19219.3-19255.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19737.3-19773.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19959.3-19995.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19293.3-19329.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19626.3-19662.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19774.3-19810.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19700.3-19736.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19552.3-19588.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19256.3-19292.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:18925.7-18925.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19367.3-19403.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19515.3-19551.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19996.3-20032.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:20033.3-20069.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:19330.3-19366.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19478.3-19514.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19811.3-19847.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19182.3-19218.6" + wire width 12 $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19848.3-19884.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19885.3-19921.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19922.3-19958.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19589.3-19625.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19404.3-19440.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19441.3-19477.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19663.3-19699.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19219.3-19255.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19737.3-19773.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19959.3-19995.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19293.3-19329.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19626.3-19662.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19774.3-19810.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19700.3-19736.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19552.3-19588.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19256.3-19292.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub10_upd + attribute \src "libresoc.v:18925.7-18925.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18925.7-18925.20" + process $proc$libresoc.v:18925$456 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165470$10365 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165470$10365_Y + attribute \src "libresoc.v:19182.3-19218.6" + process $proc$libresoc.v:19182$432 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "libresoc.v:19183.5-19183.29" + switch \initial + attribute \src "libresoc.v:19183.9-19183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165457$10352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165457$10352_Y + attribute \src "libresoc.v:19219.3-19255.6" + process $proc$libresoc.v:19219$433 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:19220.5-19220.29" + switch \initial + attribute \src "libresoc.v:19220.9-19220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165459$10354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165459$10354_Y + attribute \src "libresoc.v:19256.3-19292.6" + process $proc$libresoc.v:19256$434 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:19257.5-19257.29" + switch \initial + attribute \src "libresoc.v:19257.9-19257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165462$10357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165462$10357_Y + attribute \src "libresoc.v:19293.3-19329.6" + process $proc$libresoc.v:19293$435 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:19294.5-19294.29" + switch \initial + attribute \src "libresoc.v:19294.9-19294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165464$10359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165464$10359_Y + attribute \src "libresoc.v:19330.3-19366.6" + process $proc$libresoc.v:19330$436 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:19331.5-19331.29" + switch \initial + attribute \src "libresoc.v:19331.9-19331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165466$10361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165466$10361_Y + attribute \src "libresoc.v:19367.3-19403.6" + process $proc$libresoc.v:19367$437 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:19368.5-19368.29" + switch \initial + attribute \src "libresoc.v:19368.9-19368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165468$10363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165468$10363_Y + attribute \src "libresoc.v:19404.3-19440.6" + process $proc$libresoc.v:19404$438 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:19405.5-19405.29" + switch \initial + attribute \src "libresoc.v:19405.9-19405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165469$10364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165469$10364_Y + attribute \src "libresoc.v:19441.3-19477.6" + process $proc$libresoc.v:19441$439 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:19442.5-19442.29" + switch \initial + attribute \src "libresoc.v:19442.9-19442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165471$10366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165471$10366_Y - end - connect \$7 $not$libresoc.v:165456$10351_Y - connect \$12 $reduce_or$libresoc.v:165457$10352_Y - connect \$11 $not$libresoc.v:165458$10353_Y - connect \$16 $reduce_or$libresoc.v:165459$10354_Y - connect \$15 $not$libresoc.v:165460$10355_Y - connect \$1 $not$libresoc.v:165461$10356_Y - connect \$20 $reduce_or$libresoc.v:165462$10357_Y - connect \$19 $not$libresoc.v:165463$10358_Y - connect \$24 $reduce_or$libresoc.v:165464$10359_Y - connect \$23 $not$libresoc.v:165465$10360_Y - connect \$28 $reduce_or$libresoc.v:165466$10361_Y - connect \$27 $not$libresoc.v:165467$10362_Y - connect \$31 $reduce_or$libresoc.v:165468$10363_Y - connect \$4 $reduce_or$libresoc.v:165469$10364_Y - connect \$3 $not$libresoc.v:165470$10365_Y - connect \$8 $reduce_or$libresoc.v:165471$10366_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165487.1-165571.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$184 - attribute \src "libresoc.v:165544.17-165544.91" - wire $not$libresoc.v:165544$10367_Y - attribute \src "libresoc.v:165546.18-165546.93" - wire $not$libresoc.v:165546$10369_Y - attribute \src "libresoc.v:165548.18-165548.93" - wire $not$libresoc.v:165548$10371_Y - attribute \src "libresoc.v:165549.17-165549.138" - wire width 8 $not$libresoc.v:165549$10372_Y - attribute \src "libresoc.v:165551.18-165551.93" - wire $not$libresoc.v:165551$10374_Y - attribute \src "libresoc.v:165553.18-165553.93" - wire $not$libresoc.v:165553$10376_Y - attribute \src "libresoc.v:165555.18-165555.93" - wire $not$libresoc.v:165555$10378_Y - attribute \src "libresoc.v:165558.17-165558.91" - wire $not$libresoc.v:165558$10381_Y - attribute \src "libresoc.v:165545.18-165545.116" - wire $reduce_or$libresoc.v:165545$10368_Y - attribute \src "libresoc.v:165547.18-165547.122" - wire $reduce_or$libresoc.v:165547$10370_Y - attribute \src "libresoc.v:165550.18-165550.128" - wire $reduce_or$libresoc.v:165550$10373_Y - attribute \src "libresoc.v:165552.18-165552.134" - wire $reduce_or$libresoc.v:165552$10375_Y - attribute \src "libresoc.v:165554.18-165554.140" - wire $reduce_or$libresoc.v:165554$10377_Y - attribute \src "libresoc.v:165556.18-165556.90" - wire $reduce_or$libresoc.v:165556$10379_Y - attribute \src "libresoc.v:165557.17-165557.103" - wire $reduce_or$libresoc.v:165557$10380_Y - attribute \src "libresoc.v:165559.17-165559.109" - wire $reduce_or$libresoc.v:165559$10382_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165544$10367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165544$10367_Y + attribute \src "libresoc.v:19478.3-19514.6" + process $proc$libresoc.v:19478$440 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:19479.5-19479.29" + switch \initial + attribute \src "libresoc.v:19479.9-19479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165546$10369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165546$10369_Y + attribute \src "libresoc.v:19515.3-19551.6" + process $proc$libresoc.v:19515$441 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:19516.5-19516.29" + switch \initial + attribute \src "libresoc.v:19516.9-19516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165548$10371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165548$10371_Y + attribute \src "libresoc.v:19552.3-19588.6" + process $proc$libresoc.v:19552$442 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:19553.5-19553.29" + switch \initial + attribute \src "libresoc.v:19553.9-19553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165549$10372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165549$10372_Y + attribute \src "libresoc.v:19589.3-19625.6" + process $proc$libresoc.v:19589$443 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:19590.5-19590.29" + switch \initial + attribute \src "libresoc.v:19590.9-19590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165551$10374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165551$10374_Y + attribute \src "libresoc.v:19626.3-19662.6" + process $proc$libresoc.v:19626$444 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:19627.5-19627.29" + switch \initial + attribute \src "libresoc.v:19627.9-19627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165553$10376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165553$10376_Y + attribute \src "libresoc.v:19663.3-19699.6" + process $proc$libresoc.v:19663$445 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:19664.5-19664.29" + switch \initial + attribute \src "libresoc.v:19664.9-19664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165555$10378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165555$10378_Y + attribute \src "libresoc.v:19700.3-19736.6" + process $proc$libresoc.v:19700$446 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:19701.5-19701.29" + switch \initial + attribute \src "libresoc.v:19701.9-19701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165558$10381 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165558$10381_Y + attribute \src "libresoc.v:19737.3-19773.6" + process $proc$libresoc.v:19737$447 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:19738.5-19738.29" + switch \initial + attribute \src "libresoc.v:19738.9-19738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165545$10368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165545$10368_Y + attribute \src "libresoc.v:19774.3-19810.6" + process $proc$libresoc.v:19774$448 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:19775.5-19775.29" + switch \initial + attribute \src "libresoc.v:19775.9-19775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165547$10370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165547$10370_Y + attribute \src "libresoc.v:19811.3-19847.6" + process $proc$libresoc.v:19811$449 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:19812.5-19812.29" + switch \initial + attribute \src "libresoc.v:19812.9-19812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165550$10373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165550$10373_Y + attribute \src "libresoc.v:19848.3-19884.6" + process $proc$libresoc.v:19848$450 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:19849.5-19849.29" + switch \initial + attribute \src "libresoc.v:19849.9-19849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165552$10375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165552$10375_Y + attribute \src "libresoc.v:19885.3-19921.6" + process $proc$libresoc.v:19885$451 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:19886.5-19886.29" + switch \initial + attribute \src "libresoc.v:19886.9-19886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165554$10377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165554$10377_Y + attribute \src "libresoc.v:19922.3-19958.6" + process $proc$libresoc.v:19922$452 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:19923.5-19923.29" + switch \initial + attribute \src "libresoc.v:19923.9-19923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165556$10379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165556$10379_Y + attribute \src "libresoc.v:19959.3-19995.6" + process $proc$libresoc.v:19959$453 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:19960.5-19960.29" + switch \initial + attribute \src "libresoc.v:19960.9-19960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165557$10380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165557$10380_Y + attribute \src "libresoc.v:19996.3-20032.6" + process $proc$libresoc.v:19996$454 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:19997.5-19997.29" + switch \initial + attribute \src "libresoc.v:19997.9-19997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165559$10382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165559$10382_Y - end - connect \$7 $not$libresoc.v:165544$10367_Y - connect \$12 $reduce_or$libresoc.v:165545$10368_Y - connect \$11 $not$libresoc.v:165546$10369_Y - connect \$16 $reduce_or$libresoc.v:165547$10370_Y - connect \$15 $not$libresoc.v:165548$10371_Y - connect \$1 $not$libresoc.v:165549$10372_Y - connect \$20 $reduce_or$libresoc.v:165550$10373_Y - connect \$19 $not$libresoc.v:165551$10374_Y - connect \$24 $reduce_or$libresoc.v:165552$10375_Y - connect \$23 $not$libresoc.v:165553$10376_Y - connect \$28 $reduce_or$libresoc.v:165554$10377_Y - connect \$27 $not$libresoc.v:165555$10378_Y - connect \$31 $reduce_or$libresoc.v:165556$10379_Y - connect \$4 $reduce_or$libresoc.v:165557$10380_Y - connect \$3 $not$libresoc.v:165558$10381_Y - connect \$8 $reduce_or$libresoc.v:165559$10382_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + attribute \src "libresoc.v:20033.3-20069.6" + process $proc$libresoc.v:20033$455 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:20034.5-20034.29" + switch \initial + attribute \src "libresoc.v:20034.9-20034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:165575.1-165659.10" +attribute \src "libresoc.v:20075.1-21654.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" -module \ppick$186 - attribute \src "libresoc.v:165632.17-165632.91" - wire $not$libresoc.v:165632$10383_Y - attribute \src "libresoc.v:165634.18-165634.93" - wire $not$libresoc.v:165634$10385_Y - attribute \src "libresoc.v:165636.18-165636.93" - wire $not$libresoc.v:165636$10387_Y - attribute \src "libresoc.v:165637.17-165637.138" - wire width 8 $not$libresoc.v:165637$10388_Y - attribute \src "libresoc.v:165639.18-165639.93" - wire $not$libresoc.v:165639$10390_Y - attribute \src "libresoc.v:165641.18-165641.93" - wire $not$libresoc.v:165641$10392_Y - attribute \src "libresoc.v:165643.18-165643.93" - wire $not$libresoc.v:165643$10394_Y - attribute \src "libresoc.v:165646.17-165646.91" - wire $not$libresoc.v:165646$10397_Y - attribute \src "libresoc.v:165633.18-165633.116" - wire $reduce_or$libresoc.v:165633$10384_Y - attribute \src "libresoc.v:165635.18-165635.122" - wire $reduce_or$libresoc.v:165635$10386_Y - attribute \src "libresoc.v:165638.18-165638.128" - wire $reduce_or$libresoc.v:165638$10389_Y - attribute \src "libresoc.v:165640.18-165640.134" - wire $reduce_or$libresoc.v:165640$10391_Y - attribute \src "libresoc.v:165642.18-165642.140" - wire $reduce_or$libresoc.v:165642$10393_Y - attribute \src "libresoc.v:165644.18-165644.90" - wire $reduce_or$libresoc.v:165644$10395_Y - attribute \src "libresoc.v:165645.17-165645.103" - wire $reduce_or$libresoc.v:165645$10396_Y - attribute \src "libresoc.v:165647.17-165647.109" - wire $reduce_or$libresoc.v:165647$10398_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165632$10383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165632$10383_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165634$10385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165634$10385_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165636$10387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165636$10387_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165637$10388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165637$10388_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165639$10390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165639$10390_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165641$10392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165641$10392_Y +module \dec31_dec_sub11 + attribute \src "libresoc.v:20608.3-20662.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20828.3-20882.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21543.3-21597.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21598.3-21652.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20553.3-20607.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20773.3-20827.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21268.3-21322.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20333.3-20387.6" + wire width 12 $0\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21323.3-21377.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21378.3-21432.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21433.3-21487.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20938.3-20992.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20663.3-20717.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20718.3-20772.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:21048.3-21102.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20388.3-20442.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21158.3-21212.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21488.3-21542.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20498.3-20552.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20993.3-21047.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21213.3-21267.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21103.3-21157.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20883.3-20937.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20443.3-20497.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:20076.7-20076.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20608.3-20662.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20828.3-20882.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:21543.3-21597.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21598.3-21652.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:20553.3-20607.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20773.3-20827.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:21268.3-21322.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:20333.3-20387.6" + wire width 12 $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:21323.3-21377.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21378.3-21432.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21433.3-21487.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:20938.3-20992.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20663.3-20717.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20718.3-20772.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:21048.3-21102.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:20388.3-20442.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:21158.3-21212.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21488.3-21542.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:20498.3-20552.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20993.3-21047.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:21213.3-21267.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21103.3-21157.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:20883.3-20937.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20443.3-20497.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub11_upd + attribute \src "libresoc.v:20076.7-20076.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:20076.7-20076.20" + process $proc$libresoc.v:20076$481 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165643$10394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165643$10394_Y + attribute \src "libresoc.v:20333.3-20387.6" + process $proc$libresoc.v:20333$457 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "libresoc.v:20334.5-20334.29" + switch \initial + attribute \src "libresoc.v:20334.9-20334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165646$10397 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165646$10397_Y + attribute \src "libresoc.v:20388.3-20442.6" + process $proc$libresoc.v:20388$458 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:20389.5-20389.29" + switch \initial + attribute \src "libresoc.v:20389.9-20389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165633$10384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165633$10384_Y + attribute \src "libresoc.v:20443.3-20497.6" + process $proc$libresoc.v:20443$459 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:20444.5-20444.29" + switch \initial + attribute \src "libresoc.v:20444.9-20444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165635$10386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165635$10386_Y + attribute \src "libresoc.v:20498.3-20552.6" + process $proc$libresoc.v:20498$460 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:20499.5-20499.29" + switch \initial + attribute \src "libresoc.v:20499.9-20499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165638$10389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165638$10389_Y + attribute \src "libresoc.v:20553.3-20607.6" + process $proc$libresoc.v:20553$461 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:20554.5-20554.29" + switch \initial + attribute \src "libresoc.v:20554.9-20554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165640$10391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165640$10391_Y + attribute \src "libresoc.v:20608.3-20662.6" + process $proc$libresoc.v:20608$462 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:20609.5-20609.29" + switch \initial + attribute \src "libresoc.v:20609.9-20609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165642$10393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165642$10393_Y + attribute \src "libresoc.v:20663.3-20717.6" + process $proc$libresoc.v:20663$463 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:20664.5-20664.29" + switch \initial + attribute \src "libresoc.v:20664.9-20664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165644$10395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165644$10395_Y + attribute \src "libresoc.v:20718.3-20772.6" + process $proc$libresoc.v:20718$464 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:20719.5-20719.29" + switch \initial + attribute \src "libresoc.v:20719.9-20719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165645$10396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165645$10396_Y + attribute \src "libresoc.v:20773.3-20827.6" + process $proc$libresoc.v:20773$465 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:20774.5-20774.29" + switch \initial + attribute \src "libresoc.v:20774.9-20774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165647$10398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165647$10398_Y - end - connect \$7 $not$libresoc.v:165632$10383_Y - connect \$12 $reduce_or$libresoc.v:165633$10384_Y - connect \$11 $not$libresoc.v:165634$10385_Y - connect \$16 $reduce_or$libresoc.v:165635$10386_Y - connect \$15 $not$libresoc.v:165636$10387_Y - connect \$1 $not$libresoc.v:165637$10388_Y - connect \$20 $reduce_or$libresoc.v:165638$10389_Y - connect \$19 $not$libresoc.v:165639$10390_Y - connect \$24 $reduce_or$libresoc.v:165640$10391_Y - connect \$23 $not$libresoc.v:165641$10392_Y - connect \$28 $reduce_or$libresoc.v:165642$10393_Y - connect \$27 $not$libresoc.v:165643$10394_Y - connect \$31 $reduce_or$libresoc.v:165644$10395_Y - connect \$4 $reduce_or$libresoc.v:165645$10396_Y - connect \$3 $not$libresoc.v:165646$10397_Y - connect \$8 $reduce_or$libresoc.v:165647$10398_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165663.1-165747.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$192 - attribute \src "libresoc.v:165720.17-165720.91" - wire $not$libresoc.v:165720$10399_Y - attribute \src "libresoc.v:165722.18-165722.93" - wire $not$libresoc.v:165722$10401_Y - attribute \src "libresoc.v:165724.18-165724.93" - wire $not$libresoc.v:165724$10403_Y - attribute \src "libresoc.v:165725.17-165725.138" - wire width 8 $not$libresoc.v:165725$10404_Y - attribute \src "libresoc.v:165727.18-165727.93" - wire $not$libresoc.v:165727$10406_Y - attribute \src "libresoc.v:165729.18-165729.93" - wire $not$libresoc.v:165729$10408_Y - attribute \src "libresoc.v:165731.18-165731.93" - wire $not$libresoc.v:165731$10410_Y - attribute \src "libresoc.v:165734.17-165734.91" - wire $not$libresoc.v:165734$10413_Y - attribute \src "libresoc.v:165721.18-165721.116" - wire $reduce_or$libresoc.v:165721$10400_Y - attribute \src "libresoc.v:165723.18-165723.122" - wire $reduce_or$libresoc.v:165723$10402_Y - attribute \src "libresoc.v:165726.18-165726.128" - wire $reduce_or$libresoc.v:165726$10405_Y - attribute \src "libresoc.v:165728.18-165728.134" - wire $reduce_or$libresoc.v:165728$10407_Y - attribute \src "libresoc.v:165730.18-165730.140" - wire $reduce_or$libresoc.v:165730$10409_Y - attribute \src "libresoc.v:165732.18-165732.90" - wire $reduce_or$libresoc.v:165732$10411_Y - attribute \src "libresoc.v:165733.17-165733.103" - wire $reduce_or$libresoc.v:165733$10412_Y - attribute \src "libresoc.v:165735.17-165735.109" - wire $reduce_or$libresoc.v:165735$10414_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165720$10399 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165720$10399_Y + attribute \src "libresoc.v:20828.3-20882.6" + process $proc$libresoc.v:20828$466 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:20829.5-20829.29" + switch \initial + attribute \src "libresoc.v:20829.9-20829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165722$10401 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165722$10401_Y + attribute \src "libresoc.v:20883.3-20937.6" + process $proc$libresoc.v:20883$467 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:20884.5-20884.29" + switch \initial + attribute \src "libresoc.v:20884.9-20884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165724$10403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165724$10403_Y + attribute \src "libresoc.v:20938.3-20992.6" + process $proc$libresoc.v:20938$468 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:20939.5-20939.29" + switch \initial + attribute \src "libresoc.v:20939.9-20939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165725$10404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165725$10404_Y + attribute \src "libresoc.v:20993.3-21047.6" + process $proc$libresoc.v:20993$469 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:20994.5-20994.29" + switch \initial + attribute \src "libresoc.v:20994.9-20994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165727$10406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165727$10406_Y + attribute \src "libresoc.v:21048.3-21102.6" + process $proc$libresoc.v:21048$470 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:21049.5-21049.29" + switch \initial + attribute \src "libresoc.v:21049.9-21049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165729$10408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165729$10408_Y + attribute \src "libresoc.v:21103.3-21157.6" + process $proc$libresoc.v:21103$471 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:21104.5-21104.29" + switch \initial + attribute \src "libresoc.v:21104.9-21104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165731$10410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165731$10410_Y + attribute \src "libresoc.v:21158.3-21212.6" + process $proc$libresoc.v:21158$472 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:21159.5-21159.29" + switch \initial + attribute \src "libresoc.v:21159.9-21159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165734$10413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165734$10413_Y + attribute \src "libresoc.v:21213.3-21267.6" + process $proc$libresoc.v:21213$473 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:21214.5-21214.29" + switch \initial + attribute \src "libresoc.v:21214.9-21214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165721$10400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165721$10400_Y + attribute \src "libresoc.v:21268.3-21322.6" + process $proc$libresoc.v:21268$474 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:21269.5-21269.29" + switch \initial + attribute \src "libresoc.v:21269.9-21269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165723$10402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165723$10402_Y + attribute \src "libresoc.v:21323.3-21377.6" + process $proc$libresoc.v:21323$475 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:21324.5-21324.29" + switch \initial + attribute \src "libresoc.v:21324.9-21324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165726$10405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165726$10405_Y + attribute \src "libresoc.v:21378.3-21432.6" + process $proc$libresoc.v:21378$476 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:21379.5-21379.29" + switch \initial + attribute \src "libresoc.v:21379.9-21379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165728$10407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165728$10407_Y + attribute \src "libresoc.v:21433.3-21487.6" + process $proc$libresoc.v:21433$477 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:21434.5-21434.29" + switch \initial + attribute \src "libresoc.v:21434.9-21434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165730$10409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165730$10409_Y + attribute \src "libresoc.v:21488.3-21542.6" + process $proc$libresoc.v:21488$478 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:21489.5-21489.29" + switch \initial + attribute \src "libresoc.v:21489.9-21489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165732$10411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165732$10411_Y + attribute \src "libresoc.v:21543.3-21597.6" + process $proc$libresoc.v:21543$479 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:21544.5-21544.29" + switch \initial + attribute \src "libresoc.v:21544.9-21544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165733$10412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165733$10412_Y + attribute \src "libresoc.v:21598.3-21652.6" + process $proc$libresoc.v:21598$480 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:21599.5-21599.29" + switch \initial + attribute \src "libresoc.v:21599.9-21599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165735$10414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165735$10414_Y - end - connect \$7 $not$libresoc.v:165720$10399_Y - connect \$12 $reduce_or$libresoc.v:165721$10400_Y - connect \$11 $not$libresoc.v:165722$10401_Y - connect \$16 $reduce_or$libresoc.v:165723$10402_Y - connect \$15 $not$libresoc.v:165724$10403_Y - connect \$1 $not$libresoc.v:165725$10404_Y - connect \$20 $reduce_or$libresoc.v:165726$10405_Y - connect \$19 $not$libresoc.v:165727$10406_Y - connect \$24 $reduce_or$libresoc.v:165728$10407_Y - connect \$23 $not$libresoc.v:165729$10408_Y - connect \$28 $reduce_or$libresoc.v:165730$10409_Y - connect \$27 $not$libresoc.v:165731$10410_Y - connect \$31 $reduce_or$libresoc.v:165732$10411_Y - connect \$4 $reduce_or$libresoc.v:165733$10412_Y - connect \$3 $not$libresoc.v:165734$10413_Y - connect \$8 $reduce_or$libresoc.v:165735$10414_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:165751.1-165835.10" +attribute \src "libresoc.v:21658.1-24389.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" -module \ppick$194 - attribute \src "libresoc.v:165808.17-165808.91" - wire $not$libresoc.v:165808$10415_Y - attribute \src "libresoc.v:165810.18-165810.93" - wire $not$libresoc.v:165810$10417_Y - attribute \src "libresoc.v:165812.18-165812.93" - wire $not$libresoc.v:165812$10419_Y - attribute \src "libresoc.v:165813.17-165813.138" - wire width 8 $not$libresoc.v:165813$10420_Y - attribute \src "libresoc.v:165815.18-165815.93" - wire $not$libresoc.v:165815$10422_Y - attribute \src "libresoc.v:165817.18-165817.93" - wire $not$libresoc.v:165817$10424_Y - attribute \src "libresoc.v:165819.18-165819.93" - wire $not$libresoc.v:165819$10426_Y - attribute \src "libresoc.v:165822.17-165822.91" - wire $not$libresoc.v:165822$10429_Y - attribute \src "libresoc.v:165809.18-165809.116" - wire $reduce_or$libresoc.v:165809$10416_Y - attribute \src "libresoc.v:165811.18-165811.122" - wire $reduce_or$libresoc.v:165811$10418_Y - attribute \src "libresoc.v:165814.18-165814.128" - wire $reduce_or$libresoc.v:165814$10421_Y - attribute \src "libresoc.v:165816.18-165816.134" - wire $reduce_or$libresoc.v:165816$10423_Y - attribute \src "libresoc.v:165818.18-165818.140" - wire $reduce_or$libresoc.v:165818$10425_Y - attribute \src "libresoc.v:165820.18-165820.90" - wire $reduce_or$libresoc.v:165820$10427_Y - attribute \src "libresoc.v:165821.17-165821.103" - wire $reduce_or$libresoc.v:165821$10428_Y - attribute \src "libresoc.v:165823.17-165823.109" - wire $reduce_or$libresoc.v:165823$10430_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165808$10415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165808$10415_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165810$10417 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165810$10417_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165812$10419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165812$10419_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165813$10420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165813$10420_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165815$10422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165815$10422_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165817$10424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165817$10424_Y +module \dec31_dec_sub15 + attribute \src "libresoc.v:22431.3-22533.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22843.3-22945.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24182.3-24284.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24285.3-24387.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22328.3-22430.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22740.3-22842.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23667.3-23769.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21916.3-22018.6" + wire width 12 $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23770.3-23872.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23873.3-23975.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23976.3-24078.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23049.3-23151.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22534.3-22636.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22637.3-22739.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23255.3-23357.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:22019.3-22121.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23461.3-23563.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:24079.3-24181.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22225.3-22327.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23152.3-23254.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23564.3-23666.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23358.3-23460.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:22946.3-23048.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22122.3-22224.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:21659.7-21659.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:22431.3-22533.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22843.3-22945.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:24182.3-24284.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24285.3-24387.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:22328.3-22430.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22740.3-22842.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:23667.3-23769.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:21916.3-22018.6" + wire width 12 $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:23770.3-23872.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23873.3-23975.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23976.3-24078.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23049.3-23151.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:22534.3-22636.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22637.3-22739.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:23255.3-23357.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:22019.3-22121.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:23461.3-23563.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:24079.3-24181.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:22225.3-22327.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:23152.3-23254.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23564.3-23666.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23358.3-23460.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:22946.3-23048.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22122.3-22224.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub15_upd + attribute \src "libresoc.v:21659.7-21659.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:21659.7-21659.20" + process $proc$libresoc.v:21659$506 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165819$10426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165819$10426_Y + attribute \src "libresoc.v:21916.3-22018.6" + process $proc$libresoc.v:21916$482 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "libresoc.v:21917.5-21917.29" + switch \initial + attribute \src "libresoc.v:21917.9-21917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165822$10429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165822$10429_Y + attribute \src "libresoc.v:22019.3-22121.6" + process $proc$libresoc.v:22019$483 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:22020.5-22020.29" + switch \initial + attribute \src "libresoc.v:22020.9-22020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165809$10416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165809$10416_Y + attribute \src "libresoc.v:22122.3-22224.6" + process $proc$libresoc.v:22122$484 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:22123.5-22123.29" + switch \initial + attribute \src "libresoc.v:22123.9-22123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165811$10418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165811$10418_Y + attribute \src "libresoc.v:22225.3-22327.6" + process $proc$libresoc.v:22225$485 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:22226.5-22226.29" + switch \initial + attribute \src "libresoc.v:22226.9-22226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165814$10421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165814$10421_Y + attribute \src "libresoc.v:22328.3-22430.6" + process $proc$libresoc.v:22328$486 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:22329.5-22329.29" + switch \initial + attribute \src "libresoc.v:22329.9-22329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165816$10423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165816$10423_Y + attribute \src "libresoc.v:22431.3-22533.6" + process $proc$libresoc.v:22431$487 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:22432.5-22432.29" + switch \initial + attribute \src "libresoc.v:22432.9-22432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165818$10425 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165818$10425_Y + attribute \src "libresoc.v:22534.3-22636.6" + process $proc$libresoc.v:22534$488 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:22535.5-22535.29" + switch \initial + attribute \src "libresoc.v:22535.9-22535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165820$10427 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165820$10427_Y + attribute \src "libresoc.v:22637.3-22739.6" + process $proc$libresoc.v:22637$489 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:22638.5-22638.29" + switch \initial + attribute \src "libresoc.v:22638.9-22638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165821$10428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165821$10428_Y + attribute \src "libresoc.v:22740.3-22842.6" + process $proc$libresoc.v:22740$490 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:22741.5-22741.29" + switch \initial + attribute \src "libresoc.v:22741.9-22741.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165823$10430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165823$10430_Y - end - connect \$7 $not$libresoc.v:165808$10415_Y - connect \$12 $reduce_or$libresoc.v:165809$10416_Y - connect \$11 $not$libresoc.v:165810$10417_Y - connect \$16 $reduce_or$libresoc.v:165811$10418_Y - connect \$15 $not$libresoc.v:165812$10419_Y - connect \$1 $not$libresoc.v:165813$10420_Y - connect \$20 $reduce_or$libresoc.v:165814$10421_Y - connect \$19 $not$libresoc.v:165815$10422_Y - connect \$24 $reduce_or$libresoc.v:165816$10423_Y - connect \$23 $not$libresoc.v:165817$10424_Y - connect \$28 $reduce_or$libresoc.v:165818$10425_Y - connect \$27 $not$libresoc.v:165819$10426_Y - connect \$31 $reduce_or$libresoc.v:165820$10427_Y - connect \$4 $reduce_or$libresoc.v:165821$10428_Y - connect \$3 $not$libresoc.v:165822$10429_Y - connect \$8 $reduce_or$libresoc.v:165823$10430_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:165839.1-165923.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$200 - attribute \src "libresoc.v:165896.17-165896.91" - wire $not$libresoc.v:165896$10431_Y - attribute \src "libresoc.v:165898.18-165898.93" - wire $not$libresoc.v:165898$10433_Y - attribute \src "libresoc.v:165900.18-165900.93" - wire $not$libresoc.v:165900$10435_Y - attribute \src "libresoc.v:165901.17-165901.138" - wire width 8 $not$libresoc.v:165901$10436_Y - attribute \src "libresoc.v:165903.18-165903.93" - wire $not$libresoc.v:165903$10438_Y - attribute \src "libresoc.v:165905.18-165905.93" - wire $not$libresoc.v:165905$10440_Y - attribute \src "libresoc.v:165907.18-165907.93" - wire $not$libresoc.v:165907$10442_Y - attribute \src "libresoc.v:165910.17-165910.91" - wire $not$libresoc.v:165910$10445_Y - attribute \src "libresoc.v:165897.18-165897.116" - wire $reduce_or$libresoc.v:165897$10432_Y - attribute \src "libresoc.v:165899.18-165899.122" - wire $reduce_or$libresoc.v:165899$10434_Y - attribute \src "libresoc.v:165902.18-165902.128" - wire $reduce_or$libresoc.v:165902$10437_Y - attribute \src "libresoc.v:165904.18-165904.134" - wire $reduce_or$libresoc.v:165904$10439_Y - attribute \src "libresoc.v:165906.18-165906.140" - wire $reduce_or$libresoc.v:165906$10441_Y - attribute \src "libresoc.v:165908.18-165908.90" - wire $reduce_or$libresoc.v:165908$10443_Y - attribute \src "libresoc.v:165909.17-165909.103" - wire $reduce_or$libresoc.v:165909$10444_Y - attribute \src "libresoc.v:165911.17-165911.109" - wire $reduce_or$libresoc.v:165911$10446_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165896$10431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165896$10431_Y + attribute \src "libresoc.v:22843.3-22945.6" + process $proc$libresoc.v:22843$491 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:22844.5-22844.29" + switch \initial + attribute \src "libresoc.v:22844.9-22844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165898$10433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165898$10433_Y + attribute \src "libresoc.v:22946.3-23048.6" + process $proc$libresoc.v:22946$492 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:22947.5-22947.29" + switch \initial + attribute \src "libresoc.v:22947.9-22947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165900$10435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165900$10435_Y + attribute \src "libresoc.v:23049.3-23151.6" + process $proc$libresoc.v:23049$493 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:23050.5-23050.29" + switch \initial + attribute \src "libresoc.v:23050.9-23050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165901$10436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165901$10436_Y + attribute \src "libresoc.v:23152.3-23254.6" + process $proc$libresoc.v:23152$494 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:23153.5-23153.29" + switch \initial + attribute \src "libresoc.v:23153.9-23153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165903$10438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165903$10438_Y + attribute \src "libresoc.v:23255.3-23357.6" + process $proc$libresoc.v:23255$495 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:23256.5-23256.29" + switch \initial + attribute \src "libresoc.v:23256.9-23256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165905$10440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165905$10440_Y + attribute \src "libresoc.v:23358.3-23460.6" + process $proc$libresoc.v:23358$496 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:23359.5-23359.29" + switch \initial + attribute \src "libresoc.v:23359.9-23359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165907$10442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165907$10442_Y + attribute \src "libresoc.v:23461.3-23563.6" + process $proc$libresoc.v:23461$497 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:23462.5-23462.29" + switch \initial + attribute \src "libresoc.v:23462.9-23462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165910$10445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165910$10445_Y + attribute \src "libresoc.v:23564.3-23666.6" + process $proc$libresoc.v:23564$498 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:23565.5-23565.29" + switch \initial + attribute \src "libresoc.v:23565.9-23565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165897$10432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165897$10432_Y + attribute \src "libresoc.v:23667.3-23769.6" + process $proc$libresoc.v:23667$499 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:23668.5-23668.29" + switch \initial + attribute \src "libresoc.v:23668.9-23668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165899$10434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165899$10434_Y + attribute \src "libresoc.v:23770.3-23872.6" + process $proc$libresoc.v:23770$500 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:23771.5-23771.29" + switch \initial + attribute \src "libresoc.v:23771.9-23771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165902$10437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165902$10437_Y + attribute \src "libresoc.v:23873.3-23975.6" + process $proc$libresoc.v:23873$501 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:23874.5-23874.29" + switch \initial + attribute \src "libresoc.v:23874.9-23874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165904$10439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165904$10439_Y + attribute \src "libresoc.v:23976.3-24078.6" + process $proc$libresoc.v:23976$502 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:23977.5-23977.29" + switch \initial + attribute \src "libresoc.v:23977.9-23977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165906$10441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165906$10441_Y + attribute \src "libresoc.v:24079.3-24181.6" + process $proc$libresoc.v:24079$503 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:24080.5-24080.29" + switch \initial + attribute \src "libresoc.v:24080.9-24080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165908$10443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165908$10443_Y + attribute \src "libresoc.v:24182.3-24284.6" + process $proc$libresoc.v:24182$504 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:24183.5-24183.29" + switch \initial + attribute \src "libresoc.v:24183.9-24183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165909$10444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165909$10444_Y + attribute \src "libresoc.v:24285.3-24387.6" + process $proc$libresoc.v:24285$505 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:24286.5-24286.29" + switch \initial + attribute \src "libresoc.v:24286.9-24286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165911$10446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165911$10446_Y - end - connect \$7 $not$libresoc.v:165896$10431_Y - connect \$12 $reduce_or$libresoc.v:165897$10432_Y - connect \$11 $not$libresoc.v:165898$10433_Y - connect \$16 $reduce_or$libresoc.v:165899$10434_Y - connect \$15 $not$libresoc.v:165900$10435_Y - connect \$1 $not$libresoc.v:165901$10436_Y - connect \$20 $reduce_or$libresoc.v:165902$10437_Y - connect \$19 $not$libresoc.v:165903$10438_Y - connect \$24 $reduce_or$libresoc.v:165904$10439_Y - connect \$23 $not$libresoc.v:165905$10440_Y - connect \$28 $reduce_or$libresoc.v:165906$10441_Y - connect \$27 $not$libresoc.v:165907$10442_Y - connect \$31 $reduce_or$libresoc.v:165908$10443_Y - connect \$4 $reduce_or$libresoc.v:165909$10444_Y - connect \$3 $not$libresoc.v:165910$10445_Y - connect \$8 $reduce_or$libresoc.v:165911$10446_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:165927.1-166011.10" +attribute \src "libresoc.v:24393.1-24892.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out.ppick" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" -module \ppick$202 - attribute \src "libresoc.v:165984.17-165984.91" - wire $not$libresoc.v:165984$10447_Y - attribute \src "libresoc.v:165986.18-165986.93" - wire $not$libresoc.v:165986$10449_Y - attribute \src "libresoc.v:165988.18-165988.93" - wire $not$libresoc.v:165988$10451_Y - attribute \src "libresoc.v:165989.17-165989.138" - wire width 8 $not$libresoc.v:165989$10452_Y - attribute \src "libresoc.v:165991.18-165991.93" - wire $not$libresoc.v:165991$10454_Y - attribute \src "libresoc.v:165993.18-165993.93" - wire $not$libresoc.v:165993$10456_Y - attribute \src "libresoc.v:165995.18-165995.93" - wire $not$libresoc.v:165995$10458_Y - attribute \src "libresoc.v:165998.17-165998.91" - wire $not$libresoc.v:165998$10461_Y - attribute \src "libresoc.v:165985.18-165985.116" - wire $reduce_or$libresoc.v:165985$10448_Y - attribute \src "libresoc.v:165987.18-165987.122" - wire $reduce_or$libresoc.v:165987$10450_Y - attribute \src "libresoc.v:165990.18-165990.128" - wire $reduce_or$libresoc.v:165990$10453_Y - attribute \src "libresoc.v:165992.18-165992.134" - wire $reduce_or$libresoc.v:165992$10455_Y - attribute \src "libresoc.v:165994.18-165994.140" - wire $reduce_or$libresoc.v:165994$10457_Y - attribute \src "libresoc.v:165996.18-165996.90" - wire $reduce_or$libresoc.v:165996$10459_Y - attribute \src "libresoc.v:165997.17-165997.103" - wire $reduce_or$libresoc.v:165997$10460_Y - attribute \src "libresoc.v:165999.17-165999.109" - wire $reduce_or$libresoc.v:165999$10462_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165984$10447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:165984$10447_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165986$10449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:165986$10449_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165988$10451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:165988$10451_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:165989$10452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:165989$10452_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165991$10454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:165991$10454_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165993$10456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:165993$10456_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165995$10458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:165995$10458_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:165998$10461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:165998$10461_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165985$10448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:165985$10448_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165987$10450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:165987$10450_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165990$10453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:165990$10453_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165992$10455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:165992$10455_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165994$10457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:165994$10457_Y +module \dec31_dec_sub16 + attribute \src "libresoc.v:24701.3-24710.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24741.3-24750.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24871.3-24880.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24881.3-24890.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24691.3-24700.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24731.3-24740.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24821.3-24830.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24651.3-24660.6" + wire width 12 $0\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24831.3-24840.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24841.3-24850.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24851.3-24860.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24761.3-24770.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24711.3-24720.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24721.3-24730.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24781.3-24790.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24661.3-24670.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24801.3-24810.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24861.3-24870.6" + wire width 2 $0\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24681.3-24690.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24771.3-24780.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24811.3-24820.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24791.3-24800.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24751.3-24760.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24671.3-24680.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24394.7-24394.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:24701.3-24710.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24741.3-24750.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24871.3-24880.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24881.3-24890.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24691.3-24700.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24731.3-24740.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24821.3-24830.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24651.3-24660.6" + wire width 12 $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24831.3-24840.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24841.3-24850.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24851.3-24860.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24761.3-24770.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24711.3-24720.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24721.3-24730.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24781.3-24790.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24661.3-24670.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24801.3-24810.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24861.3-24870.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24681.3-24690.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24771.3-24780.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24811.3-24820.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24791.3-24800.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24751.3-24760.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24671.3-24680.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub16_upd + attribute \src "libresoc.v:24394.7-24394.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24394.7-24394.20" + process $proc$libresoc.v:24394$531 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:165996$10459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:165996$10459_Y + attribute \src "libresoc.v:24651.3-24660.6" + process $proc$libresoc.v:24651$507 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "libresoc.v:24652.5-24652.29" + switch \initial + attribute \src "libresoc.v:24652.9-24652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165997$10460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:165997$10460_Y + attribute \src "libresoc.v:24661.3-24670.6" + process $proc$libresoc.v:24661$508 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:24662.5-24662.29" + switch \initial + attribute \src "libresoc.v:24662.9-24662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:165999$10462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:165999$10462_Y - end - connect \$7 $not$libresoc.v:165984$10447_Y - connect \$12 $reduce_or$libresoc.v:165985$10448_Y - connect \$11 $not$libresoc.v:165986$10449_Y - connect \$16 $reduce_or$libresoc.v:165987$10450_Y - connect \$15 $not$libresoc.v:165988$10451_Y - connect \$1 $not$libresoc.v:165989$10452_Y - connect \$20 $reduce_or$libresoc.v:165990$10453_Y - connect \$19 $not$libresoc.v:165991$10454_Y - connect \$24 $reduce_or$libresoc.v:165992$10455_Y - connect \$23 $not$libresoc.v:165993$10456_Y - connect \$28 $reduce_or$libresoc.v:165994$10457_Y - connect \$27 $not$libresoc.v:165995$10458_Y - connect \$31 $reduce_or$libresoc.v:165996$10459_Y - connect \$4 $reduce_or$libresoc.v:165997$10460_Y - connect \$3 $not$libresoc.v:165998$10461_Y - connect \$8 $reduce_or$libresoc.v:165999$10462_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:166015.1-166099.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" -attribute \generator "nMigen" -module \ppick$209 - attribute \src "libresoc.v:166072.17-166072.91" - wire $not$libresoc.v:166072$10463_Y - attribute \src "libresoc.v:166074.18-166074.93" - wire $not$libresoc.v:166074$10465_Y - attribute \src "libresoc.v:166076.18-166076.93" - wire $not$libresoc.v:166076$10467_Y - attribute \src "libresoc.v:166077.17-166077.138" - wire width 8 $not$libresoc.v:166077$10468_Y - attribute \src "libresoc.v:166079.18-166079.93" - wire $not$libresoc.v:166079$10470_Y - attribute \src "libresoc.v:166081.18-166081.93" - wire $not$libresoc.v:166081$10472_Y - attribute \src "libresoc.v:166083.18-166083.93" - wire $not$libresoc.v:166083$10474_Y - attribute \src "libresoc.v:166086.17-166086.91" - wire $not$libresoc.v:166086$10477_Y - attribute \src "libresoc.v:166073.18-166073.116" - wire $reduce_or$libresoc.v:166073$10464_Y - attribute \src "libresoc.v:166075.18-166075.122" - wire $reduce_or$libresoc.v:166075$10466_Y - attribute \src "libresoc.v:166078.18-166078.128" - wire $reduce_or$libresoc.v:166078$10469_Y - attribute \src "libresoc.v:166080.18-166080.134" - wire $reduce_or$libresoc.v:166080$10471_Y - attribute \src "libresoc.v:166082.18-166082.140" - wire $reduce_or$libresoc.v:166082$10473_Y - attribute \src "libresoc.v:166084.18-166084.90" - wire $reduce_or$libresoc.v:166084$10475_Y - attribute \src "libresoc.v:166085.17-166085.103" - wire $reduce_or$libresoc.v:166085$10476_Y - attribute \src "libresoc.v:166087.17-166087.109" - wire $reduce_or$libresoc.v:166087$10478_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 2 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166072$10463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:166072$10463_Y + attribute \src "libresoc.v:24671.3-24680.6" + process $proc$libresoc.v:24671$509 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:24672.5-24672.29" + switch \initial + attribute \src "libresoc.v:24672.9-24672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166074$10465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:166074$10465_Y + attribute \src "libresoc.v:24681.3-24690.6" + process $proc$libresoc.v:24681$510 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:24682.5-24682.29" + switch \initial + attribute \src "libresoc.v:24682.9-24682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166076$10467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:166076$10467_Y + attribute \src "libresoc.v:24691.3-24700.6" + process $proc$libresoc.v:24691$511 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:24692.5-24692.29" + switch \initial + attribute \src "libresoc.v:24692.9-24692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166077$10468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:166077$10468_Y + attribute \src "libresoc.v:24701.3-24710.6" + process $proc$libresoc.v:24701$512 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:24702.5-24702.29" + switch \initial + attribute \src "libresoc.v:24702.9-24702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166079$10470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:166079$10470_Y + attribute \src "libresoc.v:24711.3-24720.6" + process $proc$libresoc.v:24711$513 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:24712.5-24712.29" + switch \initial + attribute \src "libresoc.v:24712.9-24712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166081$10472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:166081$10472_Y + attribute \src "libresoc.v:24721.3-24730.6" + process $proc$libresoc.v:24721$514 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:24722.5-24722.29" + switch \initial + attribute \src "libresoc.v:24722.9-24722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166083$10474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:166083$10474_Y + attribute \src "libresoc.v:24731.3-24740.6" + process $proc$libresoc.v:24731$515 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:24732.5-24732.29" + switch \initial + attribute \src "libresoc.v:24732.9-24732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166086$10477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166086$10477_Y + attribute \src "libresoc.v:24741.3-24750.6" + process $proc$libresoc.v:24741$516 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:24742.5-24742.29" + switch \initial + attribute \src "libresoc.v:24742.9-24742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166073$10464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:166073$10464_Y + attribute \src "libresoc.v:24751.3-24760.6" + process $proc$libresoc.v:24751$517 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:24752.5-24752.29" + switch \initial + attribute \src "libresoc.v:24752.9-24752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166075$10466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:166075$10466_Y + attribute \src "libresoc.v:24761.3-24770.6" + process $proc$libresoc.v:24761$518 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:24762.5-24762.29" + switch \initial + attribute \src "libresoc.v:24762.9-24762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166078$10469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:166078$10469_Y + attribute \src "libresoc.v:24771.3-24780.6" + process $proc$libresoc.v:24771$519 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:24772.5-24772.29" + switch \initial + attribute \src "libresoc.v:24772.9-24772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166080$10471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:166080$10471_Y + attribute \src "libresoc.v:24781.3-24790.6" + process $proc$libresoc.v:24781$520 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:24782.5-24782.29" + switch \initial + attribute \src "libresoc.v:24782.9-24782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166082$10473 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:166082$10473_Y + attribute \src "libresoc.v:24791.3-24800.6" + process $proc$libresoc.v:24791$521 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:24792.5-24792.29" + switch \initial + attribute \src "libresoc.v:24792.9-24792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166084$10475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166084$10475_Y + attribute \src "libresoc.v:24801.3-24810.6" + process $proc$libresoc.v:24801$522 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:24802.5-24802.29" + switch \initial + attribute \src "libresoc.v:24802.9-24802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166085$10476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:166085$10476_Y + attribute \src "libresoc.v:24811.3-24820.6" + process $proc$libresoc.v:24811$523 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:24812.5-24812.29" + switch \initial + attribute \src "libresoc.v:24812.9-24812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166087$10478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:166087$10478_Y - end - connect \$7 $not$libresoc.v:166072$10463_Y - connect \$12 $reduce_or$libresoc.v:166073$10464_Y - connect \$11 $not$libresoc.v:166074$10465_Y - connect \$16 $reduce_or$libresoc.v:166075$10466_Y - connect \$15 $not$libresoc.v:166076$10467_Y - connect \$1 $not$libresoc.v:166077$10468_Y - connect \$20 $reduce_or$libresoc.v:166078$10469_Y - connect \$19 $not$libresoc.v:166079$10470_Y - connect \$24 $reduce_or$libresoc.v:166080$10471_Y - connect \$23 $not$libresoc.v:166081$10472_Y - connect \$28 $reduce_or$libresoc.v:166082$10473_Y - connect \$27 $not$libresoc.v:166083$10474_Y - connect \$31 $reduce_or$libresoc.v:166084$10475_Y - connect \$4 $reduce_or$libresoc.v:166085$10476_Y - connect \$3 $not$libresoc.v:166086$10477_Y - connect \$8 $reduce_or$libresoc.v:166087$10478_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:166103.1-166187.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" -attribute \generator "nMigen" -module \ppick$211 - attribute \src "libresoc.v:166160.17-166160.91" - wire $not$libresoc.v:166160$10479_Y - attribute \src "libresoc.v:166162.18-166162.93" - wire $not$libresoc.v:166162$10481_Y - attribute \src "libresoc.v:166164.18-166164.93" - wire $not$libresoc.v:166164$10483_Y - attribute \src "libresoc.v:166165.17-166165.138" - wire width 8 $not$libresoc.v:166165$10484_Y - attribute \src "libresoc.v:166167.18-166167.93" - wire $not$libresoc.v:166167$10486_Y - attribute \src "libresoc.v:166169.18-166169.93" - wire $not$libresoc.v:166169$10488_Y - attribute \src "libresoc.v:166171.18-166171.93" - wire $not$libresoc.v:166171$10490_Y - attribute \src "libresoc.v:166174.17-166174.91" - wire $not$libresoc.v:166174$10493_Y - attribute \src "libresoc.v:166161.18-166161.116" - wire $reduce_or$libresoc.v:166161$10480_Y - attribute \src "libresoc.v:166163.18-166163.122" - wire $reduce_or$libresoc.v:166163$10482_Y - attribute \src "libresoc.v:166166.18-166166.128" - wire $reduce_or$libresoc.v:166166$10485_Y - attribute \src "libresoc.v:166168.18-166168.134" - wire $reduce_or$libresoc.v:166168$10487_Y - attribute \src "libresoc.v:166170.18-166170.140" - wire $reduce_or$libresoc.v:166170$10489_Y - attribute \src "libresoc.v:166172.18-166172.90" - wire $reduce_or$libresoc.v:166172$10491_Y - attribute \src "libresoc.v:166173.17-166173.103" - wire $reduce_or$libresoc.v:166173$10492_Y - attribute \src "libresoc.v:166175.17-166175.109" - wire $reduce_or$libresoc.v:166175$10494_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166160$10479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:166160$10479_Y + attribute \src "libresoc.v:24821.3-24830.6" + process $proc$libresoc.v:24821$524 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:24822.5-24822.29" + switch \initial + attribute \src "libresoc.v:24822.9-24822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166162$10481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:166162$10481_Y + attribute \src "libresoc.v:24831.3-24840.6" + process $proc$libresoc.v:24831$525 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:24832.5-24832.29" + switch \initial + attribute \src "libresoc.v:24832.9-24832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166164$10483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:166164$10483_Y + attribute \src "libresoc.v:24841.3-24850.6" + process $proc$libresoc.v:24841$526 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:24842.5-24842.29" + switch \initial + attribute \src "libresoc.v:24842.9-24842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166165$10484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:166165$10484_Y + attribute \src "libresoc.v:24851.3-24860.6" + process $proc$libresoc.v:24851$527 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:24852.5-24852.29" + switch \initial + attribute \src "libresoc.v:24852.9-24852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166167$10486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:166167$10486_Y + attribute \src "libresoc.v:24861.3-24870.6" + process $proc$libresoc.v:24861$528 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:24862.5-24862.29" + switch \initial + attribute \src "libresoc.v:24862.9-24862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166169$10488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:166169$10488_Y + attribute \src "libresoc.v:24871.3-24880.6" + process $proc$libresoc.v:24871$529 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:24872.5-24872.29" + switch \initial + attribute \src "libresoc.v:24872.9-24872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166171$10490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:166171$10490_Y + attribute \src "libresoc.v:24881.3-24890.6" + process $proc$libresoc.v:24881$530 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:24882.5-24882.29" + switch \initial + attribute \src "libresoc.v:24882.9-24882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166174$10493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166174$10493_Y + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:24896.1-25683.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:25264.3-25285.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25352.3-25373.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25638.3-25659.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25660.3-25681.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25242.3-25263.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25330.3-25351.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25528.3-25549.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25154.3-25175.6" + wire width 12 $0\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25550.3-25571.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25572.3-25593.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25594.3-25615.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25396.3-25417.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25286.3-25307.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25308.3-25329.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25440.3-25461.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25176.3-25197.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25484.3-25505.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25616.3-25637.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25220.3-25241.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25418.3-25439.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25506.3-25527.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25462.3-25483.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25374.3-25395.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25198.3-25219.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:24897.7-24897.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:25264.3-25285.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25352.3-25373.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25638.3-25659.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25660.3-25681.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25242.3-25263.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25330.3-25351.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25528.3-25549.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25154.3-25175.6" + wire width 12 $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25550.3-25571.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25572.3-25593.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25594.3-25615.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25396.3-25417.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25286.3-25307.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25308.3-25329.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25440.3-25461.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25176.3-25197.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25484.3-25505.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25616.3-25637.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25220.3-25241.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25418.3-25439.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25506.3-25527.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25462.3-25483.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25374.3-25395.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25198.3-25219.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub18_upd + attribute \src "libresoc.v:24897.7-24897.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:24897.7-24897.20" + process $proc$libresoc.v:24897$556 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166161$10480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:166161$10480_Y + attribute \src "libresoc.v:25154.3-25175.6" + process $proc$libresoc.v:25154$532 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "libresoc.v:25155.5-25155.29" + switch \initial + attribute \src "libresoc.v:25155.9-25155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'100000000000 + case + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166163$10482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:166163$10482_Y + attribute \src "libresoc.v:25176.3-25197.6" + process $proc$libresoc.v:25176$533 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:25177.5-25177.29" + switch \initial + attribute \src "libresoc.v:25177.9-25177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166166$10485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:166166$10485_Y + attribute \src "libresoc.v:25198.3-25219.6" + process $proc$libresoc.v:25198$534 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:25199.5-25199.29" + switch \initial + attribute \src "libresoc.v:25199.9-25199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166168$10487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:166168$10487_Y + attribute \src "libresoc.v:25220.3-25241.6" + process $proc$libresoc.v:25220$535 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:25221.5-25221.29" + switch \initial + attribute \src "libresoc.v:25221.9-25221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166170$10489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:166170$10489_Y + attribute \src "libresoc.v:25242.3-25263.6" + process $proc$libresoc.v:25242$536 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:25243.5-25243.29" + switch \initial + attribute \src "libresoc.v:25243.9-25243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166172$10491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166172$10491_Y + attribute \src "libresoc.v:25264.3-25285.6" + process $proc$libresoc.v:25264$537 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:25265.5-25265.29" + switch \initial + attribute \src "libresoc.v:25265.9-25265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166173$10492 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:166173$10492_Y + attribute \src "libresoc.v:25286.3-25307.6" + process $proc$libresoc.v:25286$538 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:25287.5-25287.29" + switch \initial + attribute \src "libresoc.v:25287.9-25287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166175$10494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:166175$10494_Y - end - connect \$7 $not$libresoc.v:166160$10479_Y - connect \$12 $reduce_or$libresoc.v:166161$10480_Y - connect \$11 $not$libresoc.v:166162$10481_Y - connect \$16 $reduce_or$libresoc.v:166163$10482_Y - connect \$15 $not$libresoc.v:166164$10483_Y - connect \$1 $not$libresoc.v:166165$10484_Y - connect \$20 $reduce_or$libresoc.v:166166$10485_Y - connect \$19 $not$libresoc.v:166167$10486_Y - connect \$24 $reduce_or$libresoc.v:166168$10487_Y - connect \$23 $not$libresoc.v:166169$10488_Y - connect \$28 $reduce_or$libresoc.v:166170$10489_Y - connect \$27 $not$libresoc.v:166171$10490_Y - connect \$31 $reduce_or$libresoc.v:166172$10491_Y - connect \$4 $reduce_or$libresoc.v:166173$10492_Y - connect \$3 $not$libresoc.v:166174$10493_Y - connect \$8 $reduce_or$libresoc.v:166175$10494_Y - connect \en_o \$31 - connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [7] - connect \ni \$1 -end -attribute \src "libresoc.v:166191.1-166221.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" -attribute \generator "nMigen" -module \rdpick_CR_cr_a - attribute \src "libresoc.v:166212.17-166212.89" - wire width 2 $not$libresoc.v:166212$10495_Y - attribute \src "libresoc.v:166214.17-166214.91" - wire $not$libresoc.v:166214$10497_Y - attribute \src "libresoc.v:166213.17-166213.103" - wire $reduce_or$libresoc.v:166213$10496_Y - attribute \src "libresoc.v:166215.17-166215.89" - wire $reduce_or$libresoc.v:166215$10498_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166212$10495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$libresoc.v:166212$10495_Y + attribute \src "libresoc.v:25308.3-25329.6" + process $proc$libresoc.v:25308$539 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:25309.5-25309.29" + switch \initial + attribute \src "libresoc.v:25309.9-25309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166214$10497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166214$10497_Y + attribute \src "libresoc.v:25330.3-25351.6" + process $proc$libresoc.v:25330$540 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:25331.5-25331.29" + switch \initial + attribute \src "libresoc.v:25331.9-25331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166213$10496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166213$10496_Y + attribute \src "libresoc.v:25352.3-25373.6" + process $proc$libresoc.v:25352$541 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:25353.5-25353.29" + switch \initial + attribute \src "libresoc.v:25353.9-25353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166215$10498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166215$10498_Y - end - connect \$1 $not$libresoc.v:166212$10495_Y - connect \$4 $reduce_or$libresoc.v:166213$10496_Y - connect \$3 $not$libresoc.v:166214$10497_Y - connect \$7 $reduce_or$libresoc.v:166215$10498_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:166225.1-166246.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" -attribute \generator "nMigen" -module \rdpick_CR_cr_b - attribute \src "libresoc.v:166240.17-166240.89" - wire $not$libresoc.v:166240$10499_Y - attribute \src "libresoc.v:166241.17-166241.89" - wire $reduce_or$libresoc.v:166241$10500_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166240$10499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:166240$10499_Y + attribute \src "libresoc.v:25374.3-25395.6" + process $proc$libresoc.v:25374$542 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:25375.5-25375.29" + switch \initial + attribute \src "libresoc.v:25375.9-25375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166241$10500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166241$10500_Y + attribute \src "libresoc.v:25396.3-25417.6" + process $proc$libresoc.v:25396$543 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:25397.5-25397.29" + switch \initial + attribute \src "libresoc.v:25397.9-25397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - connect \$1 $not$libresoc.v:166240$10499_Y - connect \$3 $reduce_or$libresoc.v:166241$10500_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:166250.1-166271.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" -attribute \generator "nMigen" -module \rdpick_CR_cr_c - attribute \src "libresoc.v:166265.17-166265.89" - wire $not$libresoc.v:166265$10501_Y - attribute \src "libresoc.v:166266.17-166266.89" - wire $reduce_or$libresoc.v:166266$10502_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166265$10501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:166265$10501_Y + attribute \src "libresoc.v:25418.3-25439.6" + process $proc$libresoc.v:25418$544 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:25419.5-25419.29" + switch \initial + attribute \src "libresoc.v:25419.9-25419.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166266$10502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166266$10502_Y + attribute \src "libresoc.v:25440.3-25461.6" + process $proc$libresoc.v:25440$545 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:25441.5-25441.29" + switch \initial + attribute \src "libresoc.v:25441.9-25441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - connect \$1 $not$libresoc.v:166265$10501_Y - connect \$3 $reduce_or$libresoc.v:166266$10502_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:166275.1-166296.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" -attribute \generator "nMigen" -module \rdpick_CR_full_cr - attribute \src "libresoc.v:166290.17-166290.89" - wire $not$libresoc.v:166290$10503_Y - attribute \src "libresoc.v:166291.17-166291.89" - wire $reduce_or$libresoc.v:166291$10504_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166290$10503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:166290$10503_Y + attribute \src "libresoc.v:25462.3-25483.6" + process $proc$libresoc.v:25462$546 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:25463.5-25463.29" + switch \initial + attribute \src "libresoc.v:25463.9-25463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166291$10504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166291$10504_Y + attribute \src "libresoc.v:25484.3-25505.6" + process $proc$libresoc.v:25484$547 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:25485.5-25485.29" + switch \initial + attribute \src "libresoc.v:25485.9-25485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - connect \$1 $not$libresoc.v:166290$10503_Y - connect \$3 $reduce_or$libresoc.v:166291$10504_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:166300.1-166339.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" -attribute \generator "nMigen" -module \rdpick_FAST_fast1 - attribute \src "libresoc.v:166327.17-166327.91" - wire $not$libresoc.v:166327$10505_Y - attribute \src "libresoc.v:166329.17-166329.89" - wire width 3 $not$libresoc.v:166329$10507_Y - attribute \src "libresoc.v:166331.17-166331.91" - wire $not$libresoc.v:166331$10509_Y - attribute \src "libresoc.v:166328.18-166328.90" - wire $reduce_or$libresoc.v:166328$10506_Y - attribute \src "libresoc.v:166330.17-166330.103" - wire $reduce_or$libresoc.v:166330$10508_Y - attribute \src "libresoc.v:166332.17-166332.105" - wire $reduce_or$libresoc.v:166332$10510_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166327$10505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:166327$10505_Y + attribute \src "libresoc.v:25506.3-25527.6" + process $proc$libresoc.v:25506$548 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:25507.5-25507.29" + switch \initial + attribute \src "libresoc.v:25507.9-25507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166329$10507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $not$libresoc.v:166329$10507_Y + attribute \src "libresoc.v:25528.3-25549.6" + process $proc$libresoc.v:25528$549 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:25529.5-25529.29" + switch \initial + attribute \src "libresoc.v:25529.9-25529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166331$10509 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166331$10509_Y + attribute \src "libresoc.v:25550.3-25571.6" + process $proc$libresoc.v:25550$550 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:25551.5-25551.29" + switch \initial + attribute \src "libresoc.v:25551.9-25551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166328$10506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166328$10506_Y + attribute \src "libresoc.v:25572.3-25593.6" + process $proc$libresoc.v:25572$551 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:25573.5-25573.29" + switch \initial + attribute \src "libresoc.v:25573.9-25573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166330$10508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166330$10508_Y + attribute \src "libresoc.v:25594.3-25615.6" + process $proc$libresoc.v:25594$552 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:25595.5-25595.29" + switch \initial + attribute \src "libresoc.v:25595.9-25595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166332$10510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166332$10510_Y - end - connect \$7 $not$libresoc.v:166327$10505_Y - connect \$11 $reduce_or$libresoc.v:166328$10506_Y - connect \$1 $not$libresoc.v:166329$10507_Y - connect \$4 $reduce_or$libresoc.v:166330$10508_Y - connect \$3 $not$libresoc.v:166331$10509_Y - connect \$8 $reduce_or$libresoc.v:166332$10510_Y - connect \en_o \$11 - connect \o { \t2 \t1 \t0 } - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:166343.1-166373.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" -attribute \generator "nMigen" -module \rdpick_FAST_fast2 - attribute \src "libresoc.v:166364.17-166364.89" - wire width 2 $not$libresoc.v:166364$10511_Y - attribute \src "libresoc.v:166366.17-166366.91" - wire $not$libresoc.v:166366$10513_Y - attribute \src "libresoc.v:166365.17-166365.103" - wire $reduce_or$libresoc.v:166365$10512_Y - attribute \src "libresoc.v:166367.17-166367.89" - wire $reduce_or$libresoc.v:166367$10514_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166364$10511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$libresoc.v:166364$10511_Y + attribute \src "libresoc.v:25616.3-25637.6" + process $proc$libresoc.v:25616$553 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:25617.5-25617.29" + switch \initial + attribute \src "libresoc.v:25617.9-25617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166366$10513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166366$10513_Y + attribute \src "libresoc.v:25638.3-25659.6" + process $proc$libresoc.v:25638$554 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:25639.5-25639.29" + switch \initial + attribute \src "libresoc.v:25639.9-25639.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166365$10512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166365$10512_Y + attribute \src "libresoc.v:25660.3-25681.6" + process $proc$libresoc.v:25660$555 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:25661.5-25661.29" + switch \initial + attribute \src "libresoc.v:25661.9-25661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166367$10514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166367$10514_Y - end - connect \$1 $not$libresoc.v:166364$10511_Y - connect \$4 $reduce_or$libresoc.v:166365$10512_Y - connect \$3 $not$libresoc.v:166366$10513_Y - connect \$7 $reduce_or$libresoc.v:166367$10514_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:166377.1-166470.10" +attribute \src "libresoc.v:25687.1-26402.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" -module \rdpick_INT_ra - attribute \src "libresoc.v:166440.17-166440.91" - wire $not$libresoc.v:166440$10515_Y - attribute \src "libresoc.v:166442.18-166442.93" - wire $not$libresoc.v:166442$10517_Y - attribute \src "libresoc.v:166444.18-166444.93" - wire $not$libresoc.v:166444$10519_Y - attribute \src "libresoc.v:166445.17-166445.89" - wire width 9 $not$libresoc.v:166445$10520_Y - attribute \src "libresoc.v:166447.18-166447.93" - wire $not$libresoc.v:166447$10522_Y - attribute \src "libresoc.v:166449.18-166449.93" - wire $not$libresoc.v:166449$10524_Y - attribute \src "libresoc.v:166451.18-166451.93" - wire $not$libresoc.v:166451$10526_Y - attribute \src "libresoc.v:166453.18-166453.93" - wire $not$libresoc.v:166453$10528_Y - attribute \src "libresoc.v:166456.17-166456.91" - wire $not$libresoc.v:166456$10531_Y - attribute \src "libresoc.v:166441.18-166441.106" - wire $reduce_or$libresoc.v:166441$10516_Y - attribute \src "libresoc.v:166443.18-166443.106" - wire $reduce_or$libresoc.v:166443$10518_Y - attribute \src "libresoc.v:166446.18-166446.106" - wire $reduce_or$libresoc.v:166446$10521_Y - attribute \src "libresoc.v:166448.18-166448.106" - wire $reduce_or$libresoc.v:166448$10523_Y - attribute \src "libresoc.v:166450.18-166450.106" - wire $reduce_or$libresoc.v:166450$10525_Y - attribute \src "libresoc.v:166452.18-166452.106" - wire $reduce_or$libresoc.v:166452$10527_Y - attribute \src "libresoc.v:166454.18-166454.90" - wire $reduce_or$libresoc.v:166454$10529_Y - attribute \src "libresoc.v:166455.17-166455.103" - wire $reduce_or$libresoc.v:166455$10530_Y - attribute \src "libresoc.v:166457.17-166457.105" - wire $reduce_or$libresoc.v:166457$10532_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 9 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 9 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 9 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 9 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166440$10515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:166440$10515_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166442$10517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:166442$10517_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166444$10519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:166444$10519_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166445$10520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 9 - connect \A \i - connect \Y $not$libresoc.v:166445$10520_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166447$10522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:166447$10522_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166449$10524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:166449$10524_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166451$10526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:166451$10526_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166453$10528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \Y $not$libresoc.v:166453$10528_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166456$10531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166456$10531_Y +module \dec31_dec_sub19 + attribute \src "libresoc.v:26040.3-26058.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26116.3-26134.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26363.3-26381.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26382.3-26400.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26021.3-26039.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26097.3-26115.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26268.3-26286.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25945.3-25963.6" + wire width 12 $0\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26287.3-26305.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26306.3-26324.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26325.3-26343.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26154.3-26172.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26059.3-26077.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26078.3-26096.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26192.3-26210.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:25964.3-25982.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26230.3-26248.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26344.3-26362.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26002.3-26020.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26173.3-26191.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26249.3-26267.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26211.3-26229.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26135.3-26153.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:25983.3-26001.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:25688.7-25688.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26040.3-26058.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26116.3-26134.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26363.3-26381.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26382.3-26400.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26021.3-26039.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26097.3-26115.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26268.3-26286.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:25945.3-25963.6" + wire width 12 $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:26287.3-26305.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26306.3-26324.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26325.3-26343.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26154.3-26172.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26059.3-26077.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26078.3-26096.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26192.3-26210.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:25964.3-25982.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:26230.3-26248.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26344.3-26362.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26002.3-26020.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26173.3-26191.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26249.3-26267.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26211.3-26229.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26135.3-26153.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:25983.3-26001.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub19_upd + attribute \src "libresoc.v:25688.7-25688.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:25688.7-25688.20" + process $proc$libresoc.v:25688$581 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166441$10516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:166441$10516_Y + attribute \src "libresoc.v:25945.3-25963.6" + process $proc$libresoc.v:25945$557 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "libresoc.v:25946.5-25946.29" + switch \initial + attribute \src "libresoc.v:25946.9-25946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166443$10518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:166443$10518_Y + attribute \src "libresoc.v:25964.3-25982.6" + process $proc$libresoc.v:25964$558 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:25965.5-25965.29" + switch \initial + attribute \src "libresoc.v:25965.9-25965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166446$10521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:166446$10521_Y + attribute \src "libresoc.v:25983.3-26001.6" + process $proc$libresoc.v:25983$559 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:25984.5-25984.29" + switch \initial + attribute \src "libresoc.v:25984.9-25984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166448$10523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:166448$10523_Y + attribute \src "libresoc.v:26002.3-26020.6" + process $proc$libresoc.v:26002$560 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:26003.5-26003.29" + switch \initial + attribute \src "libresoc.v:26003.9-26003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166450$10525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:166450$10525_Y + attribute \src "libresoc.v:26021.3-26039.6" + process $proc$libresoc.v:26021$561 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:26022.5-26022.29" + switch \initial + attribute \src "libresoc.v:26022.9-26022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166452$10527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:166452$10527_Y + attribute \src "libresoc.v:26040.3-26058.6" + process $proc$libresoc.v:26040$562 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:26041.5-26041.29" + switch \initial + attribute \src "libresoc.v:26041.9-26041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166454$10529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166454$10529_Y + attribute \src "libresoc.v:26059.3-26077.6" + process $proc$libresoc.v:26059$563 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:26060.5-26060.29" + switch \initial + attribute \src "libresoc.v:26060.9-26060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166455$10530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166455$10530_Y + attribute \src "libresoc.v:26078.3-26096.6" + process $proc$libresoc.v:26078$564 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:26079.5-26079.29" + switch \initial + attribute \src "libresoc.v:26079.9-26079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166457$10532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166457$10532_Y - end - connect \$7 $not$libresoc.v:166440$10515_Y - connect \$12 $reduce_or$libresoc.v:166441$10516_Y - connect \$11 $not$libresoc.v:166442$10517_Y - connect \$16 $reduce_or$libresoc.v:166443$10518_Y - connect \$15 $not$libresoc.v:166444$10519_Y - connect \$1 $not$libresoc.v:166445$10520_Y - connect \$20 $reduce_or$libresoc.v:166446$10521_Y - connect \$19 $not$libresoc.v:166447$10522_Y - connect \$24 $reduce_or$libresoc.v:166448$10523_Y - connect \$23 $not$libresoc.v:166449$10524_Y - connect \$28 $reduce_or$libresoc.v:166450$10525_Y - connect \$27 $not$libresoc.v:166451$10526_Y - connect \$32 $reduce_or$libresoc.v:166452$10527_Y - connect \$31 $not$libresoc.v:166453$10528_Y - connect \$35 $reduce_or$libresoc.v:166454$10529_Y - connect \$4 $reduce_or$libresoc.v:166455$10530_Y - connect \$3 $not$libresoc.v:166456$10531_Y - connect \$8 $reduce_or$libresoc.v:166457$10532_Y - connect \en_o \$35 - connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t8 \$31 - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:166474.1-166558.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" -attribute \generator "nMigen" -module \rdpick_INT_rb - attribute \src "libresoc.v:166531.17-166531.91" - wire $not$libresoc.v:166531$10533_Y - attribute \src "libresoc.v:166533.18-166533.93" - wire $not$libresoc.v:166533$10535_Y - attribute \src "libresoc.v:166535.18-166535.93" - wire $not$libresoc.v:166535$10537_Y - attribute \src "libresoc.v:166536.17-166536.89" - wire width 8 $not$libresoc.v:166536$10538_Y - attribute \src "libresoc.v:166538.18-166538.93" - wire $not$libresoc.v:166538$10540_Y - attribute \src "libresoc.v:166540.18-166540.93" - wire $not$libresoc.v:166540$10542_Y - attribute \src "libresoc.v:166542.18-166542.93" - wire $not$libresoc.v:166542$10544_Y - attribute \src "libresoc.v:166545.17-166545.91" - wire $not$libresoc.v:166545$10547_Y - attribute \src "libresoc.v:166532.18-166532.106" - wire $reduce_or$libresoc.v:166532$10534_Y - attribute \src "libresoc.v:166534.18-166534.106" - wire $reduce_or$libresoc.v:166534$10536_Y - attribute \src "libresoc.v:166537.18-166537.106" - wire $reduce_or$libresoc.v:166537$10539_Y - attribute \src "libresoc.v:166539.18-166539.106" - wire $reduce_or$libresoc.v:166539$10541_Y - attribute \src "libresoc.v:166541.18-166541.106" - wire $reduce_or$libresoc.v:166541$10543_Y - attribute \src "libresoc.v:166543.18-166543.90" - wire $reduce_or$libresoc.v:166543$10545_Y - attribute \src "libresoc.v:166544.17-166544.103" - wire $reduce_or$libresoc.v:166544$10546_Y - attribute \src "libresoc.v:166546.17-166546.105" - wire $reduce_or$libresoc.v:166546$10548_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166531$10533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:166531$10533_Y + attribute \src "libresoc.v:26097.3-26115.6" + process $proc$libresoc.v:26097$565 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:26098.5-26098.29" + switch \initial + attribute \src "libresoc.v:26098.9-26098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166533$10535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:166533$10535_Y + attribute \src "libresoc.v:26116.3-26134.6" + process $proc$libresoc.v:26116$566 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:26117.5-26117.29" + switch \initial + attribute \src "libresoc.v:26117.9-26117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166535$10537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:166535$10537_Y + attribute \src "libresoc.v:26135.3-26153.6" + process $proc$libresoc.v:26135$567 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:26136.5-26136.29" + switch \initial + attribute \src "libresoc.v:26136.9-26136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166536$10538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \i - connect \Y $not$libresoc.v:166536$10538_Y + attribute \src "libresoc.v:26154.3-26172.6" + process $proc$libresoc.v:26154$568 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:26155.5-26155.29" + switch \initial + attribute \src "libresoc.v:26155.9-26155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166538$10540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:166538$10540_Y + attribute \src "libresoc.v:26173.3-26191.6" + process $proc$libresoc.v:26173$569 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:26174.5-26174.29" + switch \initial + attribute \src "libresoc.v:26174.9-26174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166540$10542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:166540$10542_Y + attribute \src "libresoc.v:26192.3-26210.6" + process $proc$libresoc.v:26192$570 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:26193.5-26193.29" + switch \initial + attribute \src "libresoc.v:26193.9-26193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166542$10544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:166542$10544_Y + attribute \src "libresoc.v:26211.3-26229.6" + process $proc$libresoc.v:26211$571 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:26212.5-26212.29" + switch \initial + attribute \src "libresoc.v:26212.9-26212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166545$10547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166545$10547_Y + attribute \src "libresoc.v:26230.3-26248.6" + process $proc$libresoc.v:26230$572 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:26231.5-26231.29" + switch \initial + attribute \src "libresoc.v:26231.9-26231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166532$10534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:166532$10534_Y + attribute \src "libresoc.v:26249.3-26267.6" + process $proc$libresoc.v:26249$573 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:26250.5-26250.29" + switch \initial + attribute \src "libresoc.v:26250.9-26250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166534$10536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:166534$10536_Y + attribute \src "libresoc.v:26268.3-26286.6" + process $proc$libresoc.v:26268$574 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:26269.5-26269.29" + switch \initial + attribute \src "libresoc.v:26269.9-26269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166537$10539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:166537$10539_Y + attribute \src "libresoc.v:26287.3-26305.6" + process $proc$libresoc.v:26287$575 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:26288.5-26288.29" + switch \initial + attribute \src "libresoc.v:26288.9-26288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166539$10541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:166539$10541_Y + attribute \src "libresoc.v:26306.3-26324.6" + process $proc$libresoc.v:26306$576 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:26307.5-26307.29" + switch \initial + attribute \src "libresoc.v:26307.9-26307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166541$10543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:166541$10543_Y + attribute \src "libresoc.v:26325.3-26343.6" + process $proc$libresoc.v:26325$577 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:26326.5-26326.29" + switch \initial + attribute \src "libresoc.v:26326.9-26326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166543$10545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166543$10545_Y + attribute \src "libresoc.v:26344.3-26362.6" + process $proc$libresoc.v:26344$578 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:26345.5-26345.29" + switch \initial + attribute \src "libresoc.v:26345.9-26345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166544$10546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166544$10546_Y + attribute \src "libresoc.v:26363.3-26381.6" + process $proc$libresoc.v:26363$579 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:26364.5-26364.29" + switch \initial + attribute \src "libresoc.v:26364.9-26364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166546$10548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166546$10548_Y - end - connect \$7 $not$libresoc.v:166531$10533_Y - connect \$12 $reduce_or$libresoc.v:166532$10534_Y - connect \$11 $not$libresoc.v:166533$10535_Y - connect \$16 $reduce_or$libresoc.v:166534$10536_Y - connect \$15 $not$libresoc.v:166535$10537_Y - connect \$1 $not$libresoc.v:166536$10538_Y - connect \$20 $reduce_or$libresoc.v:166537$10539_Y - connect \$19 $not$libresoc.v:166538$10540_Y - connect \$24 $reduce_or$libresoc.v:166539$10541_Y - connect \$23 $not$libresoc.v:166540$10542_Y - connect \$28 $reduce_or$libresoc.v:166541$10543_Y - connect \$27 $not$libresoc.v:166542$10544_Y - connect \$31 $reduce_or$libresoc.v:166543$10545_Y - connect \$4 $reduce_or$libresoc.v:166544$10546_Y - connect \$3 $not$libresoc.v:166545$10547_Y - connect \$8 $reduce_or$libresoc.v:166546$10548_Y - connect \en_o \$31 - connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 + attribute \src "libresoc.v:26382.3-26400.6" + process $proc$libresoc.v:26382$580 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:26383.5-26383.29" + switch \initial + attribute \src "libresoc.v:26383.9-26383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:166562.1-166592.10" +attribute \src "libresoc.v:26406.1-27265.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" -module \rdpick_INT_rc - attribute \src "libresoc.v:166583.17-166583.89" - wire width 2 $not$libresoc.v:166583$10549_Y - attribute \src "libresoc.v:166585.17-166585.91" - wire $not$libresoc.v:166585$10551_Y - attribute \src "libresoc.v:166584.17-166584.103" - wire $reduce_or$libresoc.v:166584$10550_Y - attribute \src "libresoc.v:166586.17-166586.89" - wire $reduce_or$libresoc.v:166586$10552_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166583$10549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$libresoc.v:166583$10549_Y +module \dec31_dec_sub20 + attribute \src "libresoc.v:26789.3-26813.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26889.3-26913.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27214.3-27238.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27239.3-27263.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26764.3-26788.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26864.3-26888.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:27089.3-27113.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26664.3-26688.6" + wire width 12 $0\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:27114.3-27138.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27139.3-27163.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27164.3-27188.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26939.3-26963.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26814.3-26838.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26839.3-26863.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26989.3-27013.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26689.3-26713.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:27039.3-27063.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27189.3-27213.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26739.3-26763.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26964.3-26988.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:27064.3-27088.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27014.3-27038.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26914.3-26938.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26714.3-26738.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26407.7-26407.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26789.3-26813.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26889.3-26913.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:27214.3-27238.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27239.3-27263.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:26764.3-26788.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26864.3-26888.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:27089.3-27113.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:26664.3-26688.6" + wire width 12 $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:27114.3-27138.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27139.3-27163.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27164.3-27188.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:26939.3-26963.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26814.3-26838.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26839.3-26863.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26989.3-27013.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26689.3-26713.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:27039.3-27063.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27189.3-27213.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:26739.3-26763.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26964.3-26988.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:27064.3-27088.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27014.3-27038.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:26914.3-26938.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26714.3-26738.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub20_upd + attribute \src "libresoc.v:26407.7-26407.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:26407.7-26407.20" + process $proc$libresoc.v:26407$606 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166585$10551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166585$10551_Y + attribute \src "libresoc.v:26664.3-26688.6" + process $proc$libresoc.v:26664$582 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "libresoc.v:26665.5-26665.29" + switch \initial + attribute \src "libresoc.v:26665.9-26665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166584$10550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166584$10550_Y + attribute \src "libresoc.v:26689.3-26713.6" + process $proc$libresoc.v:26689$583 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:26690.5-26690.29" + switch \initial + attribute \src "libresoc.v:26690.9-26690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166586$10552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166586$10552_Y - end - connect \$1 $not$libresoc.v:166583$10549_Y - connect \$4 $reduce_or$libresoc.v:166584$10550_Y - connect \$3 $not$libresoc.v:166585$10551_Y - connect \$7 $reduce_or$libresoc.v:166586$10552_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:166596.1-166617.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" -attribute \generator "nMigen" -module \rdpick_SPR_spr1 - attribute \src "libresoc.v:166611.17-166611.89" - wire $not$libresoc.v:166611$10553_Y - attribute \src "libresoc.v:166612.17-166612.89" - wire $reduce_or$libresoc.v:166612$10554_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166611$10553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:166611$10553_Y + attribute \src "libresoc.v:26714.3-26738.6" + process $proc$libresoc.v:26714$584 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:26715.5-26715.29" + switch \initial + attribute \src "libresoc.v:26715.9-26715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166612$10554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166612$10554_Y + attribute \src "libresoc.v:26739.3-26763.6" + process $proc$libresoc.v:26739$585 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:26740.5-26740.29" + switch \initial + attribute \src "libresoc.v:26740.9-26740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - connect \$1 $not$libresoc.v:166611$10553_Y - connect \$3 $reduce_or$libresoc.v:166612$10554_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:166621.1-166660.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" -attribute \generator "nMigen" -module \rdpick_XER_xer_ca - attribute \src "libresoc.v:166648.17-166648.91" - wire $not$libresoc.v:166648$10555_Y - attribute \src "libresoc.v:166650.17-166650.89" - wire width 3 $not$libresoc.v:166650$10557_Y - attribute \src "libresoc.v:166652.17-166652.91" - wire $not$libresoc.v:166652$10559_Y - attribute \src "libresoc.v:166649.18-166649.90" - wire $reduce_or$libresoc.v:166649$10556_Y - attribute \src "libresoc.v:166651.17-166651.103" - wire $reduce_or$libresoc.v:166651$10558_Y - attribute \src "libresoc.v:166653.17-166653.105" - wire $reduce_or$libresoc.v:166653$10560_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166648$10555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:166648$10555_Y + attribute \src "libresoc.v:26764.3-26788.6" + process $proc$libresoc.v:26764$586 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:26765.5-26765.29" + switch \initial + attribute \src "libresoc.v:26765.9-26765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166650$10557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $not$libresoc.v:166650$10557_Y + attribute \src "libresoc.v:26789.3-26813.6" + process $proc$libresoc.v:26789$587 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:26790.5-26790.29" + switch \initial + attribute \src "libresoc.v:26790.9-26790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166652$10559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166652$10559_Y + attribute \src "libresoc.v:26814.3-26838.6" + process $proc$libresoc.v:26814$588 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:26815.5-26815.29" + switch \initial + attribute \src "libresoc.v:26815.9-26815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166649$10556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166649$10556_Y + attribute \src "libresoc.v:26839.3-26863.6" + process $proc$libresoc.v:26839$589 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:26840.5-26840.29" + switch \initial + attribute \src "libresoc.v:26840.9-26840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166651$10558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166651$10558_Y + attribute \src "libresoc.v:26864.3-26888.6" + process $proc$libresoc.v:26864$590 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:26865.5-26865.29" + switch \initial + attribute \src "libresoc.v:26865.9-26865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166653$10560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166653$10560_Y - end - connect \$7 $not$libresoc.v:166648$10555_Y - connect \$11 $reduce_or$libresoc.v:166649$10556_Y - connect \$1 $not$libresoc.v:166650$10557_Y - connect \$4 $reduce_or$libresoc.v:166651$10558_Y - connect \$3 $not$libresoc.v:166652$10559_Y - connect \$8 $reduce_or$libresoc.v:166653$10560_Y - connect \en_o \$11 - connect \o { \t2 \t1 \t0 } - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:166664.1-166685.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" -attribute \generator "nMigen" -module \rdpick_XER_xer_ov - attribute \src "libresoc.v:166679.17-166679.89" - wire $not$libresoc.v:166679$10561_Y - attribute \src "libresoc.v:166680.17-166680.89" - wire $reduce_or$libresoc.v:166680$10562_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166679$10561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:166679$10561_Y + attribute \src "libresoc.v:26889.3-26913.6" + process $proc$libresoc.v:26889$591 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:26890.5-26890.29" + switch \initial + attribute \src "libresoc.v:26890.9-26890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:26914.3-26938.6" + process $proc$libresoc.v:26914$592 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:26915.5-26915.29" + switch \initial + attribute \src "libresoc.v:26915.9-26915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:26939.3-26963.6" + process $proc$libresoc.v:26939$593 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:26940.5-26940.29" + switch \initial + attribute \src "libresoc.v:26940.9-26940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166680$10562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166680$10562_Y + attribute \src "libresoc.v:26964.3-26988.6" + process $proc$libresoc.v:26964$594 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:26965.5-26965.29" + switch \initial + attribute \src "libresoc.v:26965.9-26965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - connect \$1 $not$libresoc.v:166679$10561_Y - connect \$3 $reduce_or$libresoc.v:166680$10562_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:166689.1-166755.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" -attribute \generator "nMigen" -module \rdpick_XER_xer_so - attribute \src "libresoc.v:166734.17-166734.91" - wire $not$libresoc.v:166734$10563_Y - attribute \src "libresoc.v:166736.18-166736.93" - wire $not$libresoc.v:166736$10565_Y - attribute \src "libresoc.v:166738.18-166738.93" - wire $not$libresoc.v:166738$10567_Y - attribute \src "libresoc.v:166739.17-166739.89" - wire width 6 $not$libresoc.v:166739$10568_Y - attribute \src "libresoc.v:166741.18-166741.93" - wire $not$libresoc.v:166741$10570_Y - attribute \src "libresoc.v:166744.17-166744.91" - wire $not$libresoc.v:166744$10573_Y - attribute \src "libresoc.v:166735.18-166735.106" - wire $reduce_or$libresoc.v:166735$10564_Y - attribute \src "libresoc.v:166737.18-166737.106" - wire $reduce_or$libresoc.v:166737$10566_Y - attribute \src "libresoc.v:166740.18-166740.106" - wire $reduce_or$libresoc.v:166740$10569_Y - attribute \src "libresoc.v:166742.18-166742.90" - wire $reduce_or$libresoc.v:166742$10571_Y - attribute \src "libresoc.v:166743.17-166743.103" - wire $reduce_or$libresoc.v:166743$10572_Y - attribute \src "libresoc.v:166745.17-166745.105" - wire $reduce_or$libresoc.v:166745$10574_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166734$10563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:166734$10563_Y + attribute \src "libresoc.v:26989.3-27013.6" + process $proc$libresoc.v:26989$595 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:26990.5-26990.29" + switch \initial + attribute \src "libresoc.v:26990.9-26990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166736$10565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:166736$10565_Y + attribute \src "libresoc.v:27014.3-27038.6" + process $proc$libresoc.v:27014$596 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:27015.5-27015.29" + switch \initial + attribute \src "libresoc.v:27015.9-27015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166738$10567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:166738$10567_Y + attribute \src "libresoc.v:27039.3-27063.6" + process $proc$libresoc.v:27039$597 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:27040.5-27040.29" + switch \initial + attribute \src "libresoc.v:27040.9-27040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:166739$10568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \i - connect \Y $not$libresoc.v:166739$10568_Y + attribute \src "libresoc.v:27064.3-27088.6" + process $proc$libresoc.v:27064$598 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:27065.5-27065.29" + switch \initial + attribute \src "libresoc.v:27065.9-27065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166741$10570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:166741$10570_Y + attribute \src "libresoc.v:27089.3-27113.6" + process $proc$libresoc.v:27089$599 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:27090.5-27090.29" + switch \initial + attribute \src "libresoc.v:27090.9-27090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:166744$10573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:166744$10573_Y + attribute \src "libresoc.v:27114.3-27138.6" + process $proc$libresoc.v:27114$600 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:27115.5-27115.29" + switch \initial + attribute \src "libresoc.v:27115.9-27115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166735$10564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:166735$10564_Y + attribute \src "libresoc.v:27139.3-27163.6" + process $proc$libresoc.v:27139$601 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:27140.5-27140.29" + switch \initial + attribute \src "libresoc.v:27140.9-27140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166737$10566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:166737$10566_Y + attribute \src "libresoc.v:27164.3-27188.6" + process $proc$libresoc.v:27164$602 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:27165.5-27165.29" + switch \initial + attribute \src "libresoc.v:27165.9-27165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166740$10569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:166740$10569_Y + attribute \src "libresoc.v:27189.3-27213.6" + process $proc$libresoc.v:27189$603 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:27190.5-27190.29" + switch \initial + attribute \src "libresoc.v:27190.9-27190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:166742$10571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:166742$10571_Y + attribute \src "libresoc.v:27214.3-27238.6" + process $proc$libresoc.v:27214$604 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:27215.5-27215.29" + switch \initial + attribute \src "libresoc.v:27215.9-27215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166743$10572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:166743$10572_Y + attribute \src "libresoc.v:27239.3-27263.6" + process $proc$libresoc.v:27239$605 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:27240.5-27240.29" + switch \initial + attribute \src "libresoc.v:27240.9-27240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:166745$10574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:166745$10574_Y - end - connect \$7 $not$libresoc.v:166734$10563_Y - connect \$12 $reduce_or$libresoc.v:166735$10564_Y - connect \$11 $not$libresoc.v:166736$10565_Y - connect \$16 $reduce_or$libresoc.v:166737$10566_Y - connect \$15 $not$libresoc.v:166738$10567_Y - connect \$1 $not$libresoc.v:166739$10568_Y - connect \$20 $reduce_or$libresoc.v:166740$10569_Y - connect \$19 $not$libresoc.v:166741$10570_Y - connect \$23 $reduce_or$libresoc.v:166742$10571_Y - connect \$4 $reduce_or$libresoc.v:166743$10572_Y - connect \$3 $not$libresoc.v:166744$10573_Y - connect \$8 $reduce_or$libresoc.v:166745$10574_Y - connect \en_o \$23 - connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:166759.1-167230.10" +attribute \src "libresoc.v:27269.1-28686.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" -module \reg_0 - attribute \src "libresoc.v:166760.7-166760.20" +module \dec31_dec_sub21 + attribute \src "libresoc.v:28311.3-28341.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27919.3-27967.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28587.3-28635.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28636.3-28684.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27723.3-27771.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27870.3-27918.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28342.3-28390.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27527.3-27575.6" + wire width 12 $0\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28391.3-28439.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28440.3-28488.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28489.3-28537.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28066.3-28114.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27772.3-27820.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27821.3-27869.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:28115.3-28163.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27576.3-27624.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28213.3-28261.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28538.3-28586.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27674.3-27722.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:28017.3-28065.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28262.3-28310.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28164.3-28212.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:27968.3-28016.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27625.3-27673.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27270.7-27270.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167090.3-167129.6" - wire width 4 $0\r0__data_o$next[3:0]$10630 - attribute \src "libresoc.v:166845.3-166846.37" - wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:167160.3-167199.6" - wire width 4 $0\r20__data_o$next[3:0]$10644 - attribute \src "libresoc.v:166843.3-166844.39" - wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:166923.3-166949.6" - wire width 4 $0\reg$next[3:0]$10596 - attribute \src "libresoc.v:166841.3-166842.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:166853.3-166892.6" - wire width 4 $0\src10__data_o$next[3:0]$10587 - attribute \src "libresoc.v:166851.3-166852.43" - wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:166950.3-166989.6" - wire width 4 $0\src20__data_o$next[3:0]$10602 - attribute \src "libresoc.v:166849.3-166850.43" - wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:167020.3-167059.6" - wire width 4 $0\src30__data_o$next[3:0]$10616 - attribute \src "libresoc.v:166847.3-166848.43" - wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:167130.3-167159.6" - wire $0\wr_detect$10[0:0]$10638 - attribute \src "libresoc.v:167200.3-167229.6" - wire $0\wr_detect$13[0:0]$10652 - attribute \src "libresoc.v:166990.3-167019.6" - wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest20__wen - attribute \src "libresoc.v:166760.7-166760.15" + attribute \src "libresoc.v:28311.3-28341.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:27919.3-27967.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:28587.3-28635.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28636.3-28684.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:27723.3-27771.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27870.3-27918.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:28342.3-28390.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:27527.3-27575.6" + wire width 12 $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:28391.3-28439.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28440.3-28488.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28489.3-28537.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28066.3-28114.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:27772.3-27820.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27821.3-27869.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:28115.3-28163.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:27576.3-27624.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:28213.3-28261.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28538.3-28586.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:27674.3-27722.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:28017.3-28065.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28262.3-28310.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28164.3-28212.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:27968.3-28016.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27625.3-27673.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub21_upd + attribute \src "libresoc.v:27270.7-27270.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r20__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src10__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166836$10575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:166836$10575_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166837$10576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:166837$10576_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166838$10577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:166838$10577_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166839$10578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:166839$10578_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:27270.7-27270.20" + process $proc$libresoc.v:27270$631 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:166840$10579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:166840$10579_Y + attribute \src "libresoc.v:27527.3-27575.6" + process $proc$libresoc.v:27527$607 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "libresoc.v:27528.5-27528.29" + switch \initial + attribute \src "libresoc.v:27528.9-27528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] end - attribute \src "libresoc.v:166760.7-166760.20" - process $proc$libresoc.v:166760$10657 + attribute \src "libresoc.v:27576.3-27624.6" + process $proc$libresoc.v:27576$608 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:27577.5-27577.29" + switch \initial + attribute \src "libresoc.v:27577.9-27577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:166785.13-166785.30" - process $proc$libresoc.v:166785$10658 + attribute \src "libresoc.v:27625.3-27673.6" + process $proc$libresoc.v:27625$609 + assign { } { } assign { } { } - assign $1\r0__data_o[3:0] 4'0000 + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:27626.5-27626.29" + switch \initial + attribute \src "libresoc.v:27626.9-27626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end sync always - sync init - update \r0__data_o $1\r0__data_o[3:0] + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:166792.13-166792.31" - process $proc$libresoc.v:166792$10659 + attribute \src "libresoc.v:27674.3-27722.6" + process $proc$libresoc.v:27674$610 assign { } { } - assign $1\r20__data_o[3:0] 4'0000 + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:27675.5-27675.29" + switch \initial + attribute \src "libresoc.v:27675.9-27675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end sync always - sync init - update \r20__data_o $1\r20__data_o[3:0] + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:166798.13-166798.25" - process $proc$libresoc.v:166798$10660 + attribute \src "libresoc.v:27723.3-27771.6" + process $proc$libresoc.v:27723$611 + assign { } { } assign { } { } - assign $1\reg[3:0] 4'0000 + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:27724.5-27724.29" + switch \initial + attribute \src "libresoc.v:27724.9-27724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end sync always - sync init - update \reg $1\reg[3:0] + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:166803.13-166803.33" - process $proc$libresoc.v:166803$10661 + attribute \src "libresoc.v:27772.3-27820.6" + process $proc$libresoc.v:27772$612 assign { } { } - assign $1\src10__data_o[3:0] 4'0000 + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:27773.5-27773.29" + switch \initial + attribute \src "libresoc.v:27773.9-27773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end sync always - sync init - update \src10__data_o $1\src10__data_o[3:0] + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:166810.13-166810.33" - process $proc$libresoc.v:166810$10662 + attribute \src "libresoc.v:27821.3-27869.6" + process $proc$libresoc.v:27821$613 + assign { } { } assign { } { } - assign $1\src20__data_o[3:0] 4'0000 + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:27822.5-27822.29" + switch \initial + attribute \src "libresoc.v:27822.9-27822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end sync always - sync init - update \src20__data_o $1\src20__data_o[3:0] + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:166817.13-166817.33" - process $proc$libresoc.v:166817$10663 + attribute \src "libresoc.v:27870.3-27918.6" + process $proc$libresoc.v:27870$614 assign { } { } - assign $1\src30__data_o[3:0] 4'0000 + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:27871.5-27871.29" + switch \initial + attribute \src "libresoc.v:27871.9-27871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end sync always - sync init - update \src30__data_o $1\src30__data_o[3:0] + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:166841.3-166842.25" - process $proc$libresoc.v:166841$10580 + attribute \src "libresoc.v:27919.3-27967.6" + process $proc$libresoc.v:27919$615 assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:166843.3-166844.39" - process $proc$libresoc.v:166843$10581 assign { } { } - assign $0\r20__data_o[3:0] \r20__data_o$next - sync posedge \coresync_clk - update \r20__data_o $0\r20__data_o[3:0] + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:27920.5-27920.29" + switch \initial + attribute \src "libresoc.v:27920.9-27920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:166845.3-166846.37" - process $proc$libresoc.v:166845$10582 + attribute \src "libresoc.v:27968.3-28016.6" + process $proc$libresoc.v:27968$616 assign { } { } - assign $0\r0__data_o[3:0] \r0__data_o$next - sync posedge \coresync_clk - update \r0__data_o $0\r0__data_o[3:0] - end - attribute \src "libresoc.v:166847.3-166848.43" - process $proc$libresoc.v:166847$10583 assign { } { } - assign $0\src30__data_o[3:0] \src30__data_o$next - sync posedge \coresync_clk - update \src30__data_o $0\src30__data_o[3:0] + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:27969.5-27969.29" + switch \initial + attribute \src "libresoc.v:27969.9-27969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:166849.3-166850.43" - process $proc$libresoc.v:166849$10584 + attribute \src "libresoc.v:28017.3-28065.6" + process $proc$libresoc.v:28017$617 assign { } { } - assign $0\src20__data_o[3:0] \src20__data_o$next - sync posedge \coresync_clk - update \src20__data_o $0\src20__data_o[3:0] - end - attribute \src "libresoc.v:166851.3-166852.43" - process $proc$libresoc.v:166851$10585 assign { } { } - assign $0\src10__data_o[3:0] \src10__data_o$next - sync posedge \coresync_clk - update \src10__data_o $0\src10__data_o[3:0] + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:28018.5-28018.29" + switch \initial + attribute \src "libresoc.v:28018.9-28018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:166853.3-166892.6" - process $proc$libresoc.v:166853$10586 + attribute \src "libresoc.v:28066.3-28114.6" + process $proc$libresoc.v:28066$618 assign { } { } assign { } { } - assign { } { } - assign $0\src10__data_o$next[3:0]$10587 $6\src10__data_o$next[3:0]$10593 - attribute \src "libresoc.v:166854.5-166854.29" + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:28067.5-28067.29" switch \initial - attribute \src "libresoc.v:166854.9-166854.17" + attribute \src "libresoc.v:28067.9-28067.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\src10__data_o$next[3:0]$10588 $5\src10__data_o$next[3:0]$10592 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src10__data_o$next[3:0]$10589 \dest10__data_i - case - assign $2\src10__data_o$next[3:0]$10589 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src10__data_o$next[3:0]$10590 \dest20__data_i - case - assign $3\src10__data_o$next[3:0]$10590 $2\src10__data_o$next[3:0]$10589 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src10__data_o$next[3:0]$10591 \w0__data_i - case - assign $4\src10__data_o$next[3:0]$10591 $3\src10__data_o$next[3:0]$10590 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src10__data_o$next[3:0]$10592 \reg - case - assign $5\src10__data_o$next[3:0]$10592 $4\src10__data_o$next[3:0]$10591 - end + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:28115.3-28163.6" + process $proc$libresoc.v:28115$619 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:28116.5-28116.29" + switch \initial + attribute \src "libresoc.v:28116.9-28116.17" + case 1'1 case - assign $1\src10__data_o$next[3:0]$10588 4'0000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $6\src10__data_o$next[3:0]$10593 4'0000 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 case - assign $6\src10__data_o$next[3:0]$10593 $1\src10__data_o$next[3:0]$10588 + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10587 + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:166893.3-166922.6" - process $proc$libresoc.v:166893$10594 + attribute \src "libresoc.v:28164.3-28212.6" + process $proc$libresoc.v:28164$620 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:166894.5-166894.29" + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:28165.5-28165.29" switch \initial - attribute \src "libresoc.v:166894.9-166894.17" + attribute \src "libresoc.v:28165.9-28165.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:166923.3-166949.6" - process $proc$libresoc.v:166923$10595 - assign { } { } + attribute \src "libresoc.v:28213.3-28261.6" + process $proc$libresoc.v:28213$621 assign { } { } assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:28214.5-28214.29" + switch \initial + attribute \src "libresoc.v:28214.9-28214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:28262.3-28310.6" + process $proc$libresoc.v:28262$622 assign { } { } assign { } { } - assign $0\reg$next[3:0]$10596 $4\reg$next[3:0]$10600 - attribute \src "libresoc.v:166924.5-166924.29" + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:28263.5-28263.29" switch \initial - attribute \src "libresoc.v:166924.9-166924.17" + attribute \src "libresoc.v:28263.9-28263.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest10__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\reg$next[3:0]$10597 \dest10__data_i + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:28311.3-28341.6" + process $proc$libresoc.v:28311$623 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:28312.5-28312.29" + switch \initial + attribute \src "libresoc.v:28312.9-28312.17" + case 1'1 case - assign $1\reg$next[3:0]$10597 \reg end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest20__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } - assign $2\reg$next[3:0]$10598 \dest20__data_i - case - assign $2\reg$next[3:0]$10598 $1\reg$next[3:0]$10597 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w0__wen + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00101 assign { } { } - assign $3\reg$next[3:0]$10599 \w0__data_i - case - assign $3\reg$next[3:0]$10599 $2\reg$next[3:0]$10598 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 assign { } { } - assign $4\reg$next[3:0]$10600 4'0000 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 case - assign $4\reg$next[3:0]$10600 $3\reg$next[3:0]$10599 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 end sync always - update \reg$next $0\reg$next[3:0]$10596 + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:166950.3-166989.6" - process $proc$libresoc.v:166950$10601 - assign { } { } + attribute \src "libresoc.v:28342.3-28390.6" + process $proc$libresoc.v:28342$624 assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10602 $6\src20__data_o$next[3:0]$10608 - attribute \src "libresoc.v:166951.5-166951.29" + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:28343.5-28343.29" switch \initial - attribute \src "libresoc.v:166951.9-166951.17" + attribute \src "libresoc.v:28343.9-28343.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\src20__data_o$next[3:0]$10603 $5\src20__data_o$next[3:0]$10607 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src20__data_o$next[3:0]$10604 \dest10__data_i - case - assign $2\src20__data_o$next[3:0]$10604 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src20__data_o$next[3:0]$10605 \dest20__data_i - case - assign $3\src20__data_o$next[3:0]$10605 $2\src20__data_o$next[3:0]$10604 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src20__data_o$next[3:0]$10606 \w0__data_i - case - assign $4\src20__data_o$next[3:0]$10606 $3\src20__data_o$next[3:0]$10605 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src20__data_o$next[3:0]$10607 \reg - case - assign $5\src20__data_o$next[3:0]$10607 $4\src20__data_o$next[3:0]$10606 - end - case - assign $1\src20__data_o$next[3:0]$10603 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $6\src20__data_o$next[3:0]$10608 4'0000 - case - assign $6\src20__data_o$next[3:0]$10608 $1\src20__data_o$next[3:0]$10603 - end - sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10602 - end - attribute \src "libresoc.v:166990.3-167019.6" - process $proc$libresoc.v:166990$10609 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10610 $1\wr_detect$4[0:0]$10611 - attribute \src "libresoc.v:166991.5-166991.29" - switch \initial - attribute \src "libresoc.v:166991.9-166991.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + assign $1\dec31_dec_sub21_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01011 assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\wr_detect$4[0:0]$10611 $4\wr_detect$4[0:0]$10614 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10612 1'1 - case - assign $2\wr_detect$4[0:0]$10612 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10613 1'1 - case - assign $3\wr_detect$4[0:0]$10613 $2\wr_detect$4[0:0]$10612 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10614 1'1 - case - assign $4\wr_detect$4[0:0]$10614 $3\wr_detect$4[0:0]$10613 - end + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 case - assign $1\wr_detect$4[0:0]$10611 1'0 + assign $1\dec31_dec_sub21_form[4:0] 5'00000 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10610 + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:167020.3-167059.6" - process $proc$libresoc.v:167020$10615 + attribute \src "libresoc.v:28391.3-28439.6" + process $proc$libresoc.v:28391$625 assign { } { } assign { } { } - assign { } { } - assign $0\src30__data_o$next[3:0]$10616 $6\src30__data_o$next[3:0]$10622 - attribute \src "libresoc.v:167021.5-167021.29" + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:28392.5-28392.29" switch \initial - attribute \src "libresoc.v:167021.9-167021.17" + attribute \src "libresoc.v:28392.9-28392.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\src30__data_o$next[3:0]$10617 $5\src30__data_o$next[3:0]$10621 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src30__data_o$next[3:0]$10618 \dest10__data_i - case - assign $2\src30__data_o$next[3:0]$10618 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src30__data_o$next[3:0]$10619 \dest20__data_i - case - assign $3\src30__data_o$next[3:0]$10619 $2\src30__data_o$next[3:0]$10618 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src30__data_o$next[3:0]$10620 \w0__data_i - case - assign $4\src30__data_o$next[3:0]$10620 $3\src30__data_o$next[3:0]$10619 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src30__data_o$next[3:0]$10621 \reg - case - assign $5\src30__data_o$next[3:0]$10621 $4\src30__data_o$next[3:0]$10620 - end - case - assign $1\src30__data_o$next[3:0]$10617 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $6\src30__data_o$next[3:0]$10622 4'0000 + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 case - assign $6\src30__data_o$next[3:0]$10622 $1\src30__data_o$next[3:0]$10617 + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10616 + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:167060.3-167089.6" - process $proc$libresoc.v:167060$10623 + attribute \src "libresoc.v:28440.3-28488.6" + process $proc$libresoc.v:28440$626 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10624 $1\wr_detect$7[0:0]$10625 - attribute \src "libresoc.v:167061.5-167061.29" + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:28441.5-28441.29" switch \initial - attribute \src "libresoc.v:167061.9-167061.17" + attribute \src "libresoc.v:28441.9-28441.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\wr_detect$7[0:0]$10625 $4\wr_detect$7[0:0]$10628 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10626 1'1 - case - assign $2\wr_detect$7[0:0]$10626 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10627 1'1 - case - assign $3\wr_detect$7[0:0]$10627 $2\wr_detect$7[0:0]$10626 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10628 1'1 - case - assign $4\wr_detect$7[0:0]$10628 $3\wr_detect$7[0:0]$10627 - end + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 case - assign $1\wr_detect$7[0:0]$10625 1'0 + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10624 + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:167090.3-167129.6" - process $proc$libresoc.v:167090$10629 - assign { } { } + attribute \src "libresoc.v:28489.3-28537.6" + process $proc$libresoc.v:28489$627 assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10630 $6\r0__data_o$next[3:0]$10636 - attribute \src "libresoc.v:167091.5-167091.29" + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:28490.5-28490.29" switch \initial - attribute \src "libresoc.v:167091.9-167091.17" + attribute \src "libresoc.v:28490.9-28490.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\r0__data_o$next[3:0]$10631 $5\r0__data_o$next[3:0]$10635 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r0__data_o$next[3:0]$10632 \dest10__data_i - case - assign $2\r0__data_o$next[3:0]$10632 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r0__data_o$next[3:0]$10633 \dest20__data_i - case - assign $3\r0__data_o$next[3:0]$10633 $2\r0__data_o$next[3:0]$10632 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r0__data_o$next[3:0]$10634 \w0__data_i - case - assign $4\r0__data_o$next[3:0]$10634 $3\r0__data_o$next[3:0]$10633 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r0__data_o$next[3:0]$10635 \reg - case - assign $5\r0__data_o$next[3:0]$10635 $4\r0__data_o$next[3:0]$10634 - end - case - assign $1\r0__data_o$next[3:0]$10631 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01011 assign { } { } - assign $6\r0__data_o$next[3:0]$10636 4'0000 + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 case - assign $6\r0__data_o$next[3:0]$10636 $1\r0__data_o$next[3:0]$10631 + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10630 + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:167130.3-167159.6" - process $proc$libresoc.v:167130$10637 + attribute \src "libresoc.v:28538.3-28586.6" + process $proc$libresoc.v:28538$628 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10638 $1\wr_detect$10[0:0]$10639 - attribute \src "libresoc.v:167131.5-167131.29" + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:28539.5-28539.29" switch \initial - attribute \src "libresoc.v:167131.9-167131.17" + attribute \src "libresoc.v:28539.9-28539.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\wr_detect$10[0:0]$10639 $4\wr_detect$10[0:0]$10642 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10640 1'1 - case - assign $2\wr_detect$10[0:0]$10640 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10641 1'1 - case - assign $3\wr_detect$10[0:0]$10641 $2\wr_detect$10[0:0]$10640 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10642 1'1 - case - assign $4\wr_detect$10[0:0]$10642 $3\wr_detect$10[0:0]$10641 - end + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 case - assign $1\wr_detect$10[0:0]$10639 1'0 + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10638 + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] end - attribute \src "libresoc.v:167160.3-167199.6" - process $proc$libresoc.v:167160$10643 - assign { } { } + attribute \src "libresoc.v:28587.3-28635.6" + process $proc$libresoc.v:28587$629 assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10644 $6\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:167161.5-167161.29" + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:28588.5-28588.29" switch \initial - attribute \src "libresoc.v:167161.9-167161.17" + attribute \src "libresoc.v:28588.9-28588.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\r20__data_o$next[3:0]$10645 $5\r20__data_o$next[3:0]$10649 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r20__data_o$next[3:0]$10646 \dest10__data_i - case - assign $2\r20__data_o$next[3:0]$10646 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r20__data_o$next[3:0]$10647 \dest20__data_i - case - assign $3\r20__data_o$next[3:0]$10647 $2\r20__data_o$next[3:0]$10646 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r20__data_o$next[3:0]$10648 \w0__data_i - case - assign $4\r20__data_o$next[3:0]$10648 $3\r20__data_o$next[3:0]$10647 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r20__data_o$next[3:0]$10649 \reg - case - assign $5\r20__data_o$next[3:0]$10649 $4\r20__data_o$next[3:0]$10648 - end - case - assign $1\r20__data_o$next[3:0]$10645 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $6\r20__data_o$next[3:0]$10650 4'0000 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 case - assign $6\r20__data_o$next[3:0]$10650 $1\r20__data_o$next[3:0]$10645 + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10644 + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:167200.3-167229.6" - process $proc$libresoc.v:167200$10651 + attribute \src "libresoc.v:28636.3-28684.6" + process $proc$libresoc.v:28636$630 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10652 $1\wr_detect$13[0:0]$10653 - attribute \src "libresoc.v:167201.5-167201.29" + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:28637.5-28637.29" switch \initial - attribute \src "libresoc.v:167201.9-167201.17" + attribute \src "libresoc.v:28637.9-28637.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r20__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11010 assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\wr_detect$13[0:0]$10653 $4\wr_detect$13[0:0]$10656 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10654 1'1 - case - assign $2\wr_detect$13[0:0]$10654 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10655 1'1 - case - assign $3\wr_detect$13[0:0]$10655 $2\wr_detect$13[0:0]$10654 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10656 1'1 - case - assign $4\wr_detect$13[0:0]$10656 $3\wr_detect$13[0:0]$10655 - end + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 case - assign $1\wr_detect$13[0:0]$10653 1'0 + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10652 + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - connect \$9 $not$libresoc.v:166836$10575_Y - connect \$12 $not$libresoc.v:166837$10576_Y - connect \$1 $not$libresoc.v:166838$10577_Y - connect \$3 $not$libresoc.v:166839$10578_Y - connect \$6 $not$libresoc.v:166840$10579_Y + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:167234.1-167679.10" +attribute \src "libresoc.v:28690.1-30269.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" -module \reg_0$132 - attribute \src "libresoc.v:167235.7-167235.20" +module \dec31_dec_sub22 + attribute \src "libresoc.v:29223.3-29277.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29443.3-29497.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30158.3-30212.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30213.3-30267.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29168.3-29222.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29388.3-29442.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29883.3-29937.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:28948.3-29002.6" + wire width 12 $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29938.3-29992.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29993.3-30047.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:30048.3-30102.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29553.3-29607.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29278.3-29332.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29333.3-29387.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29663.3-29717.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29003.3-29057.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29773.3-29827.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:30103.3-30157.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:29113.3-29167.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29608.3-29662.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29828.3-29882.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29718.3-29772.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29498.3-29552.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29058.3-29112.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:28691.7-28691.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $0\r0__data_o$next[1:0]$10716 - attribute \src "libresoc.v:167310.3-167311.37" - wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:167646.3-167678.6" - wire width 2 $0\reg$next[1:0]$10732 - attribute \src "libresoc.v:167308.3-167309.25" - wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $0\src10__data_o$next[1:0]$10674 - attribute \src "libresoc.v:167316.3-167317.43" - wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $0\src20__data_o$next[1:0]$10684 - attribute \src "libresoc.v:167314.3-167315.43" - wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $0\src30__data_o$next[1:0]$10700 - attribute \src "libresoc.v:167312.3-167313.43" - wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:167610.3-167645.6" - wire $0\wr_detect$10[0:0]$10725 - attribute \src "libresoc.v:167446.3-167481.6" - wire $0\wr_detect$4[0:0]$10693 - attribute \src "libresoc.v:167528.3-167563.6" - wire $0\wr_detect$7[0:0]$10709 - attribute \src "libresoc.v:167364.3-167399.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $1\r0__data_o$next[1:0]$10717 - attribute \src "libresoc.v:167262.13-167262.30" - wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:167646.3-167678.6" - wire width 2 $1\reg$next[1:0]$10733 - attribute \src "libresoc.v:167268.13-167268.25" - wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $1\src10__data_o$next[1:0]$10675 - attribute \src "libresoc.v:167273.13-167273.33" - wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $1\src20__data_o$next[1:0]$10685 - attribute \src "libresoc.v:167280.13-167280.33" - wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $1\src30__data_o$next[1:0]$10701 - attribute \src "libresoc.v:167287.13-167287.33" - wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:167610.3-167645.6" - wire $1\wr_detect$10[0:0]$10726 - attribute \src "libresoc.v:167446.3-167481.6" - wire $1\wr_detect$4[0:0]$10694 - attribute \src "libresoc.v:167528.3-167563.6" - wire $1\wr_detect$7[0:0]$10710 - attribute \src "libresoc.v:167364.3-167399.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $2\r0__data_o$next[1:0]$10718 - attribute \src "libresoc.v:167646.3-167678.6" - wire width 2 $2\reg$next[1:0]$10734 - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $2\src10__data_o$next[1:0]$10676 - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $2\src20__data_o$next[1:0]$10686 - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $2\src30__data_o$next[1:0]$10702 - attribute \src "libresoc.v:167610.3-167645.6" - wire $2\wr_detect$10[0:0]$10727 - attribute \src "libresoc.v:167446.3-167481.6" - wire $2\wr_detect$4[0:0]$10695 - attribute \src "libresoc.v:167528.3-167563.6" - wire $2\wr_detect$7[0:0]$10711 - attribute \src "libresoc.v:167364.3-167399.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $3\r0__data_o$next[1:0]$10719 - attribute \src "libresoc.v:167646.3-167678.6" - wire width 2 $3\reg$next[1:0]$10735 - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $3\src10__data_o$next[1:0]$10677 - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $3\src20__data_o$next[1:0]$10687 - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $3\src30__data_o$next[1:0]$10703 - attribute \src "libresoc.v:167610.3-167645.6" - wire $3\wr_detect$10[0:0]$10728 - attribute \src "libresoc.v:167446.3-167481.6" - wire $3\wr_detect$4[0:0]$10696 - attribute \src "libresoc.v:167528.3-167563.6" - wire $3\wr_detect$7[0:0]$10712 - attribute \src "libresoc.v:167364.3-167399.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $4\r0__data_o$next[1:0]$10720 - attribute \src "libresoc.v:167646.3-167678.6" - wire width 2 $4\reg$next[1:0]$10736 - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $4\src10__data_o$next[1:0]$10678 - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $4\src20__data_o$next[1:0]$10688 - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $4\src30__data_o$next[1:0]$10704 - attribute \src "libresoc.v:167610.3-167645.6" - wire $4\wr_detect$10[0:0]$10729 - attribute \src "libresoc.v:167446.3-167481.6" - wire $4\wr_detect$4[0:0]$10697 - attribute \src "libresoc.v:167528.3-167563.6" - wire $4\wr_detect$7[0:0]$10713 - attribute \src "libresoc.v:167364.3-167399.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $5\r0__data_o$next[1:0]$10721 - attribute \src "libresoc.v:167646.3-167678.6" - wire width 2 $5\reg$next[1:0]$10737 - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $5\src10__data_o$next[1:0]$10679 - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $5\src20__data_o$next[1:0]$10689 - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $5\src30__data_o$next[1:0]$10705 - attribute \src "libresoc.v:167610.3-167645.6" - wire $5\wr_detect$10[0:0]$10730 - attribute \src "libresoc.v:167446.3-167481.6" - wire $5\wr_detect$4[0:0]$10698 - attribute \src "libresoc.v:167528.3-167563.6" - wire $5\wr_detect$7[0:0]$10714 - attribute \src "libresoc.v:167364.3-167399.6" - wire $5\wr_detect[0:0] - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $6\r0__data_o$next[1:0]$10722 - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $6\src10__data_o$next[1:0]$10680 - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $6\src20__data_o$next[1:0]$10690 - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $6\src30__data_o$next[1:0]$10706 - attribute \src "libresoc.v:167564.3-167609.6" - wire width 2 $7\r0__data_o$next[1:0]$10723 - attribute \src "libresoc.v:167318.3-167363.6" - wire width 2 $7\src10__data_o$next[1:0]$10681 - attribute \src "libresoc.v:167400.3-167445.6" - wire width 2 $7\src20__data_o$next[1:0]$10691 - attribute \src "libresoc.v:167482.3-167527.6" - wire width 2 $7\src30__data_o$next[1:0]$10707 - attribute \src "libresoc.v:167304.17-167304.104" - wire $not$libresoc.v:167304$10664_Y - attribute \src "libresoc.v:167305.17-167305.100" - wire $not$libresoc.v:167305$10665_Y - attribute \src "libresoc.v:167306.17-167306.103" - wire $not$libresoc.v:167306$10666_Y - attribute \src "libresoc.v:167307.17-167307.103" - wire $not$libresoc.v:167307$10667_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \dest30__wen - attribute \src "libresoc.v:167235.7-167235.15" + attribute \src "libresoc.v:29223.3-29277.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29443.3-29497.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:30158.3-30212.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30213.3-30267.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:29168.3-29222.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29388.3-29442.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29883.3-29937.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:28948.3-29002.6" + wire width 12 $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:29938.3-29992.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29993.3-30047.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:30048.3-30102.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:29553.3-29607.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29278.3-29332.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29333.3-29387.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29663.3-29717.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29003.3-29057.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29773.3-29827.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:30103.3-30157.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:29113.3-29167.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29608.3-29662.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29828.3-29882.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29718.3-29772.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29498.3-29552.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29058.3-29112.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub22_upd + attribute \src "libresoc.v:28691.7-28691.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src10__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167304$10664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:167304$10664_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167305$10665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:167305$10665_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167306$10666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167306$10666_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167307$10667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:167307$10667_Y - end - attribute \src "libresoc.v:167235.7-167235.20" - process $proc$libresoc.v:167235$10738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:28691.7-28691.20" + process $proc$libresoc.v:28691$656 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167262.13-167262.30" - process $proc$libresoc.v:167262$10739 - assign { } { } - assign $1\r0__data_o[1:0] 2'00 - sync always - sync init - update \r0__data_o $1\r0__data_o[1:0] - end - attribute \src "libresoc.v:167268.13-167268.25" - process $proc$libresoc.v:167268$10740 - assign { } { } - assign $1\reg[1:0] 2'00 - sync always - sync init - update \reg $1\reg[1:0] - end - attribute \src "libresoc.v:167273.13-167273.33" - process $proc$libresoc.v:167273$10741 - assign { } { } - assign $1\src10__data_o[1:0] 2'00 - sync always - sync init - update \src10__data_o $1\src10__data_o[1:0] - end - attribute \src "libresoc.v:167280.13-167280.33" - process $proc$libresoc.v:167280$10742 - assign { } { } - assign $1\src20__data_o[1:0] 2'00 - sync always - sync init - update \src20__data_o $1\src20__data_o[1:0] - end - attribute \src "libresoc.v:167287.13-167287.33" - process $proc$libresoc.v:167287$10743 - assign { } { } - assign $1\src30__data_o[1:0] 2'00 - sync always - sync init - update \src30__data_o $1\src30__data_o[1:0] - end - attribute \src "libresoc.v:167308.3-167309.25" - process $proc$libresoc.v:167308$10668 - assign { } { } - assign $0\reg[1:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[1:0] - end - attribute \src "libresoc.v:167310.3-167311.37" - process $proc$libresoc.v:167310$10669 + attribute \src "libresoc.v:28948.3-29002.6" + process $proc$libresoc.v:28948$632 assign { } { } - assign $0\r0__data_o[1:0] \r0__data_o$next - sync posedge \coresync_clk - update \r0__data_o $0\r0__data_o[1:0] - end - attribute \src "libresoc.v:167312.3-167313.43" - process $proc$libresoc.v:167312$10670 - assign { } { } - assign $0\src30__data_o[1:0] \src30__data_o$next - sync posedge \coresync_clk - update \src30__data_o $0\src30__data_o[1:0] - end - attribute \src "libresoc.v:167314.3-167315.43" - process $proc$libresoc.v:167314$10671 - assign { } { } - assign $0\src20__data_o[1:0] \src20__data_o$next - sync posedge \coresync_clk - update \src20__data_o $0\src20__data_o[1:0] - end - attribute \src "libresoc.v:167316.3-167317.43" - process $proc$libresoc.v:167316$10672 assign { } { } - assign $0\src10__data_o[1:0] \src10__data_o$next - sync posedge \coresync_clk - update \src10__data_o $0\src10__data_o[1:0] - end - attribute \src "libresoc.v:167318.3-167363.6" - process $proc$libresoc.v:167318$10673 - assign { } { } - assign { } { } - assign { } { } - assign $0\src10__data_o$next[1:0]$10674 $7\src10__data_o$next[1:0]$10681 - attribute \src "libresoc.v:167319.5-167319.29" + assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "libresoc.v:28949.5-28949.29" switch \initial - attribute \src "libresoc.v:167319.9-167319.17" + attribute \src "libresoc.v:28949.9-28949.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\src10__data_o$next[1:0]$10675 $6\src10__data_o$next[1:0]$10680 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src10__data_o$next[1:0]$10676 \dest10__data_i - case - assign $2\src10__data_o$next[1:0]$10676 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src10__data_o$next[1:0]$10677 \dest20__data_i - case - assign $3\src10__data_o$next[1:0]$10677 $2\src10__data_o$next[1:0]$10676 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src10__data_o$next[1:0]$10678 \dest30__data_i - case - assign $4\src10__data_o$next[1:0]$10678 $3\src10__data_o$next[1:0]$10677 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src10__data_o$next[1:0]$10679 \w0__data_i - case - assign $5\src10__data_o$next[1:0]$10679 $4\src10__data_o$next[1:0]$10678 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src10__data_o$next[1:0]$10680 \reg - case - assign $6\src10__data_o$next[1:0]$10680 $5\src10__data_o$next[1:0]$10679 - end - case - assign $1\src10__data_o$next[1:0]$10675 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_function_unit[11:0] 12'100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $7\src10__data_o$next[1:0]$10681 2'00 + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 case - assign $7\src10__data_o$next[1:0]$10681 $1\src10__data_o$next[1:0]$10675 + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10674 + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] end - attribute \src "libresoc.v:167364.3-167399.6" - process $proc$libresoc.v:167364$10682 + attribute \src "libresoc.v:29003.3-29057.6" + process $proc$libresoc.v:29003$633 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:167365.5-167365.29" + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:29004.5-29004.29" switch \initial - attribute \src "libresoc.v:167365.9-167365.17" + attribute \src "libresoc.v:29004.9-29004.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src10__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\wr_detect[0:0] $5\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect[0:0] 1'1 - case - assign $5\wr_detect[0:0] $4\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "libresoc.v:167400.3-167445.6" - process $proc$libresoc.v:167400$10683 - assign { } { } - assign { } { } - assign { } { } - assign $0\src20__data_o$next[1:0]$10684 $7\src20__data_o$next[1:0]$10691 - attribute \src "libresoc.v:167401.5-167401.29" - switch \initial - attribute \src "libresoc.v:167401.9-167401.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\src20__data_o$next[1:0]$10685 $6\src20__data_o$next[1:0]$10690 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src20__data_o$next[1:0]$10686 \dest10__data_i - case - assign $2\src20__data_o$next[1:0]$10686 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src20__data_o$next[1:0]$10687 \dest20__data_i - case - assign $3\src20__data_o$next[1:0]$10687 $2\src20__data_o$next[1:0]$10686 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src20__data_o$next[1:0]$10688 \dest30__data_i - case - assign $4\src20__data_o$next[1:0]$10688 $3\src20__data_o$next[1:0]$10687 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src20__data_o$next[1:0]$10689 \w0__data_i - case - assign $5\src20__data_o$next[1:0]$10689 $4\src20__data_o$next[1:0]$10688 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src20__data_o$next[1:0]$10690 \reg - case - assign $6\src20__data_o$next[1:0]$10690 $5\src20__data_o$next[1:0]$10689 - end - case - assign $1\src20__data_o$next[1:0]$10685 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } - assign $7\src20__data_o$next[1:0]$10691 2'00 - case - assign $7\src20__data_o$next[1:0]$10691 $1\src20__data_o$next[1:0]$10685 - end - sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10684 - end - attribute \src "libresoc.v:167446.3-167481.6" - process $proc$libresoc.v:167446$10692 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10693 $1\wr_detect$4[0:0]$10694 - attribute \src "libresoc.v:167447.5-167447.29" - switch \initial - attribute \src "libresoc.v:167447.9-167447.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src20__ren + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11100 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\wr_detect$4[0:0]$10694 $5\wr_detect$4[0:0]$10698 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10695 1'1 - case - assign $2\wr_detect$4[0:0]$10695 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10696 1'1 - case - assign $3\wr_detect$4[0:0]$10696 $2\wr_detect$4[0:0]$10695 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10697 1'1 - case - assign $4\wr_detect$4[0:0]$10697 $3\wr_detect$4[0:0]$10696 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$4[0:0]$10698 1'1 - case - assign $5\wr_detect$4[0:0]$10698 $4\wr_detect$4[0:0]$10697 - end + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 case - assign $1\wr_detect$4[0:0]$10694 1'0 + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10693 + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:167482.3-167527.6" - process $proc$libresoc.v:167482$10699 + attribute \src "libresoc.v:29058.3-29112.6" + process $proc$libresoc.v:29058$634 assign { } { } assign { } { } - assign { } { } - assign $0\src30__data_o$next[1:0]$10700 $7\src30__data_o$next[1:0]$10707 - attribute \src "libresoc.v:167483.5-167483.29" + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:29059.5-29059.29" switch \initial - attribute \src "libresoc.v:167483.9-167483.17" + attribute \src "libresoc.v:29059.9-29059.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\src30__data_o$next[1:0]$10701 $6\src30__data_o$next[1:0]$10706 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src30__data_o$next[1:0]$10702 \dest10__data_i - case - assign $2\src30__data_o$next[1:0]$10702 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src30__data_o$next[1:0]$10703 \dest20__data_i - case - assign $3\src30__data_o$next[1:0]$10703 $2\src30__data_o$next[1:0]$10702 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src30__data_o$next[1:0]$10704 \dest30__data_i - case - assign $4\src30__data_o$next[1:0]$10704 $3\src30__data_o$next[1:0]$10703 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src30__data_o$next[1:0]$10705 \w0__data_i - case - assign $5\src30__data_o$next[1:0]$10705 $4\src30__data_o$next[1:0]$10704 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src30__data_o$next[1:0]$10706 \reg - case - assign $6\src30__data_o$next[1:0]$10706 $5\src30__data_o$next[1:0]$10705 - end - case - assign $1\src30__data_o$next[1:0]$10701 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } - assign $7\src30__data_o$next[1:0]$10707 2'00 - case - assign $7\src30__data_o$next[1:0]$10707 $1\src30__data_o$next[1:0]$10701 - end - sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10700 - end - attribute \src "libresoc.v:167528.3-167563.6" - process $proc$libresoc.v:167528$10708 - assign { } { } - assign { } { } - assign $0\wr_detect$7[0:0]$10709 $1\wr_detect$7[0:0]$10710 - attribute \src "libresoc.v:167529.5-167529.29" - switch \initial - attribute \src "libresoc.v:167529.9-167529.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src30__ren + assign $1\dec31_dec_sub22_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\wr_detect$7[0:0]$10710 $5\wr_detect$7[0:0]$10714 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10711 1'1 - case - assign $2\wr_detect$7[0:0]$10711 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10712 1'1 - case - assign $3\wr_detect$7[0:0]$10712 $2\wr_detect$7[0:0]$10711 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10713 1'1 - case - assign $4\wr_detect$7[0:0]$10713 $3\wr_detect$7[0:0]$10712 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$7[0:0]$10714 1'1 - case - assign $5\wr_detect$7[0:0]$10714 $4\wr_detect$7[0:0]$10713 - end + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 case - assign $1\wr_detect$7[0:0]$10710 1'0 + assign $1\dec31_dec_sub22_upd[1:0] 2'00 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10709 + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:167564.3-167609.6" - process $proc$libresoc.v:167564$10715 + attribute \src "libresoc.v:29113.3-29167.6" + process $proc$libresoc.v:29113$635 assign { } { } assign { } { } - assign { } { } - assign $0\r0__data_o$next[1:0]$10716 $7\r0__data_o$next[1:0]$10723 - attribute \src "libresoc.v:167565.5-167565.29" + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:29114.5-29114.29" switch \initial - attribute \src "libresoc.v:167565.9-167565.17" + attribute \src "libresoc.v:29114.9-29114.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\r0__data_o$next[1:0]$10717 $6\r0__data_o$next[1:0]$10722 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r0__data_o$next[1:0]$10718 \dest10__data_i - case - assign $2\r0__data_o$next[1:0]$10718 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r0__data_o$next[1:0]$10719 \dest20__data_i - case - assign $3\r0__data_o$next[1:0]$10719 $2\r0__data_o$next[1:0]$10718 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r0__data_o$next[1:0]$10720 \dest30__data_i - case - assign $4\r0__data_o$next[1:0]$10720 $3\r0__data_o$next[1:0]$10719 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r0__data_o$next[1:0]$10721 \w0__data_i - case - assign $5\r0__data_o$next[1:0]$10721 $4\r0__data_o$next[1:0]$10720 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r0__data_o$next[1:0]$10722 \reg - case - assign $6\r0__data_o$next[1:0]$10722 $5\r0__data_o$next[1:0]$10721 - end - case - assign $1\r0__data_o$next[1:0]$10717 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } - assign $7\r0__data_o$next[1:0]$10723 2'00 - case - assign $7\r0__data_o$next[1:0]$10723 $1\r0__data_o$next[1:0]$10717 - end - sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10716 - end - attribute \src "libresoc.v:167610.3-167645.6" - process $proc$libresoc.v:167610$10724 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10725 $1\wr_detect$10[0:0]$10726 - attribute \src "libresoc.v:167611.5-167611.29" - switch \initial - attribute \src "libresoc.v:167611.9-167611.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r0__ren + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\wr_detect$10[0:0]$10726 $5\wr_detect$10[0:0]$10730 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10727 1'1 - case - assign $2\wr_detect$10[0:0]$10727 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest20__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10728 1'1 - case - assign $3\wr_detect$10[0:0]$10728 $2\wr_detect$10[0:0]$10727 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest30__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10729 1'1 - case - assign $4\wr_detect$10[0:0]$10729 $3\wr_detect$10[0:0]$10728 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$10[0:0]$10730 1'1 - case - assign $5\wr_detect$10[0:0]$10730 $4\wr_detect$10[0:0]$10729 - end - case - assign $1\wr_detect$10[0:0]$10726 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10725 - end - attribute \src "libresoc.v:167646.3-167678.6" - process $proc$libresoc.v:167646$10731 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[1:0]$10732 $5\reg$next[1:0]$10737 - attribute \src "libresoc.v:167647.5-167647.29" - switch \initial - attribute \src "libresoc.v:167647.9-167647.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest10__wen + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11100 assign { } { } - assign $1\reg$next[1:0]$10733 \dest10__data_i - case - assign $1\reg$next[1:0]$10733 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest20__wen + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10110 assign { } { } - assign $2\reg$next[1:0]$10734 \dest20__data_i - case - assign $2\reg$next[1:0]$10734 $1\reg$next[1:0]$10733 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest30__wen + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10100 assign { } { } - assign $3\reg$next[1:0]$10735 \dest30__data_i - case - assign $3\reg$next[1:0]$10735 $2\reg$next[1:0]$10734 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w0__wen + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 assign { } { } - assign $4\reg$next[1:0]$10736 \w0__data_i - case - assign $4\reg$next[1:0]$10736 $3\reg$next[1:0]$10735 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10010 assign { } { } - assign $5\reg$next[1:0]$10737 2'00 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 case - assign $5\reg$next[1:0]$10737 $4\reg$next[1:0]$10736 + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 end sync always - update \reg$next $0\reg$next[1:0]$10732 - end - connect \$9 $not$libresoc.v:167304$10664_Y - connect \$1 $not$libresoc.v:167305$10665_Y - connect \$3 $not$libresoc.v:167306$10666_Y - connect \$6 $not$libresoc.v:167307$10667_Y -end -attribute \src "libresoc.v:167683.1-167902.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" -attribute \generator "nMigen" -module \reg_0$135 - attribute \src "libresoc.v:167735.3-167774.6" - wire width 64 $0\cia0__data_o$next[63:0]$10750 - attribute \src "libresoc.v:167733.3-167734.41" - wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:167684.7-167684.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:167805.3-167844.6" - wire width 64 $0\msr0__data_o$next[63:0]$10759 - attribute \src "libresoc.v:167731.3-167732.41" - wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:167875.3-167901.6" - wire width 64 $0\reg$next[63:0]$10773 - attribute \src "libresoc.v:167729.3-167730.25" - wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:167845.3-167874.6" - wire $0\wr_detect$4[0:0]$10767 - attribute \src "libresoc.v:167775.3-167804.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:167735.3-167774.6" - wire width 64 $1\cia0__data_o$next[63:0]$10751 - attribute \src "libresoc.v:167691.14-167691.49" - wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:167805.3-167844.6" - wire width 64 $1\msr0__data_o$next[63:0]$10760 - attribute \src "libresoc.v:167708.14-167708.49" - wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:167875.3-167901.6" - wire width 64 $1\reg$next[63:0]$10774 - attribute \src "libresoc.v:167720.14-167720.42" - wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:167845.3-167874.6" - wire $1\wr_detect$4[0:0]$10768 - attribute \src "libresoc.v:167775.3-167804.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:167735.3-167774.6" - wire width 64 $2\cia0__data_o$next[63:0]$10752 - attribute \src "libresoc.v:167805.3-167844.6" - wire width 64 $2\msr0__data_o$next[63:0]$10761 - attribute \src "libresoc.v:167875.3-167901.6" - wire width 64 $2\reg$next[63:0]$10775 - attribute \src "libresoc.v:167845.3-167874.6" - wire $2\wr_detect$4[0:0]$10769 - attribute \src "libresoc.v:167775.3-167804.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:167735.3-167774.6" - wire width 64 $3\cia0__data_o$next[63:0]$10753 - attribute \src "libresoc.v:167805.3-167844.6" - wire width 64 $3\msr0__data_o$next[63:0]$10762 - attribute \src "libresoc.v:167875.3-167901.6" - wire width 64 $3\reg$next[63:0]$10776 - attribute \src "libresoc.v:167845.3-167874.6" - wire $3\wr_detect$4[0:0]$10770 - attribute \src "libresoc.v:167775.3-167804.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:167735.3-167774.6" - wire width 64 $4\cia0__data_o$next[63:0]$10754 - attribute \src "libresoc.v:167805.3-167844.6" - wire width 64 $4\msr0__data_o$next[63:0]$10763 - attribute \src "libresoc.v:167875.3-167901.6" - wire width 64 $4\reg$next[63:0]$10777 - attribute \src "libresoc.v:167845.3-167874.6" - wire $4\wr_detect$4[0:0]$10771 - attribute \src "libresoc.v:167775.3-167804.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:167735.3-167774.6" - wire width 64 $5\cia0__data_o$next[63:0]$10755 - attribute \src "libresoc.v:167805.3-167844.6" - wire width 64 $5\msr0__data_o$next[63:0]$10764 - attribute \src "libresoc.v:167735.3-167774.6" - wire width 64 $6\cia0__data_o$next[63:0]$10756 - attribute \src "libresoc.v:167805.3-167844.6" - wire width 64 $6\msr0__data_o$next[63:0]$10765 - attribute \src "libresoc.v:167727.17-167727.100" - wire $not$libresoc.v:167727$10744_Y - attribute \src "libresoc.v:167728.17-167728.103" - wire $not$libresoc.v:167728$10745_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr10__wen - attribute \src "libresoc.v:167684.7-167684.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167727$10744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:167727$10744_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167728$10745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167728$10745_Y - end - attribute \src "libresoc.v:167684.7-167684.20" - process $proc$libresoc.v:167684$10778 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:167691.14-167691.49" - process $proc$libresoc.v:167691$10779 - assign { } { } - assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia0__data_o $1\cia0__data_o[63:0] - end - attribute \src "libresoc.v:167708.14-167708.49" - process $proc$libresoc.v:167708$10780 - assign { } { } - assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr0__data_o $1\msr0__data_o[63:0] - end - attribute \src "libresoc.v:167720.14-167720.42" - process $proc$libresoc.v:167720$10781 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "libresoc.v:167729.3-167730.25" - process $proc$libresoc.v:167729$10746 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "libresoc.v:167731.3-167732.41" - process $proc$libresoc.v:167731$10747 - assign { } { } - assign $0\msr0__data_o[63:0] \msr0__data_o$next - sync posedge \coresync_clk - update \msr0__data_o $0\msr0__data_o[63:0] - end - attribute \src "libresoc.v:167733.3-167734.41" - process $proc$libresoc.v:167733$10748 - assign { } { } - assign $0\cia0__data_o[63:0] \cia0__data_o$next - sync posedge \coresync_clk - update \cia0__data_o $0\cia0__data_o[63:0] + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:167735.3-167774.6" - process $proc$libresoc.v:167735$10749 - assign { } { } + attribute \src "libresoc.v:29168.3-29222.6" + process $proc$libresoc.v:29168$636 assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10750 $6\cia0__data_o$next[63:0]$10756 - attribute \src "libresoc.v:167736.5-167736.29" + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:29169.5-29169.29" switch \initial - attribute \src "libresoc.v:167736.9-167736.17" + attribute \src "libresoc.v:29169.9-29169.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\cia0__data_o$next[63:0]$10751 $5\cia0__data_o$next[63:0]$10755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia0__data_o$next[63:0]$10752 \nia0__data_i - case - assign $2\cia0__data_o$next[63:0]$10752 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia0__data_o$next[63:0]$10753 \msr0__data_i - case - assign $3\cia0__data_o$next[63:0]$10753 $2\cia0__data_o$next[63:0]$10752 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia0__data_o$next[63:0]$10754 \d_wr10__data_i - case - assign $4\cia0__data_o$next[63:0]$10754 $3\cia0__data_o$next[63:0]$10753 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia0__data_o$next[63:0]$10755 \reg - case - assign $5\cia0__data_o$next[63:0]$10755 $4\cia0__data_o$next[63:0]$10754 - end - case - assign $1\cia0__data_o$next[63:0]$10751 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $6\cia0__data_o$next[63:0]$10756 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 case - assign $6\cia0__data_o$next[63:0]$10756 $1\cia0__data_o$next[63:0]$10751 + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10750 + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:167775.3-167804.6" - process $proc$libresoc.v:167775$10757 + attribute \src "libresoc.v:29223.3-29277.6" + process $proc$libresoc.v:29223$637 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:167776.5-167776.29" + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:29224.5-29224.29" switch \initial - attribute \src "libresoc.v:167776.9-167776.17" + attribute \src "libresoc.v:29224.9-29224.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:167805.3-167844.6" - process $proc$libresoc.v:167805$10758 - assign { } { } + attribute \src "libresoc.v:29278.3-29332.6" + process $proc$libresoc.v:29278$638 assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10759 $6\msr0__data_o$next[63:0]$10765 - attribute \src "libresoc.v:167806.5-167806.29" + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:29279.5-29279.29" switch \initial - attribute \src "libresoc.v:167806.9-167806.17" + attribute \src "libresoc.v:29279.9-29279.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\msr0__data_o$next[63:0]$10760 $5\msr0__data_o$next[63:0]$10764 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr0__data_o$next[63:0]$10761 \nia0__data_i - case - assign $2\msr0__data_o$next[63:0]$10761 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr0__data_o$next[63:0]$10762 \msr0__data_i - case - assign $3\msr0__data_o$next[63:0]$10762 $2\msr0__data_o$next[63:0]$10761 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr0__data_o$next[63:0]$10763 \d_wr10__data_i - case - assign $4\msr0__data_o$next[63:0]$10763 $3\msr0__data_o$next[63:0]$10762 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr0__data_o$next[63:0]$10764 \reg - case - assign $5\msr0__data_o$next[63:0]$10764 $4\msr0__data_o$next[63:0]$10763 - end - case - assign $1\msr0__data_o$next[63:0]$10760 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $6\msr0__data_o$next[63:0]$10765 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 case - assign $6\msr0__data_o$next[63:0]$10765 $1\msr0__data_o$next[63:0]$10760 + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10759 + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:167845.3-167874.6" - process $proc$libresoc.v:167845$10766 + attribute \src "libresoc.v:29333.3-29387.6" + process $proc$libresoc.v:29333$639 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10767 $1\wr_detect$4[0:0]$10768 - attribute \src "libresoc.v:167846.5-167846.29" + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:29334.5-29334.29" switch \initial - attribute \src "libresoc.v:167846.9-167846.17" + attribute \src "libresoc.v:29334.9-29334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\wr_detect$4[0:0]$10768 $4\wr_detect$4[0:0]$10771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10769 1'1 - case - assign $2\wr_detect$4[0:0]$10769 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr0__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10770 1'1 - case - assign $3\wr_detect$4[0:0]$10770 $2\wr_detect$4[0:0]$10769 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr10__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10771 1'1 - case - assign $4\wr_detect$4[0:0]$10771 $3\wr_detect$4[0:0]$10770 - end + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 case - assign $1\wr_detect$4[0:0]$10768 1'0 + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10767 + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:167875.3-167901.6" - process $proc$libresoc.v:167875$10772 - assign { } { } + attribute \src "libresoc.v:29388.3-29442.6" + process $proc$libresoc.v:29388$640 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$10773 $4\reg$next[63:0]$10777 - attribute \src "libresoc.v:167876.5-167876.29" + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:29389.5-29389.29" switch \initial - attribute \src "libresoc.v:167876.9-167876.17" + attribute \src "libresoc.v:29389.9-29389.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } - assign $1\reg$next[63:0]$10774 \nia0__data_i - case - assign $1\reg$next[63:0]$10774 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr0__wen + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $2\reg$next[63:0]$10775 \msr0__data_i - case - assign $2\reg$next[63:0]$10775 $1\reg$next[63:0]$10774 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr10__wen + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $3\reg$next[63:0]$10776 \d_wr10__data_i - case - assign $3\reg$next[63:0]$10776 $2\reg$next[63:0]$10775 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $4\reg$next[63:0]$10777 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 case - assign $4\reg$next[63:0]$10777 $3\reg$next[63:0]$10776 + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 end sync always - update \reg$next $0\reg$next[63:0]$10773 - end - connect \$1 $not$libresoc.v:167727$10744_Y - connect \$3 $not$libresoc.v:167728$10745_Y -end -attribute \src "libresoc.v:167906.1-168377.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" -attribute \generator "nMigen" -module \reg_1 - attribute \src "libresoc.v:167907.7-167907.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:168237.3-168276.6" - wire width 4 $0\r1__data_o$next[3:0]$10837 - attribute \src "libresoc.v:167992.3-167993.37" - wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:168307.3-168346.6" - wire width 4 $0\r21__data_o$next[3:0]$10851 - attribute \src "libresoc.v:167990.3-167991.39" - wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:168070.3-168096.6" - wire width 4 $0\reg$next[3:0]$10803 - attribute \src "libresoc.v:167988.3-167989.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:168000.3-168039.6" - wire width 4 $0\src11__data_o$next[3:0]$10794 - attribute \src "libresoc.v:167998.3-167999.43" - wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:168097.3-168136.6" - wire width 4 $0\src21__data_o$next[3:0]$10809 - attribute \src "libresoc.v:167996.3-167997.43" - wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:168167.3-168206.6" - wire width 4 $0\src31__data_o$next[3:0]$10823 - attribute \src "libresoc.v:167994.3-167995.43" - wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:168277.3-168306.6" - wire $0\wr_detect$10[0:0]$10845 - attribute \src "libresoc.v:168347.3-168376.6" - wire $0\wr_detect$13[0:0]$10859 - attribute \src "libresoc.v:168137.3-168166.6" - wire $0\wr_detect$4[0:0]$10817 - attribute \src "libresoc.v:168207.3-168236.6" - wire $0\wr_detect$7[0:0]$10831 - attribute \src "libresoc.v:168040.3-168069.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168237.3-168276.6" - wire width 4 $1\r1__data_o$next[3:0]$10838 - attribute \src "libresoc.v:167932.13-167932.30" - wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:168307.3-168346.6" - wire width 4 $1\r21__data_o$next[3:0]$10852 - attribute \src "libresoc.v:167939.13-167939.31" - wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:168070.3-168096.6" - wire width 4 $1\reg$next[3:0]$10804 - attribute \src "libresoc.v:167945.13-167945.25" - wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:168000.3-168039.6" - wire width 4 $1\src11__data_o$next[3:0]$10795 - attribute \src "libresoc.v:167950.13-167950.33" - wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:168097.3-168136.6" - wire width 4 $1\src21__data_o$next[3:0]$10810 - attribute \src "libresoc.v:167957.13-167957.33" - wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:168167.3-168206.6" - wire width 4 $1\src31__data_o$next[3:0]$10824 - attribute \src "libresoc.v:167964.13-167964.33" - wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:168277.3-168306.6" - wire $1\wr_detect$10[0:0]$10846 - attribute \src "libresoc.v:168347.3-168376.6" - wire $1\wr_detect$13[0:0]$10860 - attribute \src "libresoc.v:168137.3-168166.6" - wire $1\wr_detect$4[0:0]$10818 - attribute \src "libresoc.v:168207.3-168236.6" - wire $1\wr_detect$7[0:0]$10832 - attribute \src "libresoc.v:168040.3-168069.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168237.3-168276.6" - wire width 4 $2\r1__data_o$next[3:0]$10839 - attribute \src "libresoc.v:168307.3-168346.6" - wire width 4 $2\r21__data_o$next[3:0]$10853 - attribute \src "libresoc.v:168070.3-168096.6" - wire width 4 $2\reg$next[3:0]$10805 - attribute \src "libresoc.v:168000.3-168039.6" - wire width 4 $2\src11__data_o$next[3:0]$10796 - attribute \src "libresoc.v:168097.3-168136.6" - wire width 4 $2\src21__data_o$next[3:0]$10811 - attribute \src "libresoc.v:168167.3-168206.6" - wire width 4 $2\src31__data_o$next[3:0]$10825 - attribute \src "libresoc.v:168277.3-168306.6" - wire $2\wr_detect$10[0:0]$10847 - attribute \src "libresoc.v:168347.3-168376.6" - wire $2\wr_detect$13[0:0]$10861 - attribute \src "libresoc.v:168137.3-168166.6" - wire $2\wr_detect$4[0:0]$10819 - attribute \src "libresoc.v:168207.3-168236.6" - wire $2\wr_detect$7[0:0]$10833 - attribute \src "libresoc.v:168040.3-168069.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168237.3-168276.6" - wire width 4 $3\r1__data_o$next[3:0]$10840 - attribute \src "libresoc.v:168307.3-168346.6" - wire width 4 $3\r21__data_o$next[3:0]$10854 - attribute \src "libresoc.v:168070.3-168096.6" - wire width 4 $3\reg$next[3:0]$10806 - attribute \src "libresoc.v:168000.3-168039.6" - wire width 4 $3\src11__data_o$next[3:0]$10797 - attribute \src "libresoc.v:168097.3-168136.6" - wire width 4 $3\src21__data_o$next[3:0]$10812 - attribute \src "libresoc.v:168167.3-168206.6" - wire width 4 $3\src31__data_o$next[3:0]$10826 - attribute \src "libresoc.v:168277.3-168306.6" - wire $3\wr_detect$10[0:0]$10848 - attribute \src "libresoc.v:168347.3-168376.6" - wire $3\wr_detect$13[0:0]$10862 - attribute \src "libresoc.v:168137.3-168166.6" - wire $3\wr_detect$4[0:0]$10820 - attribute \src "libresoc.v:168207.3-168236.6" - wire $3\wr_detect$7[0:0]$10834 - attribute \src "libresoc.v:168040.3-168069.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168237.3-168276.6" - wire width 4 $4\r1__data_o$next[3:0]$10841 - attribute \src "libresoc.v:168307.3-168346.6" - wire width 4 $4\r21__data_o$next[3:0]$10855 - attribute \src "libresoc.v:168070.3-168096.6" - wire width 4 $4\reg$next[3:0]$10807 - attribute \src "libresoc.v:168000.3-168039.6" - wire width 4 $4\src11__data_o$next[3:0]$10798 - attribute \src "libresoc.v:168097.3-168136.6" - wire width 4 $4\src21__data_o$next[3:0]$10813 - attribute \src "libresoc.v:168167.3-168206.6" - wire width 4 $4\src31__data_o$next[3:0]$10827 - attribute \src "libresoc.v:168277.3-168306.6" - wire $4\wr_detect$10[0:0]$10849 - attribute \src "libresoc.v:168347.3-168376.6" - wire $4\wr_detect$13[0:0]$10863 - attribute \src "libresoc.v:168137.3-168166.6" - wire $4\wr_detect$4[0:0]$10821 - attribute \src "libresoc.v:168207.3-168236.6" - wire $4\wr_detect$7[0:0]$10835 - attribute \src "libresoc.v:168040.3-168069.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168237.3-168276.6" - wire width 4 $5\r1__data_o$next[3:0]$10842 - attribute \src "libresoc.v:168307.3-168346.6" - wire width 4 $5\r21__data_o$next[3:0]$10856 - attribute \src "libresoc.v:168000.3-168039.6" - wire width 4 $5\src11__data_o$next[3:0]$10799 - attribute \src "libresoc.v:168097.3-168136.6" - wire width 4 $5\src21__data_o$next[3:0]$10814 - attribute \src "libresoc.v:168167.3-168206.6" - wire width 4 $5\src31__data_o$next[3:0]$10828 - attribute \src "libresoc.v:168237.3-168276.6" - wire width 4 $6\r1__data_o$next[3:0]$10843 - attribute \src "libresoc.v:168307.3-168346.6" - wire width 4 $6\r21__data_o$next[3:0]$10857 - attribute \src "libresoc.v:168000.3-168039.6" - wire width 4 $6\src11__data_o$next[3:0]$10800 - attribute \src "libresoc.v:168097.3-168136.6" - wire width 4 $6\src21__data_o$next[3:0]$10815 - attribute \src "libresoc.v:168167.3-168206.6" - wire width 4 $6\src31__data_o$next[3:0]$10829 - attribute \src "libresoc.v:167983.17-167983.104" - wire $not$libresoc.v:167983$10782_Y - attribute \src "libresoc.v:167984.18-167984.105" - wire $not$libresoc.v:167984$10783_Y - attribute \src "libresoc.v:167985.17-167985.100" - wire $not$libresoc.v:167985$10784_Y - attribute \src "libresoc.v:167986.17-167986.103" - wire $not$libresoc.v:167986$10785_Y - attribute \src "libresoc.v:167987.17-167987.103" - wire $not$libresoc.v:167987$10786_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest21__wen - attribute \src "libresoc.v:167907.7-167907.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r21__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167983$10782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:167983$10782_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167984$10783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:167984$10783_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167985$10784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:167985$10784_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167986$10785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:167986$10785_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:167987$10786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:167987$10786_Y - end - attribute \src "libresoc.v:167907.7-167907.20" - process $proc$libresoc.v:167907$10864 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:167932.13-167932.30" - process $proc$libresoc.v:167932$10865 - assign { } { } - assign $1\r1__data_o[3:0] 4'0000 - sync always - sync init - update \r1__data_o $1\r1__data_o[3:0] - end - attribute \src "libresoc.v:167939.13-167939.31" - process $proc$libresoc.v:167939$10866 - assign { } { } - assign $1\r21__data_o[3:0] 4'0000 - sync always - sync init - update \r21__data_o $1\r21__data_o[3:0] - end - attribute \src "libresoc.v:167945.13-167945.25" - process $proc$libresoc.v:167945$10867 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "libresoc.v:167950.13-167950.33" - process $proc$libresoc.v:167950$10868 - assign { } { } - assign $1\src11__data_o[3:0] 4'0000 - sync always - sync init - update \src11__data_o $1\src11__data_o[3:0] - end - attribute \src "libresoc.v:167957.13-167957.33" - process $proc$libresoc.v:167957$10869 - assign { } { } - assign $1\src21__data_o[3:0] 4'0000 - sync always - sync init - update \src21__data_o $1\src21__data_o[3:0] - end - attribute \src "libresoc.v:167964.13-167964.33" - process $proc$libresoc.v:167964$10870 - assign { } { } - assign $1\src31__data_o[3:0] 4'0000 - sync always - sync init - update \src31__data_o $1\src31__data_o[3:0] - end - attribute \src "libresoc.v:167988.3-167989.25" - process $proc$libresoc.v:167988$10787 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:167990.3-167991.39" - process $proc$libresoc.v:167990$10788 - assign { } { } - assign $0\r21__data_o[3:0] \r21__data_o$next - sync posedge \coresync_clk - update \r21__data_o $0\r21__data_o[3:0] - end - attribute \src "libresoc.v:167992.3-167993.37" - process $proc$libresoc.v:167992$10789 - assign { } { } - assign $0\r1__data_o[3:0] \r1__data_o$next - sync posedge \coresync_clk - update \r1__data_o $0\r1__data_o[3:0] - end - attribute \src "libresoc.v:167994.3-167995.43" - process $proc$libresoc.v:167994$10790 - assign { } { } - assign $0\src31__data_o[3:0] \src31__data_o$next - sync posedge \coresync_clk - update \src31__data_o $0\src31__data_o[3:0] - end - attribute \src "libresoc.v:167996.3-167997.43" - process $proc$libresoc.v:167996$10791 - assign { } { } - assign $0\src21__data_o[3:0] \src21__data_o$next - sync posedge \coresync_clk - update \src21__data_o $0\src21__data_o[3:0] - end - attribute \src "libresoc.v:167998.3-167999.43" - process $proc$libresoc.v:167998$10792 - assign { } { } - assign $0\src11__data_o[3:0] \src11__data_o$next - sync posedge \coresync_clk - update \src11__data_o $0\src11__data_o[3:0] + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:168000.3-168039.6" - process $proc$libresoc.v:168000$10793 + attribute \src "libresoc.v:29443.3-29497.6" + process $proc$libresoc.v:29443$641 assign { } { } assign { } { } - assign { } { } - assign $0\src11__data_o$next[3:0]$10794 $6\src11__data_o$next[3:0]$10800 - attribute \src "libresoc.v:168001.5-168001.29" + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:29444.5-29444.29" switch \initial - attribute \src "libresoc.v:168001.9-168001.17" + attribute \src "libresoc.v:29444.9-29444.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10101 assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\src11__data_o$next[3:0]$10795 $5\src11__data_o$next[3:0]$10799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src11__data_o$next[3:0]$10796 \dest11__data_i - case - assign $2\src11__data_o$next[3:0]$10796 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src11__data_o$next[3:0]$10797 \dest21__data_i - case - assign $3\src11__data_o$next[3:0]$10797 $2\src11__data_o$next[3:0]$10796 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src11__data_o$next[3:0]$10798 \w1__data_i - case - assign $4\src11__data_o$next[3:0]$10798 $3\src11__data_o$next[3:0]$10797 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src11__data_o$next[3:0]$10799 \reg - case - assign $5\src11__data_o$next[3:0]$10799 $4\src11__data_o$next[3:0]$10798 - end - case - assign $1\src11__data_o$next[3:0]$10795 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $6\src11__data_o$next[3:0]$10800 4'0000 + assign $1\dec31_dec_sub22_br[0:0] 1'0 case - assign $6\src11__data_o$next[3:0]$10800 $1\src11__data_o$next[3:0]$10795 + assign $1\dec31_dec_sub22_br[0:0] 1'0 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10794 + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:168040.3-168069.6" - process $proc$libresoc.v:168040$10801 + attribute \src "libresoc.v:29498.3-29552.6" + process $proc$libresoc.v:29498$642 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:168041.5-168041.29" + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:29499.5-29499.29" switch \initial - attribute \src "libresoc.v:168041.9-168041.17" + attribute \src "libresoc.v:29499.9-29499.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "libresoc.v:168070.3-168096.6" - process $proc$libresoc.v:168070$10802 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$10803 $4\reg$next[3:0]$10807 - attribute \src "libresoc.v:168071.5-168071.29" - switch \initial - attribute \src "libresoc.v:168071.9-168071.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest11__wen + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } - assign $1\reg$next[3:0]$10804 \dest11__data_i - case - assign $1\reg$next[3:0]$10804 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest21__wen + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } - assign $2\reg$next[3:0]$10805 \dest21__data_i - case - assign $2\reg$next[3:0]$10805 $1\reg$next[3:0]$10804 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w1__wen + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $3\reg$next[3:0]$10806 \w1__data_i - case - assign $3\reg$next[3:0]$10806 $2\reg$next[3:0]$10805 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11000 assign { } { } - assign $4\reg$next[3:0]$10807 4'0000 - case - assign $4\reg$next[3:0]$10807 $3\reg$next[3:0]$10806 - end - sync always - update \reg$next $0\reg$next[3:0]$10803 - end - attribute \src "libresoc.v:168097.3-168136.6" - process $proc$libresoc.v:168097$10808 - assign { } { } - assign { } { } - assign { } { } - assign $0\src21__data_o$next[3:0]$10809 $6\src21__data_o$next[3:0]$10815 - attribute \src "libresoc.v:168098.5-168098.29" - switch \initial - attribute \src "libresoc.v:168098.9-168098.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\src21__data_o$next[3:0]$10810 $5\src21__data_o$next[3:0]$10814 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src21__data_o$next[3:0]$10811 \dest11__data_i - case - assign $2\src21__data_o$next[3:0]$10811 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src21__data_o$next[3:0]$10812 \dest21__data_i - case - assign $3\src21__data_o$next[3:0]$10812 $2\src21__data_o$next[3:0]$10811 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src21__data_o$next[3:0]$10813 \w1__data_i - case - assign $4\src21__data_o$next[3:0]$10813 $3\src21__data_o$next[3:0]$10812 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src21__data_o$next[3:0]$10814 \reg - case - assign $5\src21__data_o$next[3:0]$10814 $4\src21__data_o$next[3:0]$10813 - end - case - assign $1\src21__data_o$next[3:0]$10810 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $6\src21__data_o$next[3:0]$10815 4'0000 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 case - assign $6\src21__data_o$next[3:0]$10815 $1\src21__data_o$next[3:0]$10810 + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10809 + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:168137.3-168166.6" - process $proc$libresoc.v:168137$10816 + attribute \src "libresoc.v:29553.3-29607.6" + process $proc$libresoc.v:29553$643 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10817 $1\wr_detect$4[0:0]$10818 - attribute \src "libresoc.v:168138.5-168138.29" + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:29554.5-29554.29" switch \initial - attribute \src "libresoc.v:168138.9-168138.17" + attribute \src "libresoc.v:29554.9-29554.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\wr_detect$4[0:0]$10818 $4\wr_detect$4[0:0]$10821 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10819 1'1 - case - assign $2\wr_detect$4[0:0]$10819 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10820 1'1 - case - assign $3\wr_detect$4[0:0]$10820 $2\wr_detect$4[0:0]$10819 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10821 1'1 - case - assign $4\wr_detect$4[0:0]$10821 $3\wr_detect$4[0:0]$10820 - end + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 case - assign $1\wr_detect$4[0:0]$10818 1'0 + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10817 + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:168167.3-168206.6" - process $proc$libresoc.v:168167$10822 + attribute \src "libresoc.v:29608.3-29662.6" + process $proc$libresoc.v:29608$644 assign { } { } assign { } { } - assign { } { } - assign $0\src31__data_o$next[3:0]$10823 $6\src31__data_o$next[3:0]$10829 - attribute \src "libresoc.v:168168.5-168168.29" + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:29609.5-29609.29" switch \initial - attribute \src "libresoc.v:168168.9-168168.17" + attribute \src "libresoc.v:29609.9-29609.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\src31__data_o$next[3:0]$10824 $5\src31__data_o$next[3:0]$10828 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src31__data_o$next[3:0]$10825 \dest11__data_i - case - assign $2\src31__data_o$next[3:0]$10825 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src31__data_o$next[3:0]$10826 \dest21__data_i - case - assign $3\src31__data_o$next[3:0]$10826 $2\src31__data_o$next[3:0]$10825 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src31__data_o$next[3:0]$10827 \w1__data_i - case - assign $4\src31__data_o$next[3:0]$10827 $3\src31__data_o$next[3:0]$10826 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src31__data_o$next[3:0]$10828 \reg - case - assign $5\src31__data_o$next[3:0]$10828 $4\src31__data_o$next[3:0]$10827 - end - case - assign $1\src31__data_o$next[3:0]$10824 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $6\src31__data_o$next[3:0]$10829 4'0000 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 case - assign $6\src31__data_o$next[3:0]$10829 $1\src31__data_o$next[3:0]$10824 + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10823 + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:168207.3-168236.6" - process $proc$libresoc.v:168207$10830 + attribute \src "libresoc.v:29663.3-29717.6" + process $proc$libresoc.v:29663$645 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10831 $1\wr_detect$7[0:0]$10832 - attribute \src "libresoc.v:168208.5-168208.29" + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:29664.5-29664.29" switch \initial - attribute \src "libresoc.v:168208.9-168208.17" + attribute \src "libresoc.v:29664.9-29664.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\wr_detect$7[0:0]$10832 $4\wr_detect$7[0:0]$10835 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10833 1'1 - case - assign $2\wr_detect$7[0:0]$10833 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10834 1'1 - case - assign $3\wr_detect$7[0:0]$10834 $2\wr_detect$7[0:0]$10833 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10835 1'1 - case - assign $4\wr_detect$7[0:0]$10835 $3\wr_detect$7[0:0]$10834 - end + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 case - assign $1\wr_detect$7[0:0]$10832 1'0 + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10831 + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:168237.3-168276.6" - process $proc$libresoc.v:168237$10836 - assign { } { } + attribute \src "libresoc.v:29718.3-29772.6" + process $proc$libresoc.v:29718$646 assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10837 $6\r1__data_o$next[3:0]$10843 - attribute \src "libresoc.v:168238.5-168238.29" + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:29719.5-29719.29" switch \initial - attribute \src "libresoc.v:168238.9-168238.17" + attribute \src "libresoc.v:29719.9-29719.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\r1__data_o$next[3:0]$10838 $5\r1__data_o$next[3:0]$10842 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r1__data_o$next[3:0]$10839 \dest11__data_i - case - assign $2\r1__data_o$next[3:0]$10839 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r1__data_o$next[3:0]$10840 \dest21__data_i - case - assign $3\r1__data_o$next[3:0]$10840 $2\r1__data_o$next[3:0]$10839 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r1__data_o$next[3:0]$10841 \w1__data_i - case - assign $4\r1__data_o$next[3:0]$10841 $3\r1__data_o$next[3:0]$10840 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r1__data_o$next[3:0]$10842 \reg - case - assign $5\r1__data_o$next[3:0]$10842 $4\r1__data_o$next[3:0]$10841 - end - case - assign $1\r1__data_o$next[3:0]$10838 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $6\r1__data_o$next[3:0]$10843 4'0000 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 case - assign $6\r1__data_o$next[3:0]$10843 $1\r1__data_o$next[3:0]$10838 + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10837 + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:168277.3-168306.6" - process $proc$libresoc.v:168277$10844 + attribute \src "libresoc.v:29773.3-29827.6" + process $proc$libresoc.v:29773$647 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10845 $1\wr_detect$10[0:0]$10846 - attribute \src "libresoc.v:168278.5-168278.29" + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:29774.5-29774.29" switch \initial - attribute \src "libresoc.v:168278.9-168278.17" + attribute \src "libresoc.v:29774.9-29774.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\wr_detect$10[0:0]$10846 $4\wr_detect$10[0:0]$10849 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10847 1'1 - case - assign $2\wr_detect$10[0:0]$10847 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10848 1'1 - case - assign $3\wr_detect$10[0:0]$10848 $2\wr_detect$10[0:0]$10847 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10849 1'1 - case - assign $4\wr_detect$10[0:0]$10849 $3\wr_detect$10[0:0]$10848 - end + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 case - assign $1\wr_detect$10[0:0]$10846 1'0 + assign $1\dec31_dec_sub22_lk[0:0] 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10845 + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:168307.3-168346.6" - process $proc$libresoc.v:168307$10850 - assign { } { } + attribute \src "libresoc.v:29828.3-29882.6" + process $proc$libresoc.v:29828$648 assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10851 $6\r21__data_o$next[3:0]$10857 - attribute \src "libresoc.v:168308.5-168308.29" + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:29829.5-29829.29" switch \initial - attribute \src "libresoc.v:168308.9-168308.17" + attribute \src "libresoc.v:29829.9-29829.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\r21__data_o$next[3:0]$10852 $5\r21__data_o$next[3:0]$10856 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r21__data_o$next[3:0]$10853 \dest11__data_i - case - assign $2\r21__data_o$next[3:0]$10853 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r21__data_o$next[3:0]$10854 \dest21__data_i - case - assign $3\r21__data_o$next[3:0]$10854 $2\r21__data_o$next[3:0]$10853 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r21__data_o$next[3:0]$10855 \w1__data_i - case - assign $4\r21__data_o$next[3:0]$10855 $3\r21__data_o$next[3:0]$10854 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r21__data_o$next[3:0]$10856 \reg - case - assign $5\r21__data_o$next[3:0]$10856 $4\r21__data_o$next[3:0]$10855 - end - case - assign $1\r21__data_o$next[3:0]$10852 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $6\r21__data_o$next[3:0]$10857 4'0000 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 case - assign $6\r21__data_o$next[3:0]$10857 $1\r21__data_o$next[3:0]$10852 + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10851 + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:168347.3-168376.6" - process $proc$libresoc.v:168347$10858 + attribute \src "libresoc.v:29883.3-29937.6" + process $proc$libresoc.v:29883$649 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10859 $1\wr_detect$13[0:0]$10860 - attribute \src "libresoc.v:168348.5-168348.29" + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:29884.5-29884.29" switch \initial - attribute \src "libresoc.v:168348.9-168348.17" + attribute \src "libresoc.v:29884.9-29884.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\wr_detect$13[0:0]$10860 $4\wr_detect$13[0:0]$10863 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$10861 1'1 - case - assign $2\wr_detect$13[0:0]$10861 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$10862 1'1 - case - assign $3\wr_detect$13[0:0]$10862 $2\wr_detect$13[0:0]$10861 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$10863 1'1 - case - assign $4\wr_detect$13[0:0]$10863 $3\wr_detect$13[0:0]$10862 - end + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 case - assign $1\wr_detect$13[0:0]$10860 1'0 + assign $1\dec31_dec_sub22_form[4:0] 5'00000 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10859 - end - connect \$9 $not$libresoc.v:167983$10782_Y - connect \$12 $not$libresoc.v:167984$10783_Y - connect \$1 $not$libresoc.v:167985$10784_Y - connect \$3 $not$libresoc.v:167986$10785_Y - connect \$6 $not$libresoc.v:167987$10786_Y -end -attribute \src "libresoc.v:168381.1-168826.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" -attribute \generator "nMigen" -module \reg_1$133 - attribute \src "libresoc.v:168382.7-168382.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $0\r1__data_o$next[1:0]$10923 - attribute \src "libresoc.v:168457.3-168458.37" - wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:168793.3-168825.6" - wire width 2 $0\reg$next[1:0]$10939 - attribute \src "libresoc.v:168455.3-168456.25" - wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $0\src11__data_o$next[1:0]$10881 - attribute \src "libresoc.v:168463.3-168464.43" - wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $0\src21__data_o$next[1:0]$10891 - attribute \src "libresoc.v:168461.3-168462.43" - wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $0\src31__data_o$next[1:0]$10907 - attribute \src "libresoc.v:168459.3-168460.43" - wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:168757.3-168792.6" - wire $0\wr_detect$10[0:0]$10932 - attribute \src "libresoc.v:168593.3-168628.6" - wire $0\wr_detect$4[0:0]$10900 - attribute \src "libresoc.v:168675.3-168710.6" - wire $0\wr_detect$7[0:0]$10916 - attribute \src "libresoc.v:168511.3-168546.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $1\r1__data_o$next[1:0]$10924 - attribute \src "libresoc.v:168409.13-168409.30" - wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:168793.3-168825.6" - wire width 2 $1\reg$next[1:0]$10940 - attribute \src "libresoc.v:168415.13-168415.25" - wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $1\src11__data_o$next[1:0]$10882 - attribute \src "libresoc.v:168420.13-168420.33" - wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $1\src21__data_o$next[1:0]$10892 - attribute \src "libresoc.v:168427.13-168427.33" - wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $1\src31__data_o$next[1:0]$10908 - attribute \src "libresoc.v:168434.13-168434.33" - wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:168757.3-168792.6" - wire $1\wr_detect$10[0:0]$10933 - attribute \src "libresoc.v:168593.3-168628.6" - wire $1\wr_detect$4[0:0]$10901 - attribute \src "libresoc.v:168675.3-168710.6" - wire $1\wr_detect$7[0:0]$10917 - attribute \src "libresoc.v:168511.3-168546.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $2\r1__data_o$next[1:0]$10925 - attribute \src "libresoc.v:168793.3-168825.6" - wire width 2 $2\reg$next[1:0]$10941 - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $2\src11__data_o$next[1:0]$10883 - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $2\src21__data_o$next[1:0]$10893 - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $2\src31__data_o$next[1:0]$10909 - attribute \src "libresoc.v:168757.3-168792.6" - wire $2\wr_detect$10[0:0]$10934 - attribute \src "libresoc.v:168593.3-168628.6" - wire $2\wr_detect$4[0:0]$10902 - attribute \src "libresoc.v:168675.3-168710.6" - wire $2\wr_detect$7[0:0]$10918 - attribute \src "libresoc.v:168511.3-168546.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $3\r1__data_o$next[1:0]$10926 - attribute \src "libresoc.v:168793.3-168825.6" - wire width 2 $3\reg$next[1:0]$10942 - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $3\src11__data_o$next[1:0]$10884 - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $3\src21__data_o$next[1:0]$10894 - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $3\src31__data_o$next[1:0]$10910 - attribute \src "libresoc.v:168757.3-168792.6" - wire $3\wr_detect$10[0:0]$10935 - attribute \src "libresoc.v:168593.3-168628.6" - wire $3\wr_detect$4[0:0]$10903 - attribute \src "libresoc.v:168675.3-168710.6" - wire $3\wr_detect$7[0:0]$10919 - attribute \src "libresoc.v:168511.3-168546.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $4\r1__data_o$next[1:0]$10927 - attribute \src "libresoc.v:168793.3-168825.6" - wire width 2 $4\reg$next[1:0]$10943 - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $4\src11__data_o$next[1:0]$10885 - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $4\src21__data_o$next[1:0]$10895 - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $4\src31__data_o$next[1:0]$10911 - attribute \src "libresoc.v:168757.3-168792.6" - wire $4\wr_detect$10[0:0]$10936 - attribute \src "libresoc.v:168593.3-168628.6" - wire $4\wr_detect$4[0:0]$10904 - attribute \src "libresoc.v:168675.3-168710.6" - wire $4\wr_detect$7[0:0]$10920 - attribute \src "libresoc.v:168511.3-168546.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $5\r1__data_o$next[1:0]$10928 - attribute \src "libresoc.v:168793.3-168825.6" - wire width 2 $5\reg$next[1:0]$10944 - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $5\src11__data_o$next[1:0]$10886 - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $5\src21__data_o$next[1:0]$10896 - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $5\src31__data_o$next[1:0]$10912 - attribute \src "libresoc.v:168757.3-168792.6" - wire $5\wr_detect$10[0:0]$10937 - attribute \src "libresoc.v:168593.3-168628.6" - wire $5\wr_detect$4[0:0]$10905 - attribute \src "libresoc.v:168675.3-168710.6" - wire $5\wr_detect$7[0:0]$10921 - attribute \src "libresoc.v:168511.3-168546.6" - wire $5\wr_detect[0:0] - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $6\r1__data_o$next[1:0]$10929 - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $6\src11__data_o$next[1:0]$10887 - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $6\src21__data_o$next[1:0]$10897 - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $6\src31__data_o$next[1:0]$10913 - attribute \src "libresoc.v:168711.3-168756.6" - wire width 2 $7\r1__data_o$next[1:0]$10930 - attribute \src "libresoc.v:168465.3-168510.6" - wire width 2 $7\src11__data_o$next[1:0]$10888 - attribute \src "libresoc.v:168547.3-168592.6" - wire width 2 $7\src21__data_o$next[1:0]$10898 - attribute \src "libresoc.v:168629.3-168674.6" - wire width 2 $7\src31__data_o$next[1:0]$10914 - attribute \src "libresoc.v:168451.17-168451.104" - wire $not$libresoc.v:168451$10871_Y - attribute \src "libresoc.v:168452.17-168452.100" - wire $not$libresoc.v:168452$10872_Y - attribute \src "libresoc.v:168453.17-168453.103" - wire $not$libresoc.v:168453$10873_Y - attribute \src "libresoc.v:168454.17-168454.103" - wire $not$libresoc.v:168454$10874_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \dest31__wen - attribute \src "libresoc.v:168382.7-168382.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168451$10871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:168451$10871_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168452$10872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:168452$10872_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168453$10873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168453$10873_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168454$10874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:168454$10874_Y - end - attribute \src "libresoc.v:168382.7-168382.20" - process $proc$libresoc.v:168382$10945 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:168409.13-168409.30" - process $proc$libresoc.v:168409$10946 - assign { } { } - assign $1\r1__data_o[1:0] 2'00 - sync always - sync init - update \r1__data_o $1\r1__data_o[1:0] - end - attribute \src "libresoc.v:168415.13-168415.25" - process $proc$libresoc.v:168415$10947 - assign { } { } - assign $1\reg[1:0] 2'00 - sync always - sync init - update \reg $1\reg[1:0] - end - attribute \src "libresoc.v:168420.13-168420.33" - process $proc$libresoc.v:168420$10948 - assign { } { } - assign $1\src11__data_o[1:0] 2'00 - sync always - sync init - update \src11__data_o $1\src11__data_o[1:0] - end - attribute \src "libresoc.v:168427.13-168427.33" - process $proc$libresoc.v:168427$10949 - assign { } { } - assign $1\src21__data_o[1:0] 2'00 - sync always - sync init - update \src21__data_o $1\src21__data_o[1:0] - end - attribute \src "libresoc.v:168434.13-168434.33" - process $proc$libresoc.v:168434$10950 - assign { } { } - assign $1\src31__data_o[1:0] 2'00 - sync always - sync init - update \src31__data_o $1\src31__data_o[1:0] - end - attribute \src "libresoc.v:168455.3-168456.25" - process $proc$libresoc.v:168455$10875 - assign { } { } - assign $0\reg[1:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[1:0] - end - attribute \src "libresoc.v:168457.3-168458.37" - process $proc$libresoc.v:168457$10876 - assign { } { } - assign $0\r1__data_o[1:0] \r1__data_o$next - sync posedge \coresync_clk - update \r1__data_o $0\r1__data_o[1:0] - end - attribute \src "libresoc.v:168459.3-168460.43" - process $proc$libresoc.v:168459$10877 - assign { } { } - assign $0\src31__data_o[1:0] \src31__data_o$next - sync posedge \coresync_clk - update \src31__data_o $0\src31__data_o[1:0] - end - attribute \src "libresoc.v:168461.3-168462.43" - process $proc$libresoc.v:168461$10878 - assign { } { } - assign $0\src21__data_o[1:0] \src21__data_o$next - sync posedge \coresync_clk - update \src21__data_o $0\src21__data_o[1:0] - end - attribute \src "libresoc.v:168463.3-168464.43" - process $proc$libresoc.v:168463$10879 - assign { } { } - assign $0\src11__data_o[1:0] \src11__data_o$next - sync posedge \coresync_clk - update \src11__data_o $0\src11__data_o[1:0] + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:168465.3-168510.6" - process $proc$libresoc.v:168465$10880 + attribute \src "libresoc.v:29938.3-29992.6" + process $proc$libresoc.v:29938$650 assign { } { } assign { } { } - assign { } { } - assign $0\src11__data_o$next[1:0]$10881 $7\src11__data_o$next[1:0]$10888 - attribute \src "libresoc.v:168466.5-168466.29" + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:29939.5-29939.29" switch \initial - attribute \src "libresoc.v:168466.9-168466.17" + attribute \src "libresoc.v:29939.9-29939.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\src11__data_o$next[1:0]$10882 $6\src11__data_o$next[1:0]$10887 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src11__data_o$next[1:0]$10883 \dest11__data_i - case - assign $2\src11__data_o$next[1:0]$10883 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src11__data_o$next[1:0]$10884 \dest21__data_i - case - assign $3\src11__data_o$next[1:0]$10884 $2\src11__data_o$next[1:0]$10883 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src11__data_o$next[1:0]$10885 \dest31__data_i - case - assign $4\src11__data_o$next[1:0]$10885 $3\src11__data_o$next[1:0]$10884 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src11__data_o$next[1:0]$10886 \w1__data_i - case - assign $5\src11__data_o$next[1:0]$10886 $4\src11__data_o$next[1:0]$10885 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src11__data_o$next[1:0]$10887 \reg - case - assign $6\src11__data_o$next[1:0]$10887 $5\src11__data_o$next[1:0]$10886 - end - case - assign $1\src11__data_o$next[1:0]$10882 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $7\src11__data_o$next[1:0]$10888 2'00 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 case - assign $7\src11__data_o$next[1:0]$10888 $1\src11__data_o$next[1:0]$10882 + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10881 + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:168511.3-168546.6" - process $proc$libresoc.v:168511$10889 + attribute \src "libresoc.v:29993.3-30047.6" + process $proc$libresoc.v:29993$651 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:168512.5-168512.29" + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:29994.5-29994.29" switch \initial - attribute \src "libresoc.v:168512.9-168512.17" + attribute \src "libresoc.v:29994.9-29994.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src11__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\wr_detect[0:0] $5\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect[0:0] 1'1 - case - assign $5\wr_detect[0:0] $4\wr_detect[0:0] - end + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:168547.3-168592.6" - process $proc$libresoc.v:168547$10890 + attribute \src "libresoc.v:30048.3-30102.6" + process $proc$libresoc.v:30048$652 assign { } { } assign { } { } - assign { } { } - assign $0\src21__data_o$next[1:0]$10891 $7\src21__data_o$next[1:0]$10898 - attribute \src "libresoc.v:168548.5-168548.29" + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:30049.5-30049.29" switch \initial - attribute \src "libresoc.v:168548.9-168548.17" + attribute \src "libresoc.v:30049.9-30049.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\src21__data_o$next[1:0]$10892 $6\src21__data_o$next[1:0]$10897 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src21__data_o$next[1:0]$10893 \dest11__data_i - case - assign $2\src21__data_o$next[1:0]$10893 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src21__data_o$next[1:0]$10894 \dest21__data_i - case - assign $3\src21__data_o$next[1:0]$10894 $2\src21__data_o$next[1:0]$10893 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src21__data_o$next[1:0]$10895 \dest31__data_i - case - assign $4\src21__data_o$next[1:0]$10895 $3\src21__data_o$next[1:0]$10894 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src21__data_o$next[1:0]$10896 \w1__data_i - case - assign $5\src21__data_o$next[1:0]$10896 $4\src21__data_o$next[1:0]$10895 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src21__data_o$next[1:0]$10897 \reg - case - assign $6\src21__data_o$next[1:0]$10897 $5\src21__data_o$next[1:0]$10896 - end - case - assign $1\src21__data_o$next[1:0]$10892 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } - assign $7\src21__data_o$next[1:0]$10898 2'00 - case - assign $7\src21__data_o$next[1:0]$10898 $1\src21__data_o$next[1:0]$10892 - end - sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10891 - end - attribute \src "libresoc.v:168593.3-168628.6" - process $proc$libresoc.v:168593$10899 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10900 $1\wr_detect$4[0:0]$10901 - attribute \src "libresoc.v:168594.5-168594.29" - switch \initial - attribute \src "libresoc.v:168594.9-168594.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src21__ren + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\wr_detect$4[0:0]$10901 $5\wr_detect$4[0:0]$10905 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10902 1'1 - case - assign $2\wr_detect$4[0:0]$10902 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10903 1'1 - case - assign $3\wr_detect$4[0:0]$10903 $2\wr_detect$4[0:0]$10902 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10904 1'1 - case - assign $4\wr_detect$4[0:0]$10904 $3\wr_detect$4[0:0]$10903 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$4[0:0]$10905 1'1 - case - assign $5\wr_detect$4[0:0]$10905 $4\wr_detect$4[0:0]$10904 - end - case - assign $1\wr_detect$4[0:0]$10901 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10900 - end - attribute \src "libresoc.v:168629.3-168674.6" - process $proc$libresoc.v:168629$10906 - assign { } { } - assign { } { } - assign { } { } - assign $0\src31__data_o$next[1:0]$10907 $7\src31__data_o$next[1:0]$10914 - attribute \src "libresoc.v:168630.5-168630.29" - switch \initial - attribute \src "libresoc.v:168630.9-168630.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $1\src31__data_o$next[1:0]$10908 $6\src31__data_o$next[1:0]$10913 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src31__data_o$next[1:0]$10909 \dest11__data_i - case - assign $2\src31__data_o$next[1:0]$10909 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src31__data_o$next[1:0]$10910 \dest21__data_i - case - assign $3\src31__data_o$next[1:0]$10910 $2\src31__data_o$next[1:0]$10909 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src31__data_o$next[1:0]$10911 \dest31__data_i - case - assign $4\src31__data_o$next[1:0]$10911 $3\src31__data_o$next[1:0]$10910 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src31__data_o$next[1:0]$10912 \w1__data_i - case - assign $5\src31__data_o$next[1:0]$10912 $4\src31__data_o$next[1:0]$10911 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src31__data_o$next[1:0]$10913 \reg - case - assign $6\src31__data_o$next[1:0]$10913 $5\src31__data_o$next[1:0]$10912 - end - case - assign $1\src31__data_o$next[1:0]$10908 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10010 assign { } { } - assign $7\src31__data_o$next[1:0]$10914 2'00 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 case - assign $7\src31__data_o$next[1:0]$10914 $1\src31__data_o$next[1:0]$10908 + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$10907 + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:168675.3-168710.6" - process $proc$libresoc.v:168675$10915 + attribute \src "libresoc.v:30103.3-30157.6" + process $proc$libresoc.v:30103$653 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10916 $1\wr_detect$7[0:0]$10917 - attribute \src "libresoc.v:168676.5-168676.29" + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:30104.5-30104.29" switch \initial - attribute \src "libresoc.v:168676.9-168676.17" + attribute \src "libresoc.v:30104.9-30104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src31__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 assign { } { } - assign $1\wr_detect$7[0:0]$10917 $5\wr_detect$7[0:0]$10921 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$10918 1'1 - case - assign $2\wr_detect$7[0:0]$10918 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$10919 1'1 - case - assign $3\wr_detect$7[0:0]$10919 $2\wr_detect$7[0:0]$10918 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$10920 1'1 - case - assign $4\wr_detect$7[0:0]$10920 $3\wr_detect$7[0:0]$10919 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$7[0:0]$10921 1'1 - case - assign $5\wr_detect$7[0:0]$10921 $4\wr_detect$7[0:0]$10920 - end - case - assign $1\wr_detect$7[0:0]$10917 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10916 - end - attribute \src "libresoc.v:168711.3-168756.6" - process $proc$libresoc.v:168711$10922 - assign { } { } - assign { } { } - assign { } { } - assign $0\r1__data_o$next[1:0]$10923 $7\r1__data_o$next[1:0]$10930 - attribute \src "libresoc.v:168712.5-168712.29" - switch \initial - attribute \src "libresoc.v:168712.9-168712.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 assign { } { } - assign $1\r1__data_o$next[1:0]$10924 $6\r1__data_o$next[1:0]$10929 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r1__data_o$next[1:0]$10925 \dest11__data_i - case - assign $2\r1__data_o$next[1:0]$10925 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r1__data_o$next[1:0]$10926 \dest21__data_i - case - assign $3\r1__data_o$next[1:0]$10926 $2\r1__data_o$next[1:0]$10925 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r1__data_o$next[1:0]$10927 \dest31__data_i - case - assign $4\r1__data_o$next[1:0]$10927 $3\r1__data_o$next[1:0]$10926 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r1__data_o$next[1:0]$10928 \w1__data_i - case - assign $5\r1__data_o$next[1:0]$10928 $4\r1__data_o$next[1:0]$10927 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r1__data_o$next[1:0]$10929 \reg - case - assign $6\r1__data_o$next[1:0]$10929 $5\r1__data_o$next[1:0]$10928 - end - case - assign $1\r1__data_o$next[1:0]$10924 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } - assign $7\r1__data_o$next[1:0]$10930 2'00 - case - assign $7\r1__data_o$next[1:0]$10930 $1\r1__data_o$next[1:0]$10924 - end - sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$10923 - end - attribute \src "libresoc.v:168757.3-168792.6" - process $proc$libresoc.v:168757$10931 - assign { } { } - assign { } { } - assign $0\wr_detect$10[0:0]$10932 $1\wr_detect$10[0:0]$10933 - attribute \src "libresoc.v:168758.5-168758.29" - switch \initial - attribute \src "libresoc.v:168758.9-168758.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r1__ren + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11100 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $1\wr_detect$10[0:0]$10933 $5\wr_detect$10[0:0]$10937 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$10934 1'1 - case - assign $2\wr_detect$10[0:0]$10934 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest21__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$10935 1'1 - case - assign $3\wr_detect$10[0:0]$10935 $2\wr_detect$10[0:0]$10934 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest31__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$10936 1'1 - case - assign $4\wr_detect$10[0:0]$10936 $3\wr_detect$10[0:0]$10935 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$10[0:0]$10937 1'1 - case - assign $5\wr_detect$10[0:0]$10937 $4\wr_detect$10[0:0]$10936 - end + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 case - assign $1\wr_detect$10[0:0]$10933 1'0 + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10932 + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] end - attribute \src "libresoc.v:168793.3-168825.6" - process $proc$libresoc.v:168793$10938 - assign { } { } + attribute \src "libresoc.v:30158.3-30212.6" + process $proc$libresoc.v:30158$654 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[1:0]$10939 $5\reg$next[1:0]$10944 - attribute \src "libresoc.v:168794.5-168794.29" + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:30159.5-30159.29" switch \initial - attribute \src "libresoc.v:168794.9-168794.17" + attribute \src "libresoc.v:30159.9-30159.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest11__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } - assign $1\reg$next[1:0]$10940 \dest11__data_i - case - assign $1\reg$next[1:0]$10940 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest21__wen + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $2\reg$next[1:0]$10941 \dest21__data_i - case - assign $2\reg$next[1:0]$10941 $1\reg$next[1:0]$10940 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest31__wen + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $3\reg$next[1:0]$10942 \dest31__data_i - case - assign $3\reg$next[1:0]$10942 $2\reg$next[1:0]$10941 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w1__wen + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $4\reg$next[1:0]$10943 \w1__data_i - case - assign $4\reg$next[1:0]$10943 $3\reg$next[1:0]$10942 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } - assign $5\reg$next[1:0]$10944 2'00 - case - assign $5\reg$next[1:0]$10944 $4\reg$next[1:0]$10943 - end - sync always - update \reg$next $0\reg$next[1:0]$10939 - end - connect \$9 $not$libresoc.v:168451$10871_Y - connect \$1 $not$libresoc.v:168452$10872_Y - connect \$3 $not$libresoc.v:168453$10873_Y - connect \$6 $not$libresoc.v:168454$10874_Y -end -attribute \src "libresoc.v:168830.1-169049.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" -attribute \generator "nMigen" -module \reg_1$136 - attribute \src "libresoc.v:168882.3-168921.6" - wire width 64 $0\cia1__data_o$next[63:0]$10957 - attribute \src "libresoc.v:168880.3-168881.41" - wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:168831.7-168831.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:168952.3-168991.6" - wire width 64 $0\msr1__data_o$next[63:0]$10966 - attribute \src "libresoc.v:168878.3-168879.41" - wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:169022.3-169048.6" - wire width 64 $0\reg$next[63:0]$10980 - attribute \src "libresoc.v:168876.3-168877.25" - wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:168992.3-169021.6" - wire $0\wr_detect$4[0:0]$10974 - attribute \src "libresoc.v:168922.3-168951.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:168882.3-168921.6" - wire width 64 $1\cia1__data_o$next[63:0]$10958 - attribute \src "libresoc.v:168838.14-168838.49" - wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:168952.3-168991.6" - wire width 64 $1\msr1__data_o$next[63:0]$10967 - attribute \src "libresoc.v:168855.14-168855.49" - wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:169022.3-169048.6" - wire width 64 $1\reg$next[63:0]$10981 - attribute \src "libresoc.v:168867.14-168867.42" - wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:168992.3-169021.6" - wire $1\wr_detect$4[0:0]$10975 - attribute \src "libresoc.v:168922.3-168951.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:168882.3-168921.6" - wire width 64 $2\cia1__data_o$next[63:0]$10959 - attribute \src "libresoc.v:168952.3-168991.6" - wire width 64 $2\msr1__data_o$next[63:0]$10968 - attribute \src "libresoc.v:169022.3-169048.6" - wire width 64 $2\reg$next[63:0]$10982 - attribute \src "libresoc.v:168992.3-169021.6" - wire $2\wr_detect$4[0:0]$10976 - attribute \src "libresoc.v:168922.3-168951.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:168882.3-168921.6" - wire width 64 $3\cia1__data_o$next[63:0]$10960 - attribute \src "libresoc.v:168952.3-168991.6" - wire width 64 $3\msr1__data_o$next[63:0]$10969 - attribute \src "libresoc.v:169022.3-169048.6" - wire width 64 $3\reg$next[63:0]$10983 - attribute \src "libresoc.v:168992.3-169021.6" - wire $3\wr_detect$4[0:0]$10977 - attribute \src "libresoc.v:168922.3-168951.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:168882.3-168921.6" - wire width 64 $4\cia1__data_o$next[63:0]$10961 - attribute \src "libresoc.v:168952.3-168991.6" - wire width 64 $4\msr1__data_o$next[63:0]$10970 - attribute \src "libresoc.v:169022.3-169048.6" - wire width 64 $4\reg$next[63:0]$10984 - attribute \src "libresoc.v:168992.3-169021.6" - wire $4\wr_detect$4[0:0]$10978 - attribute \src "libresoc.v:168922.3-168951.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:168882.3-168921.6" - wire width 64 $5\cia1__data_o$next[63:0]$10962 - attribute \src "libresoc.v:168952.3-168991.6" - wire width 64 $5\msr1__data_o$next[63:0]$10971 - attribute \src "libresoc.v:168882.3-168921.6" - wire width 64 $6\cia1__data_o$next[63:0]$10963 - attribute \src "libresoc.v:168952.3-168991.6" - wire width 64 $6\msr1__data_o$next[63:0]$10972 - attribute \src "libresoc.v:168874.17-168874.100" - wire $not$libresoc.v:168874$10951_Y - attribute \src "libresoc.v:168875.17-168875.103" - wire $not$libresoc.v:168875$10952_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr11__wen - attribute \src "libresoc.v:168831.7-168831.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168874$10951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:168874$10951_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:168875$10952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:168875$10952_Y - end - attribute \src "libresoc.v:168831.7-168831.20" - process $proc$libresoc.v:168831$10985 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:168838.14-168838.49" - process $proc$libresoc.v:168838$10986 - assign { } { } - assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia1__data_o $1\cia1__data_o[63:0] - end - attribute \src "libresoc.v:168855.14-168855.49" - process $proc$libresoc.v:168855$10987 - assign { } { } - assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr1__data_o $1\msr1__data_o[63:0] - end - attribute \src "libresoc.v:168867.14-168867.42" - process $proc$libresoc.v:168867$10988 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "libresoc.v:168876.3-168877.25" - process $proc$libresoc.v:168876$10953 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "libresoc.v:168878.3-168879.41" - process $proc$libresoc.v:168878$10954 - assign { } { } - assign $0\msr1__data_o[63:0] \msr1__data_o$next - sync posedge \coresync_clk - update \msr1__data_o $0\msr1__data_o[63:0] - end - attribute \src "libresoc.v:168880.3-168881.41" - process $proc$libresoc.v:168880$10955 - assign { } { } - assign $0\cia1__data_o[63:0] \cia1__data_o$next - sync posedge \coresync_clk - update \cia1__data_o $0\cia1__data_o[63:0] - end - attribute \src "libresoc.v:168882.3-168921.6" - process $proc$libresoc.v:168882$10956 - assign { } { } - assign { } { } - assign { } { } - assign $0\cia1__data_o$next[63:0]$10957 $6\cia1__data_o$next[63:0]$10963 - attribute \src "libresoc.v:168883.5-168883.29" - switch \initial - attribute \src "libresoc.v:168883.9-168883.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia1__ren + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\cia1__data_o$next[63:0]$10958 $5\cia1__data_o$next[63:0]$10962 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia1__data_o$next[63:0]$10959 \nia1__data_i - case - assign $2\cia1__data_o$next[63:0]$10959 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia1__data_o$next[63:0]$10960 \msr1__data_i - case - assign $3\cia1__data_o$next[63:0]$10960 $2\cia1__data_o$next[63:0]$10959 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia1__data_o$next[63:0]$10961 \d_wr11__data_i - case - assign $4\cia1__data_o$next[63:0]$10961 $3\cia1__data_o$next[63:0]$10960 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia1__data_o$next[63:0]$10962 \reg - case - assign $5\cia1__data_o$next[63:0]$10962 $4\cia1__data_o$next[63:0]$10961 - end - case - assign $1\cia1__data_o$next[63:0]$10958 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10101 assign { } { } - assign $6\cia1__data_o$next[63:0]$10963 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia1__data_o$next[63:0]$10963 $1\cia1__data_o$next[63:0]$10958 - end - sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10957 - end - attribute \src "libresoc.v:168922.3-168951.6" - process $proc$libresoc.v:168922$10964 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:168923.5-168923.29" - switch \initial - attribute \src "libresoc.v:168923.9-168923.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia1__ren + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:168952.3-168991.6" - process $proc$libresoc.v:168952$10965 + attribute \src "libresoc.v:30213.3-30267.6" + process $proc$libresoc.v:30213$655 assign { } { } assign { } { } - assign { } { } - assign $0\msr1__data_o$next[63:0]$10966 $6\msr1__data_o$next[63:0]$10972 - attribute \src "libresoc.v:168953.5-168953.29" + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:30214.5-30214.29" switch \initial - attribute \src "libresoc.v:168953.9-168953.17" + attribute \src "libresoc.v:30214.9-30214.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\msr1__data_o$next[63:0]$10967 $5\msr1__data_o$next[63:0]$10971 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr1__data_o$next[63:0]$10968 \nia1__data_i - case - assign $2\msr1__data_o$next[63:0]$10968 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr1__data_o$next[63:0]$10969 \msr1__data_i - case - assign $3\msr1__data_o$next[63:0]$10969 $2\msr1__data_o$next[63:0]$10968 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr1__data_o$next[63:0]$10970 \d_wr11__data_i - case - assign $4\msr1__data_o$next[63:0]$10970 $3\msr1__data_o$next[63:0]$10969 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr1__data_o$next[63:0]$10971 \reg - case - assign $5\msr1__data_o$next[63:0]$10971 $4\msr1__data_o$next[63:0]$10970 - end - case - assign $1\msr1__data_o$next[63:0]$10967 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } - assign $6\msr1__data_o$next[63:0]$10972 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\msr1__data_o$next[63:0]$10972 $1\msr1__data_o$next[63:0]$10967 - end - sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10966 - end - attribute \src "libresoc.v:168992.3-169021.6" - process $proc$libresoc.v:168992$10973 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$10974 $1\wr_detect$4[0:0]$10975 - attribute \src "libresoc.v:168993.5-168993.29" - switch \initial - attribute \src "libresoc.v:168993.9-168993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr1__ren + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$4[0:0]$10975 $4\wr_detect$4[0:0]$10978 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$10976 1'1 - case - assign $2\wr_detect$4[0:0]$10976 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr1__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$10977 1'1 - case - assign $3\wr_detect$4[0:0]$10977 $2\wr_detect$4[0:0]$10976 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr11__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$10978 1'1 - case - assign $4\wr_detect$4[0:0]$10978 $3\wr_detect$4[0:0]$10977 - end - case - assign $1\wr_detect$4[0:0]$10975 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10974 - end - attribute \src "libresoc.v:169022.3-169048.6" - process $proc$libresoc.v:169022$10979 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$10980 $4\reg$next[63:0]$10984 - attribute \src "libresoc.v:169023.5-169023.29" - switch \initial - attribute \src "libresoc.v:169023.9-169023.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia1__wen + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10101 assign { } { } - assign $1\reg$next[63:0]$10981 \nia1__data_i - case - assign $1\reg$next[63:0]$10981 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr1__wen + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } - assign $2\reg$next[63:0]$10982 \msr1__data_i - case - assign $2\reg$next[63:0]$10982 $1\reg$next[63:0]$10981 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr11__wen + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11100 assign { } { } - assign $3\reg$next[63:0]$10983 \d_wr11__data_i - case - assign $3\reg$next[63:0]$10983 $2\reg$next[63:0]$10982 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } - assign $4\reg$next[63:0]$10984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 case - assign $4\reg$next[63:0]$10984 $3\reg$next[63:0]$10983 + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 end sync always - update \reg$next $0\reg$next[63:0]$10980 + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - connect \$1 $not$libresoc.v:168874$10951_Y - connect \$3 $not$libresoc.v:168875$10952_Y + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:169053.1-169524.10" +attribute \src "libresoc.v:30273.1-31708.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" -module \reg_2 - attribute \src "libresoc.v:169054.7-169054.20" +module \dec31_dec_sub23 + attribute \src "libresoc.v:30776.3-30824.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30972.3-31020.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31609.3-31657.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31658.3-31706.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30727.3-30775.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30923.3-30971.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31364.3-31412.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30531.3-30579.6" + wire width 12 $0\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31413.3-31461.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31462.3-31510.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31511.3-31559.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31070.3-31118.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:30825.3-30873.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30874.3-30922.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:31168.3-31216.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:30580.3-30628.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:31266.3-31314.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31560.3-31608.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:30678.3-30726.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:31119.3-31167.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31315.3-31363.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31217.3-31265.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31021.3-31069.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:30629.3-30677.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30274.7-30274.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169454.3-169493.6" - wire width 4 $0\r22__data_o$next[3:0]$11058 - attribute \src "libresoc.v:169137.3-169138.39" - wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:169384.3-169423.6" - wire width 4 $0\r2__data_o$next[3:0]$11044 - attribute \src "libresoc.v:169139.3-169140.37" - wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:169217.3-169243.6" - wire width 4 $0\reg$next[3:0]$11010 - attribute \src "libresoc.v:169135.3-169136.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:169147.3-169186.6" - wire width 4 $0\src12__data_o$next[3:0]$11001 - attribute \src "libresoc.v:169145.3-169146.43" - wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:169244.3-169283.6" - wire width 4 $0\src22__data_o$next[3:0]$11016 - attribute \src "libresoc.v:169143.3-169144.43" - wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:169314.3-169353.6" - wire width 4 $0\src32__data_o$next[3:0]$11030 - attribute \src "libresoc.v:169141.3-169142.43" - wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:169424.3-169453.6" - wire $0\wr_detect$10[0:0]$11052 - attribute \src "libresoc.v:169494.3-169523.6" - wire $0\wr_detect$13[0:0]$11066 - attribute \src "libresoc.v:169284.3-169313.6" - wire $0\wr_detect$4[0:0]$11024 - attribute \src "libresoc.v:169354.3-169383.6" - wire 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attribute \src "libresoc.v:169054.7-169054.15" + attribute \src "libresoc.v:30776.3-30824.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30972.3-31020.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:31609.3-31657.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31658.3-31706.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:30727.3-30775.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30923.3-30971.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:31364.3-31412.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:30531.3-30579.6" + wire width 12 $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:31413.3-31461.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31462.3-31510.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src 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"OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub23_upd + attribute \src "libresoc.v:30274.7-30274.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169130$10989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:169130$10989_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169131$10990 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:169131$10990_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169132$10991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:169132$10991_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169133$10992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:169133$10992_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169134$10993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:169134$10993_Y - end - attribute \src "libresoc.v:169054.7-169054.20" - process $proc$libresoc.v:169054$11071 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:30274.7-30274.20" + process $proc$libresoc.v:30274$681 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169079.13-169079.31" - process $proc$libresoc.v:169079$11072 - assign { } { } - assign $1\r22__data_o[3:0] 4'0000 - sync always - sync init - update \r22__data_o $1\r22__data_o[3:0] - end - attribute \src "libresoc.v:169086.13-169086.30" - process $proc$libresoc.v:169086$11073 - assign { } { } - assign $1\r2__data_o[3:0] 4'0000 - sync always - sync init - update \r2__data_o $1\r2__data_o[3:0] - end - attribute \src "libresoc.v:169092.13-169092.25" - process $proc$libresoc.v:169092$11074 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "libresoc.v:169097.13-169097.33" - process $proc$libresoc.v:169097$11075 - assign { } { } - assign $1\src12__data_o[3:0] 4'0000 - sync always - sync init - update \src12__data_o $1\src12__data_o[3:0] - end - attribute \src "libresoc.v:169104.13-169104.33" - process $proc$libresoc.v:169104$11076 + attribute \src "libresoc.v:30531.3-30579.6" + process $proc$libresoc.v:30531$657 assign { } { } - assign $1\src22__data_o[3:0] 4'0000 - sync always - sync init - update \src22__data_o $1\src22__data_o[3:0] - end - attribute \src "libresoc.v:169111.13-169111.33" - process $proc$libresoc.v:169111$11077 assign { } { } - assign $1\src32__data_o[3:0] 4'0000 + assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "libresoc.v:30532.5-30532.29" + switch \initial + attribute \src "libresoc.v:30532.9-30532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end sync always - sync init - update \src32__data_o $1\src32__data_o[3:0] - end - attribute \src "libresoc.v:169135.3-169136.25" - process $proc$libresoc.v:169135$10994 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:169137.3-169138.39" - process $proc$libresoc.v:169137$10995 - assign { } { } - assign $0\r22__data_o[3:0] \r22__data_o$next - sync posedge \coresync_clk - update \r22__data_o $0\r22__data_o[3:0] - end - attribute \src "libresoc.v:169139.3-169140.37" - process $proc$libresoc.v:169139$10996 - assign { } { } - assign $0\r2__data_o[3:0] \r2__data_o$next - sync posedge \coresync_clk - update \r2__data_o $0\r2__data_o[3:0] - end - attribute \src "libresoc.v:169141.3-169142.43" - process $proc$libresoc.v:169141$10997 - assign { } { } - assign $0\src32__data_o[3:0] \src32__data_o$next - sync posedge \coresync_clk - update \src32__data_o $0\src32__data_o[3:0] - end - attribute \src "libresoc.v:169143.3-169144.43" - process $proc$libresoc.v:169143$10998 - assign { } { } - assign $0\src22__data_o[3:0] \src22__data_o$next - sync posedge \coresync_clk - update \src22__data_o $0\src22__data_o[3:0] - end - attribute \src "libresoc.v:169145.3-169146.43" - process $proc$libresoc.v:169145$10999 - assign { } { } - assign $0\src12__data_o[3:0] \src12__data_o$next - sync posedge \coresync_clk - update \src12__data_o $0\src12__data_o[3:0] + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] end - attribute \src "libresoc.v:169147.3-169186.6" - process $proc$libresoc.v:169147$11000 + attribute \src "libresoc.v:30580.3-30628.6" + process $proc$libresoc.v:30580$658 assign { } { } assign { } { } - assign { } { } - assign $0\src12__data_o$next[3:0]$11001 $6\src12__data_o$next[3:0]$11007 - attribute \src "libresoc.v:169148.5-169148.29" + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:30581.5-30581.29" switch \initial - attribute \src "libresoc.v:169148.9-169148.17" + attribute \src "libresoc.v:30581.9-30581.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\src12__data_o$next[3:0]$11002 $5\src12__data_o$next[3:0]$11006 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src12__data_o$next[3:0]$11003 \dest12__data_i - case - assign $2\src12__data_o$next[3:0]$11003 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src12__data_o$next[3:0]$11004 \dest22__data_i - case - assign $3\src12__data_o$next[3:0]$11004 $2\src12__data_o$next[3:0]$11003 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src12__data_o$next[3:0]$11005 \w2__data_i - case - assign $4\src12__data_o$next[3:0]$11005 $3\src12__data_o$next[3:0]$11004 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src12__data_o$next[3:0]$11006 \reg - case - assign $5\src12__data_o$next[3:0]$11006 $4\src12__data_o$next[3:0]$11005 - end - case - assign $1\src12__data_o$next[3:0]$11002 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $6\src12__data_o$next[3:0]$11007 4'0000 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 case - assign $6\src12__data_o$next[3:0]$11007 $1\src12__data_o$next[3:0]$11002 + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$11001 + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:169187.3-169216.6" - process $proc$libresoc.v:169187$11008 + attribute \src "libresoc.v:30629.3-30677.6" + process $proc$libresoc.v:30629$659 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:169188.5-169188.29" + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:30630.5-30630.29" switch \initial - attribute \src "libresoc.v:169188.9-169188.17" + attribute \src "libresoc.v:30630.9-30630.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub23_upd[1:0] 2'00 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:169217.3-169243.6" - process $proc$libresoc.v:169217$11009 + attribute \src "libresoc.v:30678.3-30726.6" + process $proc$libresoc.v:30678$660 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11010 $4\reg$next[3:0]$11014 - attribute \src "libresoc.v:169218.5-169218.29" + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:30679.5-30679.29" switch \initial - attribute \src "libresoc.v:169218.9-169218.17" + attribute \src "libresoc.v:30679.9-30679.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest12__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $1\reg$next[3:0]$11011 \dest12__data_i - case - assign $1\reg$next[3:0]$11011 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest22__wen + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } - assign $2\reg$next[3:0]$11012 \dest22__data_i - case - assign $2\reg$next[3:0]$11012 $1\reg$next[3:0]$11011 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w2__wen + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01011 assign { } { } - assign $3\reg$next[3:0]$11013 \w2__data_i - case - assign $3\reg$next[3:0]$11013 $2\reg$next[3:0]$11012 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $4\reg$next[3:0]$11014 4'0000 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 case - assign $4\reg$next[3:0]$11014 $3\reg$next[3:0]$11013 + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 end sync always - update \reg$next $0\reg$next[3:0]$11010 + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:169244.3-169283.6" - process $proc$libresoc.v:169244$11015 + attribute \src "libresoc.v:30727.3-30775.6" + process $proc$libresoc.v:30727$661 assign { } { } assign { } { } - assign { } { } - assign $0\src22__data_o$next[3:0]$11016 $6\src22__data_o$next[3:0]$11022 - attribute \src "libresoc.v:169245.5-169245.29" + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:30728.5-30728.29" switch \initial - attribute \src "libresoc.v:169245.9-169245.17" + attribute \src "libresoc.v:30728.9-30728.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\src22__data_o$next[3:0]$11017 $5\src22__data_o$next[3:0]$11021 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src22__data_o$next[3:0]$11018 \dest12__data_i - case - assign $2\src22__data_o$next[3:0]$11018 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src22__data_o$next[3:0]$11019 \dest22__data_i - case - assign $3\src22__data_o$next[3:0]$11019 $2\src22__data_o$next[3:0]$11018 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src22__data_o$next[3:0]$11020 \w2__data_i - case - assign $4\src22__data_o$next[3:0]$11020 $3\src22__data_o$next[3:0]$11019 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src22__data_o$next[3:0]$11021 \reg - case - assign $5\src22__data_o$next[3:0]$11021 $4\src22__data_o$next[3:0]$11020 - end - case - assign $1\src22__data_o$next[3:0]$11017 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $6\src22__data_o$next[3:0]$11022 4'0000 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 case - assign $6\src22__data_o$next[3:0]$11022 $1\src22__data_o$next[3:0]$11017 + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11016 + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:169284.3-169313.6" - process $proc$libresoc.v:169284$11023 + attribute \src "libresoc.v:30776.3-30824.6" + process $proc$libresoc.v:30776$662 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11024 $1\wr_detect$4[0:0]$11025 - attribute \src "libresoc.v:169285.5-169285.29" + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:30777.5-30777.29" switch \initial - attribute \src "libresoc.v:169285.9-169285.17" + attribute \src "libresoc.v:30777.9-30777.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } - assign $1\wr_detect$4[0:0]$11025 $4\wr_detect$4[0:0]$11028 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11026 1'1 - case - assign $2\wr_detect$4[0:0]$11026 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11027 1'1 - case - assign $3\wr_detect$4[0:0]$11027 $2\wr_detect$4[0:0]$11026 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11028 1'1 - case - assign $4\wr_detect$4[0:0]$11028 $3\wr_detect$4[0:0]$11027 - end + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 case - assign $1\wr_detect$4[0:0]$11025 1'0 + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11024 + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:169314.3-169353.6" - process $proc$libresoc.v:169314$11029 + attribute \src "libresoc.v:30825.3-30873.6" + process $proc$libresoc.v:30825$663 assign { } { } assign { } { } - assign { } { } - assign $0\src32__data_o$next[3:0]$11030 $6\src32__data_o$next[3:0]$11036 - attribute \src "libresoc.v:169315.5-169315.29" + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:30826.5-30826.29" switch \initial - attribute \src "libresoc.v:169315.9-169315.17" + attribute \src "libresoc.v:30826.9-30826.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\src32__data_o$next[3:0]$11031 $5\src32__data_o$next[3:0]$11035 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src32__data_o$next[3:0]$11032 \dest12__data_i - case - assign $2\src32__data_o$next[3:0]$11032 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src32__data_o$next[3:0]$11033 \dest22__data_i - case - assign $3\src32__data_o$next[3:0]$11033 $2\src32__data_o$next[3:0]$11032 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src32__data_o$next[3:0]$11034 \w2__data_i - case - assign $4\src32__data_o$next[3:0]$11034 $3\src32__data_o$next[3:0]$11033 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src32__data_o$next[3:0]$11035 \reg - case - assign $5\src32__data_o$next[3:0]$11035 $4\src32__data_o$next[3:0]$11034 - end - case - assign $1\src32__data_o$next[3:0]$11031 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $6\src32__data_o$next[3:0]$11036 4'0000 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 case - assign $6\src32__data_o$next[3:0]$11036 $1\src32__data_o$next[3:0]$11031 + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11030 + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:169354.3-169383.6" - process $proc$libresoc.v:169354$11037 + attribute \src "libresoc.v:30874.3-30922.6" + process $proc$libresoc.v:30874$664 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11038 $1\wr_detect$7[0:0]$11039 - attribute \src "libresoc.v:169355.5-169355.29" + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:30875.5-30875.29" switch \initial - attribute \src "libresoc.v:169355.9-169355.17" + attribute \src "libresoc.v:30875.9-30875.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\wr_detect$7[0:0]$11039 $4\wr_detect$7[0:0]$11042 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$11040 1'1 - case - assign $2\wr_detect$7[0:0]$11040 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$11041 1'1 - case - assign $3\wr_detect$7[0:0]$11041 $2\wr_detect$7[0:0]$11040 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$11042 1'1 - case - assign $4\wr_detect$7[0:0]$11042 $3\wr_detect$7[0:0]$11041 - end + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 case - assign $1\wr_detect$7[0:0]$11039 1'0 + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11038 + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:169384.3-169423.6" - process $proc$libresoc.v:169384$11043 - assign { } { } + attribute \src "libresoc.v:30923.3-30971.6" + process $proc$libresoc.v:30923$665 assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11044 $6\r2__data_o$next[3:0]$11050 - attribute \src "libresoc.v:169385.5-169385.29" + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:30924.5-30924.29" switch \initial - attribute \src "libresoc.v:169385.9-169385.17" + attribute \src "libresoc.v:30924.9-30924.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\r2__data_o$next[3:0]$11045 $5\r2__data_o$next[3:0]$11049 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r2__data_o$next[3:0]$11046 \dest12__data_i - case - assign $2\r2__data_o$next[3:0]$11046 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r2__data_o$next[3:0]$11047 \dest22__data_i - case - assign $3\r2__data_o$next[3:0]$11047 $2\r2__data_o$next[3:0]$11046 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r2__data_o$next[3:0]$11048 \w2__data_i - case - assign $4\r2__data_o$next[3:0]$11048 $3\r2__data_o$next[3:0]$11047 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r2__data_o$next[3:0]$11049 \reg - case - assign $5\r2__data_o$next[3:0]$11049 $4\r2__data_o$next[3:0]$11048 - end - case - assign $1\r2__data_o$next[3:0]$11045 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $6\r2__data_o$next[3:0]$11050 4'0000 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 case - assign $6\r2__data_o$next[3:0]$11050 $1\r2__data_o$next[3:0]$11045 + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11044 + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:169424.3-169453.6" - process $proc$libresoc.v:169424$11051 + attribute \src "libresoc.v:30972.3-31020.6" + process $proc$libresoc.v:30972$666 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11052 $1\wr_detect$10[0:0]$11053 - attribute \src "libresoc.v:169425.5-169425.29" + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:30973.5-30973.29" switch \initial - attribute \src "libresoc.v:169425.9-169425.17" + attribute \src "libresoc.v:30973.9-30973.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\wr_detect$10[0:0]$11053 $4\wr_detect$10[0:0]$11056 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11054 1'1 - case - assign $2\wr_detect$10[0:0]$11054 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11055 1'1 - case - assign $3\wr_detect$10[0:0]$11055 $2\wr_detect$10[0:0]$11054 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11056 1'1 - case - assign $4\wr_detect$10[0:0]$11056 $3\wr_detect$10[0:0]$11055 - end + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 case - assign $1\wr_detect$10[0:0]$11053 1'0 + assign $1\dec31_dec_sub23_br[0:0] 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11052 + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:169454.3-169493.6" - process $proc$libresoc.v:169454$11057 - assign { } { } + attribute \src "libresoc.v:31021.3-31069.6" + process $proc$libresoc.v:31021$667 assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11058 $6\r22__data_o$next[3:0]$11064 - attribute \src "libresoc.v:169455.5-169455.29" + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:31022.5-31022.29" switch \initial - attribute \src "libresoc.v:169455.9-169455.17" + attribute \src "libresoc.v:31022.9-31022.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\r22__data_o$next[3:0]$11059 $5\r22__data_o$next[3:0]$11063 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r22__data_o$next[3:0]$11060 \dest12__data_i - case - assign $2\r22__data_o$next[3:0]$11060 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r22__data_o$next[3:0]$11061 \dest22__data_i - case - assign $3\r22__data_o$next[3:0]$11061 $2\r22__data_o$next[3:0]$11060 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r22__data_o$next[3:0]$11062 \w2__data_i - case - assign $4\r22__data_o$next[3:0]$11062 $3\r22__data_o$next[3:0]$11061 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r22__data_o$next[3:0]$11063 \reg - case - assign $5\r22__data_o$next[3:0]$11063 $4\r22__data_o$next[3:0]$11062 - end - case - assign $1\r22__data_o$next[3:0]$11059 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $6\r22__data_o$next[3:0]$11064 4'0000 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 case - assign $6\r22__data_o$next[3:0]$11064 $1\r22__data_o$next[3:0]$11059 + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11058 + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:169494.3-169523.6" - process $proc$libresoc.v:169494$11065 + attribute \src "libresoc.v:31070.3-31118.6" + process $proc$libresoc.v:31070$668 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11066 $1\wr_detect$13[0:0]$11067 - attribute \src "libresoc.v:169495.5-169495.29" + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:31071.5-31071.29" switch \initial - attribute \src "libresoc.v:169495.9-169495.17" + attribute \src "libresoc.v:31071.9-31071.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r22__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\wr_detect$13[0:0]$11067 $4\wr_detect$13[0:0]$11070 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$11068 1'1 - case - assign $2\wr_detect$13[0:0]$11068 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$11069 1'1 - case - assign $3\wr_detect$13[0:0]$11069 $2\wr_detect$13[0:0]$11068 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$11070 1'1 - case - assign $4\wr_detect$13[0:0]$11070 $3\wr_detect$13[0:0]$11069 - end + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 case - assign $1\wr_detect$13[0:0]$11067 1'0 + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11066 - end - connect \$9 $not$libresoc.v:169130$10989_Y - connect \$12 $not$libresoc.v:169131$10990_Y - connect \$1 $not$libresoc.v:169132$10991_Y - connect \$3 $not$libresoc.v:169133$10992_Y - connect \$6 $not$libresoc.v:169134$10993_Y -end -attribute \src "libresoc.v:169528.1-169973.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" -attribute \generator "nMigen" -module \reg_2$134 - attribute \src "libresoc.v:169529.7-169529.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $0\r2__data_o$next[1:0]$11130 - attribute \src "libresoc.v:169604.3-169605.37" - wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:169940.3-169972.6" - wire width 2 $0\reg$next[1:0]$11146 - attribute \src "libresoc.v:169602.3-169603.25" - wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $0\src12__data_o$next[1:0]$11088 - attribute \src "libresoc.v:169610.3-169611.43" - wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $0\src22__data_o$next[1:0]$11098 - attribute \src "libresoc.v:169608.3-169609.43" - wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $0\src32__data_o$next[1:0]$11114 - attribute \src "libresoc.v:169606.3-169607.43" - wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:169904.3-169939.6" - wire $0\wr_detect$10[0:0]$11139 - attribute \src "libresoc.v:169740.3-169775.6" - wire $0\wr_detect$4[0:0]$11107 - attribute \src "libresoc.v:169822.3-169857.6" - wire $0\wr_detect$7[0:0]$11123 - attribute \src "libresoc.v:169658.3-169693.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $1\r2__data_o$next[1:0]$11131 - attribute \src "libresoc.v:169556.13-169556.30" - wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:169940.3-169972.6" - wire width 2 $1\reg$next[1:0]$11147 - attribute \src "libresoc.v:169562.13-169562.25" - wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $1\src12__data_o$next[1:0]$11089 - attribute \src "libresoc.v:169567.13-169567.33" - wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $1\src22__data_o$next[1:0]$11099 - attribute \src "libresoc.v:169574.13-169574.33" - wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $1\src32__data_o$next[1:0]$11115 - attribute \src "libresoc.v:169581.13-169581.33" - wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:169904.3-169939.6" - wire $1\wr_detect$10[0:0]$11140 - attribute \src "libresoc.v:169740.3-169775.6" - wire $1\wr_detect$4[0:0]$11108 - attribute \src "libresoc.v:169822.3-169857.6" - wire $1\wr_detect$7[0:0]$11124 - attribute \src "libresoc.v:169658.3-169693.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $2\r2__data_o$next[1:0]$11132 - attribute \src "libresoc.v:169940.3-169972.6" - wire width 2 $2\reg$next[1:0]$11148 - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $2\src12__data_o$next[1:0]$11090 - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $2\src22__data_o$next[1:0]$11100 - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $2\src32__data_o$next[1:0]$11116 - attribute \src "libresoc.v:169904.3-169939.6" - wire $2\wr_detect$10[0:0]$11141 - attribute \src "libresoc.v:169740.3-169775.6" - wire $2\wr_detect$4[0:0]$11109 - attribute \src "libresoc.v:169822.3-169857.6" - wire $2\wr_detect$7[0:0]$11125 - attribute \src "libresoc.v:169658.3-169693.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $3\r2__data_o$next[1:0]$11133 - attribute \src "libresoc.v:169940.3-169972.6" - wire width 2 $3\reg$next[1:0]$11149 - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $3\src12__data_o$next[1:0]$11091 - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $3\src22__data_o$next[1:0]$11101 - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $3\src32__data_o$next[1:0]$11117 - attribute \src "libresoc.v:169904.3-169939.6" - wire $3\wr_detect$10[0:0]$11142 - attribute \src "libresoc.v:169740.3-169775.6" - wire $3\wr_detect$4[0:0]$11110 - attribute \src "libresoc.v:169822.3-169857.6" - wire $3\wr_detect$7[0:0]$11126 - attribute \src "libresoc.v:169658.3-169693.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $4\r2__data_o$next[1:0]$11134 - attribute \src "libresoc.v:169940.3-169972.6" - wire width 2 $4\reg$next[1:0]$11150 - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $4\src12__data_o$next[1:0]$11092 - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $4\src22__data_o$next[1:0]$11102 - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $4\src32__data_o$next[1:0]$11118 - attribute \src "libresoc.v:169904.3-169939.6" - wire $4\wr_detect$10[0:0]$11143 - attribute \src "libresoc.v:169740.3-169775.6" - wire $4\wr_detect$4[0:0]$11111 - attribute \src "libresoc.v:169822.3-169857.6" - wire $4\wr_detect$7[0:0]$11127 - attribute \src "libresoc.v:169658.3-169693.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $5\r2__data_o$next[1:0]$11135 - attribute \src "libresoc.v:169940.3-169972.6" - wire width 2 $5\reg$next[1:0]$11151 - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $5\src12__data_o$next[1:0]$11093 - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $5\src22__data_o$next[1:0]$11103 - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $5\src32__data_o$next[1:0]$11119 - attribute \src "libresoc.v:169904.3-169939.6" - wire $5\wr_detect$10[0:0]$11144 - attribute \src "libresoc.v:169740.3-169775.6" - wire $5\wr_detect$4[0:0]$11112 - attribute \src "libresoc.v:169822.3-169857.6" - wire $5\wr_detect$7[0:0]$11128 - attribute \src "libresoc.v:169658.3-169693.6" - wire $5\wr_detect[0:0] - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $6\r2__data_o$next[1:0]$11136 - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $6\src12__data_o$next[1:0]$11094 - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $6\src22__data_o$next[1:0]$11104 - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $6\src32__data_o$next[1:0]$11120 - attribute \src "libresoc.v:169858.3-169903.6" - wire width 2 $7\r2__data_o$next[1:0]$11137 - attribute \src "libresoc.v:169612.3-169657.6" - wire width 2 $7\src12__data_o$next[1:0]$11095 - attribute \src "libresoc.v:169694.3-169739.6" - wire width 2 $7\src22__data_o$next[1:0]$11105 - attribute \src "libresoc.v:169776.3-169821.6" - wire width 2 $7\src32__data_o$next[1:0]$11121 - attribute \src "libresoc.v:169598.17-169598.104" - wire $not$libresoc.v:169598$11078_Y - attribute \src "libresoc.v:169599.17-169599.100" - wire $not$libresoc.v:169599$11079_Y - attribute \src "libresoc.v:169600.17-169600.103" - wire $not$libresoc.v:169600$11080_Y - attribute \src "libresoc.v:169601.17-169601.103" - wire $not$libresoc.v:169601$11081_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 12 \dest32__wen - attribute \src "libresoc.v:169529.7-169529.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169598$11078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:169598$11078_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169599$11079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:169599$11079_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169600$11080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:169600$11080_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:169601$11081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:169601$11081_Y - end - attribute \src "libresoc.v:169529.7-169529.20" - process $proc$libresoc.v:169529$11152 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:169556.13-169556.30" - process $proc$libresoc.v:169556$11153 - assign { } { } - assign $1\r2__data_o[1:0] 2'00 - sync always - sync init - update \r2__data_o $1\r2__data_o[1:0] - end - attribute \src "libresoc.v:169562.13-169562.25" - process $proc$libresoc.v:169562$11154 - assign { } { } - assign $1\reg[1:0] 2'00 - sync always - sync init - update \reg $1\reg[1:0] - end - attribute \src "libresoc.v:169567.13-169567.33" - process $proc$libresoc.v:169567$11155 - assign { } { } - assign $1\src12__data_o[1:0] 2'00 - sync always - sync init - update \src12__data_o $1\src12__data_o[1:0] - end - attribute \src "libresoc.v:169574.13-169574.33" - process $proc$libresoc.v:169574$11156 - assign { } { } - assign $1\src22__data_o[1:0] 2'00 - sync always - sync init - update \src22__data_o $1\src22__data_o[1:0] - end - attribute \src "libresoc.v:169581.13-169581.33" - process $proc$libresoc.v:169581$11157 - assign { } { } - assign $1\src32__data_o[1:0] 2'00 - sync always - sync init - update \src32__data_o $1\src32__data_o[1:0] - end - attribute \src "libresoc.v:169602.3-169603.25" - process $proc$libresoc.v:169602$11082 - assign { } { } - assign $0\reg[1:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[1:0] - end - attribute \src "libresoc.v:169604.3-169605.37" - process $proc$libresoc.v:169604$11083 - assign { } { } - assign $0\r2__data_o[1:0] \r2__data_o$next - sync posedge \coresync_clk - update \r2__data_o $0\r2__data_o[1:0] - end - attribute \src "libresoc.v:169606.3-169607.43" - process $proc$libresoc.v:169606$11084 - assign { } { } - assign $0\src32__data_o[1:0] \src32__data_o$next - sync posedge \coresync_clk - update \src32__data_o $0\src32__data_o[1:0] - end - attribute \src "libresoc.v:169608.3-169609.43" - process $proc$libresoc.v:169608$11085 - assign { } { } - assign $0\src22__data_o[1:0] \src22__data_o$next - sync posedge \coresync_clk - update \src22__data_o $0\src22__data_o[1:0] - end - attribute \src "libresoc.v:169610.3-169611.43" - process $proc$libresoc.v:169610$11086 - assign { } { } - assign $0\src12__data_o[1:0] \src12__data_o$next - sync posedge \coresync_clk - update \src12__data_o $0\src12__data_o[1:0] + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:169612.3-169657.6" - process $proc$libresoc.v:169612$11087 + attribute \src "libresoc.v:31119.3-31167.6" + process $proc$libresoc.v:31119$669 assign { } { } assign { } { } - assign { } { } - assign $0\src12__data_o$next[1:0]$11088 $7\src12__data_o$next[1:0]$11095 - attribute \src "libresoc.v:169613.5-169613.29" + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:31120.5-31120.29" switch \initial - attribute \src "libresoc.v:169613.9-169613.17" + attribute \src "libresoc.v:31120.9-31120.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\src12__data_o$next[1:0]$11089 $6\src12__data_o$next[1:0]$11094 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src12__data_o$next[1:0]$11090 \dest12__data_i - case - assign $2\src12__data_o$next[1:0]$11090 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src12__data_o$next[1:0]$11091 \dest22__data_i - case - assign $3\src12__data_o$next[1:0]$11091 $2\src12__data_o$next[1:0]$11090 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src12__data_o$next[1:0]$11092 \dest32__data_i - case - assign $4\src12__data_o$next[1:0]$11092 $3\src12__data_o$next[1:0]$11091 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src12__data_o$next[1:0]$11093 \w2__data_i - case - assign $5\src12__data_o$next[1:0]$11093 $4\src12__data_o$next[1:0]$11092 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src12__data_o$next[1:0]$11094 \reg - case - assign $6\src12__data_o$next[1:0]$11094 $5\src12__data_o$next[1:0]$11093 - end - case - assign $1\src12__data_o$next[1:0]$11089 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $7\src12__data_o$next[1:0]$11095 2'00 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 case - assign $7\src12__data_o$next[1:0]$11095 $1\src12__data_o$next[1:0]$11089 + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11088 + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:169658.3-169693.6" - process $proc$libresoc.v:169658$11096 + attribute \src "libresoc.v:31168.3-31216.6" + process $proc$libresoc.v:31168$670 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:169659.5-169659.29" + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:31169.5-31169.29" switch \initial - attribute \src "libresoc.v:169659.9-169659.17" + attribute \src "libresoc.v:31169.9-31169.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src12__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\wr_detect[0:0] $5\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect[0:0] 1'1 - case - assign $5\wr_detect[0:0] $4\wr_detect[0:0] - end - case - assign $1\wr_detect[0:0] 1'0 - end - sync always - update \wr_detect $0\wr_detect[0:0] - end - attribute \src "libresoc.v:169694.3-169739.6" - process $proc$libresoc.v:169694$11097 - assign { } { } - assign { } { } - assign { } { } - assign $0\src22__data_o$next[1:0]$11098 $7\src22__data_o$next[1:0]$11105 - attribute \src "libresoc.v:169695.5-169695.29" - switch \initial - attribute \src "libresoc.v:169695.9-169695.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\src22__data_o$next[1:0]$11099 $6\src22__data_o$next[1:0]$11104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src22__data_o$next[1:0]$11100 \dest12__data_i - case - assign $2\src22__data_o$next[1:0]$11100 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src22__data_o$next[1:0]$11101 \dest22__data_i - case - assign $3\src22__data_o$next[1:0]$11101 $2\src22__data_o$next[1:0]$11100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src22__data_o$next[1:0]$11102 \dest32__data_i - case - assign $4\src22__data_o$next[1:0]$11102 $3\src22__data_o$next[1:0]$11101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src22__data_o$next[1:0]$11103 \w2__data_i - case - assign $5\src22__data_o$next[1:0]$11103 $4\src22__data_o$next[1:0]$11102 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src22__data_o$next[1:0]$11104 \reg - case - assign $6\src22__data_o$next[1:0]$11104 $5\src22__data_o$next[1:0]$11103 - end - case - assign $1\src22__data_o$next[1:0]$11099 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $7\src22__data_o$next[1:0]$11105 2'00 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 case - assign $7\src22__data_o$next[1:0]$11105 $1\src22__data_o$next[1:0]$11099 + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11098 + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:169740.3-169775.6" - process $proc$libresoc.v:169740$11106 + attribute \src "libresoc.v:31217.3-31265.6" + process $proc$libresoc.v:31217$671 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11107 $1\wr_detect$4[0:0]$11108 - attribute \src "libresoc.v:169741.5-169741.29" + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:31218.5-31218.29" switch \initial - attribute \src "libresoc.v:169741.9-169741.17" + attribute \src "libresoc.v:31218.9-31218.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src22__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\wr_detect$4[0:0]$11108 $5\wr_detect$4[0:0]$11112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11109 1'1 - case - assign $2\wr_detect$4[0:0]$11109 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11110 1'1 - case - assign $3\wr_detect$4[0:0]$11110 $2\wr_detect$4[0:0]$11109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11111 1'1 - case - assign $4\wr_detect$4[0:0]$11111 $3\wr_detect$4[0:0]$11110 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$4[0:0]$11112 1'1 - case - assign $5\wr_detect$4[0:0]$11112 $4\wr_detect$4[0:0]$11111 - end - case - assign $1\wr_detect$4[0:0]$11108 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11107 - end - attribute \src "libresoc.v:169776.3-169821.6" - process $proc$libresoc.v:169776$11113 - assign { } { } - assign { } { } - assign { } { } - assign $0\src32__data_o$next[1:0]$11114 $7\src32__data_o$next[1:0]$11121 - attribute \src "libresoc.v:169777.5-169777.29" - switch \initial - attribute \src "libresoc.v:169777.9-169777.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\src32__data_o$next[1:0]$11115 $6\src32__data_o$next[1:0]$11120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src32__data_o$next[1:0]$11116 \dest12__data_i - case - assign $2\src32__data_o$next[1:0]$11116 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src32__data_o$next[1:0]$11117 \dest22__data_i - case - assign $3\src32__data_o$next[1:0]$11117 $2\src32__data_o$next[1:0]$11116 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src32__data_o$next[1:0]$11118 \dest32__data_i - case - assign $4\src32__data_o$next[1:0]$11118 $3\src32__data_o$next[1:0]$11117 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src32__data_o$next[1:0]$11119 \w2__data_i - case - assign $5\src32__data_o$next[1:0]$11119 $4\src32__data_o$next[1:0]$11118 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\src32__data_o$next[1:0]$11120 \reg - case - assign $6\src32__data_o$next[1:0]$11120 $5\src32__data_o$next[1:0]$11119 - end - case - assign $1\src32__data_o$next[1:0]$11115 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 assign { } { } - assign $7\src32__data_o$next[1:0]$11121 2'00 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 case - assign $7\src32__data_o$next[1:0]$11121 $1\src32__data_o$next[1:0]$11115 + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11114 + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:169822.3-169857.6" - process $proc$libresoc.v:169822$11122 + attribute \src "libresoc.v:31266.3-31314.6" + process $proc$libresoc.v:31266$672 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11123 $1\wr_detect$7[0:0]$11124 - attribute \src "libresoc.v:169823.5-169823.29" + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:31267.5-31267.29" switch \initial - attribute \src "libresoc.v:169823.9-169823.17" + attribute \src "libresoc.v:31267.9-31267.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src32__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign $1\wr_detect$7[0:0]$11124 $5\wr_detect$7[0:0]$11128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$11125 1'1 - case - assign $2\wr_detect$7[0:0]$11125 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$11126 1'1 - case - assign $3\wr_detect$7[0:0]$11126 $2\wr_detect$7[0:0]$11125 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$11127 1'1 - case - assign $4\wr_detect$7[0:0]$11127 $3\wr_detect$7[0:0]$11126 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$7[0:0]$11128 1'1 - case - assign $5\wr_detect$7[0:0]$11128 $4\wr_detect$7[0:0]$11127 - end - case - assign $1\wr_detect$7[0:0]$11124 1'0 - end - sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11123 - end - attribute \src "libresoc.v:169858.3-169903.6" - process $proc$libresoc.v:169858$11129 - assign { } { } - assign { } { } - assign { } { } - assign $0\r2__data_o$next[1:0]$11130 $7\r2__data_o$next[1:0]$11137 - attribute \src "libresoc.v:169859.5-169859.29" - switch \initial - attribute \src "libresoc.v:169859.9-169859.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\r2__data_o$next[1:0]$11131 $6\r2__data_o$next[1:0]$11136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r2__data_o$next[1:0]$11132 \dest12__data_i - case - assign $2\r2__data_o$next[1:0]$11132 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r2__data_o$next[1:0]$11133 \dest22__data_i - case - assign $3\r2__data_o$next[1:0]$11133 $2\r2__data_o$next[1:0]$11132 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r2__data_o$next[1:0]$11134 \dest32__data_i - case - assign $4\r2__data_o$next[1:0]$11134 $3\r2__data_o$next[1:0]$11133 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r2__data_o$next[1:0]$11135 \w2__data_i - case - assign $5\r2__data_o$next[1:0]$11135 $4\r2__data_o$next[1:0]$11134 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $6\r2__data_o$next[1:0]$11136 \reg - case - assign $6\r2__data_o$next[1:0]$11136 $5\r2__data_o$next[1:0]$11135 - end - case - assign $1\r2__data_o$next[1:0]$11131 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 assign { } { } - assign $7\r2__data_o$next[1:0]$11137 2'00 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 case - assign $7\r2__data_o$next[1:0]$11137 $1\r2__data_o$next[1:0]$11131 + assign $1\dec31_dec_sub23_lk[0:0] 1'0 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11130 + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:169904.3-169939.6" - process $proc$libresoc.v:169904$11138 + attribute \src "libresoc.v:31315.3-31363.6" + process $proc$libresoc.v:31315$673 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11139 $1\wr_detect$10[0:0]$11140 - attribute \src "libresoc.v:169905.5-169905.29" + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:31316.5-31316.29" switch \initial - attribute \src "libresoc.v:169905.9-169905.17" + attribute \src "libresoc.v:31316.9-31316.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\wr_detect$10[0:0]$11140 $5\wr_detect$10[0:0]$11144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11141 1'1 - case - assign $2\wr_detect$10[0:0]$11141 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest22__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11142 1'1 - case - assign $3\wr_detect$10[0:0]$11142 $2\wr_detect$10[0:0]$11141 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest32__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11143 1'1 - case - assign $4\wr_detect$10[0:0]$11143 $3\wr_detect$10[0:0]$11142 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\wr_detect$10[0:0]$11144 1'1 - case - assign $5\wr_detect$10[0:0]$11144 $4\wr_detect$10[0:0]$11143 - end - case - assign $1\wr_detect$10[0:0]$11140 1'0 - end - sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11139 - end - attribute \src "libresoc.v:169940.3-169972.6" - process $proc$libresoc.v:169940$11145 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[1:0]$11146 $5\reg$next[1:0]$11151 - attribute \src "libresoc.v:169941.5-169941.29" - switch \initial - attribute \src "libresoc.v:169941.9-169941.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest12__wen + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $1\reg$next[1:0]$11147 \dest12__data_i - case - assign $1\reg$next[1:0]$11147 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest22__wen + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $2\reg$next[1:0]$11148 \dest22__data_i - case - assign $2\reg$next[1:0]$11148 $1\reg$next[1:0]$11147 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest32__wen + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $3\reg$next[1:0]$11149 \dest32__data_i - case - assign $3\reg$next[1:0]$11149 $2\reg$next[1:0]$11148 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w2__wen + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $4\reg$next[1:0]$11150 \w2__data_i - case - assign $4\reg$next[1:0]$11150 $3\reg$next[1:0]$11149 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 assign { } { } - assign $5\reg$next[1:0]$11151 2'00 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 case - assign $5\reg$next[1:0]$11151 $4\reg$next[1:0]$11150 + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 end sync always - update \reg$next $0\reg$next[1:0]$11146 - end - connect \$9 $not$libresoc.v:169598$11078_Y - connect \$1 $not$libresoc.v:169599$11079_Y - connect \$3 $not$libresoc.v:169600$11080_Y - connect \$6 $not$libresoc.v:169601$11081_Y -end -attribute \src "libresoc.v:169977.1-170196.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" -attribute \generator "nMigen" -module \reg_2$137 - attribute \src "libresoc.v:170029.3-170068.6" - wire width 64 $0\cia2__data_o$next[63:0]$11164 - attribute \src "libresoc.v:170027.3-170028.41" - wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:169978.7-169978.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:170099.3-170138.6" - wire width 64 $0\msr2__data_o$next[63:0]$11173 - attribute \src "libresoc.v:170025.3-170026.41" - wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:170169.3-170195.6" - wire width 64 $0\reg$next[63:0]$11187 - attribute \src "libresoc.v:170023.3-170024.25" - wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:170139.3-170168.6" - wire $0\wr_detect$4[0:0]$11181 - attribute \src "libresoc.v:170069.3-170098.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:170029.3-170068.6" - wire width 64 $1\cia2__data_o$next[63:0]$11165 - attribute \src "libresoc.v:169985.14-169985.49" - wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:170099.3-170138.6" - wire width 64 $1\msr2__data_o$next[63:0]$11174 - attribute \src "libresoc.v:170002.14-170002.49" - wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:170169.3-170195.6" - wire width 64 $1\reg$next[63:0]$11188 - attribute \src "libresoc.v:170014.14-170014.42" - wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:170139.3-170168.6" - wire $1\wr_detect$4[0:0]$11182 - attribute \src "libresoc.v:170069.3-170098.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:170029.3-170068.6" - wire width 64 $2\cia2__data_o$next[63:0]$11166 - attribute \src "libresoc.v:170099.3-170138.6" - wire width 64 $2\msr2__data_o$next[63:0]$11175 - attribute \src "libresoc.v:170169.3-170195.6" - wire width 64 $2\reg$next[63:0]$11189 - attribute \src "libresoc.v:170139.3-170168.6" - wire $2\wr_detect$4[0:0]$11183 - attribute \src "libresoc.v:170069.3-170098.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:170029.3-170068.6" - wire width 64 $3\cia2__data_o$next[63:0]$11167 - attribute \src "libresoc.v:170099.3-170138.6" - wire width 64 $3\msr2__data_o$next[63:0]$11176 - attribute \src "libresoc.v:170169.3-170195.6" - wire width 64 $3\reg$next[63:0]$11190 - attribute \src "libresoc.v:170139.3-170168.6" - wire $3\wr_detect$4[0:0]$11184 - attribute \src "libresoc.v:170069.3-170098.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:170029.3-170068.6" - wire width 64 $4\cia2__data_o$next[63:0]$11168 - attribute \src "libresoc.v:170099.3-170138.6" - wire width 64 $4\msr2__data_o$next[63:0]$11177 - attribute \src "libresoc.v:170169.3-170195.6" - wire width 64 $4\reg$next[63:0]$11191 - attribute \src "libresoc.v:170139.3-170168.6" - wire $4\wr_detect$4[0:0]$11185 - attribute \src "libresoc.v:170069.3-170098.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:170029.3-170068.6" - wire width 64 $5\cia2__data_o$next[63:0]$11169 - attribute \src "libresoc.v:170099.3-170138.6" - wire width 64 $5\msr2__data_o$next[63:0]$11178 - attribute \src "libresoc.v:170029.3-170068.6" - wire width 64 $6\cia2__data_o$next[63:0]$11170 - attribute \src "libresoc.v:170099.3-170138.6" - wire width 64 $6\msr2__data_o$next[63:0]$11179 - attribute \src "libresoc.v:170021.17-170021.100" - wire $not$libresoc.v:170021$11158_Y - attribute \src "libresoc.v:170022.17-170022.103" - wire $not$libresoc.v:170022$11159_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr12__wen - attribute \src "libresoc.v:169978.7-169978.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170021$11158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:170021$11158_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170022$11159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:170022$11159_Y - end - attribute \src "libresoc.v:169978.7-169978.20" - process $proc$libresoc.v:169978$11192 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:169985.14-169985.49" - process $proc$libresoc.v:169985$11193 - assign { } { } - assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia2__data_o $1\cia2__data_o[63:0] - end - attribute \src "libresoc.v:170002.14-170002.49" - process $proc$libresoc.v:170002$11194 - assign { } { } - assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr2__data_o $1\msr2__data_o[63:0] - end - attribute \src "libresoc.v:170014.14-170014.42" - process $proc$libresoc.v:170014$11195 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "libresoc.v:170023.3-170024.25" - process $proc$libresoc.v:170023$11160 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "libresoc.v:170025.3-170026.41" - process $proc$libresoc.v:170025$11161 - assign { } { } - assign $0\msr2__data_o[63:0] \msr2__data_o$next - sync posedge \coresync_clk - update \msr2__data_o $0\msr2__data_o[63:0] - end - attribute \src "libresoc.v:170027.3-170028.41" - process $proc$libresoc.v:170027$11162 - assign { } { } - assign $0\cia2__data_o[63:0] \cia2__data_o$next - sync posedge \coresync_clk - update \cia2__data_o $0\cia2__data_o[63:0] + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:170029.3-170068.6" - process $proc$libresoc.v:170029$11163 + attribute \src "libresoc.v:31364.3-31412.6" + process $proc$libresoc.v:31364$674 assign { } { } assign { } { } - assign { } { } - assign $0\cia2__data_o$next[63:0]$11164 $6\cia2__data_o$next[63:0]$11170 - attribute \src "libresoc.v:170030.5-170030.29" + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:31365.5-31365.29" switch \initial - attribute \src "libresoc.v:170030.9-170030.17" + attribute \src "libresoc.v:31365.9-31365.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\cia2__data_o$next[63:0]$11165 $5\cia2__data_o$next[63:0]$11169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia2__data_o$next[63:0]$11166 \nia2__data_i - case - assign $2\cia2__data_o$next[63:0]$11166 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia2__data_o$next[63:0]$11167 \msr2__data_i - case - assign $3\cia2__data_o$next[63:0]$11167 $2\cia2__data_o$next[63:0]$11166 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia2__data_o$next[63:0]$11168 \d_wr12__data_i - case - assign $4\cia2__data_o$next[63:0]$11168 $3\cia2__data_o$next[63:0]$11167 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia2__data_o$next[63:0]$11169 \reg - case - assign $5\cia2__data_o$next[63:0]$11169 $4\cia2__data_o$next[63:0]$11168 - end - case - assign $1\cia2__data_o$next[63:0]$11165 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $6\cia2__data_o$next[63:0]$11170 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\cia2__data_o$next[63:0]$11170 $1\cia2__data_o$next[63:0]$11165 - end - sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11164 - end - attribute \src "libresoc.v:170069.3-170098.6" - process $proc$libresoc.v:170069$11171 - assign { } { } - assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:170070.5-170070.29" - switch \initial - attribute \src "libresoc.v:170070.9-170070.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia2__ren + assign $1\dec31_dec_sub23_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub23_form[4:0] 5'00000 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:170099.3-170138.6" - process $proc$libresoc.v:170099$11172 - assign { } { } + attribute \src "libresoc.v:31413.3-31461.6" + process $proc$libresoc.v:31413$675 assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11173 $6\msr2__data_o$next[63:0]$11179 - attribute \src "libresoc.v:170100.5-170100.29" + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:31414.5-31414.29" switch \initial - attribute \src "libresoc.v:170100.9-170100.17" + attribute \src "libresoc.v:31414.9-31414.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\msr2__data_o$next[63:0]$11174 $5\msr2__data_o$next[63:0]$11178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr2__data_o$next[63:0]$11175 \nia2__data_i - case - assign $2\msr2__data_o$next[63:0]$11175 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr2__data_o$next[63:0]$11176 \msr2__data_i - case - assign $3\msr2__data_o$next[63:0]$11176 $2\msr2__data_o$next[63:0]$11175 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr2__data_o$next[63:0]$11177 \d_wr12__data_i - case - assign $4\msr2__data_o$next[63:0]$11177 $3\msr2__data_o$next[63:0]$11176 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr2__data_o$next[63:0]$11178 \reg - case - assign $5\msr2__data_o$next[63:0]$11178 $4\msr2__data_o$next[63:0]$11177 - end - case - assign $1\msr2__data_o$next[63:0]$11174 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 assign { } { } - assign $6\msr2__data_o$next[63:0]$11179 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $6\msr2__data_o$next[63:0]$11179 $1\msr2__data_o$next[63:0]$11174 - end - sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11173 - end - attribute \src "libresoc.v:170139.3-170168.6" - process $proc$libresoc.v:170139$11180 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$11181 $1\wr_detect$4[0:0]$11182 - attribute \src "libresoc.v:170140.5-170140.29" - switch \initial - attribute \src "libresoc.v:170140.9-170140.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr2__ren + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\wr_detect$4[0:0]$11182 $4\wr_detect$4[0:0]$11185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11183 1'1 - case - assign $2\wr_detect$4[0:0]$11183 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr2__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11184 1'1 - case - assign $3\wr_detect$4[0:0]$11184 $2\wr_detect$4[0:0]$11183 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr12__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11185 1'1 - case - assign $4\wr_detect$4[0:0]$11185 $3\wr_detect$4[0:0]$11184 - end - case - assign $1\wr_detect$4[0:0]$11182 1'0 - end - sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11181 - end - attribute \src "libresoc.v:170169.3-170195.6" - process $proc$libresoc.v:170169$11186 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$11187 $4\reg$next[63:0]$11191 - attribute \src "libresoc.v:170170.5-170170.29" - switch \initial - attribute \src "libresoc.v:170170.9-170170.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia2__wen + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } - assign $1\reg$next[63:0]$11188 \nia2__data_i - case - assign $1\reg$next[63:0]$11188 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr2__wen + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $2\reg$next[63:0]$11189 \msr2__data_i - case - assign $2\reg$next[63:0]$11189 $1\reg$next[63:0]$11188 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr12__wen + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $3\reg$next[63:0]$11190 \d_wr12__data_i - case - assign $3\reg$next[63:0]$11190 $2\reg$next[63:0]$11189 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00101 assign { } { } - assign $4\reg$next[63:0]$11191 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 case - assign $4\reg$next[63:0]$11191 $3\reg$next[63:0]$11190 + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 end sync always - update \reg$next $0\reg$next[63:0]$11187 - end - connect \$1 $not$libresoc.v:170021$11158_Y - connect \$3 $not$libresoc.v:170022$11159_Y -end -attribute \src "libresoc.v:170200.1-170671.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" -attribute \generator "nMigen" -module \reg_3 - attribute \src "libresoc.v:170201.7-170201.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:170601.3-170640.6" - wire width 4 $0\r23__data_o$next[3:0]$11265 - attribute \src "libresoc.v:170284.3-170285.39" - wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:170531.3-170570.6" - wire width 4 $0\r3__data_o$next[3:0]$11251 - attribute \src "libresoc.v:170286.3-170287.37" - wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:170364.3-170390.6" - wire width 4 $0\reg$next[3:0]$11217 - attribute \src "libresoc.v:170282.3-170283.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:170294.3-170333.6" - wire width 4 $0\src13__data_o$next[3:0]$11208 - attribute \src "libresoc.v:170292.3-170293.43" - wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:170391.3-170430.6" - wire width 4 $0\src23__data_o$next[3:0]$11223 - attribute \src "libresoc.v:170290.3-170291.43" - wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:170461.3-170500.6" - wire width 4 $0\src33__data_o$next[3:0]$11237 - attribute \src "libresoc.v:170288.3-170289.43" - wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:170571.3-170600.6" - wire $0\wr_detect$10[0:0]$11259 - attribute \src "libresoc.v:170641.3-170670.6" - wire $0\wr_detect$13[0:0]$11273 - attribute \src "libresoc.v:170431.3-170460.6" - wire $0\wr_detect$4[0:0]$11231 - attribute \src "libresoc.v:170501.3-170530.6" - wire $0\wr_detect$7[0:0]$11245 - attribute \src "libresoc.v:170334.3-170363.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:170601.3-170640.6" - wire width 4 $1\r23__data_o$next[3:0]$11266 - attribute \src "libresoc.v:170226.13-170226.31" - wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:170531.3-170570.6" - wire width 4 $1\r3__data_o$next[3:0]$11252 - attribute \src "libresoc.v:170233.13-170233.30" - wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:170364.3-170390.6" - wire width 4 $1\reg$next[3:0]$11218 - attribute \src "libresoc.v:170239.13-170239.25" - wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:170294.3-170333.6" - wire width 4 $1\src13__data_o$next[3:0]$11209 - attribute \src "libresoc.v:170244.13-170244.33" - wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:170391.3-170430.6" - wire width 4 $1\src23__data_o$next[3:0]$11224 - attribute \src "libresoc.v:170251.13-170251.33" - wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:170461.3-170500.6" - wire width 4 $1\src33__data_o$next[3:0]$11238 - attribute \src "libresoc.v:170258.13-170258.33" - wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:170571.3-170600.6" - wire $1\wr_detect$10[0:0]$11260 - attribute \src "libresoc.v:170641.3-170670.6" - wire $1\wr_detect$13[0:0]$11274 - attribute \src "libresoc.v:170431.3-170460.6" - wire $1\wr_detect$4[0:0]$11232 - attribute \src "libresoc.v:170501.3-170530.6" - wire $1\wr_detect$7[0:0]$11246 - attribute \src "libresoc.v:170334.3-170363.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:170601.3-170640.6" - wire width 4 $2\r23__data_o$next[3:0]$11267 - attribute \src "libresoc.v:170531.3-170570.6" - wire width 4 $2\r3__data_o$next[3:0]$11253 - attribute \src "libresoc.v:170364.3-170390.6" - wire width 4 $2\reg$next[3:0]$11219 - attribute \src "libresoc.v:170294.3-170333.6" - wire width 4 $2\src13__data_o$next[3:0]$11210 - attribute \src "libresoc.v:170391.3-170430.6" - wire width 4 $2\src23__data_o$next[3:0]$11225 - attribute \src "libresoc.v:170461.3-170500.6" - wire width 4 $2\src33__data_o$next[3:0]$11239 - attribute \src "libresoc.v:170571.3-170600.6" - wire $2\wr_detect$10[0:0]$11261 - attribute \src "libresoc.v:170641.3-170670.6" - wire $2\wr_detect$13[0:0]$11275 - attribute \src "libresoc.v:170431.3-170460.6" - wire $2\wr_detect$4[0:0]$11233 - attribute \src "libresoc.v:170501.3-170530.6" - wire $2\wr_detect$7[0:0]$11247 - attribute \src "libresoc.v:170334.3-170363.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:170601.3-170640.6" - wire width 4 $3\r23__data_o$next[3:0]$11268 - attribute \src "libresoc.v:170531.3-170570.6" - wire width 4 $3\r3__data_o$next[3:0]$11254 - attribute \src "libresoc.v:170364.3-170390.6" - wire width 4 $3\reg$next[3:0]$11220 - attribute \src "libresoc.v:170294.3-170333.6" - wire width 4 $3\src13__data_o$next[3:0]$11211 - attribute \src "libresoc.v:170391.3-170430.6" - wire width 4 $3\src23__data_o$next[3:0]$11226 - attribute \src "libresoc.v:170461.3-170500.6" - wire width 4 $3\src33__data_o$next[3:0]$11240 - attribute \src "libresoc.v:170571.3-170600.6" - wire $3\wr_detect$10[0:0]$11262 - attribute \src "libresoc.v:170641.3-170670.6" - wire $3\wr_detect$13[0:0]$11276 - attribute \src "libresoc.v:170431.3-170460.6" - wire $3\wr_detect$4[0:0]$11234 - attribute \src "libresoc.v:170501.3-170530.6" - wire $3\wr_detect$7[0:0]$11248 - attribute \src "libresoc.v:170334.3-170363.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:170601.3-170640.6" - wire width 4 $4\r23__data_o$next[3:0]$11269 - attribute \src "libresoc.v:170531.3-170570.6" - wire width 4 $4\r3__data_o$next[3:0]$11255 - attribute \src "libresoc.v:170364.3-170390.6" - wire width 4 $4\reg$next[3:0]$11221 - attribute \src "libresoc.v:170294.3-170333.6" - wire width 4 $4\src13__data_o$next[3:0]$11212 - attribute \src "libresoc.v:170391.3-170430.6" - wire width 4 $4\src23__data_o$next[3:0]$11227 - attribute \src "libresoc.v:170461.3-170500.6" - wire width 4 $4\src33__data_o$next[3:0]$11241 - attribute \src "libresoc.v:170571.3-170600.6" - wire $4\wr_detect$10[0:0]$11263 - attribute \src "libresoc.v:170641.3-170670.6" - wire $4\wr_detect$13[0:0]$11277 - attribute \src "libresoc.v:170431.3-170460.6" - wire $4\wr_detect$4[0:0]$11235 - attribute \src "libresoc.v:170501.3-170530.6" - wire $4\wr_detect$7[0:0]$11249 - attribute \src "libresoc.v:170334.3-170363.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:170601.3-170640.6" - wire width 4 $5\r23__data_o$next[3:0]$11270 - attribute \src "libresoc.v:170531.3-170570.6" - wire width 4 $5\r3__data_o$next[3:0]$11256 - attribute \src "libresoc.v:170294.3-170333.6" - wire width 4 $5\src13__data_o$next[3:0]$11213 - attribute \src "libresoc.v:170391.3-170430.6" - wire width 4 $5\src23__data_o$next[3:0]$11228 - attribute \src "libresoc.v:170461.3-170500.6" - wire width 4 $5\src33__data_o$next[3:0]$11242 - attribute \src "libresoc.v:170601.3-170640.6" - wire width 4 $6\r23__data_o$next[3:0]$11271 - attribute \src "libresoc.v:170531.3-170570.6" - wire width 4 $6\r3__data_o$next[3:0]$11257 - attribute \src "libresoc.v:170294.3-170333.6" - wire width 4 $6\src13__data_o$next[3:0]$11214 - attribute \src "libresoc.v:170391.3-170430.6" - wire width 4 $6\src23__data_o$next[3:0]$11229 - attribute \src "libresoc.v:170461.3-170500.6" - wire width 4 $6\src33__data_o$next[3:0]$11243 - attribute \src "libresoc.v:170277.17-170277.104" - wire $not$libresoc.v:170277$11196_Y - attribute \src "libresoc.v:170278.18-170278.105" - wire $not$libresoc.v:170278$11197_Y - attribute \src "libresoc.v:170279.17-170279.100" - wire $not$libresoc.v:170279$11198_Y - attribute \src "libresoc.v:170280.17-170280.103" - wire $not$libresoc.v:170280$11199_Y - attribute \src "libresoc.v:170281.17-170281.103" - wire $not$libresoc.v:170281$11200_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest23__wen - attribute \src "libresoc.v:170201.7-170201.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r3__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src13__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src33__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170277$11196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:170277$11196_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170278$11197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:170278$11197_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170279$11198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:170279$11198_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170280$11199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:170280$11199_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170281$11200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:170281$11200_Y - end - attribute \src "libresoc.v:170201.7-170201.20" - process $proc$libresoc.v:170201$11278 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:170226.13-170226.31" - process $proc$libresoc.v:170226$11279 - assign { } { } - assign $1\r23__data_o[3:0] 4'0000 - sync always - sync init - update \r23__data_o $1\r23__data_o[3:0] - end - attribute \src "libresoc.v:170233.13-170233.30" - process $proc$libresoc.v:170233$11280 - assign { } { } - assign $1\r3__data_o[3:0] 4'0000 - sync always - sync init - update \r3__data_o $1\r3__data_o[3:0] - end - attribute \src "libresoc.v:170239.13-170239.25" - process $proc$libresoc.v:170239$11281 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "libresoc.v:170244.13-170244.33" - process $proc$libresoc.v:170244$11282 - assign { } { } - assign $1\src13__data_o[3:0] 4'0000 - sync always - sync init - update \src13__data_o $1\src13__data_o[3:0] - end - attribute \src "libresoc.v:170251.13-170251.33" - process $proc$libresoc.v:170251$11283 - assign { } { } - assign $1\src23__data_o[3:0] 4'0000 - sync always - sync init - update \src23__data_o $1\src23__data_o[3:0] - end - attribute \src "libresoc.v:170258.13-170258.33" - process $proc$libresoc.v:170258$11284 - assign { } { } - assign $1\src33__data_o[3:0] 4'0000 - sync always - sync init - update \src33__data_o $1\src33__data_o[3:0] - end - attribute \src "libresoc.v:170282.3-170283.25" - process $proc$libresoc.v:170282$11201 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:170284.3-170285.39" - process $proc$libresoc.v:170284$11202 - assign { } { } - assign $0\r23__data_o[3:0] \r23__data_o$next - sync posedge \coresync_clk - update \r23__data_o $0\r23__data_o[3:0] - end - attribute \src "libresoc.v:170286.3-170287.37" - process $proc$libresoc.v:170286$11203 - assign { } { } - assign $0\r3__data_o[3:0] \r3__data_o$next - sync posedge \coresync_clk - update \r3__data_o $0\r3__data_o[3:0] - end - attribute \src "libresoc.v:170288.3-170289.43" - process $proc$libresoc.v:170288$11204 - assign { } { } - assign $0\src33__data_o[3:0] \src33__data_o$next - sync posedge \coresync_clk - update \src33__data_o $0\src33__data_o[3:0] - end - attribute \src "libresoc.v:170290.3-170291.43" - process $proc$libresoc.v:170290$11205 - assign { } { } - assign $0\src23__data_o[3:0] \src23__data_o$next - sync posedge \coresync_clk - update \src23__data_o $0\src23__data_o[3:0] - end - attribute \src "libresoc.v:170292.3-170293.43" - process $proc$libresoc.v:170292$11206 - assign { } { } - assign $0\src13__data_o[3:0] \src13__data_o$next - sync posedge \coresync_clk - update \src13__data_o $0\src13__data_o[3:0] + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:170294.3-170333.6" - process $proc$libresoc.v:170294$11207 + attribute \src "libresoc.v:31462.3-31510.6" + process $proc$libresoc.v:31462$676 assign { } { } assign { } { } - assign { } { } - assign $0\src13__data_o$next[3:0]$11208 $6\src13__data_o$next[3:0]$11214 - attribute \src "libresoc.v:170295.5-170295.29" + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:31463.5-31463.29" switch \initial - attribute \src "libresoc.v:170295.9-170295.17" + attribute \src "libresoc.v:31463.9-31463.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\src13__data_o$next[3:0]$11209 $5\src13__data_o$next[3:0]$11213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src13__data_o$next[3:0]$11210 \dest13__data_i - case - assign $2\src13__data_o$next[3:0]$11210 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src13__data_o$next[3:0]$11211 \dest23__data_i - case - assign $3\src13__data_o$next[3:0]$11211 $2\src13__data_o$next[3:0]$11210 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src13__data_o$next[3:0]$11212 \w3__data_i - case - assign $4\src13__data_o$next[3:0]$11212 $3\src13__data_o$next[3:0]$11211 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src13__data_o$next[3:0]$11213 \reg - case - assign $5\src13__data_o$next[3:0]$11213 $4\src13__data_o$next[3:0]$11212 - end - case - assign $1\src13__data_o$next[3:0]$11209 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $6\src13__data_o$next[3:0]$11214 4'0000 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 case - assign $6\src13__data_o$next[3:0]$11214 $1\src13__data_o$next[3:0]$11209 + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11208 + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:170334.3-170363.6" - process $proc$libresoc.v:170334$11215 + attribute \src "libresoc.v:31511.3-31559.6" + process $proc$libresoc.v:31511$677 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:170335.5-170335.29" + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:31512.5-31512.29" switch \initial - attribute \src "libresoc.v:170335.9-170335.17" + attribute \src "libresoc.v:31512.9-31512.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src13__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:170364.3-170390.6" - process $proc$libresoc.v:170364$11216 - assign { } { } - assign { } { } + attribute \src "libresoc.v:31560.3-31608.6" + process $proc$libresoc.v:31560$678 assign { } { } assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11217 $4\reg$next[3:0]$11221 - attribute \src "libresoc.v:170365.5-170365.29" + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:31561.5-31561.29" switch \initial - attribute \src "libresoc.v:170365.9-170365.17" + attribute \src "libresoc.v:31561.9-31561.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest13__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } - assign $1\reg$next[3:0]$11218 \dest13__data_i - case - assign $1\reg$next[3:0]$11218 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest23__wen + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $2\reg$next[3:0]$11219 \dest23__data_i - case - assign $2\reg$next[3:0]$11219 $1\reg$next[3:0]$11218 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w3__wen + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $3\reg$next[3:0]$11220 \w3__data_i - case - assign $3\reg$next[3:0]$11220 $2\reg$next[3:0]$11219 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $4\reg$next[3:0]$11221 4'0000 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 case - assign $4\reg$next[3:0]$11221 $3\reg$next[3:0]$11220 + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 end sync always - update \reg$next $0\reg$next[3:0]$11217 + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] end - attribute \src "libresoc.v:170391.3-170430.6" - process $proc$libresoc.v:170391$11222 + attribute \src "libresoc.v:31609.3-31657.6" + process $proc$libresoc.v:31609$679 assign { } { } assign { } { } - assign { } { } - assign $0\src23__data_o$next[3:0]$11223 $6\src23__data_o$next[3:0]$11229 - attribute \src "libresoc.v:170392.5-170392.29" + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:31610.5-31610.29" switch \initial - attribute \src "libresoc.v:170392.9-170392.17" + attribute \src "libresoc.v:31610.9-31610.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\src23__data_o$next[3:0]$11224 $5\src23__data_o$next[3:0]$11228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src23__data_o$next[3:0]$11225 \dest13__data_i - case - assign $2\src23__data_o$next[3:0]$11225 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src23__data_o$next[3:0]$11226 \dest23__data_i - case - assign $3\src23__data_o$next[3:0]$11226 $2\src23__data_o$next[3:0]$11225 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src23__data_o$next[3:0]$11227 \w3__data_i - case - assign $4\src23__data_o$next[3:0]$11227 $3\src23__data_o$next[3:0]$11226 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src23__data_o$next[3:0]$11228 \reg - case - assign $5\src23__data_o$next[3:0]$11228 $4\src23__data_o$next[3:0]$11227 - end - case - assign $1\src23__data_o$next[3:0]$11224 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 assign { } { } - assign $6\src23__data_o$next[3:0]$11229 4'0000 - case - assign $6\src23__data_o$next[3:0]$11229 $1\src23__data_o$next[3:0]$11224 - end - sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11223 - end - attribute \src "libresoc.v:170431.3-170460.6" - process $proc$libresoc.v:170431$11230 - assign { } { } - assign { } { } - assign $0\wr_detect$4[0:0]$11231 $1\wr_detect$4[0:0]$11232 - attribute \src "libresoc.v:170432.5-170432.29" - switch \initial - attribute \src "libresoc.v:170432.9-170432.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src23__ren + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\wr_detect$4[0:0]$11232 $4\wr_detect$4[0:0]$11235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11233 1'1 - case - assign $2\wr_detect$4[0:0]$11233 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11234 1'1 - case - assign $3\wr_detect$4[0:0]$11234 $2\wr_detect$4[0:0]$11233 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11235 1'1 - case - assign $4\wr_detect$4[0:0]$11235 $3\wr_detect$4[0:0]$11234 - end + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 case - assign $1\wr_detect$4[0:0]$11232 1'0 + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11231 + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:170461.3-170500.6" - process $proc$libresoc.v:170461$11236 - assign { } { } + attribute \src "libresoc.v:31658.3-31706.6" + process $proc$libresoc.v:31658$680 assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11237 $6\src33__data_o$next[3:0]$11243 - attribute \src "libresoc.v:170462.5-170462.29" + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:31659.5-31659.29" switch \initial - attribute \src "libresoc.v:170462.9-170462.17" + attribute \src "libresoc.v:31659.9-31659.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 assign { } { } - assign $1\src33__data_o$next[3:0]$11238 $5\src33__data_o$next[3:0]$11242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src33__data_o$next[3:0]$11239 \dest13__data_i - case - assign $2\src33__data_o$next[3:0]$11239 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src33__data_o$next[3:0]$11240 \dest23__data_i - case - assign $3\src33__data_o$next[3:0]$11240 $2\src33__data_o$next[3:0]$11239 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src33__data_o$next[3:0]$11241 \w3__data_i - case - assign $4\src33__data_o$next[3:0]$11241 $3\src33__data_o$next[3:0]$11240 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src33__data_o$next[3:0]$11242 \reg - case - assign $5\src33__data_o$next[3:0]$11242 $4\src33__data_o$next[3:0]$11241 - end - case - assign $1\src33__data_o$next[3:0]$11238 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign $6\src33__data_o$next[3:0]$11243 4'0000 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 case - assign $6\src33__data_o$next[3:0]$11243 $1\src33__data_o$next[3:0]$11238 + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11237 + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:31712.1-32427.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:32065.3-32083.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32141.3-32159.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32388.3-32406.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32407.3-32425.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32046.3-32064.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32122.3-32140.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32293.3-32311.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:31970.3-31988.6" + wire width 12 $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32312.3-32330.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32331.3-32349.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32350.3-32368.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32179.3-32197.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32084.3-32102.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32103.3-32121.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32217.3-32235.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:31989.3-32007.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32255.3-32273.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32369.3-32387.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32027.3-32045.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32198.3-32216.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32274.3-32292.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32236.3-32254.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32160.3-32178.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32008.3-32026.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:31713.7-31713.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:32065.3-32083.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32141.3-32159.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32388.3-32406.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32407.3-32425.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32046.3-32064.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32122.3-32140.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32293.3-32311.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:31970.3-31988.6" + wire width 12 $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:32312.3-32330.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32331.3-32349.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32350.3-32368.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32179.3-32197.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32084.3-32102.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32103.3-32121.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32217.3-32235.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:31989.3-32007.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:32255.3-32273.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32369.3-32387.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32027.3-32045.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32198.3-32216.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32274.3-32292.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32236.3-32254.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32160.3-32178.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32008.3-32026.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub24_upd + attribute \src "libresoc.v:31713.7-31713.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:31713.7-31713.20" + process $proc$libresoc.v:31713$706 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:170501.3-170530.6" - process $proc$libresoc.v:170501$11244 + attribute \src "libresoc.v:31970.3-31988.6" + process $proc$libresoc.v:31970$682 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11245 $1\wr_detect$7[0:0]$11246 - attribute \src "libresoc.v:170502.5-170502.29" + assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "libresoc.v:31971.5-31971.29" switch \initial - attribute \src "libresoc.v:170502.9-170502.17" + attribute \src "libresoc.v:31971.9-31971.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src33__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$7[0:0]$11246 $4\wr_detect$7[0:0]$11249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$11247 1'1 - case - assign $2\wr_detect$7[0:0]$11247 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$11248 1'1 - case - assign $3\wr_detect$7[0:0]$11248 $2\wr_detect$7[0:0]$11247 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$11249 1'1 - case - assign $4\wr_detect$7[0:0]$11249 $3\wr_detect$7[0:0]$11248 - end + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 case - assign $1\wr_detect$7[0:0]$11246 1'0 + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11245 + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] end - attribute \src "libresoc.v:170531.3-170570.6" - process $proc$libresoc.v:170531$11250 + attribute \src "libresoc.v:31989.3-32007.6" + process $proc$libresoc.v:31989$683 assign { } { } assign { } { } - assign { } { } - assign $0\r3__data_o$next[3:0]$11251 $6\r3__data_o$next[3:0]$11257 - attribute \src "libresoc.v:170532.5-170532.29" + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:31990.5-31990.29" switch \initial - attribute \src "libresoc.v:170532.9-170532.17" + attribute \src "libresoc.v:31990.9-31990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\r3__data_o$next[3:0]$11252 $5\r3__data_o$next[3:0]$11256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r3__data_o$next[3:0]$11253 \dest13__data_i - case - assign $2\r3__data_o$next[3:0]$11253 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r3__data_o$next[3:0]$11254 \dest23__data_i - case - assign $3\r3__data_o$next[3:0]$11254 $2\r3__data_o$next[3:0]$11253 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r3__data_o$next[3:0]$11255 \w3__data_i - case - assign $4\r3__data_o$next[3:0]$11255 $3\r3__data_o$next[3:0]$11254 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r3__data_o$next[3:0]$11256 \reg - case - assign $5\r3__data_o$next[3:0]$11256 $4\r3__data_o$next[3:0]$11255 - end - case - assign $1\r3__data_o$next[3:0]$11252 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\r3__data_o$next[3:0]$11257 4'0000 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 case - assign $6\r3__data_o$next[3:0]$11257 $1\r3__data_o$next[3:0]$11252 + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11251 + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:170571.3-170600.6" - process $proc$libresoc.v:170571$11258 + attribute \src "libresoc.v:32008.3-32026.6" + process $proc$libresoc.v:32008$684 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11259 $1\wr_detect$10[0:0]$11260 - attribute \src "libresoc.v:170572.5-170572.29" + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:32009.5-32009.29" switch \initial - attribute \src "libresoc.v:170572.9-170572.17" + attribute \src "libresoc.v:32009.9-32009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$10[0:0]$11260 $4\wr_detect$10[0:0]$11263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11261 1'1 - case - assign $2\wr_detect$10[0:0]$11261 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11262 1'1 - case - assign $3\wr_detect$10[0:0]$11262 $2\wr_detect$10[0:0]$11261 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11263 1'1 - case - assign $4\wr_detect$10[0:0]$11263 $3\wr_detect$10[0:0]$11262 - end + assign $1\dec31_dec_sub24_upd[1:0] 2'00 case - assign $1\wr_detect$10[0:0]$11260 1'0 + assign $1\dec31_dec_sub24_upd[1:0] 2'00 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11259 + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:170601.3-170640.6" - process $proc$libresoc.v:170601$11264 + attribute \src "libresoc.v:32027.3-32045.6" + process $proc$libresoc.v:32027$685 assign { } { } assign { } { } - assign { } { } - assign $0\r23__data_o$next[3:0]$11265 $6\r23__data_o$next[3:0]$11271 - attribute \src "libresoc.v:170602.5-170602.29" + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:32028.5-32028.29" switch \initial - attribute \src "libresoc.v:170602.9-170602.17" + attribute \src "libresoc.v:32028.9-32028.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\r23__data_o$next[3:0]$11266 $5\r23__data_o$next[3:0]$11270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r23__data_o$next[3:0]$11267 \dest13__data_i - case - assign $2\r23__data_o$next[3:0]$11267 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r23__data_o$next[3:0]$11268 \dest23__data_i - case - assign $3\r23__data_o$next[3:0]$11268 $2\r23__data_o$next[3:0]$11267 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r23__data_o$next[3:0]$11269 \w3__data_i - case - assign $4\r23__data_o$next[3:0]$11269 $3\r23__data_o$next[3:0]$11268 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r23__data_o$next[3:0]$11270 \reg - case - assign $5\r23__data_o$next[3:0]$11270 $4\r23__data_o$next[3:0]$11269 - end - case - assign $1\r23__data_o$next[3:0]$11266 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\r23__data_o$next[3:0]$11271 4'0000 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 case - assign $6\r23__data_o$next[3:0]$11271 $1\r23__data_o$next[3:0]$11266 + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11265 + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:170641.3-170670.6" - process $proc$libresoc.v:170641$11272 + attribute \src "libresoc.v:32046.3-32064.6" + process $proc$libresoc.v:32046$686 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11273 $1\wr_detect$13[0:0]$11274 - attribute \src "libresoc.v:170642.5-170642.29" + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:32047.5-32047.29" switch \initial - attribute \src "libresoc.v:170642.9-170642.17" + attribute \src "libresoc.v:32047.9-32047.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r23__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$13[0:0]$11274 $4\wr_detect$13[0:0]$11277 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$11275 1'1 - case - assign $2\wr_detect$13[0:0]$11275 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest23__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$11276 1'1 - case - assign $3\wr_detect$13[0:0]$11276 $2\wr_detect$13[0:0]$11275 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$11277 1'1 - case - assign $4\wr_detect$13[0:0]$11277 $3\wr_detect$13[0:0]$11276 - end + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 case - assign $1\wr_detect$13[0:0]$11274 1'0 + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11273 - end - connect \$9 $not$libresoc.v:170277$11196_Y - connect \$12 $not$libresoc.v:170278$11197_Y - connect \$1 $not$libresoc.v:170279$11198_Y - connect \$3 $not$libresoc.v:170280$11199_Y - connect \$6 $not$libresoc.v:170281$11200_Y -end -attribute \src "libresoc.v:170675.1-170894.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_3" -attribute \generator "nMigen" -module \reg_3$138 - attribute \src "libresoc.v:170727.3-170766.6" - wire width 64 $0\cia3__data_o$next[63:0]$11291 - attribute \src "libresoc.v:170725.3-170726.41" - wire width 64 $0\cia3__data_o[63:0] - attribute \src "libresoc.v:170676.7-170676.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:170797.3-170836.6" - wire width 64 $0\msr3__data_o$next[63:0]$11300 - attribute \src "libresoc.v:170723.3-170724.41" - wire width 64 $0\msr3__data_o[63:0] - attribute \src "libresoc.v:170867.3-170893.6" - wire width 64 $0\reg$next[63:0]$11314 - attribute \src "libresoc.v:170721.3-170722.25" - wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:170837.3-170866.6" - wire $0\wr_detect$4[0:0]$11308 - attribute \src "libresoc.v:170767.3-170796.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:170727.3-170766.6" - wire width 64 $1\cia3__data_o$next[63:0]$11292 - attribute \src "libresoc.v:170683.14-170683.49" - wire width 64 $1\cia3__data_o[63:0] - attribute \src "libresoc.v:170797.3-170836.6" - wire width 64 $1\msr3__data_o$next[63:0]$11301 - attribute \src "libresoc.v:170700.14-170700.49" - wire width 64 $1\msr3__data_o[63:0] - attribute \src "libresoc.v:170867.3-170893.6" - wire width 64 $1\reg$next[63:0]$11315 - attribute \src "libresoc.v:170712.14-170712.42" - wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:170837.3-170866.6" - wire $1\wr_detect$4[0:0]$11309 - attribute \src "libresoc.v:170767.3-170796.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:170727.3-170766.6" - wire width 64 $2\cia3__data_o$next[63:0]$11293 - attribute \src "libresoc.v:170797.3-170836.6" - wire width 64 $2\msr3__data_o$next[63:0]$11302 - attribute \src "libresoc.v:170867.3-170893.6" - wire width 64 $2\reg$next[63:0]$11316 - attribute \src "libresoc.v:170837.3-170866.6" - wire $2\wr_detect$4[0:0]$11310 - attribute \src "libresoc.v:170767.3-170796.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:170727.3-170766.6" - wire width 64 $3\cia3__data_o$next[63:0]$11294 - attribute \src "libresoc.v:170797.3-170836.6" - wire width 64 $3\msr3__data_o$next[63:0]$11303 - attribute \src "libresoc.v:170867.3-170893.6" - wire width 64 $3\reg$next[63:0]$11317 - attribute \src "libresoc.v:170837.3-170866.6" - wire $3\wr_detect$4[0:0]$11311 - attribute \src "libresoc.v:170767.3-170796.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:170727.3-170766.6" - wire width 64 $4\cia3__data_o$next[63:0]$11295 - attribute \src "libresoc.v:170797.3-170836.6" - wire width 64 $4\msr3__data_o$next[63:0]$11304 - attribute \src "libresoc.v:170867.3-170893.6" - wire width 64 $4\reg$next[63:0]$11318 - attribute \src "libresoc.v:170837.3-170866.6" - wire $4\wr_detect$4[0:0]$11312 - attribute \src "libresoc.v:170767.3-170796.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:170727.3-170766.6" - wire width 64 $5\cia3__data_o$next[63:0]$11296 - attribute \src "libresoc.v:170797.3-170836.6" - wire width 64 $5\msr3__data_o$next[63:0]$11305 - attribute \src "libresoc.v:170727.3-170766.6" - wire width 64 $6\cia3__data_o$next[63:0]$11297 - attribute \src "libresoc.v:170797.3-170836.6" - wire width 64 $6\msr3__data_o$next[63:0]$11306 - attribute \src "libresoc.v:170719.17-170719.100" - wire $not$libresoc.v:170719$11285_Y - attribute \src "libresoc.v:170720.17-170720.103" - wire $not$libresoc.v:170720$11286_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \cia3__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \d_wr13__wen - attribute \src "libresoc.v:170676.7-170676.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \nia3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170719$11285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:170719$11285_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170720$11286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:170720$11286_Y - end - attribute \src "libresoc.v:170676.7-170676.20" - process $proc$libresoc.v:170676$11319 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:170683.14-170683.49" - process $proc$libresoc.v:170683$11320 - assign { } { } - assign $1\cia3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \cia3__data_o $1\cia3__data_o[63:0] - end - attribute \src "libresoc.v:170700.14-170700.49" - process $proc$libresoc.v:170700$11321 - assign { } { } - assign $1\msr3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \msr3__data_o $1\msr3__data_o[63:0] - end - attribute \src "libresoc.v:170712.14-170712.42" - process $proc$libresoc.v:170712$11322 - assign { } { } - assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \reg $1\reg[63:0] - end - attribute \src "libresoc.v:170721.3-170722.25" - process $proc$libresoc.v:170721$11287 - assign { } { } - assign $0\reg[63:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[63:0] - end - attribute \src "libresoc.v:170723.3-170724.41" - process $proc$libresoc.v:170723$11288 - assign { } { } - assign $0\msr3__data_o[63:0] \msr3__data_o$next - sync posedge \coresync_clk - update \msr3__data_o $0\msr3__data_o[63:0] - end - attribute \src "libresoc.v:170725.3-170726.41" - process $proc$libresoc.v:170725$11289 - assign { } { } - assign $0\cia3__data_o[63:0] \cia3__data_o$next - sync posedge \coresync_clk - update \cia3__data_o $0\cia3__data_o[63:0] + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:170727.3-170766.6" - process $proc$libresoc.v:170727$11290 + attribute \src "libresoc.v:32065.3-32083.6" + process $proc$libresoc.v:32065$687 assign { } { } assign { } { } - assign { } { } - assign $0\cia3__data_o$next[63:0]$11291 $6\cia3__data_o$next[63:0]$11297 - attribute \src "libresoc.v:170728.5-170728.29" + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:32066.5-32066.29" switch \initial - attribute \src "libresoc.v:170728.9-170728.17" + attribute \src "libresoc.v:32066.9-32066.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\cia3__data_o$next[63:0]$11292 $5\cia3__data_o$next[63:0]$11296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\cia3__data_o$next[63:0]$11293 \nia3__data_i - case - assign $2\cia3__data_o$next[63:0]$11293 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\cia3__data_o$next[63:0]$11294 \msr3__data_i - case - assign $3\cia3__data_o$next[63:0]$11294 $2\cia3__data_o$next[63:0]$11293 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\cia3__data_o$next[63:0]$11295 \d_wr13__data_i - case - assign $4\cia3__data_o$next[63:0]$11295 $3\cia3__data_o$next[63:0]$11294 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\cia3__data_o$next[63:0]$11296 \reg - case - assign $5\cia3__data_o$next[63:0]$11296 $4\cia3__data_o$next[63:0]$11295 - end - case - assign $1\cia3__data_o$next[63:0]$11292 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\cia3__data_o$next[63:0]$11297 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 case - assign $6\cia3__data_o$next[63:0]$11297 $1\cia3__data_o$next[63:0]$11292 + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 end sync always - update \cia3__data_o$next $0\cia3__data_o$next[63:0]$11291 + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:170767.3-170796.6" - process $proc$libresoc.v:170767$11298 + attribute \src "libresoc.v:32084.3-32102.6" + process $proc$libresoc.v:32084$688 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:170768.5-170768.29" + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:32085.5-32085.29" switch \initial - attribute \src "libresoc.v:170768.9-170768.17" + attribute \src "libresoc.v:32085.9-32085.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \cia3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:170797.3-170836.6" - process $proc$libresoc.v:170797$11299 + attribute \src "libresoc.v:32103.3-32121.6" + process $proc$libresoc.v:32103$689 assign { } { } assign { } { } - assign { } { } - assign $0\msr3__data_o$next[63:0]$11300 $6\msr3__data_o$next[63:0]$11306 - attribute \src "libresoc.v:170798.5-170798.29" + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:32104.5-32104.29" switch \initial - attribute \src "libresoc.v:170798.9-170798.17" + attribute \src "libresoc.v:32104.9-32104.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\msr3__data_o$next[63:0]$11301 $5\msr3__data_o$next[63:0]$11305 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr3__data_o$next[63:0]$11302 \nia3__data_i - case - assign $2\msr3__data_o$next[63:0]$11302 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr3__data_o$next[63:0]$11303 \msr3__data_i - case - assign $3\msr3__data_o$next[63:0]$11303 $2\msr3__data_o$next[63:0]$11302 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\msr3__data_o$next[63:0]$11304 \d_wr13__data_i - case - assign $4\msr3__data_o$next[63:0]$11304 $3\msr3__data_o$next[63:0]$11303 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\msr3__data_o$next[63:0]$11305 \reg - case - assign $5\msr3__data_o$next[63:0]$11305 $4\msr3__data_o$next[63:0]$11304 - end - case - assign $1\msr3__data_o$next[63:0]$11301 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\msr3__data_o$next[63:0]$11306 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 case - assign $6\msr3__data_o$next[63:0]$11306 $1\msr3__data_o$next[63:0]$11301 + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 end sync always - update \msr3__data_o$next $0\msr3__data_o$next[63:0]$11300 + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:170837.3-170866.6" - process $proc$libresoc.v:170837$11307 + attribute \src "libresoc.v:32122.3-32140.6" + process $proc$libresoc.v:32122$690 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11308 $1\wr_detect$4[0:0]$11309 - attribute \src "libresoc.v:170838.5-170838.29" + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:32123.5-32123.29" switch \initial - attribute \src "libresoc.v:170838.9-170838.17" + attribute \src "libresoc.v:32123.9-32123.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \msr3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$4[0:0]$11309 $4\wr_detect$4[0:0]$11312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \nia3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11310 1'1 - case - assign $2\wr_detect$4[0:0]$11310 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \msr3__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11311 1'1 - case - assign $3\wr_detect$4[0:0]$11311 $2\wr_detect$4[0:0]$11310 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \d_wr13__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11312 1'1 - case - assign $4\wr_detect$4[0:0]$11312 $3\wr_detect$4[0:0]$11311 - end + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 case - assign $1\wr_detect$4[0:0]$11309 1'0 + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11308 + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:170867.3-170893.6" - process $proc$libresoc.v:170867$11313 + attribute \src "libresoc.v:32141.3-32159.6" + process $proc$libresoc.v:32141$691 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[63:0]$11314 $4\reg$next[63:0]$11318 - attribute \src "libresoc.v:170868.5-170868.29" + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:32142.5-32142.29" switch \initial - attribute \src "libresoc.v:170868.9-170868.17" + attribute \src "libresoc.v:32142.9-32142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \nia3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $1\reg$next[63:0]$11315 \nia3__data_i - case - assign $1\reg$next[63:0]$11315 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \msr3__wen + assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11000 assign { } { } - assign $2\reg$next[63:0]$11316 \msr3__data_i - case - assign $2\reg$next[63:0]$11316 $1\reg$next[63:0]$11315 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \d_wr13__wen + assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $3\reg$next[63:0]$11317 \d_wr13__data_i - case - assign $3\reg$next[63:0]$11317 $2\reg$next[63:0]$11316 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $4\reg$next[63:0]$11318 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub24_br[0:0] 1'0 case - assign $4\reg$next[63:0]$11318 $3\reg$next[63:0]$11317 + assign $1\dec31_dec_sub24_br[0:0] 1'0 end sync always - update \reg$next $0\reg$next[63:0]$11314 - end - connect \$1 $not$libresoc.v:170719$11285_Y - connect \$3 $not$libresoc.v:170720$11286_Y -end -attribute \src "libresoc.v:170898.1-171369.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" -attribute \generator "nMigen" -module \reg_4 - attribute \src "libresoc.v:170899.7-170899.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:171299.3-171338.6" - wire width 4 $0\r24__data_o$next[3:0]$11392 - attribute \src "libresoc.v:170982.3-170983.39" - wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:171229.3-171268.6" - wire width 4 $0\r4__data_o$next[3:0]$11378 - attribute \src "libresoc.v:170984.3-170985.37" - wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:171062.3-171088.6" - wire width 4 $0\reg$next[3:0]$11344 - attribute \src "libresoc.v:170980.3-170981.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:170992.3-171031.6" - wire width 4 $0\src14__data_o$next[3:0]$11335 - attribute \src "libresoc.v:170990.3-170991.43" - wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:171089.3-171128.6" - wire width 4 $0\src24__data_o$next[3:0]$11350 - attribute \src "libresoc.v:170988.3-170989.43" - wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:171159.3-171198.6" - wire width 4 $0\src34__data_o$next[3:0]$11364 - attribute \src "libresoc.v:170986.3-170987.43" - wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:171269.3-171298.6" - wire $0\wr_detect$10[0:0]$11386 - attribute \src "libresoc.v:171339.3-171368.6" - wire $0\wr_detect$13[0:0]$11400 - attribute \src "libresoc.v:171129.3-171158.6" - wire $0\wr_detect$4[0:0]$11358 - attribute \src "libresoc.v:171199.3-171228.6" - wire $0\wr_detect$7[0:0]$11372 - attribute \src "libresoc.v:171032.3-171061.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:171299.3-171338.6" - wire width 4 $1\r24__data_o$next[3:0]$11393 - attribute \src "libresoc.v:170924.13-170924.31" - wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:171229.3-171268.6" - wire width 4 $1\r4__data_o$next[3:0]$11379 - attribute \src "libresoc.v:170931.13-170931.30" - wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:171062.3-171088.6" - wire width 4 $1\reg$next[3:0]$11345 - attribute \src "libresoc.v:170937.13-170937.25" - wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:170992.3-171031.6" - wire width 4 $1\src14__data_o$next[3:0]$11336 - attribute \src "libresoc.v:170942.13-170942.33" - wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:171089.3-171128.6" - wire width 4 $1\src24__data_o$next[3:0]$11351 - attribute \src "libresoc.v:170949.13-170949.33" - wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:171159.3-171198.6" - wire width 4 $1\src34__data_o$next[3:0]$11365 - attribute \src "libresoc.v:170956.13-170956.33" - wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:171269.3-171298.6" - wire $1\wr_detect$10[0:0]$11387 - attribute \src "libresoc.v:171339.3-171368.6" - wire $1\wr_detect$13[0:0]$11401 - attribute \src "libresoc.v:171129.3-171158.6" - wire $1\wr_detect$4[0:0]$11359 - attribute \src "libresoc.v:171199.3-171228.6" - wire $1\wr_detect$7[0:0]$11373 - attribute \src "libresoc.v:171032.3-171061.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:171299.3-171338.6" - wire width 4 $2\r24__data_o$next[3:0]$11394 - attribute \src "libresoc.v:171229.3-171268.6" - wire width 4 $2\r4__data_o$next[3:0]$11380 - attribute \src "libresoc.v:171062.3-171088.6" - wire width 4 $2\reg$next[3:0]$11346 - attribute \src "libresoc.v:170992.3-171031.6" - wire width 4 $2\src14__data_o$next[3:0]$11337 - attribute \src "libresoc.v:171089.3-171128.6" - wire width 4 $2\src24__data_o$next[3:0]$11352 - attribute \src "libresoc.v:171159.3-171198.6" - wire width 4 $2\src34__data_o$next[3:0]$11366 - attribute \src "libresoc.v:171269.3-171298.6" - wire $2\wr_detect$10[0:0]$11388 - attribute \src "libresoc.v:171339.3-171368.6" - wire $2\wr_detect$13[0:0]$11402 - attribute \src "libresoc.v:171129.3-171158.6" - wire $2\wr_detect$4[0:0]$11360 - attribute \src "libresoc.v:171199.3-171228.6" - wire $2\wr_detect$7[0:0]$11374 - attribute \src "libresoc.v:171032.3-171061.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:171299.3-171338.6" - wire width 4 $3\r24__data_o$next[3:0]$11395 - attribute \src "libresoc.v:171229.3-171268.6" - wire width 4 $3\r4__data_o$next[3:0]$11381 - attribute \src "libresoc.v:171062.3-171088.6" - wire width 4 $3\reg$next[3:0]$11347 - attribute \src "libresoc.v:170992.3-171031.6" - wire width 4 $3\src14__data_o$next[3:0]$11338 - attribute \src "libresoc.v:171089.3-171128.6" - wire width 4 $3\src24__data_o$next[3:0]$11353 - attribute \src "libresoc.v:171159.3-171198.6" - wire width 4 $3\src34__data_o$next[3:0]$11367 - attribute \src "libresoc.v:171269.3-171298.6" - wire $3\wr_detect$10[0:0]$11389 - attribute \src "libresoc.v:171339.3-171368.6" - wire $3\wr_detect$13[0:0]$11403 - attribute \src "libresoc.v:171129.3-171158.6" - wire $3\wr_detect$4[0:0]$11361 - attribute \src "libresoc.v:171199.3-171228.6" - wire $3\wr_detect$7[0:0]$11375 - attribute \src "libresoc.v:171032.3-171061.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:171299.3-171338.6" - wire width 4 $4\r24__data_o$next[3:0]$11396 - attribute \src "libresoc.v:171229.3-171268.6" - wire width 4 $4\r4__data_o$next[3:0]$11382 - attribute \src "libresoc.v:171062.3-171088.6" - wire width 4 $4\reg$next[3:0]$11348 - attribute \src "libresoc.v:170992.3-171031.6" - wire width 4 $4\src14__data_o$next[3:0]$11339 - attribute \src "libresoc.v:171089.3-171128.6" - wire width 4 $4\src24__data_o$next[3:0]$11354 - attribute \src "libresoc.v:171159.3-171198.6" - wire width 4 $4\src34__data_o$next[3:0]$11368 - attribute \src "libresoc.v:171269.3-171298.6" - wire $4\wr_detect$10[0:0]$11390 - attribute \src "libresoc.v:171339.3-171368.6" - wire $4\wr_detect$13[0:0]$11404 - attribute \src "libresoc.v:171129.3-171158.6" - wire $4\wr_detect$4[0:0]$11362 - attribute \src "libresoc.v:171199.3-171228.6" - wire $4\wr_detect$7[0:0]$11376 - attribute \src "libresoc.v:171032.3-171061.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:171299.3-171338.6" - wire width 4 $5\r24__data_o$next[3:0]$11397 - attribute \src "libresoc.v:171229.3-171268.6" - wire width 4 $5\r4__data_o$next[3:0]$11383 - attribute \src "libresoc.v:170992.3-171031.6" - wire width 4 $5\src14__data_o$next[3:0]$11340 - attribute \src "libresoc.v:171089.3-171128.6" - wire width 4 $5\src24__data_o$next[3:0]$11355 - attribute \src "libresoc.v:171159.3-171198.6" - wire width 4 $5\src34__data_o$next[3:0]$11369 - attribute \src "libresoc.v:171299.3-171338.6" - wire width 4 $6\r24__data_o$next[3:0]$11398 - attribute \src "libresoc.v:171229.3-171268.6" - wire width 4 $6\r4__data_o$next[3:0]$11384 - attribute \src "libresoc.v:170992.3-171031.6" - wire width 4 $6\src14__data_o$next[3:0]$11341 - attribute \src "libresoc.v:171089.3-171128.6" - wire width 4 $6\src24__data_o$next[3:0]$11356 - attribute \src "libresoc.v:171159.3-171198.6" - wire width 4 $6\src34__data_o$next[3:0]$11370 - attribute \src "libresoc.v:170975.17-170975.104" - wire $not$libresoc.v:170975$11323_Y - attribute \src "libresoc.v:170976.18-170976.105" - wire $not$libresoc.v:170976$11324_Y - attribute \src "libresoc.v:170977.17-170977.100" - wire $not$libresoc.v:170977$11325_Y - attribute \src "libresoc.v:170978.17-170978.103" - wire $not$libresoc.v:170978$11326_Y - attribute \src "libresoc.v:170979.17-170979.103" - wire $not$libresoc.v:170979$11327_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest24__wen - attribute \src "libresoc.v:170899.7-170899.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r4__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r4__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src14__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src34__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w4__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170975$11323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:170975$11323_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170976$11324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:170976$11324_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170977$11325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:170977$11325_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170978$11326 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:170978$11326_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:170979$11327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:170979$11327_Y - end - attribute \src "libresoc.v:170899.7-170899.20" - process $proc$libresoc.v:170899$11405 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:170924.13-170924.31" - process $proc$libresoc.v:170924$11406 - assign { } { } - assign $1\r24__data_o[3:0] 4'0000 - sync always - sync init - update \r24__data_o $1\r24__data_o[3:0] - end - attribute \src "libresoc.v:170931.13-170931.30" - process $proc$libresoc.v:170931$11407 - assign { } { } - assign $1\r4__data_o[3:0] 4'0000 - sync always - sync init - update \r4__data_o $1\r4__data_o[3:0] - end - attribute \src "libresoc.v:170937.13-170937.25" - process $proc$libresoc.v:170937$11408 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "libresoc.v:170942.13-170942.33" - process $proc$libresoc.v:170942$11409 - assign { } { } - assign $1\src14__data_o[3:0] 4'0000 - sync always - sync init - update \src14__data_o $1\src14__data_o[3:0] - end - attribute \src "libresoc.v:170949.13-170949.33" - process $proc$libresoc.v:170949$11410 - assign { } { } - assign $1\src24__data_o[3:0] 4'0000 - sync always - sync init - update \src24__data_o $1\src24__data_o[3:0] - end - attribute \src "libresoc.v:170956.13-170956.33" - process $proc$libresoc.v:170956$11411 - assign { } { } - assign $1\src34__data_o[3:0] 4'0000 - sync always - sync init - update \src34__data_o $1\src34__data_o[3:0] - end - attribute \src "libresoc.v:170980.3-170981.25" - process $proc$libresoc.v:170980$11328 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:170982.3-170983.39" - process $proc$libresoc.v:170982$11329 - assign { } { } - assign $0\r24__data_o[3:0] \r24__data_o$next - sync posedge \coresync_clk - update \r24__data_o $0\r24__data_o[3:0] - end - attribute \src "libresoc.v:170984.3-170985.37" - process $proc$libresoc.v:170984$11330 - assign { } { } - assign $0\r4__data_o[3:0] \r4__data_o$next - sync posedge \coresync_clk - update \r4__data_o $0\r4__data_o[3:0] - end - attribute \src "libresoc.v:170986.3-170987.43" - process $proc$libresoc.v:170986$11331 - assign { } { } - assign $0\src34__data_o[3:0] \src34__data_o$next - sync posedge \coresync_clk - update \src34__data_o $0\src34__data_o[3:0] - end - attribute \src "libresoc.v:170988.3-170989.43" - process $proc$libresoc.v:170988$11332 - assign { } { } - assign $0\src24__data_o[3:0] \src24__data_o$next - sync posedge \coresync_clk - update \src24__data_o $0\src24__data_o[3:0] - end - attribute \src "libresoc.v:170990.3-170991.43" - process $proc$libresoc.v:170990$11333 - assign { } { } - assign $0\src14__data_o[3:0] \src14__data_o$next - sync posedge \coresync_clk - update \src14__data_o $0\src14__data_o[3:0] + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:170992.3-171031.6" - process $proc$libresoc.v:170992$11334 - assign { } { } + attribute \src "libresoc.v:32160.3-32178.6" + process $proc$libresoc.v:32160$692 assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11335 $6\src14__data_o$next[3:0]$11341 - attribute \src "libresoc.v:170993.5-170993.29" + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:32161.5-32161.29" switch \initial - attribute \src "libresoc.v:170993.9-170993.17" + attribute \src "libresoc.v:32161.9-32161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\src14__data_o$next[3:0]$11336 $5\src14__data_o$next[3:0]$11340 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src14__data_o$next[3:0]$11337 \dest14__data_i - case - assign $2\src14__data_o$next[3:0]$11337 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src14__data_o$next[3:0]$11338 \dest24__data_i - case - assign $3\src14__data_o$next[3:0]$11338 $2\src14__data_o$next[3:0]$11337 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src14__data_o$next[3:0]$11339 \w4__data_i - case - assign $4\src14__data_o$next[3:0]$11339 $3\src14__data_o$next[3:0]$11338 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src14__data_o$next[3:0]$11340 \reg - case - assign $5\src14__data_o$next[3:0]$11340 $4\src14__data_o$next[3:0]$11339 - end - case - assign $1\src14__data_o$next[3:0]$11336 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\src14__data_o$next[3:0]$11341 4'0000 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 case - assign $6\src14__data_o$next[3:0]$11341 $1\src14__data_o$next[3:0]$11336 + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11335 + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:171032.3-171061.6" - process $proc$libresoc.v:171032$11342 + attribute \src "libresoc.v:32179.3-32197.6" + process $proc$libresoc.v:32179$693 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:171033.5-171033.29" + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:32180.5-32180.29" switch \initial - attribute \src "libresoc.v:171033.9-171033.17" + attribute \src "libresoc.v:32180.9-32180.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src14__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:171062.3-171088.6" - process $proc$libresoc.v:171062$11343 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:32198.3-32216.6" + process $proc$libresoc.v:32198$694 assign { } { } assign { } { } - assign $0\reg$next[3:0]$11344 $4\reg$next[3:0]$11348 - attribute \src "libresoc.v:171063.5-171063.29" + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:32199.5-32199.29" switch \initial - attribute \src "libresoc.v:171063.9-171063.17" + attribute \src "libresoc.v:32199.9-32199.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest14__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $1\reg$next[3:0]$11345 \dest14__data_i - case - assign $1\reg$next[3:0]$11345 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest24__wen + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11000 assign { } { } - assign $2\reg$next[3:0]$11346 \dest24__data_i - case - assign $2\reg$next[3:0]$11346 $1\reg$next[3:0]$11345 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w4__wen + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $3\reg$next[3:0]$11347 \w4__data_i - case - assign $3\reg$next[3:0]$11347 $2\reg$next[3:0]$11346 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $4\reg$next[3:0]$11348 4'0000 + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 case - assign $4\reg$next[3:0]$11348 $3\reg$next[3:0]$11347 + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 end sync always - update \reg$next $0\reg$next[3:0]$11344 + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:171089.3-171128.6" - process $proc$libresoc.v:171089$11349 - assign { } { } + attribute \src "libresoc.v:32217.3-32235.6" + process $proc$libresoc.v:32217$695 assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11350 $6\src24__data_o$next[3:0]$11356 - attribute \src "libresoc.v:171090.5-171090.29" + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:32218.5-32218.29" switch \initial - attribute \src "libresoc.v:171090.9-171090.17" + attribute \src "libresoc.v:32218.9-32218.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\src24__data_o$next[3:0]$11351 $5\src24__data_o$next[3:0]$11355 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src24__data_o$next[3:0]$11352 \dest14__data_i - case - assign $2\src24__data_o$next[3:0]$11352 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src24__data_o$next[3:0]$11353 \dest24__data_i - case - assign $3\src24__data_o$next[3:0]$11353 $2\src24__data_o$next[3:0]$11352 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src24__data_o$next[3:0]$11354 \w4__data_i - case - assign $4\src24__data_o$next[3:0]$11354 $3\src24__data_o$next[3:0]$11353 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src24__data_o$next[3:0]$11355 \reg - case - assign $5\src24__data_o$next[3:0]$11355 $4\src24__data_o$next[3:0]$11354 - end - case - assign $1\src24__data_o$next[3:0]$11351 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\src24__data_o$next[3:0]$11356 4'0000 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 case - assign $6\src24__data_o$next[3:0]$11356 $1\src24__data_o$next[3:0]$11351 + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11350 + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:171129.3-171158.6" - process $proc$libresoc.v:171129$11357 + attribute \src "libresoc.v:32236.3-32254.6" + process $proc$libresoc.v:32236$696 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11358 $1\wr_detect$4[0:0]$11359 - attribute \src "libresoc.v:171130.5-171130.29" + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:32237.5-32237.29" switch \initial - attribute \src "libresoc.v:171130.9-171130.17" + attribute \src "libresoc.v:32237.9-32237.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src24__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$4[0:0]$11359 $4\wr_detect$4[0:0]$11362 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11360 1'1 - case - assign $2\wr_detect$4[0:0]$11360 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11361 1'1 - case - assign $3\wr_detect$4[0:0]$11361 $2\wr_detect$4[0:0]$11360 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11362 1'1 - case - assign $4\wr_detect$4[0:0]$11362 $3\wr_detect$4[0:0]$11361 - end + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 case - assign $1\wr_detect$4[0:0]$11359 1'0 + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11358 + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:171159.3-171198.6" - process $proc$libresoc.v:171159$11363 - assign { } { } + attribute \src "libresoc.v:32255.3-32273.6" + process $proc$libresoc.v:32255$697 assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11364 $6\src34__data_o$next[3:0]$11370 - attribute \src "libresoc.v:171160.5-171160.29" + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:32256.5-32256.29" switch \initial - attribute \src "libresoc.v:171160.9-171160.17" + attribute \src "libresoc.v:32256.9-32256.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\src34__data_o$next[3:0]$11365 $5\src34__data_o$next[3:0]$11369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src34__data_o$next[3:0]$11366 \dest14__data_i - case - assign $2\src34__data_o$next[3:0]$11366 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src34__data_o$next[3:0]$11367 \dest24__data_i - case - assign $3\src34__data_o$next[3:0]$11367 $2\src34__data_o$next[3:0]$11366 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src34__data_o$next[3:0]$11368 \w4__data_i - case - assign $4\src34__data_o$next[3:0]$11368 $3\src34__data_o$next[3:0]$11367 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src34__data_o$next[3:0]$11369 \reg - case - assign $5\src34__data_o$next[3:0]$11369 $4\src34__data_o$next[3:0]$11368 - end + assign $1\dec31_dec_sub24_lk[0:0] 1'0 case - assign $1\src34__data_o$next[3:0]$11365 4'0000 + assign $1\dec31_dec_sub24_lk[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:32274.3-32292.6" + process $proc$libresoc.v:32274$698 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:32275.5-32275.29" + switch \initial + attribute \src "libresoc.v:32275.9-32275.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $6\src34__data_o$next[3:0]$11370 4'0000 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 case - assign $6\src34__data_o$next[3:0]$11370 $1\src34__data_o$next[3:0]$11365 + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11364 + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:171199.3-171228.6" - process $proc$libresoc.v:171199$11371 + attribute \src "libresoc.v:32293.3-32311.6" + process $proc$libresoc.v:32293$699 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11372 $1\wr_detect$7[0:0]$11373 - attribute \src "libresoc.v:171200.5-171200.29" + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:32294.5-32294.29" switch \initial - attribute \src "libresoc.v:171200.9-171200.17" + attribute \src "libresoc.v:32294.9-32294.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src34__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$7[0:0]$11373 $4\wr_detect$7[0:0]$11376 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$11374 1'1 - case - assign $2\wr_detect$7[0:0]$11374 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$11375 1'1 - case - assign $3\wr_detect$7[0:0]$11375 $2\wr_detect$7[0:0]$11374 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$11376 1'1 - case - assign $4\wr_detect$7[0:0]$11376 $3\wr_detect$7[0:0]$11375 - end + assign $1\dec31_dec_sub24_form[4:0] 5'01000 case - assign $1\wr_detect$7[0:0]$11373 1'0 + assign $1\dec31_dec_sub24_form[4:0] 5'00000 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11372 + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:171229.3-171268.6" - process $proc$libresoc.v:171229$11377 - assign { } { } + attribute \src "libresoc.v:32312.3-32330.6" + process $proc$libresoc.v:32312$700 assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11378 $6\r4__data_o$next[3:0]$11384 - attribute \src "libresoc.v:171230.5-171230.29" + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:32313.5-32313.29" switch \initial - attribute \src "libresoc.v:171230.9-171230.17" + attribute \src "libresoc.v:32313.9-32313.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\r4__data_o$next[3:0]$11379 $5\r4__data_o$next[3:0]$11383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r4__data_o$next[3:0]$11380 \dest14__data_i - case - assign $2\r4__data_o$next[3:0]$11380 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r4__data_o$next[3:0]$11381 \dest24__data_i - case - assign $3\r4__data_o$next[3:0]$11381 $2\r4__data_o$next[3:0]$11380 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r4__data_o$next[3:0]$11382 \w4__data_i - case - assign $4\r4__data_o$next[3:0]$11382 $3\r4__data_o$next[3:0]$11381 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r4__data_o$next[3:0]$11383 \reg - case - assign $5\r4__data_o$next[3:0]$11383 $4\r4__data_o$next[3:0]$11382 - end + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 case - assign $1\r4__data_o$next[3:0]$11379 4'0000 + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:32331.3-32349.6" + process $proc$libresoc.v:32331$701 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:32332.5-32332.29" + switch \initial + attribute \src "libresoc.v:32332.9-32332.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $6\r4__data_o$next[3:0]$11384 4'0000 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 case - assign $6\r4__data_o$next[3:0]$11384 $1\r4__data_o$next[3:0]$11379 + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11378 + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:171269.3-171298.6" - process $proc$libresoc.v:171269$11385 + attribute \src "libresoc.v:32350.3-32368.6" + process $proc$libresoc.v:32350$702 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11386 $1\wr_detect$10[0:0]$11387 - attribute \src "libresoc.v:171270.5-171270.29" + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:32351.5-32351.29" switch \initial - attribute \src "libresoc.v:171270.9-171270.17" + attribute \src "libresoc.v:32351.9-32351.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r4__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$10[0:0]$11387 $4\wr_detect$10[0:0]$11390 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11388 1'1 - case - assign $2\wr_detect$10[0:0]$11388 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11389 1'1 - case - assign $3\wr_detect$10[0:0]$11389 $2\wr_detect$10[0:0]$11388 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11390 1'1 - case - assign $4\wr_detect$10[0:0]$11390 $3\wr_detect$10[0:0]$11389 - end + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 case - assign $1\wr_detect$10[0:0]$11387 1'0 + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11386 + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:171299.3-171338.6" - process $proc$libresoc.v:171299$11391 + attribute \src "libresoc.v:32369.3-32387.6" + process $proc$libresoc.v:32369$703 assign { } { } assign { } { } - assign { } { } - assign $0\r24__data_o$next[3:0]$11392 $6\r24__data_o$next[3:0]$11398 - attribute \src "libresoc.v:171300.5-171300.29" + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:32370.5-32370.29" switch \initial - attribute \src "libresoc.v:171300.9-171300.17" + attribute \src "libresoc.v:32370.9-32370.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\r24__data_o$next[3:0]$11393 $5\r24__data_o$next[3:0]$11397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r24__data_o$next[3:0]$11394 \dest14__data_i - case - assign $2\r24__data_o$next[3:0]$11394 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r24__data_o$next[3:0]$11395 \dest24__data_i - case - assign $3\r24__data_o$next[3:0]$11395 $2\r24__data_o$next[3:0]$11394 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r24__data_o$next[3:0]$11396 \w4__data_i - case - assign $4\r24__data_o$next[3:0]$11396 $3\r24__data_o$next[3:0]$11395 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r24__data_o$next[3:0]$11397 \reg - case - assign $5\r24__data_o$next[3:0]$11397 $4\r24__data_o$next[3:0]$11396 - end + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 case - assign $1\r24__data_o$next[3:0]$11393 4'0000 + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + end + attribute \src "libresoc.v:32388.3-32406.6" + process $proc$libresoc.v:32388$704 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:32389.5-32389.29" + switch \initial + attribute \src "libresoc.v:32389.9-32389.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $6\r24__data_o$next[3:0]$11398 4'0000 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 case - assign $6\r24__data_o$next[3:0]$11398 $1\r24__data_o$next[3:0]$11393 + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11392 + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:171339.3-171368.6" - process $proc$libresoc.v:171339$11399 + attribute \src "libresoc.v:32407.3-32425.6" + process $proc$libresoc.v:32407$705 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11400 $1\wr_detect$13[0:0]$11401 - attribute \src "libresoc.v:171340.5-171340.29" + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:32408.5-32408.29" switch \initial - attribute \src "libresoc.v:171340.9-171340.17" + attribute \src "libresoc.v:32408.9-32408.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r24__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$13[0:0]$11401 $4\wr_detect$13[0:0]$11404 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest14__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$11402 1'1 - case - assign $2\wr_detect$13[0:0]$11402 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest24__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$11403 1'1 - case - assign $3\wr_detect$13[0:0]$11403 $2\wr_detect$13[0:0]$11402 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w4__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$11404 1'1 - case - assign $4\wr_detect$13[0:0]$11404 $3\wr_detect$13[0:0]$11403 - end + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 case - assign $1\wr_detect$13[0:0]$11401 1'0 + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11400 + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - connect \$9 $not$libresoc.v:170975$11323_Y - connect \$12 $not$libresoc.v:170976$11324_Y - connect \$1 $not$libresoc.v:170977$11325_Y - connect \$3 $not$libresoc.v:170978$11326_Y - connect \$6 $not$libresoc.v:170979$11327_Y + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:171373.1-171844.10" +attribute \src "libresoc.v:32431.1-33938.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" -module \reg_5 - attribute \src "libresoc.v:171374.7-171374.20" +module \dec31_dec_sub26 + attribute \src "libresoc.v:32949.3-33000.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33157.3-33208.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33833.3-33884.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33885.3-33936.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32897.3-32948.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:33105.3-33156.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33573.3-33624.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32689.3-32740.6" + wire width 12 $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33625.3-33676.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33677.3-33728.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33729.3-33780.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33261.3-33312.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33001.3-33052.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33053.3-33104.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33365.3-33416.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32741.3-32792.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33469.3-33520.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33781.3-33832.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32845.3-32896.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33313.3-33364.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33521.3-33572.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33417.3-33468.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33209.3-33260.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32793.3-32844.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32432.7-32432.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171774.3-171813.6" - wire width 4 $0\r25__data_o$next[3:0]$11481 - attribute \src "libresoc.v:171457.3-171458.39" - wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:171704.3-171743.6" - wire width 4 $0\r5__data_o$next[3:0]$11467 - attribute \src "libresoc.v:171459.3-171460.37" - wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:171537.3-171563.6" - wire width 4 $0\reg$next[3:0]$11433 - attribute \src "libresoc.v:171455.3-171456.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:171467.3-171506.6" - wire width 4 $0\src15__data_o$next[3:0]$11424 - attribute \src "libresoc.v:171465.3-171466.43" - wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:171564.3-171603.6" - wire width 4 $0\src25__data_o$next[3:0]$11439 - attribute \src "libresoc.v:171463.3-171464.43" - wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:171634.3-171673.6" - wire width 4 $0\src35__data_o$next[3:0]$11453 - attribute \src "libresoc.v:171461.3-171462.43" - wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:171744.3-171773.6" - wire $0\wr_detect$10[0:0]$11475 - attribute \src "libresoc.v:171814.3-171843.6" - wire $0\wr_detect$13[0:0]$11489 - attribute \src "libresoc.v:171604.3-171633.6" - wire $0\wr_detect$4[0:0]$11447 - attribute \src "libresoc.v:171674.3-171703.6" - wire $0\wr_detect$7[0:0]$11461 - attribute \src "libresoc.v:171507.3-171536.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:171774.3-171813.6" - wire width 4 $1\r25__data_o$next[3:0]$11482 - attribute \src "libresoc.v:171399.13-171399.31" - wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:171704.3-171743.6" - wire width 4 $1\r5__data_o$next[3:0]$11468 - attribute \src "libresoc.v:171406.13-171406.30" - wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:171537.3-171563.6" - wire width 4 $1\reg$next[3:0]$11434 - attribute \src "libresoc.v:171412.13-171412.25" - wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:171467.3-171506.6" - wire width 4 $1\src15__data_o$next[3:0]$11425 - attribute \src "libresoc.v:171417.13-171417.33" - wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:171564.3-171603.6" - wire width 4 $1\src25__data_o$next[3:0]$11440 - attribute \src "libresoc.v:171424.13-171424.33" - wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:171634.3-171673.6" - wire width 4 $1\src35__data_o$next[3:0]$11454 - attribute \src "libresoc.v:171431.13-171431.33" - wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:171744.3-171773.6" - wire $1\wr_detect$10[0:0]$11476 - attribute \src "libresoc.v:171814.3-171843.6" - wire $1\wr_detect$13[0:0]$11490 - attribute \src "libresoc.v:171604.3-171633.6" - wire $1\wr_detect$4[0:0]$11448 - attribute \src "libresoc.v:171674.3-171703.6" - wire $1\wr_detect$7[0:0]$11462 - attribute \src "libresoc.v:171507.3-171536.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:171774.3-171813.6" - wire width 4 $2\r25__data_o$next[3:0]$11483 - attribute \src "libresoc.v:171704.3-171743.6" - wire width 4 $2\r5__data_o$next[3:0]$11469 - attribute \src "libresoc.v:171537.3-171563.6" - wire width 4 $2\reg$next[3:0]$11435 - attribute \src "libresoc.v:171467.3-171506.6" - wire width 4 $2\src15__data_o$next[3:0]$11426 - attribute \src "libresoc.v:171564.3-171603.6" - wire width 4 $2\src25__data_o$next[3:0]$11441 - attribute \src "libresoc.v:171634.3-171673.6" - wire width 4 $2\src35__data_o$next[3:0]$11455 - attribute \src "libresoc.v:171744.3-171773.6" - wire $2\wr_detect$10[0:0]$11477 - attribute \src "libresoc.v:171814.3-171843.6" - wire $2\wr_detect$13[0:0]$11491 - attribute \src "libresoc.v:171604.3-171633.6" - wire $2\wr_detect$4[0:0]$11449 - attribute \src "libresoc.v:171674.3-171703.6" - wire $2\wr_detect$7[0:0]$11463 - attribute \src "libresoc.v:171507.3-171536.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:171774.3-171813.6" - wire width 4 $3\r25__data_o$next[3:0]$11484 - attribute \src "libresoc.v:171704.3-171743.6" - wire width 4 $3\r5__data_o$next[3:0]$11470 - attribute \src "libresoc.v:171537.3-171563.6" - wire width 4 $3\reg$next[3:0]$11436 - attribute \src "libresoc.v:171467.3-171506.6" - wire width 4 $3\src15__data_o$next[3:0]$11427 - attribute \src "libresoc.v:171564.3-171603.6" - wire width 4 $3\src25__data_o$next[3:0]$11442 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest25__wen - attribute \src "libresoc.v:171374.7-171374.15" + attribute \src "libresoc.v:32949.3-33000.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:33157.3-33208.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33833.3-33884.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33885.3-33936.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:32897.3-32948.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:33105.3-33156.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33573.3-33624.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:32689.3-32740.6" + wire width 12 $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:33625.3-33676.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33677.3-33728.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33729.3-33780.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33261.3-33312.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33001.3-33052.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33053.3-33104.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33365.3-33416.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:32741.3-32792.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:33469.3-33520.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33781.3-33832.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:32845.3-32896.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:33313.3-33364.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33521.3-33572.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33417.3-33468.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33209.3-33260.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:32793.3-32844.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub26_upd + attribute \src "libresoc.v:32432.7-32432.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r5__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r5__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src15__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src35__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w5__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171450$11412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:171450$11412_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171451$11413 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:171451$11413_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171452$11414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:171452$11414_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171453$11415 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:171453$11415_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171454$11416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:171454$11416_Y - end - attribute \src "libresoc.v:171374.7-171374.20" - process $proc$libresoc.v:171374$11494 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:32432.7-32432.20" + process $proc$libresoc.v:32432$731 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171399.13-171399.31" - process $proc$libresoc.v:171399$11495 - assign { } { } - assign $1\r25__data_o[3:0] 4'0000 - sync always - sync init - update \r25__data_o $1\r25__data_o[3:0] - end - attribute \src "libresoc.v:171406.13-171406.30" - process $proc$libresoc.v:171406$11496 - assign { } { } - assign $1\r5__data_o[3:0] 4'0000 - sync always - sync init - update \r5__data_o $1\r5__data_o[3:0] - end - attribute \src "libresoc.v:171412.13-171412.25" - process $proc$libresoc.v:171412$11497 + attribute \src "libresoc.v:32689.3-32740.6" + process $proc$libresoc.v:32689$707 assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "libresoc.v:171417.13-171417.33" - process $proc$libresoc.v:171417$11498 assign { } { } - assign $1\src15__data_o[3:0] 4'0000 + assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "libresoc.v:32690.5-32690.29" + switch \initial + attribute \src "libresoc.v:32690.9-32690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end sync always - sync init - update \src15__data_o $1\src15__data_o[3:0] + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] end - attribute \src "libresoc.v:171424.13-171424.33" - process $proc$libresoc.v:171424$11499 + attribute \src "libresoc.v:32741.3-32792.6" + process $proc$libresoc.v:32741$708 assign { } { } - assign $1\src25__data_o[3:0] 4'0000 - sync always - sync init - update \src25__data_o $1\src25__data_o[3:0] - end - attribute \src "libresoc.v:171431.13-171431.33" - process $proc$libresoc.v:171431$11500 assign { } { } - assign $1\src35__data_o[3:0] 4'0000 + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:32742.5-32742.29" + switch \initial + attribute \src "libresoc.v:32742.9-32742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end sync always - sync init - update \src35__data_o $1\src35__data_o[3:0] - end - attribute \src "libresoc.v:171455.3-171456.25" - process $proc$libresoc.v:171455$11417 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:171457.3-171458.39" - process $proc$libresoc.v:171457$11418 - assign { } { } - assign $0\r25__data_o[3:0] \r25__data_o$next - sync posedge \coresync_clk - update \r25__data_o $0\r25__data_o[3:0] - end - attribute \src "libresoc.v:171459.3-171460.37" - process $proc$libresoc.v:171459$11419 - assign { } { } - assign $0\r5__data_o[3:0] \r5__data_o$next - sync posedge \coresync_clk - update \r5__data_o $0\r5__data_o[3:0] - end - attribute \src "libresoc.v:171461.3-171462.43" - process $proc$libresoc.v:171461$11420 - assign { } { } - assign $0\src35__data_o[3:0] \src35__data_o$next - sync posedge \coresync_clk - update \src35__data_o $0\src35__data_o[3:0] - end - attribute \src "libresoc.v:171463.3-171464.43" - process $proc$libresoc.v:171463$11421 - assign { } { } - assign $0\src25__data_o[3:0] \src25__data_o$next - sync posedge \coresync_clk - update \src25__data_o $0\src25__data_o[3:0] - end - attribute \src "libresoc.v:171465.3-171466.43" - process $proc$libresoc.v:171465$11422 - assign { } { } - assign $0\src15__data_o[3:0] \src15__data_o$next - sync posedge \coresync_clk - update \src15__data_o $0\src15__data_o[3:0] + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:171467.3-171506.6" - process $proc$libresoc.v:171467$11423 - assign { } { } + attribute \src "libresoc.v:32793.3-32844.6" + process $proc$libresoc.v:32793$709 assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11424 $6\src15__data_o$next[3:0]$11430 - attribute \src "libresoc.v:171468.5-171468.29" + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:32794.5-32794.29" switch \initial - attribute \src "libresoc.v:171468.9-171468.17" + attribute \src "libresoc.v:32794.9-32794.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 assign { } { } - assign $1\src15__data_o$next[3:0]$11425 $5\src15__data_o$next[3:0]$11429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src15__data_o$next[3:0]$11426 \dest15__data_i - case - assign $2\src15__data_o$next[3:0]$11426 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src15__data_o$next[3:0]$11427 \dest25__data_i - case - assign $3\src15__data_o$next[3:0]$11427 $2\src15__data_o$next[3:0]$11426 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src15__data_o$next[3:0]$11428 \w5__data_i - case - assign $4\src15__data_o$next[3:0]$11428 $3\src15__data_o$next[3:0]$11427 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src15__data_o$next[3:0]$11429 \reg - case - assign $5\src15__data_o$next[3:0]$11429 $4\src15__data_o$next[3:0]$11428 - end - case - assign $1\src15__data_o$next[3:0]$11425 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\src15__data_o$next[3:0]$11430 4'0000 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 case - assign $6\src15__data_o$next[3:0]$11430 $1\src15__data_o$next[3:0]$11425 + assign $1\dec31_dec_sub26_upd[1:0] 2'00 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11424 + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:171507.3-171536.6" - process $proc$libresoc.v:171507$11431 + attribute \src "libresoc.v:32845.3-32896.6" + process $proc$libresoc.v:32845$710 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:171508.5-171508.29" + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:32846.5-32846.29" switch \initial - attribute \src "libresoc.v:171508.9-171508.17" + attribute \src "libresoc.v:32846.9-32846.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src15__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:171537.3-171563.6" - process $proc$libresoc.v:171537$11432 - assign { } { } + attribute \src "libresoc.v:32897.3-32948.6" + process $proc$libresoc.v:32897$711 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11433 $4\reg$next[3:0]$11437 - attribute \src "libresoc.v:171538.5-171538.29" + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:32898.5-32898.29" switch \initial - attribute \src "libresoc.v:171538.9-171538.17" + attribute \src "libresoc.v:32898.9-32898.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest15__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $1\reg$next[3:0]$11434 \dest15__data_i - case - assign $1\reg$next[3:0]$11434 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest25__wen + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $2\reg$next[3:0]$11435 \dest25__data_i - case - assign $2\reg$next[3:0]$11435 $1\reg$next[3:0]$11434 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w5__wen + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10001 assign { } { } - assign $3\reg$next[3:0]$11436 \w5__data_i - case - assign $3\reg$next[3:0]$11436 $2\reg$next[3:0]$11435 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 assign { } { } - assign $4\reg$next[3:0]$11437 4'0000 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 case - assign $4\reg$next[3:0]$11437 $3\reg$next[3:0]$11436 + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 end sync always - update \reg$next $0\reg$next[3:0]$11433 + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:171564.3-171603.6" - process $proc$libresoc.v:171564$11438 - assign { } { } + attribute \src "libresoc.v:32949.3-33000.6" + process $proc$libresoc.v:32949$712 assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11439 $6\src25__data_o$next[3:0]$11445 - attribute \src "libresoc.v:171565.5-171565.29" + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:32950.5-32950.29" switch \initial - attribute \src "libresoc.v:171565.9-171565.17" + attribute \src "libresoc.v:32950.9-32950.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\src25__data_o$next[3:0]$11440 $5\src25__data_o$next[3:0]$11444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src25__data_o$next[3:0]$11441 \dest15__data_i - case - assign $2\src25__data_o$next[3:0]$11441 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src25__data_o$next[3:0]$11442 \dest25__data_i - case - assign $3\src25__data_o$next[3:0]$11442 $2\src25__data_o$next[3:0]$11441 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src25__data_o$next[3:0]$11443 \w5__data_i - case - assign $4\src25__data_o$next[3:0]$11443 $3\src25__data_o$next[3:0]$11442 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src25__data_o$next[3:0]$11444 \reg - case - assign $5\src25__data_o$next[3:0]$11444 $4\src25__data_o$next[3:0]$11443 - end - case - assign $1\src25__data_o$next[3:0]$11440 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\src25__data_o$next[3:0]$11445 4'0000 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 case - assign $6\src25__data_o$next[3:0]$11445 $1\src25__data_o$next[3:0]$11440 + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11439 + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:171604.3-171633.6" - process $proc$libresoc.v:171604$11446 + attribute \src "libresoc.v:33001.3-33052.6" + process $proc$libresoc.v:33001$713 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11447 $1\wr_detect$4[0:0]$11448 - attribute \src "libresoc.v:171605.5-171605.29" + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:33002.5-33002.29" switch \initial - attribute \src "libresoc.v:171605.9-171605.17" + attribute \src "libresoc.v:33002.9-33002.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src25__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$4[0:0]$11448 $4\wr_detect$4[0:0]$11451 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11449 1'1 - case - assign $2\wr_detect$4[0:0]$11449 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11450 1'1 - case - assign $3\wr_detect$4[0:0]$11450 $2\wr_detect$4[0:0]$11449 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11451 1'1 - case - assign $4\wr_detect$4[0:0]$11451 $3\wr_detect$4[0:0]$11450 - end + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 case - assign $1\wr_detect$4[0:0]$11448 1'0 + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11447 + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:171634.3-171673.6" - process $proc$libresoc.v:171634$11452 - assign { } { } + attribute \src "libresoc.v:33053.3-33104.6" + process $proc$libresoc.v:33053$714 assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11453 $6\src35__data_o$next[3:0]$11459 - attribute \src "libresoc.v:171635.5-171635.29" + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:33054.5-33054.29" switch \initial - attribute \src "libresoc.v:171635.9-171635.17" + attribute \src "libresoc.v:33054.9-33054.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\src35__data_o$next[3:0]$11454 $5\src35__data_o$next[3:0]$11458 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src35__data_o$next[3:0]$11455 \dest15__data_i - case - assign $2\src35__data_o$next[3:0]$11455 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src35__data_o$next[3:0]$11456 \dest25__data_i - case - assign $3\src35__data_o$next[3:0]$11456 $2\src35__data_o$next[3:0]$11455 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src35__data_o$next[3:0]$11457 \w5__data_i - case - assign $4\src35__data_o$next[3:0]$11457 $3\src35__data_o$next[3:0]$11456 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src35__data_o$next[3:0]$11458 \reg - case - assign $5\src35__data_o$next[3:0]$11458 $4\src35__data_o$next[3:0]$11457 - end - case - assign $1\src35__data_o$next[3:0]$11454 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\src35__data_o$next[3:0]$11459 4'0000 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 case - assign $6\src35__data_o$next[3:0]$11459 $1\src35__data_o$next[3:0]$11454 + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11453 + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:171674.3-171703.6" - process $proc$libresoc.v:171674$11460 + attribute \src "libresoc.v:33105.3-33156.6" + process $proc$libresoc.v:33105$715 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11461 $1\wr_detect$7[0:0]$11462 - attribute \src "libresoc.v:171675.5-171675.29" + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:33106.5-33106.29" switch \initial - attribute \src "libresoc.v:171675.9-171675.17" + attribute \src "libresoc.v:33106.9-33106.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src35__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$7[0:0]$11462 $4\wr_detect$7[0:0]$11465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$11463 1'1 - case - assign $2\wr_detect$7[0:0]$11463 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$11464 1'1 - case - assign $3\wr_detect$7[0:0]$11464 $2\wr_detect$7[0:0]$11463 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$11465 1'1 - case - assign $4\wr_detect$7[0:0]$11465 $3\wr_detect$7[0:0]$11464 - end + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 case - assign $1\wr_detect$7[0:0]$11462 1'0 + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11461 + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:171704.3-171743.6" - process $proc$libresoc.v:171704$11466 + attribute \src "libresoc.v:33157.3-33208.6" + process $proc$libresoc.v:33157$716 assign { } { } assign { } { } - assign { } { } - assign $0\r5__data_o$next[3:0]$11467 $6\r5__data_o$next[3:0]$11473 - attribute \src "libresoc.v:171705.5-171705.29" + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:33158.5-33158.29" switch \initial - attribute \src "libresoc.v:171705.9-171705.17" + attribute \src "libresoc.v:33158.9-33158.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\r5__data_o$next[3:0]$11468 $5\r5__data_o$next[3:0]$11472 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r5__data_o$next[3:0]$11469 \dest15__data_i - case - assign $2\r5__data_o$next[3:0]$11469 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r5__data_o$next[3:0]$11470 \dest25__data_i - case - assign $3\r5__data_o$next[3:0]$11470 $2\r5__data_o$next[3:0]$11469 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r5__data_o$next[3:0]$11471 \w5__data_i - case - assign $4\r5__data_o$next[3:0]$11471 $3\r5__data_o$next[3:0]$11470 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r5__data_o$next[3:0]$11472 \reg - case - assign $5\r5__data_o$next[3:0]$11472 $4\r5__data_o$next[3:0]$11471 - end - case - assign $1\r5__data_o$next[3:0]$11468 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\r5__data_o$next[3:0]$11473 4'0000 + assign $1\dec31_dec_sub26_br[0:0] 1'0 case - assign $6\r5__data_o$next[3:0]$11473 $1\r5__data_o$next[3:0]$11468 + assign $1\dec31_dec_sub26_br[0:0] 1'0 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11467 + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:171744.3-171773.6" - process $proc$libresoc.v:171744$11474 + attribute \src "libresoc.v:33209.3-33260.6" + process $proc$libresoc.v:33209$717 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11475 $1\wr_detect$10[0:0]$11476 - attribute \src "libresoc.v:171745.5-171745.29" + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:33210.5-33210.29" switch \initial - attribute \src "libresoc.v:171745.9-171745.17" + attribute \src "libresoc.v:33210.9-33210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r5__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$10[0:0]$11476 $4\wr_detect$10[0:0]$11479 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11477 1'1 - case - assign $2\wr_detect$10[0:0]$11477 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11478 1'1 - case - assign $3\wr_detect$10[0:0]$11478 $2\wr_detect$10[0:0]$11477 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11479 1'1 - case - assign $4\wr_detect$10[0:0]$11479 $3\wr_detect$10[0:0]$11478 - end + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 case - assign $1\wr_detect$10[0:0]$11476 1'0 + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11475 + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:171774.3-171813.6" - process $proc$libresoc.v:171774$11480 + attribute \src "libresoc.v:33261.3-33312.6" + process $proc$libresoc.v:33261$718 assign { } { } assign { } { } - assign { } { } - assign $0\r25__data_o$next[3:0]$11481 $6\r25__data_o$next[3:0]$11487 - attribute \src "libresoc.v:171775.5-171775.29" + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:33262.5-33262.29" switch \initial - attribute \src "libresoc.v:171775.9-171775.17" + attribute \src "libresoc.v:33262.9-33262.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\r25__data_o$next[3:0]$11482 $5\r25__data_o$next[3:0]$11486 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r25__data_o$next[3:0]$11483 \dest15__data_i - case - assign $2\r25__data_o$next[3:0]$11483 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r25__data_o$next[3:0]$11484 \dest25__data_i - case - assign $3\r25__data_o$next[3:0]$11484 $2\r25__data_o$next[3:0]$11483 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r25__data_o$next[3:0]$11485 \w5__data_i - case - assign $4\r25__data_o$next[3:0]$11485 $3\r25__data_o$next[3:0]$11484 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r25__data_o$next[3:0]$11486 \reg - case - assign $5\r25__data_o$next[3:0]$11486 $4\r25__data_o$next[3:0]$11485 - end - case - assign $1\r25__data_o$next[3:0]$11482 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\r25__data_o$next[3:0]$11487 4'0000 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 case - assign $6\r25__data_o$next[3:0]$11487 $1\r25__data_o$next[3:0]$11482 + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11481 + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:171814.3-171843.6" - process $proc$libresoc.v:171814$11488 + attribute \src "libresoc.v:33313.3-33364.6" + process $proc$libresoc.v:33313$719 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11489 $1\wr_detect$13[0:0]$11490 - attribute \src "libresoc.v:171815.5-171815.29" + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:33314.5-33314.29" switch \initial - attribute \src "libresoc.v:171815.9-171815.17" + attribute \src "libresoc.v:33314.9-33314.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r25__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$13[0:0]$11490 $4\wr_detect$13[0:0]$11493 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest15__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$11491 1'1 - case - assign $2\wr_detect$13[0:0]$11491 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest25__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$11492 1'1 - case - assign $3\wr_detect$13[0:0]$11492 $2\wr_detect$13[0:0]$11491 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w5__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$11493 1'1 - case - assign $4\wr_detect$13[0:0]$11493 $3\wr_detect$13[0:0]$11492 - end + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 case - assign $1\wr_detect$13[0:0]$11490 1'0 + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11489 - end - connect \$9 $not$libresoc.v:171450$11412_Y - connect \$12 $not$libresoc.v:171451$11413_Y - connect \$1 $not$libresoc.v:171452$11414_Y - connect \$3 $not$libresoc.v:171453$11415_Y - connect \$6 $not$libresoc.v:171454$11416_Y -end -attribute \src "libresoc.v:171848.1-172319.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" -attribute \generator "nMigen" -module \reg_6 - attribute \src "libresoc.v:171849.7-171849.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:172249.3-172288.6" - wire width 4 $0\r26__data_o$next[3:0]$11570 - attribute \src "libresoc.v:171932.3-171933.39" - wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:172179.3-172218.6" - wire width 4 $0\r6__data_o$next[3:0]$11556 - attribute \src "libresoc.v:171934.3-171935.37" - wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:172012.3-172038.6" - wire width 4 $0\reg$next[3:0]$11522 - attribute \src "libresoc.v:171930.3-171931.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:171942.3-171981.6" - wire width 4 $0\src16__data_o$next[3:0]$11513 - attribute \src "libresoc.v:171940.3-171941.43" - wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:172039.3-172078.6" - wire width 4 $0\src26__data_o$next[3:0]$11528 - attribute \src "libresoc.v:171938.3-171939.43" - wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:172109.3-172148.6" - wire width 4 $0\src36__data_o$next[3:0]$11542 - attribute \src "libresoc.v:171936.3-171937.43" - wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:172219.3-172248.6" - wire $0\wr_detect$10[0:0]$11564 - attribute \src "libresoc.v:172289.3-172318.6" - wire $0\wr_detect$13[0:0]$11578 - attribute \src "libresoc.v:172079.3-172108.6" - wire $0\wr_detect$4[0:0]$11536 - attribute \src "libresoc.v:172149.3-172178.6" - wire $0\wr_detect$7[0:0]$11550 - attribute \src "libresoc.v:171982.3-172011.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:172249.3-172288.6" - wire width 4 $1\r26__data_o$next[3:0]$11571 - attribute \src "libresoc.v:171874.13-171874.31" - wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:172179.3-172218.6" - wire width 4 $1\r6__data_o$next[3:0]$11557 - attribute \src "libresoc.v:171881.13-171881.30" - wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:172012.3-172038.6" - wire width 4 $1\reg$next[3:0]$11523 - attribute \src "libresoc.v:171887.13-171887.25" - wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:171942.3-171981.6" - wire width 4 $1\src16__data_o$next[3:0]$11514 - attribute \src "libresoc.v:171892.13-171892.33" - wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:172039.3-172078.6" - wire width 4 $1\src26__data_o$next[3:0]$11529 - attribute \src "libresoc.v:171899.13-171899.33" - wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:172109.3-172148.6" - wire width 4 $1\src36__data_o$next[3:0]$11543 - attribute \src "libresoc.v:171906.13-171906.33" - wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:172219.3-172248.6" - wire $1\wr_detect$10[0:0]$11565 - attribute \src "libresoc.v:172289.3-172318.6" - wire $1\wr_detect$13[0:0]$11579 - attribute \src "libresoc.v:172079.3-172108.6" - wire $1\wr_detect$4[0:0]$11537 - attribute \src "libresoc.v:172149.3-172178.6" - wire $1\wr_detect$7[0:0]$11551 - attribute \src "libresoc.v:171982.3-172011.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:172249.3-172288.6" - wire width 4 $2\r26__data_o$next[3:0]$11572 - attribute \src "libresoc.v:172179.3-172218.6" - wire width 4 $2\r6__data_o$next[3:0]$11558 - attribute \src "libresoc.v:172012.3-172038.6" - wire width 4 $2\reg$next[3:0]$11524 - attribute \src "libresoc.v:171942.3-171981.6" - wire width 4 $2\src16__data_o$next[3:0]$11515 - attribute \src "libresoc.v:172039.3-172078.6" - wire width 4 $2\src26__data_o$next[3:0]$11530 - attribute \src "libresoc.v:172109.3-172148.6" - wire width 4 $2\src36__data_o$next[3:0]$11544 - attribute \src "libresoc.v:172219.3-172248.6" - wire $2\wr_detect$10[0:0]$11566 - attribute \src "libresoc.v:172289.3-172318.6" - wire $2\wr_detect$13[0:0]$11580 - attribute \src "libresoc.v:172079.3-172108.6" - wire $2\wr_detect$4[0:0]$11538 - attribute \src "libresoc.v:172149.3-172178.6" - wire $2\wr_detect$7[0:0]$11552 - attribute \src "libresoc.v:171982.3-172011.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:172249.3-172288.6" - wire width 4 $3\r26__data_o$next[3:0]$11573 - attribute \src "libresoc.v:172179.3-172218.6" - wire width 4 $3\r6__data_o$next[3:0]$11559 - attribute \src "libresoc.v:172012.3-172038.6" - wire width 4 $3\reg$next[3:0]$11525 - attribute \src "libresoc.v:171942.3-171981.6" - wire width 4 $3\src16__data_o$next[3:0]$11516 - attribute \src "libresoc.v:172039.3-172078.6" - wire width 4 $3\src26__data_o$next[3:0]$11531 - attribute \src "libresoc.v:172109.3-172148.6" - wire width 4 $3\src36__data_o$next[3:0]$11545 - attribute \src "libresoc.v:172219.3-172248.6" - wire $3\wr_detect$10[0:0]$11567 - attribute \src "libresoc.v:172289.3-172318.6" - wire $3\wr_detect$13[0:0]$11581 - attribute \src "libresoc.v:172079.3-172108.6" - wire $3\wr_detect$4[0:0]$11539 - attribute \src "libresoc.v:172149.3-172178.6" - wire $3\wr_detect$7[0:0]$11553 - attribute \src "libresoc.v:171982.3-172011.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:172249.3-172288.6" - wire width 4 $4\r26__data_o$next[3:0]$11574 - attribute \src "libresoc.v:172179.3-172218.6" - wire width 4 $4\r6__data_o$next[3:0]$11560 - attribute \src "libresoc.v:172012.3-172038.6" - wire width 4 $4\reg$next[3:0]$11526 - attribute \src "libresoc.v:171942.3-171981.6" - wire width 4 $4\src16__data_o$next[3:0]$11517 - attribute \src "libresoc.v:172039.3-172078.6" - wire width 4 $4\src26__data_o$next[3:0]$11532 - attribute \src "libresoc.v:172109.3-172148.6" - wire width 4 $4\src36__data_o$next[3:0]$11546 - attribute \src "libresoc.v:172219.3-172248.6" - wire $4\wr_detect$10[0:0]$11568 - attribute \src "libresoc.v:172289.3-172318.6" - wire $4\wr_detect$13[0:0]$11582 - attribute \src "libresoc.v:172079.3-172108.6" - wire $4\wr_detect$4[0:0]$11540 - attribute \src "libresoc.v:172149.3-172178.6" - wire $4\wr_detect$7[0:0]$11554 - attribute \src "libresoc.v:171982.3-172011.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:172249.3-172288.6" - wire width 4 $5\r26__data_o$next[3:0]$11575 - attribute \src "libresoc.v:172179.3-172218.6" - wire width 4 $5\r6__data_o$next[3:0]$11561 - attribute \src "libresoc.v:171942.3-171981.6" - wire width 4 $5\src16__data_o$next[3:0]$11518 - attribute \src "libresoc.v:172039.3-172078.6" - wire width 4 $5\src26__data_o$next[3:0]$11533 - attribute \src "libresoc.v:172109.3-172148.6" - wire width 4 $5\src36__data_o$next[3:0]$11547 - attribute \src "libresoc.v:172249.3-172288.6" - wire width 4 $6\r26__data_o$next[3:0]$11576 - attribute \src "libresoc.v:172179.3-172218.6" - wire width 4 $6\r6__data_o$next[3:0]$11562 - attribute \src "libresoc.v:171942.3-171981.6" - wire width 4 $6\src16__data_o$next[3:0]$11519 - attribute \src "libresoc.v:172039.3-172078.6" - wire width 4 $6\src26__data_o$next[3:0]$11534 - attribute \src "libresoc.v:172109.3-172148.6" - wire width 4 $6\src36__data_o$next[3:0]$11548 - attribute \src "libresoc.v:171925.17-171925.104" - wire $not$libresoc.v:171925$11501_Y - attribute \src "libresoc.v:171926.18-171926.105" - wire $not$libresoc.v:171926$11502_Y - attribute \src "libresoc.v:171927.17-171927.100" - wire $not$libresoc.v:171927$11503_Y - attribute \src "libresoc.v:171928.17-171928.103" - wire $not$libresoc.v:171928$11504_Y - attribute \src "libresoc.v:171929.17-171929.103" - wire $not$libresoc.v:171929$11505_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest26__wen - attribute \src "libresoc.v:171849.7-171849.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r6__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r6__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src16__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src36__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w6__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171925$11501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:171925$11501_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171926$11502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:171926$11502_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171927$11503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:171927$11503_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171928$11504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:171928$11504_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:171929$11505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:171929$11505_Y - end - attribute \src "libresoc.v:171849.7-171849.20" - process $proc$libresoc.v:171849$11583 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:171874.13-171874.31" - process $proc$libresoc.v:171874$11584 - assign { } { } - assign $1\r26__data_o[3:0] 4'0000 - sync always - sync init - update \r26__data_o $1\r26__data_o[3:0] - end - attribute \src "libresoc.v:171881.13-171881.30" - process $proc$libresoc.v:171881$11585 - assign { } { } - assign $1\r6__data_o[3:0] 4'0000 - sync always - sync init - update \r6__data_o $1\r6__data_o[3:0] - end - attribute \src "libresoc.v:171887.13-171887.25" - process $proc$libresoc.v:171887$11586 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "libresoc.v:171892.13-171892.33" - process $proc$libresoc.v:171892$11587 - assign { } { } - assign $1\src16__data_o[3:0] 4'0000 - sync always - sync init - update \src16__data_o $1\src16__data_o[3:0] - end - attribute \src "libresoc.v:171899.13-171899.33" - process $proc$libresoc.v:171899$11588 - assign { } { } - assign $1\src26__data_o[3:0] 4'0000 - sync always - sync init - update \src26__data_o $1\src26__data_o[3:0] - end - attribute \src "libresoc.v:171906.13-171906.33" - process $proc$libresoc.v:171906$11589 - assign { } { } - assign $1\src36__data_o[3:0] 4'0000 - sync always - sync init - update \src36__data_o $1\src36__data_o[3:0] - end - attribute \src "libresoc.v:171930.3-171931.25" - process $proc$libresoc.v:171930$11506 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:171932.3-171933.39" - process $proc$libresoc.v:171932$11507 - assign { } { } - assign $0\r26__data_o[3:0] \r26__data_o$next - sync posedge \coresync_clk - update \r26__data_o $0\r26__data_o[3:0] - end - attribute \src "libresoc.v:171934.3-171935.37" - process $proc$libresoc.v:171934$11508 - assign { } { } - assign $0\r6__data_o[3:0] \r6__data_o$next - sync posedge \coresync_clk - update \r6__data_o $0\r6__data_o[3:0] - end - attribute \src "libresoc.v:171936.3-171937.43" - process $proc$libresoc.v:171936$11509 - assign { } { } - assign $0\src36__data_o[3:0] \src36__data_o$next - sync posedge \coresync_clk - update \src36__data_o $0\src36__data_o[3:0] - end - attribute \src "libresoc.v:171938.3-171939.43" - process $proc$libresoc.v:171938$11510 - assign { } { } - assign $0\src26__data_o[3:0] \src26__data_o$next - sync posedge \coresync_clk - update \src26__data_o $0\src26__data_o[3:0] - end - attribute \src "libresoc.v:171940.3-171941.43" - process $proc$libresoc.v:171940$11511 - assign { } { } - assign $0\src16__data_o[3:0] \src16__data_o$next - sync posedge \coresync_clk - update \src16__data_o $0\src16__data_o[3:0] + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:171942.3-171981.6" - process $proc$libresoc.v:171942$11512 + attribute \src "libresoc.v:33365.3-33416.6" + process $proc$libresoc.v:33365$720 assign { } { } assign { } { } - assign { } { } - assign $0\src16__data_o$next[3:0]$11513 $6\src16__data_o$next[3:0]$11519 - attribute \src "libresoc.v:171943.5-171943.29" + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:33366.5-33366.29" switch \initial - attribute \src "libresoc.v:171943.9-171943.17" + attribute \src "libresoc.v:33366.9-33366.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\src16__data_o$next[3:0]$11514 $5\src16__data_o$next[3:0]$11518 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src16__data_o$next[3:0]$11515 \dest16__data_i - case - assign $2\src16__data_o$next[3:0]$11515 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src16__data_o$next[3:0]$11516 \dest26__data_i - case - assign $3\src16__data_o$next[3:0]$11516 $2\src16__data_o$next[3:0]$11515 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src16__data_o$next[3:0]$11517 \w6__data_i - case - assign $4\src16__data_o$next[3:0]$11517 $3\src16__data_o$next[3:0]$11516 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src16__data_o$next[3:0]$11518 \reg - case - assign $5\src16__data_o$next[3:0]$11518 $4\src16__data_o$next[3:0]$11517 - end - case - assign $1\src16__data_o$next[3:0]$11514 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $6\src16__data_o$next[3:0]$11519 4'0000 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 case - assign $6\src16__data_o$next[3:0]$11519 $1\src16__data_o$next[3:0]$11514 + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11513 + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:171982.3-172011.6" - process $proc$libresoc.v:171982$11520 + attribute \src "libresoc.v:33417.3-33468.6" + process $proc$libresoc.v:33417$721 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:171983.5-171983.29" + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:33418.5-33418.29" switch \initial - attribute \src "libresoc.v:171983.9-171983.17" + attribute \src "libresoc.v:33418.9-33418.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src16__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:172012.3-172038.6" - process $proc$libresoc.v:172012$11521 + attribute \src "libresoc.v:33469.3-33520.6" + process $proc$libresoc.v:33469$722 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11522 $4\reg$next[3:0]$11526 - attribute \src "libresoc.v:172013.5-172013.29" + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:33470.5-33470.29" switch \initial - attribute \src "libresoc.v:172013.9-172013.17" + attribute \src "libresoc.v:33470.9-33470.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest16__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $1\reg$next[3:0]$11523 \dest16__data_i - case - assign $1\reg$next[3:0]$11523 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest26__wen + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $2\reg$next[3:0]$11524 \dest26__data_i - case - assign $2\reg$next[3:0]$11524 $1\reg$next[3:0]$11523 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w6__wen + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10001 assign { } { } - assign $3\reg$next[3:0]$11525 \w6__data_i - case - assign $3\reg$next[3:0]$11525 $2\reg$next[3:0]$11524 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $4\reg$next[3:0]$11526 4'0000 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 case - assign $4\reg$next[3:0]$11526 $3\reg$next[3:0]$11525 + assign $1\dec31_dec_sub26_lk[0:0] 1'0 end sync always - update \reg$next $0\reg$next[3:0]$11522 + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:172039.3-172078.6" - process $proc$libresoc.v:172039$11527 + attribute \src "libresoc.v:33521.3-33572.6" + process $proc$libresoc.v:33521$723 assign { } { } assign { } { } - assign { } { } - assign $0\src26__data_o$next[3:0]$11528 $6\src26__data_o$next[3:0]$11534 - attribute \src "libresoc.v:172040.5-172040.29" + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:33522.5-33522.29" switch \initial - attribute \src "libresoc.v:172040.9-172040.17" + attribute \src "libresoc.v:33522.9-33522.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\src26__data_o$next[3:0]$11529 $5\src26__data_o$next[3:0]$11533 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src26__data_o$next[3:0]$11530 \dest16__data_i - case - assign $2\src26__data_o$next[3:0]$11530 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src26__data_o$next[3:0]$11531 \dest26__data_i - case - assign $3\src26__data_o$next[3:0]$11531 $2\src26__data_o$next[3:0]$11530 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src26__data_o$next[3:0]$11532 \w6__data_i - case - assign $4\src26__data_o$next[3:0]$11532 $3\src26__data_o$next[3:0]$11531 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src26__data_o$next[3:0]$11533 \reg - case - assign $5\src26__data_o$next[3:0]$11533 $4\src26__data_o$next[3:0]$11532 - end - case - assign $1\src26__data_o$next[3:0]$11529 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\src26__data_o$next[3:0]$11534 4'0000 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 case - assign $6\src26__data_o$next[3:0]$11534 $1\src26__data_o$next[3:0]$11529 + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11528 + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:172079.3-172108.6" - process $proc$libresoc.v:172079$11535 + attribute \src "libresoc.v:33573.3-33624.6" + process $proc$libresoc.v:33573$724 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11536 $1\wr_detect$4[0:0]$11537 - attribute \src "libresoc.v:172080.5-172080.29" + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:33574.5-33574.29" switch \initial - attribute \src "libresoc.v:172080.9-172080.17" + attribute \src "libresoc.v:33574.9-33574.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src26__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 assign { } { } - assign $1\wr_detect$4[0:0]$11537 $4\wr_detect$4[0:0]$11540 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11538 1'1 - case - assign $2\wr_detect$4[0:0]$11538 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11539 1'1 - case - assign $3\wr_detect$4[0:0]$11539 $2\wr_detect$4[0:0]$11538 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11540 1'1 - case - assign $4\wr_detect$4[0:0]$11540 $3\wr_detect$4[0:0]$11539 - end + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 case - assign $1\wr_detect$4[0:0]$11537 1'0 + assign $1\dec31_dec_sub26_form[4:0] 5'00000 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11536 + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:172109.3-172148.6" - process $proc$libresoc.v:172109$11541 + attribute \src "libresoc.v:33625.3-33676.6" + process $proc$libresoc.v:33625$725 assign { } { } assign { } { } - assign { } { } - assign $0\src36__data_o$next[3:0]$11542 $6\src36__data_o$next[3:0]$11548 - attribute \src "libresoc.v:172110.5-172110.29" + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:33626.5-33626.29" switch \initial - attribute \src "libresoc.v:172110.9-172110.17" + attribute \src "libresoc.v:33626.9-33626.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\src36__data_o$next[3:0]$11543 $5\src36__data_o$next[3:0]$11547 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src36__data_o$next[3:0]$11544 \dest16__data_i - case - assign $2\src36__data_o$next[3:0]$11544 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src36__data_o$next[3:0]$11545 \dest26__data_i - case - assign $3\src36__data_o$next[3:0]$11545 $2\src36__data_o$next[3:0]$11544 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src36__data_o$next[3:0]$11546 \w6__data_i - case - assign $4\src36__data_o$next[3:0]$11546 $3\src36__data_o$next[3:0]$11545 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src36__data_o$next[3:0]$11547 \reg - case - assign $5\src36__data_o$next[3:0]$11547 $4\src36__data_o$next[3:0]$11546 - end - case - assign $1\src36__data_o$next[3:0]$11543 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 assign { } { } - assign $6\src36__data_o$next[3:0]$11548 4'0000 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 case - assign $6\src36__data_o$next[3:0]$11548 $1\src36__data_o$next[3:0]$11543 + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11542 + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:172149.3-172178.6" - process $proc$libresoc.v:172149$11549 + attribute \src "libresoc.v:33677.3-33728.6" + process $proc$libresoc.v:33677$726 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11550 $1\wr_detect$7[0:0]$11551 - attribute \src "libresoc.v:172150.5-172150.29" + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:33678.5-33678.29" switch \initial - attribute \src "libresoc.v:172150.9-172150.17" + attribute \src "libresoc.v:33678.9-33678.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src36__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\wr_detect$7[0:0]$11551 $4\wr_detect$7[0:0]$11554 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$11552 1'1 - case - assign $2\wr_detect$7[0:0]$11552 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$11553 1'1 - case - assign $3\wr_detect$7[0:0]$11553 $2\wr_detect$7[0:0]$11552 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$11554 1'1 - case - assign $4\wr_detect$7[0:0]$11554 $3\wr_detect$7[0:0]$11553 - end + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 case - assign $1\wr_detect$7[0:0]$11551 1'0 + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11550 + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:172179.3-172218.6" - process $proc$libresoc.v:172179$11555 - assign { } { } + attribute \src "libresoc.v:33729.3-33780.6" + process $proc$libresoc.v:33729$727 assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11556 $6\r6__data_o$next[3:0]$11562 - attribute \src "libresoc.v:172180.5-172180.29" + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:33730.5-33730.29" switch \initial - attribute \src "libresoc.v:172180.9-172180.17" + attribute \src "libresoc.v:33730.9-33730.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\r6__data_o$next[3:0]$11557 $5\r6__data_o$next[3:0]$11561 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r6__data_o$next[3:0]$11558 \dest16__data_i - case - assign $2\r6__data_o$next[3:0]$11558 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r6__data_o$next[3:0]$11559 \dest26__data_i - case - assign $3\r6__data_o$next[3:0]$11559 $2\r6__data_o$next[3:0]$11558 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r6__data_o$next[3:0]$11560 \w6__data_i - case - assign $4\r6__data_o$next[3:0]$11560 $3\r6__data_o$next[3:0]$11559 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r6__data_o$next[3:0]$11561 \reg - case - assign $5\r6__data_o$next[3:0]$11561 $4\r6__data_o$next[3:0]$11560 - end - case - assign $1\r6__data_o$next[3:0]$11557 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\r6__data_o$next[3:0]$11562 4'0000 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 case - assign $6\r6__data_o$next[3:0]$11562 $1\r6__data_o$next[3:0]$11557 + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11556 + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:172219.3-172248.6" - process $proc$libresoc.v:172219$11563 + attribute \src "libresoc.v:33781.3-33832.6" + process $proc$libresoc.v:33781$728 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11564 $1\wr_detect$10[0:0]$11565 - attribute \src "libresoc.v:172220.5-172220.29" + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:33782.5-33782.29" switch \initial - attribute \src "libresoc.v:172220.9-172220.17" + attribute \src "libresoc.v:33782.9-33782.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r6__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\wr_detect$10[0:0]$11565 $4\wr_detect$10[0:0]$11568 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11566 1'1 - case - assign $2\wr_detect$10[0:0]$11566 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11567 1'1 - case - assign $3\wr_detect$10[0:0]$11567 $2\wr_detect$10[0:0]$11566 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11568 1'1 - case - assign $4\wr_detect$10[0:0]$11568 $3\wr_detect$10[0:0]$11567 - end + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 case - assign $1\wr_detect$10[0:0]$11565 1'0 + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11564 + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] end - attribute \src "libresoc.v:172249.3-172288.6" - process $proc$libresoc.v:172249$11569 - assign { } { } + attribute \src "libresoc.v:33833.3-33884.6" + process $proc$libresoc.v:33833$729 assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11570 $6\r26__data_o$next[3:0]$11576 - attribute \src "libresoc.v:172250.5-172250.29" + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:33834.5-33834.29" switch \initial - attribute \src "libresoc.v:172250.9-172250.17" + attribute \src "libresoc.v:33834.9-33834.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\r26__data_o$next[3:0]$11571 $5\r26__data_o$next[3:0]$11575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r26__data_o$next[3:0]$11572 \dest16__data_i - case - assign $2\r26__data_o$next[3:0]$11572 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r26__data_o$next[3:0]$11573 \dest26__data_i - case - assign $3\r26__data_o$next[3:0]$11573 $2\r26__data_o$next[3:0]$11572 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r26__data_o$next[3:0]$11574 \w6__data_i - case - assign $4\r26__data_o$next[3:0]$11574 $3\r26__data_o$next[3:0]$11573 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r26__data_o$next[3:0]$11575 \reg - case - assign $5\r26__data_o$next[3:0]$11575 $4\r26__data_o$next[3:0]$11574 - end - case - assign $1\r26__data_o$next[3:0]$11571 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $6\r26__data_o$next[3:0]$11576 4'0000 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 case - assign $6\r26__data_o$next[3:0]$11576 $1\r26__data_o$next[3:0]$11571 + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11570 + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:172289.3-172318.6" - process $proc$libresoc.v:172289$11577 + attribute \src "libresoc.v:33885.3-33936.6" + process $proc$libresoc.v:33885$730 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11578 $1\wr_detect$13[0:0]$11579 - attribute \src "libresoc.v:172290.5-172290.29" + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:33886.5-33886.29" switch \initial - attribute \src "libresoc.v:172290.9-172290.17" + attribute \src "libresoc.v:33886.9-33886.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r26__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\wr_detect$13[0:0]$11579 $4\wr_detect$13[0:0]$11582 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest16__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$11580 1'1 - case - assign $2\wr_detect$13[0:0]$11580 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest26__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$11581 1'1 - case - assign $3\wr_detect$13[0:0]$11581 $2\wr_detect$13[0:0]$11580 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w6__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$11582 1'1 - case - assign $4\wr_detect$13[0:0]$11582 $3\wr_detect$13[0:0]$11581 - end + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 case - assign $1\wr_detect$13[0:0]$11579 1'0 + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11578 + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - connect \$9 $not$libresoc.v:171925$11501_Y - connect \$12 $not$libresoc.v:171926$11502_Y - connect \$1 $not$libresoc.v:171927$11503_Y - connect \$3 $not$libresoc.v:171928$11504_Y - connect \$6 $not$libresoc.v:171929$11505_Y + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:172323.1-172794.10" +attribute \src "libresoc.v:33942.1-34657.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" -module \reg_7 - attribute \src "libresoc.v:172324.7-172324.20" +module \dec31_dec_sub27 + attribute \src "libresoc.v:34295.3-34313.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34371.3-34389.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34618.3-34636.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34637.3-34655.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34276.3-34294.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34352.3-34370.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34523.3-34541.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34200.3-34218.6" + wire width 12 $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34542.3-34560.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34561.3-34579.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34580.3-34598.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34409.3-34427.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34314.3-34332.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34333.3-34351.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34447.3-34465.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34219.3-34237.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34485.3-34503.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34599.3-34617.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34257.3-34275.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34428.3-34446.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34504.3-34522.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34466.3-34484.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34390.3-34408.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34238.3-34256.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:33943.7-33943.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172724.3-172763.6" - wire width 4 $0\r27__data_o$next[3:0]$11659 - attribute \src "libresoc.v:172407.3-172408.39" - wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:172654.3-172693.6" - wire width 4 $0\r7__data_o$next[3:0]$11645 - attribute \src "libresoc.v:172409.3-172410.37" - wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:172487.3-172513.6" - wire width 4 $0\reg$next[3:0]$11611 - attribute \src "libresoc.v:172405.3-172406.25" - wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:172417.3-172456.6" - wire width 4 $0\src17__data_o$next[3:0]$11602 - attribute \src "libresoc.v:172415.3-172416.43" - wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:172514.3-172553.6" - wire width 4 $0\src27__data_o$next[3:0]$11617 - attribute \src "libresoc.v:172413.3-172414.43" - wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:172584.3-172623.6" - wire width 4 $0\src37__data_o$next[3:0]$11631 - attribute \src "libresoc.v:172411.3-172412.43" - wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:172694.3-172723.6" - wire $0\wr_detect$10[0:0]$11653 - attribute \src "libresoc.v:172764.3-172793.6" - wire $0\wr_detect$13[0:0]$11667 - attribute \src "libresoc.v:172554.3-172583.6" - wire $0\wr_detect$4[0:0]$11625 - attribute \src "libresoc.v:172624.3-172653.6" - wire $0\wr_detect$7[0:0]$11639 - attribute \src "libresoc.v:172457.3-172486.6" - wire $0\wr_detect[0:0] - attribute \src "libresoc.v:172724.3-172763.6" - wire width 4 $1\r27__data_o$next[3:0]$11660 - attribute \src "libresoc.v:172349.13-172349.31" - wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:172654.3-172693.6" - wire width 4 $1\r7__data_o$next[3:0]$11646 - attribute \src "libresoc.v:172356.13-172356.30" - wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:172487.3-172513.6" - wire width 4 $1\reg$next[3:0]$11612 - attribute \src "libresoc.v:172362.13-172362.25" - wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:172417.3-172456.6" - wire width 4 $1\src17__data_o$next[3:0]$11603 - attribute \src "libresoc.v:172367.13-172367.33" - wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:172514.3-172553.6" - wire width 4 $1\src27__data_o$next[3:0]$11618 - attribute \src "libresoc.v:172374.13-172374.33" - wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:172584.3-172623.6" - wire width 4 $1\src37__data_o$next[3:0]$11632 - attribute \src "libresoc.v:172381.13-172381.33" - wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:172694.3-172723.6" - wire $1\wr_detect$10[0:0]$11654 - attribute \src "libresoc.v:172764.3-172793.6" - wire $1\wr_detect$13[0:0]$11668 - attribute \src "libresoc.v:172554.3-172583.6" - wire $1\wr_detect$4[0:0]$11626 - attribute \src "libresoc.v:172624.3-172653.6" - wire $1\wr_detect$7[0:0]$11640 - attribute \src "libresoc.v:172457.3-172486.6" - wire $1\wr_detect[0:0] - attribute \src "libresoc.v:172724.3-172763.6" - wire width 4 $2\r27__data_o$next[3:0]$11661 - attribute \src "libresoc.v:172654.3-172693.6" - wire width 4 $2\r7__data_o$next[3:0]$11647 - attribute \src "libresoc.v:172487.3-172513.6" - wire width 4 $2\reg$next[3:0]$11613 - attribute \src "libresoc.v:172417.3-172456.6" - wire width 4 $2\src17__data_o$next[3:0]$11604 - attribute \src "libresoc.v:172514.3-172553.6" - wire width 4 $2\src27__data_o$next[3:0]$11619 - attribute \src "libresoc.v:172584.3-172623.6" - wire width 4 $2\src37__data_o$next[3:0]$11633 - attribute \src "libresoc.v:172694.3-172723.6" - wire $2\wr_detect$10[0:0]$11655 - attribute \src "libresoc.v:172764.3-172793.6" - wire $2\wr_detect$13[0:0]$11669 - attribute \src "libresoc.v:172554.3-172583.6" - wire $2\wr_detect$4[0:0]$11627 - attribute \src "libresoc.v:172624.3-172653.6" - wire $2\wr_detect$7[0:0]$11641 - attribute \src "libresoc.v:172457.3-172486.6" - wire $2\wr_detect[0:0] - attribute \src "libresoc.v:172724.3-172763.6" - wire width 4 $3\r27__data_o$next[3:0]$11662 - attribute \src "libresoc.v:172654.3-172693.6" - wire width 4 $3\r7__data_o$next[3:0]$11648 - attribute \src "libresoc.v:172487.3-172513.6" - wire width 4 $3\reg$next[3:0]$11614 - attribute \src "libresoc.v:172417.3-172456.6" - wire width 4 $3\src17__data_o$next[3:0]$11605 - attribute \src "libresoc.v:172514.3-172553.6" - wire width 4 $3\src27__data_o$next[3:0]$11620 - attribute \src "libresoc.v:172584.3-172623.6" - wire width 4 $3\src37__data_o$next[3:0]$11634 - attribute \src "libresoc.v:172694.3-172723.6" - wire $3\wr_detect$10[0:0]$11656 - attribute \src "libresoc.v:172764.3-172793.6" - wire $3\wr_detect$13[0:0]$11670 - attribute \src "libresoc.v:172554.3-172583.6" - wire $3\wr_detect$4[0:0]$11628 - attribute \src "libresoc.v:172624.3-172653.6" - wire $3\wr_detect$7[0:0]$11642 - attribute \src "libresoc.v:172457.3-172486.6" - wire $3\wr_detect[0:0] - attribute \src "libresoc.v:172724.3-172763.6" - wire width 4 $4\r27__data_o$next[3:0]$11663 - attribute \src "libresoc.v:172654.3-172693.6" - wire width 4 $4\r7__data_o$next[3:0]$11649 - attribute \src "libresoc.v:172487.3-172513.6" - wire width 4 $4\reg$next[3:0]$11615 - attribute \src "libresoc.v:172417.3-172456.6" - wire width 4 $4\src17__data_o$next[3:0]$11606 - attribute \src "libresoc.v:172514.3-172553.6" - wire width 4 $4\src27__data_o$next[3:0]$11621 - attribute \src "libresoc.v:172584.3-172623.6" - wire width 4 $4\src37__data_o$next[3:0]$11635 - attribute \src "libresoc.v:172694.3-172723.6" - wire $4\wr_detect$10[0:0]$11657 - attribute \src "libresoc.v:172764.3-172793.6" - wire $4\wr_detect$13[0:0]$11671 - attribute \src "libresoc.v:172554.3-172583.6" - wire $4\wr_detect$4[0:0]$11629 - attribute \src "libresoc.v:172624.3-172653.6" - wire $4\wr_detect$7[0:0]$11643 - attribute \src "libresoc.v:172457.3-172486.6" - wire $4\wr_detect[0:0] - attribute \src "libresoc.v:172724.3-172763.6" - wire width 4 $5\r27__data_o$next[3:0]$11664 - attribute \src "libresoc.v:172654.3-172693.6" - wire width 4 $5\r7__data_o$next[3:0]$11650 - attribute \src "libresoc.v:172417.3-172456.6" - wire width 4 $5\src17__data_o$next[3:0]$11607 - attribute \src "libresoc.v:172514.3-172553.6" - wire width 4 $5\src27__data_o$next[3:0]$11622 - attribute \src "libresoc.v:172584.3-172623.6" - wire width 4 $5\src37__data_o$next[3:0]$11636 - attribute \src "libresoc.v:172724.3-172763.6" - wire width 4 $6\r27__data_o$next[3:0]$11665 - attribute \src "libresoc.v:172654.3-172693.6" - wire width 4 $6\r7__data_o$next[3:0]$11651 - attribute \src "libresoc.v:172417.3-172456.6" - wire width 4 $6\src17__data_o$next[3:0]$11608 - attribute \src "libresoc.v:172514.3-172553.6" - wire width 4 $6\src27__data_o$next[3:0]$11623 - attribute \src "libresoc.v:172584.3-172623.6" - wire width 4 $6\src37__data_o$next[3:0]$11637 - attribute \src "libresoc.v:172400.17-172400.104" - wire $not$libresoc.v:172400$11590_Y - attribute \src "libresoc.v:172401.18-172401.105" - wire $not$libresoc.v:172401$11591_Y - attribute \src "libresoc.v:172402.17-172402.100" - wire $not$libresoc.v:172402$11592_Y - attribute \src "libresoc.v:172403.17-172403.103" - wire $not$libresoc.v:172403$11593_Y - attribute \src "libresoc.v:172404.17-172404.103" - wire $not$libresoc.v:172404$11594_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 8 \dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 10 \dest27__wen - attribute \src "libresoc.v:172324.7-172324.15" + attribute \src "libresoc.v:34295.3-34313.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34371.3-34389.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34618.3-34636.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34637.3-34655.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34276.3-34294.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34352.3-34370.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34523.3-34541.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34200.3-34218.6" + wire width 12 $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34542.3-34560.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34561.3-34579.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34580.3-34598.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34409.3-34427.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:34314.3-34332.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34333.3-34351.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34447.3-34465.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34219.3-34237.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34485.3-34503.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34599.3-34617.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34257.3-34275.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34428.3-34446.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34504.3-34522.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34466.3-34484.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34390.3-34408.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34238.3-34256.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub27_upd + attribute \src "libresoc.v:33943.7-33943.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 15 \r27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r7__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 13 \r7__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src17__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 2 \src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src37__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 6 \src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 17 \w7__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172400$11590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $not$libresoc.v:172400$11590_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172401$11591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $not$libresoc.v:172401$11591_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172402$11592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $not$libresoc.v:172402$11592_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172403$11593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $not$libresoc.v:172403$11593_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:172404$11594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $not$libresoc.v:172404$11594_Y - end - attribute \src "libresoc.v:172324.7-172324.20" - process $proc$libresoc.v:172324$11672 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:33943.7-33943.20" + process $proc$libresoc.v:33943$756 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172349.13-172349.31" - process $proc$libresoc.v:172349$11673 - assign { } { } - assign $1\r27__data_o[3:0] 4'0000 - sync always - sync init - update \r27__data_o $1\r27__data_o[3:0] - end - attribute \src "libresoc.v:172356.13-172356.30" - process $proc$libresoc.v:172356$11674 - assign { } { } - assign $1\r7__data_o[3:0] 4'0000 - sync always - sync init - update \r7__data_o $1\r7__data_o[3:0] - end - attribute \src "libresoc.v:172362.13-172362.25" - process $proc$libresoc.v:172362$11675 - assign { } { } - assign $1\reg[3:0] 4'0000 - sync always - sync init - update \reg $1\reg[3:0] - end - attribute \src "libresoc.v:172367.13-172367.33" - process $proc$libresoc.v:172367$11676 - assign { } { } - assign $1\src17__data_o[3:0] 4'0000 - sync always - sync init - update \src17__data_o $1\src17__data_o[3:0] - end - attribute \src "libresoc.v:172374.13-172374.33" - process $proc$libresoc.v:172374$11677 - assign { } { } - assign $1\src27__data_o[3:0] 4'0000 - sync always - sync init - update \src27__data_o $1\src27__data_o[3:0] - end - attribute \src "libresoc.v:172381.13-172381.33" - process $proc$libresoc.v:172381$11678 - assign { } { } - assign $1\src37__data_o[3:0] 4'0000 - sync always - sync init - update \src37__data_o $1\src37__data_o[3:0] - end - attribute \src "libresoc.v:172405.3-172406.25" - process $proc$libresoc.v:172405$11595 - assign { } { } - assign $0\reg[3:0] \reg$next - sync posedge \coresync_clk - update \reg $0\reg[3:0] - end - attribute \src "libresoc.v:172407.3-172408.39" - process $proc$libresoc.v:172407$11596 - assign { } { } - assign $0\r27__data_o[3:0] \r27__data_o$next - sync posedge \coresync_clk - update \r27__data_o $0\r27__data_o[3:0] - end - attribute \src "libresoc.v:172409.3-172410.37" - process $proc$libresoc.v:172409$11597 - assign { } { } - assign $0\r7__data_o[3:0] \r7__data_o$next - sync posedge \coresync_clk - update \r7__data_o $0\r7__data_o[3:0] - end - attribute \src "libresoc.v:172411.3-172412.43" - process $proc$libresoc.v:172411$11598 - assign { } { } - assign $0\src37__data_o[3:0] \src37__data_o$next - sync posedge \coresync_clk - update \src37__data_o $0\src37__data_o[3:0] - end - attribute \src "libresoc.v:172413.3-172414.43" - process $proc$libresoc.v:172413$11599 - assign { } { } - assign $0\src27__data_o[3:0] \src27__data_o$next - sync posedge \coresync_clk - update \src27__data_o $0\src27__data_o[3:0] - end - attribute \src "libresoc.v:172415.3-172416.43" - process $proc$libresoc.v:172415$11600 - assign { } { } - assign $0\src17__data_o[3:0] \src17__data_o$next - sync posedge \coresync_clk - update \src17__data_o $0\src17__data_o[3:0] - end - attribute \src "libresoc.v:172417.3-172456.6" - process $proc$libresoc.v:172417$11601 - assign { } { } + attribute \src "libresoc.v:34200.3-34218.6" + process $proc$libresoc.v:34200$732 assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11602 $6\src17__data_o$next[3:0]$11608 - attribute \src "libresoc.v:172418.5-172418.29" + assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "libresoc.v:34201.5-34201.29" switch \initial - attribute \src "libresoc.v:172418.9-172418.17" + attribute \src "libresoc.v:34201.9-34201.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\src17__data_o$next[3:0]$11603 $5\src17__data_o$next[3:0]$11607 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src17__data_o$next[3:0]$11604 \dest17__data_i - case - assign $2\src17__data_o$next[3:0]$11604 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src17__data_o$next[3:0]$11605 \dest27__data_i - case - assign $3\src17__data_o$next[3:0]$11605 $2\src17__data_o$next[3:0]$11604 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src17__data_o$next[3:0]$11606 \w7__data_i - case - assign $4\src17__data_o$next[3:0]$11606 $3\src17__data_o$next[3:0]$11605 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$1 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src17__data_o$next[3:0]$11607 \reg - case - assign $5\src17__data_o$next[3:0]$11607 $4\src17__data_o$next[3:0]$11606 - end - case - assign $1\src17__data_o$next[3:0]$11603 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\src17__data_o$next[3:0]$11608 4'0000 + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 case - assign $6\src17__data_o$next[3:0]$11608 $1\src17__data_o$next[3:0]$11603 + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11602 + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] end - attribute \src "libresoc.v:172457.3-172486.6" - process $proc$libresoc.v:172457$11609 + attribute \src "libresoc.v:34219.3-34237.6" + process $proc$libresoc.v:34219$733 assign { } { } assign { } { } - assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:172458.5-172458.29" + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:34220.5-34220.29" switch \initial - attribute \src "libresoc.v:172458.9-172458.17" + attribute \src "libresoc.v:34220.9-34220.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src17__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect[0:0] $4\wr_detect[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect[0:0] 1'1 - case - assign $2\wr_detect[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect[0:0] 1'1 - case - assign $3\wr_detect[0:0] $2\wr_detect[0:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect[0:0] 1'1 - case - assign $4\wr_detect[0:0] $3\wr_detect[0:0] - end + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 case - assign $1\wr_detect[0:0] 1'0 + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 end sync always - update \wr_detect $0\wr_detect[0:0] + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:172487.3-172513.6" - process $proc$libresoc.v:172487$11610 - assign { } { } + attribute \src "libresoc.v:34238.3-34256.6" + process $proc$libresoc.v:34238$734 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\reg$next[3:0]$11611 $4\reg$next[3:0]$11615 - attribute \src "libresoc.v:172488.5-172488.29" + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:34239.5-34239.29" switch \initial - attribute \src "libresoc.v:172488.9-172488.17" + attribute \src "libresoc.v:34239.9-34239.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest17__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 assign { } { } - assign $1\reg$next[3:0]$11612 \dest17__data_i - case - assign $1\reg$next[3:0]$11612 \reg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \dest27__wen + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $2\reg$next[3:0]$11613 \dest27__data_i - case - assign $2\reg$next[3:0]$11613 $1\reg$next[3:0]$11612 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch \w7__wen + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $3\reg$next[3:0]$11614 \w7__data_i - case - assign $3\reg$next[3:0]$11614 $2\reg$next[3:0]$11613 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $4\reg$next[3:0]$11615 4'0000 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 case - assign $4\reg$next[3:0]$11615 $3\reg$next[3:0]$11614 + assign $1\dec31_dec_sub27_upd[1:0] 2'00 end sync always - update \reg$next $0\reg$next[3:0]$11611 + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:172514.3-172553.6" - process $proc$libresoc.v:172514$11616 - assign { } { } + attribute \src "libresoc.v:34257.3-34275.6" + process $proc$libresoc.v:34257$735 assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11617 $6\src27__data_o$next[3:0]$11623 - attribute \src "libresoc.v:172515.5-172515.29" + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:34258.5-34258.29" switch \initial - attribute \src "libresoc.v:172515.9-172515.17" + attribute \src "libresoc.v:34258.9-34258.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\src27__data_o$next[3:0]$11618 $5\src27__data_o$next[3:0]$11622 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src27__data_o$next[3:0]$11619 \dest17__data_i - case - assign $2\src27__data_o$next[3:0]$11619 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src27__data_o$next[3:0]$11620 \dest27__data_i - case - assign $3\src27__data_o$next[3:0]$11620 $2\src27__data_o$next[3:0]$11619 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src27__data_o$next[3:0]$11621 \w7__data_i - case - assign $4\src27__data_o$next[3:0]$11621 $3\src27__data_o$next[3:0]$11620 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$3 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src27__data_o$next[3:0]$11622 \reg - case - assign $5\src27__data_o$next[3:0]$11622 $4\src27__data_o$next[3:0]$11621 - end - case - assign $1\src27__data_o$next[3:0]$11618 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\src27__data_o$next[3:0]$11623 4'0000 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 case - assign $6\src27__data_o$next[3:0]$11623 $1\src27__data_o$next[3:0]$11618 + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11617 + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:172554.3-172583.6" - process $proc$libresoc.v:172554$11624 + attribute \src "libresoc.v:34276.3-34294.6" + process $proc$libresoc.v:34276$736 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11625 $1\wr_detect$4[0:0]$11626 - attribute \src "libresoc.v:172555.5-172555.29" + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:34277.5-34277.29" switch \initial - attribute \src "libresoc.v:172555.9-172555.17" + attribute \src "libresoc.v:34277.9-34277.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src27__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$4[0:0]$11626 $4\wr_detect$4[0:0]$11629 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$4[0:0]$11627 1'1 - case - assign $2\wr_detect$4[0:0]$11627 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$4[0:0]$11628 1'1 - case - assign $3\wr_detect$4[0:0]$11628 $2\wr_detect$4[0:0]$11627 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$4[0:0]$11629 1'1 - case - assign $4\wr_detect$4[0:0]$11629 $3\wr_detect$4[0:0]$11628 - end + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 case - assign $1\wr_detect$4[0:0]$11626 1'0 + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11625 + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:172584.3-172623.6" - process $proc$libresoc.v:172584$11630 - assign { } { } + attribute \src "libresoc.v:34295.3-34313.6" + process $proc$libresoc.v:34295$737 assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11631 $6\src37__data_o$next[3:0]$11637 - attribute \src "libresoc.v:172585.5-172585.29" + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:34296.5-34296.29" switch \initial - attribute \src "libresoc.v:172585.9-172585.17" + attribute \src "libresoc.v:34296.9-34296.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\src37__data_o$next[3:0]$11632 $5\src37__data_o$next[3:0]$11636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\src37__data_o$next[3:0]$11633 \dest17__data_i - case - assign $2\src37__data_o$next[3:0]$11633 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\src37__data_o$next[3:0]$11634 \dest27__data_i - case - assign $3\src37__data_o$next[3:0]$11634 $2\src37__data_o$next[3:0]$11633 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\src37__data_o$next[3:0]$11635 \w7__data_i - case - assign $4\src37__data_o$next[3:0]$11635 $3\src37__data_o$next[3:0]$11634 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$6 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\src37__data_o$next[3:0]$11636 \reg - case - assign $5\src37__data_o$next[3:0]$11636 $4\src37__data_o$next[3:0]$11635 - end - case - assign $1\src37__data_o$next[3:0]$11632 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\src37__data_o$next[3:0]$11637 4'0000 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 case - assign $6\src37__data_o$next[3:0]$11637 $1\src37__data_o$next[3:0]$11632 + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11631 + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:172624.3-172653.6" - process $proc$libresoc.v:172624$11638 + attribute \src "libresoc.v:34314.3-34332.6" + process $proc$libresoc.v:34314$738 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11639 $1\wr_detect$7[0:0]$11640 - attribute \src "libresoc.v:172625.5-172625.29" + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:34315.5-34315.29" switch \initial - attribute \src "libresoc.v:172625.9-172625.17" + attribute \src "libresoc.v:34315.9-34315.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \src37__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$7[0:0]$11640 $4\wr_detect$7[0:0]$11643 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$7[0:0]$11641 1'1 - case - assign $2\wr_detect$7[0:0]$11641 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$7[0:0]$11642 1'1 - case - assign $3\wr_detect$7[0:0]$11642 $2\wr_detect$7[0:0]$11641 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$7[0:0]$11643 1'1 - case - assign $4\wr_detect$7[0:0]$11643 $3\wr_detect$7[0:0]$11642 - end + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 case - assign $1\wr_detect$7[0:0]$11640 1'0 + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11639 + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:172654.3-172693.6" - process $proc$libresoc.v:172654$11644 + attribute \src "libresoc.v:34333.3-34351.6" + process $proc$libresoc.v:34333$739 assign { } { } assign { } { } - assign { } { } - assign $0\r7__data_o$next[3:0]$11645 $6\r7__data_o$next[3:0]$11651 - attribute \src "libresoc.v:172655.5-172655.29" + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:34334.5-34334.29" switch \initial - attribute \src "libresoc.v:172655.9-172655.17" + attribute \src "libresoc.v:34334.9-34334.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\r7__data_o$next[3:0]$11646 $5\r7__data_o$next[3:0]$11650 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r7__data_o$next[3:0]$11647 \dest17__data_i - case - assign $2\r7__data_o$next[3:0]$11647 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r7__data_o$next[3:0]$11648 \dest27__data_i - case - assign $3\r7__data_o$next[3:0]$11648 $2\r7__data_o$next[3:0]$11647 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r7__data_o$next[3:0]$11649 \w7__data_i - case - assign $4\r7__data_o$next[3:0]$11649 $3\r7__data_o$next[3:0]$11648 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r7__data_o$next[3:0]$11650 \reg - case - assign $5\r7__data_o$next[3:0]$11650 $4\r7__data_o$next[3:0]$11649 - end - case - assign $1\r7__data_o$next[3:0]$11646 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\r7__data_o$next[3:0]$11651 4'0000 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 case - assign $6\r7__data_o$next[3:0]$11651 $1\r7__data_o$next[3:0]$11646 + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11645 + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:172694.3-172723.6" - process $proc$libresoc.v:172694$11652 + attribute \src "libresoc.v:34352.3-34370.6" + process $proc$libresoc.v:34352$740 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11653 $1\wr_detect$10[0:0]$11654 - attribute \src "libresoc.v:172695.5-172695.29" + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:34353.5-34353.29" switch \initial - attribute \src "libresoc.v:172695.9-172695.17" + attribute \src "libresoc.v:34353.9-34353.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r7__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\wr_detect$10[0:0]$11654 $4\wr_detect$10[0:0]$11657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$10[0:0]$11655 1'1 - case - assign $2\wr_detect$10[0:0]$11655 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$10[0:0]$11656 1'1 - case - assign $3\wr_detect$10[0:0]$11656 $2\wr_detect$10[0:0]$11655 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$10[0:0]$11657 1'1 - case - assign $4\wr_detect$10[0:0]$11657 $3\wr_detect$10[0:0]$11656 - end + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 case - assign $1\wr_detect$10[0:0]$11654 1'0 + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11653 + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:172724.3-172763.6" - process $proc$libresoc.v:172724$11658 + attribute \src "libresoc.v:34371.3-34389.6" + process $proc$libresoc.v:34371$741 assign { } { } assign { } { } - assign { } { } - assign $0\r27__data_o$next[3:0]$11659 $6\r27__data_o$next[3:0]$11665 - attribute \src "libresoc.v:172725.5-172725.29" + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:34372.5-34372.29" switch \initial - attribute \src "libresoc.v:172725.9-172725.17" + attribute \src "libresoc.v:34372.9-34372.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\r27__data_o$next[3:0]$11660 $5\r27__data_o$next[3:0]$11664 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\r27__data_o$next[3:0]$11661 \dest17__data_i - case - assign $2\r27__data_o$next[3:0]$11661 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\r27__data_o$next[3:0]$11662 \dest27__data_i - case - assign $3\r27__data_o$next[3:0]$11662 $2\r27__data_o$next[3:0]$11661 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\r27__data_o$next[3:0]$11663 \w7__data_i - case - assign $4\r27__data_o$next[3:0]$11663 $3\r27__data_o$next[3:0]$11662 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $5\r27__data_o$next[3:0]$11664 \reg - case - assign $5\r27__data_o$next[3:0]$11664 $4\r27__data_o$next[3:0]$11663 - end - case - assign $1\r27__data_o$next[3:0]$11660 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $6\r27__data_o$next[3:0]$11665 4'0000 + assign $1\dec31_dec_sub27_br[0:0] 1'0 case - assign $6\r27__data_o$next[3:0]$11665 $1\r27__data_o$next[3:0]$11660 + assign $1\dec31_dec_sub27_br[0:0] 1'0 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11659 + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:172764.3-172793.6" - process $proc$libresoc.v:172764$11666 + attribute \src "libresoc.v:34390.3-34408.6" + process $proc$libresoc.v:34390$742 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11667 $1\wr_detect$13[0:0]$11668 - attribute \src "libresoc.v:172765.5-172765.29" + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:34391.5-34391.29" switch \initial - attribute \src "libresoc.v:172765.9-172765.17" + attribute \src "libresoc.v:34391.9-34391.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch \r27__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } + case 5'11011 assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 assign { } { } - assign $1\wr_detect$13[0:0]$11668 $4\wr_detect$13[0:0]$11671 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest17__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\wr_detect$13[0:0]$11669 1'1 - case - assign $2\wr_detect$13[0:0]$11669 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \dest27__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\wr_detect$13[0:0]$11670 1'1 - case - assign $3\wr_detect$13[0:0]$11670 $2\wr_detect$13[0:0]$11669 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch \w7__wen - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\wr_detect$13[0:0]$11671 1'1 - case - assign $4\wr_detect$13[0:0]$11671 $3\wr_detect$13[0:0]$11670 - end - case - assign $1\wr_detect$13[0:0]$11668 1'0 - end - sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11667 - end - connect \$9 $not$libresoc.v:172400$11590_Y - connect \$12 $not$libresoc.v:172401$11591_Y - connect \$1 $not$libresoc.v:172402$11592_Y - connect \$3 $not$libresoc.v:172403$11593_Y - connect \$6 $not$libresoc.v:172404$11594_Y -end -attribute \src "libresoc.v:172798.1-172856.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" -attribute \generator "nMigen" -module \req_l - attribute \src "libresoc.v:172799.7-172799.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:172844.3-172852.6" - wire width 5 $0\q_int$next[4:0]$11689 - attribute \src "libresoc.v:172842.3-172843.27" - wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:172844.3-172852.6" - wire width 5 $1\q_int$next[4:0]$11690 - attribute \src "libresoc.v:172821.13-172821.26" - wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:172834.17-172834.96" - wire width 5 $and$libresoc.v:172834$11679_Y - attribute \src "libresoc.v:172839.17-172839.96" - wire width 5 $and$libresoc.v:172839$11684_Y - attribute \src "libresoc.v:172836.18-172836.93" - wire width 5 $not$libresoc.v:172836$11681_Y - attribute \src "libresoc.v:172838.17-172838.92" - wire width 5 $not$libresoc.v:172838$11683_Y - attribute \src "libresoc.v:172841.17-172841.92" - wire width 5 $not$libresoc.v:172841$11686_Y - attribute \src "libresoc.v:172835.18-172835.98" - wire width 5 $or$libresoc.v:172835$11680_Y - attribute \src "libresoc.v:172837.18-172837.99" - wire width 5 $or$libresoc.v:172837$11682_Y - attribute \src "libresoc.v:172840.17-172840.97" - wire width 5 $or$libresoc.v:172840$11685_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:172799.7-172799.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 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wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:172958$11707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:172958$11707_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:172963$11712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:172963$11712_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:172960$11709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $not$libresoc.v:172960$11709_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:172962$11711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$libresoc.v:172962$11711_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:172965$11714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$libresoc.v:172965$11714_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:172959$11708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_req - connect \Y $or$libresoc.v:172959$11708_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:172961$11710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $or$libresoc.v:172961$11710_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:172964$11713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_req - connect \Y $or$libresoc.v:172964$11713_Y - end - attribute \src "libresoc.v:172923.7-172923.20" - process $proc$libresoc.v:172923$11719 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:172945.13-172945.25" - process $proc$libresoc.v:172945$11720 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "libresoc.v:172966.3-172967.27" - process $proc$libresoc.v:172966$11715 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "libresoc.v:172968.3-172976.6" - process $proc$libresoc.v:172968$11716 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$11717 $1\q_int$next[2:0]$11718 - attribute \src "libresoc.v:172969.5-172969.29" - switch \initial - attribute \src "libresoc.v:172969.9-172969.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $1\q_int$next[2:0]$11718 3'000 - case - assign $1\q_int$next[2:0]$11718 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$11717 - end - connect \$9 $and$libresoc.v:172958$11707_Y - connect \$11 $or$libresoc.v:172959$11708_Y - connect \$13 $not$libresoc.v:172960$11709_Y - connect \$15 $or$libresoc.v:172961$11710_Y - connect \$1 $not$libresoc.v:172962$11711_Y - connect \$3 $and$libresoc.v:172963$11712_Y - connect \$5 $or$libresoc.v:172964$11713_Y - connect \$7 $not$libresoc.v:172965$11714_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "libresoc.v:172984.1-173042.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" -attribute \generator "nMigen" -module \req_l$121 - attribute \src "libresoc.v:172985.7-172985.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173030.3-173038.6" - wire width 3 $0\q_int$next[2:0]$11731 - attribute \src "libresoc.v:173028.3-173029.27" - wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:173030.3-173038.6" - wire width 3 $1\q_int$next[2:0]$11732 - attribute \src "libresoc.v:173007.13-173007.25" - wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:173020.17-173020.96" - wire width 3 $and$libresoc.v:173020$11721_Y - attribute \src "libresoc.v:173025.17-173025.96" - wire width 3 $and$libresoc.v:173025$11726_Y - attribute \src "libresoc.v:173022.18-173022.93" - wire width 3 $not$libresoc.v:173022$11723_Y - attribute \src "libresoc.v:173024.17-173024.92" - wire width 3 $not$libresoc.v:173024$11725_Y - attribute \src "libresoc.v:173027.17-173027.92" - wire width 3 $not$libresoc.v:173027$11728_Y - attribute \src "libresoc.v:173021.18-173021.98" - wire width 3 $or$libresoc.v:173021$11722_Y - attribute \src "libresoc.v:173023.18-173023.99" - wire width 3 $or$libresoc.v:173023$11724_Y - attribute \src "libresoc.v:173026.17-173026.97" - wire width 3 $or$libresoc.v:173026$11727_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:172985.7-172985.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173020$11721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:173020$11721_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173025$11726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173025$11726_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173022$11723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $not$libresoc.v:173022$11723_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173024$11725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$libresoc.v:173024$11725_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173027$11728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$libresoc.v:173027$11728_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173021$11722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_req - connect \Y $or$libresoc.v:173021$11722_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173023$11724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $or$libresoc.v:173023$11724_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173026$11727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_req - connect \Y $or$libresoc.v:173026$11727_Y - end - attribute \src "libresoc.v:172985.7-172985.20" - process $proc$libresoc.v:172985$11733 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173007.13-173007.25" - process $proc$libresoc.v:173007$11734 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "libresoc.v:173028.3-173029.27" - process $proc$libresoc.v:173028$11729 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "libresoc.v:173030.3-173038.6" - process $proc$libresoc.v:173030$11730 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$11731 $1\q_int$next[2:0]$11732 - attribute \src "libresoc.v:173031.5-173031.29" - switch \initial - attribute \src "libresoc.v:173031.9-173031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $1\q_int$next[2:0]$11732 3'000 - case - assign $1\q_int$next[2:0]$11732 \$5 - end - sync always - update \q_int$next $0\q_int$next[2:0]$11731 - end - connect \$9 $and$libresoc.v:173020$11721_Y - connect \$11 $or$libresoc.v:173021$11722_Y - connect \$13 $not$libresoc.v:173022$11723_Y - connect \$15 $or$libresoc.v:173023$11724_Y - connect \$1 $not$libresoc.v:173024$11725_Y - connect \$3 $and$libresoc.v:173025$11726_Y - connect \$5 $or$libresoc.v:173026$11727_Y - connect \$7 $not$libresoc.v:173027$11728_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "libresoc.v:173046.1-173104.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" -attribute \generator "nMigen" -module \req_l$25 - attribute \src "libresoc.v:173047.7-173047.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173092.3-173100.6" - wire width 3 $0\q_int$next[2:0]$11745 - attribute \src "libresoc.v:173090.3-173091.27" - wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:173092.3-173100.6" - wire width 3 $1\q_int$next[2:0]$11746 - attribute \src "libresoc.v:173069.13-173069.25" - wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:173082.17-173082.96" - wire width 3 $and$libresoc.v:173082$11735_Y - attribute \src "libresoc.v:173087.17-173087.96" - wire width 3 $and$libresoc.v:173087$11740_Y - attribute \src "libresoc.v:173084.18-173084.93" - wire width 3 $not$libresoc.v:173084$11737_Y - attribute \src "libresoc.v:173086.17-173086.92" - wire width 3 $not$libresoc.v:173086$11739_Y - attribute \src "libresoc.v:173089.17-173089.92" - wire width 3 $not$libresoc.v:173089$11742_Y - attribute \src "libresoc.v:173083.18-173083.98" - wire width 3 $or$libresoc.v:173083$11736_Y - attribute \src "libresoc.v:173085.18-173085.99" - wire width 3 $or$libresoc.v:173085$11738_Y - attribute \src "libresoc.v:173088.17-173088.97" - wire width 3 $or$libresoc.v:173088$11741_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:173047.7-173047.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173082$11735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:173082$11735_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173087$11740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173087$11740_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173084$11737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $not$libresoc.v:173084$11737_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173086$11739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$libresoc.v:173086$11739_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173089$11742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $not$libresoc.v:173089$11742_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173083$11736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_req - connect \Y $or$libresoc.v:173083$11736_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173085$11738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $or$libresoc.v:173085$11738_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173088$11741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_req - connect \Y $or$libresoc.v:173088$11741_Y - end - attribute \src "libresoc.v:173047.7-173047.20" - process $proc$libresoc.v:173047$11747 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173069.13-173069.25" - process $proc$libresoc.v:173069$11748 - assign { } { } - assign $1\q_int[2:0] 3'000 - sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "libresoc.v:173090.3-173091.27" - process $proc$libresoc.v:173090$11743 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] - end - attribute \src "libresoc.v:173092.3-173100.6" - process $proc$libresoc.v:173092$11744 - assign { } { } - assign { } { } - assign $0\q_int$next[2:0]$11745 $1\q_int$next[2:0]$11746 - attribute \src "libresoc.v:173093.5-173093.29" - switch \initial - attribute \src "libresoc.v:173093.9-173093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $1\q_int$next[2:0]$11746 3'000 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 case - assign $1\q_int$next[2:0]$11746 \$5 + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 end sync always - update \q_int$next $0\q_int$next[2:0]$11745 - end - connect \$9 $and$libresoc.v:173082$11735_Y - connect \$11 $or$libresoc.v:173083$11736_Y - connect \$13 $not$libresoc.v:173084$11737_Y - connect \$15 $or$libresoc.v:173085$11738_Y - connect \$1 $not$libresoc.v:173086$11739_Y - connect \$3 $and$libresoc.v:173087$11740_Y - connect \$5 $or$libresoc.v:173088$11741_Y - connect \$7 $not$libresoc.v:173089$11742_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "libresoc.v:173108.1-173166.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" -attribute \generator "nMigen" -module \req_l$41 - attribute \src "libresoc.v:173109.7-173109.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173154.3-173162.6" - wire width 5 $0\q_int$next[4:0]$11759 - attribute \src "libresoc.v:173152.3-173153.27" - wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:173154.3-173162.6" - wire width 5 $1\q_int$next[4:0]$11760 - attribute \src "libresoc.v:173131.13-173131.26" - wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:173144.17-173144.96" - wire width 5 $and$libresoc.v:173144$11749_Y - attribute \src "libresoc.v:173149.17-173149.96" - wire width 5 $and$libresoc.v:173149$11754_Y - attribute \src "libresoc.v:173146.18-173146.93" - wire width 5 $not$libresoc.v:173146$11751_Y - attribute \src "libresoc.v:173148.17-173148.92" - wire width 5 $not$libresoc.v:173148$11753_Y - attribute \src "libresoc.v:173151.17-173151.92" - wire width 5 $not$libresoc.v:173151$11756_Y - attribute \src "libresoc.v:173145.18-173145.98" - wire width 5 $or$libresoc.v:173145$11750_Y - attribute \src "libresoc.v:173147.18-173147.99" - wire width 5 $or$libresoc.v:173147$11752_Y - attribute \src "libresoc.v:173150.17-173150.97" - wire width 5 $or$libresoc.v:173150$11755_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:173109.7-173109.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173144$11749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:173144$11749_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173149$11754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173149$11754_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173146$11751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \Y $not$libresoc.v:173146$11751_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173148$11753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $not$libresoc.v:173148$11753_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173151$11756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $not$libresoc.v:173151$11756_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173145$11750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$9 - connect \B \s_req - connect \Y $or$libresoc.v:173145$11750_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173147$11752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \B \q_int - connect \Y $or$libresoc.v:173147$11752_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173150$11755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$3 - connect \B \s_req - connect \Y $or$libresoc.v:173150$11755_Y - end - attribute \src "libresoc.v:173109.7-173109.20" - process $proc$libresoc.v:173109$11761 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173131.13-173131.26" - process $proc$libresoc.v:173131$11762 - assign { } { } - assign $1\q_int[4:0] 5'00000 - sync always - sync init - update \q_int $1\q_int[4:0] - end - attribute \src "libresoc.v:173152.3-173153.27" - process $proc$libresoc.v:173152$11757 - assign { } { } - assign $0\q_int[4:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[4:0] + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:173154.3-173162.6" - process $proc$libresoc.v:173154$11758 + attribute \src "libresoc.v:34428.3-34446.6" + process $proc$libresoc.v:34428$744 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11759 $1\q_int$next[4:0]$11760 - attribute \src "libresoc.v:173155.5-173155.29" + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:34429.5-34429.29" switch \initial - attribute \src "libresoc.v:173155.9-173155.17" + attribute \src "libresoc.v:34429.9-34429.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\q_int$next[4:0]$11760 5'00000 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 case - assign $1\q_int$next[4:0]$11760 \$5 + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[4:0]$11759 - end - connect \$9 $and$libresoc.v:173144$11749_Y - connect \$11 $or$libresoc.v:173145$11750_Y - connect \$13 $not$libresoc.v:173146$11751_Y - connect \$15 $or$libresoc.v:173147$11752_Y - connect \$1 $not$libresoc.v:173148$11753_Y - connect \$3 $and$libresoc.v:173149$11754_Y - connect \$5 $or$libresoc.v:173150$11755_Y - connect \$7 $not$libresoc.v:173151$11756_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "libresoc.v:173170.1-173228.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" -attribute \generator "nMigen" -module \req_l$57 - attribute \src "libresoc.v:173171.7-173171.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173216.3-173224.6" - wire width 2 $0\q_int$next[1:0]$11773 - attribute \src "libresoc.v:173214.3-173215.27" - wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:173216.3-173224.6" - wire width 2 $1\q_int$next[1:0]$11774 - attribute \src "libresoc.v:173193.13-173193.25" - wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:173206.17-173206.96" - wire width 2 $and$libresoc.v:173206$11763_Y - attribute \src "libresoc.v:173211.17-173211.96" - wire width 2 $and$libresoc.v:173211$11768_Y - attribute \src "libresoc.v:173208.18-173208.93" - wire width 2 $not$libresoc.v:173208$11765_Y - attribute \src "libresoc.v:173210.17-173210.92" - wire width 2 $not$libresoc.v:173210$11767_Y - attribute \src "libresoc.v:173213.17-173213.92" - wire width 2 $not$libresoc.v:173213$11770_Y - attribute \src "libresoc.v:173207.18-173207.98" - wire width 2 $or$libresoc.v:173207$11764_Y - attribute \src "libresoc.v:173209.18-173209.99" - wire width 2 $or$libresoc.v:173209$11766_Y - attribute \src "libresoc.v:173212.17-173212.97" - wire width 2 $or$libresoc.v:173212$11769_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 2 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 2 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:173171.7-173171.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 2 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 2 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173206$11763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:173206$11763_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173211$11768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173211$11768_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173208$11765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_req - connect \Y $not$libresoc.v:173208$11765_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173210$11767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_req - connect \Y $not$libresoc.v:173210$11767_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173213$11770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_req - connect \Y $not$libresoc.v:173213$11770_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173207$11764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \$9 - connect \B \s_req - connect \Y $or$libresoc.v:173207$11764_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173209$11766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_req - connect \B \q_int - connect \Y $or$libresoc.v:173209$11766_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173212$11769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \$3 - connect \B \s_req - connect \Y $or$libresoc.v:173212$11769_Y - end - attribute \src "libresoc.v:173171.7-173171.20" - process $proc$libresoc.v:173171$11775 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173193.13-173193.25" - process $proc$libresoc.v:173193$11776 - assign { } { } - assign $1\q_int[1:0] 2'00 - sync always - sync init - update \q_int $1\q_int[1:0] - end - attribute \src "libresoc.v:173214.3-173215.27" - process $proc$libresoc.v:173214$11771 - assign { } { } - assign $0\q_int[1:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[1:0] + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:173216.3-173224.6" - process $proc$libresoc.v:173216$11772 + attribute \src "libresoc.v:34447.3-34465.6" + process $proc$libresoc.v:34447$745 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11773 $1\q_int$next[1:0]$11774 - attribute \src "libresoc.v:173217.5-173217.29" + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:34448.5-34448.29" switch \initial - attribute \src "libresoc.v:173217.9-173217.17" + attribute \src "libresoc.v:34448.9-34448.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\q_int$next[1:0]$11774 2'00 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 case - assign $1\q_int$next[1:0]$11774 \$5 + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[1:0]$11773 - end - connect \$9 $and$libresoc.v:173206$11763_Y - connect \$11 $or$libresoc.v:173207$11764_Y - connect \$13 $not$libresoc.v:173208$11765_Y - connect \$15 $or$libresoc.v:173209$11766_Y - connect \$1 $not$libresoc.v:173210$11767_Y - connect \$3 $and$libresoc.v:173211$11768_Y - connect \$5 $or$libresoc.v:173212$11769_Y - connect \$7 $not$libresoc.v:173213$11770_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "libresoc.v:173232.1-173290.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" -attribute \generator "nMigen" -module \req_l$69 - attribute \src "libresoc.v:173233.7-173233.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173278.3-173286.6" - wire width 6 $0\q_int$next[5:0]$11787 - attribute \src "libresoc.v:173276.3-173277.27" - wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:173278.3-173286.6" - wire width 6 $1\q_int$next[5:0]$11788 - attribute \src "libresoc.v:173255.13-173255.26" - wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:173268.17-173268.96" - wire width 6 $and$libresoc.v:173268$11777_Y - attribute \src "libresoc.v:173273.17-173273.96" - wire width 6 $and$libresoc.v:173273$11782_Y - attribute \src "libresoc.v:173270.18-173270.93" - wire width 6 $not$libresoc.v:173270$11779_Y - attribute \src "libresoc.v:173272.17-173272.92" - wire width 6 $not$libresoc.v:173272$11781_Y - attribute \src "libresoc.v:173275.17-173275.92" - wire width 6 $not$libresoc.v:173275$11784_Y - attribute \src "libresoc.v:173269.18-173269.98" - wire width 6 $or$libresoc.v:173269$11778_Y - attribute \src "libresoc.v:173271.18-173271.99" - wire width 6 $or$libresoc.v:173271$11780_Y - attribute \src "libresoc.v:173274.17-173274.97" - wire width 6 $or$libresoc.v:173274$11783_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:173233.7-173233.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173268$11777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:173268$11777_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173273$11782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173273$11782_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173270$11779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \Y $not$libresoc.v:173270$11779_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173272$11781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $not$libresoc.v:173272$11781_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173275$11784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $not$libresoc.v:173275$11784_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173269$11778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \s_req - connect \Y $or$libresoc.v:173269$11778_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173271$11780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \B \q_int - connect \Y $or$libresoc.v:173271$11780_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173274$11783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$3 - connect \B \s_req - connect \Y $or$libresoc.v:173274$11783_Y + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:173233.7-173233.20" - process $proc$libresoc.v:173233$11789 + attribute \src "libresoc.v:34466.3-34484.6" + process $proc$libresoc.v:34466$746 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173255.13-173255.26" - process $proc$libresoc.v:173255$11790 assign { } { } - assign $1\q_int[5:0] 6'000000 + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:34467.5-34467.29" + switch \initial + attribute \src "libresoc.v:34467.9-34467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[5:0] - end - attribute \src "libresoc.v:173276.3-173277.27" - process $proc$libresoc.v:173276$11785 - assign { } { } - assign $0\q_int[5:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[5:0] + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:173278.3-173286.6" - process $proc$libresoc.v:173278$11786 + attribute \src "libresoc.v:34485.3-34503.6" + process $proc$libresoc.v:34485$747 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$11787 $1\q_int$next[5:0]$11788 - attribute \src "libresoc.v:173279.5-173279.29" + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:34486.5-34486.29" switch \initial - attribute \src "libresoc.v:173279.9-173279.17" + attribute \src "libresoc.v:34486.9-34486.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\q_int$next[5:0]$11788 6'000000 + assign $1\dec31_dec_sub27_lk[0:0] 1'0 case - assign $1\q_int$next[5:0]$11788 \$5 + assign $1\dec31_dec_sub27_lk[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[5:0]$11787 - end - connect \$9 $and$libresoc.v:173268$11777_Y - connect \$11 $or$libresoc.v:173269$11778_Y - connect \$13 $not$libresoc.v:173270$11779_Y - connect \$15 $or$libresoc.v:173271$11780_Y - connect \$1 $not$libresoc.v:173272$11781_Y - connect \$3 $and$libresoc.v:173273$11782_Y - connect \$5 $or$libresoc.v:173274$11783_Y - connect \$7 $not$libresoc.v:173275$11784_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "libresoc.v:173294.1-173352.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" -attribute \generator "nMigen" -module \req_l$86 - attribute \src "libresoc.v:173295.7-173295.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173340.3-173348.6" - wire width 4 $0\q_int$next[3:0]$11801 - attribute \src "libresoc.v:173338.3-173339.27" - wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:173340.3-173348.6" - wire width 4 $1\q_int$next[3:0]$11802 - attribute \src "libresoc.v:173317.13-173317.25" - wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:173330.17-173330.96" - wire width 4 $and$libresoc.v:173330$11791_Y - attribute \src "libresoc.v:173335.17-173335.96" - wire width 4 $and$libresoc.v:173335$11796_Y - attribute \src "libresoc.v:173332.18-173332.93" - wire width 4 $not$libresoc.v:173332$11793_Y - attribute \src "libresoc.v:173334.17-173334.92" - wire width 4 $not$libresoc.v:173334$11795_Y - attribute \src "libresoc.v:173337.17-173337.92" - wire width 4 $not$libresoc.v:173337$11798_Y - attribute \src "libresoc.v:173331.18-173331.98" - wire width 4 $or$libresoc.v:173331$11792_Y - attribute \src "libresoc.v:173333.18-173333.99" - wire width 4 $or$libresoc.v:173333$11794_Y - attribute \src "libresoc.v:173336.17-173336.97" - wire width 4 $or$libresoc.v:173336$11797_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:173295.7-173295.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:173330$11791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:173330$11791_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173335$11796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173335$11796_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173332$11793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \Y $not$libresoc.v:173332$11793_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173334$11795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $not$libresoc.v:173334$11795_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:173337$11798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $not$libresoc.v:173337$11798_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:173331$11792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \s_req - connect \Y $or$libresoc.v:173331$11792_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173333$11794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \B \q_int - connect \Y $or$libresoc.v:173333$11794_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173336$11797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \s_req - connect \Y $or$libresoc.v:173336$11797_Y + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:173295.7-173295.20" - process $proc$libresoc.v:173295$11803 + attribute \src "libresoc.v:34504.3-34522.6" + process $proc$libresoc.v:34504$748 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173317.13-173317.25" - process $proc$libresoc.v:173317$11804 assign { } { } - assign $1\q_int[3:0] 4'0000 + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:34505.5-34505.29" + switch \initial + attribute \src "libresoc.v:34505.9-34505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[3:0] - end - attribute \src "libresoc.v:173338.3-173339.27" - process $proc$libresoc.v:173338$11799 - assign { } { } - assign $0\q_int[3:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[3:0] + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:173340.3-173348.6" - process $proc$libresoc.v:173340$11800 + attribute \src "libresoc.v:34523.3-34541.6" + process $proc$libresoc.v:34523$749 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11801 $1\q_int$next[3:0]$11802 - attribute \src "libresoc.v:173341.5-173341.29" + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:34524.5-34524.29" switch \initial - attribute \src "libresoc.v:173341.9-173341.17" + attribute \src "libresoc.v:34524.9-34524.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\q_int$next[3:0]$11802 4'0000 + assign $1\dec31_dec_sub27_form[4:0] 5'01000 case - assign $1\q_int$next[3:0]$11802 \$5 + assign $1\dec31_dec_sub27_form[4:0] 5'00000 end sync always - update \q_int$next $0\q_int$next[3:0]$11801 - end - connect \$9 $and$libresoc.v:173330$11791_Y - connect \$11 $or$libresoc.v:173331$11792_Y - connect \$13 $not$libresoc.v:173332$11793_Y - connect \$15 $or$libresoc.v:173333$11794_Y - connect \$1 $not$libresoc.v:173334$11795_Y - connect \$3 $and$libresoc.v:173335$11796_Y - connect \$5 $or$libresoc.v:173336$11797_Y - connect \$7 $not$libresoc.v:173337$11798_Y - connect \qlq_req \$15 - connect \qn_req \$13 - connect \q_req \$11 -end -attribute \src "libresoc.v:173356.1-173405.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" -attribute \generator "nMigen" -module \reset_l - attribute \src "libresoc.v:173357.7-173357.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173393.3-173401.6" - wire $0\q_int$next[0:0]$11812 - attribute \src "libresoc.v:173391.3-173392.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:173393.3-173401.6" - wire $1\q_int$next[0:0]$11813 - attribute \src "libresoc.v:173373.7-173373.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:173388.17-173388.96" - wire $and$libresoc.v:173388$11807_Y - attribute \src "libresoc.v:173387.17-173387.94" - wire $not$libresoc.v:173387$11806_Y - attribute \src "libresoc.v:173390.17-173390.94" - wire $not$libresoc.v:173390$11809_Y - attribute \src "libresoc.v:173386.17-173386.100" - wire $or$libresoc.v:173386$11805_Y - attribute \src "libresoc.v:173389.17-173389.99" - wire $or$libresoc.v:173389$11808_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:173357.7-173357.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173388$11807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173388$11807_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173387$11806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $not$libresoc.v:173387$11806_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173390$11809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $not$libresoc.v:173390$11809_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173386$11805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $or$libresoc.v:173386$11805_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173389$11808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_reset - connect \Y $or$libresoc.v:173389$11808_Y + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:173357.7-173357.20" - process $proc$libresoc.v:173357$11814 + attribute \src "libresoc.v:34542.3-34560.6" + process $proc$libresoc.v:34542$750 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173373.7-173373.19" - process $proc$libresoc.v:173373$11815 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:34543.5-34543.29" + switch \initial + attribute \src "libresoc.v:34543.9-34543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:173391.3-173392.27" - process $proc$libresoc.v:173391$11810 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:173393.3-173401.6" - process $proc$libresoc.v:173393$11811 + attribute \src "libresoc.v:34561.3-34579.6" + process $proc$libresoc.v:34561$751 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11812 $1\q_int$next[0:0]$11813 - attribute \src "libresoc.v:173394.5-173394.29" + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:34562.5-34562.29" switch \initial - attribute \src "libresoc.v:173394.9-173394.17" + attribute \src "libresoc.v:34562.9-34562.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\q_int$next[0:0]$11813 1'0 + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 case - assign $1\q_int$next[0:0]$11813 \$5 + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 end sync always - update \q_int$next $0\q_int$next[0:0]$11812 - end - connect \$9 $or$libresoc.v:173386$11805_Y - connect \$1 $not$libresoc.v:173387$11806_Y - connect \$3 $and$libresoc.v:173388$11807_Y - connect \$5 $or$libresoc.v:173389$11808_Y - connect \$7 $not$libresoc.v:173390$11809_Y - connect \qlq_reset \$9 - connect \qn_reset \$7 - connect \q_reset \q_int -end -attribute \src "libresoc.v:173409.1-173458.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" -attribute \generator "nMigen" -module \reset_l$131 - attribute \src "libresoc.v:173410.7-173410.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173446.3-173454.6" - wire $0\q_int$next[0:0]$11823 - attribute \src "libresoc.v:173444.3-173445.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:173446.3-173454.6" - wire $1\q_int$next[0:0]$11824 - attribute \src "libresoc.v:173426.7-173426.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:173441.17-173441.96" - wire $and$libresoc.v:173441$11818_Y - attribute \src "libresoc.v:173440.17-173440.94" - wire $not$libresoc.v:173440$11817_Y - attribute \src "libresoc.v:173443.17-173443.94" - wire $not$libresoc.v:173443$11820_Y - attribute \src "libresoc.v:173439.17-173439.100" - wire $or$libresoc.v:173439$11816_Y - attribute \src "libresoc.v:173442.17-173442.99" - wire $or$libresoc.v:173442$11819_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:173410.7-173410.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:173441$11818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:173441$11818_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:173440$11817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $not$libresoc.v:173440$11817_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:173443$11820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $not$libresoc.v:173443$11820_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:173439$11816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $or$libresoc.v:173439$11816_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:173442$11819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_reset - connect \Y $or$libresoc.v:173442$11819_Y + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:173410.7-173410.20" - process $proc$libresoc.v:173410$11825 + attribute \src "libresoc.v:34580.3-34598.6" + process $proc$libresoc.v:34580$752 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173426.7-173426.19" - process $proc$libresoc.v:173426$11826 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:34581.5-34581.29" + switch \initial + attribute \src "libresoc.v:34581.9-34581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:173444.3-173445.27" - process $proc$libresoc.v:173444$11821 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:173446.3-173454.6" - process $proc$libresoc.v:173446$11822 + attribute \src "libresoc.v:34599.3-34617.6" + process $proc$libresoc.v:34599$753 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11823 $1\q_int$next[0:0]$11824 - attribute \src "libresoc.v:173447.5-173447.29" + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:34600.5-34600.29" switch \initial - attribute \src "libresoc.v:173447.9-173447.17" + attribute \src "libresoc.v:34600.9-34600.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign $1\q_int$next[0:0]$11824 1'0 + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 case - assign $1\q_int$next[0:0]$11824 \$5 + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 end sync always - update \q_int$next $0\q_int$next[0:0]$11823 - end - connect \$9 $or$libresoc.v:173439$11816_Y - connect \$1 $not$libresoc.v:173440$11817_Y - connect \$3 $and$libresoc.v:173441$11818_Y - connect \$5 $or$libresoc.v:173442$11819_Y - connect \$7 $not$libresoc.v:173443$11820_Y - connect \qlq_reset \$9 - connect \qn_reset \$7 - connect \q_reset \q_int -end -attribute \src "libresoc.v:173462.1-174049.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" -attribute \generator "nMigen" -module \right_mask - attribute \src "libresoc.v:173463.7-173463.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:173661.3-174048.6" - wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:173661.3-174048.6" - wire $10\mask[9:9] - attribute \src "libresoc.v:173661.3-174048.6" - wire $11\mask[10:10] - attribute \src "libresoc.v:173661.3-174048.6" - wire $12\mask[11:11] - attribute \src "libresoc.v:173661.3-174048.6" - wire $13\mask[12:12] - attribute \src "libresoc.v:173661.3-174048.6" - wire $14\mask[13:13] - attribute \src "libresoc.v:173661.3-174048.6" - wire $15\mask[14:14] - attribute \src "libresoc.v:173661.3-174048.6" - wire $16\mask[15:15] - attribute \src "libresoc.v:173661.3-174048.6" - wire $17\mask[16:16] - attribute \src "libresoc.v:173661.3-174048.6" - wire $18\mask[17:17] - attribute \src "libresoc.v:173661.3-174048.6" - wire $19\mask[18:18] - attribute \src "libresoc.v:173661.3-174048.6" - wire $1\mask[0:0] - attribute \src "libresoc.v:173661.3-174048.6" - wire $20\mask[19:19] - attribute \src "libresoc.v:173661.3-174048.6" - wire $21\mask[20:20] - attribute \src "libresoc.v:173661.3-174048.6" - wire $22\mask[21:21] - attribute \src "libresoc.v:173661.3-174048.6" - wire $23\mask[22:22] - attribute \src "libresoc.v:173661.3-174048.6" - wire $24\mask[23:23] - attribute \src "libresoc.v:173661.3-174048.6" - wire $25\mask[24:24] - attribute \src "libresoc.v:173661.3-174048.6" - wire $26\mask[25:25] - attribute \src "libresoc.v:173661.3-174048.6" - wire $27\mask[26:26] - attribute \src "libresoc.v:173661.3-174048.6" - wire $28\mask[27:27] - attribute \src "libresoc.v:173661.3-174048.6" - wire $29\mask[28:28] - attribute \src "libresoc.v:173661.3-174048.6" - wire $2\mask[1:1] - attribute \src "libresoc.v:173661.3-174048.6" - wire $30\mask[29:29] - attribute \src "libresoc.v:173661.3-174048.6" - wire $31\mask[30:30] - attribute \src "libresoc.v:173661.3-174048.6" - wire $32\mask[31:31] - attribute \src "libresoc.v:173661.3-174048.6" - wire $33\mask[32:32] - attribute \src "libresoc.v:173661.3-174048.6" - wire $34\mask[33:33] - attribute \src "libresoc.v:173661.3-174048.6" - wire $35\mask[34:34] - attribute \src "libresoc.v:173661.3-174048.6" - wire $36\mask[35:35] - attribute \src "libresoc.v:173661.3-174048.6" - wire $37\mask[36:36] - attribute \src "libresoc.v:173661.3-174048.6" - wire $38\mask[37:37] - attribute \src "libresoc.v:173661.3-174048.6" - wire $39\mask[38:38] - attribute \src "libresoc.v:173661.3-174048.6" - wire $3\mask[2:2] - attribute \src "libresoc.v:173661.3-174048.6" - wire $40\mask[39:39] - attribute \src "libresoc.v:173661.3-174048.6" - wire $41\mask[40:40] - attribute \src "libresoc.v:173661.3-174048.6" - wire $42\mask[41:41] - attribute \src "libresoc.v:173661.3-174048.6" - wire $43\mask[42:42] - attribute \src "libresoc.v:173661.3-174048.6" - wire $44\mask[43:43] - attribute \src "libresoc.v:173661.3-174048.6" - wire $45\mask[44:44] - attribute \src "libresoc.v:173661.3-174048.6" - wire $46\mask[45:45] - attribute \src "libresoc.v:173661.3-174048.6" - wire $47\mask[46:46] - attribute \src "libresoc.v:173661.3-174048.6" - wire $48\mask[47:47] - attribute \src "libresoc.v:173661.3-174048.6" - wire $49\mask[48:48] - attribute \src "libresoc.v:173661.3-174048.6" - wire $4\mask[3:3] - attribute \src "libresoc.v:173661.3-174048.6" - wire $50\mask[49:49] - attribute \src "libresoc.v:173661.3-174048.6" - wire $51\mask[50:50] - attribute \src "libresoc.v:173661.3-174048.6" - wire $52\mask[51:51] - attribute \src "libresoc.v:173661.3-174048.6" - wire $53\mask[52:52] - attribute \src "libresoc.v:173661.3-174048.6" - wire $54\mask[53:53] - attribute \src "libresoc.v:173661.3-174048.6" - wire $55\mask[54:54] - attribute \src "libresoc.v:173661.3-174048.6" - wire $56\mask[55:55] - attribute \src "libresoc.v:173661.3-174048.6" - wire $57\mask[56:56] - attribute \src "libresoc.v:173661.3-174048.6" - wire $58\mask[57:57] - attribute \src "libresoc.v:173661.3-174048.6" - wire $59\mask[58:58] - attribute \src "libresoc.v:173661.3-174048.6" - wire $5\mask[4:4] - attribute \src "libresoc.v:173661.3-174048.6" - wire $60\mask[59:59] - attribute \src "libresoc.v:173661.3-174048.6" - wire $61\mask[60:60] - attribute \src "libresoc.v:173661.3-174048.6" - wire $62\mask[61:61] - attribute \src "libresoc.v:173661.3-174048.6" - wire $63\mask[62:62] - attribute \src "libresoc.v:173661.3-174048.6" - wire $64\mask[63:63] - attribute \src "libresoc.v:173661.3-174048.6" - wire $6\mask[5:5] - attribute \src "libresoc.v:173661.3-174048.6" - wire $7\mask[6:6] - attribute \src "libresoc.v:173661.3-174048.6" - wire $8\mask[7:7] - attribute \src "libresoc.v:173661.3-174048.6" - wire $9\mask[8:8] - attribute \src "libresoc.v:173597.17-173597.96" - wire $gt$libresoc.v:173597$11827_Y - attribute \src "libresoc.v:173598.18-173598.98" - wire $gt$libresoc.v:173598$11828_Y - attribute \src "libresoc.v:173599.19-173599.99" - wire $gt$libresoc.v:173599$11829_Y - attribute \src "libresoc.v:173600.19-173600.99" - wire $gt$libresoc.v:173600$11830_Y - attribute \src "libresoc.v:173601.19-173601.99" - wire $gt$libresoc.v:173601$11831_Y - attribute \src "libresoc.v:173602.19-173602.99" - wire $gt$libresoc.v:173602$11832_Y - attribute \src "libresoc.v:173603.19-173603.99" - wire $gt$libresoc.v:173603$11833_Y - attribute \src "libresoc.v:173604.19-173604.99" - wire $gt$libresoc.v:173604$11834_Y - attribute \src "libresoc.v:173605.19-173605.99" - wire $gt$libresoc.v:173605$11835_Y - attribute \src "libresoc.v:173606.19-173606.99" - wire $gt$libresoc.v:173606$11836_Y - attribute \src "libresoc.v:173607.19-173607.99" - wire $gt$libresoc.v:173607$11837_Y - attribute \src "libresoc.v:173608.18-173608.97" - wire $gt$libresoc.v:173608$11838_Y - attribute \src "libresoc.v:173609.19-173609.99" - wire $gt$libresoc.v:173609$11839_Y - attribute \src "libresoc.v:173610.19-173610.99" - wire $gt$libresoc.v:173610$11840_Y - attribute \src "libresoc.v:173611.19-173611.99" - wire $gt$libresoc.v:173611$11841_Y - attribute \src "libresoc.v:173612.19-173612.99" - wire $gt$libresoc.v:173612$11842_Y - attribute \src "libresoc.v:173613.19-173613.99" - wire $gt$libresoc.v:173613$11843_Y - attribute \src "libresoc.v:173614.18-173614.97" - wire $gt$libresoc.v:173614$11844_Y - attribute \src "libresoc.v:173615.18-173615.97" - wire $gt$libresoc.v:173615$11845_Y - attribute \src "libresoc.v:173616.18-173616.97" - wire $gt$libresoc.v:173616$11846_Y - attribute \src "libresoc.v:173617.17-173617.96" - wire $gt$libresoc.v:173617$11847_Y - attribute \src "libresoc.v:173618.18-173618.97" - wire $gt$libresoc.v:173618$11848_Y - attribute \src "libresoc.v:173619.18-173619.97" - wire $gt$libresoc.v:173619$11849_Y - attribute \src "libresoc.v:173620.18-173620.97" - wire $gt$libresoc.v:173620$11850_Y - attribute \src "libresoc.v:173621.18-173621.97" - wire $gt$libresoc.v:173621$11851_Y - attribute \src "libresoc.v:173622.18-173622.97" - wire $gt$libresoc.v:173622$11852_Y - attribute \src "libresoc.v:173623.18-173623.97" - wire $gt$libresoc.v:173623$11853_Y - attribute \src "libresoc.v:173624.18-173624.97" - wire $gt$libresoc.v:173624$11854_Y - attribute \src "libresoc.v:173625.18-173625.98" - wire $gt$libresoc.v:173625$11855_Y - attribute \src "libresoc.v:173626.18-173626.98" - wire $gt$libresoc.v:173626$11856_Y - attribute \src "libresoc.v:173627.18-173627.98" - wire $gt$libresoc.v:173627$11857_Y - attribute \src "libresoc.v:173628.17-173628.96" - wire $gt$libresoc.v:173628$11858_Y - attribute \src "libresoc.v:173629.18-173629.98" - wire $gt$libresoc.v:173629$11859_Y - attribute \src "libresoc.v:173630.18-173630.98" - wire $gt$libresoc.v:173630$11860_Y - attribute \src "libresoc.v:173631.18-173631.98" - wire $gt$libresoc.v:173631$11861_Y - attribute \src "libresoc.v:173632.18-173632.98" - wire $gt$libresoc.v:173632$11862_Y - attribute \src "libresoc.v:173633.18-173633.98" - wire $gt$libresoc.v:173633$11863_Y - attribute \src "libresoc.v:173634.18-173634.98" - wire $gt$libresoc.v:173634$11864_Y - attribute \src "libresoc.v:173635.18-173635.98" - wire $gt$libresoc.v:173635$11865_Y - attribute \src "libresoc.v:173636.18-173636.98" - wire $gt$libresoc.v:173636$11866_Y - attribute \src "libresoc.v:173637.18-173637.98" - wire $gt$libresoc.v:173637$11867_Y - attribute \src "libresoc.v:173638.18-173638.98" - wire $gt$libresoc.v:173638$11868_Y - attribute \src "libresoc.v:173639.17-173639.96" - wire $gt$libresoc.v:173639$11869_Y - attribute \src "libresoc.v:173640.18-173640.98" - wire $gt$libresoc.v:173640$11870_Y - attribute \src "libresoc.v:173641.18-173641.98" - wire $gt$libresoc.v:173641$11871_Y - attribute \src "libresoc.v:173642.18-173642.98" - wire $gt$libresoc.v:173642$11872_Y - attribute \src "libresoc.v:173643.18-173643.98" - wire $gt$libresoc.v:173643$11873_Y - attribute \src "libresoc.v:173644.18-173644.98" - wire $gt$libresoc.v:173644$11874_Y - attribute \src "libresoc.v:173645.18-173645.98" - wire $gt$libresoc.v:173645$11875_Y - attribute \src "libresoc.v:173646.18-173646.98" - wire $gt$libresoc.v:173646$11876_Y - attribute \src "libresoc.v:173647.18-173647.98" - wire $gt$libresoc.v:173647$11877_Y - attribute \src "libresoc.v:173648.18-173648.98" - wire $gt$libresoc.v:173648$11878_Y - attribute \src "libresoc.v:173649.18-173649.98" - wire $gt$libresoc.v:173649$11879_Y - attribute \src "libresoc.v:173650.17-173650.96" - wire $gt$libresoc.v:173650$11880_Y - attribute \src "libresoc.v:173651.18-173651.98" - wire $gt$libresoc.v:173651$11881_Y - attribute \src "libresoc.v:173652.18-173652.98" - wire $gt$libresoc.v:173652$11882_Y - attribute \src "libresoc.v:173653.18-173653.98" - wire $gt$libresoc.v:173653$11883_Y - attribute \src "libresoc.v:173654.18-173654.98" - wire $gt$libresoc.v:173654$11884_Y - attribute \src "libresoc.v:173655.18-173655.98" - wire $gt$libresoc.v:173655$11885_Y - attribute \src "libresoc.v:173656.18-173656.98" - wire $gt$libresoc.v:173656$11886_Y - attribute \src "libresoc.v:173657.18-173657.98" - wire $gt$libresoc.v:173657$11887_Y - attribute \src "libresoc.v:173658.18-173658.98" - wire $gt$libresoc.v:173658$11888_Y - attribute \src "libresoc.v:173659.18-173659.98" - wire $gt$libresoc.v:173659$11889_Y - attribute \src "libresoc.v:173660.18-173660.98" - wire $gt$libresoc.v:173660$11890_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - wire \$99 - attribute \src "libresoc.v:173463.7-173463.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" - wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" - wire width 7 input 2 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173597$11827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'100 - connect \Y $gt$libresoc.v:173597$11827_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173598$11828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110001 - connect \Y $gt$libresoc.v:173598$11828_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173599$11829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110010 - connect \Y $gt$libresoc.v:173599$11829_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173600$11830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110011 - connect \Y $gt$libresoc.v:173600$11830_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173601$11831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110100 - connect \Y $gt$libresoc.v:173601$11831_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173602$11832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110101 - connect \Y $gt$libresoc.v:173602$11832_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173603$11833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110110 - connect \Y $gt$libresoc.v:173603$11833_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173604$11834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110111 - connect \Y $gt$libresoc.v:173604$11834_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173605$11835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111000 - connect \Y $gt$libresoc.v:173605$11835_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173606$11836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111001 - connect \Y $gt$libresoc.v:173606$11836_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173607$11837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111010 - connect \Y $gt$libresoc.v:173607$11837_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173608$11838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'101 - connect \Y $gt$libresoc.v:173608$11838_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173609$11839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111011 - connect \Y $gt$libresoc.v:173609$11839_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173610$11840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111100 - connect \Y $gt$libresoc.v:173610$11840_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173611$11841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111101 - connect \Y $gt$libresoc.v:173611$11841_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173612$11842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111110 - connect \Y $gt$libresoc.v:173612$11842_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173613$11843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111111 - connect \Y $gt$libresoc.v:173613$11843_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173614$11844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'110 - connect \Y $gt$libresoc.v:173614$11844_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173615$11845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'111 - connect \Y $gt$libresoc.v:173615$11845_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173616$11846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1000 - connect \Y $gt$libresoc.v:173616$11846_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173617$11847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'0 - connect \Y $gt$libresoc.v:173617$11847_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173618$11848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1001 - connect \Y $gt$libresoc.v:173618$11848_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173619$11849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1010 - connect \Y $gt$libresoc.v:173619$11849_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173620$11850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1011 - connect \Y $gt$libresoc.v:173620$11850_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173621$11851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1100 - connect \Y $gt$libresoc.v:173621$11851_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173622$11852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1101 - connect \Y $gt$libresoc.v:173622$11852_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173623$11853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1110 - connect \Y $gt$libresoc.v:173623$11853_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173624$11854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1111 - connect \Y $gt$libresoc.v:173624$11854_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173625$11855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10000 - connect \Y $gt$libresoc.v:173625$11855_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173626$11856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10001 - connect \Y $gt$libresoc.v:173626$11856_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173627$11857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10010 - connect \Y $gt$libresoc.v:173627$11857_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173628$11858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'1 - connect \Y $gt$libresoc.v:173628$11858_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173629$11859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10011 - connect \Y $gt$libresoc.v:173629$11859_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173630$11860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10100 - connect \Y $gt$libresoc.v:173630$11860_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173631$11861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10101 - connect \Y $gt$libresoc.v:173631$11861_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173632$11862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10110 - connect \Y $gt$libresoc.v:173632$11862_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173633$11863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10111 - connect \Y $gt$libresoc.v:173633$11863_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173634$11864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11000 - connect \Y $gt$libresoc.v:173634$11864_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173635$11865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11001 - connect \Y $gt$libresoc.v:173635$11865_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173636$11866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11010 - connect \Y $gt$libresoc.v:173636$11866_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173637$11867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11011 - connect \Y $gt$libresoc.v:173637$11867_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173638$11868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11100 - connect \Y $gt$libresoc.v:173638$11868_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173639$11869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'10 - connect \Y $gt$libresoc.v:173639$11869_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173640$11870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11101 - connect \Y $gt$libresoc.v:173640$11870_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173641$11871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11110 - connect \Y $gt$libresoc.v:173641$11871_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173642$11872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11111 - connect \Y $gt$libresoc.v:173642$11872_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173643$11873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100000 - connect \Y $gt$libresoc.v:173643$11873_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173644$11874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100001 - connect \Y $gt$libresoc.v:173644$11874_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173645$11875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100010 - connect \Y $gt$libresoc.v:173645$11875_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173646$11876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100011 - connect \Y $gt$libresoc.v:173646$11876_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173647$11877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100100 - connect \Y $gt$libresoc.v:173647$11877_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173648$11878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100101 - connect \Y $gt$libresoc.v:173648$11878_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173649$11879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100110 - connect \Y $gt$libresoc.v:173649$11879_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173650$11880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'11 - connect \Y $gt$libresoc.v:173650$11880_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173651$11881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100111 - connect \Y $gt$libresoc.v:173651$11881_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173652$11882 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101000 - connect \Y $gt$libresoc.v:173652$11882_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173653$11883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101001 - connect \Y $gt$libresoc.v:173653$11883_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173654$11884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101010 - connect \Y $gt$libresoc.v:173654$11884_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173655$11885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101011 - connect \Y $gt$libresoc.v:173655$11885_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173656$11886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101100 - connect \Y $gt$libresoc.v:173656$11886_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173657$11887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101101 - connect \Y $gt$libresoc.v:173657$11887_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173658$11888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101110 - connect \Y $gt$libresoc.v:173658$11888_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173659$11889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101111 - connect \Y $gt$libresoc.v:173659$11889_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - cell $gt $gt$libresoc.v:173660$11890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110000 - connect \Y $gt$libresoc.v:173660$11890_Y + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] end - attribute \src "libresoc.v:173463.7-173463.20" - process $proc$libresoc.v:173463$11892 + attribute \src "libresoc.v:34618.3-34636.6" + process $proc$libresoc.v:34618$754 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:173661.3-174048.6" - process $proc$libresoc.v:173661$11891 - assign { } { } - assign { } { } - assign $0\mask[63:0] [0] $1\mask[0:0] - assign $0\mask[63:0] [1] $2\mask[1:1] - assign $0\mask[63:0] [2] $3\mask[2:2] - assign $0\mask[63:0] [3] $4\mask[3:3] - assign $0\mask[63:0] [4] $5\mask[4:4] - assign $0\mask[63:0] [5] $6\mask[5:5] - assign $0\mask[63:0] [6] $7\mask[6:6] - assign $0\mask[63:0] [7] $8\mask[7:7] - assign $0\mask[63:0] [8] $9\mask[8:8] - assign $0\mask[63:0] [9] $10\mask[9:9] - assign $0\mask[63:0] [10] $11\mask[10:10] - assign $0\mask[63:0] [11] $12\mask[11:11] - assign $0\mask[63:0] [12] $13\mask[12:12] - assign $0\mask[63:0] [13] $14\mask[13:13] - assign $0\mask[63:0] [14] $15\mask[14:14] - assign $0\mask[63:0] [15] $16\mask[15:15] - assign $0\mask[63:0] [16] $17\mask[16:16] - assign $0\mask[63:0] [17] $18\mask[17:17] - assign $0\mask[63:0] [18] $19\mask[18:18] - assign $0\mask[63:0] [19] $20\mask[19:19] - assign $0\mask[63:0] [20] $21\mask[20:20] - assign $0\mask[63:0] [21] $22\mask[21:21] - assign $0\mask[63:0] [22] $23\mask[22:22] - assign $0\mask[63:0] [23] $24\mask[23:23] - assign $0\mask[63:0] [24] $25\mask[24:24] - assign $0\mask[63:0] [25] $26\mask[25:25] - assign $0\mask[63:0] [26] $27\mask[26:26] - assign $0\mask[63:0] [27] $28\mask[27:27] - assign $0\mask[63:0] [28] $29\mask[28:28] - assign $0\mask[63:0] [29] $30\mask[29:29] - assign $0\mask[63:0] [30] $31\mask[30:30] - assign $0\mask[63:0] [31] $32\mask[31:31] - assign $0\mask[63:0] [32] $33\mask[32:32] - assign $0\mask[63:0] [33] $34\mask[33:33] - assign $0\mask[63:0] [34] $35\mask[34:34] - assign $0\mask[63:0] [35] $36\mask[35:35] - assign $0\mask[63:0] [36] $37\mask[36:36] - assign $0\mask[63:0] [37] $38\mask[37:37] - assign $0\mask[63:0] [38] $39\mask[38:38] - assign $0\mask[63:0] [39] $40\mask[39:39] - assign $0\mask[63:0] [40] $41\mask[40:40] - assign $0\mask[63:0] [41] $42\mask[41:41] - assign $0\mask[63:0] [42] $43\mask[42:42] - assign $0\mask[63:0] [43] $44\mask[43:43] - assign $0\mask[63:0] [44] $45\mask[44:44] - assign $0\mask[63:0] [45] $46\mask[45:45] - assign $0\mask[63:0] [46] $47\mask[46:46] - assign $0\mask[63:0] [47] $48\mask[47:47] - assign $0\mask[63:0] [48] $49\mask[48:48] - assign $0\mask[63:0] [49] $50\mask[49:49] - assign $0\mask[63:0] [50] $51\mask[50:50] - assign $0\mask[63:0] [51] $52\mask[51:51] - assign $0\mask[63:0] [52] $53\mask[52:52] - assign $0\mask[63:0] [53] $54\mask[53:53] - assign $0\mask[63:0] [54] $55\mask[54:54] - assign $0\mask[63:0] [55] $56\mask[55:55] - assign $0\mask[63:0] [56] $57\mask[56:56] - assign $0\mask[63:0] [57] $58\mask[57:57] - assign $0\mask[63:0] [58] $59\mask[58:58] - assign $0\mask[63:0] [59] $60\mask[59:59] - assign $0\mask[63:0] [60] $61\mask[60:60] - assign $0\mask[63:0] [61] $62\mask[61:61] - assign $0\mask[63:0] [62] $63\mask[62:62] - assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:173662.5-173662.29" + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:34619.5-34619.29" switch \initial - attribute \src "libresoc.v:173662.9-173662.17" + attribute \src "libresoc.v:34619.9-34619.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 assign { } { } - assign $1\mask[0:0] 1'1 - case - assign $1\mask[0:0] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$3 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $2\mask[1:1] 1'1 - case - assign $2\mask[1:1] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$5 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $3\mask[2:2] 1'1 - case - assign $3\mask[2:2] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$7 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $4\mask[3:3] 1'1 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 case - assign $4\mask[3:3] 1'0 + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$9 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:34637.3-34655.6" + process $proc$libresoc.v:34637$755 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:34638.5-34638.29" + switch \initial + attribute \src "libresoc.v:34638.9-34638.17" case 1'1 - assign { } { } - assign $5\mask[4:4] 1'1 case - assign $5\mask[4:4] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11011 assign { } { } - assign $6\mask[5:5] 1'1 - case - assign $6\mask[5:5] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$13 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $7\mask[6:6] 1'1 - case - assign $7\mask[6:6] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$15 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11001 assign { } { } - assign $8\mask[7:7] 1'1 - case - assign $8\mask[7:7] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$17 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $9\mask[8:8] 1'1 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 case - assign $9\mask[8:8] 1'0 + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:34661.1-35808.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:35104.3-35140.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35252.3-35288.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35733.3-35769.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35770.3-35806.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35067.3-35103.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35215.3-35251.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35548.3-35584.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34919.3-34955.6" + wire width 12 $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35585.3-35621.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35622.3-35658.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35659.3-35695.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35326.3-35362.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35141.3-35177.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35178.3-35214.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35400.3-35436.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:34956.3-34992.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35474.3-35510.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35696.3-35732.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35030.3-35066.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35363.3-35399.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35511.3-35547.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35437.3-35473.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35289.3-35325.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:34993.3-35029.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:34662.7-34662.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:35104.3-35140.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35252.3-35288.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35733.3-35769.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35770.3-35806.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35067.3-35103.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35215.3-35251.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35548.3-35584.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:34919.3-34955.6" + wire width 12 $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:35585.3-35621.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35622.3-35658.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35659.3-35695.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35326.3-35362.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35141.3-35177.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35178.3-35214.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35400.3-35436.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:34956.3-34992.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:35474.3-35510.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35696.3-35732.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35030.3-35066.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35363.3-35399.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35511.3-35547.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35437.3-35473.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:35289.3-35325.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:34993.3-35029.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub28_upd + attribute \src "libresoc.v:34662.7-34662.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:34662.7-34662.20" + process $proc$libresoc.v:34662$781 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34919.3-34955.6" + process $proc$libresoc.v:34919$757 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "libresoc.v:34920.5-34920.29" + switch \initial + attribute \src "libresoc.v:34920.9-34920.17" case 1'1 - assign { } { } - assign $10\mask[9:9] 1'1 case - assign $10\mask[9:9] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $11\mask[10:10] 1'1 - case - assign $11\mask[10:10] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$23 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $12\mask[11:11] 1'1 - case - assign $12\mask[11:11] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$25 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $13\mask[12:12] 1'1 - case - assign $13\mask[12:12] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$27 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 assign { } { } - assign $14\mask[13:13] 1'1 - case - assign $14\mask[13:13] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$29 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $15\mask[14:14] 1'1 - case - assign $15\mask[14:14] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$31 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $16\mask[15:15] 1'1 - case - assign $16\mask[15:15] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$33 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $17\mask[16:16] 1'1 - case - assign $17\mask[16:16] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$35 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $18\mask[17:17] 1'1 - case - assign $18\mask[17:17] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$37 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $19\mask[18:18] 1'1 - case - assign $19\mask[18:18] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$39 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 assign { } { } - assign $20\mask[19:19] 1'1 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 case - assign $20\mask[19:19] 1'0 + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$41 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + end + attribute \src "libresoc.v:34956.3-34992.6" + process $proc$libresoc.v:34956$758 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:34957.5-34957.29" + switch \initial + attribute \src "libresoc.v:34957.9-34957.17" case 1'1 - assign { } { } - assign $21\mask[20:20] 1'1 case - assign $21\mask[20:20] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $22\mask[21:21] 1'1 - case - assign $22\mask[21:21] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$45 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $23\mask[22:22] 1'1 - case - assign $23\mask[22:22] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$47 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $24\mask[23:23] 1'1 - case - assign $24\mask[23:23] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$49 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 assign { } { } - assign $25\mask[24:24] 1'1 - case - assign $25\mask[24:24] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$51 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $26\mask[25:25] 1'1 - case - assign $26\mask[25:25] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$53 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $27\mask[26:26] 1'1 - case - assign $27\mask[26:26] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$55 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $28\mask[27:27] 1'1 - case - assign $28\mask[27:27] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$57 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $29\mask[28:28] 1'1 - case - assign $29\mask[28:28] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$59 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $30\mask[29:29] 1'1 - case - assign $30\mask[29:29] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$61 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 assign { } { } - assign $31\mask[30:30] 1'1 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 case - assign $31\mask[30:30] 1'0 + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:34993.3-35029.6" + process $proc$libresoc.v:34993$759 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:34994.5-34994.29" + switch \initial + attribute \src "libresoc.v:34994.9-34994.17" case 1'1 - assign { } { } - assign $32\mask[31:31] 1'1 case - assign $32\mask[31:31] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $33\mask[32:32] 1'1 - case - assign $33\mask[32:32] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$67 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $34\mask[33:33] 1'1 - case - assign $34\mask[33:33] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$69 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $35\mask[34:34] 1'1 - case - assign $35\mask[34:34] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$71 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 assign { } { } - assign $36\mask[35:35] 1'1 - case - assign $36\mask[35:35] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$73 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $37\mask[36:36] 1'1 - case - assign $37\mask[36:36] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$75 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $38\mask[37:37] 1'1 - case - assign $38\mask[37:37] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$77 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $39\mask[38:38] 1'1 - case - assign $39\mask[38:38] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$79 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $40\mask[39:39] 1'1 - case - assign $40\mask[39:39] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$81 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $41\mask[40:40] 1'1 - case - assign $41\mask[40:40] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$83 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 assign { } { } - assign $42\mask[41:41] 1'1 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 case - assign $42\mask[41:41] 1'0 + assign $1\dec31_dec_sub28_upd[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$85 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + end + attribute \src "libresoc.v:35030.3-35066.6" + process $proc$libresoc.v:35030$760 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:35031.5-35031.29" + switch \initial + attribute \src "libresoc.v:35031.9-35031.17" case 1'1 - assign { } { } - assign $43\mask[42:42] 1'1 case - assign $43\mask[42:42] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $44\mask[43:43] 1'1 - case - assign $44\mask[43:43] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$89 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $45\mask[44:44] 1'1 - case - assign $45\mask[44:44] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$91 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $46\mask[45:45] 1'1 - case - assign $46\mask[45:45] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$93 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 assign { } { } - assign $47\mask[46:46] 1'1 - case - assign $47\mask[46:46] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$95 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $48\mask[47:47] 1'1 - case - assign $48\mask[47:47] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$97 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $49\mask[48:48] 1'1 - case - assign $49\mask[48:48] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$99 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $50\mask[49:49] 1'1 - case - assign $50\mask[49:49] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$101 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $51\mask[50:50] 1'1 - case - assign $51\mask[50:50] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$103 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $52\mask[51:51] 1'1 - case - assign $52\mask[51:51] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$105 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 assign { } { } - assign $53\mask[52:52] 1'1 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 case - assign $53\mask[52:52] 1'0 + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$107 - attribute \src "libresoc.v:0.0-0.0" + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:35067.3-35103.6" + process $proc$libresoc.v:35067$761 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:35068.5-35068.29" + switch \initial + attribute \src "libresoc.v:35068.9-35068.17" case 1'1 - assign { } { } - assign $54\mask[53:53] 1'1 case - assign $54\mask[53:53] 1'0 end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $55\mask[54:54] 1'1 - case - assign $55\mask[54:54] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$111 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $56\mask[55:55] 1'1 - case - assign $56\mask[55:55] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$113 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $57\mask[56:56] 1'1 - case - assign $57\mask[56:56] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$115 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 assign { } { } - assign $58\mask[57:57] 1'1 - case - assign $58\mask[57:57] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$117 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $59\mask[58:58] 1'1 - case - assign $59\mask[58:58] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$119 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $60\mask[59:59] 1'1 - case - assign $60\mask[59:59] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$121 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $61\mask[60:60] 1'1 - case - assign $61\mask[60:60] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$123 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $62\mask[61:61] 1'1 - case - assign $62\mask[61:61] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$125 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $63\mask[62:62] 1'1 - case - assign $63\mask[62:62] 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" - switch \$127 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $64\mask[63:63] 1'1 - case - assign $64\mask[63:63] 1'0 - end - sync always - update \mask $0\mask[63:0] - end - connect \$9 $gt$libresoc.v:173597$11827_Y - connect \$99 $gt$libresoc.v:173598$11828_Y - connect \$101 $gt$libresoc.v:173599$11829_Y - connect \$103 $gt$libresoc.v:173600$11830_Y - connect \$105 $gt$libresoc.v:173601$11831_Y - connect \$107 $gt$libresoc.v:173602$11832_Y - connect \$109 $gt$libresoc.v:173603$11833_Y - connect \$111 $gt$libresoc.v:173604$11834_Y - connect \$113 $gt$libresoc.v:173605$11835_Y - connect \$115 $gt$libresoc.v:173606$11836_Y - connect \$117 $gt$libresoc.v:173607$11837_Y - connect \$11 $gt$libresoc.v:173608$11838_Y - connect \$119 $gt$libresoc.v:173609$11839_Y - connect \$121 $gt$libresoc.v:173610$11840_Y - connect \$123 $gt$libresoc.v:173611$11841_Y - connect \$125 $gt$libresoc.v:173612$11842_Y - connect \$127 $gt$libresoc.v:173613$11843_Y - connect \$13 $gt$libresoc.v:173614$11844_Y - connect \$15 $gt$libresoc.v:173615$11845_Y - connect \$17 $gt$libresoc.v:173616$11846_Y - connect \$1 $gt$libresoc.v:173617$11847_Y - connect \$19 $gt$libresoc.v:173618$11848_Y - connect \$21 $gt$libresoc.v:173619$11849_Y - connect \$23 $gt$libresoc.v:173620$11850_Y - connect \$25 $gt$libresoc.v:173621$11851_Y - connect \$27 $gt$libresoc.v:173622$11852_Y - connect \$29 $gt$libresoc.v:173623$11853_Y - connect \$31 $gt$libresoc.v:173624$11854_Y - connect \$33 $gt$libresoc.v:173625$11855_Y - connect \$35 $gt$libresoc.v:173626$11856_Y - connect \$37 $gt$libresoc.v:173627$11857_Y - connect \$3 $gt$libresoc.v:173628$11858_Y - connect \$39 $gt$libresoc.v:173629$11859_Y - connect \$41 $gt$libresoc.v:173630$11860_Y - connect \$43 $gt$libresoc.v:173631$11861_Y - connect \$45 $gt$libresoc.v:173632$11862_Y - connect \$47 $gt$libresoc.v:173633$11863_Y - connect \$49 $gt$libresoc.v:173634$11864_Y - connect \$51 $gt$libresoc.v:173635$11865_Y - connect \$53 $gt$libresoc.v:173636$11866_Y - connect \$55 $gt$libresoc.v:173637$11867_Y - connect \$57 $gt$libresoc.v:173638$11868_Y - connect \$5 $gt$libresoc.v:173639$11869_Y - connect \$59 $gt$libresoc.v:173640$11870_Y - connect \$61 $gt$libresoc.v:173641$11871_Y - connect \$63 $gt$libresoc.v:173642$11872_Y - connect \$65 $gt$libresoc.v:173643$11873_Y - connect \$67 $gt$libresoc.v:173644$11874_Y - connect \$69 $gt$libresoc.v:173645$11875_Y - connect \$71 $gt$libresoc.v:173646$11876_Y - connect \$73 $gt$libresoc.v:173647$11877_Y - connect \$75 $gt$libresoc.v:173648$11878_Y - connect \$77 $gt$libresoc.v:173649$11879_Y - connect \$7 $gt$libresoc.v:173650$11880_Y - connect \$79 $gt$libresoc.v:173651$11881_Y - connect \$81 $gt$libresoc.v:173652$11882_Y - connect \$83 $gt$libresoc.v:173653$11883_Y - connect \$85 $gt$libresoc.v:173654$11884_Y - connect \$87 $gt$libresoc.v:173655$11885_Y - connect \$89 $gt$libresoc.v:173656$11886_Y - connect \$91 $gt$libresoc.v:173657$11887_Y - connect \$93 $gt$libresoc.v:173658$11888_Y - connect \$95 $gt$libresoc.v:173659$11889_Y - connect \$97 $gt$libresoc.v:173660$11890_Y -end -attribute \src "libresoc.v:174053.1-174111.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" -attribute \generator "nMigen" -module \rok_l - attribute \src "libresoc.v:174054.7-174054.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174099.3-174107.6" - wire $0\q_int$next[0:0]$11903 - attribute \src "libresoc.v:174097.3-174098.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174099.3-174107.6" - wire $1\q_int$next[0:0]$11904 - attribute \src "libresoc.v:174076.7-174076.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174089.17-174089.96" - wire $and$libresoc.v:174089$11893_Y - attribute \src "libresoc.v:174094.17-174094.96" - wire $and$libresoc.v:174094$11898_Y - attribute \src "libresoc.v:174091.18-174091.94" - wire $not$libresoc.v:174091$11895_Y - attribute \src "libresoc.v:174093.17-174093.93" - wire $not$libresoc.v:174093$11897_Y - attribute \src "libresoc.v:174096.17-174096.93" - wire $not$libresoc.v:174096$11900_Y - attribute \src "libresoc.v:174090.18-174090.99" - wire $or$libresoc.v:174090$11894_Y - attribute \src "libresoc.v:174092.18-174092.100" - wire $or$libresoc.v:174092$11896_Y - attribute \src "libresoc.v:174095.17-174095.98" - wire $or$libresoc.v:174095$11899_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174054.7-174054.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174089$11893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174089$11893_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174094$11898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174094$11898_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174091$11895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174091$11895_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174093$11897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174093$11897_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174096$11900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174096$11900_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174090$11894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174090$11894_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174092$11896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174092$11896_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174095$11899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174095$11899_Y - end - attribute \src "libresoc.v:174054.7-174054.20" - process $proc$libresoc.v:174054$11905 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174076.7-174076.19" - process $proc$libresoc.v:174076$11906 - assign { } { } - assign $1\q_int[0:0] 1'0 + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174097.3-174098.27" - process $proc$libresoc.v:174097$11901 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:174099.3-174107.6" - process $proc$libresoc.v:174099$11902 + attribute \src "libresoc.v:35104.3-35140.6" + process $proc$libresoc.v:35104$762 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11903 $1\q_int$next[0:0]$11904 - attribute \src "libresoc.v:174100.5-174100.29" + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:35105.5-35105.29" switch \initial - attribute \src "libresoc.v:174100.9-174100.17" + attribute \src "libresoc.v:35105.9-35105.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$11904 1'0 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 case - assign $1\q_int$next[0:0]$11904 \$5 + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 end sync always - update \q_int$next $0\q_int$next[0:0]$11903 - end - connect \$9 $and$libresoc.v:174089$11893_Y - connect \$11 $or$libresoc.v:174090$11894_Y - connect \$13 $not$libresoc.v:174091$11895_Y - connect \$15 $or$libresoc.v:174092$11896_Y - connect \$1 $not$libresoc.v:174093$11897_Y - connect \$3 $and$libresoc.v:174094$11898_Y - connect \$5 $or$libresoc.v:174095$11899_Y - connect \$7 $not$libresoc.v:174096$11900_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174115.1-174173.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" -attribute \generator "nMigen" -module \rok_l$105 - attribute \src "libresoc.v:174116.7-174116.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174161.3-174169.6" - wire $0\q_int$next[0:0]$11917 - attribute \src "libresoc.v:174159.3-174160.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174161.3-174169.6" - wire $1\q_int$next[0:0]$11918 - attribute \src "libresoc.v:174138.7-174138.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174151.17-174151.96" - wire $and$libresoc.v:174151$11907_Y - attribute \src "libresoc.v:174156.17-174156.96" - wire $and$libresoc.v:174156$11912_Y - attribute \src "libresoc.v:174153.18-174153.94" - wire $not$libresoc.v:174153$11909_Y - attribute \src "libresoc.v:174155.17-174155.93" - wire $not$libresoc.v:174155$11911_Y - attribute \src "libresoc.v:174158.17-174158.93" - wire $not$libresoc.v:174158$11914_Y - attribute \src "libresoc.v:174152.18-174152.99" - wire $or$libresoc.v:174152$11908_Y - attribute \src "libresoc.v:174154.18-174154.100" - wire $or$libresoc.v:174154$11910_Y - attribute \src "libresoc.v:174157.17-174157.98" - wire $or$libresoc.v:174157$11913_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174116.7-174116.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174151$11907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174151$11907_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174156$11912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174156$11912_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174153$11909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174153$11909_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174155$11911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174155$11911_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174158$11914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174158$11914_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174152$11908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174152$11908_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174154$11910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174154$11910_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174157$11913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174157$11913_Y - end - attribute \src "libresoc.v:174116.7-174116.20" - process $proc$libresoc.v:174116$11919 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174138.7-174138.19" - process $proc$libresoc.v:174138$11920 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174159.3-174160.27" - process $proc$libresoc.v:174159$11915 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:174161.3-174169.6" - process $proc$libresoc.v:174161$11916 + attribute \src "libresoc.v:35141.3-35177.6" + process $proc$libresoc.v:35141$763 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11917 $1\q_int$next[0:0]$11918 - attribute \src "libresoc.v:174162.5-174162.29" + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:35142.5-35142.29" switch \initial - attribute \src "libresoc.v:174162.9-174162.17" + attribute \src "libresoc.v:35142.9-35142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$11918 1'0 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 case - assign $1\q_int$next[0:0]$11918 \$5 + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$11917 - end - connect \$9 $and$libresoc.v:174151$11907_Y - connect \$11 $or$libresoc.v:174152$11908_Y - connect \$13 $not$libresoc.v:174153$11909_Y - connect \$15 $or$libresoc.v:174154$11910_Y - connect \$1 $not$libresoc.v:174155$11911_Y - connect \$3 $and$libresoc.v:174156$11912_Y - connect \$5 $or$libresoc.v:174157$11913_Y - connect \$7 $not$libresoc.v:174158$11914_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174177.1-174235.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" -attribute \generator "nMigen" -module \rok_l$123 - attribute \src "libresoc.v:174178.7-174178.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174223.3-174231.6" - wire $0\q_int$next[0:0]$11931 - attribute \src "libresoc.v:174221.3-174222.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174223.3-174231.6" - wire $1\q_int$next[0:0]$11932 - attribute \src "libresoc.v:174200.7-174200.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174213.17-174213.96" - wire $and$libresoc.v:174213$11921_Y - attribute \src "libresoc.v:174218.17-174218.96" - wire $and$libresoc.v:174218$11926_Y - attribute \src "libresoc.v:174215.18-174215.94" - wire $not$libresoc.v:174215$11923_Y - attribute \src "libresoc.v:174217.17-174217.93" - wire $not$libresoc.v:174217$11925_Y - attribute \src "libresoc.v:174220.17-174220.93" - wire $not$libresoc.v:174220$11928_Y - attribute \src "libresoc.v:174214.18-174214.99" - wire $or$libresoc.v:174214$11922_Y - attribute \src "libresoc.v:174216.18-174216.100" - wire $or$libresoc.v:174216$11924_Y - attribute \src "libresoc.v:174219.17-174219.98" - wire $or$libresoc.v:174219$11927_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174178.7-174178.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174213$11921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174213$11921_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174218$11926 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174218$11926_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174215$11923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174215$11923_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174217$11925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174217$11925_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174220$11928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174220$11928_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174214$11922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174214$11922_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174216$11924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174216$11924_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174219$11927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174219$11927_Y + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:174178.7-174178.20" - process $proc$libresoc.v:174178$11933 + attribute \src "libresoc.v:35178.3-35214.6" + process $proc$libresoc.v:35178$764 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174200.7-174200.19" - process $proc$libresoc.v:174200$11934 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:35179.5-35179.29" + switch \initial + attribute \src "libresoc.v:35179.9-35179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174221.3-174222.27" - process $proc$libresoc.v:174221$11929 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:174223.3-174231.6" - process $proc$libresoc.v:174223$11930 + attribute \src "libresoc.v:35215.3-35251.6" + process $proc$libresoc.v:35215$765 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11931 $1\q_int$next[0:0]$11932 - attribute \src "libresoc.v:174224.5-174224.29" + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:35216.5-35216.29" switch \initial - attribute \src "libresoc.v:174224.9-174224.17" + attribute \src "libresoc.v:35216.9-35216.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$11932 1'0 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 case - assign $1\q_int$next[0:0]$11932 \$5 + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$11931 - end - connect \$9 $and$libresoc.v:174213$11921_Y - connect \$11 $or$libresoc.v:174214$11922_Y - connect \$13 $not$libresoc.v:174215$11923_Y - connect \$15 $or$libresoc.v:174216$11924_Y - connect \$1 $not$libresoc.v:174217$11925_Y - connect \$3 $and$libresoc.v:174218$11926_Y - connect \$5 $or$libresoc.v:174219$11927_Y - connect \$7 $not$libresoc.v:174220$11928_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174239.1-174297.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" -attribute \generator "nMigen" -module \rok_l$14 - attribute \src "libresoc.v:174240.7-174240.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174285.3-174293.6" - wire $0\q_int$next[0:0]$11945 - attribute \src "libresoc.v:174283.3-174284.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174285.3-174293.6" - wire $1\q_int$next[0:0]$11946 - attribute \src "libresoc.v:174262.7-174262.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174275.17-174275.96" - wire $and$libresoc.v:174275$11935_Y - attribute \src "libresoc.v:174280.17-174280.96" - wire $and$libresoc.v:174280$11940_Y - attribute \src "libresoc.v:174277.18-174277.94" - wire $not$libresoc.v:174277$11937_Y - attribute \src "libresoc.v:174279.17-174279.93" - wire $not$libresoc.v:174279$11939_Y - attribute \src "libresoc.v:174282.17-174282.93" - wire $not$libresoc.v:174282$11942_Y - attribute \src "libresoc.v:174276.18-174276.99" - wire $or$libresoc.v:174276$11936_Y - attribute \src "libresoc.v:174278.18-174278.100" - wire $or$libresoc.v:174278$11938_Y - attribute \src "libresoc.v:174281.17-174281.98" - wire $or$libresoc.v:174281$11941_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174240.7-174240.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174275$11935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174275$11935_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174280$11940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174280$11940_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174277$11937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174277$11937_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174279$11939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174279$11939_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174282$11942 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174282$11942_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174276$11936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174276$11936_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174278$11938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174278$11938_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174281$11941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174281$11941_Y - end - attribute \src "libresoc.v:174240.7-174240.20" - process $proc$libresoc.v:174240$11947 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174262.7-174262.19" - process $proc$libresoc.v:174262$11948 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174283.3-174284.27" - process $proc$libresoc.v:174283$11943 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:174285.3-174293.6" - process $proc$libresoc.v:174285$11944 + attribute \src "libresoc.v:35252.3-35288.6" + process $proc$libresoc.v:35252$766 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11945 $1\q_int$next[0:0]$11946 - attribute \src "libresoc.v:174286.5-174286.29" + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:35253.5-35253.29" switch \initial - attribute \src "libresoc.v:174286.9-174286.17" + attribute \src "libresoc.v:35253.9-35253.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$11946 1'0 + assign $1\dec31_dec_sub28_br[0:0] 1'0 case - assign $1\q_int$next[0:0]$11946 \$5 + assign $1\dec31_dec_sub28_br[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$11945 - end - connect \$9 $and$libresoc.v:174275$11935_Y - connect \$11 $or$libresoc.v:174276$11936_Y - connect \$13 $not$libresoc.v:174277$11937_Y - connect \$15 $or$libresoc.v:174278$11938_Y - connect \$1 $not$libresoc.v:174279$11939_Y - connect \$3 $and$libresoc.v:174280$11940_Y - connect \$5 $or$libresoc.v:174281$11941_Y - connect \$7 $not$libresoc.v:174282$11942_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174301.1-174359.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" -attribute \generator "nMigen" -module \rok_l$27 - attribute \src "libresoc.v:174302.7-174302.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174347.3-174355.6" - wire $0\q_int$next[0:0]$11959 - attribute \src "libresoc.v:174345.3-174346.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174347.3-174355.6" - wire $1\q_int$next[0:0]$11960 - attribute \src "libresoc.v:174324.7-174324.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174337.17-174337.96" - wire $and$libresoc.v:174337$11949_Y - attribute \src "libresoc.v:174342.17-174342.96" - wire $and$libresoc.v:174342$11954_Y - attribute \src "libresoc.v:174339.18-174339.94" - wire $not$libresoc.v:174339$11951_Y - attribute \src "libresoc.v:174341.17-174341.93" - wire $not$libresoc.v:174341$11953_Y - attribute \src "libresoc.v:174344.17-174344.93" - wire $not$libresoc.v:174344$11956_Y - attribute \src "libresoc.v:174338.18-174338.99" - wire $or$libresoc.v:174338$11950_Y - attribute \src "libresoc.v:174340.18-174340.100" - wire $or$libresoc.v:174340$11952_Y - attribute \src "libresoc.v:174343.17-174343.98" - wire $or$libresoc.v:174343$11955_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174302.7-174302.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174337$11949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174337$11949_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174342$11954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174342$11954_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174339$11951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174339$11951_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174341$11953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174341$11953_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174344$11956 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174344$11956_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174338$11950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174338$11950_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174340$11952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174340$11952_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174343$11955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174343$11955_Y - end - attribute \src "libresoc.v:174302.7-174302.20" - process $proc$libresoc.v:174302$11961 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174324.7-174324.19" - process $proc$libresoc.v:174324$11962 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174345.3-174346.27" - process $proc$libresoc.v:174345$11957 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:174347.3-174355.6" - process $proc$libresoc.v:174347$11958 + attribute \src "libresoc.v:35289.3-35325.6" + process $proc$libresoc.v:35289$767 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11959 $1\q_int$next[0:0]$11960 - attribute \src "libresoc.v:174348.5-174348.29" + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:35290.5-35290.29" switch \initial - attribute \src "libresoc.v:174348.9-174348.17" + attribute \src "libresoc.v:35290.9-35290.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$11960 1'0 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 case - assign $1\q_int$next[0:0]$11960 \$5 + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$11959 - end - connect \$9 $and$libresoc.v:174337$11949_Y - connect \$11 $or$libresoc.v:174338$11950_Y - connect \$13 $not$libresoc.v:174339$11951_Y - connect \$15 $or$libresoc.v:174340$11952_Y - connect \$1 $not$libresoc.v:174341$11953_Y - connect \$3 $and$libresoc.v:174342$11954_Y - connect \$5 $or$libresoc.v:174343$11955_Y - connect \$7 $not$libresoc.v:174344$11956_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174363.1-174421.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" -attribute \generator "nMigen" -module \rok_l$43 - attribute \src "libresoc.v:174364.7-174364.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174409.3-174417.6" - wire $0\q_int$next[0:0]$11973 - attribute \src "libresoc.v:174407.3-174408.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174409.3-174417.6" - wire $1\q_int$next[0:0]$11974 - attribute \src "libresoc.v:174386.7-174386.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174399.17-174399.96" - wire $and$libresoc.v:174399$11963_Y - attribute \src "libresoc.v:174404.17-174404.96" - wire $and$libresoc.v:174404$11968_Y - attribute \src "libresoc.v:174401.18-174401.94" - wire $not$libresoc.v:174401$11965_Y - attribute \src "libresoc.v:174403.17-174403.93" - wire $not$libresoc.v:174403$11967_Y - attribute \src "libresoc.v:174406.17-174406.93" - wire $not$libresoc.v:174406$11970_Y - attribute \src "libresoc.v:174400.18-174400.99" - wire $or$libresoc.v:174400$11964_Y - attribute \src "libresoc.v:174402.18-174402.100" - wire $or$libresoc.v:174402$11966_Y - attribute \src "libresoc.v:174405.17-174405.98" - wire $or$libresoc.v:174405$11969_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174364.7-174364.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174399$11963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174399$11963_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174404$11968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174404$11968_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174401$11965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174401$11965_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174403$11967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174403$11967_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174406$11970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174406$11970_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174400$11964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174400$11964_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174402$11966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174402$11966_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174405$11969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174405$11969_Y - end - attribute \src "libresoc.v:174364.7-174364.20" - process $proc$libresoc.v:174364$11975 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174386.7-174386.19" - process $proc$libresoc.v:174386$11976 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174407.3-174408.27" - process $proc$libresoc.v:174407$11971 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:174409.3-174417.6" - process $proc$libresoc.v:174409$11972 + attribute \src "libresoc.v:35326.3-35362.6" + process $proc$libresoc.v:35326$768 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11973 $1\q_int$next[0:0]$11974 - attribute \src "libresoc.v:174410.5-174410.29" + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:35327.5-35327.29" switch \initial - attribute \src "libresoc.v:174410.9-174410.17" + attribute \src "libresoc.v:35327.9-35327.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$11974 1'0 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 case - assign $1\q_int$next[0:0]$11974 \$5 + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 end sync always - update \q_int$next $0\q_int$next[0:0]$11973 - end - connect \$9 $and$libresoc.v:174399$11963_Y - connect \$11 $or$libresoc.v:174400$11964_Y - connect \$13 $not$libresoc.v:174401$11965_Y - connect \$15 $or$libresoc.v:174402$11966_Y - connect \$1 $not$libresoc.v:174403$11967_Y - connect \$3 $and$libresoc.v:174404$11968_Y - connect \$5 $or$libresoc.v:174405$11969_Y - connect \$7 $not$libresoc.v:174406$11970_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174425.1-174483.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" -attribute \generator "nMigen" -module \rok_l$59 - attribute \src "libresoc.v:174426.7-174426.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174471.3-174479.6" - wire $0\q_int$next[0:0]$11987 - attribute \src "libresoc.v:174469.3-174470.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174471.3-174479.6" - wire $1\q_int$next[0:0]$11988 - attribute \src "libresoc.v:174448.7-174448.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174461.17-174461.96" - wire $and$libresoc.v:174461$11977_Y - attribute \src "libresoc.v:174466.17-174466.96" - wire $and$libresoc.v:174466$11982_Y - attribute \src "libresoc.v:174463.18-174463.94" - wire $not$libresoc.v:174463$11979_Y - attribute \src "libresoc.v:174465.17-174465.93" - wire $not$libresoc.v:174465$11981_Y - attribute \src "libresoc.v:174468.17-174468.93" - wire $not$libresoc.v:174468$11984_Y - attribute \src "libresoc.v:174462.18-174462.99" - wire $or$libresoc.v:174462$11978_Y - attribute \src "libresoc.v:174464.18-174464.100" - wire $or$libresoc.v:174464$11980_Y - attribute \src "libresoc.v:174467.17-174467.98" - wire $or$libresoc.v:174467$11983_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174426.7-174426.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174461$11977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174461$11977_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174466$11982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174466$11982_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174463$11979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174463$11979_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174465$11981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174465$11981_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174468$11984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174468$11984_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174462$11978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174462$11978_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174464$11980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174464$11980_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174467$11983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174467$11983_Y - end - attribute \src "libresoc.v:174426.7-174426.20" - process $proc$libresoc.v:174426$11989 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174448.7-174448.19" - process $proc$libresoc.v:174448$11990 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174469.3-174470.27" - process $proc$libresoc.v:174469$11985 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:174471.3-174479.6" - process $proc$libresoc.v:174471$11986 + attribute \src "libresoc.v:35363.3-35399.6" + process $proc$libresoc.v:35363$769 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$11987 $1\q_int$next[0:0]$11988 - attribute \src "libresoc.v:174472.5-174472.29" + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:35364.5-35364.29" switch \initial - attribute \src "libresoc.v:174472.9-174472.17" + attribute \src "libresoc.v:35364.9-35364.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$11988 1'0 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 case - assign $1\q_int$next[0:0]$11988 \$5 + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$11987 - end - connect \$9 $and$libresoc.v:174461$11977_Y - connect \$11 $or$libresoc.v:174462$11978_Y - connect \$13 $not$libresoc.v:174463$11979_Y - connect \$15 $or$libresoc.v:174464$11980_Y - connect \$1 $not$libresoc.v:174465$11981_Y - connect \$3 $and$libresoc.v:174466$11982_Y - connect \$5 $or$libresoc.v:174467$11983_Y - connect \$7 $not$libresoc.v:174468$11984_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174487.1-174545.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" -attribute \generator "nMigen" -module \rok_l$71 - attribute \src "libresoc.v:174488.7-174488.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174533.3-174541.6" - wire $0\q_int$next[0:0]$12001 - attribute \src "libresoc.v:174531.3-174532.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174533.3-174541.6" - wire $1\q_int$next[0:0]$12002 - attribute \src "libresoc.v:174510.7-174510.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174523.17-174523.96" - wire $and$libresoc.v:174523$11991_Y - attribute \src "libresoc.v:174528.17-174528.96" - wire $and$libresoc.v:174528$11996_Y - attribute \src "libresoc.v:174525.18-174525.94" - wire $not$libresoc.v:174525$11993_Y - attribute \src "libresoc.v:174527.17-174527.93" - wire $not$libresoc.v:174527$11995_Y - attribute \src "libresoc.v:174530.17-174530.93" - wire $not$libresoc.v:174530$11998_Y - attribute \src "libresoc.v:174524.18-174524.99" - wire $or$libresoc.v:174524$11992_Y - attribute \src "libresoc.v:174526.18-174526.100" - wire $or$libresoc.v:174526$11994_Y - attribute \src "libresoc.v:174529.17-174529.98" - wire $or$libresoc.v:174529$11997_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174488.7-174488.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174523$11991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174523$11991_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174528$11996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174528$11996_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174525$11993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174525$11993_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174527$11995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174527$11995_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174530$11998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174530$11998_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174524$11992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174524$11992_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174526$11994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174526$11994_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174529$11997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rdok - connect \Y $or$libresoc.v:174529$11997_Y - end - attribute \src "libresoc.v:174488.7-174488.20" - process $proc$libresoc.v:174488$12003 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174510.7-174510.19" - process $proc$libresoc.v:174510$12004 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:174531.3-174532.27" - process $proc$libresoc.v:174531$11999 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:174533.3-174541.6" - process $proc$libresoc.v:174533$12000 + attribute \src "libresoc.v:35400.3-35436.6" + process $proc$libresoc.v:35400$770 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12001 $1\q_int$next[0:0]$12002 - attribute \src "libresoc.v:174534.5-174534.29" + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:35401.5-35401.29" switch \initial - attribute \src "libresoc.v:174534.9-174534.17" + attribute \src "libresoc.v:35401.9-35401.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\q_int$next[0:0]$12002 1'0 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 case - assign $1\q_int$next[0:0]$12002 \$5 + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[0:0]$12001 - end - connect \$9 $and$libresoc.v:174523$11991_Y - connect \$11 $or$libresoc.v:174524$11992_Y - connect \$13 $not$libresoc.v:174525$11993_Y - connect \$15 $or$libresoc.v:174526$11994_Y - connect \$1 $not$libresoc.v:174527$11995_Y - connect \$3 $and$libresoc.v:174528$11996_Y - connect \$5 $or$libresoc.v:174529$11997_Y - connect \$7 $not$libresoc.v:174530$11998_Y - connect \qlq_rdok \$15 - connect \qn_rdok \$13 - connect \q_rdok \$11 -end -attribute \src "libresoc.v:174549.1-174607.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" -attribute \generator "nMigen" -module \rok_l$88 - attribute \src "libresoc.v:174550.7-174550.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:174595.3-174603.6" - wire $0\q_int$next[0:0]$12015 - attribute \src "libresoc.v:174593.3-174594.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:174595.3-174603.6" - wire $1\q_int$next[0:0]$12016 - attribute \src "libresoc.v:174572.7-174572.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:174585.17-174585.96" - wire $and$libresoc.v:174585$12005_Y - attribute \src "libresoc.v:174590.17-174590.96" - wire $and$libresoc.v:174590$12010_Y - attribute \src "libresoc.v:174587.18-174587.94" - wire $not$libresoc.v:174587$12007_Y - attribute \src "libresoc.v:174589.17-174589.93" - wire $not$libresoc.v:174589$12009_Y - attribute \src "libresoc.v:174592.17-174592.93" - wire $not$libresoc.v:174592$12012_Y - attribute \src "libresoc.v:174586.18-174586.99" - wire $or$libresoc.v:174586$12006_Y - attribute \src "libresoc.v:174588.18-174588.100" - wire $or$libresoc.v:174588$12008_Y - attribute \src "libresoc.v:174591.17-174591.98" - wire $or$libresoc.v:174591$12011_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174550.7-174550.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:174585$12005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:174585$12005_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:174590$12010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:174590$12010_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:174587$12007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $not$libresoc.v:174587$12007_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:174589$12009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174589$12009_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:174592$12012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $not$libresoc.v:174592$12012_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:174586$12006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rdok - connect \Y $or$libresoc.v:174586$12006_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:174588$12008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $or$libresoc.v:174588$12008_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:174591$12011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 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"/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:174797$12056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rs - connect \B \$77 - connect \Y $and$libresoc.v:174797$12056_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:174761$12019 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 7 - connect \A \mb - connect \Y $extend$libresoc.v:174761$12019_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:174777$12036 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \mb$8 [5:0] - connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:174777$12036_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" 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parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sh [5] - connect \Y $not$libresoc.v:174762$12021_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:174764$12023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_left - connect \Y $not$libresoc.v:174764$12023_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:174766$12025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \sh [5:0] - connect \Y $not$libresoc.v:174766$12025_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:174772$12031 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \left_mask_mask - connect \Y $not$libresoc.v:174772$12031_Y - end - attribute \src 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connect \Y $not$libresoc.v:174789$12048_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:174794$12053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \Y $not$libresoc.v:174794$12053_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:174796$12055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ml - connect \Y $not$libresoc.v:174796$12055_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:174775$12034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \B \right_shift - connect \Y $or$libresoc.v:174775$12034_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:174785$12044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$48 - connect \B \$54 - connect \Y $or$libresoc.v:174785$12044_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:174786$12045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $or$libresoc.v:174786$12045_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:174788$12047 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \mr - connect \B \ml - connect \Y $or$libresoc.v:174788$12047_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:174791$12050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$60 - connect \B \$66 - connect \Y $or$libresoc.v:174791$12050_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:174795$12054 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rot - connect \B \$72 - connect \Y $or$libresoc.v:174795$12054_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:174761$12020 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:174761$12019_Y - connect \Y $pos$libresoc.v:174761$12020_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:174798$12057 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \$79 - connect \Y $reduce_or$libresoc.v:174798$12057_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:174768$12027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \mb$8 - connect \Y $sub$libresoc.v:174768$12027_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:174771$12030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 6'111111 - connect \B \me$13 - connect \Y $sub$libresoc.v:174771$12030_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:174799.13-174802.4" - cell \left_mask \left_mask - connect \mask \left_mask_mask - connect \shift \left_mask_shift - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:174803.14-174806.4" - cell \right_mask \right_mask - connect \mask \right_mask_mask - connect \shift \right_mask_shift - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:174807.8-174811.4" - cell \rotl \rotl - connect \a \rotl_a - connect \b \rotl_b - connect \o \rotl_o + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:174612.7-174612.20" - process $proc$libresoc.v:174612$12073 + attribute \src "libresoc.v:35474.3-35510.6" + process $proc$libresoc.v:35474$772 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:174812.3-174826.6" - process $proc$libresoc.v:174812$12058 assign { } { } - assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:174813.5-174813.29" + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:35475.5-35475.29" switch \initial - attribute \src "libresoc.v:174813.9-174813.17" + attribute \src "libresoc.v:35475.9-35475.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" - switch { \sign_ext_rs \is_32bit } + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'01110 assign { } { } - assign $1\hi32[31:0] \rs [31:0] + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 5'00011 assign { } { } - assign $1\hi32[31:0] { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case + case 5'01101 assign { } { } - assign $1\hi32[31:0] \rs [63:32] - end - sync always - update \hi32 $0\hi32[31:0] - end - attribute \src "libresoc.v:174827.3-174836.6" - process $proc$libresoc.v:174827$12059 - assign { } { } - assign { } { } - assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:174828.5-174828.29" - switch \initial - attribute \src "libresoc.v:174828.9-174828.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - switch \$22 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\right_mask_shift[6:0] \$24 [6:0] + assign $1\dec31_dec_sub28_lk[0:0] 1'0 case - assign $1\right_mask_shift[6:0] 7'0000000 + assign $1\dec31_dec_sub28_lk[0:0] 1'0 end sync always - update \right_mask_shift $0\right_mask_shift[6:0] + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:174837.3-174848.6" - process $proc$libresoc.v:174837$12060 + attribute \src "libresoc.v:35511.3-35547.6" + process $proc$libresoc.v:35511$773 + assign { } { } assign { } { } - assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:174838.5-174838.29" + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:35512.5-35512.29" switch \initial - attribute \src "libresoc.v:174838.9-174838.17" + attribute \src "libresoc.v:35512.9-35512.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - switch \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $1\mr[63:0] \right_mask_mask + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case + case 5'00001 assign { } { } - assign $1\mr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \mr $0\mr[63:0] - end - attribute \src "libresoc.v:174849.3-174860.6" - process $proc$libresoc.v:174849$12061 - assign { } { } - assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:174850.5-174850.29" - switch \initial - attribute \src "libresoc.v:174850.9-174850.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - switch \$38 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $1\output_mode[1:0] { 1'1 \$40 } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case + case 5'01111 assign { } { } - assign $1\output_mode[1:0] { 1'0 \$44 } - end - sync always - update \output_mode $0\output_mode[1:0] - end - attribute \src "libresoc.v:174861.3-174879.6" - process $proc$libresoc.v:174861$12062 - assign { } { } - assign { } { } - assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:174862.5-174862.29" - switch \initial - attribute \src "libresoc.v:174862.9-174862.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" - switch \output_mode + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 assign { } { } - assign $1\result_o[63:0] \$56 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 5'00011 assign { } { } - assign $1\result_o[63:0] \$68 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 5'01101 assign { } { } - assign $1\result_o[63:0] \$70 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\result_o[63:0] \$74 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 case - assign $1\result_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 end sync always - update \result_o $0\result_o[63:0] + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:174880.3-174889.6" - process $proc$libresoc.v:174880$12063 + attribute \src "libresoc.v:35548.3-35584.6" + process $proc$libresoc.v:35548$774 assign { } { } assign { } { } - assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:174881.5-174881.29" + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:35549.5-35549.29" switch \initial - attribute \src "libresoc.v:174881.9-174881.17" + attribute \src "libresoc.v:35549.9-35549.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" - switch \output_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 5'00000 assign { } { } - assign $1\carry_out_o[0:0] \$76 - case - assign $1\carry_out_o[0:0] 1'0 - end - sync always - update \carry_out_o $0\carry_out_o[0:0] - end - attribute \src "libresoc.v:174890.3-174901.6" - process $proc$libresoc.v:174890$12064 - assign { } { } - assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:174891.5-174891.29" - switch \initial - attribute \src "libresoc.v:174891.9-174891.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" - switch \right_shift + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $1\rot_count[5:0] \$1 [5:0] + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case + case 5'00111 assign { } { } - assign $1\rot_count[5:0] \shift [5:0] - end - sync always - update \rot_count $0\rot_count[5:0] - end - attribute \src "libresoc.v:174902.3-174935.6" - process $proc$libresoc.v:174902$12065 - assign { } { } - assign $0\mb$8[6:0]$12066 $1\mb$8[6:0]$12067 - attribute \src "libresoc.v:174903.5-174903.29" - switch \initial - attribute \src "libresoc.v:174903.9-174903.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" - switch { \right_shift \clear_left } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'01111 assign { } { } - assign $1\mb$8[6:0]$12067 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12067 [6:5] $2\mb$8[6:5]$12068 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" - switch \is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\mb$8[6:5]$12068 2'01 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\mb$8[6:5]$12068 { 1'0 \mb_extra } - end + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 5'01000 assign { } { } - assign $1\mb$8[6:0]$12067 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12067 [6:5] $3\mb$8[6:5]$12069 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" - switch \is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\mb$8[6:5]$12069 { \sh [5] \$11 } - case - assign $3\mb$8[6:5]$12069 \sh [6:5] - end + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case + case 5'01110 assign { } { } - assign $1\mb$8[6:0]$12067 { 1'0 \is_32bit 5'00000 } - end - sync always - update \mb$8 $0\mb$8[6:0]$12066 - end - attribute \src "libresoc.v:174936.3-174950.6" - process $proc$libresoc.v:174936$12070 - assign { } { } - assign $0\me$13[6:0]$12071 $1\me$13[6:0]$12072 - attribute \src "libresoc.v:174937.5-174937.29" - switch \initial - attribute \src "libresoc.v:174937.9-174937.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - switch { \$18 \$14 } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 2'-1 + case 5'00011 assign { } { } - assign $1\me$13[6:0]$12072 { 2'01 \me } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 2'1- + case 5'01101 assign { } { } - assign $1\me$13[6:0]$12072 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12072 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12071 - end - connect \$9 $pos$libresoc.v:174761$12020_Y - connect \$11 $not$libresoc.v:174762$12021_Y - connect \$14 $and$libresoc.v:174763$12022_Y - connect \$16 $not$libresoc.v:174764$12023_Y - connect \$18 $and$libresoc.v:174765$12024_Y - connect \$20 $not$libresoc.v:174766$12025_Y - connect \$22 $le$libresoc.v:174767$12026_Y - connect \$25 $sub$libresoc.v:174768$12027_Y - connect \$27 $le$libresoc.v:174769$12028_Y - connect \$2 $neg$libresoc.v:174770$12029_Y - connect \$30 $sub$libresoc.v:174771$12030_Y - connect \$32 $not$libresoc.v:174772$12031_Y - connect \$34 $not$libresoc.v:174773$12032_Y - connect \$36 $and$libresoc.v:174774$12033_Y - connect \$38 $or$libresoc.v:174775$12034_Y - connect \$40 $and$libresoc.v:174776$12035_Y - connect \$42 $gt$libresoc.v:174777$12036_Y - connect \$44 $and$libresoc.v:174778$12037_Y - connect \$46 $and$libresoc.v:174779$12038_Y - connect \$48 $and$libresoc.v:174780$12039_Y - connect \$4 $not$libresoc.v:174781$12040_Y - connect \$51 $and$libresoc.v:174782$12041_Y - connect \$50 $not$libresoc.v:174783$12042_Y - connect \$54 $and$libresoc.v:174784$12043_Y - connect \$56 $or$libresoc.v:174785$12044_Y - connect \$58 $or$libresoc.v:174786$12045_Y - connect \$60 $and$libresoc.v:174787$12046_Y - connect \$63 $or$libresoc.v:174788$12047_Y - connect \$62 $not$libresoc.v:174789$12048_Y - connect \$66 $and$libresoc.v:174790$12049_Y - connect \$68 $or$libresoc.v:174791$12050_Y - connect \$6 $and$libresoc.v:174792$12051_Y - connect \$70 $and$libresoc.v:174793$12052_Y - connect \$72 $not$libresoc.v:174794$12053_Y - connect \$74 $or$libresoc.v:174795$12054_Y - connect \$77 $not$libresoc.v:174796$12055_Y - connect \$79 $and$libresoc.v:174797$12056_Y - connect \$76 $reduce_or$libresoc.v:174798$12057_Y - connect \$1 \$2 - connect \$24 \$25 - connect \$29 \$30 - connect \ml \$32 - connect \left_mask_shift \$30 [6:0] - connect \sh { \$6 \shift [5:0] } - connect \rot \rotl_o - connect \rotl_b \rot_count - connect \rotl_a \repl32 - connect \shift_signed \shift [5:0] - connect \repl32 { \hi32 \rs [31:0] } -end -attribute \src "libresoc.v:174966.1-174980.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" -attribute \generator "nMigen" -module \rotl - attribute \src "libresoc.v:174978.17-174978.32" - wire width 128 $shr$libresoc.v:174978$12075_Y - attribute \src "libresoc.v:174977.17-174977.100" - wire width 8 $sub$libresoc.v:174977$12074_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" - wire width 64 \$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - wire width 8 \$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" - wire width 64 input 3 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" - wire width 6 input 1 \b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" - wire width 64 output 2 \o - attribute \src "libresoc.v:174978.17-174978.32" - cell $shr $shr$libresoc.v:174978$12075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 128 - connect \A { \a \a } - connect \B \$2 - connect \Y $shr$libresoc.v:174978$12075_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:174977$12074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \b - connect \Y $sub$libresoc.v:174977$12074_Y - end - connect \$2 $sub$libresoc.v:174977$12074_Y - connect \$1 $shr$libresoc.v:174978$12075_Y [63:0] - connect \o \$1 -end -attribute \src "libresoc.v:174984.1-175042.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" -attribute \generator "nMigen" -module \rst_l - attribute \src "libresoc.v:174985.7-174985.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175030.3-175038.6" - wire $0\q_int$next[0:0]$12086 - attribute \src "libresoc.v:175028.3-175029.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175030.3-175038.6" - wire $1\q_int$next[0:0]$12087 - attribute \src "libresoc.v:175007.7-175007.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175020.17-175020.96" - wire $and$libresoc.v:175020$12076_Y - attribute \src "libresoc.v:175025.17-175025.96" - wire $and$libresoc.v:175025$12081_Y - attribute \src "libresoc.v:175022.18-175022.93" - wire $not$libresoc.v:175022$12078_Y - attribute \src "libresoc.v:175024.17-175024.92" - wire $not$libresoc.v:175024$12080_Y - attribute \src "libresoc.v:175027.17-175027.92" - wire $not$libresoc.v:175027$12083_Y - attribute \src "libresoc.v:175021.18-175021.98" - wire $or$libresoc.v:175021$12077_Y - attribute \src "libresoc.v:175023.18-175023.99" - wire $or$libresoc.v:175023$12079_Y - attribute \src "libresoc.v:175026.17-175026.97" - wire $or$libresoc.v:175026$12082_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:174985.7-174985.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175020$12076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175020$12076_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175025$12081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175025$12081_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175022$12078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175022$12078_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175024$12080 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175024$12080_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175027$12083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175027$12083_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175021$12077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175021$12077_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175023$12079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175023$12079_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175026$12082 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175026$12082_Y - end - attribute \src "libresoc.v:174985.7-174985.20" - process $proc$libresoc.v:174985$12088 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175007.7-175007.19" - process $proc$libresoc.v:175007$12089 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175028.3-175029.27" - process $proc$libresoc.v:175028$12084 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:175030.3-175038.6" - process $proc$libresoc.v:175030$12085 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$12086 $1\q_int$next[0:0]$12087 - attribute \src "libresoc.v:175031.5-175031.29" - switch \initial - attribute \src "libresoc.v:175031.9-175031.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $1\q_int$next[0:0]$12087 1'0 - case - assign $1\q_int$next[0:0]$12087 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$12086 - end - connect \$9 $and$libresoc.v:175020$12076_Y - connect \$11 $or$libresoc.v:175021$12077_Y - connect \$13 $not$libresoc.v:175022$12078_Y - connect \$15 $or$libresoc.v:175023$12079_Y - connect \$1 $not$libresoc.v:175024$12080_Y - connect \$3 $and$libresoc.v:175025$12081_Y - connect \$5 $or$libresoc.v:175026$12082_Y - connect \$7 $not$libresoc.v:175027$12083_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "libresoc.v:175046.1-175104.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" -attribute \generator "nMigen" -module \rst_l$104 - attribute \src "libresoc.v:175047.7-175047.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175092.3-175100.6" - wire $0\q_int$next[0:0]$12100 - attribute \src "libresoc.v:175090.3-175091.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175092.3-175100.6" - wire $1\q_int$next[0:0]$12101 - attribute \src "libresoc.v:175069.7-175069.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175082.17-175082.96" - wire $and$libresoc.v:175082$12090_Y - attribute \src "libresoc.v:175087.17-175087.96" - wire $and$libresoc.v:175087$12095_Y - attribute \src "libresoc.v:175084.18-175084.93" - wire $not$libresoc.v:175084$12092_Y - attribute \src "libresoc.v:175086.17-175086.92" - wire $not$libresoc.v:175086$12094_Y - attribute \src "libresoc.v:175089.17-175089.92" - wire $not$libresoc.v:175089$12097_Y - attribute \src "libresoc.v:175083.18-175083.98" - wire $or$libresoc.v:175083$12091_Y - attribute \src "libresoc.v:175085.18-175085.99" - wire $or$libresoc.v:175085$12093_Y - attribute \src "libresoc.v:175088.17-175088.97" - wire $or$libresoc.v:175088$12096_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:175047.7-175047.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175082$12090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175082$12090_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175087$12095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175087$12095_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175084$12092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175084$12092_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175086$12094 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175086$12094_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175089$12097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175089$12097_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175083$12091 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175083$12091_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175085$12093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175085$12093_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175088$12096 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175088$12096_Y - end - attribute \src "libresoc.v:175047.7-175047.20" - process $proc$libresoc.v:175047$12102 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175069.7-175069.19" - process $proc$libresoc.v:175069$12103 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175090.3-175091.27" - process $proc$libresoc.v:175090$12098 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:175092.3-175100.6" - process $proc$libresoc.v:175092$12099 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$12100 $1\q_int$next[0:0]$12101 - attribute \src "libresoc.v:175093.5-175093.29" - switch \initial - attribute \src "libresoc.v:175093.9-175093.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub28_form[4:0] 5'01000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$12101 1'0 + assign $1\dec31_dec_sub28_form[4:0] 5'01000 case - assign $1\q_int$next[0:0]$12101 \$5 + assign $1\dec31_dec_sub28_form[4:0] 5'00000 end sync always - update \q_int$next $0\q_int$next[0:0]$12100 - end - connect \$9 $and$libresoc.v:175082$12090_Y - connect \$11 $or$libresoc.v:175083$12091_Y - connect \$13 $not$libresoc.v:175084$12092_Y - connect \$15 $or$libresoc.v:175085$12093_Y - connect \$1 $not$libresoc.v:175086$12094_Y - connect \$3 $and$libresoc.v:175087$12095_Y - connect \$5 $or$libresoc.v:175088$12096_Y - connect \$7 $not$libresoc.v:175089$12097_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "libresoc.v:175108.1-175166.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" -attribute \generator "nMigen" -module \rst_l$122 - attribute \src "libresoc.v:175109.7-175109.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175154.3-175162.6" - wire $0\q_int$next[0:0]$12114 - attribute \src "libresoc.v:175152.3-175153.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175154.3-175162.6" - wire $1\q_int$next[0:0]$12115 - attribute \src "libresoc.v:175131.7-175131.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175144.17-175144.96" - wire $and$libresoc.v:175144$12104_Y - attribute \src "libresoc.v:175149.17-175149.96" - wire $and$libresoc.v:175149$12109_Y - attribute \src "libresoc.v:175146.18-175146.93" - wire $not$libresoc.v:175146$12106_Y - attribute \src "libresoc.v:175148.17-175148.92" - wire $not$libresoc.v:175148$12108_Y - attribute \src "libresoc.v:175151.17-175151.92" - wire $not$libresoc.v:175151$12111_Y - attribute \src "libresoc.v:175145.18-175145.98" - wire $or$libresoc.v:175145$12105_Y - attribute \src "libresoc.v:175147.18-175147.99" - wire $or$libresoc.v:175147$12107_Y - attribute \src "libresoc.v:175150.17-175150.97" - wire $or$libresoc.v:175150$12110_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:175109.7-175109.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175144$12104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175144$12104_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175149$12109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175149$12109_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175146$12106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175146$12106_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175148$12108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175148$12108_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175151$12111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175151$12111_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175145$12105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175145$12105_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175147$12107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175147$12107_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175150$12110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175150$12110_Y - end - attribute \src "libresoc.v:175109.7-175109.20" - process $proc$libresoc.v:175109$12116 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175131.7-175131.19" - process $proc$libresoc.v:175131$12117 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175152.3-175153.27" - process $proc$libresoc.v:175152$12112 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:175154.3-175162.6" - process $proc$libresoc.v:175154$12113 + attribute \src "libresoc.v:35585.3-35621.6" + process $proc$libresoc.v:35585$775 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12114 $1\q_int$next[0:0]$12115 - attribute \src "libresoc.v:175155.5-175155.29" + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:35586.5-35586.29" switch \initial - attribute \src "libresoc.v:175155.9-175155.17" + attribute \src "libresoc.v:35586.9-35586.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $1\q_int$next[0:0]$12115 1'0 - case - assign $1\q_int$next[0:0]$12115 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$12114 - end - connect \$9 $and$libresoc.v:175144$12104_Y - connect \$11 $or$libresoc.v:175145$12105_Y - connect \$13 $not$libresoc.v:175146$12106_Y - connect \$15 $or$libresoc.v:175147$12107_Y - connect \$1 $not$libresoc.v:175148$12108_Y - connect \$3 $and$libresoc.v:175149$12109_Y - connect \$5 $or$libresoc.v:175150$12110_Y - connect \$7 $not$libresoc.v:175151$12111_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "libresoc.v:175170.1-175228.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" -attribute \generator "nMigen" -module \rst_l$129 - attribute \src "libresoc.v:175171.7-175171.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175216.3-175224.6" - wire $0\q_int$next[0:0]$12128 - attribute \src "libresoc.v:175214.3-175215.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175216.3-175224.6" - wire $1\q_int$next[0:0]$12129 - attribute \src "libresoc.v:175193.7-175193.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175206.17-175206.96" - wire $and$libresoc.v:175206$12118_Y - attribute \src "libresoc.v:175211.17-175211.96" - wire $and$libresoc.v:175211$12123_Y - attribute \src "libresoc.v:175208.18-175208.93" - wire $not$libresoc.v:175208$12120_Y - attribute \src "libresoc.v:175210.17-175210.92" - wire $not$libresoc.v:175210$12122_Y - attribute \src "libresoc.v:175213.17-175213.92" - wire $not$libresoc.v:175213$12125_Y - attribute \src "libresoc.v:175207.18-175207.98" - wire $or$libresoc.v:175207$12119_Y - attribute \src "libresoc.v:175209.18-175209.99" - wire $or$libresoc.v:175209$12121_Y - attribute \src "libresoc.v:175212.17-175212.97" - wire $or$libresoc.v:175212$12124_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:175171.7-175171.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175206$12118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175206$12118_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175211$12123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175211$12123_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175208$12120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175208$12120_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175210$12122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175210$12122_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175213$12125 - parameter \A_SIGNED 0 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\Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175275$12139_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175269$12133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175269$12133_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175271$12135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175271$12135_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175274$12138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y 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\Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175337$12153_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175331$12147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175331$12147_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175333$12149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175333$12149_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175336$12152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175336$12152_Y - end - attribute \src "libresoc.v:175295.7-175295.20" - process $proc$libresoc.v:175295$12158 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175317.7-175317.19" - process $proc$libresoc.v:175317$12159 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175338.3-175339.27" - process $proc$libresoc.v:175338$12154 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:175340.3-175348.6" - process $proc$libresoc.v:175340$12155 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$12156 $1\q_int$next[0:0]$12157 - attribute \src "libresoc.v:175341.5-175341.29" - switch \initial - attribute \src "libresoc.v:175341.9-175341.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 assign { } { } - assign $1\q_int$next[0:0]$12157 1'0 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 case - assign $1\q_int$next[0:0]$12157 \$5 + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 end sync always - update \q_int$next $0\q_int$next[0:0]$12156 - end - connect \$9 $and$libresoc.v:175330$12146_Y - connect \$11 $or$libresoc.v:175331$12147_Y - connect \$13 $not$libresoc.v:175332$12148_Y - connect \$15 $or$libresoc.v:175333$12149_Y - connect \$1 $not$libresoc.v:175334$12150_Y - connect \$3 $and$libresoc.v:175335$12151_Y - connect \$5 $or$libresoc.v:175336$12152_Y - connect \$7 $not$libresoc.v:175337$12153_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "libresoc.v:175356.1-175414.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" -attribute \generator "nMigen" -module \rst_l$42 - attribute \src "libresoc.v:175357.7-175357.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175402.3-175410.6" - wire $0\q_int$next[0:0]$12170 - attribute \src "libresoc.v:175400.3-175401.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175402.3-175410.6" - wire $1\q_int$next[0:0]$12171 - attribute \src "libresoc.v:175379.7-175379.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175392.17-175392.96" - wire $and$libresoc.v:175392$12160_Y - attribute \src "libresoc.v:175397.17-175397.96" - wire $and$libresoc.v:175397$12165_Y - attribute \src "libresoc.v:175394.18-175394.93" - wire $not$libresoc.v:175394$12162_Y - attribute \src "libresoc.v:175396.17-175396.92" - wire $not$libresoc.v:175396$12164_Y - attribute \src "libresoc.v:175399.17-175399.92" - wire $not$libresoc.v:175399$12167_Y - attribute \src "libresoc.v:175393.18-175393.98" - wire $or$libresoc.v:175393$12161_Y - attribute \src "libresoc.v:175395.18-175395.99" - wire $or$libresoc.v:175395$12163_Y - attribute \src "libresoc.v:175398.17-175398.97" - wire $or$libresoc.v:175398$12166_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:175357.7-175357.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175392$12160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175392$12160_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175397$12165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175397$12165_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175394$12162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175394$12162_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175396$12164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175396$12164_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175399$12167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175399$12167_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175393$12161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175393$12161_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175395$12163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175395$12163_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175398$12166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175398$12166_Y - end - attribute \src "libresoc.v:175357.7-175357.20" - process $proc$libresoc.v:175357$12172 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175379.7-175379.19" - process $proc$libresoc.v:175379$12173 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175400.3-175401.27" - process $proc$libresoc.v:175400$12168 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:175402.3-175410.6" - process $proc$libresoc.v:175402$12169 + attribute \src "libresoc.v:35622.3-35658.6" + process $proc$libresoc.v:35622$776 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12170 $1\q_int$next[0:0]$12171 - attribute \src "libresoc.v:175403.5-175403.29" + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:35623.5-35623.29" switch \initial - attribute \src "libresoc.v:175403.9-175403.17" + attribute \src "libresoc.v:35623.9-35623.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign $1\q_int$next[0:0]$12171 1'0 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 case - assign $1\q_int$next[0:0]$12171 \$5 + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 end sync always - update \q_int$next $0\q_int$next[0:0]$12170 - end - connect \$9 $and$libresoc.v:175392$12160_Y - connect \$11 $or$libresoc.v:175393$12161_Y - connect \$13 $not$libresoc.v:175394$12162_Y - connect \$15 $or$libresoc.v:175395$12163_Y - connect \$1 $not$libresoc.v:175396$12164_Y - connect \$3 $and$libresoc.v:175397$12165_Y - connect \$5 $or$libresoc.v:175398$12166_Y - connect \$7 $not$libresoc.v:175399$12167_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "libresoc.v:175418.1-175476.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" -attribute \generator "nMigen" -module \rst_l$58 - attribute \src "libresoc.v:175419.7-175419.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175464.3-175472.6" - wire $0\q_int$next[0:0]$12184 - attribute \src "libresoc.v:175462.3-175463.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175464.3-175472.6" - wire $1\q_int$next[0:0]$12185 - attribute \src "libresoc.v:175441.7-175441.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175454.17-175454.96" - wire $and$libresoc.v:175454$12174_Y - attribute \src "libresoc.v:175459.17-175459.96" - wire $and$libresoc.v:175459$12179_Y - attribute \src "libresoc.v:175456.18-175456.93" - wire $not$libresoc.v:175456$12176_Y - attribute \src "libresoc.v:175458.17-175458.92" - wire $not$libresoc.v:175458$12178_Y - attribute \src "libresoc.v:175461.17-175461.92" - wire $not$libresoc.v:175461$12181_Y - attribute \src "libresoc.v:175455.18-175455.98" - wire $or$libresoc.v:175455$12175_Y - attribute \src "libresoc.v:175457.18-175457.99" - wire $or$libresoc.v:175457$12177_Y - attribute \src "libresoc.v:175460.17-175460.97" - wire $or$libresoc.v:175460$12180_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:175419.7-175419.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175454$12174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175454$12174_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175459$12179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175459$12179_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175456$12176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175456$12176_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175458$12178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175458$12178_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175461$12181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175461$12181_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175455$12175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175455$12175_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175457$12177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175457$12177_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175460$12180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175460$12180_Y - end - attribute \src "libresoc.v:175419.7-175419.20" - process $proc$libresoc.v:175419$12186 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175441.7-175441.19" - process $proc$libresoc.v:175441$12187 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175462.3-175463.27" - process $proc$libresoc.v:175462$12182 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:175464.3-175472.6" - process $proc$libresoc.v:175464$12183 + attribute \src "libresoc.v:35659.3-35695.6" + process $proc$libresoc.v:35659$777 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12184 $1\q_int$next[0:0]$12185 - attribute \src "libresoc.v:175465.5-175465.29" + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:35660.5-35660.29" switch \initial - attribute \src "libresoc.v:175465.9-175465.17" + attribute \src "libresoc.v:35660.9-35660.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign $1\q_int$next[0:0]$12185 1'0 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 case - assign $1\q_int$next[0:0]$12185 \$5 + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 end sync always - update \q_int$next $0\q_int$next[0:0]$12184 - end - connect \$9 $and$libresoc.v:175454$12174_Y - connect \$11 $or$libresoc.v:175455$12175_Y - connect \$13 $not$libresoc.v:175456$12176_Y - connect \$15 $or$libresoc.v:175457$12177_Y - connect \$1 $not$libresoc.v:175458$12178_Y - connect \$3 $and$libresoc.v:175459$12179_Y - connect \$5 $or$libresoc.v:175460$12180_Y - connect \$7 $not$libresoc.v:175461$12181_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "libresoc.v:175480.1-175538.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" -attribute \generator "nMigen" -module \rst_l$70 - attribute \src "libresoc.v:175481.7-175481.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175526.3-175534.6" - wire $0\q_int$next[0:0]$12198 - attribute \src "libresoc.v:175524.3-175525.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175526.3-175534.6" - wire $1\q_int$next[0:0]$12199 - attribute \src "libresoc.v:175503.7-175503.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175516.17-175516.96" - wire $and$libresoc.v:175516$12188_Y - attribute \src "libresoc.v:175521.17-175521.96" - wire $and$libresoc.v:175521$12193_Y - attribute \src "libresoc.v:175518.18-175518.93" - wire $not$libresoc.v:175518$12190_Y - attribute \src "libresoc.v:175520.17-175520.92" - wire $not$libresoc.v:175520$12192_Y - attribute \src "libresoc.v:175523.17-175523.92" - wire $not$libresoc.v:175523$12195_Y - attribute \src "libresoc.v:175517.18-175517.98" - wire $or$libresoc.v:175517$12189_Y - attribute \src "libresoc.v:175519.18-175519.99" - wire $or$libresoc.v:175519$12191_Y - attribute \src "libresoc.v:175522.17-175522.97" - wire $or$libresoc.v:175522$12194_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:175481.7-175481.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175516$12188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175516$12188_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175521$12193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175521$12193_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175518$12190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175518$12190_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175520$12192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175520$12192_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175523$12195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175523$12195_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175517$12189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175517$12189_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175519$12191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175519$12191_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175522$12194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175522$12194_Y - end - attribute \src "libresoc.v:175481.7-175481.20" - process $proc$libresoc.v:175481$12200 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175503.7-175503.19" - process $proc$libresoc.v:175503$12201 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175524.3-175525.27" - process $proc$libresoc.v:175524$12196 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:175526.3-175534.6" - process $proc$libresoc.v:175526$12197 + attribute \src "libresoc.v:35696.3-35732.6" + process $proc$libresoc.v:35696$778 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12198 $1\q_int$next[0:0]$12199 - attribute \src "libresoc.v:175527.5-175527.29" + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:35697.5-35697.29" switch \initial - attribute \src "libresoc.v:175527.9-175527.17" + attribute \src "libresoc.v:35697.9-35697.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } - assign $1\q_int$next[0:0]$12199 1'0 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 case - assign $1\q_int$next[0:0]$12199 \$5 + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 end sync always - update \q_int$next $0\q_int$next[0:0]$12198 - end - connect \$9 $and$libresoc.v:175516$12188_Y - connect \$11 $or$libresoc.v:175517$12189_Y - connect \$13 $not$libresoc.v:175518$12190_Y - connect \$15 $or$libresoc.v:175519$12191_Y - connect \$1 $not$libresoc.v:175520$12192_Y - connect \$3 $and$libresoc.v:175521$12193_Y - connect \$5 $or$libresoc.v:175522$12194_Y - connect \$7 $not$libresoc.v:175523$12195_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 -end -attribute \src "libresoc.v:175542.1-175600.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" -attribute \generator "nMigen" -module \rst_l$87 - attribute \src "libresoc.v:175543.7-175543.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:175588.3-175596.6" - wire $0\q_int$next[0:0]$12212 - attribute \src "libresoc.v:175586.3-175587.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:175588.3-175596.6" - wire $1\q_int$next[0:0]$12213 - attribute \src "libresoc.v:175565.7-175565.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:175578.17-175578.96" - wire $and$libresoc.v:175578$12202_Y - attribute \src "libresoc.v:175583.17-175583.96" - wire $and$libresoc.v:175583$12207_Y - attribute \src "libresoc.v:175580.18-175580.93" - wire $not$libresoc.v:175580$12204_Y - attribute \src "libresoc.v:175582.17-175582.92" - wire $not$libresoc.v:175582$12206_Y - attribute \src "libresoc.v:175585.17-175585.92" - wire $not$libresoc.v:175585$12209_Y - attribute \src "libresoc.v:175579.18-175579.98" - wire $or$libresoc.v:175579$12203_Y - attribute \src "libresoc.v:175581.18-175581.99" - wire $or$libresoc.v:175581$12205_Y - attribute \src "libresoc.v:175584.17-175584.97" - wire $or$libresoc.v:175584$12208_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:175543.7-175543.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:175578$12202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:175578$12202_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:175583$12207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:175583$12207_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:175580$12204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $not$libresoc.v:175580$12204_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:175582$12206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175582$12206_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:175585$12209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $not$libresoc.v:175585$12209_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:175579$12203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_rst - connect \Y $or$libresoc.v:175579$12203_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:175581$12205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $or$libresoc.v:175581$12205_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:175584$12208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_rst - connect \Y $or$libresoc.v:175584$12208_Y + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] end - attribute \src "libresoc.v:175543.7-175543.20" - process $proc$libresoc.v:175543$12214 + attribute \src "libresoc.v:35733.3-35769.6" + process $proc$libresoc.v:35733$779 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:175565.7-175565.19" - process $proc$libresoc.v:175565$12215 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:35734.5-35734.29" + switch \initial + attribute \src "libresoc.v:35734.9-35734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:175586.3-175587.27" - process $proc$libresoc.v:175586$12210 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:175588.3-175596.6" - process $proc$libresoc.v:175588$12211 + attribute \src "libresoc.v:35770.3-35806.6" + process $proc$libresoc.v:35770$780 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12212 $1\q_int$next[0:0]$12213 - attribute \src "libresoc.v:175589.5-175589.29" + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:35771.5-35771.29" switch \initial - attribute \src "libresoc.v:175589.9-175589.17" + attribute \src "libresoc.v:35771.9-35771.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 assign { } { } - assign $1\q_int$next[0:0]$12213 1'0 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 case - assign $1\q_int$next[0:0]$12213 \$5 + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 end sync always - update \q_int$next $0\q_int$next[0:0]$12212 + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - connect \$9 $and$libresoc.v:175578$12202_Y - connect \$11 $or$libresoc.v:175579$12203_Y - connect \$13 $not$libresoc.v:175580$12204_Y - connect \$15 $or$libresoc.v:175581$12205_Y - connect \$1 $not$libresoc.v:175582$12206_Y - connect \$3 $and$libresoc.v:175583$12207_Y - connect \$5 $or$libresoc.v:175584$12208_Y - connect \$7 $not$libresoc.v:175585$12209_Y - connect \qlq_rst \$15 - connect \qn_rst \$13 - connect \q_rst \$11 + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:175604.1-176007.10" +attribute \src "libresoc.v:35812.1-36383.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" -module \setup_stage - attribute \src "libresoc.v:175965.3-175990.6" - wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:175605.7-175605.20" +module \dec31_dec_sub4 + attribute \src "libresoc.v:36135.3-36147.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36187.3-36199.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36356.3-36368.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36369.3-36381.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36122.3-36134.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36174.3-36186.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36291.3-36303.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36070.3-36082.6" + wire width 12 $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36304.3-36316.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36317.3-36329.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36330.3-36342.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36213.3-36225.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36148.3-36160.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36161.3-36173.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36239.3-36251.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36083.3-36095.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36265.3-36277.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36343.3-36355.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36109.3-36121.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36226.3-36238.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36278.3-36290.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36252.3-36264.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36200.3-36212.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36096.3-36108.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:35813.7-35813.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175965.3-175990.6" - wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:175965.3-175990.6" - wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:175944.18-175944.122" - wire $and$libresoc.v:175944$12217_Y - attribute \src "libresoc.v:175946.18-175946.122" - wire $and$libresoc.v:175946$12219_Y - attribute \src "libresoc.v:175955.18-175955.105" - wire $and$libresoc.v:175955$12232_Y - attribute \src "libresoc.v:175958.18-175958.105" - wire $and$libresoc.v:175958$12235_Y - attribute \src "libresoc.v:175954.18-175954.123" - wire $eq$libresoc.v:175954$12231_Y - attribute \src "libresoc.v:175957.18-175957.123" - wire $eq$libresoc.v:175957$12234_Y - attribute \src "libresoc.v:175960.18-175960.117" - wire $eq$libresoc.v:175960$12237_Y - attribute \src "libresoc.v:175947.18-175947.97" - wire width 65 $extend$libresoc.v:175947$12220_Y - attribute \src "libresoc.v:175948.18-175948.91" - wire width 65 $extend$libresoc.v:175948$12222_Y - attribute \src "libresoc.v:175950.18-175950.97" - wire width 65 $extend$libresoc.v:175950$12225_Y - attribute \src "libresoc.v:175951.18-175951.91" - wire width 65 $extend$libresoc.v:175951$12227_Y - attribute \src "libresoc.v:175963.18-175963.99" - wire width 128 $extend$libresoc.v:175963$12240_Y - attribute \src "libresoc.v:175953.18-175953.112" - wire $ge$libresoc.v:175953$12230_Y - attribute \src "libresoc.v:175956.18-175956.124" - wire $ge$libresoc.v:175956$12233_Y - attribute \src "libresoc.v:175947.18-175947.97" - wire width 65 $neg$libresoc.v:175947$12221_Y - attribute \src "libresoc.v:175950.18-175950.97" - wire width 65 $neg$libresoc.v:175950$12226_Y - attribute \src "libresoc.v:175948.18-175948.91" - wire width 65 $pos$libresoc.v:175948$12223_Y - attribute \src "libresoc.v:175951.18-175951.91" - wire width 65 $pos$libresoc.v:175951$12228_Y - attribute \src "libresoc.v:175963.18-175963.99" - wire width 128 $pos$libresoc.v:175963$12241_Y - attribute \src "libresoc.v:175962.18-175962.117" - wire width 95 $sshl$libresoc.v:175962$12239_Y - attribute \src "libresoc.v:175964.18-175964.111" - wire width 191 $sshl$libresoc.v:175964$12242_Y - attribute \src "libresoc.v:175943.18-175943.131" - wire $ternary$libresoc.v:175943$12216_Y - attribute \src "libresoc.v:175945.18-175945.131" - wire $ternary$libresoc.v:175945$12218_Y - attribute \src "libresoc.v:175949.18-175949.119" - wire width 65 $ternary$libresoc.v:175949$12224_Y - attribute \src "libresoc.v:175952.18-175952.120" - wire width 65 $ternary$libresoc.v:175952$12229_Y - attribute \src "libresoc.v:175959.18-175959.130" - wire width 32 $ternary$libresoc.v:175959$12236_Y - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - wire \$57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 128 \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 95 \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" - wire width 64 \abs_dend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" - wire width 64 \abs_dor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire output 46 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire output 44 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire output 45 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 47 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire output 43 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire output 42 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:175605.7-175605.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute 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+ wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36174.3-36186.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36291.3-36303.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36070.3-36082.6" + wire width 12 $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36304.3-36316.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36317.3-36329.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36330.3-36342.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36213.3-36225.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36148.3-36160.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36161.3-36173.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36239.3-36251.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36083.3-36095.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36265.3-36277.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36343.3-36355.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36109.3-36121.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36226.3-36238.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36278.3-36290.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36252.3-36264.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36200.3-36212.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36096.3-36108.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub4_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -367140,108 +53136,39 @@ module \setup_stage attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 26 \logical_op__imm_data__ok$5 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub4_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -367316,1319 +53243,881 @@ module \setup_stage attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire output 32 \logical_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 50 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 49 \operation - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire output 41 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:175944$12217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$21 - connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:175944$12217_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:175946$12219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$25 - connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:175946$12219_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:175955$12232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B \$45 - connect \Y $and$libresoc.v:175955$12232_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:175958$12235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \$51 - connect \Y $and$libresoc.v:175958$12235_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub4_upd + attribute \src "libresoc.v:35813.7-35813.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:35813.7-35813.20" + process $proc$libresoc.v:35813$806 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:175954$12231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $eq$libresoc.v:175954$12231_Y + attribute \src "libresoc.v:36070.3-36082.6" + process $proc$libresoc.v:36070$782 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "libresoc.v:36071.5-36071.29" + switch \initial + attribute \src "libresoc.v:36071.9-36071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:175957$12234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $eq$libresoc.v:175957$12234_Y + attribute \src "libresoc.v:36083.3-36095.6" + process $proc$libresoc.v:36083$783 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:36084.5-36084.29" + switch \initial + attribute \src "libresoc.v:36084.9-36084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:175960$12237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $eq$libresoc.v:175960$12237_Y + attribute \src "libresoc.v:36096.3-36108.6" + process $proc$libresoc.v:36096$784 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:36097.5-36097.29" + switch \initial + attribute \src "libresoc.v:36097.9-36097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:175947$12220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $extend$libresoc.v:175947$12220_Y + attribute \src "libresoc.v:36109.3-36121.6" + process $proc$libresoc.v:36109$785 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:36110.5-36110.29" + switch \initial + attribute \src "libresoc.v:36110.9-36110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:175948$12222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $extend$libresoc.v:175948$12222_Y + attribute \src "libresoc.v:36122.3-36134.6" + process $proc$libresoc.v:36122$786 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:36123.5-36123.29" + switch \initial + attribute \src "libresoc.v:36123.9-36123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:175950$12225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $extend$libresoc.v:175950$12225_Y + attribute \src "libresoc.v:36135.3-36147.6" + process $proc$libresoc.v:36135$787 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:36136.5-36136.29" + switch \initial + attribute \src "libresoc.v:36136.9-36136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:175951$12227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $extend$libresoc.v:175951$12227_Y + attribute \src "libresoc.v:36148.3-36160.6" + process $proc$libresoc.v:36148$788 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:36149.5-36149.29" + switch \initial + attribute \src "libresoc.v:36149.9-36149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:175963$12240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 95 - parameter \Y_WIDTH 128 - connect \A \$62 - connect \Y $extend$libresoc.v:175963$12240_Y + attribute \src "libresoc.v:36161.3-36173.6" + process $proc$libresoc.v:36161$789 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:36162.5-36162.29" + switch \initial + attribute \src "libresoc.v:36162.9-36162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:175953$12230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \abs_dend - connect \B \abs_dor - connect \Y $ge$libresoc.v:175953$12230_Y + attribute \src "libresoc.v:36174.3-36186.6" + process $proc$libresoc.v:36174$790 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:36175.5-36175.29" + switch \initial + attribute \src "libresoc.v:36175.9-36175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:175956$12233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \abs_dend [31:0] - connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:175956$12233_Y + attribute \src "libresoc.v:36187.3-36199.6" + process $proc$libresoc.v:36187$791 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:36188.5-36188.29" + switch \initial + attribute \src "libresoc.v:36188.9-36188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:175947$12221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175947$12220_Y - connect \Y $neg$libresoc.v:175947$12221_Y + attribute \src "libresoc.v:36200.3-36212.6" + process $proc$libresoc.v:36200$792 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:36201.5-36201.29" + switch \initial + attribute \src "libresoc.v:36201.9-36201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:175950$12226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175950$12225_Y - connect \Y $neg$libresoc.v:175950$12226_Y + attribute \src "libresoc.v:36213.3-36225.6" + process $proc$libresoc.v:36213$793 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:36214.5-36214.29" + switch \initial + attribute \src "libresoc.v:36214.9-36214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:175948$12223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175948$12222_Y - connect \Y $pos$libresoc.v:175948$12223_Y + attribute \src "libresoc.v:36226.3-36238.6" + process $proc$libresoc.v:36226$794 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:36227.5-36227.29" + switch \initial + attribute \src "libresoc.v:36227.9-36227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:175951$12228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:175951$12227_Y - connect \Y $pos$libresoc.v:175951$12228_Y + attribute \src "libresoc.v:36239.3-36251.6" + process $proc$libresoc.v:36239$795 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:36240.5-36240.29" + switch \initial + attribute \src "libresoc.v:36240.9-36240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:175963$12241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:175963$12240_Y - connect \Y $pos$libresoc.v:175963$12241_Y + attribute \src "libresoc.v:36252.3-36264.6" + process $proc$libresoc.v:36252$796 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:36253.5-36253.29" + switch \initial + attribute \src "libresoc.v:36253.9-36253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:175962$12239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 95 - connect \A \abs_dend [31:0] - connect \B 6'100000 - connect \Y $sshl$libresoc.v:175962$12239_Y + attribute \src "libresoc.v:36265.3-36277.6" + process $proc$libresoc.v:36265$797 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:36266.5-36266.29" + switch \initial + attribute \src "libresoc.v:36266.9-36266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:175964$12242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \abs_dend - connect \B 7'1000000 - connect \Y $sshl$libresoc.v:175964$12242_Y + attribute \src "libresoc.v:36278.3-36290.6" + process $proc$libresoc.v:36278$798 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:36279.5-36279.29" + switch \initial + attribute \src "libresoc.v:36279.9-36279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:175943$12216 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175943$12216_Y + attribute \src "libresoc.v:36291.3-36303.6" + process $proc$libresoc.v:36291$799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:36292.5-36292.29" + switch \initial + attribute \src "libresoc.v:36292.9-36292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:175945$12218 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175945$12218_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:175949$12224 - parameter \WIDTH 65 - connect \A \$32 - connect \B \$30 - connect \S \divisor_neg - connect \Y $ternary$libresoc.v:175949$12224_Y + attribute \src "libresoc.v:36304.3-36316.6" + process $proc$libresoc.v:36304$800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:36305.5-36305.29" + switch \initial + attribute \src "libresoc.v:36305.9-36305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:175952$12229 - parameter \WIDTH 65 - connect \A \$39 - connect \B \$37 - connect \S \dividend_neg - connect \Y $ternary$libresoc.v:175952$12229_Y + attribute \src "libresoc.v:36317.3-36329.6" + process $proc$libresoc.v:36317$801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:36318.5-36318.29" + switch \initial + attribute \src "libresoc.v:36318.9-36318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:175959$12236 - parameter \WIDTH 32 - connect \A \abs_dor [63:32] - connect \B 0 - connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175959$12236_Y + attribute \src "libresoc.v:36330.3-36342.6" + process $proc$libresoc.v:36330$802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:36331.5-36331.29" + switch \initial + attribute \src "libresoc.v:36331.9-36331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $ternary$libresoc.v:175961$12238 - parameter \WIDTH 32 - connect \A \abs_dend [63:32] - connect \B 0 - connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:175961$12238_Y + attribute \src "libresoc.v:36343.3-36355.6" + process $proc$libresoc.v:36343$803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:36344.5-36344.29" + switch \initial + attribute \src "libresoc.v:36344.9-36344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] end - attribute \src "libresoc.v:175605.7-175605.20" - process $proc$libresoc.v:175605$12244 + attribute \src "libresoc.v:36356.3-36368.6" + process $proc$libresoc.v:36356$804 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:36357.5-36357.29" + switch \initial + attribute \src "libresoc.v:36357.9-36357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:175965.3-175990.6" - process $proc$libresoc.v:175965$12243 + attribute \src "libresoc.v:36369.3-36381.6" + process $proc$libresoc.v:36369$805 assign { } { } assign { } { } - assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:175966.5-175966.29" + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:36370.5-36370.29" switch \initial - attribute \src "libresoc.v:175966.9-175966.17" + attribute \src "libresoc.v:36370.9-36370.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" - switch \logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0011101 , 7'0101111 - assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\dividend[127:0] [31:0] \abs_dend [31:0] - assign $1\dividend[127:0] [63:32] \$59 + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 7'0011110 + case 5'00000 assign { } { } - assign $1\dividend[127:0] $2\dividend[127:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" - switch \logical_op__is_32bit - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dividend[127:0] \$61 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dividend[127:0] \$65 [127:0] - end + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 case - assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dividend $0\dividend[127:0] - end - connect \$21 $ternary$libresoc.v:175943$12216_Y - connect \$23 $and$libresoc.v:175944$12217_Y - connect \$25 $ternary$libresoc.v:175945$12218_Y - connect \$27 $and$libresoc.v:175946$12219_Y - connect \$30 $neg$libresoc.v:175947$12221_Y - connect \$32 $pos$libresoc.v:175948$12223_Y - connect \$34 $ternary$libresoc.v:175949$12224_Y - connect \$37 $neg$libresoc.v:175950$12226_Y - connect \$39 $pos$libresoc.v:175951$12228_Y - connect \$41 $ternary$libresoc.v:175952$12229_Y - connect \$43 $ge$libresoc.v:175953$12230_Y - connect \$45 $eq$libresoc.v:175954$12231_Y - connect \$47 $and$libresoc.v:175955$12232_Y - connect \$49 $ge$libresoc.v:175956$12233_Y - connect \$51 $eq$libresoc.v:175957$12234_Y - connect \$53 $and$libresoc.v:175958$12235_Y - connect \$55 $ternary$libresoc.v:175959$12236_Y - connect \$57 $eq$libresoc.v:175960$12237_Y - connect \$59 $ternary$libresoc.v:175961$12238_Y - connect \$62 $sshl$libresoc.v:175962$12239_Y - connect \$61 $pos$libresoc.v:175963$12241_Y - connect \$66 $sshl$libresoc.v:175964$12242_Y - connect \$29 \$34 - connect \$36 \$41 - connect \$65 \$66 - connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } - connect \muxid$1 \muxid - connect \xer_so$20 \xer_so - connect \div_by_zero \$57 - connect \divisor_radicand [63:32] \$55 - connect \divisor_radicand [31:0] \abs_dor [31:0] - connect \dive_abs_ov32 \$53 - connect \dive_abs_ov64 \$47 - connect \abs_dend \$41 [63:0] - connect \abs_dor \$34 [63:0] - connect \divisor_neg \$27 - connect \dividend_neg \$23 - connect \operation 2'01 + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:176011.1-177212.10" +attribute \src "libresoc.v:36387.1-37678.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" -module \shiftrot0 - attribute \src "libresoc.v:176783.3-176784.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:176781.3-176782.46" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:177132.3-177140.6" - wire $0\alu_l_r_alu$next[0:0]$12462 - attribute \src "libresoc.v:176699.3-176700.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12379 - attribute \src "libresoc.v:176727.3-176728.75" - wire width 12 $0\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12380 - attribute \src "libresoc.v:176729.3-176730.89" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12381 - attribute \src "libresoc.v:176731.3-176732.85" - wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12382 - attribute \src "libresoc.v:176745.3-176746.83" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12383 - attribute \src "libresoc.v:176749.3-176750.77" - wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12384 - attribute \src "libresoc.v:176757.3-176758.69" - wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12385 - attribute \src "libresoc.v:176725.3-176726.79" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12386 - attribute \src "libresoc.v:176743.3-176744.79" - wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12387 - attribute \src "libresoc.v:176753.3-176754.77" - wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12388 - attribute \src "libresoc.v:176755.3-176756.79" - wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12389 - attribute \src "libresoc.v:176737.3-176738.73" - wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12390 - attribute \src "libresoc.v:176739.3-176740.73" - wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12391 - attribute \src "libresoc.v:176747.3-176748.85" - wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12392 - attribute \src "libresoc.v:176751.3-176752.79" - wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12393 - attribute \src "libresoc.v:176735.3-176736.73" - wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12394 - attribute \src "libresoc.v:176733.3-176734.73" - wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12395 - attribute \src "libresoc.v:176741.3-176742.79" - wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:177123.3-177131.6" - wire $0\alui_l_r_alui$next[0:0]$12459 - attribute \src "libresoc.v:176701.3-176702.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:177007.3-177028.6" - wire width 64 $0\data_r0__o$next[63:0]$12420 - attribute \src "libresoc.v:176721.3-176722.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:177007.3-177028.6" - wire $0\data_r0__o_ok$next[0:0]$12421 - attribute \src "libresoc.v:176723.3-176724.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:177029.3-177050.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12428 - attribute \src "libresoc.v:176717.3-176718.43" - wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:177029.3-177050.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12429 - attribute \src "libresoc.v:176719.3-176720.49" - wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:177051.3-177072.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12436 - attribute \src "libresoc.v:176713.3-176714.47" - wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:177051.3-177072.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12437 - attribute \src "libresoc.v:176715.3-176716.53" - wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:177141.3-177150.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:177151.3-177160.6" - wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:177161.3-177170.6" - wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:176012.7-176012.20" +module \dec31_dec_sub8 + attribute \src "libresoc.v:36860.3-36902.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:37032.3-37074.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37591.3-37633.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37634.3-37676.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36817.3-36859.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36989.3-37031.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37376.3-37418.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36645.3-36687.6" + wire width 12 $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37419.3-37461.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37462.3-37504.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37505.3-37547.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37118.3-37160.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36903.3-36945.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36946.3-36988.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37204.3-37246.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36688.3-36730.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37290.3-37332.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37548.3-37590.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36774.3-36816.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37161.3-37203.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37333.3-37375.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37247.3-37289.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37075.3-37117.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36731.3-36773.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36388.7-36388.20" wire $0\initial[0:0] - attribute \src "libresoc.v:176924.3-176932.6" - wire $0\opc_l_r_opc$next[0:0]$12364 - attribute \src "libresoc.v:176767.3-176768.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:176915.3-176923.6" - wire $0\opc_l_s_opc$next[0:0]$12361 - attribute \src "libresoc.v:176769.3-176770.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:177171.3-177179.6" - wire width 3 $0\prev_wr_go$next[2:0]$12468 - attribute \src "libresoc.v:176779.3-176780.37" - wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:176869.3-176878.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:176960.3-176968.6" - wire width 3 $0\req_l_r_req$next[2:0]$12376 - attribute \src "libresoc.v:176759.3-176760.39" - wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:176951.3-176959.6" - wire width 3 $0\req_l_s_req$next[2:0]$12373 - attribute \src "libresoc.v:176761.3-176762.39" - wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:176888.3-176896.6" - wire $0\rok_l_r_rdok$next[0:0]$12352 - attribute \src "libresoc.v:176775.3-176776.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:176879.3-176887.6" - wire $0\rok_l_s_rdok$next[0:0]$12349 - attribute \src "libresoc.v:176777.3-176778.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:176906.3-176914.6" - wire $0\rst_l_r_rst$next[0:0]$12358 - attribute \src "libresoc.v:176771.3-176772.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:176897.3-176905.6" - wire $0\rst_l_s_rst$next[0:0]$12355 - attribute \src "libresoc.v:176773.3-176774.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:176942.3-176950.6" - wire width 5 $0\src_l_r_src$next[4:0]$12370 - attribute \src "libresoc.v:176763.3-176764.39" - wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:176933.3-176941.6" - wire width 5 $0\src_l_s_src$next[4:0]$12367 - attribute \src "libresoc.v:176765.3-176766.39" - wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:177073.3-177082.6" - wire width 64 $0\src_r0$next[63:0]$12444 - attribute \src "libresoc.v:176711.3-176712.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:177083.3-177092.6" - wire width 64 $0\src_r1$next[63:0]$12447 - attribute \src "libresoc.v:176709.3-176710.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:177093.3-177102.6" - wire width 64 $0\src_r2$next[63:0]$12450 - attribute \src "libresoc.v:176707.3-176708.29" - wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:177103.3-177112.6" - wire $0\src_r3$next[0:0]$12453 - attribute \src "libresoc.v:176705.3-176706.29" - wire $0\src_r3[0:0] - attribute \src "libresoc.v:177113.3-177122.6" - wire width 2 $0\src_r4$next[1:0]$12456 - attribute \src "libresoc.v:176703.3-176704.29" - wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:176134.7-176134.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:176144.7-176144.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:177132.3-177140.6" - wire $1\alu_l_r_alu$next[0:0]$12463 - attribute \src "libresoc.v:176152.7-176152.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 - attribute \src "libresoc.v:176193.14-176193.53" - wire width 12 $1\alu_shift_rot0_sr_op__fn_unit[11:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 - attribute \src "libresoc.v:176197.14-176197.73" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 - attribute \src "libresoc.v:176201.7-176201.48" - wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 - attribute \src "libresoc.v:176209.13-176209.53" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 - attribute \src "libresoc.v:176213.7-176213.44" - wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 - attribute \src "libresoc.v:176217.14-176217.48" - wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 - attribute \src "libresoc.v:176295.13-176295.52" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 - attribute \src "libresoc.v:176299.7-176299.45" - wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 - attribute \src "libresoc.v:176303.7-176303.44" - wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 - attribute \src "libresoc.v:176307.7-176307.45" - wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 - attribute \src "libresoc.v:176311.7-176311.42" - wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 - attribute \src "libresoc.v:176315.7-176315.42" - wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 - attribute \src "libresoc.v:176319.7-176319.48" - wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 - attribute \src "libresoc.v:176323.7-176323.45" - wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 - attribute \src "libresoc.v:176327.7-176327.42" - wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 - attribute \src "libresoc.v:176331.7-176331.42" - wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 - attribute \src "libresoc.v:176335.7-176335.45" - wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:177123.3-177131.6" - wire $1\alui_l_r_alui$next[0:0]$12460 - attribute \src "libresoc.v:176347.7-176347.27" - wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:177007.3-177028.6" - wire width 64 $1\data_r0__o$next[63:0]$12422 - attribute \src "libresoc.v:176381.14-176381.47" - wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:177007.3-177028.6" - wire $1\data_r0__o_ok$next[0:0]$12423 - attribute \src "libresoc.v:176385.7-176385.27" - wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:177029.3-177050.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12430 - attribute \src "libresoc.v:176389.13-176389.33" - wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:177029.3-177050.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12431 - attribute \src "libresoc.v:176393.7-176393.30" - wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:177051.3-177072.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12438 - attribute \src "libresoc.v:176397.13-176397.35" - wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:177051.3-177072.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12439 - attribute \src "libresoc.v:176401.7-176401.32" - wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:177141.3-177150.6" - wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:177151.3-177160.6" - wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:177161.3-177170.6" - wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:176924.3-176932.6" - wire $1\opc_l_r_opc$next[0:0]$12365 - attribute \src "libresoc.v:176418.7-176418.25" - wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:176915.3-176923.6" - wire $1\opc_l_s_opc$next[0:0]$12362 - attribute \src "libresoc.v:176422.7-176422.25" - wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:177171.3-177179.6" - wire width 3 $1\prev_wr_go$next[2:0]$12469 - attribute \src "libresoc.v:176551.13-176551.30" - wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:176869.3-176878.6" - wire $1\req_done[0:0] - attribute \src "libresoc.v:176960.3-176968.6" - wire width 3 $1\req_l_r_req$next[2:0]$12377 - attribute \src "libresoc.v:176559.13-176559.31" - wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:176951.3-176959.6" - wire width 3 $1\req_l_s_req$next[2:0]$12374 - attribute \src "libresoc.v:176563.13-176563.31" - wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:176888.3-176896.6" - wire $1\rok_l_r_rdok$next[0:0]$12353 - attribute \src "libresoc.v:176575.7-176575.26" - wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:176879.3-176887.6" - wire $1\rok_l_s_rdok$next[0:0]$12350 - attribute \src "libresoc.v:176579.7-176579.26" - wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:176906.3-176914.6" - wire $1\rst_l_r_rst$next[0:0]$12359 - attribute \src "libresoc.v:176583.7-176583.25" - wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:176897.3-176905.6" - wire $1\rst_l_s_rst$next[0:0]$12356 - attribute \src "libresoc.v:176587.7-176587.25" - wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:176942.3-176950.6" - wire width 5 $1\src_l_r_src$next[4:0]$12371 - attribute \src "libresoc.v:176605.13-176605.32" - wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:176933.3-176941.6" - wire width 5 $1\src_l_s_src$next[4:0]$12368 - attribute \src "libresoc.v:176609.13-176609.32" - wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:177073.3-177082.6" - wire width 64 $1\src_r0$next[63:0]$12445 - attribute \src "libresoc.v:176615.14-176615.43" - wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:177083.3-177092.6" - wire width 64 $1\src_r1$next[63:0]$12448 - attribute \src "libresoc.v:176619.14-176619.43" - wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:177093.3-177102.6" - wire width 64 $1\src_r2$next[63:0]$12451 - attribute \src "libresoc.v:176623.14-176623.43" - wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:177103.3-177112.6" - wire $1\src_r3$next[0:0]$12454 - attribute \src "libresoc.v:176627.7-176627.20" - wire $1\src_r3[0:0] - attribute \src "libresoc.v:177113.3-177122.6" - wire width 2 $1\src_r4$next[1:0]$12457 - attribute \src "libresoc.v:176631.13-176631.26" - wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:176969.3-177006.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12413 - attribute \src "libresoc.v:176969.3-177006.6" - wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_shift_rot0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rc - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_shift_rot0_sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_shift_rot0_sr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_shift_rot0_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_shift_rot0_sr_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__imm_data__ok$next + attribute \src "libresoc.v:36860.3-36902.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:37032.3-37074.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37591.3-37633.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37634.3-37676.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:36817.3-36859.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36989.3-37031.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:37376.3-37418.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:36645.3-36687.6" + wire width 12 $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:37419.3-37461.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37462.3-37504.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37505.3-37547.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37118.3-37160.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:36903.3-36945.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36946.3-36988.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:37204.3-37246.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:36688.3-36730.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:37290.3-37332.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37548.3-37590.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:36774.3-36816.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:37161.3-37203.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37333.3-37375.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37247.3-37289.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37075.3-37117.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:36731.3-36773.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub8_cr_out attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" attribute \enum_value_01 "ONE" attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_shift_rot0_sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_shift_rot0_sr_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__input_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_shift_rot0_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_shift_rot0_sr_op__insn$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_shift_rot0_sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_shift_rot0_sr_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__output_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_shift_rot0_sr_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 2 \alu_shift_rot0_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_shift_rot0_xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire \alu_shift_rot0_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 33 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 20 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 19 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 23 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 22 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 21 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 31 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 30 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__xer_ca_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 32 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 34 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:176012.7-176012.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 29 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub8_form attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -368642,22 +54131,39 @@ module \shiftrot0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_shift_rot0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 5 \oper_i_alu_shift_rot0__imm_data__ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 12 \oper_i_alu_shift_rot0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 14 \oper_i_alu_shift_rot0__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \oper_i_alu_shift_rot0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub8_in3_sel attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -368732,9170 +54238,6320 @@ module \shiftrot0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_shift_rot0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 11 \oper_i_alu_shift_rot0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 16 \oper_i_alu_shift_rot0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 17 \oper_i_alu_shift_rot0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 8 \oper_i_alu_shift_rot0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 9 \oper_i_alu_shift_rot0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 13 \oper_i_alu_shift_rot0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 15 \oper_i_alu_shift_rot0__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_shift_rot0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 6 \oper_i_alu_shift_rot0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 10 \oper_i_alu_shift_rot0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 5 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 25 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire input 27 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 28 \src5_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4 - attribute \src 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$and$libresoc.v:176682$12287_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:176683$12288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:176683$12288_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:176684$12289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:176684$12289_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:176694$12299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:176694$12299_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:176695$12300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:176695$12300_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:176696$12301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:176696$12301_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:176698$12303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$94 - connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:176698$12303_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:176668$12273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$42 - connect \B 1'0 - connect \Y $eq$libresoc.v:176668$12273_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:176670$12275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:176670$12275_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:176640$12245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:176640$12245_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:176651$12256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$libresoc.v:176651$12256_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:176653$12258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$libresoc.v:176653$12258_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:176656$12261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:176656$12261_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:176659$12264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$23 - connect \Y $not$libresoc.v:176659$12264_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:176665$12270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:176665$12270_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:176676$12281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:176676$12281_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:176697$12302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:176697$12302_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:176664$12269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \B \$34 - connect \Y $or$libresoc.v:176664$12269_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:176674$12279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:176674$12279_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:176675$12280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:176675$12280_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:176677$12282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:176677$12282_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:176678$12283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:176678$12283_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:176681$12286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:176681$12286_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:176687$12292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$5 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:176687$12292_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:176693$12298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$7 - connect \Y $reduce_and$libresoc.v:176693$12298_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:176658$12263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \Y $reduce_or$libresoc.v:176658$12263_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:176662$12267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:176662$12267_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:176663$12268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:176663$12268_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:176685$12290 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:176685$12290_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:176686$12291 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_shift_rot0_sr_op__imm_data__data - connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:176686$12291_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176688$12293 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:176688$12293_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176689$12294 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $ternary$libresoc.v:176689$12294_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176690$12295 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:176690$12295_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176691$12296 - parameter \WIDTH 1 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:176691$12296_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:176692$12297 - parameter \WIDTH 2 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:176692$12297_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176785.15-176791.4" - cell \alu_l$125 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176792.18-176827.4" - cell \alu_shift_rot0 \alu_shift_rot0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cr_a \alu_shift_rot0_cr_a - connect \cr_a_ok \cr_a_ok - connect \n_ready_i \alu_shift_rot0_n_ready_i - connect \n_valid_o \alu_shift_rot0_n_valid_o - connect \o \alu_shift_rot0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_shift_rot0_p_ready_o - connect \p_valid_i \alu_shift_rot0_p_valid_i - connect \ra \alu_shift_rot0_ra - connect \rb \alu_shift_rot0_rb - connect \rc \alu_shift_rot0_rc - connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit - connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data - connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok - connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry - connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr - connect \sr_op__insn \alu_shift_rot0_sr_op__insn - connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type - connect \sr_op__invert_in \alu_shift_rot0_sr_op__invert_in - connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit - connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed - connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe - connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok - connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry - connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr - connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok - connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc - connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 - connect \xer_ca \alu_shift_rot0_xer_ca - connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 - connect \xer_ca_ok \xer_ca_ok - connect \xer_so \alu_shift_rot0_xer_so - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176828.16-176834.4" - cell \alui_l$124 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176835.15-176841.4" - cell \opc_l$120 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176842.15-176848.4" - cell \req_l$121 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176849.15-176855.4" - cell \rok_l$123 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176856.15-176861.4" - cell \rst_l$122 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:176862.15-176868.4" - cell \src_l$119 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:176012.7-176012.20" - process $proc$libresoc.v:176012$12470 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:176134.7-176134.24" - process $proc$libresoc.v:176134$12471 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:176144.7-176144.26" - process $proc$libresoc.v:176144$12472 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:176152.7-176152.25" - process $proc$libresoc.v:176152$12473 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:176193.14-176193.53" - process $proc$libresoc.v:176193$12474 - assign { } { } - assign $1\alu_shift_rot0_sr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:176197.14-176197.73" - process $proc$libresoc.v:176197$12475 - assign { } { } - assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:176201.7-176201.48" - process $proc$libresoc.v:176201$12476 - assign { } { } - assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:176209.13-176209.53" - process $proc$libresoc.v:176209$12477 - assign { } { } - assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 - sync always - sync init - update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] - end - attribute \src "libresoc.v:176213.7-176213.44" - process $proc$libresoc.v:176213$12478 - assign { } { } - assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] - end - attribute \src "libresoc.v:176217.14-176217.48" - process $proc$libresoc.v:176217$12479 - assign { } { } - assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 - sync always - sync init - update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] - end - attribute \src "libresoc.v:176295.13-176295.52" - process $proc$libresoc.v:176295$12480 - assign { } { } - assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] - end - attribute \src "libresoc.v:176299.7-176299.45" - process $proc$libresoc.v:176299$12481 - assign { } { } - assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] - end - attribute \src "libresoc.v:176303.7-176303.44" - process $proc$libresoc.v:176303$12482 - assign { } { } - assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:176307.7-176307.45" - process $proc$libresoc.v:176307$12483 - assign { } { } - assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] - end - attribute \src "libresoc.v:176311.7-176311.42" - process $proc$libresoc.v:176311$12484 - assign { } { } - assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] - end - attribute \src "libresoc.v:176315.7-176315.42" - process $proc$libresoc.v:176315$12485 - assign { } { } - assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] - end - attribute \src "libresoc.v:176319.7-176319.48" - process $proc$libresoc.v:176319$12486 - assign { } { } - assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] - end - attribute \src "libresoc.v:176323.7-176323.45" - process $proc$libresoc.v:176323$12487 - assign { } { } - assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] - end - attribute \src "libresoc.v:176327.7-176327.42" - process $proc$libresoc.v:176327$12488 - assign { } { } - assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] - end - attribute \src "libresoc.v:176331.7-176331.42" - process $proc$libresoc.v:176331$12489 - assign { } { } - assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] - end - attribute \src "libresoc.v:176335.7-176335.45" - process $proc$libresoc.v:176335$12490 - assign { } { } - assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 - sync always - sync init - update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] - end - attribute \src "libresoc.v:176347.7-176347.27" - process $proc$libresoc.v:176347$12491 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:176381.14-176381.47" - process $proc$libresoc.v:176381$12492 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:176385.7-176385.27" - process $proc$libresoc.v:176385$12493 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:176389.13-176389.33" - process $proc$libresoc.v:176389$12494 - assign { } { } - assign $1\data_r1__cr_a[3:0] 4'0000 - sync always - sync init - update \data_r1__cr_a $1\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:176393.7-176393.30" - process $proc$libresoc.v:176393$12495 - assign { } { } - assign $1\data_r1__cr_a_ok[0:0] 1'0 - sync always - sync init - update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:176397.13-176397.35" - process $proc$libresoc.v:176397$12496 - assign { } { } - assign $1\data_r2__xer_ca[1:0] 2'00 - sync always - sync init - update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] - end - attribute \src "libresoc.v:176401.7-176401.32" - process $proc$libresoc.v:176401$12497 - assign { } { } - assign $1\data_r2__xer_ca_ok[0:0] 1'0 - sync always - sync init - update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] - end - attribute \src "libresoc.v:176418.7-176418.25" - process $proc$libresoc.v:176418$12498 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:176422.7-176422.25" - process $proc$libresoc.v:176422$12499 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:176551.13-176551.30" - process $proc$libresoc.v:176551$12500 - assign { } { } - assign $1\prev_wr_go[2:0] 3'000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[2:0] - end - attribute \src "libresoc.v:176559.13-176559.31" - process $proc$libresoc.v:176559$12501 - assign { } { } - assign $1\req_l_r_req[2:0] 3'111 - sync always - sync init - update \req_l_r_req $1\req_l_r_req[2:0] - end - attribute \src "libresoc.v:176563.13-176563.31" - process $proc$libresoc.v:176563$12502 - assign { } { } - assign $1\req_l_s_req[2:0] 3'000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[2:0] - end - attribute \src "libresoc.v:176575.7-176575.26" - process $proc$libresoc.v:176575$12503 - assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 - sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] - end - attribute \src "libresoc.v:176579.7-176579.26" - process $proc$libresoc.v:176579$12504 - assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:176583.7-176583.25" - process $proc$libresoc.v:176583$12505 - assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 - sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:176587.7-176587.25" - process $proc$libresoc.v:176587$12506 - assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:176605.13-176605.32" - process $proc$libresoc.v:176605$12507 - assign { } { } - assign $1\src_l_r_src[4:0] 5'11111 - sync always - sync init - update \src_l_r_src $1\src_l_r_src[4:0] - end - attribute \src "libresoc.v:176609.13-176609.32" - process $proc$libresoc.v:176609$12508 - assign { } { } - assign $1\src_l_s_src[4:0] 5'00000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[4:0] - end - attribute \src "libresoc.v:176615.14-176615.43" - process $proc$libresoc.v:176615$12509 - assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r0 $1\src_r0[63:0] - end - attribute \src "libresoc.v:176619.14-176619.43" - process $proc$libresoc.v:176619$12510 - assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r1 $1\src_r1[63:0] - end - attribute \src "libresoc.v:176623.14-176623.43" - process $proc$libresoc.v:176623$12511 - assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r2 $1\src_r2[63:0] - end - attribute \src "libresoc.v:176627.7-176627.20" - process $proc$libresoc.v:176627$12512 - assign { } { } - assign $1\src_r3[0:0] 1'0 - sync always - sync init - update \src_r3 $1\src_r3[0:0] - end - attribute \src "libresoc.v:176631.13-176631.26" - process $proc$libresoc.v:176631$12513 - assign { } { } - assign $1\src_r4[1:0] 2'00 - sync always - sync init - update \src_r4 $1\src_r4[1:0] - end - attribute \src "libresoc.v:176699.3-176700.39" - process $proc$libresoc.v:176699$12304 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:176701.3-176702.43" - process $proc$libresoc.v:176701$12305 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:176703.3-176704.29" - process $proc$libresoc.v:176703$12306 - assign { } { } - assign $0\src_r4[1:0] \src_r4$next - sync posedge \coresync_clk - update \src_r4 $0\src_r4[1:0] - end - attribute \src "libresoc.v:176705.3-176706.29" - process $proc$libresoc.v:176705$12307 - assign { } { } - assign $0\src_r3[0:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[0:0] - end - attribute \src "libresoc.v:176707.3-176708.29" - process $proc$libresoc.v:176707$12308 - assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] - end - attribute \src "libresoc.v:176709.3-176710.29" - process $proc$libresoc.v:176709$12309 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:176711.3-176712.29" - process $proc$libresoc.v:176711$12310 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:176713.3-176714.47" - process $proc$libresoc.v:176713$12311 - assign { } { } - assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next - sync posedge \coresync_clk - update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] - end - attribute \src "libresoc.v:176715.3-176716.53" - process $proc$libresoc.v:176715$12312 - assign { } { } - assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next - sync posedge \coresync_clk - update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] - end - attribute \src "libresoc.v:176717.3-176718.43" - process $proc$libresoc.v:176717$12313 - assign { } { } - assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next - sync posedge \coresync_clk - update \data_r1__cr_a $0\data_r1__cr_a[3:0] - end - attribute \src "libresoc.v:176719.3-176720.49" - process $proc$libresoc.v:176719$12314 - assign { } { } - assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next - sync posedge \coresync_clk - update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] - end - attribute \src "libresoc.v:176721.3-176722.37" - process $proc$libresoc.v:176721$12315 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:176723.3-176724.43" - process $proc$libresoc.v:176723$12316 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:176725.3-176726.79" - process $proc$libresoc.v:176725$12317 - assign { } { } - assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] - end - attribute \src "libresoc.v:176727.3-176728.75" - process $proc$libresoc.v:176727$12318 - assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit[11:0] \alu_shift_rot0_sr_op__fn_unit$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:176729.3-176730.89" - process $proc$libresoc.v:176729$12319 - assign { } { } - assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - end - attribute \src "libresoc.v:176731.3-176732.85" - process $proc$libresoc.v:176731$12320 - assign { } { } - assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - end - attribute \src "libresoc.v:176733.3-176734.73" - process $proc$libresoc.v:176733$12321 - assign { } { } - assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] - end - attribute \src "libresoc.v:176735.3-176736.73" - process $proc$libresoc.v:176735$12322 - assign { } { } - assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] - end - attribute \src "libresoc.v:176737.3-176738.73" - process $proc$libresoc.v:176737$12323 - assign { } { } - assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] - end - attribute \src "libresoc.v:176739.3-176740.73" - process $proc$libresoc.v:176739$12324 - assign { } { } - assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] - end - attribute \src "libresoc.v:176741.3-176742.79" - process $proc$libresoc.v:176741$12325 - assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] - end - attribute \src "libresoc.v:176743.3-176744.79" - process $proc$libresoc.v:176743$12326 - assign { } { } - assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] - end - attribute \src "libresoc.v:176745.3-176746.83" - process $proc$libresoc.v:176745$12327 - assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] - end - attribute \src "libresoc.v:176747.3-176748.85" - process $proc$libresoc.v:176747$12328 - assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] - end - attribute \src "libresoc.v:176749.3-176750.77" - process $proc$libresoc.v:176749$12329 - assign { } { } - assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] - end - attribute \src "libresoc.v:176751.3-176752.79" - process $proc$libresoc.v:176751$12330 - assign { } { } - assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] - end - attribute \src "libresoc.v:176753.3-176754.77" - process $proc$libresoc.v:176753$12331 - assign { } { } - assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:176755.3-176756.79" - process $proc$libresoc.v:176755$12332 - assign { } { } - assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] - end - attribute \src "libresoc.v:176757.3-176758.69" - process $proc$libresoc.v:176757$12333 - assign { } { } - assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] - end - attribute \src "libresoc.v:176759.3-176760.39" - process $proc$libresoc.v:176759$12334 - assign { } { } - assign $0\req_l_r_req[2:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[2:0] - end - attribute \src "libresoc.v:176761.3-176762.39" - process $proc$libresoc.v:176761$12335 - assign { } { } - assign $0\req_l_s_req[2:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[2:0] - end - attribute \src "libresoc.v:176763.3-176764.39" - process $proc$libresoc.v:176763$12336 - assign { } { } - assign $0\src_l_r_src[4:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[4:0] - end - attribute \src "libresoc.v:176765.3-176766.39" - process $proc$libresoc.v:176765$12337 - assign { } { } - assign $0\src_l_s_src[4:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[4:0] - end - attribute \src "libresoc.v:176767.3-176768.39" - process $proc$libresoc.v:176767$12338 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub8_upd + attribute \src "libresoc.v:36388.7-36388.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:36388.7-36388.20" + process $proc$libresoc.v:36388$831 assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:176769.3-176770.39" - process $proc$libresoc.v:176769$12339 + attribute \src "libresoc.v:36645.3-36687.6" + process $proc$libresoc.v:36645$807 assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:176771.3-176772.39" - process $proc$libresoc.v:176771$12340 assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] + assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "libresoc.v:36646.5-36646.29" + switch \initial + attribute \src "libresoc.v:36646.9-36646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] end - attribute \src "libresoc.v:176773.3-176774.39" - process $proc$libresoc.v:176773$12341 + attribute \src "libresoc.v:36688.3-36730.6" + process $proc$libresoc.v:36688$808 assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:176775.3-176776.41" - process $proc$libresoc.v:176775$12342 assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:36689.5-36689.29" + switch \initial + attribute \src "libresoc.v:36689.9-36689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:176777.3-176778.41" - process $proc$libresoc.v:176777$12343 + attribute \src "libresoc.v:36731.3-36773.6" + process $proc$libresoc.v:36731$809 assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:176779.3-176780.37" - process $proc$libresoc.v:176779$12344 assign { } { } - assign $0\prev_wr_go[2:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[2:0] + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:36732.5-36732.29" + switch \initial + attribute \src "libresoc.v:36732.9-36732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:176781.3-176782.46" - process $proc$libresoc.v:176781$12345 + attribute \src "libresoc.v:36774.3-36816.6" + process $proc$libresoc.v:36774$810 assign { } { } - assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:176783.3-176784.25" - process $proc$libresoc.v:176783$12346 assign { } { } - assign $0\all_rd_dly[0:0] \$10 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:36775.5-36775.29" + switch \initial + attribute \src "libresoc.v:36775.9-36775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:176869.3-176878.6" - process $proc$libresoc.v:176869$12347 + attribute \src "libresoc.v:36817.3-36859.6" + process $proc$libresoc.v:36817$811 assign { } { } assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:176870.5-176870.29" + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:36818.5-36818.29" switch \initial - attribute \src "libresoc.v:176870.9-176870.17" + attribute \src "libresoc.v:36818.9-36818.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\req_done[0:0] 1'1 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 case - assign $1\req_done[0:0] \$46 + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 end sync always - update \req_done $0\req_done[0:0] + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:176879.3-176887.6" - process $proc$libresoc.v:176879$12348 + attribute \src "libresoc.v:36860.3-36902.6" + process $proc$libresoc.v:36860$812 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12349 $1\rok_l_s_rdok$next[0:0]$12350 - attribute \src "libresoc.v:176880.5-176880.29" + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:36861.5-36861.29" switch \initial - attribute \src "libresoc.v:176880.9-176880.17" + attribute \src "libresoc.v:36861.9-36861.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12350 1'0 + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 case - assign $1\rok_l_s_rdok$next[0:0]$12350 \cu_issue_i + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12349 + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:176888.3-176896.6" - process $proc$libresoc.v:176888$12351 + attribute \src "libresoc.v:36903.3-36945.6" + process $proc$libresoc.v:36903$813 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12352 $1\rok_l_r_rdok$next[0:0]$12353 - attribute \src "libresoc.v:176889.5-176889.29" + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:36904.5-36904.29" switch \initial - attribute \src "libresoc.v:176889.9-176889.17" + attribute \src "libresoc.v:36904.9-36904.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12353 1'1 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12353 \$64 + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12352 + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:176897.3-176905.6" - process $proc$libresoc.v:176897$12354 + attribute \src "libresoc.v:36946.3-36988.6" + process $proc$libresoc.v:36946$814 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12355 $1\rst_l_s_rst$next[0:0]$12356 - attribute \src "libresoc.v:176898.5-176898.29" + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:36947.5-36947.29" switch \initial - attribute \src "libresoc.v:176898.9-176898.17" + attribute \src "libresoc.v:36947.9-36947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12356 1'0 + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12356 \all_rd + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12355 + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:176906.3-176914.6" - process $proc$libresoc.v:176906$12357 + attribute \src "libresoc.v:36989.3-37031.6" + process $proc$libresoc.v:36989$815 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12358 $1\rst_l_r_rst$next[0:0]$12359 - attribute \src "libresoc.v:176907.5-176907.29" + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:36990.5-36990.29" switch \initial - attribute \src "libresoc.v:176907.9-176907.17" + attribute \src "libresoc.v:36990.9-36990.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12359 1'1 + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12359 \rst_r + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12358 + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:176915.3-176923.6" - process $proc$libresoc.v:176915$12360 + attribute \src "libresoc.v:37032.3-37074.6" + process $proc$libresoc.v:37032$816 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12361 $1\opc_l_s_opc$next[0:0]$12362 - attribute \src "libresoc.v:176916.5-176916.29" + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:37033.5-37033.29" switch \initial - attribute \src "libresoc.v:176916.9-176916.17" + attribute \src "libresoc.v:37033.9-37033.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12362 1'0 + assign $1\dec31_dec_sub8_br[0:0] 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12362 \cu_issue_i + assign $1\dec31_dec_sub8_br[0:0] 1'0 end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12361 + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:176924.3-176932.6" - process $proc$libresoc.v:176924$12363 + attribute \src "libresoc.v:37075.3-37117.6" + process $proc$libresoc.v:37075$817 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12364 $1\opc_l_r_opc$next[0:0]$12365 - attribute \src "libresoc.v:176925.5-176925.29" + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:37076.5-37076.29" switch \initial - attribute \src "libresoc.v:176925.9-176925.17" + attribute \src "libresoc.v:37076.9-37076.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12365 1'1 + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 case - assign $1\opc_l_r_opc$next[0:0]$12365 \req_done + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12364 + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:176933.3-176941.6" - process $proc$libresoc.v:176933$12366 + attribute \src "libresoc.v:37118.3-37160.6" + process $proc$libresoc.v:37118$818 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12367 $1\src_l_s_src$next[4:0]$12368 - attribute \src "libresoc.v:176934.5-176934.29" + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:37119.5-37119.29" switch \initial - attribute \src "libresoc.v:176934.9-176934.17" + attribute \src "libresoc.v:37119.9-37119.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\src_l_s_src$next[4:0]$12368 5'00000 + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 case - assign $1\src_l_s_src$next[4:0]$12368 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12367 + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:176942.3-176950.6" - process $proc$libresoc.v:176942$12369 + attribute \src "libresoc.v:37161.3-37203.6" + process $proc$libresoc.v:37161$819 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12370 $1\src_l_r_src$next[4:0]$12371 - attribute \src "libresoc.v:176943.5-176943.29" + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:37162.5-37162.29" switch \initial - attribute \src "libresoc.v:176943.9-176943.17" + attribute \src "libresoc.v:37162.9-37162.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\src_l_r_src$next[4:0]$12371 5'11111 + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 case - assign $1\src_l_r_src$next[4:0]$12371 \reset_r + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12370 + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:176951.3-176959.6" - process $proc$libresoc.v:176951$12372 + attribute \src "libresoc.v:37204.3-37246.6" + process $proc$libresoc.v:37204$820 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12373 $1\req_l_s_req$next[2:0]$12374 - attribute \src "libresoc.v:176952.5-176952.29" + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:37205.5-37205.29" switch \initial - attribute \src "libresoc.v:176952.9-176952.17" + attribute \src "libresoc.v:37205.9-37205.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\req_l_s_req$next[2:0]$12374 3'000 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 case - assign $1\req_l_s_req$next[2:0]$12374 \$66 + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12373 + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:176960.3-176968.6" - process $proc$libresoc.v:176960$12375 + attribute \src "libresoc.v:37247.3-37289.6" + process $proc$libresoc.v:37247$821 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12376 $1\req_l_r_req$next[2:0]$12377 - attribute \src "libresoc.v:176961.5-176961.29" + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:37248.5-37248.29" switch \initial - attribute \src "libresoc.v:176961.9-176961.17" + attribute \src "libresoc.v:37248.9-37248.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\req_l_r_req$next[2:0]$12377 3'111 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 case - assign $1\req_l_r_req$next[2:0]$12377 \$68 + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12376 + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:176969.3-177006.6" - process $proc$libresoc.v:176969$12378 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:37290.3-37332.6" + process $proc$libresoc.v:37290$822 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12379 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12382 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12383 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12384 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12385 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12386 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12387 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12388 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12391 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12392 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 - assign { } { } - assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12395 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12380 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12413 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12381 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12414 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12389 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12415 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12390 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12416 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12393 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12417 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12394 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12418 - attribute \src "libresoc.v:176970.5-176970.29" + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:37291.5-37291.29" switch \initial - attribute \src "libresoc.v:176970.9-176970.17" + attribute \src "libresoc.v:37291.9-37291.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "libresoc.v:37333.3-37375.6" + process $proc$libresoc.v:37333$823 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:37334.5-37334.29" + switch \initial + attribute \src "libresoc.v:37334.9-37334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } - case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12396 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12399 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12400 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12401 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12402 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12403 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12404 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12405 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12408 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12409 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12412 \alu_shift_rot0_sr_op__write_cr0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12413 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12414 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12418 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12417 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12415 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12416 1'0 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12413 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12397 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12414 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12398 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12415 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12406 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12416 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12407 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12417 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12410 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12418 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12411 + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$12379 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12380 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12381 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12382 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12383 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12384 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12385 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12386 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12387 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12388 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12389 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12390 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12391 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12392 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12393 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12394 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12395 + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:177007.3-177028.6" - process $proc$libresoc.v:177007$12419 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:37376.3-37418.6" + process $proc$libresoc.v:37376$824 assign { } { } assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$12420 $2\data_r0__o$next[63:0]$12424 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12421 $3\data_r0__o_ok$next[0:0]$12426 - attribute \src "libresoc.v:177008.5-177008.29" + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:37377.5-37377.29" switch \initial - attribute \src "libresoc.v:177008.9-177008.17" + attribute \src "libresoc.v:37377.9-37377.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12423 $1\data_r0__o$next[63:0]$12422 } { \o_ok \alu_shift_rot0_o } - case - assign $1\data_r0__o$next[63:0]$12422 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12423 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12425 $2\data_r0__o$next[63:0]$12424 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$12424 $1\data_r0__o$next[63:0]$12422 - assign $2\data_r0__o_ok$next[0:0]$12425 $1\data_r0__o_ok$next[0:0]$12423 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12426 1'0 + assign $1\dec31_dec_sub8_form[4:0] 5'10001 case - assign $3\data_r0__o_ok$next[0:0]$12426 $2\data_r0__o_ok$next[0:0]$12425 + assign $1\dec31_dec_sub8_form[4:0] 5'00000 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12420 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12421 + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:177029.3-177050.6" - process $proc$libresoc.v:177029$12427 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:37419.3-37461.6" + process $proc$libresoc.v:37419$825 assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12428 $2\data_r1__cr_a$next[3:0]$12432 - assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12429 $3\data_r1__cr_a_ok$next[0:0]$12434 - attribute \src "libresoc.v:177030.5-177030.29" + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:37420.5-37420.29" switch \initial - attribute \src "libresoc.v:177030.9-177030.17" + attribute \src "libresoc.v:37420.9-37420.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12431 $1\data_r1__cr_a$next[3:0]$12430 } { \cr_a_ok \alu_shift_rot0_cr_a } - case - assign $1\data_r1__cr_a$next[3:0]$12430 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12431 \data_r1__cr_a_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12433 $2\data_r1__cr_a$next[3:0]$12432 } 5'00000 - case - assign $2\data_r1__cr_a$next[3:0]$12432 $1\data_r1__cr_a$next[3:0]$12430 - assign $2\data_r1__cr_a_ok$next[0:0]$12433 $1\data_r1__cr_a_ok$next[0:0]$12431 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12434 1'0 - case - assign $3\data_r1__cr_a_ok$next[0:0]$12434 $2\data_r1__cr_a_ok$next[0:0]$12433 - end - sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12428 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12429 - end - attribute \src "libresoc.v:177051.3-177072.6" - process $proc$libresoc.v:177051$12435 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12436 $2\data_r2__xer_ca$next[1:0]$12440 - assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12437 $3\data_r2__xer_ca_ok$next[0:0]$12442 - attribute \src "libresoc.v:177052.5-177052.29" - switch \initial - attribute \src "libresoc.v:177052.9-177052.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12439 $1\data_r2__xer_ca$next[1:0]$12438 } { \xer_ca_ok \alu_shift_rot0_xer_ca } - case - assign $1\data_r2__xer_ca$next[1:0]$12438 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12439 \data_r2__xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10100 assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12441 $2\data_r2__xer_ca$next[1:0]$12440 } 3'000 - case - assign $2\data_r2__xer_ca$next[1:0]$12440 $1\data_r2__xer_ca$next[1:0]$12438 - assign $2\data_r2__xer_ca_ok$next[0:0]$12441 $1\data_r2__xer_ca_ok$next[0:0]$12439 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10111 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12442 1'0 - case - assign $3\data_r2__xer_ca_ok$next[0:0]$12442 $2\data_r2__xer_ca_ok$next[0:0]$12441 - end - sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12436 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12437 - end - attribute \src "libresoc.v:177073.3-177082.6" - process $proc$libresoc.v:177073$12443 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$12444 $1\src_r0$next[63:0]$12445 - attribute \src "libresoc.v:177074.5-177074.29" - switch \initial - attribute \src "libresoc.v:177074.9-177074.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 assign { } { } - assign $1\src_r0$next[63:0]$12445 \src1_i - case - assign $1\src_r0$next[63:0]$12445 \src_r0 - end - sync always - update \src_r0$next $0\src_r0$next[63:0]$12444 - end - attribute \src "libresoc.v:177083.3-177092.6" - process $proc$libresoc.v:177083$12446 - assign { } { } - assign { } { } - assign $0\src_r1$next[63:0]$12447 $1\src_r1$next[63:0]$12448 - attribute \src "libresoc.v:177084.5-177084.29" - switch \initial - attribute \src "libresoc.v:177084.9-177084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_sel + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10110 assign { } { } - assign $1\src_r1$next[63:0]$12448 \src_or_imm + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 case - assign $1\src_r1$next[63:0]$12448 \src_r1 + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12447 + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:177093.3-177102.6" - process $proc$libresoc.v:177093$12449 + attribute \src "libresoc.v:37462.3-37504.6" + process $proc$libresoc.v:37462$826 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12450 $1\src_r2$next[63:0]$12451 - attribute \src "libresoc.v:177094.5-177094.29" + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:37463.5-37463.29" switch \initial - attribute \src "libresoc.v:177094.9-177094.17" + attribute \src "libresoc.v:37463.9-37463.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00011 assign { } { } - assign $1\src_r2$next[63:0]$12451 \src3_i - case - assign $1\src_r2$next[63:0]$12451 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[63:0]$12450 - end - attribute \src "libresoc.v:177103.3-177112.6" - process $proc$libresoc.v:177103$12452 - assign { } { } - assign { } { } - assign $0\src_r3$next[0:0]$12453 $1\src_r3$next[0:0]$12454 - attribute \src "libresoc.v:177104.5-177104.29" - switch \initial - attribute \src "libresoc.v:177104.9-177104.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10011 assign { } { } - assign $1\src_r3$next[0:0]$12454 \src4_i - case - assign $1\src_r3$next[0:0]$12454 \src_r3 - end - sync always - update \src_r3$next $0\src_r3$next[0:0]$12453 - end - attribute \src "libresoc.v:177113.3-177122.6" - process $proc$libresoc.v:177113$12455 - assign { } { } - assign { } { } - assign $0\src_r4$next[1:0]$12456 $1\src_r4$next[1:0]$12457 - attribute \src "libresoc.v:177114.5-177114.29" - switch \initial - attribute \src "libresoc.v:177114.9-177114.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [4] + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00001 assign { } { } - assign $1\src_r4$next[1:0]$12457 \src5_i - case - assign $1\src_r4$next[1:0]$12457 \src_r4 - end - sync always - update \src_r4$next $0\src_r4$next[1:0]$12456 - end - attribute \src "libresoc.v:177123.3-177131.6" - process $proc$libresoc.v:177123$12458 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12459 $1\alui_l_r_alui$next[0:0]$12460 - attribute \src "libresoc.v:177124.5-177124.29" - switch \initial - attribute \src "libresoc.v:177124.9-177124.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10001 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12460 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$12460 \$90 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12459 - end - attribute \src "libresoc.v:177132.3-177140.6" - process $proc$libresoc.v:177132$12461 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12462 $1\alu_l_r_alu$next[0:0]$12463 - attribute \src "libresoc.v:177133.5-177133.29" - switch \initial - attribute \src "libresoc.v:177133.9-177133.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12463 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$12463 \$92 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12462 - end - attribute \src "libresoc.v:177141.3-177150.6" - process $proc$libresoc.v:177141$12464 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:177142.5-177142.29" - switch \initial - attribute \src "libresoc.v:177142.9-177142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$114 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:177151.3-177160.6" - process $proc$libresoc.v:177151$12465 - assign { } { } - assign { } { } - assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:177152.5-177152.29" - switch \initial - attribute \src "libresoc.v:177152.9-177152.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$116 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00100 assign { } { } - assign $1\dest2_o[3:0] \data_r1__cr_a - case - assign $1\dest2_o[3:0] 4'0000 - end - sync always - update \dest2_o $0\dest2_o[3:0] - end - attribute \src "libresoc.v:177161.3-177170.6" - process $proc$libresoc.v:177161$12466 - assign { } { } - assign { } { } - assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:177162.5-177162.29" - switch \initial - attribute \src "libresoc.v:177162.9-177162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$118 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10100 assign { } { } - assign $1\dest3_o[1:0] \data_r2__xer_ca - case - assign $1\dest3_o[1:0] 2'00 - end - sync always - update \dest3_o $0\dest3_o[1:0] - end - attribute \src "libresoc.v:177171.3-177179.6" - process $proc$libresoc.v:177171$12467 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[2:0]$12468 $1\prev_wr_go$next[2:0]$12469 - attribute \src "libresoc.v:177172.5-177172.29" - switch \initial - attribute \src "libresoc.v:177172.9-177172.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $1\prev_wr_go$next[2:0]$12469 3'000 - case - assign $1\prev_wr_go$next[2:0]$12469 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12468 - end - connect \$100 $not$libresoc.v:176640$12245_Y - connect \$102 $and$libresoc.v:176641$12246_Y - connect \$104 $and$libresoc.v:176642$12247_Y - connect \$106 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\alu_shift_rot0_xer_so \$86 - connect \alu_shift_rot0_rc \$84 - connect \alu_shift_rot0_rb \$82 - connect \alu_shift_rot0_ra \$80 - connect \src_or_imm \$78 - connect \src_sel \$76 - connect \cu_wrmask_o { \$74 \$72 \$70 } - connect \reset_r \$62 - connect \reset_w \$60 - connect \rst_r \$58 - connect \reset \$56 - connect \wr_any \$36 - connect \cu_done_o \$30 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$18 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_shift_rot0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$14 - connect \all_rd_dly$next \all_rd - connect \all_rd \$10 -end -attribute \src "libresoc.v:177216.1-177393.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.spr" -attribute \generator "nMigen" -module \spr - attribute \src "libresoc.v:177365.3-177368.6" - wire width 7 $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 - attribute \src "libresoc.v:177365.3-177368.6" - wire width 64 $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 - attribute \src "libresoc.v:177365.3-177368.6" - wire width 64 $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 - attribute \src "libresoc.v:177365.3-177368.6" - wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:177217.7-177217.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:177370.3-177378.6" - wire $0\ren_delay$next[0:0]$12632 - attribute \src "libresoc.v:177249.3-177250.35" - wire $0\ren_delay[0:0] - attribute \src "libresoc.v:177379.3-177388.6" - wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:177370.3-177378.6" - wire $1\ren_delay$next[0:0]$12633 - attribute \src "libresoc.v:177233.7-177233.23" - wire $1\ren_delay[0:0] - attribute \src "libresoc.v:177379.3-177388.6" - wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:177369.26-177369.32" - wire width 64 $memrd$\memory$libresoc.v:177369$12630_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:177367$12624_ADDR - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:177367$12624_DATA - attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:177367$12624_EN - attribute \src "libresoc.v:177364.13-177364.16" - wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:177217.7-177217.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 7 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 7 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 3 \spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 6 \spr1__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 2 \spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire input 4 \spr1__ren - attribute \src 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64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12725 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12725 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 90 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12726 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12726 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 91 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12727 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12727 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 92 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12728 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12728 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 93 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12729 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12729 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 94 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12730 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12730 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 95 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12731 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12731 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 96 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12732 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12732 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 97 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12733 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12733 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 98 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12734 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12734 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 99 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12735 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12735 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 100 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12736 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12736 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 101 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12737 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12737 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 102 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12738 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12738 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 103 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12739 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12739 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 104 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12740 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12740 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 105 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12741 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12741 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 106 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12742 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12742 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 107 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12743 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12743 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 108 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12744 - parameter \ABITS 32 - parameter \MEMID "\\memory" - parameter \PRIORITY 12744 - parameter \WIDTH 64 - parameter \WORDS 1 - connect \ADDR 109 - connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "libresoc.v:177369.26-177369.32" - cell $memrd $memrd$\memory$libresoc.v:177369$12630 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \_0_ - connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:177369$12630_DATA - connect \EN 1'x - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12745 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 12745 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:177367$12624_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:177367$12624_DATA - connect \EN $memwr$\memory$libresoc.v:177367$12624_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12748 - sync always - sync init - end - attribute \src "libresoc.v:177217.7-177217.20" - process $proc$libresoc.v:177217$12746 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:177233.7-177233.23" - process $proc$libresoc.v:177233$12747 - assign { } { } - assign $1\ren_delay[0:0] 1'0 - sync always - sync init - update \ren_delay $1\ren_delay[0:0] - end - attribute \src "libresoc.v:177249.3-177250.35" - process $proc$libresoc.v:177249$12625 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:177365.3-177368.6" - process $proc$libresoc.v:177365$12626 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:177367.5-177367.59" - switch \spr1__wen - attribute \src "libresoc.v:177367.9-177367.18" - case 1'1 - assign $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 64'1111111111111111111111111111111111111111111111111111111111111111 - case - end - sync posedge \coresync_clk - update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:177367$12624_ADDR $0$memwr$\memory$libresoc.v:177367$12624_ADDR[6:0]$12627 - update $memwr$\memory$libresoc.v:177367$12624_DATA $0$memwr$\memory$libresoc.v:177367$12624_DATA[63:0]$12628 - update $memwr$\memory$libresoc.v:177367$12624_EN $0$memwr$\memory$libresoc.v:177367$12624_EN[63:0]$12629 - end - attribute \src "libresoc.v:177370.3-177378.6" - process $proc$libresoc.v:177370$12631 - assign { } { } - assign { } { } - assign $0\ren_delay$next[0:0]$12632 $1\ren_delay$next[0:0]$12633 - attribute \src "libresoc.v:177371.5-177371.29" - switch \initial - attribute \src "libresoc.v:177371.9-177371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10111 assign { } { } - assign $1\ren_delay$next[0:0]$12633 1'0 - case - assign $1\ren_delay$next[0:0]$12633 \spr1__ren - end - sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12632 - end - attribute \src "libresoc.v:177379.3-177388.6" - process $proc$libresoc.v:177379$12634 - assign { } { } - assign { } { } - assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:177380.5-177380.29" - switch \initial - attribute \src "libresoc.v:177380.9-177380.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch \ren_delay + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 assign { } { } - assign $1\spr1__data_o[63:0] \memory_r_data + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 case - assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \spr1__data_o $0\spr1__data_o[63:0] - end - connect \memory_r_data $memrd$\memory$libresoc.v:177369$12630_DATA - connect \memory_w_data \spr1__data_i - connect \memory_w_en \spr1__wen - connect \memory_w_addr \spr1__addr$1 - connect \memory_r_addr \spr1__addr -end -attribute \src "libresoc.v:177397.1-178644.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" -attribute \generator "nMigen" -module \spr0 - attribute \src "libresoc.v:178141.3-178142.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:178139.3-178140.40" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:178535.3-178543.6" - wire $0\alu_l_r_alu$next[0:0]$12962 - attribute \src "libresoc.v:178069.3-178070.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:178321.3-178333.6" - wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12884 - attribute \src "libresoc.v:178111.3-178112.65" - wire width 12 $0\alu_spr0_spr_op__fn_unit[11:0] - attribute \src "libresoc.v:178321.3-178333.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12885 - attribute \src "libresoc.v:178113.3-178114.59" - wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:178321.3-178333.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12886 - attribute \src "libresoc.v:178109.3-178110.69" - wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:178321.3-178333.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12887 - attribute \src "libresoc.v:178115.3-178116.67" - wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:178526.3-178534.6" - wire $0\alui_l_r_alui$next[0:0]$12959 - attribute \src "libresoc.v:178071.3-178072.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:178334.3-178355.6" - wire width 64 $0\data_r0__o$next[63:0]$12893 - attribute \src "libresoc.v:178105.3-178106.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:178334.3-178355.6" - wire $0\data_r0__o_ok$next[0:0]$12894 - attribute \src "libresoc.v:178107.3-178108.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:178356.3-178377.6" - wire width 64 $0\data_r1__spr1$next[63:0]$12901 - attribute \src "libresoc.v:178101.3-178102.43" - wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:178356.3-178377.6" - wire $0\data_r1__spr1_ok$next[0:0]$12902 - attribute \src "libresoc.v:178103.3-178104.49" - wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:178378.3-178399.6" - wire width 64 $0\data_r2__fast1$next[63:0]$12909 - attribute \src "libresoc.v:178097.3-178098.45" - wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:178378.3-178399.6" - wire $0\data_r2__fast1_ok$next[0:0]$12910 - attribute \src "libresoc.v:178099.3-178100.51" - wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:178400.3-178421.6" - wire $0\data_r3__xer_so$next[0:0]$12917 - attribute \src "libresoc.v:178093.3-178094.47" - wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:178400.3-178421.6" - wire $0\data_r3__xer_so_ok$next[0:0]$12918 - attribute \src "libresoc.v:178095.3-178096.53" - wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:178422.3-178443.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$12925 - attribute \src "libresoc.v:178089.3-178090.47" - wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:178422.3-178443.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$12926 - attribute \src "libresoc.v:178091.3-178092.53" - wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:178444.3-178465.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$12933 - attribute \src "libresoc.v:178085.3-178086.47" - wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:178444.3-178465.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$12934 - attribute \src "libresoc.v:178087.3-178088.53" - wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:178544.3-178553.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:178554.3-178563.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:178564.3-178573.6" - wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:178574.3-178583.6" - wire $0\dest4_o[0:0] - attribute \src "libresoc.v:178584.3-178593.6" - wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:178594.3-178603.6" - wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:177398.7-177398.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:178276.3-178284.6" - wire $0\opc_l_r_opc$next[0:0]$12869 - attribute \src "libresoc.v:178125.3-178126.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:178267.3-178275.6" - wire $0\opc_l_s_opc$next[0:0]$12866 - attribute \src "libresoc.v:178127.3-178128.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:178604.3-178612.6" - wire width 6 $0\prev_wr_go$next[5:0]$12971 - attribute \src "libresoc.v:178137.3-178138.37" - wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:178221.3-178230.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:178312.3-178320.6" - wire width 6 $0\req_l_r_req$next[5:0]$12881 - attribute \src "libresoc.v:178117.3-178118.39" - wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:178303.3-178311.6" - wire width 6 $0\req_l_s_req$next[5:0]$12878 - attribute \src "libresoc.v:178119.3-178120.39" - wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:178240.3-178248.6" - wire $0\rok_l_r_rdok$next[0:0]$12857 - attribute \src "libresoc.v:178133.3-178134.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:178231.3-178239.6" - wire $0\rok_l_s_rdok$next[0:0]$12854 - attribute \src "libresoc.v:178135.3-178136.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:178258.3-178266.6" - wire $0\rst_l_r_rst$next[0:0]$12863 - attribute \src "libresoc.v:178129.3-178130.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:178249.3-178257.6" - wire $0\rst_l_s_rst$next[0:0]$12860 - attribute \src "libresoc.v:178131.3-178132.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:178294.3-178302.6" - wire width 6 $0\src_l_r_src$next[5:0]$12875 - attribute \src "libresoc.v:178121.3-178122.39" - wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:178285.3-178293.6" - wire width 6 $0\src_l_s_src$next[5:0]$12872 - attribute \src "libresoc.v:178123.3-178124.39" - wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:178466.3-178475.6" - wire width 64 $0\src_r0$next[63:0]$12941 - attribute \src "libresoc.v:178083.3-178084.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:178476.3-178485.6" - wire width 64 $0\src_r1$next[63:0]$12944 - attribute \src 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$and$libresoc.v:178024$12770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [5] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178024$12770_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:178025$12771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$6 - connect \B \$8 - connect \Y $and$libresoc.v:178025$12771_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:178027$12773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$16 - connect \Y $and$libresoc.v:178027$12773_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:178029$12775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B \$20 - connect \Y $and$libresoc.v:178029$12775_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:178030$12776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:178030$12776_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:178032$12778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__rel_o - connect \B \$28 - connect \Y $and$libresoc.v:178032$12778_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:178035$12781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$26 - connect \Y $and$libresoc.v:178035$12781_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:178040$12786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B \$42 - connect \Y $and$libresoc.v:178040$12786_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:178041$12787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:178041$12787_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:178043$12789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$44 - connect \B \$48 - connect \Y $and$libresoc.v:178043$12789_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:178045$12791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$52 - connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:178045$12791_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:178046$12792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$54 - connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:178046$12792_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:178047$12793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$56 - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178047$12793_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:178052$12798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178052$12798_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:178053$12799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:178053$12799_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:178054$12800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:178054$12800_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:178056$12802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178056$12802_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:178057$12803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \spr1_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178057$12803_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:178058$12804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178058$12804_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:178059$12805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178059$12805_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:178060$12806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178060$12806_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:178061$12807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:178061$12807_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:178068$12814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:178068$12814_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:178042$12788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$46 - connect \B 1'0 - connect \Y $eq$libresoc.v:178042$12788_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:178044$12790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:178044$12790_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:178003$12749 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:178003$12749_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:178007$12753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:178007$12753_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:178026$12772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$libresoc.v:178026$12772_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:178028$12774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$libresoc.v:178028$12774_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:178031$12777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:178031$12777_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:178034$12780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $not$libresoc.v:178034$12780_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:178039$12785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:178039$12785_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:178014$12760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:178014$12760_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:178038$12784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \B \$38 - connect \Y $or$libresoc.v:178038$12784_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:178048$12794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:178048$12794_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:178049$12795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:178049$12795_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:178050$12796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:178050$12796_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:178051$12797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:178051$12797_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:178055$12801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:178055$12801_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:178020$12766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \$11 - connect \Y $reduce_and$libresoc.v:178020$12766_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:178033$12779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \$30 - connect \Y $reduce_or$libresoc.v:178033$12779_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:178036$12782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:178036$12782_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:178037$12783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:178037$12783_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:178062$12808 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:178062$12808_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:178063$12809 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:178063$12809_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:178064$12810 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:178064$12810_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:178065$12811 - parameter \WIDTH 1 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:178065$12811_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:178066$12812 - parameter \WIDTH 2 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:178066$12812_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:178067$12813 - parameter \WIDTH 2 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:178067$12813_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178143.14-178149.4" - cell \alu_l$73 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178150.12-178179.4" - cell \alu_spr0 \alu_spr0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \alu_spr0_fast1 - connect \fast1$2 \alu_spr0_fast1$2 - connect \fast1_ok \fast1_ok - connect \n_ready_i \alu_spr0_n_ready_i - connect \n_valid_o \alu_spr0_n_valid_o - connect \o \alu_spr0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_spr0_p_ready_o - connect \p_valid_i \alu_spr0_p_valid_i - connect \ra \alu_spr0_ra - connect \spr1 \alu_spr0_spr1 - connect \spr1$1 \alu_spr0_spr1$1 - connect \spr1_ok \spr1_ok - connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit - connect \spr_op__insn \alu_spr0_spr_op__insn - connect \spr_op__insn_type \alu_spr0_spr_op__insn_type - connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit - connect \xer_ca \alu_spr0_xer_ca - connect \xer_ca$5 \alu_spr0_xer_ca$5 - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov \alu_spr0_xer_ov - connect \xer_ov$4 \alu_spr0_xer_ov$4 - connect \xer_ov_ok \xer_ov_ok - connect \xer_so \alu_spr0_xer_so - connect \xer_so$3 \alu_spr0_xer_so$3 - connect \xer_so_ok \xer_so_ok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178180.15-178186.4" - cell \alui_l$72 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178187.14-178193.4" - cell \opc_l$68 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178194.14-178200.4" - cell \req_l$69 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178201.14-178207.4" - cell \rok_l$71 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178208.14-178213.4" - cell \rst_l$70 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:178214.14-178220.4" - cell \src_l$67 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src - end - attribute \src "libresoc.v:177398.7-177398.20" - process $proc$libresoc.v:177398$12973 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:177534.7-177534.24" - process $proc$libresoc.v:177534$12974 - assign { } { } - assign $1\all_rd_dly[0:0] 1'0 - sync always - sync init - update \all_rd_dly $1\all_rd_dly[0:0] - end - attribute \src "libresoc.v:177544.7-177544.26" - process $proc$libresoc.v:177544$12975 - assign { } { } - assign $1\alu_done_dly[0:0] 1'0 - sync always - sync init - update \alu_done_dly $1\alu_done_dly[0:0] - end - attribute \src "libresoc.v:177552.7-177552.25" - process $proc$libresoc.v:177552$12976 - assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 - sync always - sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:177595.14-177595.48" - process $proc$libresoc.v:177595$12977 - assign { } { } - assign $1\alu_spr0_spr_op__fn_unit[11:0] 12'000000000000 - sync always - sync init - update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:177599.14-177599.43" - process $proc$libresoc.v:177599$12978 - assign { } { } - assign $1\alu_spr0_spr_op__insn[31:0] 0 - sync always - sync init - update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] - end - attribute \src "libresoc.v:177677.13-177677.47" - process $proc$libresoc.v:177677$12979 - assign { } { } - assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 - sync always - sync init - update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] - end - attribute \src "libresoc.v:177681.7-177681.39" - process $proc$libresoc.v:177681$12980 - assign { } { } - assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 - sync always - sync init - update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:177699.7-177699.27" - process $proc$libresoc.v:177699$12981 - assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 - sync always - sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:177731.14-177731.47" - process $proc$libresoc.v:177731$12982 - assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r0__o $1\data_r0__o[63:0] - end - attribute \src "libresoc.v:177735.7-177735.27" - process $proc$libresoc.v:177735$12983 - assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 - sync always - sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:177739.14-177739.50" - process $proc$libresoc.v:177739$12984 - assign { } { } - assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r1__spr1 $1\data_r1__spr1[63:0] - end - attribute \src "libresoc.v:177743.7-177743.30" - process $proc$libresoc.v:177743$12985 - assign { } { } - assign $1\data_r1__spr1_ok[0:0] 1'0 - sync always - sync init - update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] - end - attribute \src "libresoc.v:177747.14-177747.51" - process $proc$libresoc.v:177747$12986 - assign { } { } - assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \data_r2__fast1 $1\data_r2__fast1[63:0] - end - attribute \src "libresoc.v:177751.7-177751.31" - process $proc$libresoc.v:177751$12987 - assign { } { } - assign $1\data_r2__fast1_ok[0:0] 1'0 - sync always - sync init - update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] - end - attribute \src "libresoc.v:177755.7-177755.29" - process $proc$libresoc.v:177755$12988 - assign { } { } - assign $1\data_r3__xer_so[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so $1\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:177759.7-177759.32" - process $proc$libresoc.v:177759$12989 - assign { } { } - assign $1\data_r3__xer_so_ok[0:0] 1'0 - sync always - sync init - update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:177763.13-177763.35" - process $proc$libresoc.v:177763$12990 - assign { } { } - assign $1\data_r4__xer_ov[1:0] 2'00 - sync always - sync init - update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] - end - attribute \src "libresoc.v:177767.7-177767.32" - process $proc$libresoc.v:177767$12991 - assign { } { } - assign $1\data_r4__xer_ov_ok[0:0] 1'0 - sync always - sync init - update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:177771.13-177771.35" - process $proc$libresoc.v:177771$12992 - assign { } { } - assign $1\data_r5__xer_ca[1:0] 2'00 - sync always - sync init - update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] - end - attribute \src "libresoc.v:177775.7-177775.32" - process $proc$libresoc.v:177775$12993 - assign { } { } - assign $1\data_r5__xer_ca_ok[0:0] 1'0 - sync always - sync init - update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] - end - attribute \src "libresoc.v:177803.7-177803.25" - process $proc$libresoc.v:177803$12994 - assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 - sync always - sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:177807.7-177807.25" - process $proc$libresoc.v:177807$12995 - assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 - sync always - sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:177906.13-177906.31" - process $proc$libresoc.v:177906$12996 - assign { } { } - assign $1\prev_wr_go[5:0] 6'000000 - sync always - sync init - update \prev_wr_go $1\prev_wr_go[5:0] - end - attribute \src "libresoc.v:177914.13-177914.32" - process $proc$libresoc.v:177914$12997 - assign { } { } - assign $1\req_l_r_req[5:0] 6'111111 + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end sync always - sync init - update \req_l_r_req $1\req_l_r_req[5:0] + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:177918.13-177918.32" - process $proc$libresoc.v:177918$12998 + attribute \src "libresoc.v:37505.3-37547.6" + process $proc$libresoc.v:37505$827 assign { } { } - assign $1\req_l_s_req[5:0] 6'000000 - sync always - sync init - update \req_l_s_req $1\req_l_s_req[5:0] - end - attribute \src "libresoc.v:177930.7-177930.26" - process $proc$libresoc.v:177930$12999 assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:37506.5-37506.29" + switch \initial + attribute \src "libresoc.v:37506.9-37506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end sync always - sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:177934.7-177934.26" - process $proc$libresoc.v:177934$13000 + attribute \src "libresoc.v:37548.3-37590.6" + process $proc$libresoc.v:37548$828 assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 - sync always - sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:177938.7-177938.25" - process $proc$libresoc.v:177938$13001 assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:37549.5-37549.29" + switch \initial + attribute \src "libresoc.v:37549.9-37549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end sync always - sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] end - attribute \src "libresoc.v:177942.7-177942.25" - process $proc$libresoc.v:177942$13002 + attribute \src "libresoc.v:37591.3-37633.6" + process $proc$libresoc.v:37591$829 assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 - sync always - sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:177964.13-177964.32" - process $proc$libresoc.v:177964$13003 assign { } { } - assign $1\src_l_r_src[5:0] 6'111111 + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:37592.5-37592.29" + switch \initial + attribute \src "libresoc.v:37592.9-37592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end sync always - sync init - update \src_l_r_src $1\src_l_r_src[5:0] + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:177968.13-177968.32" - process $proc$libresoc.v:177968$13004 + attribute \src "libresoc.v:37634.3-37676.6" + process $proc$libresoc.v:37634$830 assign { } { } - assign $1\src_l_s_src[5:0] 6'000000 - sync always - sync init - update \src_l_s_src $1\src_l_s_src[5:0] - end - attribute \src "libresoc.v:177972.14-177972.43" - process $proc$libresoc.v:177972$13005 assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:37635.5-37635.29" + switch \initial + attribute \src "libresoc.v:37635.9-37635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end sync always - sync init - update \src_r0 $1\src_r0[63:0] + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:177976.14-177976.43" - process $proc$libresoc.v:177976$13006 + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:37682.1-39261.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "libresoc.v:38215.3-38269.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38435.3-38489.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39150.3-39204.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39205.3-39259.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38160.3-38214.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38380.3-38434.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38875.3-38929.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37940.3-37994.6" + wire width 12 $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38930.3-38984.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38985.3-39039.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:39040.3-39094.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38545.3-38599.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38270.3-38324.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38325.3-38379.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38655.3-38709.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:37995.3-38049.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38765.3-38819.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:39095.3-39149.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:38105.3-38159.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38600.3-38654.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38820.3-38874.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38710.3-38764.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38490.3-38544.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38050.3-38104.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:37683.7-37683.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:38215.3-38269.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38435.3-38489.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:39150.3-39204.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39205.3-39259.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:38160.3-38214.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38380.3-38434.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38875.3-38929.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:37940.3-37994.6" + wire width 12 $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:38930.3-38984.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38985.3-39039.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:39040.3-39094.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:38545.3-38599.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38270.3-38324.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38325.3-38379.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38655.3-38709.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:37995.3-38049.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:38765.3-38819.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:39095.3-39149.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:38105.3-38159.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38600.3-38654.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38820.3-38874.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38710.3-38764.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38490.3-38544.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38050.3-38104.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec31_dec_sub9_upd + attribute \src "libresoc.v:37683.7-37683.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 5 \opcode_switch + attribute \src "libresoc.v:37683.7-37683.20" + process $proc$libresoc.v:37683$856 assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\initial[0:0] 1'0 sync always + update \initial $0\initial[0:0] sync init - update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:177980.14-177980.43" - process $proc$libresoc.v:177980$13007 + attribute \src "libresoc.v:37940.3-37994.6" + process $proc$libresoc.v:37940$832 assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \src_r2 $1\src_r2[63:0] - end - attribute \src "libresoc.v:177984.7-177984.20" - process $proc$libresoc.v:177984$13008 assign { } { } - assign $1\src_r3[0:0] 1'0 + assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "libresoc.v:37941.5-37941.29" + switch \initial + attribute \src "libresoc.v:37941.9-37941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end sync always - sync init - update \src_r3 $1\src_r3[0:0] + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] end - attribute \src "libresoc.v:177988.13-177988.26" - process $proc$libresoc.v:177988$13009 + attribute \src "libresoc.v:37995.3-38049.6" + process $proc$libresoc.v:37995$833 assign { } { } - assign $1\src_r4[1:0] 2'00 - sync always - sync init - update \src_r4 $1\src_r4[1:0] - end - attribute \src "libresoc.v:177992.13-177992.26" - process $proc$libresoc.v:177992$13010 assign { } { } - assign $1\src_r5[1:0] 2'00 + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:37996.5-37996.29" + switch \initial + attribute \src "libresoc.v:37996.9-37996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end sync always - sync init - update \src_r5 $1\src_r5[1:0] - end - attribute \src "libresoc.v:178069.3-178070.39" - process $proc$libresoc.v:178069$12815 - assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] - end - attribute \src "libresoc.v:178071.3-178072.43" - process $proc$libresoc.v:178071$12816 - assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] - end - attribute \src "libresoc.v:178073.3-178074.29" - process $proc$libresoc.v:178073$12817 - assign { } { } - assign $0\src_r5[1:0] \src_r5$next - sync posedge \coresync_clk - update \src_r5 $0\src_r5[1:0] - end - attribute \src "libresoc.v:178075.3-178076.29" - process $proc$libresoc.v:178075$12818 - assign { } { } - assign $0\src_r4[1:0] \src_r4$next - sync posedge \coresync_clk - update \src_r4 $0\src_r4[1:0] - end - attribute \src "libresoc.v:178077.3-178078.29" - process $proc$libresoc.v:178077$12819 - assign { } { } - assign $0\src_r3[0:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[0:0] - end - attribute \src "libresoc.v:178079.3-178080.29" - process $proc$libresoc.v:178079$12820 - assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] - end - attribute \src "libresoc.v:178081.3-178082.29" - process $proc$libresoc.v:178081$12821 - assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] - end - attribute \src "libresoc.v:178083.3-178084.29" - process $proc$libresoc.v:178083$12822 - assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] - end - attribute \src "libresoc.v:178085.3-178086.47" - process $proc$libresoc.v:178085$12823 - assign { } { } - assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next - sync posedge \coresync_clk - update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] - end - attribute \src "libresoc.v:178087.3-178088.53" - process $proc$libresoc.v:178087$12824 - assign { } { } - assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next - sync posedge \coresync_clk - update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] - end - attribute \src "libresoc.v:178089.3-178090.47" - process $proc$libresoc.v:178089$12825 - assign { } { } - assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next - sync posedge \coresync_clk - update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] - end - attribute \src "libresoc.v:178091.3-178092.53" - process $proc$libresoc.v:178091$12826 - assign { } { } - assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next - sync posedge \coresync_clk - update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] - end - attribute \src "libresoc.v:178093.3-178094.47" - process $proc$libresoc.v:178093$12827 - assign { } { } - assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next - sync posedge \coresync_clk - update \data_r3__xer_so $0\data_r3__xer_so[0:0] - end - attribute \src "libresoc.v:178095.3-178096.53" - process $proc$libresoc.v:178095$12828 - assign { } { } - assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next - sync posedge \coresync_clk - update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] - end - attribute \src "libresoc.v:178097.3-178098.45" - process $proc$libresoc.v:178097$12829 - assign { } { } - assign $0\data_r2__fast1[63:0] \data_r2__fast1$next - sync posedge \coresync_clk - update \data_r2__fast1 $0\data_r2__fast1[63:0] - end - attribute \src "libresoc.v:178099.3-178100.51" - process $proc$libresoc.v:178099$12830 - assign { } { } - assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next - sync posedge \coresync_clk - update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] - end - attribute \src "libresoc.v:178101.3-178102.43" - process $proc$libresoc.v:178101$12831 - assign { } { } - assign $0\data_r1__spr1[63:0] \data_r1__spr1$next - sync posedge \coresync_clk - update \data_r1__spr1 $0\data_r1__spr1[63:0] - end - attribute \src "libresoc.v:178103.3-178104.49" - process $proc$libresoc.v:178103$12832 - assign { } { } - assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next - sync posedge \coresync_clk - update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] - end - attribute \src "libresoc.v:178105.3-178106.37" - process $proc$libresoc.v:178105$12833 - assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] - end - attribute \src "libresoc.v:178107.3-178108.43" - process $proc$libresoc.v:178107$12834 - assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] - end - attribute \src "libresoc.v:178109.3-178110.69" - process $proc$libresoc.v:178109$12835 - assign { } { } - assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] - end - attribute \src "libresoc.v:178111.3-178112.65" - process $proc$libresoc.v:178111$12836 - assign { } { } - assign $0\alu_spr0_spr_op__fn_unit[11:0] \alu_spr0_spr_op__fn_unit$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[11:0] - end - attribute \src "libresoc.v:178113.3-178114.59" - process $proc$libresoc.v:178113$12837 - assign { } { } - assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] - end - attribute \src "libresoc.v:178115.3-178116.67" - process $proc$libresoc.v:178115$12838 - assign { } { } - assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next - sync posedge \coresync_clk - update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] - end - attribute \src "libresoc.v:178117.3-178118.39" - process $proc$libresoc.v:178117$12839 - assign { } { } - assign $0\req_l_r_req[5:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[5:0] - end - attribute \src "libresoc.v:178119.3-178120.39" - process $proc$libresoc.v:178119$12840 - assign { } { } - assign $0\req_l_s_req[5:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[5:0] - end - attribute \src "libresoc.v:178121.3-178122.39" - process $proc$libresoc.v:178121$12841 - assign { } { } - assign $0\src_l_r_src[5:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[5:0] - end - attribute \src "libresoc.v:178123.3-178124.39" - process $proc$libresoc.v:178123$12842 - assign { } { } - assign $0\src_l_s_src[5:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[5:0] - end - attribute \src "libresoc.v:178125.3-178126.39" - process $proc$libresoc.v:178125$12843 - assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] - end - attribute \src "libresoc.v:178127.3-178128.39" - process $proc$libresoc.v:178127$12844 - assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] - end - attribute \src "libresoc.v:178129.3-178130.39" - process $proc$libresoc.v:178129$12845 - assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] - end - attribute \src "libresoc.v:178131.3-178132.39" - process $proc$libresoc.v:178131$12846 - assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] - end - attribute \src "libresoc.v:178133.3-178134.41" - process $proc$libresoc.v:178133$12847 - assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:178135.3-178136.41" - process $proc$libresoc.v:178135$12848 + attribute \src "libresoc.v:38050.3-38104.6" + process $proc$libresoc.v:38050$834 assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] - end - attribute \src "libresoc.v:178137.3-178138.37" - process $proc$libresoc.v:178137$12849 assign { } { } - assign $0\prev_wr_go[5:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[5:0] + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:38051.5-38051.29" + switch \initial + attribute \src "libresoc.v:38051.9-38051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:178139.3-178140.40" - process $proc$libresoc.v:178139$12850 + attribute \src "libresoc.v:38105.3-38159.6" + process $proc$libresoc.v:38105$835 assign { } { } - assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] - end - attribute \src "libresoc.v:178141.3-178142.25" - process $proc$libresoc.v:178141$12851 assign { } { } - assign $0\all_rd_dly[0:0] \$14 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:38106.5-38106.29" + switch \initial + attribute \src "libresoc.v:38106.9-38106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:178221.3-178230.6" - process $proc$libresoc.v:178221$12852 + attribute \src "libresoc.v:38160.3-38214.6" + process $proc$libresoc.v:38160$836 assign { } { } assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:178222.5-178222.29" + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:38161.5-38161.29" switch \initial - attribute \src "libresoc.v:178222.9-178222.17" + attribute \src "libresoc.v:38161.9-38161.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $1\req_done[0:0] 1'1 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 case - assign $1\req_done[0:0] \$50 + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 end sync always - update \req_done $0\req_done[0:0] + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:178231.3-178239.6" - process $proc$libresoc.v:178231$12853 + attribute \src "libresoc.v:38215.3-38269.6" + process $proc$libresoc.v:38215$837 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12854 $1\rok_l_s_rdok$next[0:0]$12855 - attribute \src "libresoc.v:178232.5-178232.29" + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:38216.5-38216.29" switch \initial - attribute \src "libresoc.v:178232.9-178232.17" + attribute \src "libresoc.v:38216.9-38216.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12855 1'0 - case - assign $1\rok_l_s_rdok$next[0:0]$12855 \cu_issue_i - end - sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12854 - end - attribute \src "libresoc.v:178240.3-178248.6" - process $proc$libresoc.v:178240$12856 - assign { } { } - assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12857 $1\rok_l_r_rdok$next[0:0]$12858 - attribute \src "libresoc.v:178241.5-178241.29" - switch \initial - attribute \src "libresoc.v:178241.9-178241.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11100 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12858 1'1 - case - assign $1\rok_l_r_rdok$next[0:0]$12858 \$68 - end - sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12857 - end - attribute \src "libresoc.v:178249.3-178257.6" - process $proc$libresoc.v:178249$12859 - assign { } { } - assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12860 $1\rst_l_s_rst$next[0:0]$12861 - attribute \src "libresoc.v:178250.5-178250.29" - switch \initial - attribute \src "libresoc.v:178250.9-178250.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12861 1'0 - case - assign $1\rst_l_s_rst$next[0:0]$12861 \all_rd - end - sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12860 - end - attribute \src "libresoc.v:178258.3-178266.6" - process $proc$libresoc.v:178258$12862 - assign { } { } - assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12863 $1\rst_l_r_rst$next[0:0]$12864 - attribute \src "libresoc.v:178259.5-178259.29" - switch \initial - attribute \src "libresoc.v:178259.9-178259.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12864 1'1 - case - assign $1\rst_l_r_rst$next[0:0]$12864 \rst_r - end - sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12863 - end - attribute \src "libresoc.v:178267.3-178275.6" - process $proc$libresoc.v:178267$12865 - assign { } { } - assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12866 $1\opc_l_s_opc$next[0:0]$12867 - attribute \src "libresoc.v:178268.5-178268.29" - switch \initial - attribute \src "libresoc.v:178268.9-178268.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12867 1'0 - case - assign $1\opc_l_s_opc$next[0:0]$12867 \cu_issue_i - end - sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12866 - end - attribute \src "libresoc.v:178276.3-178284.6" - process $proc$libresoc.v:178276$12868 - assign { } { } - assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12869 $1\opc_l_r_opc$next[0:0]$12870 - attribute \src "libresoc.v:178277.5-178277.29" - switch \initial - attribute \src "libresoc.v:178277.9-178277.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12870 1'1 - case - assign $1\opc_l_r_opc$next[0:0]$12870 \req_done - end - sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12869 - end - attribute \src "libresoc.v:178285.3-178293.6" - process $proc$libresoc.v:178285$12871 - assign { } { } - assign { } { } - assign $0\src_l_s_src$next[5:0]$12872 $1\src_l_s_src$next[5:0]$12873 - attribute \src "libresoc.v:178286.5-178286.29" - switch \initial - attribute \src "libresoc.v:178286.9-178286.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 assign { } { } - assign $1\src_l_s_src$next[5:0]$12873 6'000000 - case - assign $1\src_l_s_src$next[5:0]$12873 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - end - sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12872 - end - attribute \src "libresoc.v:178294.3-178302.6" - process $proc$libresoc.v:178294$12874 - assign { } { } - assign { } { } - assign $0\src_l_r_src$next[5:0]$12875 $1\src_l_r_src$next[5:0]$12876 - attribute \src "libresoc.v:178295.5-178295.29" - switch \initial - attribute \src "libresoc.v:178295.9-178295.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } - assign $1\src_l_r_src$next[5:0]$12876 6'111111 - case - assign $1\src_l_r_src$next[5:0]$12876 \reset_r - end - sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12875 - end - attribute \src "libresoc.v:178303.3-178311.6" - process $proc$libresoc.v:178303$12877 - assign { } { } - assign { } { } - assign $0\req_l_s_req$next[5:0]$12878 $1\req_l_s_req$next[5:0]$12879 - attribute \src "libresoc.v:178304.5-178304.29" - switch \initial - attribute \src "libresoc.v:178304.9-178304.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $1\req_l_s_req$next[5:0]$12879 6'000000 - case - assign $1\req_l_s_req$next[5:0]$12879 \$70 - end - sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12878 - end - attribute \src "libresoc.v:178312.3-178320.6" - process $proc$libresoc.v:178312$12880 - assign { } { } - assign { } { } - assign $0\req_l_r_req$next[5:0]$12881 $1\req_l_r_req$next[5:0]$12882 - attribute \src "libresoc.v:178313.5-178313.29" - switch \initial - attribute \src "libresoc.v:178313.9-178313.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11000 assign { } { } - assign $1\req_l_r_req$next[5:0]$12882 6'111111 - case - assign $1\req_l_r_req$next[5:0]$12882 \$72 - end - sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12881 - end - attribute \src "libresoc.v:178321.3-178333.6" - process $proc$libresoc.v:178321$12883 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12884 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12888 - assign $0\alu_spr0_spr_op__insn$next[31:0]$12885 $1\alu_spr0_spr_op__insn$next[31:0]$12889 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12886 $1\alu_spr0_spr_op__insn_type$next[6:0]$12890 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12887 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12891 - attribute \src "libresoc.v:178322.5-178322.29" - switch \initial - attribute \src "libresoc.v:178322.9-178322.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12891 $1\alu_spr0_spr_op__insn$next[31:0]$12889 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12888 $1\alu_spr0_spr_op__insn_type$next[6:0]$12890 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 case - assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12888 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$12889 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12890 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12891 \alu_spr0_spr_op__is_32bit + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12884 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12885 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12886 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12887 + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:178334.3-178355.6" - process $proc$libresoc.v:178334$12892 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:38270.3-38324.6" + process $proc$libresoc.v:38270$838 assign { } { } assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$12893 $2\data_r0__o$next[63:0]$12897 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12894 $3\data_r0__o_ok$next[0:0]$12899 - attribute \src "libresoc.v:178335.5-178335.29" + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:38271.5-38271.29" switch \initial - attribute \src "libresoc.v:178335.9-178335.17" + attribute \src "libresoc.v:38271.9-38271.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12896 $1\data_r0__o$next[63:0]$12895 } { \o_ok \alu_spr0_o } - case - assign $1\data_r0__o$next[63:0]$12895 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12896 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12898 $2\data_r0__o$next[63:0]$12897 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r0__o$next[63:0]$12897 $1\data_r0__o$next[63:0]$12895 - assign $2\data_r0__o_ok$next[0:0]$12898 $1\data_r0__o_ok$next[0:0]$12896 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12899 1'0 - case - assign $3\data_r0__o_ok$next[0:0]$12899 $2\data_r0__o_ok$next[0:0]$12898 - end - sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12893 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12894 - end - attribute \src "libresoc.v:178356.3-178377.6" - process $proc$libresoc.v:178356$12900 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__spr1$next[63:0]$12901 $2\data_r1__spr1$next[63:0]$12905 - assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$12902 $3\data_r1__spr1_ok$next[0:0]$12907 - attribute \src "libresoc.v:178357.5-178357.29" - switch \initial - attribute \src "libresoc.v:178357.9-178357.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$12904 $1\data_r1__spr1$next[63:0]$12903 } { \spr1_ok \alu_spr0_spr1 } - case - assign $1\data_r1__spr1$next[63:0]$12903 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$12904 \data_r1__spr1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$12906 $2\data_r1__spr1$next[63:0]$12905 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r1__spr1$next[63:0]$12905 $1\data_r1__spr1$next[63:0]$12903 - assign $2\data_r1__spr1_ok$next[0:0]$12906 $1\data_r1__spr1_ok$next[0:0]$12904 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11000 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$12907 1'0 - case - assign $3\data_r1__spr1_ok$next[0:0]$12907 $2\data_r1__spr1_ok$next[0:0]$12906 - end - sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12901 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12902 - end - attribute \src "libresoc.v:178378.3-178399.6" - process $proc$libresoc.v:178378$12908 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r2__fast1$next[63:0]$12909 $2\data_r2__fast1$next[63:0]$12913 - assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$12910 $3\data_r2__fast1_ok$next[0:0]$12915 - attribute \src "libresoc.v:178379.5-178379.29" - switch \initial - attribute \src "libresoc.v:178379.9-178379.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$12912 $1\data_r2__fast1$next[63:0]$12911 } { \fast1_ok \alu_spr0_fast1 } - case - assign $1\data_r2__fast1$next[63:0]$12911 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$12912 \data_r2__fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10010 assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$12914 $2\data_r2__fast1$next[63:0]$12913 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r2__fast1$next[63:0]$12913 $1\data_r2__fast1$next[63:0]$12911 - assign $2\data_r2__fast1_ok$next[0:0]$12914 $1\data_r2__fast1_ok$next[0:0]$12912 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$12915 1'0 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$12915 $2\data_r2__fast1_ok$next[0:0]$12914 + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12909 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12910 + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:178400.3-178421.6" - process $proc$libresoc.v:178400$12916 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:38325.3-38379.6" + process $proc$libresoc.v:38325$839 assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$12917 $2\data_r3__xer_so$next[0:0]$12921 - assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$12918 $3\data_r3__xer_so_ok$next[0:0]$12923 - attribute \src "libresoc.v:178401.5-178401.29" + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:38326.5-38326.29" switch \initial - attribute \src "libresoc.v:178401.9-178401.17" + attribute \src "libresoc.v:38326.9-38326.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$12920 $1\data_r3__xer_so$next[0:0]$12919 } { \xer_so_ok \alu_spr0_xer_so } - case - assign $1\data_r3__xer_so$next[0:0]$12919 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$12920 \data_r3__xer_so_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$12922 $2\data_r3__xer_so$next[0:0]$12921 } 2'00 - case - assign $2\data_r3__xer_so$next[0:0]$12921 $1\data_r3__xer_so$next[0:0]$12919 - assign $2\data_r3__xer_so_ok$next[0:0]$12922 $1\data_r3__xer_so_ok$next[0:0]$12920 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$12923 1'0 - case - assign $3\data_r3__xer_so_ok$next[0:0]$12923 $2\data_r3__xer_so_ok$next[0:0]$12922 - end - sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12917 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12918 - end - attribute \src "libresoc.v:178422.3-178443.6" - process $proc$libresoc.v:178422$12924 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$12925 $2\data_r4__xer_ov$next[1:0]$12929 - assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$12926 $3\data_r4__xer_ov_ok$next[0:0]$12931 - attribute \src "libresoc.v:178423.5-178423.29" - switch \initial - attribute \src "libresoc.v:178423.9-178423.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$12928 $1\data_r4__xer_ov$next[1:0]$12927 } { \xer_ov_ok \alu_spr0_xer_ov } - case - assign $1\data_r4__xer_ov$next[1:0]$12927 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$12928 \data_r4__xer_ov_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$12930 $2\data_r4__xer_ov$next[1:0]$12929 } 3'000 - case - assign $2\data_r4__xer_ov$next[1:0]$12929 $1\data_r4__xer_ov$next[1:0]$12927 - assign $2\data_r4__xer_ov_ok$next[0:0]$12930 $1\data_r4__xer_ov_ok$next[0:0]$12928 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11000 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$12931 1'0 - case - assign $3\data_r4__xer_ov_ok$next[0:0]$12931 $2\data_r4__xer_ov_ok$next[0:0]$12930 - end - sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12925 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12926 - end - attribute \src "libresoc.v:178444.3-178465.6" - process $proc$libresoc.v:178444$12932 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$12933 $2\data_r5__xer_ca$next[1:0]$12937 - assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$12934 $3\data_r5__xer_ca_ok$next[0:0]$12939 - attribute \src "libresoc.v:178445.5-178445.29" - switch \initial - attribute \src "libresoc.v:178445.9-178445.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$12936 $1\data_r5__xer_ca$next[1:0]$12935 } { \xer_ca_ok \alu_spr0_xer_ca } - case - assign $1\data_r5__xer_ca$next[1:0]$12935 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$12936 \data_r5__xer_ca_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10010 assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$12938 $2\data_r5__xer_ca$next[1:0]$12937 } 3'000 - case - assign $2\data_r5__xer_ca$next[1:0]$12937 $1\data_r5__xer_ca$next[1:0]$12935 - assign $2\data_r5__xer_ca_ok$next[0:0]$12938 $1\data_r5__xer_ca_ok$next[0:0]$12936 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00111 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$12939 1'0 - case - assign $3\data_r5__xer_ca_ok$next[0:0]$12939 $2\data_r5__xer_ca_ok$next[0:0]$12938 - end - sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12933 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12934 - end - attribute \src "libresoc.v:178466.3-178475.6" - process $proc$libresoc.v:178466$12940 - assign { } { } - assign { } { } - assign $0\src_r0$next[63:0]$12941 $1\src_r0$next[63:0]$12942 - attribute \src "libresoc.v:178467.5-178467.29" - switch \initial - attribute \src "libresoc.v:178467.9-178467.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10111 assign { } { } - assign $1\src_r0$next[63:0]$12942 \src1_i + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 case - assign $1\src_r0$next[63:0]$12942 \src_r0 + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12941 + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:178476.3-178485.6" - process $proc$libresoc.v:178476$12943 + attribute \src "libresoc.v:38380.3-38434.6" + process $proc$libresoc.v:38380$840 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12944 $1\src_r1$next[63:0]$12945 - attribute \src "libresoc.v:178477.5-178477.29" + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:38381.5-38381.29" switch \initial - attribute \src "libresoc.v:178477.9-178477.17" + attribute \src "libresoc.v:38381.9-38381.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01100 assign { } { } - assign $1\src_r1$next[63:0]$12945 \src2_i - case - assign $1\src_r1$next[63:0]$12945 \src_r1 - end - sync always - update \src_r1$next $0\src_r1$next[63:0]$12944 - end - attribute \src "libresoc.v:178486.3-178495.6" - process $proc$libresoc.v:178486$12946 - assign { } { } - assign { } { } - assign $0\src_r2$next[63:0]$12947 $1\src_r2$next[63:0]$12948 - attribute \src "libresoc.v:178487.5-178487.29" - switch \initial - attribute \src "libresoc.v:178487.9-178487.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11100 assign { } { } - assign $1\src_r2$next[63:0]$12948 \src3_i - case - assign $1\src_r2$next[63:0]$12948 \src_r2 - end - sync always - update \src_r2$next $0\src_r2$next[63:0]$12947 - end - attribute \src "libresoc.v:178496.3-178505.6" - process $proc$libresoc.v:178496$12949 - assign { } { } - assign { } { } - assign $0\src_r3$next[0:0]$12950 $1\src_r3$next[0:0]$12951 - attribute \src "libresoc.v:178497.5-178497.29" - switch \initial - attribute \src "libresoc.v:178497.9-178497.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01101 assign { } { } - assign $1\src_r3$next[0:0]$12951 \src4_i - case - assign $1\src_r3$next[0:0]$12951 \src_r3 - end - sync always - update \src_r3$next $0\src_r3$next[0:0]$12950 - end - attribute \src "libresoc.v:178506.3-178515.6" - process $proc$libresoc.v:178506$12952 - assign { } { } - assign { } { } - assign $0\src_r4$next[1:0]$12953 $1\src_r4$next[1:0]$12954 - attribute \src "libresoc.v:178507.5-178507.29" - switch \initial - attribute \src "libresoc.v:178507.9-178507.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [4] + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11101 assign { } { } - assign $1\src_r4$next[1:0]$12954 \src5_i - case - assign $1\src_r4$next[1:0]$12954 \src_r4 - end - sync always - update \src_r4$next $0\src_r4$next[1:0]$12953 - end - attribute \src "libresoc.v:178516.3-178525.6" - process $proc$libresoc.v:178516$12955 - assign { } { } - assign { } { } - assign $0\src_r5$next[1:0]$12956 $1\src_r5$next[1:0]$12957 - attribute \src "libresoc.v:178517.5-178517.29" - switch \initial - attribute \src "libresoc.v:178517.9-178517.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [5] + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01110 assign { } { } - assign $1\src_r5$next[1:0]$12957 \src6_i - case - assign $1\src_r5$next[1:0]$12957 \src_r5 - end - sync always - update \src_r5$next $0\src_r5$next[1:0]$12956 - end - attribute \src "libresoc.v:178526.3-178534.6" - process $proc$libresoc.v:178526$12958 - assign { } { } - assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12959 $1\alui_l_r_alui$next[0:0]$12960 - attribute \src "libresoc.v:178527.5-178527.29" - switch \initial - attribute \src "libresoc.v:178527.9-178527.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11110 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12960 1'1 - case - assign $1\alui_l_r_alui$next[0:0]$12960 \$98 - end - sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12959 - end - attribute \src "libresoc.v:178535.3-178543.6" - process $proc$libresoc.v:178535$12961 - assign { } { } - assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12962 $1\alu_l_r_alu$next[0:0]$12963 - attribute \src "libresoc.v:178536.5-178536.29" - switch \initial - attribute \src "libresoc.v:178536.9-178536.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01111 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12963 1'1 - case - assign $1\alu_l_r_alu$next[0:0]$12963 \$100 - end - sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12962 - end - attribute \src "libresoc.v:178544.3-178553.6" - process $proc$libresoc.v:178544$12964 - assign { } { } - assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:178545.5-178545.29" - switch \initial - attribute \src "libresoc.v:178545.9-178545.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$126 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11111 assign { } { } - assign $1\dest1_o[63:0] \data_r0__o - case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest1_o $0\dest1_o[63:0] - end - attribute \src "libresoc.v:178554.3-178563.6" - process $proc$libresoc.v:178554$12965 - assign { } { } - assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:178555.5-178555.29" - switch \initial - attribute \src "libresoc.v:178555.9-178555.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$128 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'01000 assign { } { } - assign $1\dest2_o[63:0] \data_r1__spr1 - case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest2_o $0\dest2_o[63:0] - end - attribute \src "libresoc.v:178564.3-178573.6" - process $proc$libresoc.v:178564$12966 - assign { } { } - assign { } { } - assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:178565.5-178565.29" - switch \initial - attribute \src "libresoc.v:178565.9-178565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$130 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'11000 assign { } { } - assign $1\dest3_o[63:0] \data_r2__fast1 - case - assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dest3_o $0\dest3_o[63:0] - end - attribute \src "libresoc.v:178574.3-178583.6" - process $proc$libresoc.v:178574$12967 - assign { } { } - assign { } { } - assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:178575.5-178575.29" - switch \initial - attribute \src "libresoc.v:178575.9-178575.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$132 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00010 assign { } { } - assign $1\dest4_o[0:0] \data_r3__xer_so - case - assign $1\dest4_o[0:0] 1'0 - end - sync always - update \dest4_o $0\dest4_o[0:0] - end - attribute \src "libresoc.v:178584.3-178593.6" - process $proc$libresoc.v:178584$12968 - assign { } { } - assign { } { } - assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:178585.5-178585.29" - switch \initial - attribute \src "libresoc.v:178585.9-178585.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$134 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'00000 assign { } { } - assign $1\dest5_o[1:0] \data_r4__xer_ov - case - assign $1\dest5_o[1:0] 2'00 - end - sync always - update \dest5_o $0\dest5_o[1:0] - end - attribute \src "libresoc.v:178594.3-178603.6" - process $proc$libresoc.v:178594$12969 - assign { } { } - assign { } { } - assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:178595.5-178595.29" - switch \initial - attribute \src "libresoc.v:178595.9-178595.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$136 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10010 assign { } { } - assign $1\dest6_o[1:0] \data_r5__xer_ca - case - assign $1\dest6_o[1:0] 2'00 - end - sync always - update \dest6_o $0\dest6_o[1:0] - end - attribute \src "libresoc.v:178604.3-178612.6" - process $proc$libresoc.v:178604$12970 - assign { } { } - assign { } { } - assign $0\prev_wr_go$next[5:0]$12971 $1\prev_wr_go$next[5:0]$12972 - attribute \src "libresoc.v:178605.5-178605.29" - switch \initial - attribute \src "libresoc.v:178605.9-178605.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 5'10000 assign { } { } - assign $1\prev_wr_go$next[5:0]$12972 6'000000 - case - assign $1\prev_wr_go$next[5:0]$12972 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12971 - end - connect \$9 $not$libresoc.v:178003$12749_Y - connect \$100 $and$libresoc.v:178004$12750_Y - connect \$102 $and$libresoc.v:178005$12751_Y - connect \$104 $and$libresoc.v:178006$12752_Y - connect \$106 $not$libresoc.v:178007$12753_Y - connect \$108 $and$libresoc.v:178008$12754_Y - connect \$110 $and$libresoc.v:178009$12755_Y - connect \$112 $and$libresoc.v:178010$12756_Y - connect \$114 $and$libresoc.v:178011$12757_Y - connect \$116 $and$libresoc.v:178012$12758_Y - connect \$118 $and$libresoc.v:178013$12759_Y - connect \$11 $or$libresoc.v:178014$12760_Y - connect \$120 $and$libresoc.v:178015$12761_Y - connect \$122 $and$libresoc.v:178016$12762_Y - connect \$124 $and$libresoc.v:178017$12763_Y - connect \$126 $and$libresoc.v:178018$12764_Y - connect \$128 $and$libresoc.v:178019$12765_Y - connect \$8 $reduce_and$libresoc.v:178020$12766_Y - connect \$130 $and$libresoc.v:178021$12767_Y - connect \$132 $and$libresoc.v:178022$12768_Y - connect \$134 $and$libresoc.v:178023$12769_Y - connect \$136 $and$libresoc.v:178024$12770_Y - connect \$14 $and$libresoc.v:178025$12771_Y - connect \$16 $not$libresoc.v:178026$12772_Y - connect \$18 $and$libresoc.v:178027$12773_Y - connect \$20 $not$libresoc.v:178028$12774_Y - connect \$22 $and$libresoc.v:178029$12775_Y - connect \$24 $and$libresoc.v:178030$12776_Y - connect \$28 $not$libresoc.v:178031$12777_Y - connect \$30 $and$libresoc.v:178032$12778_Y - connect \$27 $reduce_or$libresoc.v:178033$12779_Y - connect \$26 $not$libresoc.v:178034$12780_Y - connect \$34 $and$libresoc.v:178035$12781_Y - connect \$36 $reduce_or$libresoc.v:178036$12782_Y - connect \$38 $reduce_or$libresoc.v:178037$12783_Y - connect \$40 $or$libresoc.v:178038$12784_Y - connect \$42 $not$libresoc.v:178039$12785_Y - connect \$44 $and$libresoc.v:178040$12786_Y - connect \$46 $and$libresoc.v:178041$12787_Y - connect \$48 $eq$libresoc.v:178042$12788_Y - connect \$50 $and$libresoc.v:178043$12789_Y - connect \$52 $eq$libresoc.v:178044$12790_Y - connect \$54 $and$libresoc.v:178045$12791_Y - connect \$56 $and$libresoc.v:178046$12792_Y - connect \$58 $and$libresoc.v:178047$12793_Y - connect \$60 $or$libresoc.v:178048$12794_Y - connect \$62 $or$libresoc.v:178049$12795_Y - connect \$64 $or$libresoc.v:178050$12796_Y - connect \$66 $or$libresoc.v:178051$12797_Y - connect \$68 $and$libresoc.v:178052$12798_Y - connect \$6 $and$libresoc.v:178053$12799_Y - connect \$70 $and$libresoc.v:178054$12800_Y - connect \$72 $or$libresoc.v:178055$12801_Y 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\$94 - connect \alu_spr0_xer_so$3 \$92 - connect \alu_spr0_fast1$2 \$90 - connect \alu_spr0_spr1$1 \$88 - connect \alu_spr0_ra \$86 - connect \cu_wrmask_o { \$84 \$82 \$80 \$78 \$76 \$74 } - connect \reset_r \$66 - connect \reset_w \$64 - connect \rst_r \$62 - connect \reset \$60 - connect \wr_any \$40 - connect \cu_done_o \$34 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$22 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_spr0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$18 - connect \all_rd_dly$next \all_rd - connect \all_rd \$14 -end -attribute \src "libresoc.v:178648.1-179162.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" -attribute \generator "nMigen" -module \spr_main - attribute \src "libresoc.v:178915.3-178930.6" - wire width 64 $0\fast1$7[63:0]$13019 - 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1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178909$13012_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178910$13013 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178910$13013_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178911$13014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178911$13014_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178912$13015 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178912$13015_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:178913$13016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178913$13016_Y - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:178914$13017 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $eq$libresoc.v:178914$13017_Y - end - attribute \src "libresoc.v:178649.7-178649.20" - process $proc$libresoc.v:178649$13047 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:178915.3-178930.6" - process $proc$libresoc.v:178915$13018 - assign { } { } - assign { } { } - assign $0\fast1$7[63:0]$13019 $1\fast1$7[63:0]$13020 - attribute \src "libresoc.v:178916.5-178916.29" - switch \initial - attribute \src "libresoc.v:178916.9-178916.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'00111 assign { } { } - assign $1\fast1$7[63:0]$13020 $2\fast1$7[63:0]$13021 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\fast1$7[63:0]$13021 \ra - case - assign $2\fast1$7[63:0]$13021 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\fast1$7[63:0]$13020 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \fast1$7 $0\fast1$7[63:0]$13019 - end - attribute \src "libresoc.v:178931.3-178949.6" - process $proc$libresoc.v:178931$13022 - assign { } { } - assign { } { } - assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:178932.5-178932.29" - switch \initial - attribute \src "libresoc.v:178932.9-178932.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'10111 assign { } { } - assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1_ok[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\spr1_ok[0:0] 1'1 - end + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 case - assign $1\spr1_ok[0:0] 1'0 + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 end sync always - update \spr1_ok $0\spr1_ok[0:0] + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:178950.3-178991.6" - process $proc$libresoc.v:178950$13023 - assign { } { } + attribute \src "libresoc.v:38435.3-38489.6" + process $proc$libresoc.v:38435$841 assign { } { } assign { } { } - assign { } { } - assign $0\o_ok[0:0] $1\o_ok[0:0] - assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:178951.5-178951.29" + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:38436.5-38436.29" switch \initial - attribute \src "libresoc.v:178951.9-178951.17" + attribute \src "libresoc.v:38436.9-38436.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0101110 + case 5'01100 assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 assign { } { } - assign $1\o_ok[0:0] 1'1 - assign $1\o[63:0] $2\o[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 - assign { } { } - assign $2\o[63:0] [17:0] \fast1 [17:0] - assign $2\o[63:0] [63:18] $3\o[63:18] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - switch \$23 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\o[63:18] [45:14] 0 - assign $3\o[63:18] [10:2] 9'000000000 - assign $3\o[63:18] [13] \xer_so - assign $3\o[63:18] [12] \xer_ov [0] - assign $3\o[63:18] [1] \xer_ov [1] - assign $3\o[63:18] [11] \xer_ca [0] - assign $3\o[63:18] [0] \xer_ca [1] - case - assign $3\o[63:18] \fast1 [63:18] - end - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign $2\o[63:0] [63:32] 0 - assign $2\o[63:0] [31:0] \fast1 [63:32] - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\o[63:0] \spr1 - end - case - assign $1\o_ok[0:0] 1'0 - assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \o_ok $0\o_ok[0:0] - update \o $0\o[63:0] - end - attribute \src "libresoc.v:178992.3-179007.6" - process $proc$libresoc.v:178992$13024 - assign { } { } - assign { } { } - assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:178993.5-178993.29" - switch \initial - attribute \src "libresoc.v:178993.9-178993.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + assign $1\dec31_dec_sub9_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'01101 assign { } { } - assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\fast1_ok[0:0] 1'1 - case - assign $2\fast1_ok[0:0] 1'0 - end + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 case - assign $1\fast1_ok[0:0] 1'0 + assign $1\dec31_dec_sub9_br[0:0] 1'0 end sync always - update \fast1_ok $0\fast1_ok[0:0] + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:179008.3-179028.6" - process $proc$libresoc.v:179008$13025 + attribute \src "libresoc.v:38490.3-38544.6" + process $proc$libresoc.v:38490$842 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$13026 $1\xer_so$8[0:0]$13027 - attribute \src "libresoc.v:179009.5-179009.29" + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:38491.5-38491.29" switch \initial - attribute \src "libresoc.v:179009.9-179009.17" + attribute \src "libresoc.v:38491.9-38491.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'10000 assign { } { } - assign $1\xer_so$8[0:0]$13027 $2\xer_so$8[0:0]$13028 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_so$8[0:0]$13028 $3\xer_so$8[0:0]$13029 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$11 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_so$8[0:0]$13029 \ra [31] - case - assign $3\xer_so$8[0:0]$13029 1'0 - end - case - assign $2\xer_so$8[0:0]$13028 1'0 - end + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 case - assign $1\xer_so$8[0:0]$13027 1'0 + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$13026 + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:179029.3-179049.6" - process $proc$libresoc.v:179029$13030 + attribute \src "libresoc.v:38545.3-38599.6" + process $proc$libresoc.v:38545$843 assign { } { } assign { } { } - assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:179030.5-179030.29" + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:38546.5-38546.29" switch \initial - attribute \src "libresoc.v:179030.9-179030.17" + attribute \src "libresoc.v:38546.9-38546.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'01100 assign { } { } - assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$13 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_so_ok[0:0] 1'1 - case - assign $3\xer_so_ok[0:0] 1'0 - end - case - assign $2\xer_so_ok[0:0] 1'0 - end + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 case - assign $1\xer_so_ok[0:0] 1'0 + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 end sync always - update \xer_so_ok $0\xer_so_ok[0:0] + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:179050.3-179073.6" - process $proc$libresoc.v:179050$13031 + attribute \src "libresoc.v:38600.3-38654.6" + process $proc$libresoc.v:38600$844 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$13032 $1\xer_ov$9[1:0]$13033 - attribute \src "libresoc.v:179051.5-179051.29" + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:38601.5-38601.29" switch \initial - attribute \src "libresoc.v:179051.9-179051.17" + attribute \src "libresoc.v:38601.9-38601.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'01100 assign { } { } - assign $1\xer_ov$9[1:0]$13033 $2\xer_ov$9[1:0]$13034 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ov$9[1:0]$13034 $3\xer_ov$9[1:0]$13035 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$15 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ov$9[1:0]$13035 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13035 [1] \ra [19] - case - assign $3\xer_ov$9[1:0]$13035 2'00 - end - case - assign $2\xer_ov$9[1:0]$13034 2'00 - end + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 case - assign $1\xer_ov$9[1:0]$13033 2'00 + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$13032 + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:179074.3-179094.6" - process $proc$libresoc.v:179074$13036 + attribute \src "libresoc.v:38655.3-38709.6" + process $proc$libresoc.v:38655$845 assign { } { } assign { } { } - assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:179075.5-179075.29" + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:38656.5-38656.29" switch \initial - attribute \src "libresoc.v:179075.9-179075.17" + attribute \src "libresoc.v:38656.9-38656.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'01100 assign { } { } - assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$17 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ov_ok[0:0] 1'1 - case - assign $3\xer_ov_ok[0:0] 1'0 - end - case - assign $2\xer_ov_ok[0:0] 1'0 - end + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 case - assign $1\xer_ov_ok[0:0] 1'0 + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 end sync always - update \xer_ov_ok $0\xer_ov_ok[0:0] + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:179095.3-179118.6" - process $proc$libresoc.v:179095$13037 + attribute \src "libresoc.v:38710.3-38764.6" + process $proc$libresoc.v:38710$846 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13038 $1\xer_ca$10[1:0]$13039 - attribute \src "libresoc.v:179096.5-179096.29" + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:38711.5-38711.29" switch \initial - attribute \src "libresoc.v:179096.9-179096.17" + attribute \src "libresoc.v:38711.9-38711.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'11100 assign { } { } - assign $1\xer_ca$10[1:0]$13039 $2\xer_ca$10[1:0]$13040 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ca$10[1:0]$13040 $3\xer_ca$10[1:0]$13041 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$19 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ca$10[1:0]$13041 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13041 [1] \ra [18] - case - assign $3\xer_ca$10[1:0]$13041 2'00 - end - case - assign $2\xer_ca$10[1:0]$13040 2'00 - end + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 case - assign $1\xer_ca$10[1:0]$13039 2'00 + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13038 + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:179119.3-179139.6" - process $proc$libresoc.v:179119$13042 + attribute \src "libresoc.v:38765.3-38819.6" + process $proc$libresoc.v:38765$847 assign { } { } assign { } { } - assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:179120.5-179120.29" + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:38766.5-38766.29" switch \initial - attribute \src "libresoc.v:179120.9-179120.17" + attribute \src "libresoc.v:38766.9-38766.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'01100 assign { } { } - assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign { } { } - assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch \$21 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\xer_ca_ok[0:0] 1'1 - case - assign $3\xer_ca_ok[0:0] 1'0 - end - case - assign $2\xer_ca_ok[0:0] 1'0 - end + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 case - assign $1\xer_ca_ok[0:0] 1'0 + assign $1\dec31_dec_sub9_lk[0:0] 1'0 end sync always - update \xer_ca_ok $0\xer_ca_ok[0:0] + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:179140.3-179158.6" - process $proc$libresoc.v:179140$13043 + attribute \src "libresoc.v:38820.3-38874.6" + process $proc$libresoc.v:38820$848 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13044 $1\spr1$6[63:0]$13045 - attribute \src "libresoc.v:179141.5-179141.29" + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:38821.5-38821.29" switch \initial - attribute \src "libresoc.v:179141.9-179141.17" + attribute \src "libresoc.v:38821.9-38821.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 7'0110001 + case 5'01100 assign { } { } - assign $1\spr1$6[63:0]$13045 $2\spr1$6[63:0]$13046 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13046 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\spr1$6[63:0]$13046 \ra - end + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 case - assign $1\spr1$6[63:0]$13045 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 end sync always - update \spr1$6 $0\spr1$6[63:0]$13044 - end - connect \$11 $eq$libresoc.v:178908$13011_Y - connect \$13 $eq$libresoc.v:178909$13012_Y - connect \$15 $eq$libresoc.v:178910$13013_Y - connect \$17 $eq$libresoc.v:178911$13014_Y - connect \$19 $eq$libresoc.v:178912$13015_Y - connect \$21 $eq$libresoc.v:178913$13016_Y - connect \$23 $eq$libresoc.v:178914$13017_Y - connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - connect \muxid$1 \muxid - connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } -end -attribute \src "libresoc.v:179166.1-179981.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" -attribute \generator "nMigen" -module \sprmap - attribute \src "libresoc.v:179293.3-179323.6" - wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:179324.3-179354.6" - wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:179167.7-179167.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:179355.3-179667.6" - wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:179668.3-179980.6" - wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:179293.3-179323.6" - wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:179324.3-179354.6" - wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:179355.3-179667.6" - wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:179668.3-179980.6" - wire $1\spr_o_ok[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \fast_o_ok - attribute \src "libresoc.v:179167.7-179167.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" - wire width 10 input 5 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \spr_o_ok - attribute \src "libresoc.v:179167.7-179167.20" - process $proc$libresoc.v:179167$13052 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:179293.3-179323.6" - process $proc$libresoc.v:179293$13048 + attribute \src "libresoc.v:38875.3-38929.6" + process $proc$libresoc.v:38875$849 assign { } { } assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:179294.5-179294.29" + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:38876.5-38876.29" switch \initial - attribute \src "libresoc.v:179294.9-179294.17" + attribute \src "libresoc.v:38876.9-38876.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 + case 5'01100 assign { } { } - assign $1\fast_o[2:0] 3'101 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 + case 5'11100 assign { } { } - assign $1\fast_o[2:0] 3'001 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 + case 5'01101 assign { } { } - assign $1\fast_o[2:0] 3'000 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 + case 5'11101 assign { } { } - assign $1\fast_o[2:0] 3'110 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 + case 5'01110 assign { } { } - assign $1\fast_o[2:0] 3'011 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 + case 5'11110 assign { } { } - assign $1\fast_o[2:0] 3'100 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 + case 5'01111 assign { } { } - assign $1\fast_o[2:0] 3'111 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 + case 5'11111 assign { } { } - assign $1\fast_o[2:0] 3'010 + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 case - assign $1\fast_o[2:0] 3'000 + assign $1\dec31_dec_sub9_form[4:0] 5'00000 end sync always - update \fast_o $0\fast_o[2:0] + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:179324.3-179354.6" - process $proc$libresoc.v:179324$13049 + attribute \src "libresoc.v:38930.3-38984.6" + process $proc$libresoc.v:38930$850 assign { } { } assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:179325.5-179325.29" + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:38931.5-38931.29" switch \initial - attribute \src "libresoc.v:179325.9-179325.17" + attribute \src "libresoc.v:38931.9-38931.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 + case 5'01100 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 + case 5'11100 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 + case 5'01101 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 + case 5'11101 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 + case 5'01110 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 + case 5'11110 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 + case 5'01111 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 + case 5'11111 assign { } { } - assign $1\fast_o_ok[0:0] 1'1 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 case - assign $1\fast_o_ok[0:0] 1'0 + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 end sync always - update \fast_o_ok $0\fast_o_ok[0:0] + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:179355.3-179667.6" - process $proc$libresoc.v:179355$13050 + attribute \src "libresoc.v:38985.3-39039.6" + process $proc$libresoc.v:38985$851 assign { } { } assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:179356.5-179356.29" + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:38986.5-38986.29" switch \initial - attribute \src "libresoc.v:179356.9-179356.17" + attribute \src "libresoc.v:38986.9-38986.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 + case 5'01100 assign { } { } - assign $1\spr_o[9:0] 10'0000000111 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 + case 5'11100 assign { } { } - assign $1\spr_o[9:0] 10'0000001011 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 + case 5'01101 assign { } { } - assign $1\spr_o[9:0] 10'0000001100 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 + case 5'11101 assign { } { } - assign $1\spr_o[9:0] 10'0000001101 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 + case 5'01110 assign { } { } - assign $1\spr_o[9:0] 10'0000001110 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 + case 5'11110 assign { } { } - assign $1\spr_o[9:0] 10'0000001111 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 + case 5'01111 assign { } { } - assign $1\spr_o[9:0] 10'0000010000 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 + case 5'11111 assign { } { } - assign $1\spr_o[9:0] 10'0000010001 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 + case 5'01000 assign { } { } - assign $1\spr_o[9:0] 10'0000010010 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 + case 5'11000 assign { } { } - assign $1\spr_o[9:0] 10'0000010011 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 + case 5'00010 assign { } { } - assign $1\spr_o[9:0] 10'0000010100 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 + case 5'00000 assign { } { } - assign $1\spr_o[9:0] 10'0000010101 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 + case 5'10010 assign { } { } - assign $1\spr_o[9:0] 10'0000010110 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 + case 5'10000 assign { } { } - assign $1\spr_o[9:0] 10'0000010111 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 + case 5'00111 assign { } { } - assign $1\spr_o[9:0] 10'0000011000 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 + case 5'10111 assign { } { } - assign $1\spr_o[9:0] 10'0000011001 + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:39040.3-39094.6" + process $proc$libresoc.v:39040$852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:39041.5-39041.29" + switch \initial + attribute \src "libresoc.v:39041.9-39041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 + case 5'01100 assign { } { } - assign $1\spr_o[9:0] 10'0000011010 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 + case 5'11100 assign { } { } - assign $1\spr_o[9:0] 10'0000011011 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 + case 5'01101 assign { } { } - assign $1\spr_o[9:0] 10'0000011100 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 + case 5'11101 assign { } { } - assign $1\spr_o[9:0] 10'0000011101 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 + case 5'01110 assign { } { } - assign $1\spr_o[9:0] 10'0000011110 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 + case 5'11110 assign { } { } - assign $1\spr_o[9:0] 10'0000011111 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 + case 5'01111 assign { } { } - assign $1\spr_o[9:0] 10'0000100000 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 + case 5'11111 assign { } { } - assign $1\spr_o[9:0] 10'0000100001 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 + case 5'01000 assign { } { } - assign $1\spr_o[9:0] 10'0000100011 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 + case 5'11000 assign { } { } - assign $1\spr_o[9:0] 10'0000100100 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 + case 5'00010 assign { } { } - assign $1\spr_o[9:0] 10'0000100101 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 5'00000 assign { } { } - assign $1\spr_o[9:0] 10'0000100110 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 + case 5'10010 assign { } { } - assign $1\spr_o[9:0] 10'0000100111 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 + case 5'10000 assign { } { } - assign $1\spr_o[9:0] 10'0000101000 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 + case 5'00111 assign { } { } - assign $1\spr_o[9:0] 10'0000101001 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 + case 5'10111 assign { } { } - assign $1\spr_o[9:0] 10'0000101010 + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + end + attribute \src "libresoc.v:39095.3-39149.6" + process $proc$libresoc.v:39095$853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:39096.5-39096.29" + switch \initial + attribute \src "libresoc.v:39096.9-39096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 + case 5'01100 assign { } { } - assign $1\spr_o[9:0] 10'0000101011 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 + case 5'11100 assign { } { } - assign $1\spr_o[9:0] 10'0000101100 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 + case 5'01101 assign { } { } - assign $1\spr_o[9:0] 10'0000101101 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 + case 5'11101 assign { } { } - assign $1\spr_o[9:0] 10'0000101110 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 + case 5'01110 assign { } { } - assign $1\spr_o[9:0] 10'0000101111 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 + case 5'11110 assign { } { } - assign $1\spr_o[9:0] 10'0000110000 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 + case 5'01111 assign { } { } - assign $1\spr_o[9:0] 10'0000110001 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 + case 5'11111 assign { } { } - assign $1\spr_o[9:0] 10'0000110010 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 + case 5'01000 assign { } { } - assign $1\spr_o[9:0] 10'0000110011 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 + case 5'11000 assign { } { } - assign $1\spr_o[9:0] 10'0000110100 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 + case 5'00010 assign { } { } - assign $1\spr_o[9:0] 10'0000110101 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 + case 5'00000 assign { } { } - assign $1\spr_o[9:0] 10'0000110110 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 + case 5'10010 assign { } { } - assign $1\spr_o[9:0] 10'0000110111 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 + case 5'10000 assign { } { } - assign $1\spr_o[9:0] 10'0000111000 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 + case 5'00111 assign { } { } - assign $1\spr_o[9:0] 10'0000111001 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 + case 5'10111 assign { } { } - assign $1\spr_o[9:0] 10'0000111010 + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + end + attribute \src "libresoc.v:39150.3-39204.6" + process $proc$libresoc.v:39150$854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:39151.5-39151.29" + switch \initial + attribute \src "libresoc.v:39151.9-39151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 + case 5'01100 assign { } { } - assign $1\spr_o[9:0] 10'0000111011 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 + case 5'11100 assign { } { } - assign $1\spr_o[9:0] 10'0000111100 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 + case 5'01101 assign { } { } - assign $1\spr_o[9:0] 10'0000111101 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 + case 5'11101 assign { } { } - assign $1\spr_o[9:0] 10'0000111110 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 + case 5'01110 assign { } { } - assign $1\spr_o[9:0] 10'0000111111 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 + case 5'11110 assign { } { } - assign $1\spr_o[9:0] 10'0001000000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 + case 5'01111 assign { } { } - assign $1\spr_o[9:0] 10'0001000001 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 + case 5'11111 assign { } { } - assign $1\spr_o[9:0] 10'0001000010 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 + case 5'01000 assign { } { } - assign $1\spr_o[9:0] 10'0001000011 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 + case 5'11000 assign { } { } - assign $1\spr_o[9:0] 10'0001000100 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 + case 5'00010 assign { } { } - assign $1\spr_o[9:0] 10'0001000101 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 + case 5'00000 assign { } { } - assign $1\spr_o[9:0] 10'0001000110 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 + case 5'10010 assign { } { } - assign $1\spr_o[9:0] 10'0001000111 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 + case 5'10000 assign { } { } - assign $1\spr_o[9:0] 10'0001001000 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 + case 5'00111 assign { } { } - assign $1\spr_o[9:0] 10'0001001001 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 + case 5'10111 assign { } { } - assign $1\spr_o[9:0] 10'0001001010 + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:39205.3-39259.6" + process $proc$libresoc.v:39205$855 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:39206.5-39206.29" + switch \initial + attribute \src "libresoc.v:39206.9-39206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 + case 5'01100 assign { } { } - assign $1\spr_o[9:0] 10'0001001011 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 + case 5'11100 assign { } { } - assign $1\spr_o[9:0] 10'0001001100 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 + case 5'01101 assign { } { } - assign $1\spr_o[9:0] 10'0001001101 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 + case 5'11101 assign { } { } - assign $1\spr_o[9:0] 10'0001001110 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 + case 5'01110 assign { } { } - assign $1\spr_o[9:0] 10'0001001111 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 + case 5'11110 assign { } { } - assign $1\spr_o[9:0] 10'0001010000 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 + case 5'01111 assign { } { } - assign $1\spr_o[9:0] 10'0001010001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 + case 5'11111 assign { } { } - assign $1\spr_o[9:0] 10'0001010010 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 + case 5'01000 assign { } { } - assign $1\spr_o[9:0] 10'0001010011 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 + case 5'11000 assign { } { } - assign $1\spr_o[9:0] 10'0001010100 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 + case 5'00010 assign { } { } - assign $1\spr_o[9:0] 10'0001010101 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 + case 5'00000 assign { } { } - assign $1\spr_o[9:0] 10'0001010110 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 + case 5'10010 assign { } { } - assign $1\spr_o[9:0] 10'0001010111 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 + case 5'10000 assign { } { } - assign $1\spr_o[9:0] 10'0001011000 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 + case 5'00111 assign { } { } - assign $1\spr_o[9:0] 10'0001011001 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 + case 5'10111 assign { } { } - assign $1\spr_o[9:0] 10'0001011010 + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:39265.1-39908.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "libresoc.v:39603.3-39618.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:39667.3-39682.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:39875.3-39890.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:39891.3-39906.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:39587.3-39602.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:39651.3-39666.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:39795.3-39810.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:39523.3-39538.6" + wire width 12 $0\dec58_function_unit[11:0] + attribute \src "libresoc.v:39811.3-39826.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39827.3-39842.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39843.3-39858.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39699.3-39714.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:39619.3-39634.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:39635.3-39650.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:39731.3-39746.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:39539.3-39554.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39763.3-39778.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:39859.3-39874.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "libresoc.v:39571.3-39586.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39715.3-39730.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:39779.3-39794.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39747.3-39762.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:39683.3-39698.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39555.3-39570.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:39266.7-39266.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:39603.3-39618.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:39667.3-39682.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:39875.3-39890.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:39891.3-39906.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:39587.3-39602.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:39651.3-39666.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:39795.3-39810.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:39523.3-39538.6" + wire width 12 $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:39811.3-39826.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39827.3-39842.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39843.3-39858.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39699.3-39714.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:39619.3-39634.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:39635.3-39650.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:39731.3-39746.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:39539.3-39554.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39763.3-39778.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:39859.3-39874.6" + wire width 2 $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:39571.3-39586.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39715.3-39730.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:39779.3-39794.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39747.3-39762.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39683.3-39698.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39555.3-39570.6" + wire width 2 $1\dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec58_upd + attribute \src "libresoc.v:39266.7-39266.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39266.7-39266.20" + process $proc$libresoc.v:39266$881 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:39523.3-39538.6" + process $proc$libresoc.v:39523$857 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] + attribute \src "libresoc.v:39524.5-39524.29" + switch \initial + attribute \src "libresoc.v:39524.9-39524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 + case 2'00 assign { } { } - assign $1\spr_o[9:0] 10'0001011011 + assign $1\dec58_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 + case 2'01 assign { } { } - assign $1\spr_o[9:0] 10'0001011100 + assign $1\dec58_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 + case 2'10 assign { } { } - assign $1\spr_o[9:0] 10'0001011101 + assign $1\dec58_function_unit[11:0] 12'000000000100 + case + assign $1\dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[11:0] + end + attribute \src "libresoc.v:39539.3-39554.6" + process $proc$libresoc.v:39539$858 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:39540.5-39540.29" + switch \initial + attribute \src "libresoc.v:39540.9-39540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 + case 2'00 assign { } { } - assign $1\spr_o[9:0] 10'0001011110 + assign $1\dec58_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 + case 2'01 assign { } { } - assign $1\spr_o[9:0] 10'0001011111 + assign $1\dec58_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 + case 2'10 assign { } { } - assign $1\spr_o[9:0] 10'0001100000 + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:39555.3-39570.6" + process $proc$libresoc.v:39555$859 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:39556.5-39556.29" + switch \initial + attribute \src "libresoc.v:39556.9-39556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 + case 2'00 assign { } { } - assign $1\spr_o[9:0] 10'0001100001 + assign $1\dec58_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 + case 2'01 assign { } { } - assign $1\spr_o[9:0] 10'0001100010 + assign $1\dec58_upd[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 + case 2'10 assign { } { } - assign $1\spr_o[9:0] 10'0001100011 + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "libresoc.v:39571.3-39586.6" + process $proc$libresoc.v:39571$860 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:39572.5-39572.29" + switch \initial + attribute \src "libresoc.v:39572.9-39572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 + case 2'00 assign { } { } - assign $1\spr_o[9:0] 10'0001100100 + assign $1\dec58_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 + case 2'01 assign { } { } - assign $1\spr_o[9:0] 10'0001100110 + assign $1\dec58_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 + case 2'10 assign { } { } - assign $1\spr_o[9:0] 10'0001100111 + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:39587.3-39602.6" + process $proc$libresoc.v:39587$861 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:39588.5-39588.29" + switch \initial + attribute \src "libresoc.v:39588.9-39588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 + case 2'00 assign { } { } - assign $1\spr_o[9:0] 10'0001101000 + assign $1\dec58_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 + case 2'01 assign { } { } - assign $1\spr_o[9:0] 10'0001101001 + assign $1\dec58_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 + case 2'10 assign { } { } - assign $1\spr_o[9:0] 10'0001101010 + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "libresoc.v:39603.3-39618.6" + process $proc$libresoc.v:39603$862 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:39604.5-39604.29" + switch \initial + attribute \src "libresoc.v:39604.9-39604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 + case 2'00 assign { } { } - assign $1\spr_o[9:0] 10'0001101011 + assign $1\dec58_asmcode[7:0] 8'01010010 attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 + case 2'01 assign { } { } - assign $1\spr_o[9:0] 10'0001101100 + assign $1\dec58_asmcode[7:0] 8'01010101 attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 + case 2'10 assign { } { } - assign $1\spr_o[9:0] 10'0001101101 + assign $1\dec58_asmcode[7:0] 8'01100010 case - assign $1\spr_o[9:0] 10'0000000000 + assign $1\dec58_asmcode[7:0] 8'00000000 end sync always - update \spr_o $0\spr_o[9:0] + update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:179668.3-179980.6" - process $proc$libresoc.v:179668$13051 + attribute \src "libresoc.v:39619.3-39634.6" + process $proc$libresoc.v:39619$863 assign { } { } assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:179669.5-179669.29" + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:39620.5-39620.29" switch \initial - attribute \src "libresoc.v:179669.9-179669.17" + attribute \src "libresoc.v:39620.9-39620.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "libresoc.v:39635.3-39650.6" + process $proc$libresoc.v:39635$864 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:39636.5-39636.29" + switch \initial + attribute \src "libresoc.v:39636.9-39636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "libresoc.v:39651.3-39666.6" + process $proc$libresoc.v:39651$865 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:39652.5-39652.29" + switch \initial + attribute \src "libresoc.v:39652.9-39652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "libresoc.v:39667.3-39682.6" + process $proc$libresoc.v:39667$866 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:39668.5-39668.29" + switch \initial + attribute \src "libresoc.v:39668.9-39668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:39683.3-39698.6" + process $proc$libresoc.v:39683$867 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:39684.5-39684.29" + switch \initial + attribute \src "libresoc.v:39684.9-39684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:39699.3-39714.6" + process $proc$libresoc.v:39699$868 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:39700.5-39700.29" + switch \initial + attribute \src "libresoc.v:39700.9-39700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_internal_op[6:0] 7'0100101 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "libresoc.v:39715.3-39730.6" + process $proc$libresoc.v:39715$869 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:39716.5-39716.29" + switch \initial + attribute \src "libresoc.v:39716.9-39716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "libresoc.v:39731.3-39746.6" + process $proc$libresoc.v:39731$870 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:39732.5-39732.29" + switch \initial + attribute \src "libresoc.v:39732.9-39732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "libresoc.v:39747.3-39762.6" + process $proc$libresoc.v:39747$871 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:39748.5-39748.29" + switch \initial + attribute \src "libresoc.v:39748.9-39748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "libresoc.v:39763.3-39778.6" + process $proc$libresoc.v:39763$872 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:39764.5-39764.29" + switch \initial + attribute \src "libresoc.v:39764.9-39764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:39779.3-39794.6" + process $proc$libresoc.v:39779$873 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:39780.5-39780.29" + switch \initial + attribute \src "libresoc.v:39780.9-39780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "libresoc.v:39795.3-39810.6" + process $proc$libresoc.v:39795$874 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:39796.5-39796.29" + switch \initial + attribute \src "libresoc.v:39796.9-39796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "libresoc.v:39811.3-39826.6" + process $proc$libresoc.v:39811$875 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:39812.5-39812.29" + switch \initial + attribute \src "libresoc.v:39812.9-39812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:39827.3-39842.6" + process $proc$libresoc.v:39827$876 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:39828.5-39828.29" + switch \initial + attribute \src "libresoc.v:39828.9-39828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:39843.3-39858.6" + process $proc$libresoc.v:39843$877 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:39844.5-39844.29" + switch \initial + attribute \src "libresoc.v:39844.9-39844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in3_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:39859.3-39874.6" + process $proc$libresoc.v:39859$878 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:39860.5-39860.29" + switch \initial + attribute \src "libresoc.v:39860.9-39860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_out_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] + end + attribute \src "libresoc.v:39875.3-39890.6" + process $proc$libresoc.v:39875$879 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:39876.5-39876.29" + switch \initial + attribute \src "libresoc.v:39876.9-39876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "libresoc.v:39891.3-39906.6" + process $proc$libresoc.v:39891$880 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:39892.5-39892.29" + switch \initial + attribute \src "libresoc.v:39892.9-39892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 + case 2'10 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:39912.1-40483.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:40235.3-40247.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:40287.3-40299.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:40456.3-40468.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:40469.3-40481.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:40222.3-40234.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:40274.3-40286.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:40391.3-40403.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:40170.3-40182.6" + wire width 12 $0\dec62_function_unit[11:0] + attribute \src "libresoc.v:40404.3-40416.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40417.3-40429.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40430.3-40442.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40313.3-40325.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:40248.3-40260.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:40261.3-40273.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:40339.3-40351.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:40183.3-40195.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40365.3-40377.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:40443.3-40455.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "libresoc.v:40209.3-40221.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40326.3-40338.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:40378.3-40390.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40352.3-40364.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:40300.3-40312.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40196.3-40208.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:39913.7-39913.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:40235.3-40247.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40287.3-40299.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:40456.3-40468.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40469.3-40481.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:40222.3-40234.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40274.3-40286.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40391.3-40403.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:40170.3-40182.6" + wire width 12 $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40404.3-40416.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40417.3-40429.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40430.3-40442.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40313.3-40325.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40248.3-40260.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40261.3-40273.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40339.3-40351.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40183.3-40195.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40365.3-40377.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:40443.3-40455.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40209.3-40221.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40326.3-40338.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40378.3-40390.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40352.3-40364.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40300.3-40312.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40196.3-40208.6" + wire width 2 $1\dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 18 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 9 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 10 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 14 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 17 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 12 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 3 output 5 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 6 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 7 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 15 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 16 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 21 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 4 output 11 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 23 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 8 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 13 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 20 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 24 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 22 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:179" + wire output 19 \dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 output 12 \dec62_upd + attribute \src "libresoc.v:39913.7-39913.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:285" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322" + wire width 2 \opcode_switch + attribute \src "libresoc.v:39913.7-39913.20" + process $proc$libresoc.v:39913$906 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:40170.3-40182.6" + process $proc$libresoc.v:40170$882 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] + attribute \src "libresoc.v:40171.5-40171.29" + switch \initial + attribute \src "libresoc.v:40171.9-40171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_function_unit[11:0] 12'000000000100 attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_function_unit[11:0] 12'000000000100 + case + assign $1\dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[11:0] + end + attribute \src "libresoc.v:40183.3-40195.6" + process $proc$libresoc.v:40183$883 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:40184.5-40184.29" + switch \initial + attribute \src "libresoc.v:40184.9-40184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_ldst_len[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:40196.3-40208.6" + process $proc$libresoc.v:40196$884 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:40197.5-40197.29" + switch \initial + attribute \src "libresoc.v:40197.9-40197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_upd[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "libresoc.v:40209.3-40221.6" + process $proc$libresoc.v:40209$885 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:40210.5-40210.29" + switch \initial + attribute \src "libresoc.v:40210.9-40210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_rc_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "libresoc.v:40222.3-40234.6" + process $proc$libresoc.v:40222$886 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:40223.5-40223.29" + switch \initial + attribute \src "libresoc.v:40223.9-40223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cry_in[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "libresoc.v:40235.3-40247.6" + process $proc$libresoc.v:40235$887 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:40236.5-40236.29" + switch \initial + attribute \src "libresoc.v:40236.9-40236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_asmcode[7:0] 8'10101100 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_asmcode[7:0] 8'10101111 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "libresoc.v:40248.3-40260.6" + process $proc$libresoc.v:40248$888 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:40249.5-40249.29" + switch \initial + attribute \src "libresoc.v:40249.9-40249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_inv_a[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "libresoc.v:40261.3-40273.6" + process $proc$libresoc.v:40261$889 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:40262.5-40262.29" + switch \initial + attribute \src "libresoc.v:40262.9-40262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_inv_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:40274.3-40286.6" + process $proc$libresoc.v:40274$890 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:40275.5-40275.29" + switch \initial + attribute \src "libresoc.v:40275.9-40275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cry_out[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:40287.3-40299.6" + process $proc$libresoc.v:40287$891 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:40288.5-40288.29" + switch \initial + attribute \src "libresoc.v:40288.9-40288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_br[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:40300.3-40312.6" + process $proc$libresoc.v:40300$892 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:40301.5-40301.29" + switch \initial + attribute \src "libresoc.v:40301.9-40301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_sgn_ext[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:40313.3-40325.6" + process $proc$libresoc.v:40313$893 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:40314.5-40314.29" + switch \initial + attribute \src "libresoc.v:40314.9-40314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_internal_op[6:0] 7'0100110 attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "libresoc.v:40326.3-40338.6" + process $proc$libresoc.v:40326$894 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:40327.5-40327.29" + switch \initial + attribute \src "libresoc.v:40327.9-40327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_rsrv[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "libresoc.v:40339.3-40351.6" + process $proc$libresoc.v:40339$895 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:40340.5-40340.29" + switch \initial + attribute \src "libresoc.v:40340.9-40340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_is_32b[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:40352.3-40364.6" + process $proc$libresoc.v:40352$896 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:40353.5-40353.29" + switch \initial + attribute \src "libresoc.v:40353.9-40353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_sgn[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:40365.3-40377.6" + process $proc$libresoc.v:40365$897 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:40366.5-40366.29" + switch \initial + attribute \src "libresoc.v:40366.9-40366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_lk[0:0] 1'0 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:40378.3-40390.6" + process $proc$libresoc.v:40378$898 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:40379.5-40379.29" + switch \initial + attribute \src "libresoc.v:40379.9-40379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_sgl_pipe[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "libresoc.v:40391.3-40403.6" + process $proc$libresoc.v:40391$899 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:40392.5-40392.29" + switch \initial + attribute \src "libresoc.v:40392.9-40392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_form[4:0] 5'00101 attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:40404.3-40416.6" + process $proc$libresoc.v:40404$900 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:40405.5-40405.29" + switch \initial + attribute \src "libresoc.v:40405.9-40405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_in1_sel[2:0] 3'010 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:40417.3-40429.6" + process $proc$libresoc.v:40417$901 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:40418.5-40418.29" + switch \initial + attribute \src "libresoc.v:40418.9-40418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_in2_sel[3:0] 4'1000 attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:40430.3-40442.6" + process $proc$libresoc.v:40430$902 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:40431.5-40431.29" + switch \initial + attribute \src "libresoc.v:40431.9-40431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_in3_sel[1:0] 2'01 attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "libresoc.v:40443.3-40455.6" + process $proc$libresoc.v:40443$903 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:40444.5-40444.29" + switch \initial + attribute \src "libresoc.v:40444.9-40444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_out_sel[1:0] 2'00 attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] + end + attribute \src "libresoc.v:40456.3-40468.6" + process $proc$libresoc.v:40456$904 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:40457.5-40457.29" + switch \initial + attribute \src "libresoc.v:40457.9-40457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cr_in[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "libresoc.v:40469.3-40481.6" + process $proc$libresoc.v:40469$905 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:40470.5-40470.29" + switch \initial + attribute \src "libresoc.v:40470.9-40470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:423" + switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 + case 2'00 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cr_out[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 + case 2'01 assign { } { } - assign $1\spr_o_ok[0:0] 1'1 + assign $1\dec62_cr_out[2:0] 3'000 case - assign $1\spr_o_ok[0:0] 1'0 + assign $1\dec62_cr_out[2:0] 3'000 end sync always - update \spr_o_ok $0\spr_o_ok[0:0] + update \dec62_cr_out $0\dec62_cr_out[2:0] end + connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:179985.1-180800.10" +attribute \src "libresoc.v:40487.1-40992.10" attribute \cells_not_processed 1 -attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \fast_a_ok + attribute \src "libresoc.v:40488.7-40488.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 13 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + wire width 5 \ra attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 output 3 \fast_o + wire width 5 output 2 \reg_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 4 \fast_o_ok - attribute \src "libresoc.v:179986.7-179986.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" - wire width 10 input 5 \spr_i + wire output 3 \reg_a_ok + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:133" + wire width 10 \spr attribute \enum_base_type "SPR" attribute \enum_value_0000000001 "XER" attribute \enum_value_0000000011 "DSCR" @@ -378008,14503 +60664,78955 @@ module \sprmap$212 attribute \enum_value_1110000010 "PPR32" attribute \enum_value_1111111111 "PIR" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 output 1 \spr_o + wire width 10 output 4 \spr_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 2 \spr_o_ok - attribute \src "libresoc.v:179986.7-179986.20" - process $proc$libresoc.v:179986$13057 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:180112.3-180142.6" - process $proc$libresoc.v:180112$13053 - assign { } { } - assign { } { } - assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:180113.5-180113.29" - switch \initial - attribute \src "libresoc.v:180113.9-180113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o[2:0] 3'000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o[2:0] 3'100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o[2:0] 3'111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o[2:0] 3'010 - case - assign $1\fast_o[2:0] 3'000 - end - sync always - update \fast_o $0\fast_o[2:0] - end - attribute \src "libresoc.v:180143.3-180173.6" - process $proc$libresoc.v:180143$13054 - assign { } { } - assign { } { } - assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:180144.5-180144.29" - switch \initial - attribute \src "libresoc.v:180144.9-180144.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101111 - assign { } { } - assign $1\fast_o_ok[0:0] 1'1 - case - assign $1\fast_o_ok[0:0] 1'0 - end - sync always - update \fast_o_ok $0\fast_o_ok[0:0] - end - attribute \src "libresoc.v:180174.3-180486.6" - process $proc$libresoc.v:180174$13055 - assign { } { } - assign { } { } - assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:180175.5-180175.29" - switch \initial - attribute \src "libresoc.v:180175.9-180175.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o[9:0] 10'0000001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o[9:0] 10'0000010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o[9:0] 10'0000010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o[9:0] 10'0000010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o[9:0] 10'0000011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0000100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000100101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0000101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0000101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0000101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o[9:0] 10'0000101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0000101101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o[9:0] 10'0000101110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o[9:0] 10'0000101111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o[9:0] 10'0000110001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o[9:0] 10'0000110010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o[9:0] 10'0000110100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o[9:0] 10'0000110101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o[9:0] 10'0000110110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000110111 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o[9:0] 10'0000111000 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111001 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0000111010 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o[9:0] 10'0000111011 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o[9:0] 10'0000111100 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o[9:0] 10'0000111101 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o[9:0] 10'0000111110 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o[9:0] 10'0000111111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001000000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o[9:0] 10'0001000001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001000010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o[9:0] 10'0001000011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o[9:0] 10'0001000100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o[9:0] 10'0001000101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o[9:0] 10'0001000110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o[9:0] 10'0001000111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o[9:0] 10'0001001001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o[9:0] 10'0001001010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o[9:0] 10'0001001011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o[9:0] 10'0001001100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001001101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001001110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o[9:0] 10'0001001111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o[9:0] 10'0001010010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o[9:0] 10'0001010011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001010100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o[9:0] 10'0001010101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o[9:0] 10'0001010110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o[9:0] 10'0001010111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o[9:0] 10'0001011001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o[9:0] 10'0001011010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o[9:0] 10'0001011011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o[9:0] 10'0001011100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o[9:0] 10'0001011101 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o[9:0] 10'0001011110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o[9:0] 10'0001011111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o[9:0] 10'0001100000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o[9:0] 10'0001100010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o[9:0] 10'0001100011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o[9:0] 10'0001100100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o[9:0] 10'0001100110 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o[9:0] 10'0001100111 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101000 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o[9:0] 10'0001101001 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101010 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o[9:0] 10'0001101011 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o[9:0] 10'0001101100 - attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o[9:0] 10'0001101101 - case - assign $1\spr_o[9:0] 10'0000000000 - end - sync always - update \spr_o $0\spr_o[9:0] - end - attribute \src "libresoc.v:180487.3-180799.6" - process $proc$libresoc.v:180487$13056 - assign { } { } - assign { } { } - assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:180488.5-180488.29" - switch \initial - attribute \src "libresoc.v:180488.9-180488.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" - switch \spr_i - attribute \src "libresoc.v:0.0-0.0" - case 10'0000000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0000111101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0010111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100011111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100110110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0100111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0101011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0110111110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'0111010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100000111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100001110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100011110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100100 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100101 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100100110 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100101011 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1100110111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010001 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1101010111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000000 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1110000010 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - attribute \src "libresoc.v:0.0-0.0" - case 10'1111111111 - assign { } { } - assign $1\spr_o_ok[0:0] 1'1 - case - assign $1\spr_o_ok[0:0] 1'0 - end - sync always - update \spr_o_ok $0\spr_o_ok[0:0] + wire output 5 \spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $and $and$libresoc.v:40873$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $and$libresoc.v:40873$913_Y end -end -attribute \src "libresoc.v:180804.1-180862.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" -attribute \generator "nMigen" -module \src_l - attribute \src "libresoc.v:180805.7-180805.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:180850.3-180858.6" - wire width 4 $0\q_int$next[3:0]$13068 - attribute \src "libresoc.v:180848.3-180849.27" - wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:180850.3-180858.6" - wire width 4 $1\q_int$next[3:0]$13069 - attribute \src "libresoc.v:180827.13-180827.25" - wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:180840.17-180840.96" - wire width 4 $and$libresoc.v:180840$13058_Y - attribute \src "libresoc.v:180845.17-180845.96" - wire width 4 $and$libresoc.v:180845$13063_Y - attribute \src "libresoc.v:180842.18-180842.93" - wire width 4 $not$libresoc.v:180842$13060_Y - attribute \src "libresoc.v:180844.17-180844.92" - wire width 4 $not$libresoc.v:180844$13062_Y - attribute \src "libresoc.v:180847.17-180847.92" - wire width 4 $not$libresoc.v:180847$13065_Y - attribute \src "libresoc.v:180841.18-180841.98" - wire width 4 $or$libresoc.v:180841$13059_Y - attribute \src "libresoc.v:180843.18-180843.99" - wire width 4 $or$libresoc.v:180843$13061_Y - attribute \src "libresoc.v:180846.17-180846.97" - wire width 4 $or$libresoc.v:180846$13064_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:180805.7-180805.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:180840$13058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $and $and$libresoc.v:40878$918 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:180840$13058_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \B \$27 + connect \Y $and$libresoc.v:40878$918_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:180845$13063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $and $and$libresoc.v:40881$921 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:180845$13063_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:40881$921_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:180842$13060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + cell $eq $eq$libresoc.v:40868$908 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $not$libresoc.v:180842$13060_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:40868$908_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180844$13062 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + cell $eq $eq$libresoc.v:40869$909 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$libresoc.v:180844$13062_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:40869$909_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180847$13065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + cell $eq $eq$libresoc.v:40870$910 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$libresoc.v:180847$13065_Y + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:40870$910_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180841$13059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102" + cell $eq $eq$libresoc.v:40872$912 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:180841$13059_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$libresoc.v:40872$912_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:180843$13061 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + cell $eq $eq$libresoc.v:40875$915 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:180843$13061_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$libresoc.v:40875$915_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:180846$13064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103" + cell $eq $eq$libresoc.v:40879$919 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:180846$13064_Y + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$libresoc.v:40879$919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $ne $ne$libresoc.v:40871$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:40871$911_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $ne $ne$libresoc.v:40880$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$libresoc.v:40880$920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + cell $not $not$libresoc.v:40876$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:40876$916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + cell $not $not$libresoc.v:40877$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [5] + connect \Y $not$libresoc.v:40877$917_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $or $or$libresoc.v:40867$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$7 + connect \Y $or$libresoc.v:40867$907_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + cell $or $or$libresoc.v:40874$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$19 + connect \Y $or$libresoc.v:40874$914_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:40882.10-40888.4" + cell \sprmap \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:180805.7-180805.20" - process $proc$libresoc.v:180805$13070 + attribute \src "libresoc.v:40488.7-40488.20" + process $proc$libresoc.v:40488$928 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180827.13-180827.25" - process $proc$libresoc.v:180827$13071 + attribute \src "libresoc.v:40889.3-40904.6" + process $proc$libresoc.v:40889$922 + assign { } { } assign { } { } - assign $1\q_int[3:0] 4'0000 + assign { } { } + assign $0\reg_a[4:0] $2\reg_a[4:0] + attribute \src "libresoc.v:40890.5-40890.29" + switch \initial + attribute \src "libresoc.v:40890.9-40890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a[4:0] \ra + case + assign $1\reg_a[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a[4:0] \RS + case + assign $2\reg_a[4:0] $1\reg_a[4:0] + end sync always - sync init - update \q_int $1\q_int[3:0] + update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:180848.3-180849.27" - process $proc$libresoc.v:180848$13066 + attribute \src "libresoc.v:40905.3-40920.6" + process $proc$libresoc.v:40905$923 assign { } { } - assign $0\q_int[3:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[3:0] - end - attribute \src "libresoc.v:180850.3-180858.6" - process $proc$libresoc.v:180850$13067 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13068 $1\q_int$next[3:0]$13069 - attribute \src "libresoc.v:180851.5-180851.29" + assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] + attribute \src "libresoc.v:40906.5-40906.29" switch \initial - attribute \src "libresoc.v:180851.9-180851.17" + attribute \src "libresoc.v:40906.9-40906.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a_ok[0:0] 1'1 + case + assign $1\reg_a_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109" + switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13069 4'0000 + assign $2\reg_a_ok[0:0] 1'1 case - assign $1\q_int$next[3:0]$13069 \$5 + assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] end sync always - update \q_int$next $0\q_int$next[3:0]$13068 - end - connect \$9 $and$libresoc.v:180840$13058_Y - connect \$11 $or$libresoc.v:180841$13059_Y - connect \$13 $not$libresoc.v:180842$13060_Y - connect \$15 $or$libresoc.v:180843$13061_Y - connect \$1 $not$libresoc.v:180844$13062_Y - connect \$3 $and$libresoc.v:180845$13063_Y - connect \$5 $or$libresoc.v:180846$13064_Y - connect \$7 $not$libresoc.v:180847$13065_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "libresoc.v:180866.1-180924.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" -attribute \generator "nMigen" -module \src_l$10 - attribute \src "libresoc.v:180867.7-180867.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:180912.3-180920.6" - wire width 6 $0\q_int$next[5:0]$13082 - attribute \src "libresoc.v:180910.3-180911.27" - wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:180912.3-180920.6" - wire width 6 $1\q_int$next[5:0]$13083 - attribute \src "libresoc.v:180889.13-180889.26" - wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:180902.17-180902.96" - wire width 6 $and$libresoc.v:180902$13072_Y - attribute \src "libresoc.v:180907.17-180907.96" - wire width 6 $and$libresoc.v:180907$13077_Y - attribute \src "libresoc.v:180904.18-180904.93" - wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:180867.7-180867.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src 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$not $not$libresoc.v:180904$13074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $not$libresoc.v:180904$13074_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180906$13076 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$libresoc.v:180906$13076_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180909$13079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$libresoc.v:180909$13079_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180903$13073 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:180903$13073_Y - end - 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$1\fast_a_ok[0:0] + attribute \src "libresoc.v:40922.5-40922.29" + switch \initial + attribute \src "libresoc.v:40922.9-40922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $2\fast_a[2:0] + assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:119" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'1 + case + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $3\fast_a[2:0] + assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'1 + case + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $1\fast_a[2:0] 3'000 + assign $1\fast_a_ok[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \fast_a $0\fast_a[2:0] + update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:180889.13-180889.26" - process $proc$libresoc.v:180889$13085 + attribute \src "libresoc.v:40957.3-40967.6" + process $proc$libresoc.v:40957$925 assign { } { } - assign $1\q_int[5:0] 6'000000 + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:40958.5-40958.29" + switch \initial + attribute \src "libresoc.v:40958.9-40958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end sync always - sync init - update \q_int $1\q_int[5:0] + update \spr $0\spr[9:0] end - attribute \src "libresoc.v:180910.3-180911.27" - process $proc$libresoc.v:180910$13080 + attribute \src "libresoc.v:40968.3-40978.6" + process $proc$libresoc.v:40968$926 assign { } { } - assign $0\q_int[5:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[5:0] + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:40969.5-40969.29" + switch \initial + attribute \src "libresoc.v:40969.9-40969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\sprmap_spr_i[9:0] \spr + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:180912.3-180920.6" - process $proc$libresoc.v:180912$13081 + attribute \src "libresoc.v:40979.3-40990.6" + process $proc$libresoc.v:40979$927 + assign { } { } assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13082 $1\q_int$next[5:0]$13083 - attribute \src "libresoc.v:180913.5-180913.29" + assign { } { } + assign $0\spr_a[9:0] $1\spr_a[9:0] + assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] + attribute \src "libresoc.v:40980.5-40980.29" switch \initial - attribute \src "libresoc.v:180913.9-180913.17" + attribute \src "libresoc.v:40980.9-40980.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" + switch \internal_op attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 7'0101110 + assign { } { } assign { } { } - assign $1\q_int$next[5:0]$13083 6'000000 + assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } case - assign $1\q_int$next[5:0]$13083 \$5 + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[5:0]$13082 + update \spr_a $0\spr_a[9:0] + update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $and$libresoc.v:180902$13072_Y - connect \$11 $or$libresoc.v:180903$13073_Y - connect \$13 $not$libresoc.v:180904$13074_Y - connect \$15 $or$libresoc.v:180905$13075_Y - connect \$1 $not$libresoc.v:180906$13076_Y - connect \$3 $and$libresoc.v:180907$13077_Y - connect \$5 $or$libresoc.v:180908$13078_Y - connect \$7 $not$libresoc.v:180909$13079_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect 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$and$libresoc.v:180969$13091_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:180966$13088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$libresoc.v:180966$13088_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:180968$13090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:180968$13090_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:180971$13093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:180971$13093_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:41117$929_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:180965$13087 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + cell $eq $eq$libresoc.v:41119$931 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:180965$13087_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0001000 + connect \Y $eq$libresoc.v:41119$931_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:180967$13089 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:41118$930 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:180967$13089_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:41118$930_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:180970$13092 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + cell $not $not$libresoc.v:41120$932 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:180970$13092_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:41120$932_Y end - attribute \src "libresoc.v:180929.7-180929.20" - process $proc$libresoc.v:180929$13098 + attribute \src "libresoc.v:40997.7-40997.20" + process $proc$libresoc.v:40997$937 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180951.13-180951.25" - process $proc$libresoc.v:180951$13099 + attribute \src "libresoc.v:41121.3-41135.6" + process $proc$libresoc.v:41121$933 assign { } { } - assign $1\q_int[2:0] 3'000 + assign { } { } + assign $0\reg_b[4:0] $1\reg_b[4:0] + attribute \src "libresoc.v:41122.5-41122.29" + switch \initial + attribute \src "libresoc.v:41122.9-41122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b[4:0] \RS + case + assign $1\reg_b[4:0] 5'00000 + end sync always - sync init - update \q_int $1\q_int[2:0] + update \reg_b $0\reg_b[4:0] end - attribute \src "libresoc.v:180972.3-180973.27" - process $proc$libresoc.v:180972$13094 + attribute \src "libresoc.v:41136.3-41150.6" + process $proc$libresoc.v:41136$934 assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] + assign { } { } + assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] + attribute \src "libresoc.v:41137.5-41137.29" + switch \initial + attribute \src "libresoc.v:41137.9-41137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + case + assign $1\reg_b_ok[0:0] 1'0 + end + sync always + update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:180974.3-180982.6" - process $proc$libresoc.v:180974$13095 + attribute \src "libresoc.v:41151.3-41168.6" + process $proc$libresoc.v:41151$935 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13096 $1\q_int$next[2:0]$13097 - attribute \src "libresoc.v:180975.5-180975.29" + assign $0\fast_b[2:0] $1\fast_b[2:0] + attribute \src "libresoc.v:41152.5-41152.29" switch \initial - attribute \src "libresoc.v:180975.9-180975.17" + attribute \src "libresoc.v:41152.9-41152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + switch { \XL_XO [5] \$3 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b[2:0] 3'010 + case + assign $2\fast_b[2:0] 3'000 + end + case + assign $1\fast_b[2:0] 3'000 + end + sync always + update \fast_b $0\fast_b[2:0] + end + attribute \src "libresoc.v:41169.3-41186.6" + process $proc$libresoc.v:41169$936 + assign { } { } + assign { } { } + assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] + attribute \src "libresoc.v:41170.5-41170.29" + switch \initial + attribute \src "libresoc.v:41170.9-41170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" + switch \$5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13097 3'000 + assign $1\fast_b_ok[0:0] $2\fast_b_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" + switch { \XL_XO [5] \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + case + assign $2\fast_b_ok[0:0] 1'0 + end case - assign $1\q_int$next[2:0]$13097 \$5 + assign $1\fast_b_ok[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[2:0]$13096 + update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $and$libresoc.v:180964$13086_Y - connect \$11 $or$libresoc.v:180965$13087_Y - connect \$13 $not$libresoc.v:180966$13088_Y - connect \$15 $or$libresoc.v:180967$13089_Y - connect \$1 $not$libresoc.v:180968$13090_Y - connect \$3 $and$libresoc.v:180969$13091_Y - connect \$5 $or$libresoc.v:180970$13092_Y - connect \$7 $not$libresoc.v:180971$13093_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 + connect \$1 $eq$libresoc.v:41117$929_Y + connect \$3 $not$libresoc.v:41118$930_Y + connect \$5 $eq$libresoc.v:41119$931_Y + connect \$7 $not$libresoc.v:41120$932_Y end -attribute \src "libresoc.v:180990.1-181048.10" +attribute \src "libresoc.v:41191.1-41239.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" -module \src_l$119 - attribute \src "libresoc.v:180991.7-180991.20" +module \dec_c + attribute \src "libresoc.v:41192.7-41192.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181036.3-181044.6" - wire width 5 $0\q_int$next[4:0]$13110 - attribute \src "libresoc.v:181034.3-181035.27" - wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:181036.3-181044.6" - wire width 5 $1\q_int$next[4:0]$13111 - attribute \src "libresoc.v:181013.13-181013.26" - wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:181026.17-181026.96" - wire width 5 $and$libresoc.v:181026$13100_Y - attribute \src "libresoc.v:181031.17-181031.96" - wire width 5 $and$libresoc.v:181031$13105_Y - attribute \src "libresoc.v:181028.18-181028.93" - wire width 5 $not$libresoc.v:181028$13102_Y - attribute \src "libresoc.v:181030.17-181030.92" - wire width 5 $not$libresoc.v:181030$13104_Y - attribute \src "libresoc.v:181033.17-181033.92" - wire width 5 $not$libresoc.v:181033$13107_Y - attribute \src "libresoc.v:181027.18-181027.98" - wire width 5 $or$libresoc.v:181027$13101_Y - attribute \src "libresoc.v:181029.18-181029.99" - wire width 5 $or$libresoc.v:181029$13103_Y - attribute \src "libresoc.v:181032.17-181032.97" - wire width 5 $or$libresoc.v:181032$13106_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:180991.7-180991.15" + attribute \src "libresoc.v:41209.3-41223.6" + wire width 5 $0\reg_c[4:0] + attribute \src "libresoc.v:41224.3-41238.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:41209.3-41223.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:41224.3-41238.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 3 \RS + attribute \src "libresoc.v:41192.7-41192.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181026$13100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181026$13100_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181031$13105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181031$13105_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181028$13102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_src - connect \Y $not$libresoc.v:181028$13102_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181030$13104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_src - connect \Y $not$libresoc.v:181030$13104_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181033$13107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_src - connect \Y $not$libresoc.v:181033$13107_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181027$13101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:181027$13101_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181029$13103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:181029$13103_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181032$13106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:181032$13106_Y - end - attribute \src "libresoc.v:180991.7-180991.20" - process $proc$libresoc.v:180991$13112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:282" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:41192.7-41192.20" + process $proc$libresoc.v:41192$940 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181013.13-181013.26" - process $proc$libresoc.v:181013$13113 + attribute \src "libresoc.v:41209.3-41223.6" + process $proc$libresoc.v:41209$938 assign { } { } - assign $1\q_int[4:0] 5'00000 - sync always - sync init - update \q_int $1\q_int[4:0] - end - attribute \src "libresoc.v:181034.3-181035.27" - process $proc$libresoc.v:181034$13108 assign { } { } - assign $0\q_int[4:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[4:0] + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:41210.5-41210.29" + switch \initial + attribute \src "libresoc.v:41210.9-41210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:181036.3-181044.6" - process $proc$libresoc.v:181036$13109 + attribute \src "libresoc.v:41224.3-41238.6" + process $proc$libresoc.v:41224$939 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13110 $1\q_int$next[4:0]$13111 - attribute \src "libresoc.v:181037.5-181037.29" + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:41225.5-41225.29" switch \initial - attribute \src "libresoc.v:181037.9-181037.17" + attribute \src "libresoc.v:41225.9-41225.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 assign { } { } - assign $1\q_int$next[4:0]$13111 5'00000 + assign $1\reg_c_ok[0:0] 1'1 case - assign $1\q_int$next[4:0]$13111 \$5 + assign $1\reg_c_ok[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[4:0]$13110 + update \reg_c_ok $0\reg_c_ok[0:0] end - connect \$9 $and$libresoc.v:181026$13100_Y - connect \$11 $or$libresoc.v:181027$13101_Y - connect \$13 $not$libresoc.v:181028$13102_Y - connect \$15 $or$libresoc.v:181029$13103_Y - connect \$1 $not$libresoc.v:181030$13104_Y - connect \$3 $and$libresoc.v:181031$13105_Y - connect \$5 $or$libresoc.v:181032$13106_Y - connect \$7 $not$libresoc.v:181033$13107_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 end -attribute \src "libresoc.v:181052.1-181110.10" +attribute \src "libresoc.v:41243.1-41548.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" -module \src_l$127 - attribute \src "libresoc.v:181053.7-181053.20" +module \dec_cr_in + attribute \src "libresoc.v:41442.3-41468.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:41469.3-41479.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41420.3-41430.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:41480.3-41490.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:41491.3-41501.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:41393.3-41419.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41529.3-41547.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:41431.3-41441.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41244.7-41244.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181098.3-181106.6" - wire width 3 $0\q_int$next[2:0]$13124 - attribute \src "libresoc.v:181096.3-181097.27" - wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181098.3-181106.6" - wire width 3 $1\q_int$next[2:0]$13125 - attribute \src "libresoc.v:181075.13-181075.25" - wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181088.17-181088.96" - wire width 3 $and$libresoc.v:181088$13114_Y - attribute \src "libresoc.v:181093.17-181093.96" - wire width 3 $and$libresoc.v:181093$13119_Y - attribute \src "libresoc.v:181090.18-181090.93" - wire width 3 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$and$libresoc.v:41388$944 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:181089$13115_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:41388$944_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181091$13117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:41385$941 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:181091$13117_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41385$941_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181094$13120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + cell $eq $eq$libresoc.v:41387$943 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:181094$13120_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:41387$943_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:41389.9-41392.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o end - attribute \src "libresoc.v:181053.7-181053.20" - process $proc$libresoc.v:181053$13126 + attribute \src "libresoc.v:41244.7-41244.20" + process $proc$libresoc.v:41244$955 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - 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"libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:181098.3-181106.6" - process $proc$libresoc.v:181098$13123 + attribute \src "libresoc.v:41420.3-41430.6" + process $proc$libresoc.v:41420$946 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13124 $1\q_int$next[2:0]$13125 - attribute \src "libresoc.v:181099.5-181099.29" + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:41421.5-41421.29" switch \initial - attribute \src "libresoc.v:181099.9-181099.17" + attribute \src "libresoc.v:41421.9-41421.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'100 assign { } { } - assign $1\q_int$next[2:0]$13125 3'000 + assign $1\cr_bitfield_b_ok[0:0] 1'1 case - assign $1\q_int$next[2:0]$13125 \$5 + assign $1\cr_bitfield_b_ok[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[2:0]$13124 - end - connect \$9 $and$libresoc.v:181088$13114_Y - connect \$11 $or$libresoc.v:181089$13115_Y - connect \$13 $not$libresoc.v:181090$13116_Y - connect \$15 $or$libresoc.v:181091$13117_Y - connect \$1 $not$libresoc.v:181092$13118_Y - connect \$3 $and$libresoc.v:181093$13119_Y - connect \$5 $or$libresoc.v:181094$13120_Y - connect \$7 $not$libresoc.v:181095$13121_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "libresoc.v:181114.1-181172.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" -attribute \generator "nMigen" -module \src_l$23 - attribute \src "libresoc.v:181115.7-181115.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:181160.3-181168.6" - wire width 3 $0\q_int$next[2:0]$13138 - attribute \src "libresoc.v:181158.3-181159.27" - wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181160.3-181168.6" - wire width 3 $1\q_int$next[2:0]$13139 - attribute \src "libresoc.v:181137.13-181137.25" - wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181150.17-181150.96" - wire width 3 $and$libresoc.v:181150$13128_Y - attribute \src "libresoc.v:181155.17-181155.96" - wire width 3 $and$libresoc.v:181155$13133_Y - attribute \src "libresoc.v:181152.18-181152.93" - wire width 3 $not$libresoc.v:181152$13130_Y - attribute \src "libresoc.v:181154.17-181154.92" - wire width 3 $not$libresoc.v:181154$13132_Y - attribute \src "libresoc.v:181157.17-181157.92" - wire width 3 $not$libresoc.v:181157$13135_Y - attribute \src "libresoc.v:181151.18-181151.98" - wire width 3 $or$libresoc.v:181151$13129_Y - attribute \src "libresoc.v:181153.18-181153.99" - wire width 3 $or$libresoc.v:181153$13131_Y - attribute \src "libresoc.v:181156.17-181156.97" - wire width 3 $or$libresoc.v:181156$13134_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:181115.7-181115.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181150$13128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181150$13128_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181155$13133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181155$13133_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181152$13130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$libresoc.v:181152$13130_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181154$13132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:181154$13132_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181157$13135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:181157$13135_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181151$13129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:181151$13129_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181153$13131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:181153$13131_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181156$13134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:181156$13134_Y + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:181115.7-181115.20" - process $proc$libresoc.v:181115$13140 + attribute \src "libresoc.v:41431.3-41441.6" + process $proc$libresoc.v:41431$947 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:181137.13-181137.25" - process $proc$libresoc.v:181137$13141 assign { } { } - assign $1\q_int[2:0] 3'000 + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41432.5-41432.29" + switch \initial + attribute \src "libresoc.v:41432.9-41432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[2:0] - end - attribute \src "libresoc.v:181158.3-181159.27" - process $proc$libresoc.v:181158$13136 - assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:181160.3-181168.6" - process $proc$libresoc.v:181160$13137 + attribute \src "libresoc.v:41442.3-41468.6" + process $proc$libresoc.v:41442$948 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13138 $1\q_int$next[2:0]$13139 - attribute \src "libresoc.v:181161.5-181161.29" + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41443.5-41443.29" switch \initial - attribute \src "libresoc.v:181161.9-181161.17" + attribute \src "libresoc.v:41443.9-41443.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 assign { } { } - assign $1\q_int$next[2:0]$13139 3'000 + assign $1\cr_bitfield[2:0] \BC [4:2] case - assign $1\q_int$next[2:0]$13139 \$5 + assign $1\cr_bitfield[2:0] 3'000 end sync always - update \q_int$next $0\q_int$next[2:0]$13138 - end - connect \$9 $and$libresoc.v:181150$13128_Y - connect \$11 $or$libresoc.v:181151$13129_Y - connect \$13 $not$libresoc.v:181152$13130_Y - connect \$15 $or$libresoc.v:181153$13131_Y - connect \$1 $not$libresoc.v:181154$13132_Y - connect \$3 $and$libresoc.v:181155$13133_Y - connect \$5 $or$libresoc.v:181156$13134_Y - connect \$7 $not$libresoc.v:181157$13135_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "libresoc.v:181176.1-181234.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" -attribute \generator "nMigen" -module \src_l$39 - attribute \src "libresoc.v:181177.7-181177.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:181222.3-181230.6" - wire width 4 $0\q_int$next[3:0]$13152 - attribute \src "libresoc.v:181220.3-181221.27" - wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:181222.3-181230.6" - wire width 4 $1\q_int$next[3:0]$13153 - attribute \src "libresoc.v:181199.13-181199.25" - wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:181212.17-181212.96" - wire width 4 $and$libresoc.v:181212$13142_Y - attribute \src "libresoc.v:181217.17-181217.96" - wire width 4 $and$libresoc.v:181217$13147_Y - attribute \src "libresoc.v:181214.18-181214.93" - wire width 4 $not$libresoc.v:181214$13144_Y - attribute \src "libresoc.v:181216.17-181216.92" - wire width 4 $not$libresoc.v:181216$13146_Y - attribute \src "libresoc.v:181219.17-181219.92" - wire width 4 $not$libresoc.v:181219$13149_Y - attribute \src "libresoc.v:181213.18-181213.98" - wire width 4 $or$libresoc.v:181213$13143_Y - attribute \src "libresoc.v:181215.18-181215.99" - wire width 4 $or$libresoc.v:181215$13145_Y - attribute \src "libresoc.v:181218.17-181218.97" - wire width 4 $or$libresoc.v:181218$13148_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:181177.7-181177.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181212$13142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181212$13142_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181217$13147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181217$13147_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181214$13144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $not$libresoc.v:181214$13144_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181216$13146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$libresoc.v:181216$13146_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181219$13149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $not$libresoc.v:181219$13149_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181213$13143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:181213$13143_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181215$13145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:181215$13145_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181218$13148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:181218$13148_Y + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:181177.7-181177.20" - process $proc$libresoc.v:181177$13154 + attribute \src "libresoc.v:41469.3-41479.6" + process $proc$libresoc.v:41469$949 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:181199.13-181199.25" - process $proc$libresoc.v:181199$13155 assign { } { } - assign $1\q_int[3:0] 4'0000 + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:41470.5-41470.29" + switch \initial + attribute \src "libresoc.v:41470.9-41470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end sync always - sync init - update \q_int $1\q_int[3:0] - end - attribute \src "libresoc.v:181220.3-181221.27" - process $proc$libresoc.v:181220$13150 - assign { } { } - assign $0\q_int[3:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[3:0] + update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:181222.3-181230.6" - process $proc$libresoc.v:181222$13151 + attribute \src "libresoc.v:41480.3-41490.6" + process $proc$libresoc.v:41480$950 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13152 $1\q_int$next[3:0]$13153 - attribute \src "libresoc.v:181223.5-181223.29" + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:41481.5-41481.29" switch \initial - attribute \src "libresoc.v:181223.9-181223.17" + attribute \src "libresoc.v:41481.9-41481.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'100 assign { } { } - assign $1\q_int$next[3:0]$13153 4'0000 + assign $1\cr_bitfield_o[2:0] \BT [4:2] case - assign $1\q_int$next[3:0]$13153 \$5 + assign $1\cr_bitfield_o[2:0] 3'000 end sync always - update \q_int$next $0\q_int$next[3:0]$13152 - end - connect \$9 $and$libresoc.v:181212$13142_Y - connect \$11 $or$libresoc.v:181213$13143_Y - connect \$13 $not$libresoc.v:181214$13144_Y - connect \$15 $or$libresoc.v:181215$13145_Y - connect \$1 $not$libresoc.v:181216$13146_Y - connect \$3 $and$libresoc.v:181217$13147_Y - connect \$5 $or$libresoc.v:181218$13148_Y - connect \$7 $not$libresoc.v:181219$13149_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "libresoc.v:181238.1-181296.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" -attribute \generator "nMigen" -module \src_l$55 - attribute \src "libresoc.v:181239.7-181239.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:181284.3-181292.6" - wire width 3 $0\q_int$next[2:0]$13166 - attribute \src "libresoc.v:181282.3-181283.27" - wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181284.3-181292.6" - wire width 3 $1\q_int$next[2:0]$13167 - attribute \src "libresoc.v:181261.13-181261.25" - wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181274.17-181274.96" - wire width 3 $and$libresoc.v:181274$13156_Y - attribute \src "libresoc.v:181279.17-181279.96" - wire width 3 $and$libresoc.v:181279$13161_Y - attribute \src "libresoc.v:181276.18-181276.93" - wire width 3 $not$libresoc.v:181276$13158_Y - attribute \src "libresoc.v:181278.17-181278.92" - wire width 3 $not$libresoc.v:181278$13160_Y - attribute \src "libresoc.v:181281.17-181281.92" - wire width 3 $not$libresoc.v:181281$13163_Y - attribute \src "libresoc.v:181275.18-181275.98" - wire width 3 $or$libresoc.v:181275$13157_Y - attribute \src "libresoc.v:181277.18-181277.99" - wire width 3 $or$libresoc.v:181277$13159_Y - attribute \src "libresoc.v:181280.17-181280.97" - wire width 3 $or$libresoc.v:181280$13162_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:181239.7-181239.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181274$13156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181274$13156_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181279$13161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181279$13161_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181276$13158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$libresoc.v:181276$13158_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181278$13160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:181278$13160_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181281$13163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:181281$13163_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181275$13157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:181275$13157_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181277$13159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:181277$13159_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181280$13162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:181280$13162_Y + update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:181239.7-181239.20" - process $proc$libresoc.v:181239$13168 + attribute \src "libresoc.v:41491.3-41501.6" + process $proc$libresoc.v:41491$951 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:41492.5-41492.29" + switch \initial + attribute \src "libresoc.v:41492.9-41492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end sync always - update \initial $0\initial[0:0] - sync init + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:181261.13-181261.25" - process $proc$libresoc.v:181261$13169 + attribute \src "libresoc.v:41502.3-41512.6" + process $proc$libresoc.v:41502$952 assign { } { } - assign $1\q_int[2:0] 3'000 + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:41503.5-41503.29" + switch \initial + attribute \src "libresoc.v:41503.9-41503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[2:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:181282.3-181283.27" - process $proc$libresoc.v:181282$13164 + attribute \src "libresoc.v:41513.3-41528.6" + process $proc$libresoc.v:41513$953 assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:41514.5-41514.29" + switch \initial + attribute \src "libresoc.v:41514.9-41514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:181284.3-181292.6" - process $proc$libresoc.v:181284$13165 + attribute \src "libresoc.v:41529.3-41547.6" + process $proc$libresoc.v:41529$954 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13166 $1\q_int$next[2:0]$13167 - attribute \src "libresoc.v:181285.5-181285.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:41530.5-41530.29" switch \initial - attribute \src "libresoc.v:181285.9-181285.17" + attribute \src "libresoc.v:41530.9-41530.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:506" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'110 assign { } { } - assign $1\q_int$next[2:0]$13167 3'000 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\q_int$next[2:0]$13167 \$5 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \q_int$next $0\q_int$next[2:0]$13166 + update \cr_fxm $0\cr_fxm[7:0] end - connect \$9 $and$libresoc.v:181274$13156_Y - connect \$11 $or$libresoc.v:181275$13157_Y - connect \$13 $not$libresoc.v:181276$13158_Y - connect \$15 $or$libresoc.v:181277$13159_Y - connect \$1 $not$libresoc.v:181278$13160_Y - connect \$3 $and$libresoc.v:181279$13161_Y - connect \$5 $or$libresoc.v:181280$13162_Y - connect \$7 $not$libresoc.v:181281$13163_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 + connect \$1 $eq$libresoc.v:41385$941_Y + connect \$3 $and$libresoc.v:41386$942_Y + connect \$5 $eq$libresoc.v:41387$943_Y + connect \$7 $and$libresoc.v:41388$944_Y end -attribute \src "libresoc.v:181300.1-181358.10" +attribute \src "libresoc.v:41552.1-41795.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" 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"libresoc.v:181341.17-181341.96" - wire width 6 $and$libresoc.v:181341$13175_Y - attribute \src "libresoc.v:181338.18-181338.93" - wire width 6 $not$libresoc.v:181338$13172_Y - attribute \src "libresoc.v:181340.17-181340.92" - wire width 6 $not$libresoc.v:181340$13174_Y - attribute \src "libresoc.v:181343.17-181343.92" - wire width 6 $not$libresoc.v:181343$13177_Y - attribute \src "libresoc.v:181337.18-181337.98" - wire width 6 $or$libresoc.v:181337$13171_Y - attribute \src "libresoc.v:181339.18-181339.99" - wire width 6 $or$libresoc.v:181339$13173_Y - attribute \src "libresoc.v:181342.17-181342.97" - wire width 6 $or$libresoc.v:181342$13176_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:181301.7-181301.15" + attribute \src "libresoc.v:41728.3-41738.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:41709.3-41727.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41679.3-41697.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:41698.3-41708.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41728.3-41738.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:41739.3-41759.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:41760.3-41794.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:41672.17-41672.117" + wire $eq$libresoc.v:41672$956_Y + attribute \src "libresoc.v:41673.17-41673.117" + wire $eq$libresoc.v:41673$957_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:41553.7-41553.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181336$13170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181336$13170_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181341$13175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181341$13175_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181338$13172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $not$libresoc.v:181338$13172_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181340$13174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$libresoc.v:181340$13174_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181343$13177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $not$libresoc.v:181343$13177_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181337$13171 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:554" + wire width 32 input 11 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:552" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:553" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:41672$956 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:181337$13171_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:41672$956_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181339$13173 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + cell $eq $eq$libresoc.v:41673$957 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:181339$13173_Y + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:41673$957_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181342$13176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:181342$13176_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:41674.13-41678.4" + cell \ppick$1 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o end - attribute \src "libresoc.v:181301.7-181301.20" - process $proc$libresoc.v:181301$13182 + attribute \src "libresoc.v:41553.7-41553.20" + process $proc$libresoc.v:41553$964 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181323.13-181323.26" - process $proc$libresoc.v:181323$13183 + attribute \src "libresoc.v:41679.3-41697.6" + process $proc$libresoc.v:41679$958 assign { } { } - assign $1\q_int[5:0] 6'000000 - sync always - sync init - update \q_int $1\q_int[5:0] - end - attribute \src "libresoc.v:181344.3-181345.27" - process $proc$libresoc.v:181344$13178 assign { } { } - assign $0\q_int[5:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[5:0] + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:41680.5-41680.29" + switch \initial + attribute \src "libresoc.v:41680.9-41680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:181346.3-181354.6" - process $proc$libresoc.v:181346$13179 + attribute \src "libresoc.v:41698.3-41708.6" + process $proc$libresoc.v:41698$959 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13180 $1\q_int$next[5:0]$13181 - attribute \src "libresoc.v:181347.5-181347.29" + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:41699.5-41699.29" switch \initial - attribute \src "libresoc.v:181347.9-181347.17" + attribute \src "libresoc.v:41699.9-41699.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'100 assign { } { } - assign $1\q_int$next[5:0]$13181 6'000000 + assign $1\cr_fxm_ok[0:0] 1'1 case - assign $1\q_int$next[5:0]$13181 \$5 + assign $1\cr_fxm_ok[0:0] 1'0 end sync always - update \q_int$next $0\q_int$next[5:0]$13180 - end - connect \$9 $and$libresoc.v:181336$13170_Y - connect \$11 $or$libresoc.v:181337$13171_Y - connect \$13 $not$libresoc.v:181338$13172_Y - connect \$15 $or$libresoc.v:181339$13173_Y - connect \$1 $not$libresoc.v:181340$13174_Y - connect \$3 $and$libresoc.v:181341$13175_Y - connect \$5 $or$libresoc.v:181342$13176_Y - connect \$7 $not$libresoc.v:181343$13177_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 -end -attribute \src "libresoc.v:181362.1-181420.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" -attribute \generator "nMigen" -module \src_l$84 - attribute \src "libresoc.v:181363.7-181363.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:181408.3-181416.6" - wire width 3 $0\q_int$next[2:0]$13194 - attribute \src "libresoc.v:181406.3-181407.27" - wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:181408.3-181416.6" - wire width 3 $1\q_int$next[2:0]$13195 - attribute \src "libresoc.v:181385.13-181385.25" - wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:181398.17-181398.96" - wire width 3 $and$libresoc.v:181398$13184_Y - attribute \src "libresoc.v:181403.17-181403.96" - wire width 3 $and$libresoc.v:181403$13189_Y - attribute \src "libresoc.v:181400.18-181400.93" - wire width 3 $not$libresoc.v:181400$13186_Y - attribute \src "libresoc.v:181402.17-181402.92" - wire width 3 $not$libresoc.v:181402$13188_Y - attribute \src "libresoc.v:181405.17-181405.92" - wire width 3 $not$libresoc.v:181405$13191_Y - attribute \src "libresoc.v:181399.18-181399.98" - wire width 3 $or$libresoc.v:181399$13185_Y - attribute \src "libresoc.v:181401.18-181401.99" - wire width 3 $or$libresoc.v:181401$13187_Y - attribute \src "libresoc.v:181404.17-181404.97" - wire width 3 $or$libresoc.v:181404$13190_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:181363.7-181363.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181398$13184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181398$13184_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181403$13189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181403$13189_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181400$13186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $not$libresoc.v:181400$13186_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181402$13188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:181402$13188_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181405$13191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $not$libresoc.v:181405$13191_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181399$13185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$9 - connect \B \s_src - connect \Y $or$libresoc.v:181399$13185_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181401$13187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $or$libresoc.v:181401$13187_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181404$13190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \$3 - connect \B \s_src - connect \Y $or$libresoc.v:181404$13190_Y + update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:181363.7-181363.20" - process $proc$libresoc.v:181363$13196 + attribute \src "libresoc.v:41709.3-41727.6" + process $proc$libresoc.v:41709$960 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:41710.5-41710.29" + switch \initial + attribute \src "libresoc.v:41710.9-41710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end sync always - update \initial $0\initial[0:0] - sync init + update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:181385.13-181385.25" - process $proc$libresoc.v:181385$13197 + attribute \src "libresoc.v:41728.3-41738.6" + process $proc$libresoc.v:41728$961 + assign { } { } assign { } { } - assign $1\q_int[2:0] 3'000 + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:41729.5-41729.29" + switch \initial + attribute \src "libresoc.v:41729.9-41729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end sync always - sync init - update \q_int $1\q_int[2:0] + update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:181406.3-181407.27" - process $proc$libresoc.v:181406$13192 + attribute \src "libresoc.v:41739.3-41759.6" + process $proc$libresoc.v:41739$962 assign { } { } - assign $0\q_int[2:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[2:0] + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:41740.5-41740.29" + switch \initial + attribute \src "libresoc.v:41740.9-41740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:181408.3-181416.6" - process $proc$libresoc.v:181408$13193 + attribute \src "libresoc.v:41760.3-41794.6" + process $proc$libresoc.v:41760$963 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13194 $1\q_int$next[2:0]$13195 - attribute \src "libresoc.v:181409.5-181409.29" + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:41761.5-41761.29" switch \initial - attribute \src "libresoc.v:181409.9-181409.17" + attribute \src "libresoc.v:41761.9-41761.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:567" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 3'100 assign { } { } - assign $1\q_int$next[2:0]$13195 3'000 + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:584" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end case - assign $1\q_int$next[2:0]$13195 \$5 + assign $1\cr_fxm[7:0] 8'00000000 end sync always - update \q_int$next $0\q_int$next[2:0]$13194 + update \cr_fxm $0\cr_fxm[7:0] end - connect \$9 $and$libresoc.v:181398$13184_Y - connect \$11 $or$libresoc.v:181399$13185_Y - connect \$13 $not$libresoc.v:181400$13186_Y - connect \$15 $or$libresoc.v:181401$13187_Y - connect \$1 $not$libresoc.v:181402$13188_Y - connect \$3 $and$libresoc.v:181403$13189_Y - connect \$5 $or$libresoc.v:181404$13190_Y - connect \$7 $not$libresoc.v:181405$13191_Y - connect \qlq_src \$15 - connect \qn_src \$13 - connect \q_src \$11 + connect \$1 $eq$libresoc.v:41672$956_Y + connect \$3 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+ wire $2\spr_o_ok[0:0] + attribute \src "libresoc.v:42204.3-42219.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42237.3-42275.6" + wire width 3 $3\fast_o[2:0] + attribute \src "libresoc.v:42237.3-42275.6" + wire $3\fast_o_ok[0:0] + attribute \src "libresoc.v:42237.3-42275.6" + wire width 3 $4\fast_o[2:0] + attribute \src "libresoc.v:42237.3-42275.6" + wire $4\fast_o_ok[0:0] + attribute \src "libresoc.v:42152.17-42152.117" + wire $eq$libresoc.v:42152$965_Y + attribute \src "libresoc.v:42153.17-42153.117" + wire $eq$libresoc.v:42153$966_Y + attribute \src "libresoc.v:42154.17-42154.117" + wire $eq$libresoc.v:42154$967_Y + attribute \src "libresoc.v:42155.17-42155.104" + wire $not$libresoc.v:42155$968_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 8 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \fast_o_ok + attribute \src "libresoc.v:41800.7-41800.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 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"TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 4 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:42152$965 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181460$13198_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42152$965_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181465$13203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:42153$966 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181465$13203_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181462$13200 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \Y $not$libresoc.v:181462$13200_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181464$13202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $not$libresoc.v:181464$13202_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181467$13205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $not$libresoc.v:181467$13205_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42153$966_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181461$13199 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + cell $eq $eq$libresoc.v:42154$967 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_st_active - connect \Y $or$libresoc.v:181461$13199_Y + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:42154$967_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181463$13201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + cell $not $not$libresoc.v:42155$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \B \q_int - connect \Y $or$libresoc.v:181463$13201_Y + connect \A \BO [2] + connect \Y $not$libresoc.v:42155$968_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181466$13204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_st_active - connect \Y $or$libresoc.v:181466$13204_Y + attribute \module_not_derived 1 + attribute \src "libresoc.v:42156.14-42162.4" + cell \sprmap$2 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:181425.7-181425.20" - process $proc$libresoc.v:181425$13210 + attribute \src "libresoc.v:41800.7-41800.20" + process $proc$libresoc.v:41800$975 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181447.7-181447.19" - process $proc$libresoc.v:181447$13211 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:181468.3-181469.27" - process $proc$libresoc.v:181468$13206 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:181470.3-181478.6" - process $proc$libresoc.v:181470$13207 + attribute \src "libresoc.v:42163.3-42177.6" + process $proc$libresoc.v:42163$969 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13208 $1\q_int$next[0:0]$13209 - attribute \src "libresoc.v:181471.5-181471.29" + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:42164.5-42164.29" switch \initial - attribute \src "libresoc.v:181471.9-181471.17" + attribute \src "libresoc.v:42164.9-42164.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 assign { } { } - assign $1\q_int$next[0:0]$13209 1'0 - case - assign $1\q_int$next[0:0]$13209 \$5 - end - sync always - update \q_int$next $0\q_int$next[0:0]$13208 - end - connect \$9 $and$libresoc.v:181460$13198_Y - connect \$11 $or$libresoc.v:181461$13199_Y - connect \$13 $not$libresoc.v:181462$13200_Y - connect \$15 $or$libresoc.v:181463$13201_Y - connect \$1 $not$libresoc.v:181464$13202_Y - connect \$3 $and$libresoc.v:181465$13203_Y - connect \$5 $or$libresoc.v:181466$13204_Y - connect \$7 $not$libresoc.v:181467$13205_Y - connect \qlq_st_active \$15 - connect \qn_st_active \$13 - connect \q_st_active \$11 -end -attribute \src "libresoc.v:181486.1-181544.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" -attribute \generator "nMigen" -module \st_done - attribute \src "libresoc.v:181487.7-181487.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:181532.3-181540.6" - wire $0\q_int$next[0:0]$13222 - attribute \src "libresoc.v:181530.3-181531.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:181532.3-181540.6" - wire $1\q_int$next[0:0]$13223 - attribute \src "libresoc.v:181509.7-181509.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:181522.17-181522.96" - wire $and$libresoc.v:181522$13212_Y - attribute \src "libresoc.v:181527.17-181527.96" - wire $and$libresoc.v:181527$13217_Y - attribute \src "libresoc.v:181524.18-181524.97" - wire $not$libresoc.v:181524$13214_Y - attribute \src "libresoc.v:181526.17-181526.96" - wire $not$libresoc.v:181526$13216_Y - attribute \src "libresoc.v:181529.17-181529.96" - wire $not$libresoc.v:181529$13219_Y - attribute \src "libresoc.v:181523.18-181523.102" - wire $or$libresoc.v:181523$13213_Y - attribute \src "libresoc.v:181525.18-181525.103" - wire $or$libresoc.v:181525$13215_Y - attribute \src "libresoc.v:181528.17-181528.101" - wire $or$libresoc.v:181528$13218_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:181487.7-181487.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181522$13212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181522$13212_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181527$13217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181527$13217_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181524$13214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \Y $not$libresoc.v:181524$13214_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181526$13216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $not$libresoc.v:181526$13216_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181529$13219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $not$libresoc.v:181529$13219_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181523$13213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_st_done - connect \Y $or$libresoc.v:181523$13213_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181525$13215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \B \q_int - connect \Y $or$libresoc.v:181525$13215_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181528$13218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_st_done - connect \Y $or$libresoc.v:181528$13218_Y - end - attribute \src "libresoc.v:181487.7-181487.20" - process $proc$libresoc.v:181487$13224 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:181509.7-181509.19" - process $proc$libresoc.v:181509$13225 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:181530.3-181531.27" - process $proc$libresoc.v:181530$13220 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:181532.3-181540.6" - process $proc$libresoc.v:181532$13221 - assign { } { } - assign { } { } - assign $0\q_int$next[0:0]$13222 $1\q_int$next[0:0]$13223 - attribute \src "libresoc.v:181533.5-181533.29" - switch \initial - attribute \src "libresoc.v:181533.9-181533.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + assign $1\reg_o[4:0] \RT attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $1\q_int$next[0:0]$13223 1'0 + assign $1\reg_o[4:0] \RA case - assign $1\q_int$next[0:0]$13223 \$5 + assign $1\reg_o[4:0] 5'00000 end sync always - update \q_int$next $0\q_int$next[0:0]$13222 - end - connect \$9 $and$libresoc.v:181522$13212_Y - connect \$11 $or$libresoc.v:181523$13213_Y - connect \$13 $not$libresoc.v:181524$13214_Y - connect \$15 $or$libresoc.v:181525$13215_Y - connect \$1 $not$libresoc.v:181526$13216_Y - connect \$3 $and$libresoc.v:181527$13217_Y - connect \$5 $or$libresoc.v:181528$13218_Y - connect \$7 $not$libresoc.v:181529$13219_Y - connect \qlq_st_done \$15 - connect \qn_st_done \$13 - connect \q_st_done \$11 -end -attribute \src "libresoc.v:181548.1-181803.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.state" -attribute \generator "nMigen" -module \state - attribute \src "libresoc.v:181776.3-181785.6" - wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:181549.7-181549.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:181757.3-181766.6" - wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:181748.3-181756.6" - wire width 4 $0\ren_delay$12$next[3:0]$13238 - attribute \src "libresoc.v:181688.3-181689.43" - wire width 4 $0\ren_delay$12[3:0]$13235 - attribute \src "libresoc.v:181669.13-181669.34" - wire width 4 $0\ren_delay$12[3:0]$13248 - attribute \src "libresoc.v:181767.3-181775.6" - wire width 4 $0\ren_delay$next[3:0]$13242 - attribute \src "libresoc.v:181690.3-181691.35" - wire width 4 $0\ren_delay[3:0] - attribute \src "libresoc.v:181776.3-181785.6" - wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:181757.3-181766.6" - wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:181748.3-181756.6" - wire width 4 $1\ren_delay$12$next[3:0]$13239 - attribute \src "libresoc.v:181767.3-181775.6" - wire width 4 $1\ren_delay$next[3:0]$13243 - attribute \src "libresoc.v:181667.13-181667.29" - wire width 4 $1\ren_delay[3:0] - attribute \src "libresoc.v:181680.18-181680.95" - wire width 64 $or$libresoc.v:181680$13226_Y - attribute \src "libresoc.v:181682.18-181682.124" - wire width 64 $or$libresoc.v:181682$13228_Y - attribute \src "libresoc.v:181683.18-181683.124" - wire width 64 $or$libresoc.v:181683$13229_Y - attribute \src "libresoc.v:181684.18-181684.97" - wire width 64 $or$libresoc.v:181684$13230_Y - attribute \src "libresoc.v:181686.17-181686.123" - wire width 64 $or$libresoc.v:181686$13232_Y - attribute \src "libresoc.v:181687.17-181687.123" - wire width 64 $or$libresoc.v:181687$13233_Y - attribute \src "libresoc.v:181681.18-181681.100" - wire $reduce_or$libresoc.v:181681$13227_Y - attribute \src "libresoc.v:181685.17-181685.95" - wire $reduce_or$libresoc.v:181685$13231_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 \$10 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 \$19 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 12 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 5 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 10 \data_i$2 - attribute \src "libresoc.v:181549.7-181549.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 6 \msr__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_cia0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_d_wr10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_0_nia0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_cia1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_d_wr11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_1_nia1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_cia2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_d_wr12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_d_wr12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_nia2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_cia3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_d_wr13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_d_wr13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_3_nia3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 8 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 4 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \wen$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:181680$13226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$6 - connect \B \$8 - connect \Y $or$libresoc.v:181680$13226_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181682$13228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_msr0__data_o - connect \B \reg_1_msr1__data_o - connect \Y $or$libresoc.v:181682$13228_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181683$13229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_2_msr2__data_o - connect \B \reg_3_msr3__data_o - connect \Y $or$libresoc.v:181683$13229_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:181684$13230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \$15 - connect \B \$17 - connect \Y $or$libresoc.v:181684$13230_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181686$13232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_cia0__data_o - connect \B \reg_1_cia1__data_o - connect \Y $or$libresoc.v:181686$13232_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:181687$13233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_2_cia2__data_o - connect \B \reg_3_cia3__data_o - connect \Y $or$libresoc.v:181687$13233_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:181681$13227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:181681$13227_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:181685$13231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:181685$13231_Y - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:181692.15-181705.4" - cell \reg_0$135 \reg_0 - connect \cia0__data_o \reg_0_cia0__data_o - connect \cia0__ren \reg_0_cia0__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr10__data_i \reg_0_d_wr10__data_i - connect \d_wr10__wen \reg_0_d_wr10__wen - connect \msr0__data_i \reg_0_msr0__data_i - connect \msr0__data_o \reg_0_msr0__data_o - connect \msr0__ren \reg_0_msr0__ren - connect \msr0__wen \reg_0_msr0__wen - connect \nia0__data_i \reg_0_nia0__data_i - connect \nia0__wen \reg_0_nia0__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:181706.15-181719.4" - cell \reg_1$136 \reg_1 - connect \cia1__data_o \reg_1_cia1__data_o - connect \cia1__ren \reg_1_cia1__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr11__data_i \reg_1_d_wr11__data_i - connect \d_wr11__wen \reg_1_d_wr11__wen - connect \msr1__data_i \reg_1_msr1__data_i - connect \msr1__data_o \reg_1_msr1__data_o - connect \msr1__ren \reg_1_msr1__ren - connect \msr1__wen \reg_1_msr1__wen - connect \nia1__data_i \reg_1_nia1__data_i - connect \nia1__wen \reg_1_nia1__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:181720.15-181733.4" - cell \reg_2$137 \reg_2 - connect \cia2__data_o \reg_2_cia2__data_o - connect \cia2__ren \reg_2_cia2__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr12__data_i \reg_2_d_wr12__data_i - connect \d_wr12__wen \reg_2_d_wr12__wen - connect \msr2__data_i \reg_2_msr2__data_i - connect \msr2__data_o \reg_2_msr2__data_o - connect \msr2__ren \reg_2_msr2__ren - connect \msr2__wen \reg_2_msr2__wen - connect \nia2__data_i \reg_2_nia2__data_i - connect \nia2__wen \reg_2_nia2__wen - end - attribute \module_not_derived 1 - attribute \src "libresoc.v:181734.15-181747.4" - cell \reg_3$138 \reg_3 - connect \cia3__data_o \reg_3_cia3__data_o - connect \cia3__ren \reg_3_cia3__ren - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \d_wr13__data_i \reg_3_d_wr13__data_i - connect \d_wr13__wen \reg_3_d_wr13__wen - connect \msr3__data_i \reg_3_msr3__data_i - connect \msr3__data_o \reg_3_msr3__data_o - connect \msr3__ren \reg_3_msr3__ren - connect \msr3__wen \reg_3_msr3__wen - connect \nia3__data_i \reg_3_nia3__data_i - connect \nia3__wen \reg_3_nia3__wen - end - attribute \src "libresoc.v:181549.7-181549.20" - process $proc$libresoc.v:181549$13245 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:181667.13-181667.29" - process $proc$libresoc.v:181667$13246 - assign { } { } - assign $1\ren_delay[3:0] 4'0000 - sync always - sync init - update \ren_delay $1\ren_delay[3:0] - end - attribute \src "libresoc.v:181669.13-181669.34" - process $proc$libresoc.v:181669$13247 - assign { } { } - assign $0\ren_delay$12[3:0]$13248 4'0000 - sync always - sync init - update \ren_delay$12 $0\ren_delay$12[3:0]$13248 - end - attribute \src "libresoc.v:181688.3-181689.43" - process $proc$libresoc.v:181688$13234 - assign { } { } - assign $0\ren_delay$12[3:0]$13235 \ren_delay$12$next - sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[3:0]$13235 - end - attribute \src "libresoc.v:181690.3-181691.35" - process $proc$libresoc.v:181690$13236 - assign { } { } - assign $0\ren_delay[3:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[3:0] + update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:181748.3-181756.6" - process $proc$libresoc.v:181748$13237 + attribute \src "libresoc.v:42178.3-42192.6" + process $proc$libresoc.v:42178$970 assign { } { } assign { } { } - assign $0\ren_delay$12$next[3:0]$13238 $1\ren_delay$12$next[3:0]$13239 - attribute \src "libresoc.v:181749.5-181749.29" + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42179.5-42179.29" switch \initial - attribute \src "libresoc.v:181749.9-181749.17" + attribute \src "libresoc.v:42179.9-42179.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign $1\ren_delay$12$next[3:0]$13239 4'0000 + assign $1\reg_o_ok[0:0] 1'1 case - assign $1\ren_delay$12$next[3:0]$13239 \msr__ren + assign $1\reg_o_ok[0:0] 1'0 end sync always - update \ren_delay$12$next $0\ren_delay$12$next[3:0]$13238 + update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:181757.3-181766.6" - process $proc$libresoc.v:181757$13240 + attribute \src "libresoc.v:42193.3-42203.6" + process $proc$libresoc.v:42193$971 assign { } { } assign { } { } - assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:181758.5-181758.29" + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:42194.5-42194.29" switch \initial - attribute \src "libresoc.v:181758.9-181758.17" + attribute \src "libresoc.v:42194.9-42194.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'11 assign { } { } - assign $1\msr__data_o[63:0] \$19 + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } case - assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr[9:0] 10'0000000000 end sync always - update \msr__data_o $0\msr__data_o[63:0] + update \spr $0\spr[9:0] end - attribute \src "libresoc.v:181767.3-181775.6" - process $proc$libresoc.v:181767$13241 + attribute \src "libresoc.v:42204.3-42219.6" + process $proc$libresoc.v:42204$972 assign { } { } assign { } { } - assign $0\ren_delay$next[3:0]$13242 $1\ren_delay$next[3:0]$13243 - attribute \src "libresoc.v:181768.5-181768.29" + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:42205.5-42205.29" switch \initial - attribute \src "libresoc.v:181768.9-181768.17" + attribute \src "libresoc.v:42205.9-42205.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'11 assign { } { } - assign $1\ren_delay$next[3:0]$13243 4'0000 + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end case - assign $1\ren_delay$next[3:0]$13243 \cia__ren + assign $1\sprmap_spr_i[9:0] 10'0000000000 end sync always - update \ren_delay$next $0\ren_delay$next[3:0]$13242 + update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:181776.3-181785.6" - process $proc$libresoc.v:181776$13244 + attribute \src "libresoc.v:42220.3-42236.6" + process $proc$libresoc.v:42220$973 + assign { } { } assign { } { } assign { } { } - assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:181777.5-181777.29" + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:42221.5-42221.29" switch \initial - attribute \src "libresoc.v:181777.9-181777.17" + attribute \src "libresoc.v:42221.9-42221.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'11 + assign { } { } assign { } { } - assign $1\cia__data_o[63:0] \$10 + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end case - assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 end sync always - update \cia__data_o $0\cia__data_o[63:0] - end - connect \$10 $or$libresoc.v:181680$13226_Y - connect \$13 $reduce_or$libresoc.v:181681$13227_Y - connect \$15 $or$libresoc.v:181682$13228_Y - connect \$17 $or$libresoc.v:181683$13229_Y - connect \$19 $or$libresoc.v:181684$13230_Y - connect \$4 $reduce_or$libresoc.v:181685$13231_Y - connect \$6 $or$libresoc.v:181686$13232_Y - connect \$8 $or$libresoc.v:181687$13233_Y - connect \reg_3_d_wr13__data_i \data_i - connect \reg_2_d_wr12__data_i \data_i - connect \reg_1_d_wr11__data_i \data_i - connect \reg_0_d_wr10__data_i \data_i - connect { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen - connect \reg_3_msr3__data_i \data_i$2 - connect \reg_2_msr2__data_i \data_i$2 - connect \reg_1_msr1__data_i \data_i$2 - connect \reg_0_msr0__data_i \data_i$2 - connect { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 - connect \reg_3_nia3__data_i \data_i$1 - connect \reg_2_nia2__data_i \data_i$1 - connect \reg_1_nia1__data_i \data_i$1 - connect \reg_0_nia0__data_i \data_i$1 - connect { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen - connect { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren - connect { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren -end -attribute \src "libresoc.v:181807.1-181865.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" -attribute \generator "nMigen" -module \sto_l - attribute \src "libresoc.v:181808.7-181808.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:181853.3-181861.6" - wire $0\q_int$next[0:0]$13259 - attribute \src "libresoc.v:181851.3-181852.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:181853.3-181861.6" - wire $1\q_int$next[0:0]$13260 - attribute \src "libresoc.v:181830.7-181830.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:181843.17-181843.96" - wire $and$libresoc.v:181843$13249_Y - attribute \src "libresoc.v:181848.17-181848.96" - wire $and$libresoc.v:181848$13254_Y - attribute \src "libresoc.v:181845.18-181845.93" - wire $not$libresoc.v:181845$13251_Y - attribute \src "libresoc.v:181847.17-181847.92" - wire $not$libresoc.v:181847$13253_Y - attribute \src "libresoc.v:181850.17-181850.92" - wire $not$libresoc.v:181850$13256_Y - attribute \src "libresoc.v:181844.18-181844.98" - wire $or$libresoc.v:181844$13250_Y - attribute \src "libresoc.v:181846.18-181846.99" - wire $or$libresoc.v:181846$13252_Y - attribute \src "libresoc.v:181849.17-181849.97" - wire $or$libresoc.v:181849$13255_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:181808.7-181808.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:181843$13249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:181843$13249_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:181848$13254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:181848$13254_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:181845$13251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \Y $not$libresoc.v:181845$13251_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:181847$13253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $not$libresoc.v:181847$13253_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:181850$13256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $not$libresoc.v:181850$13256_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:181844$13250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_sto - connect \Y $or$libresoc.v:181844$13250_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:181846$13252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \B \q_int - connect \Y $or$libresoc.v:181846$13252_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:181849$13255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_sto - connect \Y $or$libresoc.v:181849$13255_Y + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:181808.7-181808.20" - process $proc$libresoc.v:181808$13261 + attribute \src "libresoc.v:42237.3-42275.6" + process $proc$libresoc.v:42237$974 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:181830.7-181830.19" - process $proc$libresoc.v:181830$13262 assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:181851.3-181852.27" - process $proc$libresoc.v:181851$13257 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:181853.3-181861.6" - process $proc$libresoc.v:181853$13258 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13259 $1\q_int$next[0:0]$13260 - attribute \src "libresoc.v:181854.5-181854.29" + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:42238.5-42238.29" switch \initial - attribute \src "libresoc.v:181854.9-181854.17" + attribute \src "libresoc.v:42238.9-42238.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:324" + switch \sel_in attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'11 + assign { } { } assign { } { } - assign $1\q_int$next[0:0]$13260 1'0 + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end case - assign $1\q_int$next[0:0]$13260 \$5 + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 end - sync always - update \q_int$next $0\q_int$next[0:0]$13259 - end - connect \$9 $and$libresoc.v:181843$13249_Y - connect \$11 $or$libresoc.v:181844$13250_Y - connect \$13 $not$libresoc.v:181845$13251_Y - connect \$15 $or$libresoc.v:181846$13252_Y - connect \$1 $not$libresoc.v:181847$13253_Y - connect \$3 $and$libresoc.v:181848$13254_Y - connect \$5 $or$libresoc.v:181849$13255_Y - connect \$7 $not$libresoc.v:181850$13256_Y - connect \qlq_sto \$15 - connect \qn_sto \$13 - connect \q_sto \$11 -end -attribute \src "libresoc.v:181870.1-183013.10" -attribute \cells_not_processed 1 -attribute \top 1 -attribute \nmigen.hierarchy "test_issuer" -attribute \generator "nMigen" -module \test_issuer - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 9 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 7 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 6 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 8 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" - wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 372 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:36" - wire width 3 input 374 \clk_sel_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:34" - wire \clksel_clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" - wire \clksel_pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" - wire \clksel_pllclk_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:103" - wire input 4 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 344 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 338 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 347 \dbus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 346 \dbus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 342 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 340 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 339 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 348 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 341 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 343 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 345 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 19 \eint_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 20 \eint_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 21 \eint_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 22 \eint_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 23 \eint_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 37 \gpio_e10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_e10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_e10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_e10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 41 \gpio_e10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 42 \gpio_e10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 43 \gpio_e11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_e11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_e11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_e11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 47 \gpio_e11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 48 \gpio_e11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 49 \gpio_e12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_e12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_e12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_e12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 53 \gpio_e12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 54 \gpio_e12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 55 \gpio_e13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_e13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_e13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_e13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 59 \gpio_e13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 60 \gpio_e13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 61 \gpio_e14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \gpio_e14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \gpio_e14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \gpio_e14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 65 \gpio_e14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 66 \gpio_e14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 67 \gpio_e15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \gpio_e15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \gpio_e15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \gpio_e15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 71 \gpio_e15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 72 \gpio_e15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 25 \gpio_e8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \gpio_e8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 29 \gpio_e8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 30 \gpio_e8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 31 \gpio_e9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 35 \gpio_e9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 36 \gpio_e9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 73 \gpio_s0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \gpio_s0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \gpio_s0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \gpio_s0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 77 \gpio_s0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 78 \gpio_s0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 79 \gpio_s1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \gpio_s1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \gpio_s1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \gpio_s1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 83 \gpio_s1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 84 \gpio_s1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 85 \gpio_s2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \gpio_s2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \gpio_s2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \gpio_s2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 89 \gpio_s2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 90 \gpio_s2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 91 \gpio_s3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \gpio_s3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \gpio_s3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \gpio_s3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 95 \gpio_s3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 96 \gpio_s3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 97 \gpio_s4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \gpio_s4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \gpio_s4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \gpio_s4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 101 \gpio_s4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 102 \gpio_s4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 103 \gpio_s5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \gpio_s5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \gpio_s5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \gpio_s5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 107 \gpio_s5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 108 \gpio_s5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 109 \gpio_s6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \gpio_s6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \gpio_s6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \gpio_s6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 113 \gpio_s6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 114 \gpio_s6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 115 \gpio_s7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \gpio_s7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \gpio_s7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \gpio_s7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 119 \gpio_s7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 120 \gpio_s7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 333 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 327 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 336 \ibus__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 335 \ibus__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 331 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 329 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 328 \ibus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 337 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 330 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 332 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 334 \ibus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 355 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 349 \icp_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 2 input 358 \icp_wb__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 3 input 357 \icp_wb__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 353 \icp_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 351 \icp_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 350 \icp_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 359 \icp_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 352 \icp_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 354 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 356 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 366 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 360 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 2 input 369 \ics_wb__bte - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 3 input 368 \ics_wb__cti - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 364 \ics_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 362 \ics_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 361 \ics_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 370 \ics_wb__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 363 \ics_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 365 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 367 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 371 \int_level_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 17 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 10 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 14 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 12 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 11 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 18 \jtag_wb__err - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 13 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 15 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 16 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" - wire input 3 \memerr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \mspi0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 122 \mspi0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \mspi0_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 124 \mspi0_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 127 \mspi0_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \mspi0_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \mspi0_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 126 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 130 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 132 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 135 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 134 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 144 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 137 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 141 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 142 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:42152$965_Y + connect \$3 $eq$libresoc.v:42153$966_Y + connect \$5 $eq$libresoc.v:42154$967_Y + connect \$7 $not$libresoc.v:42155$968_Y +end +attribute \src "libresoc.v:42280.1-42441.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:42401.3-42420.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:42421.3-42440.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:42281.7-42281.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:42401.3-42420.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:42421.3-42440.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:42387.3-42400.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42401.3-42420.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:42421.3-42440.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:42385.17-42385.108" + wire $eq$libresoc.v:42385$976_Y + attribute \src "libresoc.v:42386.17-42386.100" + wire width 6 $extend$libresoc.v:42386$977_Y + attribute \src "libresoc.v:42386.17-42386.100" + wire width 6 $pos$libresoc.v:42386$978_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire width 5 input 7 \RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 376 \pc_i + wire width 3 output 4 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 1 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:101" - wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:35" - wire output 375 \pll_48_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:78" - wire \pll_clk_24_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/select.py:79" - wire \pll_clk_pll_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 146 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 373 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 156 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 149 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 153 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 154 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 157 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 161 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 162 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 178 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 231 \sdr_a_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sdr_a_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 267 \sdr_a_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 269 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 271 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 233 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 235 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 237 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 239 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 241 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 243 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 245 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_a_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 247 \sdr_a_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_a_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 249 \sdr_a_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_a_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 251 \sdr_ba_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_ba_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 253 \sdr_ba_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_ba_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 261 \sdr_cas_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_cas_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 257 \sdr_cke__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_cke__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 255 \sdr_clock__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_clock__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 265 \sdr_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 181 \sdr_dm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 274 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 275 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 276 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \sdr_dq_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 184 \sdr_dq_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 185 \sdr_dq_0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 186 \sdr_dq_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \sdr_dq_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \sdr_dq_0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dq_10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 292 \sdr_dq_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 293 \sdr_dq_10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 294 \sdr_dq_10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 298 \sdr_dq_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 299 \sdr_dq_11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 300 \sdr_dq_11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 304 \sdr_dq_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 305 \sdr_dq_12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 306 \sdr_dq_12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 310 \sdr_dq_13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 311 \sdr_dq_13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 312 \sdr_dq_13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 316 \sdr_dq_14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 317 \sdr_dq_14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 318 \sdr_dq_14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 322 \sdr_dq_15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 323 \sdr_dq_15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 324 \sdr_dq_15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \sdr_dq_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 190 \sdr_dq_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 191 \sdr_dq_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 192 \sdr_dq_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \sdr_dq_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \sdr_dq_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \sdr_dq_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 196 \sdr_dq_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 197 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 198 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 202 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 203 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 204 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 208 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 209 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 210 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 214 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 215 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 216 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \sdr_dq_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \sdr_dq_5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \sdr_dq_6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 220 \sdr_dq_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 221 \sdr_dq_6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 222 \sdr_dq_6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \sdr_dq_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \sdr_dq_6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \sdr_dq_7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 226 \sdr_dq_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 227 \sdr_dq_7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 228 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 280 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 281 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 282 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 286 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 287 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 288 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 259 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 263 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire \ti_coresync_clk - attribute \module_not_derived 1 - attribute \src "libresoc.v:182635.10-182641.4" - cell \clksel \clksel - connect \clk_24_i \clksel_clk_24_i - connect \clk_sel_i \clk_sel_i - connect \pll_48_o \pll_48_o - connect \pllclk_clk \clksel_pllclk_clk - connect \pllclk_rst \clksel_pllclk_rst + wire output 5 \fast_o_ok + attribute \src "libresoc.v:42281.7-42281.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:366" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + cell $eq $eq$libresoc.v:42385$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:42385$976_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:182642.7-182645.4" - cell \pll \pll - connect \clk_24_i \pll_clk_24_i - connect \clk_pll_o \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $extend$libresoc.v:42386$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $extend$libresoc.v:42386$977_Y end - attribute \module_not_derived 1 - attribute \src "libresoc.v:182646.6-183007.4" - cell \ti \ti - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_bus__tdo \TAP_bus__tdo - connect \TAP_bus__tms \TAP_bus__tms - connect \busy_o \busy_o - connect \clk \clk - connect \core_bigendian_i \core_bigendian_i - connect \coresync_clk \ti_coresync_clk - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \eint_0__core__i \eint_0__core__i - connect \eint_0__pad__i \eint_0__pad__i - connect \eint_1__core__i \eint_1__core__i - connect \eint_1__pad__i \eint_1__pad__i - connect \eint_2__core__i \eint_2__core__i - connect \eint_2__pad__i \eint_2__pad__i - connect \gpio_e10__core__i \gpio_e10__core__i - connect \gpio_e10__core__o \gpio_e10__core__o - connect \gpio_e10__core__oe \gpio_e10__core__oe - connect \gpio_e10__pad__i \gpio_e10__pad__i - connect \gpio_e10__pad__o \gpio_e10__pad__o - connect \gpio_e10__pad__oe \gpio_e10__pad__oe - connect \gpio_e11__core__i \gpio_e11__core__i - connect \gpio_e11__core__o \gpio_e11__core__o - connect \gpio_e11__core__oe \gpio_e11__core__oe - connect \gpio_e11__pad__i \gpio_e11__pad__i - connect \gpio_e11__pad__o \gpio_e11__pad__o - connect \gpio_e11__pad__oe \gpio_e11__pad__oe - connect \gpio_e12__core__i \gpio_e12__core__i - connect \gpio_e12__core__o \gpio_e12__core__o - connect \gpio_e12__core__oe \gpio_e12__core__oe - connect \gpio_e12__pad__i \gpio_e12__pad__i - connect \gpio_e12__pad__o \gpio_e12__pad__o - connect \gpio_e12__pad__oe \gpio_e12__pad__oe - connect \gpio_e13__core__i \gpio_e13__core__i - connect \gpio_e13__core__o \gpio_e13__core__o - connect \gpio_e13__core__oe \gpio_e13__core__oe - connect \gpio_e13__pad__i \gpio_e13__pad__i - connect \gpio_e13__pad__o \gpio_e13__pad__o - connect \gpio_e13__pad__oe \gpio_e13__pad__oe - connect \gpio_e14__core__i \gpio_e14__core__i - connect \gpio_e14__core__o \gpio_e14__core__o - connect \gpio_e14__core__oe \gpio_e14__core__oe - connect \gpio_e14__pad__i \gpio_e14__pad__i - connect \gpio_e14__pad__o \gpio_e14__pad__o - connect \gpio_e14__pad__oe \gpio_e14__pad__oe - connect \gpio_e15__core__i \gpio_e15__core__i - connect \gpio_e15__core__o \gpio_e15__core__o - connect \gpio_e15__core__oe \gpio_e15__core__oe - connect \gpio_e15__pad__i \gpio_e15__pad__i - connect \gpio_e15__pad__o \gpio_e15__pad__o - connect \gpio_e15__pad__oe \gpio_e15__pad__oe - connect \gpio_e8__core__i \gpio_e8__core__i - connect \gpio_e8__core__o \gpio_e8__core__o - connect \gpio_e8__core__oe \gpio_e8__core__oe - connect \gpio_e8__pad__i \gpio_e8__pad__i - connect \gpio_e8__pad__o \gpio_e8__pad__o - connect \gpio_e8__pad__oe \gpio_e8__pad__oe - connect \gpio_e9__core__i \gpio_e9__core__i - connect \gpio_e9__core__o \gpio_e9__core__o - connect \gpio_e9__core__oe \gpio_e9__core__oe - connect \gpio_e9__pad__i \gpio_e9__pad__i - connect \gpio_e9__pad__o \gpio_e9__pad__o - connect \gpio_e9__pad__oe \gpio_e9__pad__oe - connect \gpio_s0__core__i \gpio_s0__core__i - connect \gpio_s0__core__o \gpio_s0__core__o - connect \gpio_s0__core__oe \gpio_s0__core__oe - connect \gpio_s0__pad__i \gpio_s0__pad__i - connect \gpio_s0__pad__o \gpio_s0__pad__o - connect \gpio_s0__pad__oe \gpio_s0__pad__oe - connect \gpio_s1__core__i \gpio_s1__core__i - connect \gpio_s1__core__o \gpio_s1__core__o - connect \gpio_s1__core__oe \gpio_s1__core__oe - connect \gpio_s1__pad__i \gpio_s1__pad__i - connect \gpio_s1__pad__o \gpio_s1__pad__o - connect \gpio_s1__pad__oe \gpio_s1__pad__oe - connect \gpio_s2__core__i \gpio_s2__core__i - connect \gpio_s2__core__o \gpio_s2__core__o - connect \gpio_s2__core__oe \gpio_s2__core__oe - connect \gpio_s2__pad__i \gpio_s2__pad__i - connect \gpio_s2__pad__o \gpio_s2__pad__o - connect \gpio_s2__pad__oe \gpio_s2__pad__oe - connect \gpio_s3__core__i \gpio_s3__core__i - connect \gpio_s3__core__o \gpio_s3__core__o - connect \gpio_s3__core__oe \gpio_s3__core__oe - connect \gpio_s3__pad__i \gpio_s3__pad__i - connect \gpio_s3__pad__o \gpio_s3__pad__o - connect \gpio_s3__pad__oe \gpio_s3__pad__oe - connect \gpio_s4__core__i \gpio_s4__core__i - connect \gpio_s4__core__o \gpio_s4__core__o - connect \gpio_s4__core__oe \gpio_s4__core__oe - connect \gpio_s4__pad__i \gpio_s4__pad__i - connect \gpio_s4__pad__o \gpio_s4__pad__o - connect \gpio_s4__pad__oe \gpio_s4__pad__oe - connect \gpio_s5__core__i \gpio_s5__core__i - connect \gpio_s5__core__o \gpio_s5__core__o - connect \gpio_s5__core__oe \gpio_s5__core__oe - connect \gpio_s5__pad__i \gpio_s5__pad__i - connect \gpio_s5__pad__o \gpio_s5__pad__o - connect \gpio_s5__pad__oe \gpio_s5__pad__oe - connect \gpio_s6__core__i \gpio_s6__core__i - connect \gpio_s6__core__o \gpio_s6__core__o - connect \gpio_s6__core__oe \gpio_s6__core__oe - connect \gpio_s6__pad__i \gpio_s6__pad__i - connect \gpio_s6__pad__o \gpio_s6__pad__o - connect \gpio_s6__pad__oe \gpio_s6__pad__oe - connect \gpio_s7__core__i \gpio_s7__core__i - connect \gpio_s7__core__o \gpio_s7__core__o - connect \gpio_s7__core__oe \gpio_s7__core__oe - connect \gpio_s7__pad__i \gpio_s7__pad__i - connect \gpio_s7__pad__o \gpio_s7__pad__o - connect \gpio_s7__pad__oe \gpio_s7__pad__oe - connect \ibus__ack \ibus__ack - connect \ibus__adr \ibus__adr - connect \ibus__cyc \ibus__cyc - connect \ibus__dat_r \ibus__dat_r - connect \ibus__err \ibus__err - connect \ibus__sel \ibus__sel - connect \ibus__stb \ibus__stb - connect \icp_wb__ack \icp_wb__ack - connect \icp_wb__adr \icp_wb__adr - connect \icp_wb__cyc \icp_wb__cyc - connect \icp_wb__dat_r \icp_wb__dat_r - connect \icp_wb__dat_w \icp_wb__dat_w - connect \icp_wb__sel \icp_wb__sel - connect \icp_wb__stb \icp_wb__stb - connect \icp_wb__we \icp_wb__we - connect \ics_wb__ack \ics_wb__ack - connect \ics_wb__adr \ics_wb__adr - connect \ics_wb__cyc \ics_wb__cyc - connect \ics_wb__dat_r \ics_wb__dat_r - connect \ics_wb__dat_w \ics_wb__dat_w - connect \ics_wb__stb \ics_wb__stb - connect \ics_wb__we \ics_wb__we - connect \int_level_i \int_level_i - connect \jtag_wb__ack \jtag_wb__ack - connect \jtag_wb__adr \jtag_wb__adr - connect \jtag_wb__cyc \jtag_wb__cyc - connect \jtag_wb__dat_r \jtag_wb__dat_r - connect \jtag_wb__dat_w \jtag_wb__dat_w - connect \jtag_wb__sel \jtag_wb__sel - connect \jtag_wb__stb \jtag_wb__stb - connect \jtag_wb__we \jtag_wb__we - connect \mspi0_clk__core__o \mspi0_clk__core__o - connect \mspi0_clk__pad__o \mspi0_clk__pad__o - connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o - connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o - connect \mspi0_miso__core__i \mspi0_miso__core__i - connect \mspi0_miso__pad__i \mspi0_miso__pad__i - connect \mspi0_mosi__core__o \mspi0_mosi__core__o - connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o - connect \mtwi_scl__core__o \mtwi_scl__core__o - connect \mtwi_scl__pad__o \mtwi_scl__pad__o - connect \mtwi_sda__core__i \mtwi_sda__core__i - connect \mtwi_sda__core__o \mtwi_sda__core__o - connect \mtwi_sda__core__oe \mtwi_sda__core__oe - connect \mtwi_sda__pad__i \mtwi_sda__pad__i - connect \mtwi_sda__pad__o \mtwi_sda__pad__o - connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe - connect \pc_i \pc_i - connect \pc_i_ok \pc_i_ok - connect \pc_o \pc_o - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o - connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe - connect \sdr_a_0__core__o \sdr_a_0__core__o - connect \sdr_a_0__pad__o \sdr_a_0__pad__o - connect \sdr_a_10__core__o \sdr_a_10__core__o - connect \sdr_a_10__pad__o \sdr_a_10__pad__o - connect \sdr_a_11__core__o \sdr_a_11__core__o - connect \sdr_a_11__pad__o \sdr_a_11__pad__o - connect \sdr_a_12__core__o \sdr_a_12__core__o - connect \sdr_a_12__pad__o \sdr_a_12__pad__o - connect \sdr_a_1__core__o \sdr_a_1__core__o - connect \sdr_a_1__pad__o \sdr_a_1__pad__o - connect \sdr_a_2__core__o \sdr_a_2__core__o - connect \sdr_a_2__pad__o \sdr_a_2__pad__o - connect \sdr_a_3__core__o \sdr_a_3__core__o - connect \sdr_a_3__pad__o \sdr_a_3__pad__o - connect \sdr_a_4__core__o \sdr_a_4__core__o - connect \sdr_a_4__pad__o \sdr_a_4__pad__o - connect \sdr_a_5__core__o \sdr_a_5__core__o - connect \sdr_a_5__pad__o \sdr_a_5__pad__o - connect \sdr_a_6__core__o \sdr_a_6__core__o - connect \sdr_a_6__pad__o \sdr_a_6__pad__o - connect \sdr_a_7__core__o \sdr_a_7__core__o - connect \sdr_a_7__pad__o \sdr_a_7__pad__o - connect \sdr_a_8__core__o \sdr_a_8__core__o - connect \sdr_a_8__pad__o \sdr_a_8__pad__o - connect \sdr_a_9__core__o \sdr_a_9__core__o - connect \sdr_a_9__pad__o \sdr_a_9__pad__o - connect \sdr_ba_0__core__o \sdr_ba_0__core__o - connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o - connect \sdr_ba_1__core__o \sdr_ba_1__core__o - connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o - connect \sdr_cas_n__core__o \sdr_cas_n__core__o - connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o - connect \sdr_cke__core__o \sdr_cke__core__o - connect \sdr_cke__pad__o \sdr_cke__pad__o - connect \sdr_clock__core__o \sdr_clock__core__o - connect \sdr_clock__pad__o \sdr_clock__pad__o - connect \sdr_cs_n__core__o \sdr_cs_n__core__o - connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o - connect \sdr_dm_0__core__o \sdr_dm_0__core__o - connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o - connect \sdr_dm_1__core__i \sdr_dm_1__core__i - connect \sdr_dm_1__core__o \sdr_dm_1__core__o - connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe - connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i - connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o - connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe - connect \sdr_dq_0__core__i \sdr_dq_0__core__i - connect \sdr_dq_0__core__o \sdr_dq_0__core__o - connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe - connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i - connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o - connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe - connect \sdr_dq_10__core__i \sdr_dq_10__core__i - connect \sdr_dq_10__core__o \sdr_dq_10__core__o - connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe - connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i - connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o - connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe - connect \sdr_dq_11__core__i \sdr_dq_11__core__i - connect \sdr_dq_11__core__o \sdr_dq_11__core__o - connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe - connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i - connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o - connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe - connect \sdr_dq_12__core__i \sdr_dq_12__core__i - connect \sdr_dq_12__core__o \sdr_dq_12__core__o - connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe - connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i - connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o - connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe - connect \sdr_dq_13__core__i \sdr_dq_13__core__i - connect \sdr_dq_13__core__o \sdr_dq_13__core__o - connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe - connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i - connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o - connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe - connect \sdr_dq_14__core__i \sdr_dq_14__core__i - connect \sdr_dq_14__core__o \sdr_dq_14__core__o - connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe - connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i - connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o - connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe - connect \sdr_dq_15__core__i \sdr_dq_15__core__i - connect \sdr_dq_15__core__o \sdr_dq_15__core__o - connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe - connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i - connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o - connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe - connect \sdr_dq_1__core__i \sdr_dq_1__core__i - connect \sdr_dq_1__core__o \sdr_dq_1__core__o - connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe - connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i - connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o - connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe - connect \sdr_dq_2__core__i \sdr_dq_2__core__i - connect \sdr_dq_2__core__o \sdr_dq_2__core__o - connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe - connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i - connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o - connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe - connect \sdr_dq_3__core__i \sdr_dq_3__core__i - connect \sdr_dq_3__core__o \sdr_dq_3__core__o - connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe - connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i - connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o - connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe - connect \sdr_dq_4__core__i \sdr_dq_4__core__i - connect \sdr_dq_4__core__o \sdr_dq_4__core__o - connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe - connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i - connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o - connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe - connect \sdr_dq_5__core__i \sdr_dq_5__core__i - connect \sdr_dq_5__core__o \sdr_dq_5__core__o - connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe - connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i - connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o - connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe - connect \sdr_dq_6__core__i \sdr_dq_6__core__i - connect \sdr_dq_6__core__o \sdr_dq_6__core__o - connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe - connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i - connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o - connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe - connect \sdr_dq_7__core__i \sdr_dq_7__core__i - connect \sdr_dq_7__core__o \sdr_dq_7__core__o - connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe - connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i - connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o - connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe - connect \sdr_dq_8__core__i \sdr_dq_8__core__i - connect \sdr_dq_8__core__o \sdr_dq_8__core__o - connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe - connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i - connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o - connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe - connect \sdr_dq_9__core__i \sdr_dq_9__core__i - connect \sdr_dq_9__core__o \sdr_dq_9__core__o - connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe - connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i - connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o - connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe - connect \sdr_ras_n__core__o \sdr_ras_n__core__o - connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o - connect \sdr_we_n__core__o \sdr_we_n__core__o - connect \sdr_we_n__pad__o \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + cell $pos $pos$libresoc.v:42386$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $extend$libresoc.v:42386$977_Y + connect \Y $pos$libresoc.v:42386$978_Y + end + attribute \src "libresoc.v:42281.7-42281.20" + process $proc$libresoc.v:42281$982 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42387.3-42400.6" + process $proc$libresoc.v:42387$979 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:42388.5-42388.29" + switch \initial + attribute \src "libresoc.v:42388.9-42388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:377" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\reg_o[4:0] \$3 [4:0] + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o[4:0] 5'00000 + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o $0\reg_o[4:0] + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:42401.3-42420.6" + process $proc$libresoc.v:42401$980 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:42402.5-42402.29" + switch \initial + attribute \src "libresoc.v:42402.9-42402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o[2:0] 3'001 + case + assign $2\fast_o[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o[2:0] 3'100 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:42421.3-42440.6" + process $proc$libresoc.v:42421$981 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:42422.5-42422.29" + switch \initial + attribute \src "libresoc.v:42422.9-42422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o_ok[0:0] 1'1 + case + assign $2\fast_o_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:42385$976_Y + connect \$3 $pos$libresoc.v:42386$978_Y +end +attribute \src "libresoc.v:42445.1-42579.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:42446.7-42446.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42537.3-42557.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:42558.3-42578.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:42537.3-42557.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:42558.3-42578.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:42537.3-42557.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:42558.3-42578.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 4 \OE + attribute \src "libresoc.v:42446.7-42446.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:170" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:445" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:42446.7-42446.20" + process $proc$libresoc.v:42446$985 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42537.3-42557.6" + process $proc$libresoc.v:42537$983 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:42538.5-42538.29" + switch \initial + attribute \src "libresoc.v:42538.9-42538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:42558.3-42578.6" + process $proc$libresoc.v:42558$984 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:42559.5-42559.29" + switch \initial + attribute \src "libresoc.v:42559.9-42559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] end - connect \clksel_pllclk_rst \rst - connect \pll_clk_24_i \clksel_clk_24_i - connect \clksel_clk_24_i \clk - connect \clksel_pllclk_clk \pll_clk_pll_o - connect \ti_coresync_clk \clk end -attribute \src "libresoc.v:183017.1-186895.10" +attribute \src "libresoc.v:42583.1-42637.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti" +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" -module \ti - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $0\core_asmcode$next[7:0]$13512 - attribute \src "libresoc.v:185176.3-185177.41" - wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:186638.3-186674.6" - wire $0\core_bigendian_i$10$next[0:0]$13794 - attribute \src "libresoc.v:185172.3-185173.57" - wire $0\core_bigendian_i$10[0:0]$13333 - attribute \src "libresoc.v:183160.7-183160.35" - wire $0\core_bigendian_i$10[0:0]$13825 - attribute \src "libresoc.v:186336.3-186348.6" - wire width 4 $0\core_cia__ren[3:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13513 - attribute \src "libresoc.v:185244.3-185245.53" - wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13514 - attribute \src "libresoc.v:185288.3-185289.57" - wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13515 - attribute \src "libresoc.v:185290.3-185291.63" - wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13516 - attribute \src "libresoc.v:185292.3-185293.57" - wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$13517 - attribute \src "libresoc.v:185270.3-185271.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13386 - attribute \src "libresoc.v:183186.7-183186.44" - wire $0\core_core_core_exc_$signal$3[0:0]$13833 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$13518 - attribute \src "libresoc.v:185272.3-185273.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13388 - attribute \src "libresoc.v:183190.7-183190.44" - wire $0\core_core_core_exc_$signal$4[0:0]$13835 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$13519 - attribute \src "libresoc.v:185276.3-185277.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13392 - attribute \src "libresoc.v:183194.7-183194.44" - wire $0\core_core_core_exc_$signal$5[0:0]$13837 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$13520 - attribute \src "libresoc.v:185278.3-185279.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13394 - attribute \src "libresoc.v:183198.7-183198.44" - wire $0\core_core_core_exc_$signal$6[0:0]$13839 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$13521 - attribute \src "libresoc.v:185280.3-185281.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13396 - attribute \src "libresoc.v:183202.7-183202.44" - wire $0\core_core_core_exc_$signal$7[0:0]$13841 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$13522 - attribute \src "libresoc.v:185282.3-185283.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13398 - attribute \src "libresoc.v:183206.7-183206.44" - wire $0\core_core_core_exc_$signal$8[0:0]$13843 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$13523 - attribute \src "libresoc.v:185284.3-185285.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13400 - attribute \src "libresoc.v:183210.7-183210.44" - wire $0\core_core_core_exc_$signal$9[0:0]$13845 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_exc_$signal$next[0:0]$13524 - attribute \src "libresoc.v:185268.3-185269.71" - wire $0\core_core_core_exc_$signal[0:0]$13384 - attribute \src "libresoc.v:183184.7-183184.42" - wire $0\core_core_core_exc_$signal[0:0]$13831 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 12 $0\core_core_core_fn_unit$next[11:0]$13525 - attribute \src "libresoc.v:185250.3-185251.61" - wire width 12 $0\core_core_core_fn_unit[11:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13526 - attribute \src "libresoc.v:185264.3-185265.69" - wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13527 - attribute \src "libresoc.v:185246.3-185247.55" - wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$13528 - attribute \src "libresoc.v:185248.3-185249.65" - wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_is_32bit$next[0:0]$13529 - attribute \src "libresoc.v:185298.3-185299.63" - wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $0\core_core_core_msr$next[63:0]$13530 - attribute \src "libresoc.v:185242.3-185243.53" - wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_oe$next[0:0]$13531 - attribute \src "libresoc.v:185260.3-185261.51" - wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_oe_ok$next[0:0]$13532 - attribute \src "libresoc.v:185262.3-185263.57" - wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_rc$next[0:0]$13533 - attribute \src "libresoc.v:185256.3-185257.51" - wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_core_rc_ok$next[0:0]$13534 - attribute \src "libresoc.v:185258.3-185259.57" - wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$13535 - attribute \src "libresoc.v:185286.3-185287.63" - wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$13536 - attribute \src "libresoc.v:185266.3-185267.63" - wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_cr_in1$next[2:0]$13537 - attribute \src "libresoc.v:185226.3-185227.49" - wire width 3 $0\core_core_cr_in1[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_cr_in1_ok$next[0:0]$13538 - attribute \src "libresoc.v:185228.3-185229.55" - wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_cr_in2$1$next[2:0]$13539 - attribute \src "libresoc.v:185234.3-185235.55" - wire width 3 $0\core_core_cr_in2$1[2:0]$13365 - attribute \src "libresoc.v:183365.13-183365.40" - wire width 3 $0\core_core_cr_in2$1[2:0]$13862 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_cr_in2$next[2:0]$13540 - attribute \src "libresoc.v:185230.3-185231.49" - wire width 3 $0\core_core_cr_in2[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$13541 - attribute \src "libresoc.v:185236.3-185237.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13367 - attribute \src "libresoc.v:183373.7-183373.37" - wire $0\core_core_cr_in2_ok$2[0:0]$13865 - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_cr_in2_ok$next[0:0]$13542 - attribute \src "libresoc.v:185232.3-185233.55" - wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_cr_out$next[2:0]$13543 - attribute \src "libresoc.v:185238.3-185239.49" - wire width 3 $0\core_core_cr_out[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_cr_wr_ok$next[0:0]$13544 - attribute \src "libresoc.v:185294.3-185295.53" - wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $0\core_core_ea$next[4:0]$13545 - attribute \src "libresoc.v:185182.3-185183.41" - wire width 5 $0\core_core_ea[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_fast1$next[2:0]$13546 - attribute \src "libresoc.v:185210.3-185211.47" - wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_fast1_ok$next[0:0]$13547 - attribute \src "libresoc.v:185212.3-185213.53" - wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_fast2$next[2:0]$13548 - attribute \src "libresoc.v:185214.3-185215.47" - wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_fast2_ok$next[0:0]$13549 - attribute \src "libresoc.v:185216.3-185217.53" - wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_fasto1$next[2:0]$13550 - attribute \src "libresoc.v:185218.3-185219.49" - wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_fasto2$next[2:0]$13551 - attribute \src "libresoc.v:185222.3-185223.49" - wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_lk$next[0:0]$13552 - attribute \src "libresoc.v:185254.3-185255.41" - wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $0\core_core_pc$next[63:0]$13433 - attribute \src "libresoc.v:185156.3-185157.41" - wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $0\core_core_reg1$next[4:0]$13553 - attribute \src "libresoc.v:185186.3-185187.45" - wire width 5 $0\core_core_reg1[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_reg1_ok$next[0:0]$13554 - attribute \src "libresoc.v:185188.3-185189.51" - wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $0\core_core_reg2$next[4:0]$13555 - attribute \src "libresoc.v:185190.3-185191.45" - wire width 5 $0\core_core_reg2[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_reg2_ok$next[0:0]$13556 - attribute \src "libresoc.v:185192.3-185193.51" - wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $0\core_core_reg3$next[4:0]$13557 - attribute \src "libresoc.v:185194.3-185195.45" - wire width 5 $0\core_core_reg3[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_reg3_ok$next[0:0]$13558 - attribute \src "libresoc.v:185196.3-185197.51" - wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $0\core_core_rego$next[4:0]$13559 - attribute \src "libresoc.v:185178.3-185179.45" - wire width 5 $0\core_core_rego[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $0\core_core_spr1$next[9:0]$13560 - attribute \src "libresoc.v:185202.3-185203.45" - wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_core_spr1_ok$next[0:0]$13561 - attribute \src "libresoc.v:185204.3-185205.51" - wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $0\core_core_spro$next[9:0]$13562 - attribute \src "libresoc.v:185198.3-185199.45" - wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $0\core_core_xer_in$next[2:0]$13563 - attribute \src "libresoc.v:185206.3-185207.49" - wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_cr_out_ok$next[0:0]$13564 - attribute \src "libresoc.v:185240.3-185241.45" - wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:186370.3-186390.6" - wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $0\core_dec$next[63:0]$13434 - attribute \src "libresoc.v:185162.3-185163.33" - wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:186034.3-186043.6" - wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:186044.3-186053.6" - wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_ea_ok$next[0:0]$13565 - attribute \src "libresoc.v:185184.3-185185.37" - wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire $0\core_eint$next[0:0]$13435 - attribute \src "libresoc.v:185160.3-185161.35" - wire $0\core_eint[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_fasto1_ok$next[0:0]$13566 - attribute \src "libresoc.v:185220.3-185221.45" - wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_fasto2_ok$next[0:0]$13567 - attribute \src "libresoc.v:185224.3-185225.45" - wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:186083.3-186092.6" - wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:186122.3-186131.6" - wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:186230.3-186244.6" - wire width 3 $0\core_issue__addr$11[2:0]$13483 - attribute \src "libresoc.v:186161.3-186175.6" - wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:186260.3-186274.6" - wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:186176.3-186190.6" - wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:186245.3-186259.6" - wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:186023.3-186033.6" - wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:186003.3-186022.6" - wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $0\core_msr$next[63:0]$13436 - attribute \src "libresoc.v:185158.3-185159.33" - wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:186391.3-186406.6" - wire width 4 $0\core_msr__ren[3:0] - attribute \src "libresoc.v:186601.3-186637.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13788 - attribute \src "libresoc.v:185174.3-185175.47" - wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_rego_ok$next[0:0]$13568 - attribute \src "libresoc.v:185180.3-185181.41" - wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_spro_ok$next[0:0]$13569 - attribute \src "libresoc.v:185200.3-185201.41" - wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:186838.3-186856.6" - wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:186349.3-186369.6" - wire width 4 $0\core_wen[3:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $0\core_xer_out$next[0:0]$13570 - attribute \src "libresoc.v:185208.3-185209.41" - wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:185304.3-185305.43" - wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:186093.3-186101.6" - wire $0\d_cr_delay$next[0:0]$13465 - attribute \src "libresoc.v:185318.3-185319.37" - wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:186054.3-186062.6" - wire $0\d_reg_delay$next[0:0]$13459 - attribute \src "libresoc.v:185152.3-185153.39" - wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:186132.3-186140.6" - wire $0\d_xer_delay$next[0:0]$13471 - attribute \src "libresoc.v:185296.3-185297.39" - wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:186857.3-186875.6" - wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:186112.3-186121.6" - wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:186102.3-186111.6" - wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:186073.3-186082.6" - wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:186063.3-186072.6" - wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:186151.3-186160.6" - wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:186141.3-186150.6" - wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:185889.3-185897.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13421 - attribute \src "libresoc.v:185322.3-185323.45" - wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:186407.3-186415.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13504 - attribute \src "libresoc.v:185314.3-185315.39" - wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:185898.3-185906.6" - wire $0\dbg_dmi_req_i$next[0:0]$13424 - attribute \src "libresoc.v:185320.3-185321.43" - wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:186302.3-186310.6" - wire $0\dbg_dmi_we_i$next[0:0]$13493 - attribute \src "libresoc.v:185316.3-185317.41" - wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:186275.3-186290.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13488 - attribute \src "libresoc.v:185252.3-185253.41" - wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:186582.3-186590.6" - wire $0\dec2_cur_eint$next[0:0]$13782 - attribute \src "libresoc.v:185308.3-185309.43" - wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:185907.3-185927.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13427 - attribute \src "libresoc.v:185164.3-185165.41" - wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:186741.3-186761.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13803 - attribute \src "libresoc.v:185170.3-185171.39" - wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:185928.3-185946.6" - wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:186591.3-186600.6" - wire width 2 $0\delay$next[1:0]$13785 - attribute \src "libresoc.v:185306.3-185307.27" - wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:186191.3-186218.6" - wire width 2 $0\fsm_state$133$next[1:0]$13478 - attribute \src "libresoc.v:185274.3-185275.45" - wire width 2 $0\fsm_state$133[1:0]$13390 - attribute \src "libresoc.v:184350.13-184350.35" - wire width 2 $0\fsm_state$133[1:0]$13914 - attribute \src "libresoc.v:186792.3-186837.6" - wire width 2 $0\fsm_state$next[1:0]$13814 - attribute \src "libresoc.v:185166.3-185167.35" - wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:185979.3-186002.6" - wire width 32 $0\ilatch$next[31:0]$13450 - attribute \src "libresoc.v:185154.3-185155.29" - wire width 32 $0\ilatch[31:0] - attribute \src "libresoc.v:186675.3-186690.6" - wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186691.3-186715.6" - wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186716.3-186740.6" - wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:183018.7-183018.20" +module \dec_rc + attribute \src "libresoc.v:42584.7-42584.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186564.3-186572.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13776 - attribute \src "libresoc.v:185312.3-185313.49" - wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:186573.3-186581.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13779 - attribute \src "libresoc.v:185310.3-185311.47" - wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:186762.3-186791.6" - wire $0\msr_read$next[0:0]$13808 - attribute \src "libresoc.v:185168.3-185169.33" - wire $0\msr_read[0:0] - attribute \src "libresoc.v:186219.3-186229.6" - wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:186291.3-186301.6" - wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:186320.3-186335.6" - wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:186416.3-186440.6" - wire $0\pc_changed$next[0:0]$13507 - attribute \src "libresoc.v:185300.3-185301.37" - wire $0\pc_changed[0:0] - attribute \src "libresoc.v:186311.3-186319.6" - wire $0\pc_ok_delay$next[0:0]$13496 - attribute \src "libresoc.v:185302.3-185303.39" - wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $1\core_asmcode$next[7:0]$13571 - attribute \src "libresoc.v:183154.13-183154.33" - wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:186638.3-186674.6" - wire $1\core_bigendian_i$10$next[0:0]$13795 - attribute \src "libresoc.v:186336.3-186348.6" - wire width 4 $1\core_cia__ren[3:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $1\core_core_core_cia$next[63:0]$13572 - attribute \src "libresoc.v:183168.14-183168.55" - wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$13573 - attribute \src "libresoc.v:183172.13-183172.41" - wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$13574 - attribute \src "libresoc.v:183176.7-183176.37" - wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$13575 - attribute \src "libresoc.v:183180.13-183180.41" - wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$13576 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$13577 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$13578 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$13579 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$13580 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$13581 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$13582 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_exc_$signal$next[0:0]$13583 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 12 $1\core_core_core_fn_unit$next[11:0]$13584 - attribute \src "libresoc.v:183229.14-183229.46" - wire width 12 $1\core_core_core_fn_unit[11:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$13585 - attribute \src "libresoc.v:183237.13-183237.46" - wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 32 $1\core_core_core_insn$next[31:0]$13586 - attribute \src "libresoc.v:183241.14-183241.41" - wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$13587 - attribute \src "libresoc.v:183319.13-183319.45" - wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_is_32bit$next[0:0]$13588 - attribute \src "libresoc.v:183323.7-183323.37" - wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $1\core_core_core_msr$next[63:0]$13589 - attribute \src "libresoc.v:183327.14-183327.55" - wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_oe$next[0:0]$13590 - attribute \src "libresoc.v:183331.7-183331.31" - wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_oe_ok$next[0:0]$13591 - attribute \src "libresoc.v:183335.7-183335.34" - wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_rc$next[0:0]$13592 - attribute \src "libresoc.v:183339.7-183339.31" - wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_core_rc_ok$next[0:0]$13593 - attribute \src "libresoc.v:183343.7-183343.34" - wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$13594 - attribute \src "libresoc.v:183347.14-183347.48" - wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$13595 - attribute \src "libresoc.v:183351.13-183351.44" - wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_cr_in1$next[2:0]$13596 - attribute \src "libresoc.v:183355.13-183355.36" - wire width 3 $1\core_core_cr_in1[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_cr_in1_ok$next[0:0]$13597 - attribute \src "libresoc.v:183359.7-183359.33" - wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_cr_in2$1$next[2:0]$13598 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_cr_in2$next[2:0]$13599 - attribute \src "libresoc.v:183363.13-183363.36" - wire width 3 $1\core_core_cr_in2[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$13600 - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_cr_in2_ok$next[0:0]$13601 - attribute \src "libresoc.v:183371.7-183371.33" - wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_cr_out$next[2:0]$13602 - attribute \src "libresoc.v:183379.13-183379.36" - wire width 3 $1\core_core_cr_out[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_cr_wr_ok$next[0:0]$13603 - attribute \src "libresoc.v:183383.7-183383.32" - wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $1\core_core_ea$next[4:0]$13604 - attribute \src "libresoc.v:183387.13-183387.33" - wire width 5 $1\core_core_ea[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_fast1$next[2:0]$13605 - attribute \src "libresoc.v:183391.13-183391.35" - wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_fast1_ok$next[0:0]$13606 - attribute \src "libresoc.v:183395.7-183395.32" - wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_fast2$next[2:0]$13607 - attribute \src "libresoc.v:183399.13-183399.35" - wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_fast2_ok$next[0:0]$13608 - attribute \src "libresoc.v:183403.7-183403.32" - wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_fasto1$next[2:0]$13609 - attribute \src "libresoc.v:183407.13-183407.36" - wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_fasto2$next[2:0]$13610 - attribute \src "libresoc.v:183411.13-183411.36" - wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_lk$next[0:0]$13611 - attribute \src "libresoc.v:183415.7-183415.26" - wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $1\core_core_pc$next[63:0]$13437 - attribute \src "libresoc.v:183419.14-183419.49" - wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $1\core_core_reg1$next[4:0]$13612 - attribute \src "libresoc.v:183423.13-183423.35" - wire width 5 $1\core_core_reg1[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_reg1_ok$next[0:0]$13613 - attribute \src "libresoc.v:183427.7-183427.31" - wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $1\core_core_reg2$next[4:0]$13614 - attribute \src "libresoc.v:183431.13-183431.35" - wire width 5 $1\core_core_reg2[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_reg2_ok$next[0:0]$13615 - attribute \src "libresoc.v:183435.7-183435.31" - wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $1\core_core_reg3$next[4:0]$13616 - attribute \src "libresoc.v:183439.13-183439.35" - wire width 5 $1\core_core_reg3[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_reg3_ok$next[0:0]$13617 - attribute \src "libresoc.v:183443.7-183443.31" - wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $1\core_core_rego$next[4:0]$13618 - attribute \src "libresoc.v:183447.13-183447.35" - wire width 5 $1\core_core_rego[4:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $1\core_core_spr1$next[9:0]$13619 - attribute \src "libresoc.v:183562.13-183562.37" - wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_core_spr1_ok$next[0:0]$13620 - attribute \src "libresoc.v:183566.7-183566.31" - wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $1\core_core_spro$next[9:0]$13621 - attribute \src "libresoc.v:183681.13-183681.37" - wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $1\core_core_xer_in$next[2:0]$13622 - attribute \src "libresoc.v:183687.13-183687.36" - wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_cr_out_ok$next[0:0]$13623 - attribute \src "libresoc.v:183695.7-183695.28" - wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:186370.3-186390.6" - wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $1\core_dec$next[63:0]$13438 - attribute \src "libresoc.v:183709.14-183709.45" - wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:186034.3-186043.6" - wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:186044.3-186053.6" - wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_ea_ok$next[0:0]$13624 - attribute \src "libresoc.v:183719.7-183719.24" - wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire $1\core_eint$next[0:0]$13439 - attribute \src "libresoc.v:183723.7-183723.23" - wire $1\core_eint[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_fasto1_ok$next[0:0]$13625 - attribute \src "libresoc.v:183727.7-183727.28" - wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_fasto2_ok$next[0:0]$13626 - attribute \src "libresoc.v:183731.7-183731.28" - wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:186083.3-186092.6" - wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:186122.3-186131.6" - wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:186230.3-186244.6" - wire width 3 $1\core_issue__addr$11[2:0]$13484 - attribute \src "libresoc.v:186161.3-186175.6" - wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:186260.3-186274.6" - wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:186176.3-186190.6" - wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:186245.3-186259.6" - wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:186023.3-186033.6" - wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:186003.3-186022.6" - wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $1\core_msr$next[63:0]$13440 - attribute \src "libresoc.v:183759.14-183759.45" - wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:186391.3-186406.6" - wire width 4 $1\core_msr__ren[3:0] - attribute \src "libresoc.v:186601.3-186637.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13789 - attribute \src "libresoc.v:183767.14-183767.37" - wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_rego_ok$next[0:0]$13627 - attribute \src "libresoc.v:183771.7-183771.26" - wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_spro_ok$next[0:0]$13628 - attribute \src "libresoc.v:183775.7-183775.26" - wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:186838.3-186856.6" - wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:186349.3-186369.6" - wire width 4 $1\core_wen[3:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $1\core_xer_out$next[0:0]$13629 - attribute \src "libresoc.v:183787.7-183787.26" - wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:183793.7-183793.30" - wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:186093.3-186101.6" - wire $1\d_cr_delay$next[0:0]$13466 - attribute \src "libresoc.v:183799.7-183799.24" - wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:186054.3-186062.6" - wire $1\d_reg_delay$next[0:0]$13460 - attribute \src "libresoc.v:183803.7-183803.25" - wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:186132.3-186140.6" - wire $1\d_xer_delay$next[0:0]$13472 - attribute \src "libresoc.v:183807.7-183807.25" - wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:186857.3-186875.6" - wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:186112.3-186121.6" - wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:186102.3-186111.6" - wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:186073.3-186082.6" - wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:186063.3-186072.6" - wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:186151.3-186160.6" - wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:186141.3-186150.6" - wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:185889.3-185897.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13422 - attribute \src "libresoc.v:183843.13-183843.34" - wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:186407.3-186415.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13505 - attribute \src "libresoc.v:183847.14-183847.48" - wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:185898.3-185906.6" - wire $1\dbg_dmi_req_i$next[0:0]$13425 - attribute \src "libresoc.v:183853.7-183853.27" - wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:186302.3-186310.6" - wire $1\dbg_dmi_we_i$next[0:0]$13494 - attribute \src "libresoc.v:183857.7-183857.26" - wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:186275.3-186290.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13489 - attribute \src "libresoc.v:183911.14-183911.49" - wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:186582.3-186590.6" - wire $1\dec2_cur_eint$next[0:0]$13783 - attribute \src "libresoc.v:183915.7-183915.27" - wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:185907.3-185927.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13428 - attribute \src "libresoc.v:183919.14-183919.49" - wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:186741.3-186761.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13804 - attribute \src "libresoc.v:183923.14-183923.48" - wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:185928.3-185946.6" - wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:186591.3-186600.6" - wire width 2 $1\delay$next[1:0]$13786 - attribute \src "libresoc.v:184332.13-184332.25" - wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:186191.3-186218.6" - wire width 2 $1\fsm_state$133$next[1:0]$13479 - attribute \src "libresoc.v:186792.3-186837.6" - wire width 2 $1\fsm_state$next[1:0]$13815 - attribute \src "libresoc.v:184348.13-184348.29" - wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:185979.3-186002.6" - wire width 32 $1\ilatch$next[31:0]$13451 - attribute \src "libresoc.v:184592.14-184592.28" - wire width 32 $1\ilatch[31:0] - attribute \src "libresoc.v:186675.3-186690.6" - wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186691.3-186715.6" - wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186716.3-186740.6" - wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186564.3-186572.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13777 - attribute \src "libresoc.v:184610.7-184610.30" - wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:186573.3-186581.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13780 - attribute \src "libresoc.v:184618.14-184618.52" - wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:186762.3-186791.6" - wire $1\msr_read$next[0:0]$13809 - attribute \src "libresoc.v:184674.7-184674.22" - wire $1\msr_read[0:0] - attribute \src "libresoc.v:186219.3-186229.6" - wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:186291.3-186301.6" - wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:186320.3-186335.6" - wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:186416.3-186440.6" - wire $1\pc_changed$next[0:0]$13508 - attribute \src "libresoc.v:184702.7-184702.24" - wire $1\pc_changed[0:0] - attribute \src "libresoc.v:186311.3-186319.6" - wire $1\pc_ok_delay$next[0:0]$13497 - attribute \src "libresoc.v:184712.7-184712.25" - wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $2\core_asmcode$next[7:0]$13630 - attribute \src "libresoc.v:186638.3-186674.6" - wire $2\core_bigendian_i$10$next[0:0]$13796 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $2\core_core_core_cia$next[63:0]$13631 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$13632 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$13633 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$13634 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$13635 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$13636 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$13637 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$13638 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$13639 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$13640 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$13641 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_exc_$signal$next[0:0]$13642 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 12 $2\core_core_core_fn_unit$next[11:0]$13643 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$13644 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 32 $2\core_core_core_insn$next[31:0]$13645 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$13646 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_is_32bit$next[0:0]$13647 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $2\core_core_core_msr$next[63:0]$13648 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_oe$next[0:0]$13649 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_oe_ok$next[0:0]$13650 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_rc$next[0:0]$13651 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_core_rc_ok$next[0:0]$13652 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$13653 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$13654 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_cr_in1$next[2:0]$13655 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_cr_in1_ok$next[0:0]$13656 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_cr_in2$1$next[2:0]$13657 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_cr_in2$next[2:0]$13658 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$13659 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_cr_in2_ok$next[0:0]$13660 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_cr_out$next[2:0]$13661 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_cr_wr_ok$next[0:0]$13662 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $2\core_core_ea$next[4:0]$13663 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_fast1$next[2:0]$13664 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_fast1_ok$next[0:0]$13665 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_fast2$next[2:0]$13666 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_fast2_ok$next[0:0]$13667 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_fasto1$next[2:0]$13668 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_fasto2$next[2:0]$13669 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_lk$next[0:0]$13670 - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $2\core_core_pc$next[63:0]$13441 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $2\core_core_reg1$next[4:0]$13671 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_reg1_ok$next[0:0]$13672 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $2\core_core_reg2$next[4:0]$13673 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_reg2_ok$next[0:0]$13674 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $2\core_core_reg3$next[4:0]$13675 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_reg3_ok$next[0:0]$13676 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $2\core_core_rego$next[4:0]$13677 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $2\core_core_spr1$next[9:0]$13678 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_core_spr1_ok$next[0:0]$13679 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $2\core_core_spro$next[9:0]$13680 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $2\core_core_xer_in$next[2:0]$13681 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_cr_out_ok$next[0:0]$13682 - attribute \src "libresoc.v:186370.3-186390.6" - wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $2\core_dec$next[63:0]$13442 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_ea_ok$next[0:0]$13683 - attribute \src "libresoc.v:185947.3-185978.6" - wire $2\core_eint$next[0:0]$13443 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_fasto1_ok$next[0:0]$13684 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_fasto2_ok$next[0:0]$13685 - attribute \src "libresoc.v:186003.3-186022.6" - wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $2\core_msr$next[63:0]$13444 - attribute \src "libresoc.v:186391.3-186406.6" - wire width 4 $2\core_msr__ren[3:0] - attribute \src "libresoc.v:186601.3-186637.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13790 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_rego_ok$next[0:0]$13686 - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_spro_ok$next[0:0]$13687 - attribute \src "libresoc.v:186838.3-186856.6" - wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:186349.3-186369.6" - wire width 4 $2\core_wen[3:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $2\core_xer_out$next[0:0]$13688 - attribute \src "libresoc.v:186857.3-186875.6" - wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:186275.3-186290.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13490 - attribute \src "libresoc.v:185907.3-185927.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13429 - attribute \src "libresoc.v:186741.3-186761.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13805 - attribute \src "libresoc.v:185928.3-185946.6" - wire width 32 $2\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:186191.3-186218.6" - wire width 2 $2\fsm_state$133$next[1:0]$13480 - attribute \src "libresoc.v:186792.3-186837.6" - wire width 2 $2\fsm_state$next[1:0]$13816 - attribute \src "libresoc.v:185979.3-186002.6" - wire width 32 $2\ilatch$next[31:0]$13452 - attribute \src "libresoc.v:186675.3-186690.6" - wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186691.3-186715.6" - wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186716.3-186740.6" - wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186762.3-186791.6" - wire $2\msr_read$next[0:0]$13810 - attribute \src "libresoc.v:186320.3-186335.6" - wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:186416.3-186440.6" - wire $2\pc_changed$next[0:0]$13509 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $3\core_asmcode$next[7:0]$13689 - attribute \src "libresoc.v:186638.3-186674.6" - wire $3\core_bigendian_i$10$next[0:0]$13797 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $3\core_core_core_cia$next[63:0]$13690 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $3\core_core_core_cr_rd$next[7:0]$13691 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$13692 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $3\core_core_core_cr_wr$next[7:0]$13693 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$13694 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$13695 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$13696 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$13697 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$13698 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$13699 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$13700 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_exc_$signal$next[0:0]$13701 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 12 $3\core_core_core_fn_unit$next[11:0]$13702 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 2 $3\core_core_core_input_carry$next[1:0]$13703 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 32 $3\core_core_core_insn$next[31:0]$13704 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 7 $3\core_core_core_insn_type$next[6:0]$13705 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_is_32bit$next[0:0]$13706 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 64 $3\core_core_core_msr$next[63:0]$13707 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_oe$next[0:0]$13708 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_oe_ok$next[0:0]$13709 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_rc$next[0:0]$13710 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_core_rc_ok$next[0:0]$13711 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 13 $3\core_core_core_trapaddr$next[12:0]$13712 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 8 $3\core_core_core_traptype$next[7:0]$13713 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_cr_in1$next[2:0]$13714 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_cr_in1_ok$next[0:0]$13715 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_cr_in2$1$next[2:0]$13716 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_cr_in2$next[2:0]$13717 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$13718 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_cr_in2_ok$next[0:0]$13719 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_cr_out$next[2:0]$13720 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_cr_wr_ok$next[0:0]$13721 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $3\core_core_ea$next[4:0]$13722 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_fast1$next[2:0]$13723 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_fast1_ok$next[0:0]$13724 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_fast2$next[2:0]$13725 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_fast2_ok$next[0:0]$13726 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_fasto1$next[2:0]$13727 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_fasto2$next[2:0]$13728 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_lk$next[0:0]$13729 - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $3\core_core_pc$next[63:0]$13445 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $3\core_core_reg1$next[4:0]$13730 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_reg1_ok$next[0:0]$13731 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $3\core_core_reg2$next[4:0]$13732 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_reg2_ok$next[0:0]$13733 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $3\core_core_reg3$next[4:0]$13734 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_reg3_ok$next[0:0]$13735 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 5 $3\core_core_rego$next[4:0]$13736 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $3\core_core_spr1$next[9:0]$13737 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_core_spr1_ok$next[0:0]$13738 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 10 $3\core_core_spro$next[9:0]$13739 - attribute \src "libresoc.v:186441.3-186563.6" - wire width 3 $3\core_core_xer_in$next[2:0]$13740 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_cr_out_ok$next[0:0]$13741 - attribute \src "libresoc.v:186370.3-186390.6" - wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $3\core_dec$next[63:0]$13446 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_ea_ok$next[0:0]$13742 - attribute \src "libresoc.v:185947.3-185978.6" - wire $3\core_eint$next[0:0]$13447 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_fasto1_ok$next[0:0]$13743 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_fasto2_ok$next[0:0]$13744 - attribute \src "libresoc.v:185947.3-185978.6" - wire width 64 $3\core_msr$next[63:0]$13448 - attribute \src "libresoc.v:186601.3-186637.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13791 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_rego_ok$next[0:0]$13745 - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_spro_ok$next[0:0]$13746 - attribute \src "libresoc.v:186349.3-186369.6" - wire width 4 $3\core_wen[3:0] - attribute \src "libresoc.v:186441.3-186563.6" - wire $3\core_xer_out$next[0:0]$13747 - attribute \src "libresoc.v:185907.3-185927.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13430 - attribute \src "libresoc.v:186741.3-186761.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13806 - attribute \src "libresoc.v:186792.3-186837.6" - wire width 2 $3\fsm_state$next[1:0]$13817 - attribute \src "libresoc.v:185979.3-186002.6" - wire width 32 $3\ilatch$next[31:0]$13453 - attribute \src "libresoc.v:186691.3-186715.6" - wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186716.3-186740.6" - wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186762.3-186791.6" - wire $3\msr_read$next[0:0]$13811 - attribute \src "libresoc.v:186416.3-186440.6" - wire $3\pc_changed$next[0:0]$13510 - attribute \src "libresoc.v:186638.3-186674.6" - wire $4\core_bigendian_i$10$next[0:0]$13798 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_cr_rd_ok$next[0:0]$13748 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$3$next[0:0]$13749 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$4$next[0:0]$13750 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$5$next[0:0]$13751 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$6$next[0:0]$13752 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$7$next[0:0]$13753 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$8$next[0:0]$13754 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$9$next[0:0]$13755 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_exc_$signal$next[0:0]$13756 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_oe_ok$next[0:0]$13757 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_core_rc_ok$next[0:0]$13758 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_cr_in1_ok$next[0:0]$13759 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_cr_in2_ok$2$next[0:0]$13760 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_cr_in2_ok$next[0:0]$13761 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_cr_wr_ok$next[0:0]$13762 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_fast1_ok$next[0:0]$13763 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_fast2_ok$next[0:0]$13764 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_reg1_ok$next[0:0]$13765 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_reg2_ok$next[0:0]$13766 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_reg3_ok$next[0:0]$13767 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_core_spr1_ok$next[0:0]$13768 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_cr_out_ok$next[0:0]$13769 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_ea_ok$next[0:0]$13770 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_fasto1_ok$next[0:0]$13771 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_fasto2_ok$next[0:0]$13772 - attribute \src "libresoc.v:186601.3-186637.6" - wire width 32 $4\core_raw_insn_i$next[31:0]$13792 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_rego_ok$next[0:0]$13773 - attribute \src "libresoc.v:186441.3-186563.6" - wire $4\core_spro_ok$next[0:0]$13774 - attribute \src "libresoc.v:186792.3-186837.6" - wire width 2 $4\fsm_state$next[1:0]$13818 - attribute \src "libresoc.v:186762.3-186791.6" - wire $4\msr_read$next[0:0]$13812 - attribute \src "libresoc.v:186792.3-186837.6" - wire width 2 $5\fsm_state$next[1:0]$13819 - attribute \src "libresoc.v:185113.19-185113.115" - wire width 65 $add$libresoc.v:185113$13283_Y - attribute \src "libresoc.v:185121.18-185121.107" - wire width 65 $add$libresoc.v:185121$13291_Y - attribute \src "libresoc.v:185096.19-185096.102" - wire $and$libresoc.v:185096$13264_Y - attribute \src "libresoc.v:185100.19-185100.104" - wire $and$libresoc.v:185100$13268_Y - attribute \src "libresoc.v:185103.19-185103.104" - wire $and$libresoc.v:185103$13271_Y - attribute \src "libresoc.v:185120.18-185120.109" - wire $and$libresoc.v:185120$13290_Y - attribute \src "libresoc.v:185129.18-185129.101" - wire $and$libresoc.v:185129$13299_Y - attribute \src "libresoc.v:185130.18-185130.114" - wire width 4 $and$libresoc.v:185130$13300_Y - attribute \src "libresoc.v:185137.18-185137.101" - wire $and$libresoc.v:185137$13307_Y - attribute \src "libresoc.v:185140.18-185140.101" - wire $and$libresoc.v:185140$13310_Y - attribute \src "libresoc.v:185143.18-185143.101" - wire $and$libresoc.v:185143$13313_Y - attribute \src "libresoc.v:185146.18-185146.101" - wire $and$libresoc.v:185146$13316_Y - attribute \src "libresoc.v:185149.18-185149.101" - wire $and$libresoc.v:185149$13319_Y - attribute \src "libresoc.v:185110.19-185110.114" - wire width 64 $extend$libresoc.v:185110$13278_Y - attribute \src "libresoc.v:185111.19-185111.113" - wire width 64 $extend$libresoc.v:185111$13280_Y - attribute \src "libresoc.v:185105.19-185105.111" - wire width 7 $mul$libresoc.v:185105$13273_Y - attribute \src "libresoc.v:185107.19-185107.111" - wire width 7 $mul$libresoc.v:185107$13275_Y - attribute \src "libresoc.v:185109.19-185109.123" - wire $ne$libresoc.v:185109$13277_Y - attribute \src "libresoc.v:185114.18-185114.102" - wire $ne$libresoc.v:185114$13284_Y - attribute \src "libresoc.v:185118.18-185118.102" - wire $ne$libresoc.v:185118$13288_Y - attribute \src "libresoc.v:185095.18-185095.108" - wire $not$libresoc.v:185095$13263_Y - attribute \src "libresoc.v:185097.19-185097.107" - wire $not$libresoc.v:185097$13265_Y - attribute \src "libresoc.v:185098.19-185098.107" - wire $not$libresoc.v:185098$13266_Y - attribute \src "libresoc.v:185099.19-185099.109" - wire $not$libresoc.v:185099$13267_Y - attribute \src "libresoc.v:185101.19-185101.107" - wire $not$libresoc.v:185101$13269_Y - attribute \src "libresoc.v:185102.19-185102.109" - wire $not$libresoc.v:185102$13270_Y - attribute \src "libresoc.v:185104.19-185104.100" - wire $not$libresoc.v:185104$13272_Y - attribute \src "libresoc.v:185119.18-185119.103" - wire $not$libresoc.v:185119$13289_Y - attribute \src "libresoc.v:185122.18-185122.98" - wire $not$libresoc.v:185122$13292_Y - attribute \src "libresoc.v:185123.18-185123.106" - wire $not$libresoc.v:185123$13293_Y - attribute \src "libresoc.v:185124.18-185124.101" - wire $not$libresoc.v:185124$13294_Y - attribute \src "libresoc.v:185125.18-185125.106" - wire $not$libresoc.v:185125$13295_Y - attribute \src "libresoc.v:185126.18-185126.101" - wire $not$libresoc.v:185126$13296_Y - attribute \src "libresoc.v:185127.18-185127.106" - wire $not$libresoc.v:185127$13297_Y - attribute \src "libresoc.v:185128.18-185128.108" - wire $not$libresoc.v:185128$13298_Y - attribute \src "libresoc.v:185132.18-185132.106" - wire $not$libresoc.v:185132$13302_Y - attribute \src "libresoc.v:185133.18-185133.106" - wire $not$libresoc.v:185133$13303_Y - attribute \src "libresoc.v:185134.18-185134.106" - wire $not$libresoc.v:185134$13304_Y - attribute \src "libresoc.v:185135.18-185135.106" - wire $not$libresoc.v:185135$13305_Y - attribute \src "libresoc.v:185136.18-185136.108" - wire $not$libresoc.v:185136$13306_Y - attribute \src "libresoc.v:185138.18-185138.106" - wire $not$libresoc.v:185138$13308_Y - attribute \src "libresoc.v:185139.18-185139.108" - wire $not$libresoc.v:185139$13309_Y - attribute \src "libresoc.v:185141.18-185141.106" - wire $not$libresoc.v:185141$13311_Y - attribute \src "libresoc.v:185142.18-185142.108" - wire $not$libresoc.v:185142$13312_Y - attribute \src "libresoc.v:185144.18-185144.106" - wire $not$libresoc.v:185144$13314_Y - attribute \src "libresoc.v:185145.18-185145.108" - wire $not$libresoc.v:185145$13315_Y - attribute \src "libresoc.v:185147.18-185147.106" - wire $not$libresoc.v:185147$13317_Y - attribute \src "libresoc.v:185148.18-185148.108" - wire $not$libresoc.v:185148$13318_Y - attribute \src "libresoc.v:185150.18-185150.99" - wire $not$libresoc.v:185150$13320_Y - attribute \src "libresoc.v:185151.18-185151.106" - wire $not$libresoc.v:185151$13321_Y - attribute \src "libresoc.v:185116.18-185116.110" - wire $or$libresoc.v:185116$13286_Y - attribute \src "libresoc.v:185117.18-185117.100" - wire $or$libresoc.v:185117$13287_Y - attribute \src "libresoc.v:185110.19-185110.114" - wire width 64 $pos$libresoc.v:185110$13279_Y - attribute \src "libresoc.v:185111.19-185111.113" - wire width 64 $pos$libresoc.v:185111$13281_Y - attribute \src "libresoc.v:185131.18-185131.91" - wire $reduce_or$libresoc.v:185131$13301_Y - attribute \src "libresoc.v:185106.19-185106.42" - wire width 64 $shr$libresoc.v:185106$13274_Y - attribute \src "libresoc.v:185108.19-185108.42" - wire width 64 $shr$libresoc.v:185108$13276_Y - attribute \src "libresoc.v:185112.19-185112.115" - wire width 65 $sub$libresoc.v:185112$13282_Y - attribute \src "libresoc.v:185115.18-185115.101" - wire width 3 $sub$libresoc.v:185115$13285_Y - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + attribute \src "libresoc.v:42599.3-42617.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:42618.3-42636.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:42599.3-42617.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:42618.3-42636.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:450" + wire input 3 \Rc + attribute \src "libresoc.v:42584.7-42584.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:42584.7-42584.20" + process $proc$libresoc.v:42584$988 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42599.3-42617.6" + process $proc$libresoc.v:42599$986 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:42600.5-42600.29" + switch \initial + attribute \src "libresoc.v:42600.9-42600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:42618.3-42636.6" + process $proc$libresoc.v:42618$987 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:42619.5-42619.29" + switch \initial + attribute \src "libresoc.v:42619.9-42619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:42641.1-43020.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.imem" +attribute \generator "nMigen" +module \imem + attribute \src "libresoc.v:42972.3-42981.6" + wire $0\a_busy_o[0:0] + attribute \src "libresoc.v:42952.3-42971.6" + wire width 45 $0\f_badaddr_o$next[44:0]$1057 + attribute \src "libresoc.v:42783.3-42784.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "libresoc.v:42982.3-42999.6" + wire $0\f_busy_o[0:0] + attribute \src "libresoc.v:42929.3-42951.6" + wire $0\f_fetch_err_o$next[0:0]$1052 + attribute \src "libresoc.v:42785.3-42786.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "libresoc.v:43000.3-43017.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "libresoc.v:42906.3-42928.6" + wire width 45 $0\ibus__adr$next[44:0]$1047 + attribute \src "libresoc.v:42787.3-42788.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "libresoc.v:42797.3-42824.6" + wire $0\ibus__cyc$next[0:0]$1023 + attribute \src "libresoc.v:42795.3-42796.35" + wire $0\ibus__cyc[0:0] + attribute \src "libresoc.v:42853.3-42880.6" + wire width 8 $0\ibus__sel$next[7:0]$1035 + attribute \src "libresoc.v:42791.3-42792.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "libresoc.v:42825.3-42852.6" + wire $0\ibus__stb$next[0:0]$1029 + attribute \src "libresoc.v:42793.3-42794.35" + wire $0\ibus__stb[0:0] + attribute \src "libresoc.v:42881.3-42905.6" + wire width 64 $0\ibus_rdata$next[63:0]$1041 + attribute \src "libresoc.v:42789.3-42790.37" + wire width 64 $0\ibus_rdata[63:0] + attribute \src "libresoc.v:42642.7-42642.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:42972.3-42981.6" + wire $1\a_busy_o[0:0] + attribute \src "libresoc.v:42952.3-42971.6" + wire width 45 $1\f_badaddr_o$next[44:0]$1058 + attribute \src "libresoc.v:42706.14-42706.44" + wire width 45 $1\f_badaddr_o[44:0] + attribute \src "libresoc.v:42982.3-42999.6" + wire $1\f_busy_o[0:0] + attribute \src "libresoc.v:42929.3-42951.6" + wire $1\f_fetch_err_o$next[0:0]$1053 + attribute \src "libresoc.v:42713.7-42713.27" + wire $1\f_fetch_err_o[0:0] + attribute \src "libresoc.v:43000.3-43017.6" + wire width 64 $1\f_instr_o[63:0] + attribute \src "libresoc.v:42906.3-42928.6" + wire width 45 $1\ibus__adr$next[44:0]$1048 + attribute \src "libresoc.v:42727.14-42727.42" + wire width 45 $1\ibus__adr[44:0] + attribute \src "libresoc.v:42797.3-42824.6" + wire $1\ibus__cyc$next[0:0]$1024 + attribute \src "libresoc.v:42732.7-42732.23" + wire $1\ibus__cyc[0:0] + attribute \src "libresoc.v:42853.3-42880.6" + wire width 8 $1\ibus__sel$next[7:0]$1036 + attribute \src "libresoc.v:42741.13-42741.30" + wire width 8 $1\ibus__sel[7:0] + attribute \src "libresoc.v:42825.3-42852.6" + wire $1\ibus__stb$next[0:0]$1030 + attribute \src "libresoc.v:42746.7-42746.23" + wire $1\ibus__stb[0:0] + attribute \src "libresoc.v:42881.3-42905.6" + wire width 64 $1\ibus_rdata$next[63:0]$1042 + attribute \src "libresoc.v:42750.14-42750.47" + wire width 64 $1\ibus_rdata[63:0] + attribute \src "libresoc.v:42952.3-42971.6" + wire width 45 $2\f_badaddr_o$next[44:0]$1059 + attribute \src "libresoc.v:42982.3-42999.6" + wire $2\f_busy_o[0:0] + attribute \src "libresoc.v:42929.3-42951.6" + wire $2\f_fetch_err_o$next[0:0]$1054 + attribute \src "libresoc.v:43000.3-43017.6" + wire width 64 $2\f_instr_o[63:0] + attribute \src "libresoc.v:42906.3-42928.6" + wire width 45 $2\ibus__adr$next[44:0]$1049 + attribute \src "libresoc.v:42797.3-42824.6" + wire $2\ibus__cyc$next[0:0]$1025 + attribute \src "libresoc.v:42853.3-42880.6" + wire width 8 $2\ibus__sel$next[7:0]$1037 + attribute \src "libresoc.v:42825.3-42852.6" + wire $2\ibus__stb$next[0:0]$1031 + attribute \src "libresoc.v:42881.3-42905.6" + wire width 64 $2\ibus_rdata$next[63:0]$1043 + attribute \src "libresoc.v:42952.3-42971.6" + wire width 45 $3\f_badaddr_o$next[44:0]$1060 + attribute \src "libresoc.v:42929.3-42951.6" + wire $3\f_fetch_err_o$next[0:0]$1055 + attribute \src "libresoc.v:42906.3-42928.6" + wire width 45 $3\ibus__adr$next[44:0]$1050 + attribute \src "libresoc.v:42797.3-42824.6" + wire $3\ibus__cyc$next[0:0]$1026 + attribute \src "libresoc.v:42853.3-42880.6" + wire width 8 $3\ibus__sel$next[7:0]$1038 + attribute \src "libresoc.v:42825.3-42852.6" + wire $3\ibus__stb$next[0:0]$1032 + attribute \src "libresoc.v:42881.3-42905.6" + wire width 64 $3\ibus_rdata$next[63:0]$1044 + attribute \src "libresoc.v:42797.3-42824.6" + wire $4\ibus__cyc$next[0:0]$1027 + attribute \src "libresoc.v:42853.3-42880.6" + wire width 8 $4\ibus__sel$next[7:0]$1039 + attribute \src "libresoc.v:42825.3-42852.6" + wire $4\ibus__stb$next[0:0]$1033 + attribute \src "libresoc.v:42881.3-42905.6" + wire width 64 $4\ibus_rdata$next[63:0]$1045 + attribute \src "libresoc.v:42759.18-42759.110" + wire $and$libresoc.v:42759$991_Y + attribute \src "libresoc.v:42765.18-42765.110" + wire $and$libresoc.v:42765$997_Y + attribute \src "libresoc.v:42770.18-42770.110" + wire $and$libresoc.v:42770$1002_Y + attribute \src "libresoc.v:42773.17-42773.108" + wire $and$libresoc.v:42773$1005_Y + attribute \src "libresoc.v:42776.18-42776.110" + wire $and$libresoc.v:42776$1008_Y + attribute \src "libresoc.v:42777.18-42777.115" + wire $and$libresoc.v:42777$1009_Y + attribute \src "libresoc.v:42779.18-42779.115" + wire $and$libresoc.v:42779$1011_Y + attribute \src "libresoc.v:42758.18-42758.105" + wire $not$libresoc.v:42758$990_Y + attribute \src "libresoc.v:42761.18-42761.105" + wire $not$libresoc.v:42761$993_Y + attribute \src "libresoc.v:42762.17-42762.104" + wire $not$libresoc.v:42762$994_Y + attribute \src "libresoc.v:42764.18-42764.105" + wire $not$libresoc.v:42764$996_Y + attribute \src "libresoc.v:42767.18-42767.105" + wire $not$libresoc.v:42767$999_Y + attribute \src "libresoc.v:42769.18-42769.105" + wire $not$libresoc.v:42769$1001_Y + attribute \src "libresoc.v:42772.18-42772.105" + wire $not$libresoc.v:42772$1004_Y + attribute \src "libresoc.v:42775.18-42775.105" + wire $not$libresoc.v:42775$1007_Y + attribute \src "libresoc.v:42778.18-42778.105" + wire $not$libresoc.v:42778$1010_Y + attribute \src "libresoc.v:42780.18-42780.105" + wire $not$libresoc.v:42780$1012_Y + attribute \src "libresoc.v:42782.17-42782.104" + wire $not$libresoc.v:42782$1014_Y + attribute \src "libresoc.v:42757.17-42757.103" + wire $or$libresoc.v:42757$989_Y + attribute \src "libresoc.v:42760.18-42760.115" + wire $or$libresoc.v:42760$992_Y + attribute \src "libresoc.v:42763.18-42763.106" + wire $or$libresoc.v:42763$995_Y + attribute \src "libresoc.v:42766.18-42766.115" + wire $or$libresoc.v:42766$998_Y + attribute \src "libresoc.v:42768.18-42768.106" + wire $or$libresoc.v:42768$1000_Y + attribute \src "libresoc.v:42771.18-42771.115" + wire $or$libresoc.v:42771$1003_Y + attribute \src "libresoc.v:42774.18-42774.106" + wire $or$libresoc.v:42774$1006_Y + attribute \src "libresoc.v:42781.17-42781.114" + wire $or$libresoc.v:42781$1013_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 2 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire \a_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire input 3 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 15 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire output 5 \f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 output 6 \f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 4 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 14 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 8 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 13 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 10 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 12 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 \ibus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 11 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" + wire width 64 \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" + wire width 64 \ibus_rdata$next + attribute \src "libresoc.v:42642.7-42642.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire input 7 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42759$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$11 + connect \Y $and$libresoc.v:42759$991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42765$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$21 + connect \Y $and$libresoc.v:42765$997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42770$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$31 + connect \Y $and$libresoc.v:42770$1002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42773$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$1 + connect \Y $and$libresoc.v:42773$1005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:42776$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$41 + connect \Y $and$libresoc.v:42776$1008_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:42777$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:42777$1009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:42779$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:42779$1011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42758$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42758$990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:42761$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42761$993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42762$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42762$994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42764$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42764$996_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:42767$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42767$999_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42769$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42769$1001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:42772$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42772$1004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:42775$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:42775$1007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:42778$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:42778$1010_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:42780$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:42780$1012_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:42782$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:42782$1014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42757$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:42757$989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42760$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42760$992_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42763$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:42763$995_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42766$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42766$998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42768$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:42768$1000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42771$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42771$1003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42774$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:42774$1006_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:42781$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:42781$1013_Y + end + attribute \src "libresoc.v:42642.7-42642.20" + process $proc$libresoc.v:42642$1064 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:42706.14-42706.44" + process $proc$libresoc.v:42706$1065 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42713.7-42713.27" + process $proc$libresoc.v:42713$1066 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42727.14-42727.42" + process $proc$libresoc.v:42727$1067 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:42732.7-42732.23" + process $proc$libresoc.v:42732$1068 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42741.13-42741.30" + process $proc$libresoc.v:42741$1069 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:42746.7-42746.23" + process $proc$libresoc.v:42746$1070 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:42750.14-42750.47" + process $proc$libresoc.v:42750$1071 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42783.3-42784.39" + process $proc$libresoc.v:42783$1015 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:42785.3-42786.43" + process $proc$libresoc.v:42785$1016 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:42787.3-42788.35" + process $proc$libresoc.v:42787$1017 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:42789.3-42790.37" + process $proc$libresoc.v:42789$1018 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:42791.3-42792.35" + process $proc$libresoc.v:42791$1019 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:42793.3-42794.35" + process $proc$libresoc.v:42793$1020 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:42795.3-42796.35" + process $proc$libresoc.v:42795$1021 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:42797.3-42824.6" + process $proc$libresoc.v:42797$1022 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$1023 $4\ibus__cyc$next[0:0]$1027 + attribute \src "libresoc.v:42798.5-42798.29" + switch \initial + attribute \src "libresoc.v:42798.9-42798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$1024 $2\ibus__cyc$next[0:0]$1025 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$1025 $3\ibus__cyc$next[0:0]$1026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$1026 1'0 + case + assign $3\ibus__cyc$next[0:0]$1026 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__cyc$next[0:0]$1025 1'1 + case + assign $2\ibus__cyc$next[0:0]$1025 \ibus__cyc + end + case + assign $1\ibus__cyc$next[0:0]$1024 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__cyc$next[0:0]$1027 1'0 + case + assign $4\ibus__cyc$next[0:0]$1027 $1\ibus__cyc$next[0:0]$1024 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$1023 + end + attribute \src "libresoc.v:42825.3-42852.6" + process $proc$libresoc.v:42825$1028 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$1029 $4\ibus__stb$next[0:0]$1033 + attribute \src "libresoc.v:42826.5-42826.29" + switch \initial + attribute \src "libresoc.v:42826.9-42826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__stb$next[0:0]$1030 $2\ibus__stb$next[0:0]$1031 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__stb$next[0:0]$1031 $3\ibus__stb$next[0:0]$1032 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$1032 1'0 + case + assign $3\ibus__stb$next[0:0]$1032 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__stb$next[0:0]$1031 1'1 + case + assign $2\ibus__stb$next[0:0]$1031 \ibus__stb + end + case + assign $1\ibus__stb$next[0:0]$1030 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__stb$next[0:0]$1033 1'0 + case + assign $4\ibus__stb$next[0:0]$1033 $1\ibus__stb$next[0:0]$1030 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$1029 + end + attribute \src "libresoc.v:42853.3-42880.6" + process $proc$libresoc.v:42853$1034 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$1035 $4\ibus__sel$next[7:0]$1039 + attribute \src "libresoc.v:42854.5-42854.29" + switch \initial + attribute \src "libresoc.v:42854.9-42854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__sel$next[7:0]$1036 $2\ibus__sel$next[7:0]$1037 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__sel$next[7:0]$1037 $3\ibus__sel$next[7:0]$1038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$1038 8'00000000 + case + assign $3\ibus__sel$next[7:0]$1038 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__sel$next[7:0]$1037 8'11111111 + case + assign $2\ibus__sel$next[7:0]$1037 \ibus__sel + end + case + assign $1\ibus__sel$next[7:0]$1036 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__sel$next[7:0]$1039 8'00000000 + case + assign $4\ibus__sel$next[7:0]$1039 $1\ibus__sel$next[7:0]$1036 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$1035 + end + attribute \src "libresoc.v:42881.3-42905.6" + process $proc$libresoc.v:42881$1040 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$1041 $4\ibus_rdata$next[63:0]$1045 + attribute \src "libresoc.v:42882.5-42882.29" + switch \initial + attribute \src "libresoc.v:42882.9-42882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$1042 $2\ibus_rdata$next[63:0]$1043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$1043 $3\ibus_rdata$next[63:0]$1044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$1044 \ibus__dat_r + case + assign $3\ibus_rdata$next[63:0]$1044 \ibus_rdata + end + case + assign $2\ibus_rdata$next[63:0]$1043 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$1042 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus_rdata$next[63:0]$1045 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\ibus_rdata$next[63:0]$1045 $1\ibus_rdata$next[63:0]$1042 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$1041 + end + attribute \src "libresoc.v:42906.3-42928.6" + process $proc$libresoc.v:42906$1046 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$1047 $3\ibus__adr$next[44:0]$1050 + attribute \src "libresoc.v:42907.5-42907.29" + switch \initial + attribute \src "libresoc.v:42907.9-42907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__adr$next[44:0]$1048 $2\ibus__adr$next[44:0]$1049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\ibus__adr$next[44:0]$1049 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__adr$next[44:0]$1049 \a_pc_i [47:3] + case + assign $2\ibus__adr$next[44:0]$1049 \ibus__adr + end + case + assign $1\ibus__adr$next[44:0]$1048 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__adr$next[44:0]$1050 45'000000000000000000000000000000000000000000000 + case + assign $3\ibus__adr$next[44:0]$1050 $1\ibus__adr$next[44:0]$1048 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$1047 + end + attribute \src "libresoc.v:42929.3-42951.6" + process $proc$libresoc.v:42929$1051 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$1052 $3\f_fetch_err_o$next[0:0]$1055 + attribute \src "libresoc.v:42930.5-42930.29" + switch \initial + attribute \src "libresoc.v:42930.9-42930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$1053 $2\f_fetch_err_o$next[0:0]$1054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$1054 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$1054 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$1054 \f_fetch_err_o + end + case + assign $1\f_fetch_err_o$next[0:0]$1053 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_fetch_err_o$next[0:0]$1055 1'0 + case + assign $3\f_fetch_err_o$next[0:0]$1055 $1\f_fetch_err_o$next[0:0]$1053 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$1052 + end + attribute \src "libresoc.v:42952.3-42971.6" + process $proc$libresoc.v:42952$1056 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$1057 $3\f_badaddr_o$next[44:0]$1060 + attribute \src "libresoc.v:42953.5-42953.29" + switch \initial + attribute \src "libresoc.v:42953.9-42953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$1058 $2\f_badaddr_o$next[44:0]$1059 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$1059 \ibus__adr + case + assign $2\f_badaddr_o$next[44:0]$1059 \f_badaddr_o + end + case + assign $1\f_badaddr_o$next[44:0]$1058 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_badaddr_o$next[44:0]$1060 45'000000000000000000000000000000000000000000000 + case + assign $3\f_badaddr_o$next[44:0]$1060 $1\f_badaddr_o$next[44:0]$1058 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$1057 + end + attribute \src "libresoc.v:42972.3-42981.6" + process $proc$libresoc.v:42972$1061 + assign { } { } + assign { } { } + assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] + attribute \src "libresoc.v:42973.5-42973.29" + switch \initial + attribute \src "libresoc.v:42973.9-42973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_busy_o[0:0] \ibus__cyc + case + assign $1\a_busy_o[0:0] 1'0 + end + sync always + update \a_busy_o $0\a_busy_o[0:0] + end + attribute \src "libresoc.v:42982.3-42999.6" + process $proc$libresoc.v:42982$1062 + assign { } { } + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:42983.5-42983.29" + switch \initial + attribute \src "libresoc.v:42983.9-42983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_busy_o[0:0] \ibus__cyc + end + case + assign $1\f_busy_o[0:0] 1'0 + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:43000.3-43017.6" + process $proc$libresoc.v:43000$1063 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:43001.5-43001.29" + switch \initial + attribute \src "libresoc.v:43001.9-43001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_instr_o[63:0] \ibus_rdata + end + case + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$libresoc.v:42757$989_Y + connect \$11 $not$libresoc.v:42758$990_Y + connect \$13 $and$libresoc.v:42759$991_Y + connect \$15 $or$libresoc.v:42760$992_Y + connect \$17 $not$libresoc.v:42761$993_Y + connect \$1 $not$libresoc.v:42762$994_Y + connect \$19 $or$libresoc.v:42763$995_Y + connect \$21 $not$libresoc.v:42764$996_Y + connect \$23 $and$libresoc.v:42765$997_Y + connect \$25 $or$libresoc.v:42766$998_Y + connect \$27 $not$libresoc.v:42767$999_Y + connect \$29 $or$libresoc.v:42768$1000_Y + connect \$31 $not$libresoc.v:42769$1001_Y + connect \$33 $and$libresoc.v:42770$1002_Y + connect \$35 $or$libresoc.v:42771$1003_Y + connect \$37 $not$libresoc.v:42772$1004_Y + connect \$3 $and$libresoc.v:42773$1005_Y + connect \$39 $or$libresoc.v:42774$1006_Y + connect \$41 $not$libresoc.v:42775$1007_Y + connect \$43 $and$libresoc.v:42776$1008_Y + connect \$45 $and$libresoc.v:42777$1009_Y + connect \$47 $not$libresoc.v:42778$1010_Y + connect \$49 $and$libresoc.v:42779$1011_Y + connect \$51 $not$libresoc.v:42780$1012_Y + connect \$5 $or$libresoc.v:42781$1013_Y + connect \$7 $not$libresoc.v:42782$1014_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 +end +attribute \src "libresoc.v:43024.1-45737.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:45169.3-45195.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44817.3-44832.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$1482 + attribute \src "libresoc.v:44720.3-44721.41" + wire width 4 $0\dmi0__addr_i[3:0] + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $0\dmi0__din$next[63:0]$1495 + attribute \src "libresoc.v:44716.3-44717.35" + wire width 64 $0\dmi0__din[63:0] + attribute \src "libresoc.v:45019.3-45035.6" + wire $0\dmi0_addrsr__oe$next[0:0]$1419 + attribute \src "libresoc.v:44748.3-44749.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$1423 + attribute \src "libresoc.v:44746.3-44747.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:45001.3-45009.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$1413 + attribute \src "libresoc.v:44752.3-44753.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:45010.3-45018.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 + attribute \src "libresoc.v:44750.3-44751.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$1500 + attribute \src "libresoc.v:44714.3-44715.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:45075.3-45091.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$1434 + attribute \src "libresoc.v:44740.3-44741.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$1438 + attribute \src "libresoc.v:44738.3-44739.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:45057.3-45065.6" + wire $0\dmi0_datasr_update_core$next[0:0]$1428 + attribute \src "libresoc.v:44744.3-44745.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:45066.3-45074.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$1431 + attribute \src "libresoc.v:44742.3-44743.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $0\fsm_state$503$next[2:0]$1488 + attribute \src "libresoc.v:44718.3-44719.45" + wire width 3 $0\fsm_state$503[2:0]$1334 + attribute \src "libresoc.v:43670.13-43670.35" + wire width 3 $0\fsm_state$503[2:0]$1534 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $0\fsm_state$next[2:0]$1465 + attribute \src "libresoc.v:44726.3-44727.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:43025.7-43025.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45511.3-45531.6" + wire width 154 $0\io_bd$next[153:0]$1517 + attribute \src "libresoc.v:44778.3-44779.27" + wire width 154 $0\io_bd[153:0] + attribute \src "libresoc.v:45493.3-45510.6" + wire width 154 $0\io_sr$next[153:0]$1513 + attribute \src "libresoc.v:44780.3-44781.27" + wire width 154 $0\io_sr[153:0] + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$1459 + attribute \src "libresoc.v:44728.3-44729.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:45282.3-45308.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$1472 + attribute \src "libresoc.v:44724.3-44725.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44907.3-44923.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$1389 + attribute \src "libresoc.v:44764.3-44765.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44924.3-44944.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$1393 + attribute \src "libresoc.v:44762.3-44763.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44889.3-44897.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$1383 + attribute \src "libresoc.v:44768.3-44769.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44898.3-44906.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 + attribute \src "libresoc.v:44766.3-44767.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45309.3-45329.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$1477 + attribute \src "libresoc.v:44722.3-44723.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44963.3-44979.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$1404 + attribute \src "libresoc.v:44756.3-44757.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44980.3-45000.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$1408 + attribute \src "libresoc.v:44754.3-44755.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44945.3-44953.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$1398 + attribute \src "libresoc.v:44760.3-44761.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44954.3-44962.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 + attribute \src "libresoc.v:44758.3-44759.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44851.3-44867.6" + wire $0\sr0__oe$next[0:0]$1374 + attribute \src "libresoc.v:44772.3-44773.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:44868.3-44888.6" + wire width 3 $0\sr0_reg$next[2:0]$1378 + attribute \src "libresoc.v:44770.3-44771.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:44833.3-44841.6" + wire $0\sr0_update_core$next[0:0]$1368 + attribute \src "libresoc.v:44776.3-44777.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:44842.3-44850.6" + wire $0\sr0_update_core_prev$next[0:0]$1371 + attribute \src "libresoc.v:44774.3-44775.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:45483.3-45492.6" + wire width 2 $0\sr5__i[1:0] + attribute \src "libresoc.v:45131.3-45147.6" + wire $0\sr5__oe$next[0:0]$1449 + attribute \src "libresoc.v:44732.3-44733.31" + wire $0\sr5__oe[0:0] + attribute \src "libresoc.v:45148.3-45168.6" + wire width 2 $0\sr5_reg$next[1:0]$1453 + attribute \src "libresoc.v:44730.3-44731.31" + wire width 2 $0\sr5_reg[1:0] + attribute \src "libresoc.v:45113.3-45121.6" + wire $0\sr5_update_core$next[0:0]$1443 + attribute \src "libresoc.v:44736.3-44737.47" + wire $0\sr5_update_core[0:0] + attribute \src "libresoc.v:45122.3-45130.6" + wire $0\sr5_update_core_prev$next[0:0]$1446 + attribute \src "libresoc.v:44734.3-44735.57" + wire $0\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $0\wb_dcache_en$next[0:0]$1505 + attribute \src "libresoc.v:44712.3-44713.41" + wire $0\wb_dcache_en[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $0\wb_icache_en$next[0:0]$1506 + attribute \src "libresoc.v:44710.3-44711.41" + wire $0\wb_icache_en[0:0] + attribute \src "libresoc.v:45169.3-45195.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:44817.3-44832.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$1483 + attribute \src "libresoc.v:43583.13-43583.32" + wire width 4 $1\dmi0__addr_i[3:0] + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $1\dmi0__din$next[63:0]$1496 + attribute \src "libresoc.v:43588.14-43588.46" + wire width 64 $1\dmi0__din[63:0] + attribute \src "libresoc.v:45019.3-45035.6" + wire $1\dmi0_addrsr__oe$next[0:0]$1420 + attribute \src "libresoc.v:43602.7-43602.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$1424 + attribute \src "libresoc.v:43610.13-43610.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:45001.3-45009.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$1414 + attribute \src "libresoc.v:43618.7-43618.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:45010.3-45018.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 + attribute \src "libresoc.v:43622.7-43622.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$1501 + attribute \src "libresoc.v:43626.14-43626.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:45075.3-45091.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$1435 + attribute \src "libresoc.v:43632.13-43632.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$1439 + attribute \src "libresoc.v:43640.14-43640.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:45057.3-45065.6" + wire $1\dmi0_datasr_update_core$next[0:0]$1429 + attribute \src "libresoc.v:43648.7-43648.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:45066.3-45074.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$1432 + attribute \src "libresoc.v:43652.7-43652.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $1\fsm_state$503$next[2:0]$1489 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $1\fsm_state$next[2:0]$1466 + attribute \src "libresoc.v:43668.13-43668.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:45511.3-45531.6" + wire width 154 $1\io_bd$next[153:0]$1518 + attribute \src "libresoc.v:43868.15-43868.67" + wire width 154 $1\io_bd[153:0] + attribute \src "libresoc.v:45493.3-45510.6" + wire width 154 $1\io_sr$next[153:0]$1514 + attribute \src "libresoc.v:43880.15-43880.67" + wire width 154 $1\io_sr[153:0] + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$1460 + attribute \src "libresoc.v:43889.14-43889.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:45282.3-45308.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$1473 + attribute \src "libresoc.v:43898.14-43898.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:44907.3-44923.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$1390 + attribute \src "libresoc.v:43912.7-43912.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:44924.3-44944.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$1394 + attribute \src "libresoc.v:43920.14-43920.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:44889.3-44897.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$1384 + attribute \src "libresoc.v:43928.7-43928.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:44898.3-44906.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 + attribute \src "libresoc.v:43932.7-43932.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:45309.3-45329.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$1478 + attribute \src "libresoc.v:43936.14-43936.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:44963.3-44979.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$1405 + attribute \src "libresoc.v:43942.13-43942.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:44980.3-45000.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$1409 + attribute \src "libresoc.v:43950.14-43950.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:44945.3-44953.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$1399 + attribute \src "libresoc.v:43958.7-43958.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:44954.3-44962.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 + attribute \src "libresoc.v:43962.7-43962.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:44851.3-44867.6" + wire $1\sr0__oe$next[0:0]$1375 + attribute \src "libresoc.v:44392.7-44392.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:44868.3-44888.6" + wire width 3 $1\sr0_reg$next[2:0]$1379 + attribute \src "libresoc.v:44400.13-44400.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:44833.3-44841.6" + wire $1\sr0_update_core$next[0:0]$1369 + attribute \src "libresoc.v:44408.7-44408.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:44842.3-44850.6" + wire $1\sr0_update_core_prev$next[0:0]$1372 + attribute \src "libresoc.v:44412.7-44412.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:45483.3-45492.6" + wire width 2 $1\sr5__i[1:0] + attribute \src "libresoc.v:45131.3-45147.6" + wire $1\sr5__oe$next[0:0]$1450 + attribute \src "libresoc.v:44422.7-44422.21" + wire $1\sr5__oe[0:0] + attribute \src "libresoc.v:45148.3-45168.6" + wire width 2 $1\sr5_reg$next[1:0]$1454 + attribute \src "libresoc.v:44430.13-44430.27" + wire width 2 $1\sr5_reg[1:0] + attribute \src "libresoc.v:45113.3-45121.6" + wire $1\sr5_update_core$next[0:0]$1444 + attribute \src "libresoc.v:44438.7-44438.29" + wire $1\sr5_update_core[0:0] + attribute \src "libresoc.v:45122.3-45130.6" + wire $1\sr5_update_core_prev$next[0:0]$1447 + attribute \src "libresoc.v:44442.7-44442.34" + wire $1\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $1\wb_dcache_en$next[0:0]$1507 + attribute \src "libresoc.v:44446.7-44446.26" + wire $1\wb_dcache_en[0:0] + attribute \src "libresoc.v:45464.3-45482.6" + wire $1\wb_icache_en$next[0:0]$1508 + attribute \src "libresoc.v:44451.7-44451.26" + wire $1\wb_icache_en[0:0] + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$1484 + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $2\dmi0__din$next[63:0]$1497 + attribute \src "libresoc.v:45019.3-45035.6" + wire $2\dmi0_addrsr__oe$next[0:0]$1421 + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$1425 + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$1502 + attribute \src "libresoc.v:45075.3-45091.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$1436 + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$1440 + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 $2\fsm_state$503$next[2:0]$1490 + attribute \src "libresoc.v:45229.3-45281.6" + wire width 3 $2\fsm_state$next[2:0]$1467 + attribute \src "libresoc.v:45511.3-45531.6" + wire width 154 $2\io_bd$next[153:0]$1519 + attribute \src "libresoc.v:45493.3-45510.6" + wire width 154 $2\io_sr$next[153:0]$1515 + attribute \src "libresoc.v:45196.3-45228.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$1461 + attribute \src "libresoc.v:45282.3-45308.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$1474 + attribute \src "libresoc.v:44907.3-44923.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$1391 + attribute \src "libresoc.v:44924.3-44944.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$1395 + attribute \src "libresoc.v:45309.3-45329.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$1479 + attribute \src "libresoc.v:44963.3-44979.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$1406 + attribute \src "libresoc.v:44980.3-45000.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$1410 + attribute \src "libresoc.v:44851.3-44867.6" + wire $2\sr0__oe$next[0:0]$1376 + attribute \src "libresoc.v:44868.3-44888.6" + wire width 3 $2\sr0_reg$next[2:0]$1380 + attribute \src "libresoc.v:45131.3-45147.6" + wire $2\sr5__oe$next[0:0]$1451 + attribute \src "libresoc.v:45148.3-45168.6" + wire width 2 $2\sr5_reg$next[1:0]$1455 + attribute \src "libresoc.v:45464.3-45482.6" + wire $2\wb_dcache_en$next[0:0]$1509 + attribute \src "libresoc.v:45464.3-45482.6" + wire $2\wb_icache_en$next[0:0]$1510 + attribute \src "libresoc.v:45330.3-45362.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$1485 + attribute \src "libresoc.v:45416.3-45442.6" + wire width 64 $3\dmi0__din$next[63:0]$1498 + attribute \src "libresoc.v:45036.3-45056.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$1426 + attribute \src "libresoc.v:45443.3-45463.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$1503 + attribute \src "libresoc.v:45092.3-45112.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$1441 + attribute \src "libresoc.v:45363.3-45415.6" + wire width 3 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"/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" - wire width 32 \$119 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:287" - wire width 32 \$123 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 \$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \$129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" - wire width 65 \$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" - wire width 65 \$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" - wire width 65 \$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" - wire width 65 \$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$129 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$131 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$133 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$135 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire 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wire \$195 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$197 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$199 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$201 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$203 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$205 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$207 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$209 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - wire width 3 \$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - wire width 3 \$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - wire \$30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - wire width 65 \$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - wire width 65 \$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$211 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$213 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$215 + attribute \src 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attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$237 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$239 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$241 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$243 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$245 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$247 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$249 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$251 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$253 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$255 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$257 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$259 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$263 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$265 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$267 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$269 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$271 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$273 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$275 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$277 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$279 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$281 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$283 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$285 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$287 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$289 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$291 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$293 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$295 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$297 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$299 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$301 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$303 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$305 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$307 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$309 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$311 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$313 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$315 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$317 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$319 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$321 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$323 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$325 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$327 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$329 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$331 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$333 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$335 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$337 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$339 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$341 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$343 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$345 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$347 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$349 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$351 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$353 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$355 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$357 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$359 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$361 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$363 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + wire \$365 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$367 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$369 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$371 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$373 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$375 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$377 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$379 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$381 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$383 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$385 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$387 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$389 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$391 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$393 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$395 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$397 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$399 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$401 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$403 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$405 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$407 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$409 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - wire \$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$53 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire \$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" - wire width 4 \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - wire \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - wire \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" - wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 342 \TAP_bus__tck - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 178 \TAP_bus__tdi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 333 \TAP_bus__tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 343 \TAP_bus__tms - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" - wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 1 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" - wire width 8 \core_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" - wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:103" - wire input 4 \core_bigendian_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire \core_bigendian_i$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" - wire \core_bigendian_i$10$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \core_cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" - wire width 64 \core_core_core_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" - wire width 64 \core_core_core_cia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \core_core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \core_core_core_cr_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \core_core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \core_core_core_cr_rd_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \core_core_core_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \core_core_core_cr_wr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \core_core_core_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \core_core_core_exc_$signal$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \core_core_core_exc_$signal$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \core_core_core_exc_$signal$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \core_core_core_exc_$signal$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \core_core_core_exc_$signal$5 - attribute \src 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"/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \_idblock_id_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \_idblock_select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire \_irblock_tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 360 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \cu_st__rel_o_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \cu_st__rel_o_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \cu_st__rel_o_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342" - wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:342" - wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:332" - wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:332" - wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" - wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:352" - wire \d_xer_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dbg_core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dbg_core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" - wire \dbg_core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" - wire \dbg_core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" - wire \dbg_core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire \dbg_d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 \dbg_d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_cr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire \dbg_d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" - wire width 7 \dbg_d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 \dbg_d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" - wire \dbg_d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" - wire width 64 \dbg_d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" - wire \dbg_d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire \dbg_dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \dbg_dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 \dbg_dmi_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \dbg_dmi_din - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 \dbg_dmi_din$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 \dbg_dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire \dbg_dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire \dbg_dmi_req_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire \dbg_dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire \dbg_dmi_we_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" - wire \dbg_terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 9 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 14 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 8 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 13 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 16 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 10 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 12 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 11 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 15 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" - wire width 8 \dec2_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" - wire \dec2_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" - wire width 64 \dec2_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_in2$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_cr_in2_ok$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \dec2_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 8 \dec2_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \dec2_cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \dec2_cur_dec$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire \dec2_cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire \dec2_cur_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dec2_cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dec2_cur_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dec2_cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dec2_cur_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \dec2_exc_$signal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \dec2_exc_$signal$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \dec2_exc_$signal$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \dec2_exc_$signal$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" - wire \dec2_exc_$signal$17 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 3 \dec2_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_fasto2_ok - attribute \enum_base_type "Function" - attribute \enum_value_000000000000 "NONE" - attribute \enum_value_000000000010 "ALU" - attribute \enum_value_000000000100 "LDST" - attribute \enum_value_000000001000 "SHIFT_ROT" - attribute \enum_value_000000010000 "LOGICAL" - attribute \enum_value_000000100000 "BRANCH" - attribute \enum_value_000001000000 "CR" - attribute \enum_value_000010000000 "TRAP" - attribute \enum_value_000100000000 "MUL" - attribute \enum_value_001000000000 "DIV" - attribute \enum_value_010000000000 "SPR" - attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 12 \dec2_fn_unit - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 2 \dec2_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 32 \dec2_insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" - wire width 32 \dec2_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_reg3_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 5 \dec2_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_rego_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 \dec2_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_spr1_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 10 \dec2_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire \dec2_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" - wire width 13 \dec2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 8 \dec2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" - wire width 3 \dec2_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" - wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" - wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" - wire width 2 \delay$next + wire input 329 \clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire input 6 \dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 output 2 \dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \dmi0__addr_i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 output 5 \dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \dmi0__din$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 input 7 \dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 3 \dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 4 \dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 164 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 9 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 165 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 10 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 166 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 11 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 13 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 14 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 12 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s7__pad__oe + attribute \src "libresoc.v:43025.7-43025.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 325 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 319 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 321 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 326 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 324 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 320 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 322 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 323 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \pwm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \eint_0__core__i + wire output 228 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 24 \eint_0__pad__i + wire input 77 \sd0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \eint_1__core__i + wire output 232 \sd0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 25 \eint_1__pad__i + wire output 229 \sd0_cmd__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \eint_2__core__i + wire input 75 \sd0_cmd__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - wire width 2 \fsm_state$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - wire width 2 \fsm_state$133$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - wire width 2 \fsm_state$next + wire input 76 \sd0_cmd__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e10__core__i + wire input 74 \sd0_cmd__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 34 \gpio_e10__core__o + wire output 230 \sd0_cmd__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 35 \gpio_e10__core__oe + wire output 231 \sd0_cmd__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 33 \gpio_e10__pad__i + wire output 233 \sd0_data0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e10__pad__o + wire input 79 \sd0_data0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e10__pad__oe + wire input 80 \sd0_data0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e11__core__i + wire input 78 \sd0_data0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 37 \gpio_e11__core__o + wire output 234 \sd0_data0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 38 \gpio_e11__core__oe + wire output 235 \sd0_data0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 36 \gpio_e11__pad__i + wire output 236 \sd0_data1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e11__pad__o + wire input 82 \sd0_data1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_e11__pad__oe + wire input 83 \sd0_data1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_e12__core__i + wire input 81 \sd0_data1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 40 \gpio_e12__core__o + wire output 237 \sd0_data1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 41 \gpio_e12__core__oe + wire output 238 \sd0_data1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 39 \gpio_e12__pad__i + wire output 239 \sd0_data2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_e12__pad__o + wire input 85 \sd0_data2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_e12__pad__oe + wire input 86 \sd0_data2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_e13__core__i + wire input 84 \sd0_data2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 43 \gpio_e13__core__o + wire output 240 \sd0_data2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 44 \gpio_e13__core__oe + wire output 241 \sd0_data2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 42 \gpio_e13__pad__i + wire output 242 \sd0_data3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_e13__pad__o + wire input 88 \sd0_data3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_e13__pad__oe + wire input 89 \sd0_data3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_e14__core__i + wire input 87 \sd0_data3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 46 \gpio_e14__core__o + wire output 243 \sd0_data3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 47 \gpio_e14__core__oe + wire output 244 \sd0_data3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 45 \gpio_e14__pad__i + wire input 115 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_e14__pad__o + wire output 270 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_e14__pad__oe + wire input 133 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_e15__core__i + wire output 288 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 49 \gpio_e15__core__o + wire input 134 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 50 \gpio_e15__core__oe + wire output 289 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 48 \gpio_e15__pad__i + wire input 135 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_e15__pad__o + wire output 290 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_e15__pad__oe + wire input 116 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e8__core__i + wire output 271 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 28 \gpio_e8__core__o + wire input 117 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 29 \gpio_e8__core__oe + wire output 272 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 27 \gpio_e8__pad__i + wire input 118 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e8__pad__o + wire output 273 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e8__pad__oe + wire input 119 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e9__core__i + wire output 274 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 31 \gpio_e9__core__o + wire input 120 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 32 \gpio_e9__core__oe + wire output 275 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 30 \gpio_e9__pad__i + wire input 121 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e9__pad__o + wire output 276 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e9__pad__oe + wire input 122 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s0__core__i + wire output 277 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 52 \gpio_s0__core__o + wire input 123 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 53 \gpio_s0__core__oe + wire output 278 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 51 \gpio_s0__pad__i + wire input 124 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s0__pad__o + wire output 279 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s0__pad__oe + wire input 125 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s1__core__i + wire output 280 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 55 \gpio_s1__core__o + wire input 126 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 56 \gpio_s1__core__oe + wire output 281 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 54 \gpio_s1__pad__i + wire input 130 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s1__pad__o + wire output 285 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s1__pad__oe + wire input 128 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s2__core__i + wire output 283 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 58 \gpio_s2__core__o + wire input 127 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 59 \gpio_s2__core__oe + wire output 282 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 57 \gpio_s2__pad__i + wire input 132 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s2__pad__o + wire output 287 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s2__pad__oe + wire input 90 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s3__core__i + wire output 245 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 61 \gpio_s3__core__o + wire output 291 \sdr_dm_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 62 \gpio_s3__core__oe + wire input 137 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 60 \gpio_s3__pad__i + wire input 138 \sdr_dm_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s3__pad__o + wire input 136 \sdr_dm_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \gpio_s3__pad__oe + wire output 292 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \gpio_s4__core__i + wire output 293 \sdr_dm_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 64 \gpio_s4__core__o + wire output 246 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \gpio_s4__core__oe + wire input 92 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 63 \gpio_s4__pad__i + wire input 93 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \gpio_s4__pad__o + wire input 91 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \gpio_s4__pad__oe + wire output 247 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \gpio_s5__core__i + wire output 248 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \gpio_s5__core__o + wire output 300 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \gpio_s5__core__oe + wire input 146 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \gpio_s5__pad__i + wire input 147 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \gpio_s5__pad__o + wire input 145 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \gpio_s5__pad__oe + wire output 301 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \gpio_s6__core__i + wire output 302 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \gpio_s6__core__o + wire output 303 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \gpio_s6__core__oe + wire input 149 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \gpio_s6__pad__i + wire input 150 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \gpio_s6__pad__o + wire input 148 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \gpio_s6__pad__oe + wire output 304 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \gpio_s7__core__i + wire output 305 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \gpio_s7__core__o + wire output 306 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \gpio_s7__core__oe + wire input 152 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \gpio_s7__pad__i + wire input 153 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \gpio_s7__pad__o + wire input 151 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \gpio_s7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 18 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 23 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 17 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 22 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 19 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 21 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 20 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 344 \icp_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 350 \icp_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 345 \icp_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 346 \icp_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 347 \icp_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 351 \icp_wb__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 348 \icp_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 349 \icp_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 357 \ics_wb__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 352 \ics_wb__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 354 \ics_wb__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 356 \ics_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 358 \ics_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 355 \ics_wb__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 359 \ics_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" - wire width 32 \ilatch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:196" - wire width 32 \ilatch$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 \imem_a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire \imem_a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire \imem_f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 \imem_f_instr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire \imem_f_valid_i + wire output 307 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr5_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr5_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr5_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr5_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_dcache_en$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" - wire \imem_wb_icache_en - attribute \src "libresoc.v:183018.7-183018.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 353 \int_level_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__ack_o - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__ack_o$next - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 4 \jtag_dmi0__addr_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \jtag_dmi0__din - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \jtag_dmi0__dout - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 64 \jtag_dmi0__dout$next + wire output 8 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + cell $add $add$libresoc.v:44674$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:44674$1292_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + cell $add $add$libresoc.v:44676$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:44676$1294_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + cell $add $add$libresoc.v:44682$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:44682$1301_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + cell $add $add$libresoc.v:44683$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:44683$1302_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $and$libresoc.v:44498$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44498$1116_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:44565$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$27 + connect \Y $and$libresoc.v:44565$1183_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $and$libresoc.v:44576$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44576$1194_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:44604$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$367 + connect \Y $and$libresoc.v:44604$1222_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44607$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$373 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44607$1225_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44610$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$377 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44610$1228_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44612$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$381 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44612$1230_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:44614$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$385 + connect \Y $and$libresoc.v:44614$1232_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44617$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$391 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44617$1235_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44619$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$395 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:44619$1237_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:44623$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$399 + connect \B \_fsm_update + connect \Y $and$libresoc.v:44623$1241_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:44625$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$403 + connect \Y $and$libresoc.v:44625$1243_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:44629$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$411 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:44629$1247_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:44631$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$415 + connect \B \_fsm_shift + connect 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"/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__req_i + cell $pos $extend$libresoc.v:44677$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \dmi0__addr_i + connect \Y $extend$libresoc.v:44677$1295_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:44606$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44606$1224_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:44608$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44608$1226_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:44611$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44611$1229_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:44616$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44616$1234_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:44618$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44618$1236_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:44622$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44622$1240_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:44628$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44628$1246_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:44630$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44630$1248_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:44633$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44633$1251_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:44638$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44638$1256_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:44640$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44640$1258_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:44642$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44642$1260_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:44649$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44649$1267_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:44651$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44651$1269_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:44653$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44653$1271_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:44659$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44659$1277_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:44661$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44661$1279_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:44663$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:44663$1281_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44613$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:44613$1231_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44624$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:44624$1242_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44635$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:44635$1253_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44645$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:44645$1263_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44656$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:44656$1274_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:44666$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core + connect \Y $not$libresoc.v:44666$1284_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $not $not$libresoc.v:44669$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$484 + connect \Y $not$libresoc.v:44669$1287_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44487$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:44487$1105_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44532$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \$21 + connect \Y $or$libresoc.v:44532$1150_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:44554$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:44554$1172_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44601$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:44601$1219_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:44603$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$363 + connect \B \$365 + connect \Y $or$libresoc.v:44603$1221_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:44609$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:44609$1227_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:44632$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:44632$1250_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $or $or$libresoc.v:44672$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$487 + connect \B \$489 + connect \Y $or$libresoc.v:44672$1290_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $or $or$libresoc.v:44680$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$504 + connect \B \$506 + connect \Y $or$libresoc.v:44680$1299_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $or $or$libresoc.v:44688$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:44688$1307_Y + end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire \jtag_dmi0__we_i - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 340 \jtag_wb__ack - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 334 \jtag_wb__adr - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 336 \jtag_wb__cyc - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 341 \jtag_wb__dat_r - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 339 \jtag_wb__dat_w - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 335 \jtag_wb__sel - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 337 \jtag_wb__stb - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 338 \jtag_wb__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \mspi0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \mspi0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \mspi0_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \mspi0_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \mspi0_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \mspi0_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \mspi0_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \msr_read - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" - wire \msr_read$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:390" - wire width 64 \new_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:407" - wire width 64 \new_tb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" - wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:203" - wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" - wire \pc_changed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 7 \pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire input 6 \pc_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:101" - wire width 64 output 5 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" - wire \pc_ok_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" - wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:166" + cell $pos $pos$libresoc.v:44677$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:44677$1295_Y + connect \Y $pos$libresoc.v:44677$1296_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44455$1073 + parameter \WIDTH 1 + connect \A \gpio_e15__pad__i + connect \B \io_bd [24] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44455$1073_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44456$1074 + parameter \WIDTH 1 + connect \A \gpio_e15__core__o + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44456$1074_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44457$1075 + parameter \WIDTH 1 + connect \A \gpio_e15__core__oe + connect \B \io_bd [26] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44457$1075_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44458$1076 + parameter \WIDTH 1 + connect \A \gpio_s0__pad__i + connect \B \io_bd [27] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44458$1076_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44459$1077 + parameter \WIDTH 1 + connect \A \gpio_s0__core__o + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44459$1077_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44460$1078 + parameter \WIDTH 1 + connect \A \gpio_s0__core__oe + connect \B \io_bd [29] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44460$1078_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44461$1079 + parameter \WIDTH 1 + connect \A \gpio_s1__pad__i + connect \B \io_bd [30] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44461$1079_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44462$1080 + parameter \WIDTH 1 + connect \A \gpio_s1__core__o + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44462$1080_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44463$1081 + parameter \WIDTH 1 + connect \A \gpio_s1__core__oe + connect \B \io_bd [32] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44463$1081_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44464$1082 + parameter \WIDTH 1 + connect \A \gpio_s2__pad__i + connect \B \io_bd [33] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44464$1082_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44466$1084 + parameter \WIDTH 1 + connect \A \gpio_s2__core__o + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44466$1084_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44467$1085 + parameter \WIDTH 1 + connect \A \gpio_s2__core__oe + connect \B \io_bd [35] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44467$1085_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44468$1086 + parameter \WIDTH 1 + connect \A \gpio_s3__pad__i + connect \B \io_bd [36] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44468$1086_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44469$1087 + parameter \WIDTH 1 + connect \A \gpio_s3__core__o + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44469$1087_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44470$1088 + parameter \WIDTH 1 + connect \A \gpio_s3__core__oe + connect \B \io_bd [38] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44470$1088_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44471$1089 + parameter \WIDTH 1 + connect \A \gpio_s4__pad__i + connect \B \io_bd [39] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44471$1089_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44472$1090 + parameter \WIDTH 1 + connect \A \gpio_s4__core__o + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44472$1090_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44473$1091 + parameter \WIDTH 1 + connect \A \gpio_s4__core__oe + connect \B \io_bd [41] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44473$1091_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44474$1092 + parameter \WIDTH 1 + connect \A \gpio_s5__pad__i + connect \B \io_bd [42] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44474$1092_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44475$1093 + parameter \WIDTH 1 + connect \A \gpio_s5__core__o + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44475$1093_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44477$1095 + parameter \WIDTH 1 + connect \A \gpio_s5__core__oe + connect \B \io_bd [44] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44477$1095_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44478$1096 + parameter \WIDTH 1 + connect \A \gpio_s6__pad__i + connect \B \io_bd [45] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44478$1096_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44479$1097 + parameter \WIDTH 1 + connect \A \gpio_s6__core__o + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44479$1097_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44480$1098 + parameter \WIDTH 1 + connect \A \gpio_s6__core__oe + connect \B \io_bd [47] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44480$1098_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44481$1099 + parameter \WIDTH 1 + connect \A \gpio_s7__pad__i + connect \B \io_bd [48] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44481$1099_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44482$1100 + parameter \WIDTH 1 + connect \A \gpio_s7__core__o + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44482$1100_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44483$1101 + parameter \WIDTH 1 + connect \A \gpio_s7__core__oe + connect \B \io_bd [50] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44483$1101_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44484$1102 + parameter \WIDTH 1 + connect \A \mspi0_clk__core__o + connect \B \io_bd [51] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44484$1102_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44485$1103 + parameter \WIDTH 1 + connect \A \mspi0_cs_n__core__o + connect \B \io_bd [52] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44485$1103_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44486$1104 + parameter \WIDTH 1 + connect \A \mspi0_mosi__core__o + connect \B \io_bd [53] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44486$1104_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44488$1106 + parameter \WIDTH 1 + connect \A \mspi0_miso__pad__i + connect \B \io_bd [54] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44488$1106_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44489$1107 + parameter \WIDTH 1 + connect \A \mspi1_clk__core__o + connect \B \io_bd [55] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44489$1107_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44490$1108 + parameter \WIDTH 1 + connect \A \mspi1_cs_n__core__o + connect \B \io_bd [56] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44490$1108_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44491$1109 + parameter \WIDTH 1 + connect \A \mspi1_mosi__core__o + connect \B \io_bd [57] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44491$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44492$1110 + parameter \WIDTH 1 + connect \A \mspi1_miso__pad__i + connect \B \io_bd [58] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44492$1110_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44493$1111 + parameter \WIDTH 1 + connect \A \mtwi_sda__pad__i + connect \B \io_bd [59] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44493$1111_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44494$1112 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__o + connect \B \io_bd [60] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44494$1112_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44495$1113 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__oe + connect \B \io_bd [61] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44495$1113_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44496$1114 + parameter \WIDTH 1 + connect \A \mtwi_scl__core__o + connect \B \io_bd [62] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44496$1114_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44497$1115 + parameter \WIDTH 1 + connect \A \pwm_0__core__o + connect \B \io_bd [63] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44497$1115_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44499$1117 + parameter \WIDTH 1 + connect \A \pwm_1__core__o + connect \B \io_bd [64] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44499$1117_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44500$1118 + parameter \WIDTH 1 + connect \A \sd0_cmd__pad__i + connect \B \io_bd [65] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44500$1118_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44501$1119 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__o + connect \B \io_bd [66] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44501$1119_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44502$1120 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__oe + connect \B \io_bd [67] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44502$1120_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44503$1121 + parameter \WIDTH 1 + connect \A \sd0_clk__core__o + connect \B \io_bd [68] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44503$1121_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44504$1122 + parameter \WIDTH 1 + connect \A \sd0_data0__pad__i + connect \B \io_bd [69] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44504$1122_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44505$1123 + parameter \WIDTH 1 + connect \A \sd0_data0__core__o + connect \B \io_bd [70] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44505$1123_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44506$1124 + parameter \WIDTH 1 + connect \A \sd0_data0__core__oe + connect \B \io_bd [71] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44506$1124_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44507$1125 + parameter \WIDTH 1 + connect \A \sd0_data1__pad__i + connect \B \io_bd [72] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44507$1125_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44508$1126 + parameter \WIDTH 1 + connect \A \sd0_data1__core__o + connect \B \io_bd [73] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44508$1126_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44511$1129 + parameter \WIDTH 1 + connect \A \sd0_data1__core__oe + connect \B \io_bd [74] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44511$1129_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44512$1130 + parameter \WIDTH 1 + connect \A \sd0_data2__pad__i + connect \B \io_bd [75] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44512$1130_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44513$1131 + parameter \WIDTH 1 + connect \A \sd0_data2__core__o + connect \B \io_bd [76] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44513$1131_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44514$1132 + parameter \WIDTH 1 + connect \A \sd0_data2__core__oe + connect \B \io_bd [77] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44514$1132_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44515$1133 + parameter \WIDTH 1 + connect \A \sd0_data3__pad__i + connect \B \io_bd [78] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44515$1133_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44516$1134 + parameter \WIDTH 1 + connect \A \sd0_data3__core__o + connect \B \io_bd [79] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44516$1134_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44517$1135 + parameter \WIDTH 1 + connect \A \sd0_data3__core__oe + connect \B \io_bd [80] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44517$1135_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44518$1136 + parameter \WIDTH 1 + connect \A \sdr_dm_0__core__o + connect \B \io_bd [81] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44518$1136_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44519$1137 + parameter \WIDTH 1 + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [82] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44519$1137_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44520$1138 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__o + connect \B \io_bd [83] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44520$1138_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44522$1140 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [84] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44522$1140_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44523$1141 + parameter \WIDTH 1 + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [85] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44523$1141_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44524$1142 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__o + connect \B \io_bd [86] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44524$1142_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44525$1143 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [87] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44525$1143_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44526$1144 + parameter \WIDTH 1 + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [88] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44526$1144_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44527$1145 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__o + connect \B \io_bd [89] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44527$1145_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44528$1146 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [90] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44528$1146_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44529$1147 + parameter \WIDTH 1 + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [91] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44529$1147_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44530$1148 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__o + connect \B \io_bd [92] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44530$1148_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44531$1149 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [93] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44531$1149_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44533$1151 + parameter \WIDTH 1 + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [94] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44533$1151_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44534$1152 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__o + connect \B \io_bd [95] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44534$1152_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44535$1153 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [96] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44535$1153_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44536$1154 + parameter \WIDTH 1 + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [97] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44536$1154_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44537$1155 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__o + connect \B \io_bd [98] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44537$1155_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44538$1156 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [99] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44538$1156_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44539$1157 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [100] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44539$1157_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44540$1158 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__o + connect \B \io_bd [101] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44540$1158_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44541$1159 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [102] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44541$1159_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44542$1160 + parameter \WIDTH 1 + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [103] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44542$1160_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44544$1162 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__o + connect \B \io_bd [104] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44544$1162_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44545$1163 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [105] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44545$1163_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44546$1164 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o + connect \B \io_bd [106] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44546$1164_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44547$1165 + parameter \WIDTH 1 + connect \A \sdr_a_1__core__o + connect \B \io_bd [107] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44547$1165_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44548$1166 + parameter \WIDTH 1 + connect \A \sdr_a_2__core__o + connect \B \io_bd [108] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44548$1166_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44549$1167 + parameter \WIDTH 1 + connect \A \sdr_a_3__core__o + connect \B \io_bd [109] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44549$1167_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44550$1168 + parameter \WIDTH 1 + connect \A \sdr_a_4__core__o + connect \B \io_bd [110] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44550$1168_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44551$1169 + parameter \WIDTH 1 + connect \A \sdr_a_5__core__o + connect \B \io_bd [111] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44551$1169_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44552$1170 + parameter \WIDTH 1 + connect \A \sdr_a_6__core__o + connect \B \io_bd [112] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44552$1170_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44553$1171 + parameter \WIDTH 1 + connect \A \sdr_a_7__core__o + connect \B \io_bd [113] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44553$1171_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44555$1173 + parameter \WIDTH 1 + connect \A \sdr_a_8__core__o + connect \B \io_bd [114] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44555$1173_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44556$1174 + parameter \WIDTH 1 + connect \A \sdr_a_9__core__o + connect \B \io_bd [115] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44556$1174_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44557$1175 + parameter \WIDTH 1 + connect \A \sdr_ba_0__core__o + connect \B \io_bd [116] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44557$1175_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44558$1176 + parameter \WIDTH 1 + connect \A \sdr_ba_1__core__o + connect \B \io_bd [117] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44558$1176_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44559$1177 + parameter \WIDTH 1 + connect \A \sdr_clock__core__o + connect \B \io_bd [118] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44559$1177_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44560$1178 + parameter \WIDTH 1 + connect \A \sdr_cke__core__o + connect \B \io_bd [119] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44560$1178_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44561$1179 + parameter \WIDTH 1 + connect \A \sdr_ras_n__core__o + connect \B \io_bd [120] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44561$1179_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44562$1180 + parameter \WIDTH 1 + connect \A \sdr_cas_n__core__o + connect \B \io_bd [121] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44562$1180_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44563$1181 + parameter \WIDTH 1 + connect \A \sdr_we_n__core__o + connect \B \io_bd [122] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44563$1181_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44564$1182 + parameter \WIDTH 1 + connect \A \sdr_cs_n__core__o + connect \B \io_bd [123] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44564$1182_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44566$1184 + parameter \WIDTH 1 + connect \A \sdr_a_10__core__o + connect \B \io_bd [124] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44566$1184_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44567$1185 + parameter \WIDTH 1 + connect \A \sdr_a_11__core__o + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44567$1185_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:44568$1186 + parameter \WIDTH 1 + connect \A \sdr_a_12__core__o + connect \B \io_bd [126] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44568$1186_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44569$1187 + parameter \WIDTH 1 + connect \A \sdr_dm_1__pad__i + connect \B \io_bd [127] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44569$1187_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44570$1188 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__o + connect \B \io_bd [128] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44570$1188_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44571$1189 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__oe + connect \B \io_bd [129] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44571$1189_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44572$1190 + parameter \WIDTH 1 + connect \A \sdr_dq_8__pad__i + connect \B \io_bd [130] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44572$1190_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44573$1191 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__o + connect \B \io_bd [131] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44573$1191_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44574$1192 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__oe + connect \B \io_bd [132] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44574$1192_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44575$1193 + parameter \WIDTH 1 + connect \A \sdr_dq_9__pad__i + connect \B \io_bd [133] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44575$1193_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44577$1195 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__o + connect \B \io_bd [134] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44577$1195_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44578$1196 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__oe + connect \B \io_bd [135] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44578$1196_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44579$1197 + parameter \WIDTH 1 + connect \A \sdr_dq_10__pad__i + connect \B \io_bd [136] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44579$1197_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44580$1198 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__o + connect \B \io_bd [137] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44580$1198_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44581$1199 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__oe + connect \B \io_bd [138] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44581$1199_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44582$1200 + parameter \WIDTH 1 + connect \A \sdr_dq_11__pad__i + connect \B \io_bd [139] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44582$1200_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44583$1201 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__o + connect \B \io_bd [140] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44583$1201_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44584$1202 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__oe + connect \B \io_bd [141] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44584$1202_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44585$1203 + parameter \WIDTH 1 + connect \A \sdr_dq_12__pad__i + connect \B \io_bd [142] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44585$1203_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44586$1204 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__o + connect \B \io_bd [143] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44586$1204_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44588$1206 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__oe + connect \B \io_bd [144] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44588$1206_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44589$1207 + parameter \WIDTH 1 + connect \A \sdr_dq_13__pad__i + connect \B \io_bd [145] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44589$1207_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44590$1208 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__o + connect \B \io_bd [146] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44590$1208_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44591$1209 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__oe + connect \B \io_bd [147] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44591$1209_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44592$1210 + parameter \WIDTH 1 + connect \A \sdr_dq_14__pad__i + connect \B \io_bd [148] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44592$1210_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44593$1211 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__o + connect \B \io_bd [149] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44593$1211_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44594$1212 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__oe + connect \B \io_bd [150] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44594$1212_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44595$1213 + parameter \WIDTH 1 + connect \A \sdr_dq_15__pad__i + connect \B \io_bd [151] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44595$1213_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44596$1214 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__o + connect \B \io_bd [152] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44596$1214_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44597$1215 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__oe + connect \B \io_bd [153] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44597$1215_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44684$1303 + parameter \WIDTH 1 + connect \A \eint_0__pad__i + connect \B \io_bd [0] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44684$1303_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44685$1304 + parameter \WIDTH 1 + connect \A \eint_1__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44685$1304_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:44686$1305 + parameter \WIDTH 1 + connect \A \eint_2__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44686$1305_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44687$1306 + parameter \WIDTH 1 + connect \A \gpio_e8__pad__i + connect \B \io_bd [3] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44687$1306_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44689$1308 + parameter \WIDTH 1 + connect \A \gpio_e8__core__o + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44689$1308_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44690$1309 + parameter \WIDTH 1 + connect \A \gpio_e8__core__oe + connect \B \io_bd [5] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44690$1309_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44691$1310 + parameter \WIDTH 1 + connect \A \gpio_e9__pad__i + connect \B \io_bd [6] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44691$1310_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44692$1311 + parameter \WIDTH 1 + connect \A \gpio_e9__core__o + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44692$1311_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44693$1312 + parameter \WIDTH 1 + connect \A \gpio_e9__core__oe + connect \B \io_bd [8] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44693$1312_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44694$1313 + parameter \WIDTH 1 + connect \A \gpio_e10__pad__i + connect \B \io_bd [9] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44694$1313_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44695$1314 + parameter \WIDTH 1 + connect \A \gpio_e10__core__o + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44695$1314_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44696$1315 + parameter \WIDTH 1 + connect \A \gpio_e10__core__oe + connect \B \io_bd [11] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44696$1315_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44697$1316 + parameter \WIDTH 1 + connect \A \gpio_e11__pad__i + connect \B \io_bd [12] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44697$1316_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44698$1317 + parameter \WIDTH 1 + connect \A \gpio_e11__core__o + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44698$1317_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44700$1319 + parameter \WIDTH 1 + connect \A \gpio_e11__core__oe + connect \B \io_bd [14] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44700$1319_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44701$1320 + parameter \WIDTH 1 + connect \A \gpio_e12__pad__i + connect \B \io_bd [15] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44701$1320_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44702$1321 + parameter \WIDTH 1 + connect \A \gpio_e12__core__o + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44702$1321_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44703$1322 + parameter \WIDTH 1 + connect \A \gpio_e12__core__oe + connect \B \io_bd [17] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44703$1322_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44704$1323 + parameter \WIDTH 1 + connect \A \gpio_e13__pad__i + connect \B \io_bd [18] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44704$1323_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44705$1324 + parameter \WIDTH 1 + connect \A \gpio_e13__core__o + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44705$1324_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44706$1325 + parameter \WIDTH 1 + connect \A \gpio_e13__core__oe + connect \B \io_bd [20] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44706$1325_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:44707$1326 + parameter \WIDTH 1 + connect \A \gpio_e14__pad__i + connect \B \io_bd [21] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:44707$1326_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:44708$1327 + parameter \WIDTH 1 + connect \A \gpio_e14__core__o + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44708$1327_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:44709$1328 + parameter \WIDTH 1 + connect \A \gpio_e14__core__oe + connect \B \io_bd [23] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:44709$1328_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:44782.8-44794.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:44795.12-44805.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \id_bypass \_idblock_id_bypass + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \select_id \_idblock_select_id + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:44806.12-44816.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:43025.7-43025.20" + process $proc$libresoc.v:43025$1520 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:43583.13-43583.32" + process $proc$libresoc.v:43583$1521 + assign { } { } + assign $1\dmi0__addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0__addr_i $1\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:43588.14-43588.46" + process $proc$libresoc.v:43588$1522 + assign { } { } + assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0__din $1\dmi0__din[63:0] + end + attribute \src "libresoc.v:43602.7-43602.29" + process $proc$libresoc.v:43602$1523 + assign { } { } + assign $1\dmi0_addrsr__oe[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43610.13-43610.36" + process $proc$libresoc.v:43610$1524 + assign { } { } + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 + sync always + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:43618.7-43618.37" + process $proc$libresoc.v:43618$1525 + assign { } { } + assign $1\dmi0_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43622.7-43622.42" + process $proc$libresoc.v:43622$1526 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43626.14-43626.51" + process $proc$libresoc.v:43626$1527 + assign { } { } + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:43632.13-43632.35" + process $proc$libresoc.v:43632$1528 + assign { } { } + assign $1\dmi0_datasr__oe[1:0] 2'00 + sync always + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:43640.14-43640.52" + process $proc$libresoc.v:43640$1529 + assign { } { } + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:43648.7-43648.37" + process $proc$libresoc.v:43648$1530 + assign { } { } + assign $1\dmi0_datasr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43652.7-43652.42" + process $proc$libresoc.v:43652$1531 + assign { } { } + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43668.13-43668.29" + process $proc$libresoc.v:43668$1532 + assign { } { } + assign $1\fsm_state[2:0] 3'000 + sync always + sync init + update \fsm_state $1\fsm_state[2:0] + end + attribute \src "libresoc.v:43670.13-43670.35" + process $proc$libresoc.v:43670$1533 + assign { } { } + assign $0\fsm_state$503[2:0]$1534 3'000 + sync always + sync init + update \fsm_state$503 $0\fsm_state$503[2:0]$1534 + end + attribute \src "libresoc.v:43868.15-43868.67" + process $proc$libresoc.v:43868$1535 + assign { } { } + assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_bd $1\io_bd[153:0] + end + attribute \src "libresoc.v:43880.15-43880.67" + process $proc$libresoc.v:43880$1536 + assign { } { } + assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_sr $1\io_sr[153:0] + end + attribute \src "libresoc.v:43889.14-43889.41" + process $proc$libresoc.v:43889$1537 + assign { } { } + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:43898.14-43898.51" + process $proc$libresoc.v:43898$1538 + assign { } { } + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:43912.7-43912.32" + process $proc$libresoc.v:43912$1539 + assign { } { } + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:43920.14-43920.47" + process $proc$libresoc.v:43920$1540 + assign { } { } + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:43928.7-43928.40" + process $proc$libresoc.v:43928$1541 + assign { } { } + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:43932.7-43932.45" + process $proc$libresoc.v:43932$1542 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:43936.14-43936.54" + process $proc$libresoc.v:43936$1543 + assign { } { } + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:43942.13-43942.38" + process $proc$libresoc.v:43942$1544 + assign { } { } + assign $1\jtag_wb_datasr__oe[1:0] 2'00 + sync always + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:43950.14-43950.55" + process $proc$libresoc.v:43950$1545 + assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:43958.7-43958.40" + process $proc$libresoc.v:43958$1546 + assign { } { } + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:43962.7-43962.45" + process $proc$libresoc.v:43962$1547 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44392.7-44392.21" + process $proc$libresoc.v:44392$1548 + assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] + end + attribute \src "libresoc.v:44400.13-44400.27" + process $proc$libresoc.v:44400$1549 + assign { } { } + assign $1\sr0_reg[2:0] 3'000 + sync always + sync init + update \sr0_reg $1\sr0_reg[2:0] + end + attribute \src "libresoc.v:44408.7-44408.29" + process $proc$libresoc.v:44408$1550 + assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] + end + attribute \src "libresoc.v:44412.7-44412.34" + process $proc$libresoc.v:44412$1551 + assign { } { } + assign $1\sr0_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:44422.7-44422.21" + process $proc$libresoc.v:44422$1552 + assign { } { } + assign $1\sr5__oe[0:0] 1'0 + sync always + sync init + update \sr5__oe $1\sr5__oe[0:0] + end + attribute \src "libresoc.v:44430.13-44430.27" + process $proc$libresoc.v:44430$1553 + assign { } { } + assign $1\sr5_reg[1:0] 2'00 + sync always + sync init + update \sr5_reg $1\sr5_reg[1:0] + end + attribute \src "libresoc.v:44438.7-44438.29" + process $proc$libresoc.v:44438$1554 + assign { } { } + assign $1\sr5_update_core[0:0] 1'0 + sync always + sync init + update \sr5_update_core $1\sr5_update_core[0:0] + end + attribute \src "libresoc.v:44442.7-44442.34" + process $proc$libresoc.v:44442$1555 + assign { } { } + assign $1\sr5_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:44446.7-44446.26" + process $proc$libresoc.v:44446$1556 + assign { } { } + assign $1\wb_dcache_en[0:0] 1'1 + sync always + sync init + update \wb_dcache_en $1\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:44451.7-44451.26" + process $proc$libresoc.v:44451$1557 + assign { } { } + assign $1\wb_icache_en[0:0] 1'1 + sync always + sync init + update \wb_icache_en $1\wb_icache_en[0:0] + end + attribute \src "libresoc.v:44710.3-44711.41" + process $proc$libresoc.v:44710$1329 + assign { } { } + assign $0\wb_icache_en[0:0] \wb_icache_en$next + sync posedge \clk + update \wb_icache_en $0\wb_icache_en[0:0] + end + attribute \src "libresoc.v:44712.3-44713.41" + process $proc$libresoc.v:44712$1330 + assign { } { } + assign $0\wb_dcache_en[0:0] \wb_dcache_en$next + sync posedge \clk + update \wb_dcache_en $0\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:44714.3-44715.45" + process $proc$libresoc.v:44714$1331 + assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:44716.3-44717.35" + process $proc$libresoc.v:44716$1332 + assign { } { } + assign $0\dmi0__din[63:0] \dmi0__din$next + sync posedge \clk + update \dmi0__din $0\dmi0__din[63:0] + end + attribute \src "libresoc.v:44718.3-44719.45" + process $proc$libresoc.v:44718$1333 + assign { } { } + assign $0\fsm_state$503[2:0]$1334 \fsm_state$503$next + sync posedge \clk + update \fsm_state$503 $0\fsm_state$503[2:0]$1334 + end + attribute \src "libresoc.v:44720.3-44721.41" + process $proc$libresoc.v:44720$1335 + assign { } { } + assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next + sync posedge \clk + update \dmi0__addr_i $0\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:44722.3-44723.51" + process $proc$libresoc.v:44722$1336 + assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:44724.3-44725.45" + process $proc$libresoc.v:44724$1337 + assign { } { } + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:44726.3-44727.35" + process $proc$libresoc.v:44726$1338 + assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] + end + attribute \src "libresoc.v:44728.3-44729.41" + process $proc$libresoc.v:44728$1339 + assign { } { } + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:44730.3-44731.31" + process $proc$libresoc.v:44730$1340 + assign { } { } + assign $0\sr5_reg[1:0] \sr5_reg$next + sync posedge \posjtag_clk + update \sr5_reg $0\sr5_reg[1:0] + end + attribute \src "libresoc.v:44732.3-44733.31" + process $proc$libresoc.v:44732$1341 + assign { } { } + assign $0\sr5__oe[0:0] \sr5__oe$next + sync posedge \clk + update \sr5__oe $0\sr5__oe[0:0] + end + attribute \src "libresoc.v:44734.3-44735.57" + process $proc$libresoc.v:44734$1342 + assign { } { } + assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next + sync posedge \clk + update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:44736.3-44737.47" + process $proc$libresoc.v:44736$1343 + assign { } { } + assign $0\sr5_update_core[0:0] \sr5_update_core$next + sync posedge \clk + update \sr5_update_core $0\sr5_update_core[0:0] + end + attribute \src "libresoc.v:44738.3-44739.47" + process $proc$libresoc.v:44738$1344 + assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:44740.3-44741.47" + process $proc$libresoc.v:44740$1345 + assign { } { } + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:44742.3-44743.73" + process $proc$libresoc.v:44742$1346 + assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44744.3-44745.63" + process $proc$libresoc.v:44744$1347 + assign { } { } + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:44746.3-44747.47" + process $proc$libresoc.v:44746$1348 + assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:44748.3-44749.47" + process $proc$libresoc.v:44748$1349 + assign { } { } + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:44750.3-44751.73" + process $proc$libresoc.v:44750$1350 + assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44752.3-44753.63" + process $proc$libresoc.v:44752$1351 + assign { } { } + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:44754.3-44755.53" + process $proc$libresoc.v:44754$1352 + assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:44756.3-44757.53" + process $proc$libresoc.v:44756$1353 + assign { } { } + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:44758.3-44759.79" + process $proc$libresoc.v:44758$1354 + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44760.3-44761.69" + process $proc$libresoc.v:44760$1355 + assign { } { } + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:44762.3-44763.53" + process $proc$libresoc.v:44762$1356 + assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:44764.3-44765.53" + process $proc$libresoc.v:44764$1357 + assign { } { } + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:44766.3-44767.79" + process $proc$libresoc.v:44766$1358 + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:44768.3-44769.69" + process $proc$libresoc.v:44768$1359 + assign { } { } + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:44770.3-44771.31" + process $proc$libresoc.v:44770$1360 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] + end + attribute \src "libresoc.v:44772.3-44773.31" + process $proc$libresoc.v:44772$1361 + assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] + end + attribute \src "libresoc.v:44774.3-44775.57" + process $proc$libresoc.v:44774$1362 + assign { } { } + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:44776.3-44777.47" + process $proc$libresoc.v:44776$1363 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] + end + attribute \src "libresoc.v:44778.3-44779.27" + process $proc$libresoc.v:44778$1364 + assign { } { } + assign $0\io_bd[153:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[153:0] + end + attribute \src "libresoc.v:44780.3-44781.27" + process $proc$libresoc.v:44780$1365 + assign { } { } + assign $0\io_sr[153:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[153:0] + end + attribute \src "libresoc.v:44817.3-44832.6" + process $proc$libresoc.v:44817$1366 + assign { } { } + assign { } { } + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:44818.5-44818.29" + switch \initial + attribute \src "libresoc.v:44818.9-44818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { \$369 \_idblock_select_id \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [153] + case + assign $1\TAP_tdo[0:0] 1'0 + end + sync always + update \TAP_tdo $0\TAP_tdo[0:0] + end + attribute \src "libresoc.v:44833.3-44841.6" + process $proc$libresoc.v:44833$1367 + assign { } { } + assign { } { } + assign $0\sr0_update_core$next[0:0]$1368 $1\sr0_update_core$next[0:0]$1369 + attribute \src "libresoc.v:44834.5-44834.29" + switch \initial + attribute \src "libresoc.v:44834.9-44834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core$next[0:0]$1369 1'0 + case + assign $1\sr0_update_core$next[0:0]$1369 \sr0_update + end + sync always + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$1368 + end + attribute \src "libresoc.v:44842.3-44850.6" + process $proc$libresoc.v:44842$1370 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$1371 $1\sr0_update_core_prev$next[0:0]$1372 + attribute \src "libresoc.v:44843.5-44843.29" + switch \initial + attribute \src "libresoc.v:44843.9-44843.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$1372 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$1372 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$1371 + end + attribute \src "libresoc.v:44851.3-44867.6" + process $proc$libresoc.v:44851$1373 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$1374 $2\sr0__oe$next[0:0]$1376 + attribute \src "libresoc.v:44852.5-44852.29" + switch \initial + attribute \src "libresoc.v:44852.9-44852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$387 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$1375 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$1375 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$1376 1'0 + case + assign $2\sr0__oe$next[0:0]$1376 $1\sr0__oe$next[0:0]$1375 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$1374 + end + attribute \src "libresoc.v:44868.3-44888.6" + process $proc$libresoc.v:44868$1377 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$1378 $3\sr0_reg$next[2:0]$1381 + attribute \src "libresoc.v:44869.5-44869.29" + switch \initial + attribute \src "libresoc.v:44869.9-44869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$1379 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$1379 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$1380 \sr0__i + case + assign $2\sr0_reg$next[2:0]$1380 $1\sr0_reg$next[2:0]$1379 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$1381 3'000 + case + assign $3\sr0_reg$next[2:0]$1381 $2\sr0_reg$next[2:0]$1380 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$1378 + end + attribute \src "libresoc.v:44889.3-44897.6" + process $proc$libresoc.v:44889$1382 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$1383 $1\jtag_wb_addrsr_update_core$next[0:0]$1384 + attribute \src "libresoc.v:44890.5-44890.29" + switch \initial + attribute \src "libresoc.v:44890.9-44890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$1384 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$1383 + end + attribute \src "libresoc.v:44898.3-44906.6" + process $proc$libresoc.v:44898$1385 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 + attribute \src "libresoc.v:44899.5-44899.29" + switch \initial + attribute \src "libresoc.v:44899.9-44899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$1387 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$1386 + end + attribute \src "libresoc.v:44907.3-44923.6" + process $proc$libresoc.v:44907$1388 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$1389 $2\jtag_wb_addrsr__oe$next[0:0]$1391 + attribute \src "libresoc.v:44908.5-44908.29" + switch \initial + attribute \src "libresoc.v:44908.9-44908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$405 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$1390 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$1391 $1\jtag_wb_addrsr__oe$next[0:0]$1390 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$1389 + end + attribute \src "libresoc.v:44924.3-44944.6" + process $proc$libresoc.v:44924$1392 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$1393 $3\jtag_wb_addrsr_reg$next[28:0]$1396 + attribute \src "libresoc.v:44925.5-44925.29" + switch \initial + attribute \src "libresoc.v:44925.9-44925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$1394 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$1395 $1\jtag_wb_addrsr_reg$next[28:0]$1394 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$1396 $2\jtag_wb_addrsr_reg$next[28:0]$1395 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$1393 + end + attribute \src "libresoc.v:44945.3-44953.6" + process $proc$libresoc.v:44945$1397 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$1398 $1\jtag_wb_datasr_update_core$next[0:0]$1399 + attribute \src "libresoc.v:44946.5-44946.29" + switch \initial + attribute \src "libresoc.v:44946.9-44946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$1399 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$1398 + end + attribute \src "libresoc.v:44954.3-44962.6" + process $proc$libresoc.v:44954$1400 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 + attribute \src "libresoc.v:44955.5-44955.29" + switch \initial + attribute \src "libresoc.v:44955.9-44955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$1402 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$1401 + end + attribute \src "libresoc.v:44963.3-44979.6" + process $proc$libresoc.v:44963$1403 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$1404 $2\jtag_wb_datasr__oe$next[1:0]$1406 + attribute \src "libresoc.v:44964.5-44964.29" + switch \initial + attribute \src "libresoc.v:44964.9-44964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$425 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$1405 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$1405 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$1406 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$1406 $1\jtag_wb_datasr__oe$next[1:0]$1405 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$1404 + end + attribute \src "libresoc.v:44980.3-45000.6" + process $proc$libresoc.v:44980$1407 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$1408 $3\jtag_wb_datasr_reg$next[63:0]$1411 + attribute \src "libresoc.v:44981.5-44981.29" + switch \initial + attribute \src "libresoc.v:44981.9-44981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$1409 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$1409 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$1410 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$1410 $1\jtag_wb_datasr_reg$next[63:0]$1409 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$1411 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$1411 $2\jtag_wb_datasr_reg$next[63:0]$1410 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$1408 + end + attribute \src "libresoc.v:45001.3-45009.6" + process $proc$libresoc.v:45001$1412 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$1413 $1\dmi0_addrsr_update_core$next[0:0]$1414 + attribute \src "libresoc.v:45002.5-45002.29" + switch \initial + attribute \src "libresoc.v:45002.9-45002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$1414 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$1414 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$1413 + end + attribute \src "libresoc.v:45010.3-45018.6" + process $proc$libresoc.v:45010$1415 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 + attribute \src "libresoc.v:45011.5-45011.29" + switch \initial + attribute \src "libresoc.v:45011.9-45011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$1417 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$1416 + end + attribute \src "libresoc.v:45019.3-45035.6" + process $proc$libresoc.v:45019$1418 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$1419 $2\dmi0_addrsr__oe$next[0:0]$1421 + attribute \src "libresoc.v:45020.5-45020.29" + switch \initial + attribute \src "libresoc.v:45020.9-45020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$443 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$1420 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$1420 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$1421 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$1421 $1\dmi0_addrsr__oe$next[0:0]$1420 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$1419 + end + attribute \src "libresoc.v:45036.3-45056.6" + process $proc$libresoc.v:45036$1422 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$1423 $3\dmi0_addrsr_reg$next[7:0]$1426 + attribute \src "libresoc.v:45037.5-45037.29" + switch \initial + attribute \src "libresoc.v:45037.9-45037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$1424 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$1424 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$1425 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$1425 $1\dmi0_addrsr_reg$next[7:0]$1424 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$1426 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$1426 $2\dmi0_addrsr_reg$next[7:0]$1425 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$1423 + end + attribute \src "libresoc.v:45057.3-45065.6" + process $proc$libresoc.v:45057$1427 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$1428 $1\dmi0_datasr_update_core$next[0:0]$1429 + attribute \src "libresoc.v:45058.5-45058.29" + switch \initial + attribute \src "libresoc.v:45058.9-45058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$1429 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$1429 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$1428 + end + attribute \src "libresoc.v:45066.3-45074.6" + process $proc$libresoc.v:45066$1430 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$1431 $1\dmi0_datasr_update_core_prev$next[0:0]$1432 + attribute \src "libresoc.v:45067.5-45067.29" + switch \initial + attribute \src "libresoc.v:45067.9-45067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$1432 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$1431 + end + attribute \src "libresoc.v:45075.3-45091.6" + process $proc$libresoc.v:45075$1433 + assign { } { } + assign { } { } + assign $0\dmi0_datasr__oe$next[1:0]$1434 $2\dmi0_datasr__oe$next[1:0]$1436 + attribute \src "libresoc.v:45076.5-45076.29" + switch \initial + attribute \src "libresoc.v:45076.9-45076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$463 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$1435 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$1435 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$1436 2'00 + case + assign $2\dmi0_datasr__oe$next[1:0]$1436 $1\dmi0_datasr__oe$next[1:0]$1435 + end + sync always + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$1434 + end + attribute \src "libresoc.v:45092.3-45112.6" + process $proc$libresoc.v:45092$1437 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$1438 $3\dmi0_datasr_reg$next[63:0]$1441 + attribute \src "libresoc.v:45093.5-45093.29" + switch \initial + attribute \src "libresoc.v:45093.9-45093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_reg$next[63:0]$1439 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + case + assign $1\dmi0_datasr_reg$next[63:0]$1439 \dmi0_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$1440 \dmi0_datasr__i + case + assign $2\dmi0_datasr_reg$next[63:0]$1440 $1\dmi0_datasr_reg$next[63:0]$1439 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$1441 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$1441 $2\dmi0_datasr_reg$next[63:0]$1440 + end + sync always + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$1438 + end + attribute \src "libresoc.v:45113.3-45121.6" + process $proc$libresoc.v:45113$1442 + assign { } { } + assign { } { } + assign $0\sr5_update_core$next[0:0]$1443 $1\sr5_update_core$next[0:0]$1444 + attribute \src "libresoc.v:45114.5-45114.29" + switch \initial + attribute \src "libresoc.v:45114.9-45114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core$next[0:0]$1444 1'0 + case + assign $1\sr5_update_core$next[0:0]$1444 \sr5_update + end + sync always + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$1443 + end + attribute \src "libresoc.v:45122.3-45130.6" + process $proc$libresoc.v:45122$1445 + assign { } { } + assign { } { } + assign $0\sr5_update_core_prev$next[0:0]$1446 $1\sr5_update_core_prev$next[0:0]$1447 + attribute \src "libresoc.v:45123.5-45123.29" + switch \initial + attribute \src "libresoc.v:45123.9-45123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core_prev$next[0:0]$1447 1'0 + case + assign $1\sr5_update_core_prev$next[0:0]$1447 \sr5_update_core + end + sync always + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$1446 + end + attribute \src "libresoc.v:45131.3-45147.6" + process $proc$libresoc.v:45131$1448 + assign { } { } + assign { } { } + assign $0\sr5__oe$next[0:0]$1449 $2\sr5__oe$next[0:0]$1451 + attribute \src "libresoc.v:45132.5-45132.29" + switch \initial + attribute \src "libresoc.v:45132.9-45132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$481 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__oe$next[0:0]$1450 \sr5_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr5__oe$next[0:0]$1450 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5__oe$next[0:0]$1451 1'0 + case + assign $2\sr5__oe$next[0:0]$1451 $1\sr5__oe$next[0:0]$1450 + end + sync always + update \sr5__oe$next $0\sr5__oe$next[0:0]$1449 + end + attribute \src "libresoc.v:45148.3-45168.6" + process $proc$libresoc.v:45148$1452 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr5_reg$next[1:0]$1453 $3\sr5_reg$next[1:0]$1456 + attribute \src "libresoc.v:45149.5-45149.29" + switch \initial + attribute \src "libresoc.v:45149.9-45149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr5_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_reg$next[1:0]$1454 { \TAP_bus__tdi \sr5_reg [1] } + case + assign $1\sr5_reg$next[1:0]$1454 \sr5_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr5_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5_reg$next[1:0]$1455 \sr5__i + case + assign $2\sr5_reg$next[1:0]$1455 $1\sr5_reg$next[1:0]$1454 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr5_reg$next[1:0]$1456 2'00 + case + assign $3\sr5_reg$next[1:0]$1456 $2\sr5_reg$next[1:0]$1455 + end + sync always + update \sr5_reg$next $0\sr5_reg$next[1:0]$1453 + end + attribute \src "libresoc.v:45169.3-45195.6" + process $proc$libresoc.v:45169$1457 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:45170.5-45170.29" + switch \initial + attribute \src "libresoc.v:45170.9-45170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" + switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 6'-----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'----1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'---1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'--1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'-1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'1----- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:45196.3-45228.6" + process $proc$libresoc.v:45196$1458 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$1459 $4\jtag_wb__adr$next[28:0]$1463 + attribute \src "libresoc.v:45197.5-45197.29" + switch \initial + attribute \src "libresoc.v:45197.9-45197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$1460 $2\jtag_wb__adr$next[28:0]$1461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$1461 \$495 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$1461 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$1460 $3\jtag_wb__adr$next[28:0]$1462 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$1462 \$498 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$1462 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$1460 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$1463 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$1463 $1\jtag_wb__adr$next[28:0]$1460 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$1459 + end + attribute \src "libresoc.v:45229.3-45281.6" + process $proc$libresoc.v:45229$1464 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$1465 $5\fsm_state$next[2:0]$1470 + attribute \src "libresoc.v:45230.5-45230.29" + switch \initial + attribute \src "libresoc.v:45230.9-45230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 $2\fsm_state$next[2:0]$1467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$1467 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$1467 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$1467 3'010 + case + assign $2\fsm_state$next[2:0]$1467 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 $3\fsm_state$next[2:0]$1468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$1468 3'000 + case + assign $3\fsm_state$next[2:0]$1468 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$1466 $4\fsm_state$next[2:0]$1469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$1469 3'001 + case + assign $4\fsm_state$next[2:0]$1469 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$1466 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$1470 3'000 + case + assign $5\fsm_state$next[2:0]$1470 $1\fsm_state$next[2:0]$1466 + end + sync always + update \fsm_state$next $0\fsm_state$next[2:0]$1465 + end + attribute \src "libresoc.v:45282.3-45308.6" + process $proc$libresoc.v:45282$1471 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$1472 $3\jtag_wb__dat_w$next[63:0]$1475 + attribute \src "libresoc.v:45283.5-45283.29" + switch \initial + attribute \src "libresoc.v:45283.9-45283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$1473 $2\jtag_wb__dat_w$next[63:0]$1474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$1474 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$1473 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$1475 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$1475 $1\jtag_wb__dat_w$next[63:0]$1473 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$1472 + end + attribute \src "libresoc.v:45309.3-45329.6" + process $proc$libresoc.v:45309$1476 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$1477 $3\jtag_wb_datasr__i$next[63:0]$1480 + attribute \src "libresoc.v:45310.5-45310.29" + switch \initial + attribute \src "libresoc.v:45310.9-45310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$1478 $2\jtag_wb_datasr__i$next[63:0]$1479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$1479 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$1478 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$1480 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$1480 $1\jtag_wb_datasr__i$next[63:0]$1478 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$1477 + end + attribute \src "libresoc.v:45330.3-45362.6" + process $proc$libresoc.v:45330$1481 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__addr_i$next[3:0]$1482 $4\dmi0__addr_i$next[3:0]$1486 + attribute \src "libresoc.v:45331.5-45331.29" + switch \initial + attribute \src "libresoc.v:45331.9-45331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$1483 $2\dmi0__addr_i$next[3:0]$1484 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$1484 \$512 [3:0] + case + assign $2\dmi0__addr_i$next[3:0]$1484 \dmi0__addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$1483 $3\dmi0__addr_i$next[3:0]$1485 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__addr_i$next[3:0]$1485 \$515 [3:0] + case + assign $3\dmi0__addr_i$next[3:0]$1485 \dmi0__addr_i + end + case + assign $1\dmi0__addr_i$next[3:0]$1483 \dmi0__addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0__addr_i$next[3:0]$1486 4'0000 + case + assign $4\dmi0__addr_i$next[3:0]$1486 $1\dmi0__addr_i$next[3:0]$1483 + end + sync always + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$1482 + end + attribute \src "libresoc.v:45363.3-45415.6" + process $proc$libresoc.v:45363$1487 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$503$next[2:0]$1488 $5\fsm_state$503$next[2:0]$1493 + attribute \src "libresoc.v:45364.5-45364.29" + switch \initial + attribute \src "libresoc.v:45364.9-45364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 $2\fsm_state$503$next[2:0]$1490 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$503$next[2:0]$1490 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$503$next[2:0]$1490 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$503$next[2:0]$1490 3'010 + case + assign $2\fsm_state$503$next[2:0]$1490 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 $3\fsm_state$503$next[2:0]$1491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$503$next[2:0]$1491 3'000 + case + assign $3\fsm_state$503$next[2:0]$1491 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$503$next[2:0]$1489 $4\fsm_state$503$next[2:0]$1492 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$503$next[2:0]$1492 3'001 + case + assign $4\fsm_state$503$next[2:0]$1492 \fsm_state$503 + end + case + assign $1\fsm_state$503$next[2:0]$1489 \fsm_state$503 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$503$next[2:0]$1493 3'000 + case + assign $5\fsm_state$503$next[2:0]$1493 $1\fsm_state$503$next[2:0]$1489 + end + sync always + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$1488 + end + attribute \src "libresoc.v:45416.3-45442.6" + process $proc$libresoc.v:45416$1494 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__din$next[63:0]$1495 $3\dmi0__din$next[63:0]$1498 + attribute \src "libresoc.v:45417.5-45417.29" + switch \initial + attribute \src "libresoc.v:45417.9-45417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__din$next[63:0]$1496 $2\dmi0__din$next[63:0]$1497 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0__din$next[63:0]$1497 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0__din$next[63:0]$1497 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0__din$next[63:0]$1497 \dmi0_datasr__o + case + assign $2\dmi0__din$next[63:0]$1497 \dmi0__din + end + case + assign $1\dmi0__din$next[63:0]$1496 \dmi0__din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__din$next[63:0]$1498 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0__din$next[63:0]$1498 $1\dmi0__din$next[63:0]$1496 + end + sync always + update \dmi0__din$next $0\dmi0__din$next[63:0]$1495 + end + attribute \src "libresoc.v:45443.3-45463.6" + process $proc$libresoc.v:45443$1499 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$1500 $3\dmi0_datasr__i$next[63:0]$1503 + attribute \src "libresoc.v:45444.5-45444.29" + switch \initial + attribute \src "libresoc.v:45444.9-45444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$1501 $2\dmi0_datasr__i$next[63:0]$1502 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0__dout + case + assign $2\dmi0_datasr__i$next[63:0]$1502 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$1501 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr__i$next[63:0]$1503 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr__i$next[63:0]$1503 $1\dmi0_datasr__i$next[63:0]$1501 + end + sync always + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$1500 + end + attribute \src "libresoc.v:45464.3-45482.6" + process $proc$libresoc.v:45464$1504 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\wb_dcache_en$next[0:0]$1505 $2\wb_dcache_en$next[0:0]$1509 + assign $0\wb_icache_en$next[0:0]$1506 $2\wb_icache_en$next[0:0]$1510 + attribute \src "libresoc.v:45465.5-45465.29" + switch \initial + attribute \src "libresoc.v:45465.9-45465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" + switch \sr5__oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\wb_dcache_en$next[0:0]$1507 $1\wb_icache_en$next[0:0]$1508 } \sr5__o + case + assign $1\wb_dcache_en$next[0:0]$1507 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$1508 \wb_icache_en + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\wb_icache_en$next[0:0]$1510 1'1 + assign $2\wb_dcache_en$next[0:0]$1509 1'1 + case + assign $2\wb_dcache_en$next[0:0]$1509 $1\wb_dcache_en$next[0:0]$1507 + assign $2\wb_icache_en$next[0:0]$1510 $1\wb_icache_en$next[0:0]$1508 + end + sync always + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$1505 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$1506 + end + attribute \src "libresoc.v:45483.3-45492.6" + process $proc$libresoc.v:45483$1511 + assign { } { } + assign { } { } + assign $0\sr5__i[1:0] $1\sr5__i[1:0] + attribute \src "libresoc.v:45484.5-45484.29" + switch \initial + attribute \src "libresoc.v:45484.9-45484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" + switch \sr5__ie + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } + case + assign $1\sr5__i[1:0] 2'00 + end + sync always + update \sr5__i $0\sr5__i[1:0] + end + attribute \src "libresoc.v:45493.3-45510.6" + process $proc$libresoc.v:45493$1512 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[153:0]$1513 $2\io_sr$next[153:0]$1515 + attribute \src "libresoc.v:45494.5-45494.29" + switch \initial + attribute \src "libresoc.v:45494.9-45494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[153:0]$1514 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[153:0]$1514 { \io_sr [152:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[153:0]$1514 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[153:0]$1515 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[153:0]$1515 $1\io_sr$next[153:0]$1514 + end + sync always + update \io_sr$next $0\io_sr$next[153:0]$1513 + end + attribute \src "libresoc.v:45511.3-45531.6" + process $proc$libresoc.v:45511$1516 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_bd$next[153:0]$1517 $2\io_bd$next[153:0]$1519 + attribute \src "libresoc.v:45512.5-45512.29" + switch \initial + attribute \src "libresoc.v:45512.9-45512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[153:0]$1518 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[153:0]$1518 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[153:0]$1518 \io_sr + case + assign $1\io_bd$next[153:0]$1518 \io_bd + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[153:0]$1519 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$1519 $1\io_bd$next[153:0]$1518 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$1517 + end + connect \$9 $eq$libresoc.v:44454$1072_Y + connect \$99 $ternary$libresoc.v:44455$1073_Y + connect \$101 $ternary$libresoc.v:44456$1074_Y + connect \$103 $ternary$libresoc.v:44457$1075_Y + connect \$105 $ternary$libresoc.v:44458$1076_Y + connect \$107 $ternary$libresoc.v:44459$1077_Y + connect \$109 $ternary$libresoc.v:44460$1078_Y + connect \$111 $ternary$libresoc.v:44461$1079_Y + connect \$113 $ternary$libresoc.v:44462$1080_Y + connect \$115 $ternary$libresoc.v:44463$1081_Y + connect \$117 $ternary$libresoc.v:44464$1082_Y + connect \$11 $eq$libresoc.v:44465$1083_Y + connect \$119 $ternary$libresoc.v:44466$1084_Y + connect \$121 $ternary$libresoc.v:44467$1085_Y + connect \$123 $ternary$libresoc.v:44468$1086_Y + connect \$125 $ternary$libresoc.v:44469$1087_Y + connect \$127 $ternary$libresoc.v:44470$1088_Y + connect \$129 $ternary$libresoc.v:44471$1089_Y + connect \$131 $ternary$libresoc.v:44472$1090_Y + connect \$133 $ternary$libresoc.v:44473$1091_Y + connect \$135 $ternary$libresoc.v:44474$1092_Y + connect \$137 $ternary$libresoc.v:44475$1093_Y + connect \$13 $eq$libresoc.v:44476$1094_Y + connect \$139 $ternary$libresoc.v:44477$1095_Y + connect \$141 $ternary$libresoc.v:44478$1096_Y + connect \$143 $ternary$libresoc.v:44479$1097_Y + connect \$145 $ternary$libresoc.v:44480$1098_Y + connect \$147 $ternary$libresoc.v:44481$1099_Y + connect \$149 $ternary$libresoc.v:44482$1100_Y + connect \$151 $ternary$libresoc.v:44483$1101_Y + connect \$153 $ternary$libresoc.v:44484$1102_Y + connect \$155 $ternary$libresoc.v:44485$1103_Y + connect \$157 $ternary$libresoc.v:44486$1104_Y + connect \$15 $or$libresoc.v:44487$1105_Y + connect \$159 $ternary$libresoc.v:44488$1106_Y + connect \$161 $ternary$libresoc.v:44489$1107_Y + connect \$163 $ternary$libresoc.v:44490$1108_Y + connect \$165 $ternary$libresoc.v:44491$1109_Y + connect \$167 $ternary$libresoc.v:44492$1110_Y + connect \$169 $ternary$libresoc.v:44493$1111_Y + connect \$171 $ternary$libresoc.v:44494$1112_Y + connect \$173 $ternary$libresoc.v:44495$1113_Y + connect \$175 $ternary$libresoc.v:44496$1114_Y + connect \$177 $ternary$libresoc.v:44497$1115_Y + connect \$17 $and$libresoc.v:44498$1116_Y + connect \$179 $ternary$libresoc.v:44499$1117_Y + connect \$181 $ternary$libresoc.v:44500$1118_Y + connect \$183 $ternary$libresoc.v:44501$1119_Y + connect \$185 $ternary$libresoc.v:44502$1120_Y + connect \$187 $ternary$libresoc.v:44503$1121_Y + connect \$189 $ternary$libresoc.v:44504$1122_Y + connect \$191 $ternary$libresoc.v:44505$1123_Y + connect \$193 $ternary$libresoc.v:44506$1124_Y + connect \$195 $ternary$libresoc.v:44507$1125_Y + connect \$197 $ternary$libresoc.v:44508$1126_Y + connect \$1 $eq$libresoc.v:44509$1127_Y + connect \$19 $eq$libresoc.v:44510$1128_Y + connect \$199 $ternary$libresoc.v:44511$1129_Y + connect \$201 $ternary$libresoc.v:44512$1130_Y + connect \$203 $ternary$libresoc.v:44513$1131_Y + connect \$205 $ternary$libresoc.v:44514$1132_Y + connect \$207 $ternary$libresoc.v:44515$1133_Y + connect \$209 $ternary$libresoc.v:44516$1134_Y + connect \$211 $ternary$libresoc.v:44517$1135_Y + connect \$213 $ternary$libresoc.v:44518$1136_Y + connect \$215 $ternary$libresoc.v:44519$1137_Y + connect \$217 $ternary$libresoc.v:44520$1138_Y + connect \$21 $eq$libresoc.v:44521$1139_Y + connect \$219 $ternary$libresoc.v:44522$1140_Y + connect \$221 $ternary$libresoc.v:44523$1141_Y + connect \$223 $ternary$libresoc.v:44524$1142_Y + connect \$225 $ternary$libresoc.v:44525$1143_Y + connect \$227 $ternary$libresoc.v:44526$1144_Y + connect \$229 $ternary$libresoc.v:44527$1145_Y + connect \$231 $ternary$libresoc.v:44528$1146_Y + connect \$233 $ternary$libresoc.v:44529$1147_Y + connect \$235 $ternary$libresoc.v:44530$1148_Y + connect \$237 $ternary$libresoc.v:44531$1149_Y + connect \$23 $or$libresoc.v:44532$1150_Y + connect \$239 $ternary$libresoc.v:44533$1151_Y + connect \$241 $ternary$libresoc.v:44534$1152_Y + connect \$243 $ternary$libresoc.v:44535$1153_Y + connect \$245 $ternary$libresoc.v:44536$1154_Y + connect \$247 $ternary$libresoc.v:44537$1155_Y + connect \$249 $ternary$libresoc.v:44538$1156_Y + connect \$251 $ternary$libresoc.v:44539$1157_Y + connect \$253 $ternary$libresoc.v:44540$1158_Y + connect \$255 $ternary$libresoc.v:44541$1159_Y + connect \$257 $ternary$libresoc.v:44542$1160_Y + connect \$25 $eq$libresoc.v:44543$1161_Y + connect \$259 $ternary$libresoc.v:44544$1162_Y + connect \$261 $ternary$libresoc.v:44545$1163_Y + connect \$263 $ternary$libresoc.v:44546$1164_Y + connect \$265 $ternary$libresoc.v:44547$1165_Y + connect \$267 $ternary$libresoc.v:44548$1166_Y + connect \$269 $ternary$libresoc.v:44549$1167_Y + connect \$271 $ternary$libresoc.v:44550$1168_Y + connect \$273 $ternary$libresoc.v:44551$1169_Y + connect \$275 $ternary$libresoc.v:44552$1170_Y + connect \$277 $ternary$libresoc.v:44553$1171_Y + connect \$27 $or$libresoc.v:44554$1172_Y + connect \$279 $ternary$libresoc.v:44555$1173_Y + connect \$281 $ternary$libresoc.v:44556$1174_Y + connect \$283 $ternary$libresoc.v:44557$1175_Y + connect \$285 $ternary$libresoc.v:44558$1176_Y + connect \$287 $ternary$libresoc.v:44559$1177_Y + connect \$289 $ternary$libresoc.v:44560$1178_Y + connect \$291 $ternary$libresoc.v:44561$1179_Y + connect \$293 $ternary$libresoc.v:44562$1180_Y + connect \$295 $ternary$libresoc.v:44563$1181_Y + connect \$297 $ternary$libresoc.v:44564$1182_Y + connect \$29 $and$libresoc.v:44565$1183_Y + connect \$299 $ternary$libresoc.v:44566$1184_Y + connect \$301 $ternary$libresoc.v:44567$1185_Y + connect \$303 $ternary$libresoc.v:44568$1186_Y + connect \$305 $ternary$libresoc.v:44569$1187_Y + connect \$307 $ternary$libresoc.v:44570$1188_Y + connect \$309 $ternary$libresoc.v:44571$1189_Y + connect \$311 $ternary$libresoc.v:44572$1190_Y + connect \$313 $ternary$libresoc.v:44573$1191_Y + connect \$315 $ternary$libresoc.v:44574$1192_Y + connect \$317 $ternary$libresoc.v:44575$1193_Y + connect \$31 $and$libresoc.v:44576$1194_Y + connect \$319 $ternary$libresoc.v:44577$1195_Y + connect \$321 $ternary$libresoc.v:44578$1196_Y + connect \$323 $ternary$libresoc.v:44579$1197_Y + connect \$325 $ternary$libresoc.v:44580$1198_Y + connect \$327 $ternary$libresoc.v:44581$1199_Y + connect \$329 $ternary$libresoc.v:44582$1200_Y + connect \$331 $ternary$libresoc.v:44583$1201_Y + connect \$333 $ternary$libresoc.v:44584$1202_Y + connect \$335 $ternary$libresoc.v:44585$1203_Y + connect \$337 $ternary$libresoc.v:44586$1204_Y + connect \$33 $eq$libresoc.v:44587$1205_Y + connect \$339 $ternary$libresoc.v:44588$1206_Y + connect \$341 $ternary$libresoc.v:44589$1207_Y + connect \$343 $ternary$libresoc.v:44590$1208_Y + connect \$345 $ternary$libresoc.v:44591$1209_Y + connect \$347 $ternary$libresoc.v:44592$1210_Y + connect \$349 $ternary$libresoc.v:44593$1211_Y + connect \$351 $ternary$libresoc.v:44594$1212_Y + connect \$353 $ternary$libresoc.v:44595$1213_Y + connect \$355 $ternary$libresoc.v:44596$1214_Y + connect \$357 $ternary$libresoc.v:44597$1215_Y + connect \$35 $eq$libresoc.v:44598$1216_Y + connect \$359 $eq$libresoc.v:44599$1217_Y + connect \$361 $eq$libresoc.v:44600$1218_Y + connect \$363 $or$libresoc.v:44601$1219_Y + connect \$365 $eq$libresoc.v:44602$1220_Y + connect \$367 $or$libresoc.v:44603$1221_Y + connect \$369 $and$libresoc.v:44604$1222_Y + connect \$371 $eq$libresoc.v:44605$1223_Y + connect \$373 $ne$libresoc.v:44606$1224_Y + connect \$375 $and$libresoc.v:44607$1225_Y + connect \$377 $ne$libresoc.v:44608$1226_Y + connect \$37 $or$libresoc.v:44609$1227_Y + connect \$379 $and$libresoc.v:44610$1228_Y + connect \$381 $ne$libresoc.v:44611$1229_Y + connect \$383 $and$libresoc.v:44612$1230_Y + connect \$385 $not$libresoc.v:44613$1231_Y + connect \$387 $and$libresoc.v:44614$1232_Y + connect \$389 $eq$libresoc.v:44615$1233_Y + connect \$391 $ne$libresoc.v:44616$1234_Y + connect \$393 $and$libresoc.v:44617$1235_Y + connect \$395 $ne$libresoc.v:44618$1236_Y + connect \$397 $and$libresoc.v:44619$1237_Y + connect \$3 $eq$libresoc.v:44620$1238_Y + connect \$39 $eq$libresoc.v:44621$1239_Y + connect \$399 $ne$libresoc.v:44622$1240_Y + connect \$401 $and$libresoc.v:44623$1241_Y + connect \$403 $not$libresoc.v:44624$1242_Y + connect \$405 $and$libresoc.v:44625$1243_Y + connect \$407 $eq$libresoc.v:44626$1244_Y + connect \$409 $eq$libresoc.v:44627$1245_Y + connect \$411 $ne$libresoc.v:44628$1246_Y + connect \$413 $and$libresoc.v:44629$1247_Y + connect \$415 $ne$libresoc.v:44630$1248_Y + connect \$417 $and$libresoc.v:44631$1249_Y + connect \$41 $or$libresoc.v:44632$1250_Y + connect \$419 $ne$libresoc.v:44633$1251_Y + connect \$421 $and$libresoc.v:44634$1252_Y + connect \$423 $not$libresoc.v:44635$1253_Y + connect \$425 $and$libresoc.v:44636$1254_Y + connect \$427 $eq$libresoc.v:44637$1255_Y + connect \$429 $ne$libresoc.v:44638$1256_Y + connect \$431 $and$libresoc.v:44639$1257_Y + connect \$433 $ne$libresoc.v:44640$1258_Y + connect \$435 $and$libresoc.v:44641$1259_Y + connect \$437 $ne$libresoc.v:44642$1260_Y + connect \$43 $and$libresoc.v:44643$1261_Y + connect \$439 $and$libresoc.v:44644$1262_Y + connect \$441 $not$libresoc.v:44645$1263_Y + connect \$443 $and$libresoc.v:44646$1264_Y + connect \$445 $eq$libresoc.v:44647$1265_Y + connect \$447 $eq$libresoc.v:44648$1266_Y + connect \$449 $ne$libresoc.v:44649$1267_Y + connect \$451 $and$libresoc.v:44650$1268_Y + connect \$453 $ne$libresoc.v:44651$1269_Y + connect \$455 $and$libresoc.v:44652$1270_Y + connect \$457 $ne$libresoc.v:44653$1271_Y + connect \$45 $and$libresoc.v:44654$1272_Y + connect \$459 $and$libresoc.v:44655$1273_Y + connect \$461 $not$libresoc.v:44656$1274_Y + connect \$463 $and$libresoc.v:44657$1275_Y + connect \$465 $eq$libresoc.v:44658$1276_Y + connect \$467 $ne$libresoc.v:44659$1277_Y + connect \$469 $and$libresoc.v:44660$1278_Y + connect \$471 $ne$libresoc.v:44661$1279_Y + connect \$473 $and$libresoc.v:44662$1280_Y + connect \$475 $ne$libresoc.v:44663$1281_Y + connect \$477 $and$libresoc.v:44664$1282_Y + connect \$47 $eq$libresoc.v:44665$1283_Y + connect \$479 $not$libresoc.v:44666$1284_Y + connect \$481 $and$libresoc.v:44667$1285_Y + connect \$484 $eq$libresoc.v:44668$1286_Y + connect \$483 $not$libresoc.v:44669$1287_Y + connect \$487 $eq$libresoc.v:44670$1288_Y + connect \$489 $eq$libresoc.v:44671$1289_Y + connect \$491 $or$libresoc.v:44672$1290_Y + connect \$493 $eq$libresoc.v:44673$1291_Y + connect \$496 $add$libresoc.v:44674$1292_Y + connect \$49 $eq$libresoc.v:44675$1293_Y + connect \$499 $add$libresoc.v:44676$1294_Y + connect \$501 $pos$libresoc.v:44677$1296_Y + connect \$504 $eq$libresoc.v:44678$1297_Y + connect \$506 $eq$libresoc.v:44679$1298_Y + connect \$508 $or$libresoc.v:44680$1299_Y + connect \$510 $eq$libresoc.v:44681$1300_Y + connect \$513 $add$libresoc.v:44682$1301_Y + connect \$516 $add$libresoc.v:44683$1302_Y + connect \$51 $ternary$libresoc.v:44684$1303_Y + connect \$53 $ternary$libresoc.v:44685$1304_Y + connect \$55 $ternary$libresoc.v:44686$1305_Y + connect \$57 $ternary$libresoc.v:44687$1306_Y + connect \$5 $or$libresoc.v:44688$1307_Y + connect \$59 $ternary$libresoc.v:44689$1308_Y + connect \$61 $ternary$libresoc.v:44690$1309_Y + connect \$63 $ternary$libresoc.v:44691$1310_Y + connect \$65 $ternary$libresoc.v:44692$1311_Y + connect \$67 $ternary$libresoc.v:44693$1312_Y + connect \$69 $ternary$libresoc.v:44694$1313_Y + connect \$71 $ternary$libresoc.v:44695$1314_Y + connect \$73 $ternary$libresoc.v:44696$1315_Y + connect \$75 $ternary$libresoc.v:44697$1316_Y + connect \$77 $ternary$libresoc.v:44698$1317_Y + connect \$7 $and$libresoc.v:44699$1318_Y + connect \$79 $ternary$libresoc.v:44700$1319_Y + connect \$81 $ternary$libresoc.v:44701$1320_Y + connect \$83 $ternary$libresoc.v:44702$1321_Y + connect \$85 $ternary$libresoc.v:44703$1322_Y + connect \$87 $ternary$libresoc.v:44704$1323_Y + connect \$89 $ternary$libresoc.v:44705$1324_Y + connect \$91 $ternary$libresoc.v:44706$1325_Y + connect \$93 $ternary$libresoc.v:44707$1326_Y + connect \$95 $ternary$libresoc.v:44708$1327_Y + connect \$97 $ternary$libresoc.v:44709$1328_Y + connect \$495 \$496 + connect \$498 \$499 + connect \$512 \$513 + connect \$515 \$516 + connect \sr5__ie 1'0 + connect \sr0__i \sr0__o + connect \dmi0__we_i \$510 + connect \dmi0__req_i \$508 + connect \dmi0_addrsr__i \$501 + connect \jtag_wb__we \$493 + connect \jtag_wb__stb \$491 + connect \jtag_wb__cyc \$483 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \sr5_update \$477 + connect \sr5_shift \$473 + connect \sr5_capture \$469 + connect \sr5_isir \$465 + connect \sr5__o \sr5_reg + connect \dmi0_datasr_update \$459 + connect \dmi0_datasr_shift \$455 + connect \dmi0_datasr_capture \$451 + connect \dmi0_datasr_isir { \$447 \$445 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$439 + connect \dmi0_addrsr_shift \$435 + connect \dmi0_addrsr_capture \$431 + connect \dmi0_addrsr_isir \$427 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$421 + connect \jtag_wb_datasr_shift \$417 + connect \jtag_wb_datasr_capture \$413 + connect \jtag_wb_datasr_isir { \$409 \$407 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$401 + connect \jtag_wb_addrsr_shift \$397 + connect \jtag_wb_addrsr_capture \$393 + connect \jtag_wb_addrsr_isir \$389 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$383 + connect \sr0_shift \$379 + connect \sr0_capture \$375 + connect \sr0_isir \$371 + connect \sr0__o \sr0_reg + connect \sdr_dq_15__pad__oe \$357 + connect \sdr_dq_15__pad__o \$355 + connect \sdr_dq_15__core__i \$353 + connect \sdr_dq_14__pad__oe \$351 + connect \sdr_dq_14__pad__o \$349 + connect \sdr_dq_14__core__i \$347 + connect \sdr_dq_13__pad__oe \$345 + connect \sdr_dq_13__pad__o \$343 + connect \sdr_dq_13__core__i \$341 + connect \sdr_dq_12__pad__oe \$339 + connect \sdr_dq_12__pad__o \$337 + connect \sdr_dq_12__core__i \$335 + connect \sdr_dq_11__pad__oe \$333 + connect \sdr_dq_11__pad__o \$331 + connect \sdr_dq_11__core__i \$329 + connect \sdr_dq_10__pad__oe \$327 + connect \sdr_dq_10__pad__o \$325 + connect \sdr_dq_10__core__i \$323 + connect \sdr_dq_9__pad__oe \$321 + connect \sdr_dq_9__pad__o \$319 + connect \sdr_dq_9__core__i \$317 + connect \sdr_dq_8__pad__oe \$315 + connect \sdr_dq_8__pad__o \$313 + connect \sdr_dq_8__core__i \$311 + connect \sdr_dm_1__pad__oe \$309 + connect \sdr_dm_1__pad__o \$307 + connect \sdr_dm_1__core__i \$305 + connect \sdr_a_12__pad__o \$303 + connect \sdr_a_11__pad__o \$301 + connect \sdr_a_10__pad__o \$299 + connect \sdr_cs_n__pad__o \$297 + connect \sdr_we_n__pad__o \$295 + connect \sdr_cas_n__pad__o \$293 + connect \sdr_ras_n__pad__o \$291 + connect \sdr_cke__pad__o \$289 + connect \sdr_clock__pad__o \$287 + connect \sdr_ba_1__pad__o \$285 + connect \sdr_ba_0__pad__o \$283 + connect \sdr_a_9__pad__o \$281 + connect \sdr_a_8__pad__o \$279 + connect \sdr_a_7__pad__o \$277 + connect \sdr_a_6__pad__o \$275 + connect \sdr_a_5__pad__o \$273 + connect \sdr_a_4__pad__o \$271 + connect \sdr_a_3__pad__o \$269 + connect \sdr_a_2__pad__o \$267 + connect \sdr_a_1__pad__o \$265 + connect \sdr_a_0__pad__o \$263 + connect \sdr_dq_7__pad__oe \$261 + connect \sdr_dq_7__pad__o \$259 + connect \sdr_dq_7__core__i \$257 + connect \sdr_dq_6__pad__oe \$255 + connect \sdr_dq_6__pad__o \$253 + connect \sdr_dq_6__core__i \$251 + connect \sdr_dq_5__pad__oe \$249 + connect \sdr_dq_5__pad__o \$247 + connect \sdr_dq_5__core__i \$245 + connect \sdr_dq_4__pad__oe \$243 + connect \sdr_dq_4__pad__o \$241 + connect \sdr_dq_4__core__i \$239 + connect \sdr_dq_3__pad__oe \$237 + connect \sdr_dq_3__pad__o \$235 + connect \sdr_dq_3__core__i \$233 + connect \sdr_dq_2__pad__oe \$231 + connect \sdr_dq_2__pad__o \$229 + connect \sdr_dq_2__core__i \$227 + connect \sdr_dq_1__pad__oe \$225 + connect \sdr_dq_1__pad__o \$223 + connect \sdr_dq_1__core__i \$221 + connect \sdr_dq_0__pad__oe \$219 + connect \sdr_dq_0__pad__o \$217 + connect \sdr_dq_0__core__i \$215 + connect \sdr_dm_0__pad__o \$213 + connect \sd0_data3__pad__oe \$211 + connect \sd0_data3__pad__o \$209 + connect \sd0_data3__core__i \$207 + connect \sd0_data2__pad__oe \$205 + connect \sd0_data2__pad__o \$203 + connect \sd0_data2__core__i \$201 + connect \sd0_data1__pad__oe \$199 + connect \sd0_data1__pad__o \$197 + connect \sd0_data1__core__i \$195 + connect \sd0_data0__pad__oe \$193 + connect \sd0_data0__pad__o \$191 + connect \sd0_data0__core__i \$189 + connect \sd0_clk__pad__o \$187 + connect \sd0_cmd__pad__oe \$185 + connect \sd0_cmd__pad__o \$183 + connect \sd0_cmd__core__i \$181 + connect \pwm_1__pad__o \$179 + connect \pwm_0__pad__o \$177 + connect \mtwi_scl__pad__o \$175 + connect \mtwi_sda__pad__oe \$173 + connect \mtwi_sda__pad__o \$171 + connect \mtwi_sda__core__i \$169 + connect \mspi1_miso__core__i \$167 + connect \mspi1_mosi__pad__o \$165 + connect \mspi1_cs_n__pad__o \$163 + connect \mspi1_clk__pad__o \$161 + connect \mspi0_miso__core__i \$159 + connect \mspi0_mosi__pad__o \$157 + connect \mspi0_cs_n__pad__o \$155 + connect \mspi0_clk__pad__o \$153 + connect \gpio_s7__pad__oe \$151 + connect \gpio_s7__pad__o \$149 + connect \gpio_s7__core__i \$147 + connect \gpio_s6__pad__oe \$145 + connect \gpio_s6__pad__o \$143 + connect \gpio_s6__core__i \$141 + connect \gpio_s5__pad__oe \$139 + connect \gpio_s5__pad__o \$137 + connect \gpio_s5__core__i \$135 + connect \gpio_s4__pad__oe \$133 + connect \gpio_s4__pad__o \$131 + connect \gpio_s4__core__i \$129 + connect \gpio_s3__pad__oe \$127 + connect \gpio_s3__pad__o \$125 + connect \gpio_s3__core__i \$123 + connect \gpio_s2__pad__oe \$121 + connect \gpio_s2__pad__o \$119 + connect \gpio_s2__core__i \$117 + connect \gpio_s1__pad__oe \$115 + connect \gpio_s1__pad__o \$113 + connect \gpio_s1__core__i \$111 + connect \gpio_s0__pad__oe \$109 + connect \gpio_s0__pad__o \$107 + connect \gpio_s0__core__i \$105 + connect \gpio_e15__pad__oe \$103 + connect \gpio_e15__pad__o \$101 + connect \gpio_e15__core__i \$99 + connect \gpio_e14__pad__oe \$97 + connect \gpio_e14__pad__o \$95 + connect \gpio_e14__core__i \$93 + connect \gpio_e13__pad__oe \$91 + connect \gpio_e13__pad__o \$89 + connect \gpio_e13__core__i \$87 + connect \gpio_e12__pad__oe \$85 + connect \gpio_e12__pad__o \$83 + connect \gpio_e12__core__i \$81 + connect \gpio_e11__pad__oe \$79 + connect \gpio_e11__pad__o \$77 + connect \gpio_e11__core__i \$75 + connect \gpio_e10__pad__oe \$73 + connect \gpio_e10__pad__o \$71 + connect \gpio_e10__core__i \$69 + connect \gpio_e9__pad__oe \$67 + connect \gpio_e9__pad__o \$65 + connect \gpio_e9__core__i \$63 + connect \gpio_e8__pad__oe \$61 + connect \gpio_e8__pad__o \$59 + connect \gpio_e8__core__i \$57 + connect \eint_2__core__i \$55 + connect \eint_1__core__i \$53 + connect \eint_0__core__i \$51 + connect \io_bd2core \$49 + connect \io_bd2io \$47 + connect \io_update \$45 + connect \io_shift \$31 + connect \io_capture \$17 + connect \_idblock_id_bypass \$9 + connect \_idblock_select_id \$7 +end +attribute \src "ls180.v:4.1-10575.10" +attribute \cells_not_processed 1 +module \ls180 + attribute \src "ls180.v:10059.1-10069.4" + wire width 7 $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 + attribute \src "ls180.v:10059.1-10069.4" + wire width 7 $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 + attribute \src "ls180.v:10059.1-10069.4" + wire width 7 $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 + attribute \src "ls180.v:10059.1-10069.4" + wire width 7 $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 + attribute \src "ls180.v:10059.1-10069.4" + wire width 32 $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 + attribute \src "ls180.v:10079.1-10083.4" + wire width 3 $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 + attribute \src "ls180.v:10079.1-10083.4" + wire width 25 $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 + attribute \src "ls180.v:10079.1-10083.4" + wire width 25 $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 + attribute \src "ls180.v:10093.1-10097.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 + attribute \src "ls180.v:10093.1-10097.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 + attribute \src "ls180.v:10093.1-10097.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 + attribute \src "ls180.v:10107.1-10111.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 + attribute \src "ls180.v:10107.1-10111.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 + attribute \src "ls180.v:10107.1-10111.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 + attribute \src "ls180.v:10121.1-10125.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 + attribute \src "ls180.v:10121.1-10125.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 + attribute \src "ls180.v:10121.1-10125.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 + attribute \src "ls180.v:10136.1-10140.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 + attribute \src "ls180.v:10136.1-10140.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 + attribute \src "ls180.v:10136.1-10140.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 + attribute \src "ls180.v:10153.1-10157.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 + attribute \src "ls180.v:10153.1-10157.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 + attribute \src "ls180.v:10153.1-10157.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 + attribute \src "ls180.v:10169.1-10173.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 + attribute \src "ls180.v:10169.1-10173.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 + attribute \src "ls180.v:10169.1-10173.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 + attribute \src "ls180.v:10183.1-10187.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 + attribute \src "ls180.v:10183.1-10187.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 + attribute \src "ls180.v:10183.1-10187.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 + attribute \src "ls180.v:3226.1-3319.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3383.1-3476.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3540.1-3633.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3697.1-3790.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6520.1-6536.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:6741.1-6757.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:6758.1-6774.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:6826.1-6833.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:6834.1-6841.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:6842.1-6849.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:6850.1-6857.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:6858.1-6865.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:6866.1-6873.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:6874.1-6881.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:6882.1-6889.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6537.1-6553.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:6890.1-6897.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:6898.1-6905.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:6906.1-6913.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:6914.1-6921.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:6922.1-6941.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:6942.1-6961.4" + wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:6962.1-6981.4" + wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:6982.1-7001.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:7002.1-7021.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:7022.1-7041.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6554.1-6570.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:7042.1-7061.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:7062.1-7081.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6571.1-6587.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6588.1-6604.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6605.1-6621.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6673.1-6689.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6690.1-6706.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6707.1-6723.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6724.1-6740.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6622.1-6638.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6639.1-6655.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6656.1-6672.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:6775.1-6791.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:6792.1-6808.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:6809.1-6825.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:5760.1-5771.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5649.1-5685.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5649.1-5685.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5649.1-5685.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5649.1-5685.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5649.1-5685.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5649.1-5685.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5649.1-5685.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:5649.1-5685.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1881.5-1881.44" + wire $0\builder_libresocsim_wishbone_err[0:0] + attribute \src "ls180.v:1770.5-1770.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1771.5-1771.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1772.5-1772.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1773.5-1773.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5649.1-5685.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3132.1-3162.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5459.1-5498.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5556.1-5592.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4701.1-4773.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4546.1-4639.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4436.1-4512.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4673.1-4700.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4402.1-4435.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:5760.1-5771.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:5760.1-5771.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5710.1-5717.4" + wire width 5 $0\builder_slave_sel[4:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\builder_slave_sel_r[4:0] + attribute \src "ls180.v:4233.1-4281.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:4292.1-4340.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7201.1-7229.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7230.1-7258.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7082.1-7098.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7099.1-7115.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7116.1-7132.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7133.1-7149.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7150.1-7166.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7167.1-7183.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7184.1-7200.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:140.11-140.24" + wire width 3 $0\eint_1[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 36 $0\main_dummy[35:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_gpio_oe_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_gpio_out_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_gpio_out_storage[15:0] + attribute \src "ls180.v:7316.1-7334.4" + wire width 16 $0\main_gpio_status[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_i2c_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_i2c_storage[2:0] + attribute \src "ls180.v:7355.1-7357.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1558.11-1558.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1557.11-1557.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:5518.1-5555.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1649.11-1649.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1648.11-1648.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1641.12-1641.45" + wire width 32 $0\main_interface1_bus_dat_w[31:0] + attribute \src "ls180.v:5518.1-5555.4" + wire width 4 $0\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 64 $0\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:2790.1-2836.4" + wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:171.11-171.69" + wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] + attribute \src "ls180.v:170.11-170.69" + wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:2778.1-2788.4" + wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2790.1-2836.4" + wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:2850.1-2896.4" + wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:186.11-186.69" + wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] + attribute \src "ls180.v:185.11-185.69" + wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:2838.1-2848.4" + wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2850.1-2896.4" + wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:2910.1-2956.4" + wire width 30 $0\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:201.11-201.69" + wire width 2 $0\main_libresocsim_interface2_converted_interface_bte[1:0] + attribute \src "ls180.v:200.11-200.69" + wire width 3 $0\main_libresocsim_interface2_converted_interface_cti[2:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:2898.1-2908.4" + wire width 32 $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:2910.1-2956.4" + wire width 4 $0\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:129.12-129.74" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + attribute \src "ls180.v:159.5-159.69" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + attribute \src "ls180.v:137.5-137.72" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + attribute \src "ls180.v:147.12-147.78" + wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + attribute \src "ls180.v:145.5-145.74" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] + attribute \src "ls180.v:135.5-135.74" + wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] + attribute \src "ls180.v:2850.1-2896.4" + wire $0\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:76.5-76.46" + wire $0\main_libresocsim_libresoc_dbus_err[0:0] + attribute \src "ls180.v:2790.1-2836.4" + wire $0\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:87.5-87.46" + wire $0\main_libresocsim_libresoc_ibus_err[0:0] + attribute \src "ls180.v:2771.1-2776.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:2910.1-2956.4" + wire $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:118.5-118.49" + wire $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:217.5-217.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:2959.1-2965.4" + wire width 4 $0\main_libresocsim_we[3:0] + attribute \src "ls180.v:2971.1-2976.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:4043.1-4089.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:4031.1-4041.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:4043.1-4089.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1582.5-1582.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5426.1-5433.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5459.1-5498.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5459.1-5498.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:5459.1-5498.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5459.1-5498.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5459.1-5498.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5459.1-5498.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5459.1-5498.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1391.5-1391.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5114.1-5121.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5170.1-5177.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5124.1-5131.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5180.1-5187.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5134.1-5141.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5190.1-5197.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5144.1-5151.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5200.1-5207.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5159.1-5166.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1497.5-1497.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5153.1-5158.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:5106.1-5111.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:5026.1-5105.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:4988.1-4995.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:4998.1-5005.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:5008.1-5015.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:5018.1-5025.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1454.5-1454.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:5026.1-5105.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:5026.1-5105.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:4966.1-4973.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:5604.1-5620.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:5518.1-5555.4" + wire width 32 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5556.1-5592.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5556.1-5592.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5556.1-5592.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5556.1-5592.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5556.1-5592.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5556.1-5592.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1662.5-1662.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5518.1-5555.4" + wire width 32 $0\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:5518.1-5555.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1718.5-1718.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5634.1-5641.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4372.1-4400.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1183.5-1183.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1184.5-1184.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1164.5-1164.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4546.1-4639.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1137.5-1137.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1138.5-1138.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1139.5-1139.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1141.5-1141.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1142.5-1142.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1144.11-1144.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1145.5-1145.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1150.11-1150.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1151.5-1151.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4546.1-4639.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4546.1-4639.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4546.1-4639.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4436.1-4512.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4436.1-4512.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4436.1-4512.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4436.1-4512.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4436.1-4512.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4436.1-4512.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1127.11-1127.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1128.5-1128.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4436.1-4512.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4807.1-4908.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1339.5-1339.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1340.5-1340.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1320.5-1320.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1291.5-1291.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1292.5-1292.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1293.5-1293.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1295.5-1295.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1296.5-1296.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1298.11-1298.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1299.5-1299.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1302.5-1302.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1303.5-1303.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1304.11-1304.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1305.5-1305.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1312.5-1312.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4807.1-4908.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4807.1-4908.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4807.1-4908.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4701.1-4773.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4701.1-4773.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1261.5-1261.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1262.5-1262.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1242.5-1242.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4673.1-4700.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4673.1-4700.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4673.1-4700.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4673.1-4700.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1229.5-1229.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1230.5-1230.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1231.5-1231.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1232.5-1232.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1233.5-1233.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1234.5-1234.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1235.11-1235.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1236.11-1236.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1237.5-1237.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1227.5-1227.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4701.1-4773.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1216.5-1216.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1217.5-1217.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4701.1-4773.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4701.1-4773.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4701.1-4773.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5208.1-5398.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4701.1-4773.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4701.1-4773.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4673.1-4700.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4402.1-4435.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4402.1-4435.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1109.5-1109.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4402.1-4435.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4402.1-4435.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4402.1-4435.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4402.1-4435.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4402.1-4435.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3188.1-3195.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:449.5-449.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:432.5-432.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:433.5-433.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3210.1-3217.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3177.1-3184.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:3875.1-3883.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3226.1-3319.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:491.32-491.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:489.32-489.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3345.1-3352.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:531.5-531.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:514.5-514.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:515.5-515.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3367.1-3374.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3334.1-3341.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:3884.1-3892.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3383.1-3476.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:573.32-573.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:571.32-571.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3502.1-3509.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:613.5-613.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:596.5-596.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:597.5-597.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3524.1-3531.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3491.1-3498.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:3893.1-3901.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3540.1-3633.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:655.32-655.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:653.32-653.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3659.1-3666.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:695.5-695.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:678.5-678.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:679.5-679.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3681.1-3688.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3648.1-3655.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:3902.1-3910.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3697.1-3790.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:737.32-737.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:735.32-735.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3824.1-3829.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:3830.1-3835.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:3836.1-3841.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:745.5-745.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3810.1-3816.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:743.5-743.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:742.5-742.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:740.5-740.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:741.5-741.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:3857.1-3862.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:3863.1-3868.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:3869.1-3874.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:3843.1-3849.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:3915.1-3987.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3132.1-3162.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:393.5-393.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:394.5-394.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3132.1-3162.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:329.5-329.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:378.5-378.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:4011.1-4024.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:4011.1-4024.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:279.5-279.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3073.1-3089.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3073.1-3089.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3073.1-3089.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3073.1-3089.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:3015.1-3069.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:776.12-776.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:777.11-777.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3132.1-3162.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:3015.1-3069.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:3015.1-3069.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:779.5-779.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:780.5-780.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:3915.1-3987.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:784.32-784.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:782.32-782.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_spimaster11_storage[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spimaster12_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spimaster16_storage[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spimaster17_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spimaster1_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_spimaster1_storage[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spimaster21_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spimaster22_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spimaster23_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spimaster24_re[0:0] + attribute \src "ls180.v:4233.1-4281.4" + wire $0\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:4233.1-4281.4" + wire $0\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_spimaster27_count[2:0] + attribute \src "ls180.v:4233.1-4281.4" + wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4233.1-4281.4" + wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4233.1-4281.4" + wire $0\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:4233.1-4281.4" + wire $0\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:4233.1-4281.4" + wire $0\main_spimaster2_done[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:4233.1-4281.4" + wire $0\main_spimaster3_irq[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1000.12-1000.47" + wire width 16 $0\main_spimaster8_clk_divider[15:0] + attribute \src "ls180.v:6285.1-6290.4" + wire $0\main_spimaster9_start[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:4292.1-4340.4" + wire $0\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 16 $0\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_spisdcard_count[2:0] + attribute \src "ls180.v:4292.1-4340.4" + wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:4292.1-4340.4" + wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:4292.1-4340.4" + wire $0\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:4292.1-4340.4" + wire $0\main_spisdcard_done0[0:0] + attribute \src "ls180.v:4292.1-4340.4" + wire $0\main_spisdcard_irq[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spisdcard_miso[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:4292.1-4340.4" + wire $0\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:4292.1-4340.4" + wire $0\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 3 $0\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:6331.1-6336.4" + wire $0\main_spisdcard_start1[0:0] + attribute \src "ls180.v:4151.1-4155.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4140.1-4144.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_re[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:855.5-855.38" + wire $0\main_uart_phy_source_first[0:0] + attribute \src "ls180.v:856.5-856.37" + wire $0\main_uart_phy_source_last[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 32 $0\main_uart_phy_storage[31:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 8 $0\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:982.5-982.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4145.1-4150.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:964.5-964.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4203.1-4210.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4134.1-4139.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:927.5-927.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:910.5-910.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:911.5-911.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4173.1-4180.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:4043.1-4089.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:823.5-823.29" + wire $0\main_wb_sdram_err[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:10059.1-10069.4" + wire width 7 $0\memadr[6:0] + attribute \src "ls180.v:10079.1-10083.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10093.1-10097.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10107.1-10111.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10121.1-10125.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10136.1-10140.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10142.1-10145.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10153.1-10157.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10159.1-10162.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10169.1-10173.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10183.1-10187.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7431.1-10055.4" + wire width 2 $0\pwm[1:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7359.1-7429.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7359.1-7429.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7359.1-7429.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\spimaster_clk[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\spimaster_cs_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\spimaster_mosi[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:7431.1-10055.4" + wire $0\uart_tx[0:0] + attribute \src "ls180.v:1749.11-1749.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1748.11-1748.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1751.11-1751.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1750.11-1750.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1753.11-1753.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1752.11-1752.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1755.11-1755.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1754.11-1754.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2600.5-2600.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2613.5-2613.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2614.5-2614.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2618.12-2618.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2619.5-2619.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2620.5-2620.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2621.12-2621.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2622.5-2622.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2623.5-2623.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2624.12-2624.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2625.5-2625.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2601.12-2601.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2626.5-2626.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2627.12-2627.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2628.5-2628.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2629.5-2629.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2630.12-2630.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2631.12-2631.50" + wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] + attribute \src "ls180.v:2632.11-2632.48" + wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] + attribute \src "ls180.v:2633.5-2633.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2634.5-2634.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2635.5-2635.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2602.11-2602.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2636.11-2636.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2637.11-2637.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2603.5-2603.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2604.5-2604.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2605.5-2605.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2609.5-2609.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2610.12-2610.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2611.11-2611.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2612.5-2612.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2606.5-2606.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2607.5-2607.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2608.5-2608.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2615.5-2615.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2616.5-2616.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2617.5-2617.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1735.5-1735.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1734.5-1734.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1739.5-1739.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1738.5-1738.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1743.5-1743.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1742.5-1742.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1780.5-1780.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1779.5-1779.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:1900.12-1900.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:1897.5-1897.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:1894.11-1894.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:1904.11-1904.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2406.11-2406.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2439.11-2439.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2480.11-2480.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2545.11-2545.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2570.11-2570.52" + wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1945.11-1945.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1974.11-1974.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1987.11-1987.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2028.11-2028.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2069.11-2069.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2134.11-2134.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2267.11-2267.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2348.11-2348.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2365.11-2365.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1867.12-1867.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2596.12-2596.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2597.5-2597.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1869.11-1869.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2594.11-2594.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2595.5-2595.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1868.5-1868.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2598.5-2598.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2599.5-2599.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1877.5-1877.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1873.12-1873.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1757.11-1757.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1756.11-1756.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2703.32-2703.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2704.32-2704.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2723.32-2723.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2724.32-2724.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2725.32-2725.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2726.32-2726.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2727.32-2727.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2728.32-2728.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2729.32-2729.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2730.32-2730.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2731.32-2731.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2732.32-2732.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2733.32-2733.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2734.32-2734.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2735.32-2735.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2736.32-2736.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2705.32-2705.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2706.32-2706.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2707.32-2707.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2708.32-2708.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2709.32-2709.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2710.32-2710.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2711.32-2711.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2712.32-2712.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2713.32-2713.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2714.32-2714.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2715.32-2715.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2716.32-2716.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2717.32-2717.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2718.32-2718.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2719.32-2719.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2720.32-2720.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2721.32-2721.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2722.32-2722.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1775.5-1775.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1776.5-1776.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1777.5-1777.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1778.5-1778.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1774.5-1774.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2593.11-2593.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1747.11-1747.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1746.11-1746.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1856.11-1856.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1855.11-1855.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1824.5-1824.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1823.5-1823.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1836.11-1836.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1835.11-1835.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1860.5-1860.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1859.5-1859.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1864.11-1864.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1863.11-1863.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1812.11-1812.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1811.11-1811.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1800.11-1800.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1799.11-1799.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1796.11-1796.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1795.11-1795.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1808.5-1808.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1807.5-1807.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1816.11-1816.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1815.11-1815.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1792.5-1792.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1791.5-1791.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:1888.5-1888.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1884.12-1884.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:1895.11-1895.35" + wire width 5 $1\builder_slave_sel[4:0] + attribute \src "ls180.v:1896.11-1896.37" + wire width 5 $1\builder_slave_sel_r[4:0] + attribute \src "ls180.v:1784.11-1784.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1783.11-1783.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1788.11-1788.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1787.11-1787.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2592.11-2592.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2645.5-2645.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2646.5-2646.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2638.11-2638.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2639.12-2639.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2640.5-2640.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2641.5-2641.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2642.5-2642.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2643.5-2643.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2644.5-2644.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:836.5-836.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:833.5-833.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1781.5-1781.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1782.5-1782.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:835.12-835.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:832.5-832.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:267.12-267.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:268.5-268.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:1067.12-1067.30" + wire width 36 $1\main_dummy[35:0] + attribute \src "ls180.v:984.5-984.27" + wire $1\main_gpio_oe_re[0:0] + attribute \src "ls180.v:983.12-983.40" + wire width 16 $1\main_gpio_oe_storage[15:0] + attribute \src "ls180.v:988.5-988.28" + wire $1\main_gpio_out_re[0:0] + attribute \src "ls180.v:987.12-987.41" + wire width 16 $1\main_gpio_out_storage[15:0] + attribute \src "ls180.v:985.12-985.36" + wire width 16 $1\main_gpio_status[15:0] + attribute \src "ls180.v:1092.5-1092.23" + wire $1\main_i2c_re[0:0] + attribute \src "ls180.v:1091.11-1091.34" + wire width 3 $1\main_i2c_storage[2:0] + attribute \src "ls180.v:252.5-252.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:1640.12-1640.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1644.5-1644.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1643.11-1643.41" + wire width 4 $1\main_interface1_bus_sel[3:0] + attribute \src "ls180.v:1645.5-1645.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1647.5-1647.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:63.12-63.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:174.5-174.47" + wire $1\main_libresocsim_converter0_counter[0:0] + attribute \src "ls180.v:1736.5-1736.69" + wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1737.5-1737.72" + wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:176.12-176.53" + wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] + attribute \src "ls180.v:173.5-173.44" + wire $1\main_libresocsim_converter0_skip[0:0] + attribute \src "ls180.v:189.5-189.47" + wire $1\main_libresocsim_converter1_counter[0:0] + attribute \src "ls180.v:1740.5-1740.69" + wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1741.5-1741.72" + wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:191.12-191.53" + wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] + attribute \src "ls180.v:188.5-188.44" + wire $1\main_libresocsim_converter1_skip[0:0] + attribute \src "ls180.v:204.5-204.47" + wire $1\main_libresocsim_converter2_counter[0:0] + attribute \src "ls180.v:1744.5-1744.69" + wire $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1745.5-1745.72" + wire $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:206.12-206.53" + wire width 64 $1\main_libresocsim_converter2_dat_r[63:0] + attribute \src "ls180.v:203.5-203.44" + wire $1\main_libresocsim_converter2_skip[0:0] + attribute \src "ls180.v:227.5-227.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:226.5-226.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:247.5-247.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:246.5-246.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:162.12-162.71" + wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "ls180.v:166.5-166.63" + wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "ls180.v:163.12-163.73" + wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "ls180.v:165.11-165.69" + wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "ls180.v:167.5-167.63" + wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "ls180.v:169.5-169.62" + wire $1\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "ls180.v:177.12-177.71" + wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "ls180.v:181.5-181.63" + wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "ls180.v:178.12-178.73" + wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "ls180.v:180.11-180.69" + wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "ls180.v:182.5-182.63" + wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "ls180.v:184.5-184.62" + wire $1\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "ls180.v:192.12-192.71" + wire width 30 $1\main_libresocsim_interface2_converted_interface_adr[29:0] + attribute \src "ls180.v:196.5-196.63" + wire $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + attribute \src "ls180.v:193.12-193.73" + wire width 32 $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + attribute \src "ls180.v:195.11-195.69" + wire width 4 $1\main_libresocsim_interface2_converted_interface_sel[3:0] + attribute \src "ls180.v:197.5-197.63" + wire $1\main_libresocsim_interface2_converted_interface_stb[0:0] + attribute \src "ls180.v:199.5-199.62" + wire $1\main_libresocsim_interface2_converted_interface_we[0:0] + attribute \src "ls180.v:72.5-72.46" + wire $1\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "ls180.v:83.5-83.46" + wire $1\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "ls180.v:65.12-65.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:116.5-116.49" + wire $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + attribute \src "ls180.v:223.5-223.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:222.12-222.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:213.5-213.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:225.5-225.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:224.12-224.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:56.5-56.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:55.5-55.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:58.5-58.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:57.12-57.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:229.5-229.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:228.5-228.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:248.12-248.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:230.12-230.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:220.11-220.37" + wire width 4 $1\main_libresocsim_we[3:0] + attribute \src "ls180.v:236.5-236.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:237.5-237.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:234.5-234.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:824.12-824.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:828.5-828.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:825.12-825.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:827.11-827.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:829.5-829.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:831.5-831.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:1071.12-1071.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1073.5-1073.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1072.5-1072.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1077.5-1077.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1076.12-1076.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1075.5-1075.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1074.12-1074.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1081.12-1081.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1083.5-1083.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1082.5-1082.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1087.5-1087.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1086.12-1086.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1085.5-1085.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1084.12-1084.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:269.11-269.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:1609.11-1609.50" + wire width 2 $1\main_sdblock2mem_converter_demux[1:0] + attribute \src "ls180.v:1605.5-1605.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1606.5-1606.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1607.12-1607.66" + wire width 32 $1\main_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "ls180.v:1608.11-1608.77" + wire width 3 $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "ls180.v:1611.5-1611.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1584.11-1584.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1581.11-1581.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1583.11-1583.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1585.11-1585.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1619.12-1619.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1620.12-1620.60" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "ls180.v:1617.5-1617.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1627.5-1627.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1626.12-1626.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1631.5-1631.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1630.5-1630.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1629.5-1629.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1628.12-1628.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1635.5-1635.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1634.5-1634.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1637.12-1637.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1857.12-1857.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1858.5-1858.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1622.5-1622.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1632.5-1632.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1401.5-1401.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1400.12-1400.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1399.5-1399.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1398.11-1398.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1385.5-1385.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1384.12-1384.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1387.5-1387.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1386.12-1386.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1540.11-1540.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1841.11-1841.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1842.5-1842.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1541.5-1541.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1837.5-1837.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1838.5-1838.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1542.5-1542.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1845.5-1845.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1846.5-1846.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1392.13-1392.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1853.13-1853.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1854.5-1854.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1543.5-1543.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1847.5-1847.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1848.5-1848.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1501.11-1501.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1507.5-1507.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1506.12-1506.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1502.12-1502.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1514.5-1514.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1513.12-1513.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1509.12-1509.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1521.5-1521.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1520.12-1520.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1516.12-1516.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1528.5-1528.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1527.12-1527.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1523.12-1523.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1530.12-1530.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1531.12-1531.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1532.12-1532.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1533.12-1533.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1535.12-1535.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1536.12-1536.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1537.12-1537.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1538.12-1538.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1492.5-1492.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1493.5-1493.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1494.11-1494.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1491.5-1491.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1490.5-1490.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1495.5-1495.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1500.11-1500.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1534.5-1534.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1457.11-1457.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1833.11-1833.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1834.5-1834.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1462.12-1462.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1458.12-1458.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1469.12-1469.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1465.12-1465.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1476.12-1476.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1472.12-1472.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1483.12-1483.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1479.12-1479.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1486.12-1486.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1825.12-1825.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1826.5-1826.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1487.12-1487.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1827.12-1827.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1828.5-1828.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1488.12-1488.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1829.12-1829.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1830.5-1830.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1489.12-1489.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1831.12-1831.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1832.5-1832.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1448.5-1448.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1455.5-1455.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1456.11-1456.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1453.5-1453.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1452.5-1452.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1444.11-1444.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1402.11-1402.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1545.12-1545.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1843.12-1843.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1844.5-1844.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1546.5-1546.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1839.5-1839.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1840.5-1840.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1547.5-1547.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1849.5-1849.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1850.5-1850.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1548.5-1548.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1851.5-1851.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1852.5-1852.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1693.11-1693.48" + wire width 2 $1\main_sdmem2block_converter_mux[1:0] + attribute \src "ls180.v:1691.11-1691.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1667.5-1667.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1666.12-1666.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1665.12-1665.45" + wire width 32 $1\main_sdmem2block_dma_data[31:0] + attribute \src "ls180.v:1861.12-1861.75" + wire width 32 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "ls180.v:1862.5-1862.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1672.5-1672.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1671.5-1671.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1670.5-1670.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1669.5-1669.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1668.12-1668.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1675.5-1675.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1674.5-1674.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1679.12-1679.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1865.12-1865.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1866.5-1866.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1658.5-1658.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1659.12-1659.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1657.5-1657.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1656.5-1656.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1663.5-1663.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1664.12-1664.60" + wire width 32 $1\main_sdmem2block_dma_source_payload_data[31:0] + attribute \src "ls180.v:1660.5-1660.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1720.11-1720.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1717.11-1717.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1719.11-1719.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1721.11-1721.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1101.5-1101.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1104.5-1104.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1105.5-1105.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1103.11-1103.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1099.5-1099.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1098.11-1098.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1207.5-1207.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1208.5-1208.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1209.11-1209.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1205.5-1205.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1192.11-1192.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1188.5-1188.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1189.5-1189.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1190.11-1190.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1191.11-1191.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1194.5-1194.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1210.5-1210.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1805.5-1805.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1806.5-1806.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1180.5-1180.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1175.5-1175.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1162.11-1162.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1801.11-1801.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1802.5-1802.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1147.5-1147.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1148.5-1148.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1149.5-1149.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1154.5-1154.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1155.11-1155.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1153.5-1153.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1152.5-1152.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1158.5-1158.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1159.11-1159.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1160.11-1160.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1157.5-1157.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1156.5-1156.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1161.12-1161.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1803.12-1803.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1804.5-1804.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1134.11-1134.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1797.11-1797.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1798.5-1798.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1133.5-1133.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1124.5-1124.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1125.5-1125.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1126.5-1126.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1131.5-1131.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1132.11-1132.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1130.5-1130.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1129.5-1129.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1318.11-1318.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1817.11-1817.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1818.5-1818.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1363.5-1363.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1364.5-1364.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1365.11-1365.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1361.5-1361.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1348.5-1348.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1344.5-1344.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1345.5-1345.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1346.11-1346.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1347.11-1347.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1350.5-1350.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1366.5-1366.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1821.5-1821.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1822.5-1822.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1336.5-1336.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1331.5-1331.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1301.5-1301.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1308.5-1308.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1309.11-1309.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1307.5-1307.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1306.5-1306.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1313.5-1313.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1314.11-1314.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1315.11-1315.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1311.5-1311.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1310.5-1310.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1316.5-1316.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1317.12-1317.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1819.12-1819.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1820.5-1820.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1226.11-1226.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1813.11-1813.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1814.5-1814.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1285.5-1285.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1286.5-1286.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1287.11-1287.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1283.5-1283.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1270.11-1270.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1266.5-1266.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1267.5-1267.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1268.11-1268.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1269.11-1269.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1272.5-1272.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1288.5-1288.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1809.5-1809.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1810.5-1810.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1258.5-1258.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1253.5-1253.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1240.5-1240.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1215.5-1215.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1218.11-1218.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1219.5-1219.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1222.5-1222.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1223.5-1223.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1224.11-1224.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1221.5-1221.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1220.5-1220.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1238.5-1238.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1225.5-1225.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1239.5-1239.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1119.11-1119.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1793.11-1793.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1794.5-1794.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1114.5-1114.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1115.5-1115.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1116.5-1116.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1117.11-1117.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1118.5-1118.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1368.5-1368.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1371.11-1371.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:331.5-331.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:330.12-330.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:333.5-333.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:332.11-332.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:429.5-429.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:451.11-451.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:448.11-448.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:450.11-450.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:452.11-452.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:475.5-475.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:476.5-476.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:478.12-478.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:477.5-477.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:473.5-473.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:421.12-421.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:423.5-423.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:426.5-426.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:427.5-427.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:428.5-428.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:424.5-424.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:425.5-425.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:420.5-420.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:419.5-419.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:418.5-418.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:416.5-416.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:415.5-415.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:479.12-479.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:483.5-483.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:484.5-484.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:482.5-482.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:480.5-480.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:487.11-487.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:486.32-486.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:511.5-511.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:533.11-533.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:530.11-530.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:532.11-532.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:534.11-534.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:557.5-557.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:558.5-558.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:560.12-560.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:559.5-559.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:555.5-555.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:503.12-503.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:505.5-505.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:508.5-508.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:509.5-509.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:510.5-510.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:506.5-506.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:507.5-507.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:502.5-502.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:501.5-501.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:500.5-500.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:498.5-498.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:497.5-497.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:561.12-561.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:565.5-565.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:566.5-566.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:564.5-564.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:562.5-562.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:569.11-569.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:568.32-568.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:593.5-593.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:615.11-615.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:612.11-612.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:614.11-614.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:616.11-616.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:639.5-639.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:640.5-640.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:642.12-642.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:641.5-641.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:637.5-637.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:585.12-585.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:587.5-587.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:590.5-590.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:591.5-591.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:592.5-592.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:588.5-588.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:589.5-589.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:584.5-584.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:583.5-583.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:582.5-582.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:580.5-580.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:579.5-579.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:643.12-643.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:647.5-647.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:648.5-648.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:646.5-646.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:644.5-644.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:651.11-651.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:650.32-650.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:675.5-675.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:697.11-697.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:694.11-694.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:696.11-696.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:698.11-698.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:721.5-721.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:722.5-722.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:724.12-724.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:723.5-723.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:719.5-719.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:667.12-667.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:669.5-669.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:672.5-672.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:673.5-673.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:674.5-674.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:670.5-670.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:671.5-671.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:666.5-666.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:665.5-665.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:664.5-664.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:662.5-662.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:661.5-661.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:725.12-725.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:729.5-729.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:730.5-730.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:728.5-728.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:726.5-726.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:733.11-733.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:732.32-732.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:748.5-748.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:749.5-749.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:750.5-750.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:756.11-756.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:754.11-754.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:766.5-766.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:767.5-767.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:768.5-768.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:763.5-763.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:774.11-774.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:772.11-772.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:761.5-761.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:758.5-758.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:759.5-759.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:387.5-387.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:388.12-388.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:389.11-389.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:390.5-390.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:391.5-391.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:392.5-392.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:386.5-386.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:385.5-385.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:325.5-325.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:324.11-324.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:369.12-369.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:370.11-370.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:371.5-371.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:372.5-372.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:373.5-373.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:382.5-382.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:374.5-374.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:380.5-380.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:793.5-793.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:796.5-796.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:366.12-366.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:367.11-367.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:272.5-272.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:273.5-273.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:274.5-274.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:284.12-284.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:285.5-285.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:275.5-275.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:311.5-311.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:302.12-302.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:303.11-303.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:304.5-304.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:308.5-308.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:305.5-305.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:309.5-309.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:306.5-306.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:315.5-315.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:310.5-310.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:307.5-307.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:312.12-312.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:313.5-313.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:314.11-314.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:403.5-403.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:402.5-402.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:323.5-323.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:409.5-409.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:408.11-408.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:407.5-407.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:404.5-404.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:300.12-300.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:301.5-301.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:336.12-336.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:778.11-778.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:322.11-322.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:787.5-787.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:786.32-786.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:795.11-795.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:798.11-798.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:400.11-400.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:790.11-790.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:789.32-789.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:335.5-335.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:334.12-334.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:1003.12-1003.44" + wire width 16 $1\main_spimaster11_storage[15:0] + attribute \src "ls180.v:1004.5-1004.31" + wire $1\main_spimaster12_re[0:0] + attribute \src "ls180.v:1008.11-1008.42" + wire width 8 $1\main_spimaster16_storage[7:0] + attribute \src "ls180.v:1009.5-1009.31" + wire $1\main_spimaster17_re[0:0] + attribute \src "ls180.v:1065.5-1065.30" + wire $1\main_spimaster1_re[0:0] + attribute \src "ls180.v:1064.12-1064.45" + wire width 16 $1\main_spimaster1_storage[15:0] + attribute \src "ls180.v:1013.5-1013.36" + wire $1\main_spimaster21_storage[0:0] + attribute \src "ls180.v:1014.5-1014.31" + wire $1\main_spimaster22_re[0:0] + attribute \src "ls180.v:1015.5-1015.36" + wire $1\main_spimaster23_storage[0:0] + attribute \src "ls180.v:1016.5-1016.31" + wire $1\main_spimaster24_re[0:0] + attribute \src "ls180.v:1017.5-1017.39" + wire $1\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:1018.5-1018.38" + wire $1\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:1019.11-1019.40" + wire width 3 $1\main_spimaster27_count[2:0] + attribute \src "ls180.v:1785.11-1785.62" + wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1786.5-1786.59" + wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:1020.5-1020.39" + wire $1\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:1021.5-1021.39" + wire $1\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:994.5-994.32" + wire $1\main_spimaster2_done[0:0] + attribute \src "ls180.v:1022.12-1022.48" + wire width 16 $1\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:1025.11-1025.44" + wire width 8 $1\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:1026.11-1026.43" + wire width 3 $1\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:1027.11-1027.44" + wire width 8 $1\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:995.5-995.31" + wire $1\main_spimaster3_irq[0:0] + attribute \src "ls180.v:997.11-997.38" + wire width 8 $1\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1001.5-1001.33" + wire $1\main_spimaster9_start[0:0] + attribute \src "ls180.v:1058.12-1058.47" + wire width 16 $1\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:1053.5-1053.37" + wire $1\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:1040.5-1040.37" + wire $1\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:1039.12-1039.50" + wire width 16 $1\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:1055.11-1055.38" + wire width 3 $1\main_spisdcard_count[2:0] + attribute \src "ls180.v:1789.11-1789.60" + wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1790.5-1790.57" + wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1054.5-1054.36" + wire $1\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:1050.5-1050.32" + wire $1\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:1049.5-1049.37" + wire $1\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:1030.5-1030.32" + wire $1\main_spisdcard_done0[0:0] + attribute \src "ls180.v:1031.5-1031.30" + wire $1\main_spisdcard_irq[0:0] + attribute \src "ls180.v:1052.5-1052.38" + wire $1\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:1051.5-1051.43" + wire $1\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:1033.11-1033.37" + wire width 8 $1\main_spisdcard_miso[7:0] + attribute \src "ls180.v:1063.11-1063.42" + wire width 8 $1\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:1057.5-1057.37" + wire $1\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:1061.11-1061.42" + wire width 8 $1\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:1056.5-1056.37" + wire $1\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:1045.5-1045.34" + wire $1\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:1062.11-1062.41" + wire width 3 $1\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:1044.11-1044.45" + wire width 8 $1\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:1037.5-1037.33" + wire $1\main_spisdcard_start1[0:0] + attribute \src "ls180.v:891.11-891.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:893.5-893.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:887.11-887.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:892.11-892.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:859.12-859.54" + wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:849.12-849.54" + wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:842.5-842.28" + wire $1\main_uart_phy_re[0:0] + attribute \src "ls180.v:863.11-863.43" + wire width 4 $1\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:864.5-864.33" + wire $1\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:861.5-861.30" + wire $1\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:862.11-862.38" + wire width 8 $1\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:844.5-844.36" + wire $1\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:857.11-857.51" + wire width 8 $1\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:853.5-853.38" + wire $1\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:841.12-841.47" + wire width 32 $1\main_uart_phy_storage[31:0] + attribute \src "ls180.v:851.11-851.43" + wire width 4 $1\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:852.5-852.33" + wire $1\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:850.11-850.38" + wire width 8 $1\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:858.5-858.39" + wire $1\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:848.5-848.39" + wire $1\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:882.5-882.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:966.11-966.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:963.11-963.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:965.11-965.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:956.5-956.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:967.11-967.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:883.5-883.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:880.5-880.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:877.5-877.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:929.11-929.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:926.11-926.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:928.11-928.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:919.5-919.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:930.11-930.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:878.5-878.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:875.5-875.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:819.5-819.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:837.5-837.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "ls180.v:2819.68-2819.110" + wire $add$ls180.v:2819$22_Y + attribute \src "ls180.v:2879.68-2879.110" + wire $add$ls180.v:2879$33_Y + attribute \src "ls180.v:2939.68-2939.110" + wire $add$ls180.v:2939$44_Y + attribute \src "ls180.v:4072.54-4072.83" + wire $add$ls180.v:4072$537_Y + attribute \src "ls180.v:4172.36-4172.89" + wire width 5 $add$ls180.v:4172$583_Y + attribute \src "ls180.v:4202.36-4202.89" + wire width 5 $add$ls180.v:4202$594_Y + attribute \src "ls180.v:4257.54-4257.83" + wire width 3 $add$ls180.v:4257$607_Y + attribute \src "ls180.v:4316.52-4316.79" + wire width 3 $add$ls180.v:4316$615_Y + attribute \src "ls180.v:4420.58-4420.86" + wire width 8 $add$ls180.v:4420$643_Y + attribute \src "ls180.v:4477.58-4477.86" + wire width 8 $add$ls180.v:4477$646_Y + attribute \src "ls180.v:4494.58-4494.86" + wire width 8 $add$ls180.v:4494$648_Y + attribute \src "ls180.v:4587.59-4587.87" + wire width 8 $add$ls180.v:4587$665_Y + attribute \src "ls180.v:4612.59-4612.87" + wire width 8 $add$ls180.v:4612$668_Y + attribute \src "ls180.v:4734.53-4734.82" + wire width 8 $add$ls180.v:4734$685_Y + attribute \src "ls180.v:4845.65-4845.114" + wire width 10 $add$ls180.v:4845$699_Y + attribute \src "ls180.v:4850.62-4850.91" + wire width 10 $add$ls180.v:4850$702_Y + attribute \src "ls180.v:4876.61-4876.90" + wire width 10 $add$ls180.v:4876$705_Y + attribute \src "ls180.v:5080.80-5080.117" + wire width 3 $add$ls180.v:5080$890_Y + attribute \src "ls180.v:5274.54-5274.82" + wire width 3 $add$ls180.v:5274$965_Y + attribute \src "ls180.v:5326.55-5326.84" + wire width 32 $add$ls180.v:5326$975_Y + attribute \src "ls180.v:5352.57-5352.86" + wire width 32 $add$ls180.v:5352$983_Y + attribute \src "ls180.v:5473.51-5473.134" + wire width 32 $add$ls180.v:5473$999_Y + attribute \src "ls180.v:5476.77-5476.125" + wire width 32 $add$ls180.v:5476$1001_Y + attribute \src "ls180.v:5569.50-5569.105" + wire width 32 $add$ls180.v:5569$1010_Y + attribute \src "ls180.v:5571.77-5571.111" + wire width 32 $add$ls180.v:5571$1011_Y + attribute \src "ls180.v:7503.36-7503.70" + wire width 32 $add$ls180.v:7503$2415_Y + attribute \src "ls180.v:7588.37-7588.72" + wire width 4 $add$ls180.v:7588$2436_Y + attribute \src "ls180.v:7605.60-7605.119" + wire width 3 $add$ls180.v:7605$2440_Y + attribute \src "ls180.v:7608.60-7608.119" + wire width 3 $add$ls180.v:7608$2441_Y + attribute \src "ls180.v:7612.59-7612.116" + wire width 4 $add$ls180.v:7612$2446_Y + attribute \src "ls180.v:7651.60-7651.119" + wire width 3 $add$ls180.v:7651$2456_Y + attribute \src "ls180.v:7654.60-7654.119" + wire width 3 $add$ls180.v:7654$2457_Y + attribute \src "ls180.v:7658.59-7658.116" + wire width 4 $add$ls180.v:7658$2462_Y + attribute \src "ls180.v:7697.60-7697.119" + wire width 3 $add$ls180.v:7697$2472_Y + attribute \src "ls180.v:7700.60-7700.119" + wire width 3 $add$ls180.v:7700$2473_Y + attribute \src "ls180.v:7704.59-7704.116" + wire width 4 $add$ls180.v:7704$2478_Y + attribute \src "ls180.v:7743.60-7743.119" + wire width 3 $add$ls180.v:7743$2488_Y + attribute \src "ls180.v:7746.60-7746.119" + wire width 3 $add$ls180.v:7746$2489_Y + attribute \src "ls180.v:7750.59-7750.116" + wire width 4 $add$ls180.v:7750$2494_Y + attribute \src "ls180.v:7980.34-7980.66" + wire width 4 $add$ls180.v:7980$2548_Y + attribute \src "ls180.v:7996.73-7996.131" + wire width 33 $add$ls180.v:7996$2551_Y + attribute \src "ls180.v:8009.34-8009.66" + wire width 4 $add$ls180.v:8009$2555_Y + attribute \src "ls180.v:8028.73-8028.131" + wire width 33 $add$ls180.v:8028$2558_Y + attribute \src "ls180.v:8054.33-8054.65" + wire width 4 $add$ls180.v:8054$2566_Y + attribute \src "ls180.v:8057.33-8057.65" + wire width 4 $add$ls180.v:8057$2567_Y + attribute \src "ls180.v:8061.33-8061.64" + wire width 5 $add$ls180.v:8061$2572_Y + attribute \src "ls180.v:8076.33-8076.65" + wire width 4 $add$ls180.v:8076$2577_Y + attribute \src "ls180.v:8079.33-8079.65" + wire width 4 $add$ls180.v:8079$2578_Y + attribute \src "ls180.v:8083.33-8083.64" + wire width 5 $add$ls180.v:8083$2583_Y + attribute \src "ls180.v:8104.35-8104.70" + wire width 16 $add$ls180.v:8104$2585_Y + attribute \src "ls180.v:8139.34-8139.68" + wire width 16 $add$ls180.v:8139$2590_Y + attribute \src "ls180.v:8175.25-8175.49" + wire width 32 $add$ls180.v:8175$2595_Y + attribute \src "ls180.v:8189.25-8189.49" + wire width 32 $add$ls180.v:8189$2599_Y + attribute \src "ls180.v:8203.31-8203.61" + wire width 9 $add$ls180.v:8203$2604_Y + attribute \src "ls180.v:8226.45-8226.88" + wire width 3 $add$ls180.v:8226$2608_Y + attribute \src "ls180.v:8272.71-8272.114" + wire width 4 $add$ls180.v:8272$2614_Y + attribute \src "ls180.v:8307.46-8307.90" + wire width 3 $add$ls180.v:8307$2620_Y + attribute \src "ls180.v:8353.72-8353.116" + wire width 4 $add$ls180.v:8353$2626_Y + attribute \src "ls180.v:8386.47-8386.92" + wire $add$ls180.v:8386$2632_Y + attribute \src "ls180.v:8414.73-8414.118" + wire width 2 $add$ls180.v:8414$2638_Y + attribute \src "ls180.v:8526.39-8526.75" + wire width 4 $add$ls180.v:8526$2651_Y + attribute \src "ls180.v:8587.37-8587.73" + wire width 5 $add$ls180.v:8587$2655_Y + attribute \src "ls180.v:8590.37-8590.73" + wire width 5 $add$ls180.v:8590$2656_Y + attribute \src "ls180.v:8594.36-8594.70" + wire width 6 $add$ls180.v:8594$2661_Y + attribute \src "ls180.v:8609.41-8609.80" + wire width 2 $add$ls180.v:8609$2665_Y + attribute \src "ls180.v:8643.67-8643.106" + wire width 3 $add$ls180.v:8643$2671_Y + attribute \src "ls180.v:8669.39-8669.76" + wire width 2 $add$ls180.v:8669$2673_Y + attribute \src "ls180.v:8673.37-8673.73" + wire width 5 $add$ls180.v:8673$2677_Y + attribute \src "ls180.v:8676.37-8676.73" + wire width 5 $add$ls180.v:8676$2678_Y + attribute \src "ls180.v:8680.36-8680.70" + wire width 6 $add$ls180.v:8680$2683_Y + attribute \src "ls180.v:2813.9-2813.80" + wire $and$ls180.v:2813$17_Y + attribute \src "ls180.v:2831.9-2831.80" + wire $and$ls180.v:2831$24_Y + attribute \src "ls180.v:2873.9-2873.80" + wire $and$ls180.v:2873$28_Y + attribute \src "ls180.v:2891.9-2891.80" + wire $and$ls180.v:2891$35_Y + attribute \src "ls180.v:2933.9-2933.86" + wire $and$ls180.v:2933$39_Y + attribute \src "ls180.v:2951.9-2951.86" + wire $and$ls180.v:2951$46_Y + attribute \src "ls180.v:2961.31-2961.90" + wire $and$ls180.v:2961$48_Y + attribute \src "ls180.v:2961.30-2961.121" + wire $and$ls180.v:2961$49_Y + attribute \src "ls180.v:2961.29-2961.156" + wire $and$ls180.v:2961$50_Y + attribute \src "ls180.v:2962.31-2962.90" + wire $and$ls180.v:2962$51_Y + attribute \src "ls180.v:2962.30-2962.121" + wire $and$ls180.v:2962$52_Y + attribute \src "ls180.v:2962.29-2962.156" + wire $and$ls180.v:2962$53_Y + attribute \src "ls180.v:2963.31-2963.90" + wire $and$ls180.v:2963$54_Y + attribute \src "ls180.v:2963.30-2963.121" + wire $and$ls180.v:2963$55_Y + attribute \src "ls180.v:2963.29-2963.156" + wire $and$ls180.v:2963$56_Y + attribute \src "ls180.v:2964.31-2964.90" + wire $and$ls180.v:2964$57_Y + attribute \src "ls180.v:2964.30-2964.121" + wire $and$ls180.v:2964$58_Y + attribute \src "ls180.v:2964.29-2964.156" + wire $and$ls180.v:2964$59_Y + attribute \src "ls180.v:2973.7-2973.89" + wire $and$ls180.v:2973$62_Y + attribute \src "ls180.v:2978.32-2978.111" + wire $and$ls180.v:2978$63_Y + attribute \src "ls180.v:3092.40-3092.99" + wire $and$ls180.v:3092$70_Y + attribute \src "ls180.v:3093.40-3093.99" + wire $and$ls180.v:3093$71_Y + attribute \src "ls180.v:3131.38-3131.103" + wire $and$ls180.v:3131$77_Y + attribute \src "ls180.v:3185.50-3185.119" + wire $and$ls180.v:3185$85_Y + attribute \src "ls180.v:3185.49-3185.167" + wire $and$ls180.v:3185$86_Y + attribute \src "ls180.v:3186.49-3186.118" + wire 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"ls180.v:6049.104-6049.149" + wire $eq$ls180.v:6049$1580_Y + attribute \src "ls180.v:6050.107-6050.152" + wire $eq$ls180.v:6050$1584_Y + attribute \src "ls180.v:6052.104-6052.149" + wire $eq$ls180.v:6052$1587_Y + attribute \src "ls180.v:6053.107-6053.152" + wire $eq$ls180.v:6053$1591_Y + attribute \src "ls180.v:6055.104-6055.149" + wire $eq$ls180.v:6055$1594_Y + attribute \src "ls180.v:6056.107-6056.152" + wire $eq$ls180.v:6056$1598_Y + attribute \src "ls180.v:6058.104-6058.149" + wire $eq$ls180.v:6058$1601_Y + attribute \src "ls180.v:6059.107-6059.152" + wire $eq$ls180.v:6059$1605_Y + attribute \src "ls180.v:6061.104-6061.149" + wire $eq$ls180.v:6061$1608_Y + attribute \src "ls180.v:6062.107-6062.152" + wire $eq$ls180.v:6062$1612_Y + attribute \src "ls180.v:6064.100-6064.145" + wire $eq$ls180.v:6064$1615_Y + attribute \src "ls180.v:6065.103-6065.148" + wire $eq$ls180.v:6065$1619_Y + attribute \src "ls180.v:6067.101-6067.146" + wire $eq$ls180.v:6067$1622_Y + attribute \src "ls180.v:6068.104-6068.149" + wire $eq$ls180.v:6068$1626_Y + attribute \src "ls180.v:6070.104-6070.149" + wire $eq$ls180.v:6070$1629_Y + attribute \src "ls180.v:6071.107-6071.152" + wire $eq$ls180.v:6071$1633_Y + attribute \src "ls180.v:6073.104-6073.149" + wire $eq$ls180.v:6073$1636_Y + attribute \src "ls180.v:6074.107-6074.152" + wire $eq$ls180.v:6074$1640_Y + attribute \src "ls180.v:6076.103-6076.148" + wire $eq$ls180.v:6076$1643_Y + attribute \src "ls180.v:6077.106-6077.151" + wire $eq$ls180.v:6077$1647_Y + attribute \src "ls180.v:6079.103-6079.148" + wire $eq$ls180.v:6079$1650_Y + attribute \src "ls180.v:6080.106-6080.151" + wire $eq$ls180.v:6080$1654_Y + attribute \src "ls180.v:6082.103-6082.148" + wire $eq$ls180.v:6082$1657_Y + attribute \src "ls180.v:6083.106-6083.151" + wire $eq$ls180.v:6083$1661_Y + attribute \src "ls180.v:6085.103-6085.148" + wire $eq$ls180.v:6085$1664_Y + attribute \src "ls180.v:6086.106-6086.151" + wire $eq$ls180.v:6086$1668_Y + attribute \src "ls180.v:6122.32-6122.78" + wire $eq$ls180.v:6122$1670_Y + attribute \src "ls180.v:6124.100-6124.144" + wire $eq$ls180.v:6124$1672_Y + attribute \src "ls180.v:6125.103-6125.147" + wire $eq$ls180.v:6125$1676_Y + attribute \src "ls180.v:6127.100-6127.144" + wire $eq$ls180.v:6127$1679_Y + attribute \src "ls180.v:6128.103-6128.147" + wire $eq$ls180.v:6128$1683_Y + attribute \src "ls180.v:6130.100-6130.144" + wire $eq$ls180.v:6130$1686_Y + attribute \src "ls180.v:6131.103-6131.147" + wire $eq$ls180.v:6131$1690_Y + attribute \src "ls180.v:6133.100-6133.144" + wire $eq$ls180.v:6133$1693_Y + attribute \src "ls180.v:6134.103-6134.147" + wire $eq$ls180.v:6134$1697_Y + attribute \src "ls180.v:6136.100-6136.144" + wire $eq$ls180.v:6136$1700_Y + attribute \src "ls180.v:6137.103-6137.147" + wire $eq$ls180.v:6137$1704_Y + attribute \src "ls180.v:6139.100-6139.144" + wire $eq$ls180.v:6139$1707_Y + attribute \src "ls180.v:6140.103-6140.147" + wire $eq$ls180.v:6140$1711_Y + attribute \src "ls180.v:6142.100-6142.144" + wire $eq$ls180.v:6142$1714_Y + attribute \src "ls180.v:6143.103-6143.147" + wire $eq$ls180.v:6143$1718_Y + attribute \src "ls180.v:6145.100-6145.144" + wire $eq$ls180.v:6145$1721_Y + attribute \src "ls180.v:6146.103-6146.147" + wire $eq$ls180.v:6146$1725_Y + attribute \src "ls180.v:6148.102-6148.146" + wire $eq$ls180.v:6148$1728_Y + attribute \src "ls180.v:6149.105-6149.149" + wire $eq$ls180.v:6149$1732_Y + attribute \src "ls180.v:6151.102-6151.146" + wire $eq$ls180.v:6151$1735_Y + attribute \src "ls180.v:6152.105-6152.149" + wire $eq$ls180.v:6152$1739_Y + attribute \src "ls180.v:6154.102-6154.147" + wire $eq$ls180.v:6154$1742_Y + attribute \src "ls180.v:6155.105-6155.150" + wire $eq$ls180.v:6155$1746_Y + attribute \src "ls180.v:6157.102-6157.147" + wire $eq$ls180.v:6157$1749_Y + attribute \src "ls180.v:6158.105-6158.150" + wire $eq$ls180.v:6158$1753_Y + attribute \src "ls180.v:6160.102-6160.147" + wire $eq$ls180.v:6160$1756_Y + attribute \src "ls180.v:6161.105-6161.150" + wire $eq$ls180.v:6161$1760_Y + attribute \src "ls180.v:6163.99-6163.144" + wire $eq$ls180.v:6163$1763_Y + attribute \src "ls180.v:6164.102-6164.147" + wire $eq$ls180.v:6164$1767_Y + attribute \src "ls180.v:6166.100-6166.145" + wire $eq$ls180.v:6166$1770_Y + attribute \src "ls180.v:6167.103-6167.148" + wire $eq$ls180.v:6167$1774_Y + attribute \src "ls180.v:6169.102-6169.147" + wire $eq$ls180.v:6169$1777_Y + attribute \src "ls180.v:6170.105-6170.150" + wire $eq$ls180.v:6170$1781_Y + attribute \src "ls180.v:6172.102-6172.147" + wire $eq$ls180.v:6172$1784_Y + attribute \src "ls180.v:6173.105-6173.150" + wire $eq$ls180.v:6173$1788_Y + attribute \src "ls180.v:6175.102-6175.147" + wire $eq$ls180.v:6175$1791_Y + attribute \src "ls180.v:6176.105-6176.150" + wire $eq$ls180.v:6176$1795_Y + attribute \src "ls180.v:6178.102-6178.147" + wire $eq$ls180.v:6178$1798_Y + attribute \src "ls180.v:6179.105-6179.150" + wire $eq$ls180.v:6179$1802_Y + attribute \src "ls180.v:6201.32-6201.78" + wire $eq$ls180.v:6201$1804_Y + attribute \src "ls180.v:6203.102-6203.146" + wire $eq$ls180.v:6203$1806_Y + attribute \src "ls180.v:6204.105-6204.149" + wire $eq$ls180.v:6204$1810_Y + attribute \src "ls180.v:6206.107-6206.151" + wire $eq$ls180.v:6206$1813_Y + attribute \src "ls180.v:6207.110-6207.154" + wire $eq$ls180.v:6207$1817_Y + attribute \src "ls180.v:6209.107-6209.151" + wire $eq$ls180.v:6209$1820_Y + attribute \src "ls180.v:6210.110-6210.154" + wire $eq$ls180.v:6210$1824_Y + attribute \src "ls180.v:6212.100-6212.144" + wire $eq$ls180.v:6212$1827_Y + attribute \src "ls180.v:6213.103-6213.147" + wire $eq$ls180.v:6213$1831_Y + attribute \src "ls180.v:6218.32-6218.77" + wire $eq$ls180.v:6218$1833_Y + attribute \src "ls180.v:6220.104-6220.148" + wire $eq$ls180.v:6220$1835_Y + attribute \src "ls180.v:6221.107-6221.151" + wire $eq$ls180.v:6221$1839_Y + attribute \src "ls180.v:6223.108-6223.152" + wire $eq$ls180.v:6223$1842_Y + attribute \src "ls180.v:6224.111-6224.155" + wire $eq$ls180.v:6224$1846_Y + attribute \src "ls180.v:6226.98-6226.142" + wire $eq$ls180.v:6226$1849_Y + attribute \src "ls180.v:6227.101-6227.145" + wire $eq$ls180.v:6227$1853_Y + attribute \src "ls180.v:6229.108-6229.152" + wire $eq$ls180.v:6229$1856_Y + attribute \src "ls180.v:6230.111-6230.155" + wire $eq$ls180.v:6230$1860_Y + attribute \src "ls180.v:6232.108-6232.152" + wire $eq$ls180.v:6232$1863_Y + attribute \src "ls180.v:6233.111-6233.155" + wire $eq$ls180.v:6233$1867_Y + attribute \src "ls180.v:6235.109-6235.153" + wire $eq$ls180.v:6235$1870_Y + attribute \src "ls180.v:6236.112-6236.156" + wire $eq$ls180.v:6236$1874_Y + attribute \src "ls180.v:6238.107-6238.151" + wire $eq$ls180.v:6238$1877_Y + attribute \src "ls180.v:6239.110-6239.154" + wire $eq$ls180.v:6239$1881_Y + attribute \src "ls180.v:6241.107-6241.151" + wire $eq$ls180.v:6241$1884_Y + attribute \src "ls180.v:6242.110-6242.154" + wire $eq$ls180.v:6242$1888_Y + attribute \src "ls180.v:6244.107-6244.151" + wire $eq$ls180.v:6244$1891_Y + attribute \src "ls180.v:6245.110-6245.154" + wire $eq$ls180.v:6245$1895_Y + attribute \src "ls180.v:6247.107-6247.151" + wire $eq$ls180.v:6247$1898_Y + attribute \src "ls180.v:6248.110-6248.154" + wire $eq$ls180.v:6248$1902_Y + attribute \src "ls180.v:6263.33-6263.79" + wire $eq$ls180.v:6263$1904_Y + attribute \src "ls180.v:6265.102-6265.147" + wire $eq$ls180.v:6265$1906_Y + attribute \src "ls180.v:6266.105-6266.150" + wire $eq$ls180.v:6266$1910_Y + attribute \src "ls180.v:6268.102-6268.147" + wire $eq$ls180.v:6268$1913_Y + attribute \src "ls180.v:6269.105-6269.150" + wire $eq$ls180.v:6269$1917_Y + attribute \src "ls180.v:6271.100-6271.145" + wire $eq$ls180.v:6271$1920_Y + attribute \src "ls180.v:6272.103-6272.148" + wire $eq$ls180.v:6272$1924_Y + attribute \src "ls180.v:6274.99-6274.144" + wire $eq$ls180.v:6274$1927_Y + attribute \src "ls180.v:6275.102-6275.147" + wire $eq$ls180.v:6275$1931_Y + attribute \src "ls180.v:6277.98-6277.143" + wire $eq$ls180.v:6277$1934_Y + attribute \src "ls180.v:6278.101-6278.146" + wire $eq$ls180.v:6278$1938_Y + attribute \src "ls180.v:6280.97-6280.142" + wire $eq$ls180.v:6280$1941_Y + attribute \src "ls180.v:6281.100-6281.145" + wire $eq$ls180.v:6281$1945_Y + attribute \src "ls180.v:6283.103-6283.148" + wire $eq$ls180.v:6283$1948_Y + attribute \src "ls180.v:6284.106-6284.151" + wire $eq$ls180.v:6284$1952_Y + attribute \src "ls180.v:6303.33-6303.79" + wire $eq$ls180.v:6303$1955_Y + attribute \src "ls180.v:6305.102-6305.147" + wire $eq$ls180.v:6305$1957_Y + attribute \src "ls180.v:6306.105-6306.150" + wire $eq$ls180.v:6306$1961_Y + attribute \src "ls180.v:6308.102-6308.147" + wire $eq$ls180.v:6308$1964_Y + attribute \src "ls180.v:6309.105-6309.150" + wire $eq$ls180.v:6309$1968_Y + attribute \src "ls180.v:6311.100-6311.145" + wire $eq$ls180.v:6311$1971_Y + attribute \src "ls180.v:6312.103-6312.148" + wire $eq$ls180.v:6312$1975_Y + attribute \src "ls180.v:6314.99-6314.144" + wire $eq$ls180.v:6314$1978_Y + attribute \src "ls180.v:6315.102-6315.147" + wire $eq$ls180.v:6315$1982_Y + attribute \src "ls180.v:6317.98-6317.143" + wire $eq$ls180.v:6317$1985_Y + attribute \src "ls180.v:6318.101-6318.146" + wire $eq$ls180.v:6318$1989_Y + attribute \src "ls180.v:6320.97-6320.142" + wire $eq$ls180.v:6320$1992_Y + attribute \src "ls180.v:6321.100-6321.145" + wire $eq$ls180.v:6321$1996_Y + attribute \src "ls180.v:6323.103-6323.148" + wire $eq$ls180.v:6323$1999_Y + attribute \src "ls180.v:6324.106-6324.151" + wire $eq$ls180.v:6324$2003_Y + attribute \src "ls180.v:6326.106-6326.151" + wire $eq$ls180.v:6326$2006_Y + attribute \src "ls180.v:6327.109-6327.154" + wire $eq$ls180.v:6327$2010_Y + attribute \src "ls180.v:6329.106-6329.151" + wire $eq$ls180.v:6329$2013_Y + attribute \src "ls180.v:6330.109-6330.154" + wire $eq$ls180.v:6330$2017_Y + attribute \src "ls180.v:6351.33-6351.79" + wire $eq$ls180.v:6351$2020_Y + attribute \src "ls180.v:6353.99-6353.144" + wire $eq$ls180.v:6353$2022_Y + attribute \src "ls180.v:6354.102-6354.147" + wire $eq$ls180.v:6354$2026_Y + attribute \src "ls180.v:6356.99-6356.144" + wire $eq$ls180.v:6356$2029_Y + attribute \src "ls180.v:6357.102-6357.147" + wire $eq$ls180.v:6357$2033_Y + attribute \src "ls180.v:6359.99-6359.144" + wire $eq$ls180.v:6359$2036_Y + attribute \src "ls180.v:6360.102-6360.147" + wire $eq$ls180.v:6360$2040_Y + attribute \src "ls180.v:6362.99-6362.144" + wire $eq$ls180.v:6362$2043_Y + attribute \src "ls180.v:6363.102-6363.147" + wire $eq$ls180.v:6363$2047_Y + attribute \src "ls180.v:6365.101-6365.146" + wire $eq$ls180.v:6365$2050_Y + attribute \src "ls180.v:6366.104-6366.149" + wire $eq$ls180.v:6366$2054_Y + attribute \src "ls180.v:6368.101-6368.146" + wire $eq$ls180.v:6368$2057_Y + attribute \src "ls180.v:6369.104-6369.149" + wire $eq$ls180.v:6369$2061_Y + attribute \src "ls180.v:6371.101-6371.146" + wire $eq$ls180.v:6371$2064_Y + attribute \src "ls180.v:6372.104-6372.149" + wire $eq$ls180.v:6372$2068_Y + attribute \src "ls180.v:6374.101-6374.146" + wire $eq$ls180.v:6374$2071_Y + attribute \src "ls180.v:6375.104-6375.149" + wire $eq$ls180.v:6375$2075_Y + attribute \src "ls180.v:6377.97-6377.142" + wire $eq$ls180.v:6377$2078_Y + attribute \src "ls180.v:6378.100-6378.145" + wire $eq$ls180.v:6378$2082_Y + attribute \src "ls180.v:6380.107-6380.152" + wire $eq$ls180.v:6380$2085_Y + attribute \src "ls180.v:6381.110-6381.155" + wire $eq$ls180.v:6381$2089_Y + attribute \src "ls180.v:6383.100-6383.146" + wire $eq$ls180.v:6383$2092_Y + attribute \src "ls180.v:6384.103-6384.149" + wire $eq$ls180.v:6384$2096_Y + attribute \src "ls180.v:6386.100-6386.146" + wire $eq$ls180.v:6386$2099_Y + attribute \src "ls180.v:6387.103-6387.149" + wire $eq$ls180.v:6387$2103_Y + attribute \src "ls180.v:6389.100-6389.146" + wire $eq$ls180.v:6389$2106_Y + attribute \src "ls180.v:6390.103-6390.149" + wire $eq$ls180.v:6390$2110_Y + attribute \src "ls180.v:6392.100-6392.146" + wire $eq$ls180.v:6392$2113_Y + attribute \src "ls180.v:6393.103-6393.149" + wire $eq$ls180.v:6393$2117_Y + attribute \src "ls180.v:6395.112-6395.158" + wire $eq$ls180.v:6395$2120_Y + attribute \src "ls180.v:6396.115-6396.161" + wire $eq$ls180.v:6396$2124_Y + attribute \src "ls180.v:6398.113-6398.159" + wire $eq$ls180.v:6398$2127_Y + attribute \src "ls180.v:6399.116-6399.162" + wire $eq$ls180.v:6399$2131_Y + attribute \src "ls180.v:6401.104-6401.150" + wire $eq$ls180.v:6401$2134_Y + attribute \src "ls180.v:6402.107-6402.153" + wire $eq$ls180.v:6402$2138_Y + attribute \src "ls180.v:6419.33-6419.79" + wire $eq$ls180.v:6419$2140_Y + attribute \src "ls180.v:6421.90-6421.135" + wire $eq$ls180.v:6421$2142_Y + attribute \src "ls180.v:6422.93-6422.138" + wire $eq$ls180.v:6422$2146_Y + attribute \src "ls180.v:6424.100-6424.145" + wire $eq$ls180.v:6424$2149_Y + attribute \src "ls180.v:6425.103-6425.148" + wire $eq$ls180.v:6425$2153_Y + attribute \src "ls180.v:6427.101-6427.146" + wire $eq$ls180.v:6427$2156_Y + attribute \src "ls180.v:6428.104-6428.149" + wire $eq$ls180.v:6428$2160_Y + attribute \src "ls180.v:6430.105-6430.150" + wire $eq$ls180.v:6430$2163_Y + attribute \src "ls180.v:6431.108-6431.153" + wire $eq$ls180.v:6431$2167_Y + attribute \src "ls180.v:6433.106-6433.151" + wire $eq$ls180.v:6433$2170_Y + attribute \src "ls180.v:6434.109-6434.154" + wire $eq$ls180.v:6434$2174_Y + attribute \src "ls180.v:6436.104-6436.149" + wire $eq$ls180.v:6436$2177_Y + attribute \src "ls180.v:6437.107-6437.152" + wire $eq$ls180.v:6437$2181_Y + attribute \src "ls180.v:6439.101-6439.146" + wire $eq$ls180.v:6439$2184_Y + attribute \src "ls180.v:6440.104-6440.149" + wire $eq$ls180.v:6440$2188_Y + attribute \src "ls180.v:6442.100-6442.145" + wire $eq$ls180.v:6442$2191_Y + attribute \src "ls180.v:6443.103-6443.148" + wire $eq$ls180.v:6443$2195_Y + attribute \src "ls180.v:6453.33-6453.79" + wire $eq$ls180.v:6453$2197_Y + attribute \src "ls180.v:6455.106-6455.151" + wire $eq$ls180.v:6455$2199_Y + attribute \src "ls180.v:6456.109-6456.154" + wire $eq$ls180.v:6456$2203_Y + attribute \src "ls180.v:6458.106-6458.151" + wire $eq$ls180.v:6458$2206_Y + attribute \src "ls180.v:6459.109-6459.154" + wire $eq$ls180.v:6459$2210_Y + attribute \src "ls180.v:6461.106-6461.151" + wire $eq$ls180.v:6461$2213_Y + attribute \src "ls180.v:6462.109-6462.154" + wire $eq$ls180.v:6462$2217_Y + attribute \src "ls180.v:6464.106-6464.151" + wire $eq$ls180.v:6464$2220_Y + attribute \src "ls180.v:6465.109-6465.154" + wire $eq$ls180.v:6465$2224_Y + attribute \src "ls180.v:6846.41-6846.81" + wire $eq$ls180.v:6846$2261_Y + attribute \src "ls180.v:6846.144-6846.177" + wire $eq$ls180.v:6846$2262_Y + attribute \src "ls180.v:6846.219-6846.252" + wire $eq$ls180.v:6846$2265_Y + attribute \src "ls180.v:6846.294-6846.327" + wire $eq$ls180.v:6846$2268_Y + attribute \src "ls180.v:6870.41-6870.81" + wire $eq$ls180.v:6870$2277_Y + attribute \src "ls180.v:6870.144-6870.177" + wire $eq$ls180.v:6870$2278_Y + attribute \src "ls180.v:6870.219-6870.252" + wire $eq$ls180.v:6870$2281_Y + attribute \src "ls180.v:6870.294-6870.327" + wire $eq$ls180.v:6870$2284_Y + attribute \src "ls180.v:6894.41-6894.81" + wire $eq$ls180.v:6894$2293_Y + attribute \src "ls180.v:6894.144-6894.177" + wire $eq$ls180.v:6894$2294_Y + attribute \src "ls180.v:6894.219-6894.252" + wire $eq$ls180.v:6894$2297_Y + attribute \src "ls180.v:6894.294-6894.327" + wire $eq$ls180.v:6894$2300_Y + attribute \src "ls180.v:6918.41-6918.81" + wire $eq$ls180.v:6918$2309_Y + attribute \src "ls180.v:6918.144-6918.177" + wire $eq$ls180.v:6918$2310_Y + attribute \src "ls180.v:6918.219-6918.252" + wire $eq$ls180.v:6918$2313_Y + attribute \src "ls180.v:6918.294-6918.327" + wire $eq$ls180.v:6918$2316_Y + attribute \src "ls180.v:7511.8-7511.38" + wire $eq$ls180.v:7511$2419_Y + attribute \src "ls180.v:7542.8-7542.42" + wire $eq$ls180.v:7542$2427_Y + attribute \src "ls180.v:7562.38-7562.74" + wire $eq$ls180.v:7562$2430_Y + attribute \src "ls180.v:7569.7-7569.43" + wire $eq$ls180.v:7569$2432_Y + attribute \src "ls180.v:7576.7-7576.43" + wire $eq$ls180.v:7576$2433_Y + attribute \src "ls180.v:7584.7-7584.43" + wire $eq$ls180.v:7584$2434_Y + attribute \src "ls180.v:7636.9-7636.54" + wire $eq$ls180.v:7636$2452_Y + attribute \src "ls180.v:7682.9-7682.54" + wire $eq$ls180.v:7682$2468_Y + attribute \src "ls180.v:7728.9-7728.54" + wire $eq$ls180.v:7728$2484_Y + attribute \src "ls180.v:7774.9-7774.54" + wire $eq$ls180.v:7774$2500_Y + attribute \src "ls180.v:7924.9-7924.41" + wire $eq$ls180.v:7924$2512_Y + attribute \src "ls180.v:7939.9-7939.41" + wire $eq$ls180.v:7939$2515_Y + attribute \src "ls180.v:7945.49-7945.82" + wire $eq$ls180.v:7945$2516_Y + attribute \src "ls180.v:7945.131-7945.164" + wire $eq$ls180.v:7945$2519_Y + attribute \src "ls180.v:7945.213-7945.246" + wire $eq$ls180.v:7945$2522_Y + attribute \src "ls180.v:7945.295-7945.328" + wire $eq$ls180.v:7945$2525_Y + attribute \src "ls180.v:7946.50-7946.83" + wire $eq$ls180.v:7946$2528_Y + attribute \src "ls180.v:7946.132-7946.165" + wire $eq$ls180.v:7946$2531_Y + attribute \src "ls180.v:7946.214-7946.247" + wire $eq$ls180.v:7946$2534_Y + attribute \src "ls180.v:7946.296-7946.329" + wire $eq$ls180.v:7946$2537_Y + attribute \src "ls180.v:7981.9-7981.42" + wire $eq$ls180.v:7981$2549_Y + attribute \src "ls180.v:7984.10-7984.43" + wire $eq$ls180.v:7984$2550_Y + attribute \src "ls180.v:8010.9-8010.42" + wire $eq$ls180.v:8010$2556_Y + attribute \src "ls180.v:8015.10-8015.43" + wire $eq$ls180.v:8015$2557_Y + attribute \src "ls180.v:8222.9-8222.53" + wire $eq$ls180.v:8222$2606_Y + attribute \src "ls180.v:8303.9-8303.54" + wire $eq$ls180.v:8303$2618_Y + attribute \src "ls180.v:8382.9-8382.55" + wire $eq$ls180.v:8382$2630_Y + attribute \src "ls180.v:8605.9-8605.49" + wire $eq$ls180.v:8605$2663_Y + attribute \src "ls180.v:8181.8-8181.54" + wire $ge$ls180.v:8181$2598_Y + attribute \src "ls180.v:8195.8-8195.54" + wire $ge$ls180.v:8195$2602_Y + attribute \src "ls180.v:5155.47-5155.83" + wire $gt$ls180.v:5155$914_Y + attribute \src "ls180.v:5161.7-5161.43" + wire $lt$ls180.v:5161$917_Y + attribute \src "ls180.v:8176.8-8176.43" + wire $lt$ls180.v:8176$2596_Y + attribute \src "ls180.v:8190.8-8190.43" + wire $lt$ls180.v:8190$2600_Y + attribute \src "ls180.v:10071.33-10071.36" + wire width 32 $memrd$\mem$ls180.v:10071$2705_DATA + attribute \src "ls180.v:10082.12-10082.19" + wire width 25 $memrd$\storage$ls180.v:10082$2710_DATA + attribute \src "ls180.v:10089.68-10089.75" + wire width 25 $memrd$\storage$ls180.v:10089$2712_DATA + attribute \src "ls180.v:10096.14-10096.23" + wire width 25 $memrd$\storage_1$ls180.v:10096$2717_DATA + attribute \src "ls180.v:10103.68-10103.77" + wire width 25 $memrd$\storage_1$ls180.v:10103$2719_DATA + attribute \src "ls180.v:10110.14-10110.23" + wire width 25 $memrd$\storage_2$ls180.v:10110$2724_DATA + attribute \src "ls180.v:10117.68-10117.77" + wire width 25 $memrd$\storage_2$ls180.v:10117$2726_DATA + attribute \src "ls180.v:10124.14-10124.23" + wire width 25 $memrd$\storage_3$ls180.v:10124$2731_DATA + attribute \src "ls180.v:10131.68-10131.77" + wire width 25 $memrd$\storage_3$ls180.v:10131$2733_DATA + attribute \src "ls180.v:10139.14-10139.23" + wire width 10 $memrd$\storage_4$ls180.v:10139$2738_DATA + attribute \src "ls180.v:10144.15-10144.24" + wire width 10 $memrd$\storage_4$ls180.v:10144$2740_DATA + attribute \src "ls180.v:10156.14-10156.23" + wire width 10 $memrd$\storage_5$ls180.v:10156$2745_DATA + attribute \src "ls180.v:10161.15-10161.24" + wire width 10 $memrd$\storage_5$ls180.v:10161$2747_DATA + attribute \src "ls180.v:10172.14-10172.23" + wire width 10 $memrd$\storage_6$ls180.v:10172$2752_DATA + attribute \src "ls180.v:10179.45-10179.54" + wire width 10 $memrd$\storage_6$ls180.v:10179$2754_DATA + attribute \src "ls180.v:10186.14-10186.23" + wire width 10 $memrd$\storage_7$ls180.v:10186$2759_DATA + attribute \src "ls180.v:10193.45-10193.54" + wire width 10 $memrd$\storage_7$ls180.v:10193$2761_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10061$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10061$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10061$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10063$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10063$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10063$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10065$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10065$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10065$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 7 $memwr$\mem$ls180.v:10067$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10067$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$ls180.v:10067$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:10081$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10081$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10081$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10095$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10095$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10095$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10109$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10109$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10109$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10123$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10123$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10123$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10138$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10138$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10138$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_5$ls180.v:10155$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10155$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10155$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$ls180.v:10171$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10171$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10171$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$ls180.v:10185$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10185$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10185$12_EN + attribute \src "ls180.v:2969.41-2969.71" + wire $ne$ls180.v:2969$60_Y + attribute \src "ls180.v:3130.70-3130.104" + wire $ne$ls180.v:3130$74_Y + attribute \src "ls180.v:3191.8-3191.142" + wire $ne$ls180.v:3191$93_Y + attribute \src "ls180.v:3223.75-3223.133" + wire $ne$ls180.v:3223$100_Y + attribute \src "ls180.v:3224.75-3224.133" + wire $ne$ls180.v:3224$101_Y + attribute \src "ls180.v:3348.8-3348.142" + wire $ne$ls180.v:3348$123_Y + attribute \src "ls180.v:3380.75-3380.133" + wire $ne$ls180.v:3380$130_Y + attribute \src "ls180.v:3381.75-3381.133" + wire $ne$ls180.v:3381$131_Y + attribute \src "ls180.v:3505.8-3505.142" + wire $ne$ls180.v:3505$153_Y + attribute \src "ls180.v:3537.75-3537.133" + wire $ne$ls180.v:3537$160_Y + attribute \src "ls180.v:3538.75-3538.133" + wire $ne$ls180.v:3538$161_Y + attribute \src "ls180.v:3662.8-3662.142" + wire $ne$ls180.v:3662$183_Y + attribute \src "ls180.v:3694.75-3694.133" + wire $ne$ls180.v:3694$190_Y + attribute \src "ls180.v:3695.75-3695.133" + wire $ne$ls180.v:3695$191_Y + attribute \src "ls180.v:4187.47-4187.80" + wire $ne$ls180.v:4187$589_Y + attribute \src "ls180.v:4188.47-4188.79" + wire $ne$ls180.v:4188$590_Y + attribute \src "ls180.v:4217.47-4217.80" + wire $ne$ls180.v:4217$600_Y + attribute \src "ls180.v:4218.47-4218.79" + wire $ne$ls180.v:4218$601_Y + attribute \src "ls180.v:4687.32-4687.89" + wire $ne$ls180.v:4687$681_Y + attribute \src "ls180.v:5334.10-5334.56" + wire $ne$ls180.v:5334$978_Y + attribute \src "ls180.v:5439.51-5439.87" + wire $ne$ls180.v:5439$992_Y + attribute \src "ls180.v:5440.51-5440.86" + wire $ne$ls180.v:5440$993_Y + attribute \src "ls180.v:5647.51-5647.87" + wire $ne$ls180.v:5647$1023_Y + attribute \src "ls180.v:5648.51-5648.86" + wire $ne$ls180.v:5648$1024_Y + attribute \src "ls180.v:5679.79-5679.119" + wire $ne$ls180.v:5679$1027_Y + attribute \src "ls180.v:7501.7-7501.52" + wire $ne$ls180.v:7501$2414_Y + attribute \src "ls180.v:7551.9-7551.43" + wire $ne$ls180.v:7551$2428_Y + attribute \src "ls180.v:7587.8-7587.44" + wire $ne$ls180.v:7587$2435_Y + attribute \src "ls180.v:8525.9-8525.47" + wire $ne$ls180.v:8525$2650_Y + attribute \src "ls180.v:2777.45-2777.80" + wire $not$ls180.v:2777$14_Y + attribute \src "ls180.v:2816.61-2816.94" + wire $not$ls180.v:2816$19_Y + attribute \src "ls180.v:2817.61-2817.94" + wire $not$ls180.v:2817$20_Y + attribute \src "ls180.v:2837.45-2837.80" + wire $not$ls180.v:2837$25_Y + attribute \src "ls180.v:2876.61-2876.94" + wire $not$ls180.v:2876$30_Y + attribute \src "ls180.v:2877.61-2877.94" + wire $not$ls180.v:2877$31_Y + attribute \src "ls180.v:2897.45-2897.83" + wire $not$ls180.v:2897$36_Y + attribute \src "ls180.v:2936.61-2936.94" + wire $not$ls180.v:2936$41_Y + attribute \src "ls180.v:2937.61-2937.94" + wire $not$ls180.v:2937$42_Y + attribute \src "ls180.v:3079.34-3079.64" + wire $not$ls180.v:3079$66_Y + attribute \src "ls180.v:3080.31-3080.61" + wire $not$ls180.v:3080$67_Y + attribute \src "ls180.v:3081.32-3081.62" + wire $not$ls180.v:3081$68_Y + attribute \src "ls180.v:3082.32-3082.62" + wire $not$ls180.v:3082$69_Y + attribute \src "ls180.v:3124.33-3124.56" + wire $not$ls180.v:3124$72_Y + attribute \src "ls180.v:3225.58-3225.106" + wire $not$ls180.v:3225$102_Y + attribute \src "ls180.v:3279.9-3279.45" + wire $not$ls180.v:3279$107_Y + attribute \src "ls180.v:3382.58-3382.106" + wire $not$ls180.v:3382$132_Y + attribute \src "ls180.v:3436.9-3436.45" + wire $not$ls180.v:3436$137_Y + attribute \src "ls180.v:3539.58-3539.106" + wire $not$ls180.v:3539$162_Y + attribute \src "ls180.v:3593.9-3593.45" + wire $not$ls180.v:3593$167_Y + attribute \src "ls180.v:3696.58-3696.106" + wire $not$ls180.v:3696$192_Y + attribute \src "ls180.v:3750.9-3750.45" + wire $not$ls180.v:3750$197_Y + attribute \src "ls180.v:3792.149-3792.187" + wire $not$ls180.v:3792$200_Y + attribute \src "ls180.v:3792.193-3792.230" + wire $not$ls180.v:3792$202_Y + attribute \src "ls180.v:3793.149-3793.187" + wire $not$ls180.v:3793$206_Y + attribute \src "ls180.v:3793.193-3793.230" + wire $not$ls180.v:3793$208_Y + attribute \src "ls180.v:3809.43-3809.73" + wire width 2 $not$ls180.v:3809$236_Y + attribute \src "ls180.v:3812.205-3812.245" + wire $not$ls180.v:3812$239_Y + attribute \src "ls180.v:3812.251-3812.290" + wire $not$ls180.v:3812$241_Y + attribute \src "ls180.v:3812.159-3812.292" + wire $not$ls180.v:3812$243_Y + attribute \src "ls180.v:3813.205-3813.245" + wire $not$ls180.v:3813$252_Y + attribute \src "ls180.v:3813.251-3813.290" + wire $not$ls180.v:3813$254_Y + attribute \src "ls180.v:3813.159-3813.292" + wire $not$ls180.v:3813$256_Y + attribute \src "ls180.v:3814.205-3814.245" + wire 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"ls180.v:5016.899-5016.983" + wire $xor$ls180.v:5016$876_Y + attribute \src "ls180.v:5016.634-5016.718" + wire $xor$ls180.v:5016$877_Y + attribute \src "ls180.v:5016.588-5016.719" + wire $xor$ls180.v:5016$878_Y + attribute \src "ls180.v:5016.234-5016.318" + wire $xor$ls180.v:5016$879_Y + attribute \src "ls180.v:5016.187-5016.319" + wire $xor$ls180.v:5016$880_Y + attribute \src "ls180.v:5017.899-5017.983" + wire $xor$ls180.v:5017$881_Y + attribute \src "ls180.v:5017.634-5017.718" + wire $xor$ls180.v:5017$882_Y + attribute \src "ls180.v:5017.588-5017.719" + wire $xor$ls180.v:5017$883_Y + attribute \src "ls180.v:5017.234-5017.318" + wire $xor$ls180.v:5017$884_Y + attribute \src "ls180.v:5017.187-5017.319" + wire $xor$ls180.v:5017$885_Y + attribute \src "ls180.v:5168.879-5168.961" + wire $xor$ls180.v:5168$918_Y + attribute \src "ls180.v:5168.620-5168.702" + wire $xor$ls180.v:5168$919_Y + attribute \src "ls180.v:5168.575-5168.703" + wire $xor$ls180.v:5168$920_Y + attribute \src "ls180.v:5168.229-5168.311" + wire $xor$ls180.v:5168$921_Y + attribute \src "ls180.v:5168.183-5168.312" + wire $xor$ls180.v:5168$922_Y + attribute \src "ls180.v:5169.879-5169.961" + wire $xor$ls180.v:5169$923_Y + attribute \src "ls180.v:5169.620-5169.702" + wire $xor$ls180.v:5169$924_Y + attribute \src "ls180.v:5169.575-5169.703" + wire $xor$ls180.v:5169$925_Y + attribute \src "ls180.v:5169.229-5169.311" + wire $xor$ls180.v:5169$926_Y + attribute \src "ls180.v:5169.183-5169.312" + wire $xor$ls180.v:5169$927_Y + attribute \src "ls180.v:5178.879-5178.961" + wire $xor$ls180.v:5178$929_Y + attribute \src "ls180.v:5178.620-5178.702" + wire $xor$ls180.v:5178$930_Y + attribute \src "ls180.v:5178.575-5178.703" + wire $xor$ls180.v:5178$931_Y + attribute \src "ls180.v:5178.229-5178.311" + wire $xor$ls180.v:5178$932_Y + attribute \src "ls180.v:5178.183-5178.312" + wire $xor$ls180.v:5178$933_Y + attribute \src "ls180.v:5179.879-5179.961" + wire $xor$ls180.v:5179$934_Y + attribute \src "ls180.v:5179.620-5179.702" + wire $xor$ls180.v:5179$935_Y + attribute \src "ls180.v:5179.575-5179.703" + wire $xor$ls180.v:5179$936_Y + attribute \src "ls180.v:5179.229-5179.311" + wire $xor$ls180.v:5179$937_Y + attribute \src "ls180.v:5179.183-5179.312" + wire $xor$ls180.v:5179$938_Y + attribute \src "ls180.v:5188.879-5188.961" + wire $xor$ls180.v:5188$940_Y + attribute \src "ls180.v:5188.620-5188.702" + wire $xor$ls180.v:5188$941_Y + attribute \src "ls180.v:5188.575-5188.703" + wire $xor$ls180.v:5188$942_Y + attribute \src "ls180.v:5188.229-5188.311" + wire $xor$ls180.v:5188$943_Y + attribute \src "ls180.v:5188.183-5188.312" + wire $xor$ls180.v:5188$944_Y + attribute \src "ls180.v:5189.879-5189.961" + wire $xor$ls180.v:5189$945_Y + attribute \src "ls180.v:5189.620-5189.702" + wire $xor$ls180.v:5189$946_Y + attribute \src "ls180.v:5189.575-5189.703" + wire $xor$ls180.v:5189$947_Y + attribute \src "ls180.v:5189.229-5189.311" + wire $xor$ls180.v:5189$948_Y + attribute \src "ls180.v:5189.183-5189.312" + wire $xor$ls180.v:5189$949_Y + attribute \src "ls180.v:5198.879-5198.961" + wire $xor$ls180.v:5198$951_Y + attribute \src "ls180.v:5198.620-5198.702" + wire $xor$ls180.v:5198$952_Y + attribute \src "ls180.v:5198.575-5198.703" + wire $xor$ls180.v:5198$953_Y + attribute \src "ls180.v:5198.229-5198.311" + wire $xor$ls180.v:5198$954_Y + attribute \src "ls180.v:5198.183-5198.312" + wire $xor$ls180.v:5198$955_Y + attribute \src "ls180.v:5199.879-5199.961" + wire $xor$ls180.v:5199$956_Y + attribute \src "ls180.v:5199.620-5199.702" + wire $xor$ls180.v:5199$957_Y + attribute \src "ls180.v:5199.575-5199.703" + wire $xor$ls180.v:5199$958_Y + attribute \src "ls180.v:5199.229-5199.311" + wire $xor$ls180.v:5199$959_Y + attribute \src "ls180.v:5199.183-5199.312" + wire $xor$ls180.v:5199$960_Y + attribute \src "ls180.v:1749.11-1749.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1748.11-1748.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1751.11-1751.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1750.11-1750.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1753.11-1753.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1752.11-1752.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1755.11-1755.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1754.11-1754.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2600.5-2600.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2601.12-2601.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2613.5-2613.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2614.5-2614.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2618.12-2618.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2619.5-2619.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2620.5-2620.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2621.12-2621.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2622.5-2622.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2623.5-2623.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2624.12-2624.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2625.5-2625.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2602.11-2602.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2626.5-2626.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2627.12-2627.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2628.5-2628.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2629.5-2629.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2630.12-2630.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2631.12-2631.42" + wire width 32 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2632.11-2632.41" + wire width 4 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2633.5-2633.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2634.5-2634.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2635.5-2635.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2603.5-2603.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2636.11-2636.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2637.11-2637.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2604.5-2604.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2605.5-2605.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2609.5-2609.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2610.12-2610.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2611.11-2611.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2612.5-2612.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2606.5-2606.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2607.5-2607.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2608.5-2608.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2615.5-2615.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2616.5-2616.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2617.5-2617.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1735.5-1735.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1734.5-1734.29" + wire \builder_converter0_state + attribute \src "ls180.v:1739.5-1739.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1738.5-1738.29" + wire \builder_converter1_state + attribute \src "ls180.v:1743.5-1743.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1742.5-1742.29" + wire \builder_converter2_state + attribute \src "ls180.v:1780.5-1780.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1779.5-1779.28" + wire \builder_converter_state + attribute \src "ls180.v:1900.12-1900.25" + wire width 20 \builder_count + attribute \src "ls180.v:2588.13-2588.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2591.12-2591.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2590.12-2590.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2589.6-2589.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:1938.12-1938.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:1937.6-1937.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:1940.12-1940.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:1939.6-1939.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:1934.12-1934.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:1933.6-1933.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:1936.12-1936.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:1935.6-1935.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:1930.12-1930.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:1929.6-1929.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:1932.12-1932.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:1931.6-1931.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:1926.12-1926.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:1925.6-1925.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:1928.12-1928.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:1927.6-1927.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:1906.6-1906.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:1905.6-1905.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:1908.6-1908.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:1907.6-1907.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:1922.12-1922.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:1921.6-1921.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:1924.12-1924.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:1923.6-1923.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:1918.12-1918.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:1917.6-1917.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:1920.12-1920.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:1919.6-1919.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:1914.12-1914.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:1913.6-1913.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:1916.12-1916.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:1915.6-1915.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:1910.12-1910.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:1909.6-1909.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:1912.12-1912.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:1911.6-1911.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:1941.6-1941.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2412.12-2412.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2411.6-2411.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2414.12-2414.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2413.6-2413.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2408.12-2408.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2407.6-2407.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2410.12-2410.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2409.6-2409.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2428.6-2428.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2427.6-2427.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2430.6-2430.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2429.6-2429.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2432.6-2432.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2431.6-2431.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2434.6-2434.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2433.6-2433.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2424.12-2424.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2423.6-2423.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2426.12-2426.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2425.6-2425.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2420.12-2420.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2419.6-2419.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2422.12-2422.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2421.6-2421.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2435.6-2435.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2416.6-2416.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2415.6-2415.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2418.6-2418.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2417.6-2417.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2473.12-2473.44" + wire width 8 \builder_csrbank11_clk_divider0_r + attribute \src "ls180.v:2472.6-2472.39" + wire \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:2475.12-2475.44" + wire width 8 \builder_csrbank11_clk_divider0_w + attribute \src "ls180.v:2474.6-2474.39" + wire \builder_csrbank11_clk_divider0_we + attribute \src "ls180.v:2469.12-2469.44" + wire width 8 \builder_csrbank11_clk_divider1_r + attribute \src "ls180.v:2468.6-2468.39" + wire \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:2471.12-2471.44" + wire width 8 \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:2470.6-2470.39" + wire \builder_csrbank11_clk_divider1_we + attribute \src "ls180.v:2445.12-2445.40" + wire width 8 \builder_csrbank11_control0_r + attribute \src "ls180.v:2444.6-2444.35" + wire \builder_csrbank11_control0_re + attribute \src "ls180.v:2447.12-2447.40" + wire width 8 \builder_csrbank11_control0_w + attribute \src "ls180.v:2446.6-2446.35" + wire \builder_csrbank11_control0_we + attribute \src "ls180.v:2441.12-2441.40" + wire width 8 \builder_csrbank11_control1_r + attribute \src "ls180.v:2440.6-2440.35" + wire \builder_csrbank11_control1_re + attribute \src "ls180.v:2443.12-2443.40" + wire width 8 \builder_csrbank11_control1_w + attribute \src "ls180.v:2442.6-2442.35" + wire \builder_csrbank11_control1_we + attribute \src "ls180.v:2461.6-2461.29" + wire \builder_csrbank11_cs0_r + attribute \src "ls180.v:2460.6-2460.30" + wire \builder_csrbank11_cs0_re + attribute \src "ls180.v:2463.6-2463.29" + wire \builder_csrbank11_cs0_w + attribute \src "ls180.v:2462.6-2462.30" + wire \builder_csrbank11_cs0_we + attribute \src "ls180.v:2465.6-2465.35" + wire \builder_csrbank11_loopback0_r + attribute \src "ls180.v:2464.6-2464.36" + wire \builder_csrbank11_loopback0_re + attribute \src "ls180.v:2467.6-2467.35" + wire \builder_csrbank11_loopback0_w + attribute \src "ls180.v:2466.6-2466.36" + wire \builder_csrbank11_loopback0_we + attribute \src "ls180.v:2457.12-2457.36" + wire width 8 \builder_csrbank11_miso_r + attribute \src "ls180.v:2456.6-2456.31" + wire \builder_csrbank11_miso_re + attribute \src "ls180.v:2459.12-2459.36" + wire width 8 \builder_csrbank11_miso_w + attribute \src "ls180.v:2458.6-2458.31" + wire \builder_csrbank11_miso_we + attribute \src "ls180.v:2453.12-2453.37" + wire width 8 \builder_csrbank11_mosi0_r + attribute \src "ls180.v:2452.6-2452.32" + wire \builder_csrbank11_mosi0_re + attribute \src "ls180.v:2455.12-2455.37" + wire width 8 \builder_csrbank11_mosi0_w + attribute \src "ls180.v:2454.6-2454.32" + wire \builder_csrbank11_mosi0_we + attribute \src "ls180.v:2476.6-2476.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2449.6-2449.32" + wire \builder_csrbank11_status_r + attribute \src "ls180.v:2448.6-2448.33" + wire \builder_csrbank11_status_re + attribute \src "ls180.v:2451.6-2451.32" + wire \builder_csrbank11_status_w + attribute \src "ls180.v:2450.6-2450.33" + wire \builder_csrbank11_status_we + attribute \src "ls180.v:2514.6-2514.29" + wire \builder_csrbank12_en0_r + attribute \src "ls180.v:2513.6-2513.30" + wire \builder_csrbank12_en0_re + attribute \src "ls180.v:2516.6-2516.29" + wire \builder_csrbank12_en0_w + attribute \src "ls180.v:2515.6-2515.30" + wire \builder_csrbank12_en0_we + attribute \src "ls180.v:2538.6-2538.36" + wire \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2537.6-2537.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2540.6-2540.36" + wire \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2539.6-2539.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2494.12-2494.37" + wire width 8 \builder_csrbank12_load0_r + attribute \src "ls180.v:2493.6-2493.32" + wire \builder_csrbank12_load0_re + attribute \src "ls180.v:2496.12-2496.37" + wire width 8 \builder_csrbank12_load0_w + attribute \src "ls180.v:2495.6-2495.32" + wire \builder_csrbank12_load0_we + attribute \src "ls180.v:2490.12-2490.37" + wire width 8 \builder_csrbank12_load1_r + attribute \src "ls180.v:2489.6-2489.32" + wire \builder_csrbank12_load1_re + attribute \src "ls180.v:2492.12-2492.37" + wire width 8 \builder_csrbank12_load1_w + attribute \src "ls180.v:2491.6-2491.32" + wire \builder_csrbank12_load1_we + attribute \src "ls180.v:2486.12-2486.37" + wire width 8 \builder_csrbank12_load2_r + attribute \src "ls180.v:2485.6-2485.32" + wire \builder_csrbank12_load2_re + attribute \src "ls180.v:2488.12-2488.37" + wire width 8 \builder_csrbank12_load2_w + attribute \src "ls180.v:2487.6-2487.32" + wire \builder_csrbank12_load2_we + attribute \src "ls180.v:2482.12-2482.37" + wire width 8 \builder_csrbank12_load3_r + attribute \src "ls180.v:2481.6-2481.32" + wire \builder_csrbank12_load3_re + attribute \src "ls180.v:2484.12-2484.37" + wire width 8 \builder_csrbank12_load3_w + attribute \src "ls180.v:2483.6-2483.32" + wire \builder_csrbank12_load3_we + attribute \src "ls180.v:2510.12-2510.39" + wire width 8 \builder_csrbank12_reload0_r + attribute \src "ls180.v:2509.6-2509.34" + wire \builder_csrbank12_reload0_re + attribute \src "ls180.v:2512.12-2512.39" + wire width 8 \builder_csrbank12_reload0_w + attribute \src "ls180.v:2511.6-2511.34" + wire \builder_csrbank12_reload0_we + attribute \src "ls180.v:2506.12-2506.39" + wire width 8 \builder_csrbank12_reload1_r + attribute \src "ls180.v:2505.6-2505.34" + wire \builder_csrbank12_reload1_re + attribute \src "ls180.v:2508.12-2508.39" + wire width 8 \builder_csrbank12_reload1_w + attribute \src "ls180.v:2507.6-2507.34" + wire \builder_csrbank12_reload1_we + attribute \src "ls180.v:2502.12-2502.39" + wire width 8 \builder_csrbank12_reload2_r + attribute \src "ls180.v:2501.6-2501.34" + wire \builder_csrbank12_reload2_re + attribute \src "ls180.v:2504.12-2504.39" + wire width 8 \builder_csrbank12_reload2_w + attribute \src "ls180.v:2503.6-2503.34" + wire \builder_csrbank12_reload2_we + attribute \src "ls180.v:2498.12-2498.39" + wire width 8 \builder_csrbank12_reload3_r + attribute \src "ls180.v:2497.6-2497.34" + wire \builder_csrbank12_reload3_re + attribute \src "ls180.v:2500.12-2500.39" + wire width 8 \builder_csrbank12_reload3_w + attribute \src "ls180.v:2499.6-2499.34" + wire \builder_csrbank12_reload3_we + attribute \src "ls180.v:2541.6-2541.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2518.6-2518.39" + wire \builder_csrbank12_update_value0_r + attribute \src "ls180.v:2517.6-2517.40" + wire \builder_csrbank12_update_value0_re + attribute \src "ls180.v:2520.6-2520.39" + wire \builder_csrbank12_update_value0_w + attribute \src "ls180.v:2519.6-2519.40" + wire \builder_csrbank12_update_value0_we + attribute \src "ls180.v:2534.12-2534.38" + wire width 8 \builder_csrbank12_value0_r + attribute \src "ls180.v:2533.6-2533.33" + wire \builder_csrbank12_value0_re + attribute \src "ls180.v:2536.12-2536.38" + wire width 8 \builder_csrbank12_value0_w + attribute \src "ls180.v:2535.6-2535.33" + wire \builder_csrbank12_value0_we + attribute \src "ls180.v:2530.12-2530.38" + wire width 8 \builder_csrbank12_value1_r + attribute \src "ls180.v:2529.6-2529.33" + wire \builder_csrbank12_value1_re + attribute \src "ls180.v:2532.12-2532.38" + wire width 8 \builder_csrbank12_value1_w + attribute \src "ls180.v:2531.6-2531.33" + wire \builder_csrbank12_value1_we + attribute \src "ls180.v:2526.12-2526.38" + wire width 8 \builder_csrbank12_value2_r + attribute \src "ls180.v:2525.6-2525.33" + wire \builder_csrbank12_value2_re + attribute \src "ls180.v:2528.12-2528.38" + wire width 8 \builder_csrbank12_value2_w + attribute \src "ls180.v:2527.6-2527.33" + wire \builder_csrbank12_value2_we + attribute \src "ls180.v:2522.12-2522.38" + wire width 8 \builder_csrbank12_value3_r + attribute \src "ls180.v:2521.6-2521.33" + wire \builder_csrbank12_value3_re + attribute \src "ls180.v:2524.12-2524.38" + wire width 8 \builder_csrbank12_value3_w + attribute \src "ls180.v:2523.6-2523.33" + wire \builder_csrbank12_value3_we + attribute \src "ls180.v:2555.12-2555.42" + wire width 2 \builder_csrbank13_ev_enable0_r + attribute \src "ls180.v:2554.6-2554.37" + wire \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:2557.12-2557.42" + wire width 2 \builder_csrbank13_ev_enable0_w + attribute \src "ls180.v:2556.6-2556.37" + wire \builder_csrbank13_ev_enable0_we + attribute \src "ls180.v:2551.6-2551.33" + wire \builder_csrbank13_rxempty_r + attribute \src "ls180.v:2550.6-2550.34" + wire \builder_csrbank13_rxempty_re + attribute \src "ls180.v:2553.6-2553.33" + wire \builder_csrbank13_rxempty_w + attribute \src "ls180.v:2552.6-2552.34" + wire \builder_csrbank13_rxempty_we + attribute \src "ls180.v:2563.6-2563.32" + wire \builder_csrbank13_rxfull_r + attribute \src "ls180.v:2562.6-2562.33" + wire \builder_csrbank13_rxfull_re + attribute \src "ls180.v:2565.6-2565.32" + wire \builder_csrbank13_rxfull_w + attribute \src "ls180.v:2564.6-2564.33" + wire \builder_csrbank13_rxfull_we + attribute \src "ls180.v:2566.6-2566.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2559.6-2559.33" + wire \builder_csrbank13_txempty_r + attribute \src "ls180.v:2558.6-2558.34" + wire \builder_csrbank13_txempty_re + attribute \src "ls180.v:2561.6-2561.33" + wire \builder_csrbank13_txempty_w + attribute \src "ls180.v:2560.6-2560.34" + wire \builder_csrbank13_txempty_we + attribute \src "ls180.v:2547.6-2547.32" + wire \builder_csrbank13_txfull_r + attribute \src "ls180.v:2546.6-2546.33" + wire \builder_csrbank13_txfull_re + attribute \src "ls180.v:2549.6-2549.32" + wire \builder_csrbank13_txfull_w + attribute \src "ls180.v:2548.6-2548.33" + wire \builder_csrbank13_txfull_we + attribute \src "ls180.v:2587.6-2587.27" + wire \builder_csrbank14_sel + attribute \src "ls180.v:2584.12-2584.44" + wire width 8 \builder_csrbank14_tuning_word0_r + attribute \src "ls180.v:2583.6-2583.39" + wire \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:2586.12-2586.44" + wire width 8 \builder_csrbank14_tuning_word0_w + attribute \src "ls180.v:2585.6-2585.39" + wire \builder_csrbank14_tuning_word0_we + attribute \src "ls180.v:2580.12-2580.44" + wire width 8 \builder_csrbank14_tuning_word1_r + attribute \src "ls180.v:2579.6-2579.39" + wire \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:2582.12-2582.44" + wire width 8 \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:2581.6-2581.39" + wire \builder_csrbank14_tuning_word1_we + attribute \src "ls180.v:2576.12-2576.44" + wire width 8 \builder_csrbank14_tuning_word2_r + attribute \src "ls180.v:2575.6-2575.39" + wire \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:2578.12-2578.44" + wire width 8 \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:2577.6-2577.39" + wire \builder_csrbank14_tuning_word2_we + attribute \src "ls180.v:2572.12-2572.44" + wire width 8 \builder_csrbank14_tuning_word3_r + attribute \src "ls180.v:2571.6-2571.39" + wire \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:2574.12-2574.44" + wire width 8 \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:2573.6-2573.39" + wire \builder_csrbank14_tuning_word3_we + attribute \src "ls180.v:1959.12-1959.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:1958.6-1958.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:1961.12-1961.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:1960.6-1960.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:1955.12-1955.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:1954.6-1954.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:1957.12-1957.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:1956.6-1956.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:1951.12-1951.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:1950.6-1950.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:1953.12-1953.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:1952.6-1952.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:1947.12-1947.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:1946.6-1946.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:1949.12-1949.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:1948.6-1948.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:1967.12-1967.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:1966.6-1966.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:1969.12-1969.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:1968.6-1968.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:1963.12-1963.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:1962.6-1962.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:1965.12-1965.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:1964.6-1964.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:1970.6-1970.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:1980.6-1980.26" + wire \builder_csrbank2_r_r + attribute \src "ls180.v:1979.6-1979.27" + wire \builder_csrbank2_r_re + attribute \src "ls180.v:1982.6-1982.26" + wire \builder_csrbank2_r_w + attribute \src "ls180.v:1981.6-1981.27" + wire \builder_csrbank2_r_we + attribute \src "ls180.v:1983.6-1983.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:1976.12-1976.33" + wire width 3 \builder_csrbank2_w0_r + attribute \src "ls180.v:1975.6-1975.28" + wire \builder_csrbank2_w0_re + attribute \src "ls180.v:1978.12-1978.33" + wire width 3 \builder_csrbank2_w0_w + attribute \src "ls180.v:1977.6-1977.28" + wire \builder_csrbank2_w0_we + attribute \src "ls180.v:1989.6-1989.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:1988.6-1988.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:1991.6-1991.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:1990.6-1990.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:2021.12-2021.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:2020.6-2020.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:2023.12-2023.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:2022.6-2022.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:2017.12-2017.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:2016.6-2016.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:2019.12-2019.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:2018.6-2018.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:2013.12-2013.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:2012.6-2012.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:2015.12-2015.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:2014.6-2014.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:2009.12-2009.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:2008.6-2008.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:2011.12-2011.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:2010.6-2010.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2024.6-2024.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:2005.12-2005.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:2004.6-2004.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:2007.12-2007.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:2006.6-2006.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:2001.12-2001.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:2000.6-2000.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:2003.12-2003.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:2002.6-2002.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:1997.12-1997.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:1996.6-1996.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:1999.12-1999.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:1998.6-1998.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:1993.12-1993.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:1992.6-1992.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:1995.12-1995.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:1994.6-1994.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2030.6-2030.32" + wire \builder_csrbank4_enable0_r + attribute \src "ls180.v:2029.6-2029.33" + wire \builder_csrbank4_enable0_re + attribute \src "ls180.v:2032.6-2032.32" + wire \builder_csrbank4_enable0_w + attribute \src "ls180.v:2031.6-2031.33" + wire \builder_csrbank4_enable0_we + attribute \src "ls180.v:2062.12-2062.38" + wire width 8 \builder_csrbank4_period0_r + attribute \src "ls180.v:2061.6-2061.33" + wire \builder_csrbank4_period0_re + attribute \src "ls180.v:2064.12-2064.38" + wire width 8 \builder_csrbank4_period0_w + attribute \src "ls180.v:2063.6-2063.33" + wire \builder_csrbank4_period0_we + attribute \src "ls180.v:2058.12-2058.38" + wire width 8 \builder_csrbank4_period1_r + attribute \src "ls180.v:2057.6-2057.33" + wire \builder_csrbank4_period1_re + attribute \src "ls180.v:2060.12-2060.38" + wire width 8 \builder_csrbank4_period1_w + attribute \src "ls180.v:2059.6-2059.33" + wire \builder_csrbank4_period1_we + attribute \src "ls180.v:2054.12-2054.38" + wire width 8 \builder_csrbank4_period2_r + attribute \src "ls180.v:2053.6-2053.33" + wire \builder_csrbank4_period2_re + attribute \src "ls180.v:2056.12-2056.38" + wire width 8 \builder_csrbank4_period2_w + attribute \src "ls180.v:2055.6-2055.33" + wire \builder_csrbank4_period2_we + attribute \src "ls180.v:2050.12-2050.38" + wire width 8 \builder_csrbank4_period3_r + attribute \src "ls180.v:2049.6-2049.33" + wire \builder_csrbank4_period3_re + attribute \src "ls180.v:2052.12-2052.38" + wire width 8 \builder_csrbank4_period3_w + attribute \src "ls180.v:2051.6-2051.33" + wire \builder_csrbank4_period3_we + attribute \src "ls180.v:2065.6-2065.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2046.12-2046.37" + wire width 8 \builder_csrbank4_width0_r + attribute \src "ls180.v:2045.6-2045.32" + wire \builder_csrbank4_width0_re + attribute \src "ls180.v:2048.12-2048.37" + wire width 8 \builder_csrbank4_width0_w + attribute \src "ls180.v:2047.6-2047.32" + wire \builder_csrbank4_width0_we + attribute \src "ls180.v:2042.12-2042.37" + wire width 8 \builder_csrbank4_width1_r + attribute \src "ls180.v:2041.6-2041.32" + wire \builder_csrbank4_width1_re + attribute \src "ls180.v:2044.12-2044.37" + wire width 8 \builder_csrbank4_width1_w + attribute \src "ls180.v:2043.6-2043.32" + wire \builder_csrbank4_width1_we + attribute \src "ls180.v:2038.12-2038.37" + wire width 8 \builder_csrbank4_width2_r + attribute \src "ls180.v:2037.6-2037.32" + wire \builder_csrbank4_width2_re + attribute \src "ls180.v:2040.12-2040.37" + wire width 8 \builder_csrbank4_width2_w + attribute \src "ls180.v:2039.6-2039.32" + wire \builder_csrbank4_width2_we + attribute \src "ls180.v:2034.12-2034.37" + wire width 8 \builder_csrbank4_width3_r + attribute \src "ls180.v:2033.6-2033.32" + wire \builder_csrbank4_width3_re + attribute \src "ls180.v:2036.12-2036.37" + wire width 8 \builder_csrbank4_width3_w + attribute \src "ls180.v:2035.6-2035.32" + wire \builder_csrbank4_width3_we + attribute \src "ls180.v:2099.12-2099.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "ls180.v:2098.6-2098.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:2101.12-2101.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:2100.6-2100.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "ls180.v:2095.12-2095.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "ls180.v:2094.6-2094.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:2097.12-2097.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:2096.6-2096.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "ls180.v:2091.12-2091.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "ls180.v:2090.6-2090.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:2093.12-2093.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:2092.6-2092.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "ls180.v:2087.12-2087.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "ls180.v:2086.6-2086.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:2089.12-2089.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:2088.6-2088.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "ls180.v:2083.12-2083.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "ls180.v:2082.6-2082.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:2085.12-2085.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:2084.6-2084.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "ls180.v:2079.12-2079.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "ls180.v:2078.6-2078.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:2081.12-2081.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:2080.6-2080.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "ls180.v:2075.12-2075.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "ls180.v:2074.6-2074.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:2077.12-2077.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:2076.6-2076.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "ls180.v:2071.12-2071.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "ls180.v:2070.6-2070.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:2073.12-2073.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:2072.6-2072.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "ls180.v:2123.6-2123.33" + wire \builder_csrbank5_dma_done_r + attribute \src "ls180.v:2122.6-2122.34" + wire \builder_csrbank5_dma_done_re + attribute \src "ls180.v:2125.6-2125.33" + wire \builder_csrbank5_dma_done_w + attribute \src "ls180.v:2124.6-2124.34" + wire \builder_csrbank5_dma_done_we + attribute \src "ls180.v:2119.6-2119.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "ls180.v:2118.6-2118.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:2121.6-2121.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "ls180.v:2120.6-2120.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "ls180.v:2115.12-2115.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "ls180.v:2114.6-2114.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:2117.12-2117.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:2116.6-2116.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "ls180.v:2111.12-2111.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "ls180.v:2110.6-2110.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:2113.12-2113.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:2112.6-2112.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "ls180.v:2107.12-2107.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "ls180.v:2106.6-2106.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:2109.12-2109.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:2108.6-2108.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "ls180.v:2103.12-2103.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "ls180.v:2102.6-2102.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:2105.12-2105.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:2104.6-2104.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "ls180.v:2127.6-2127.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "ls180.v:2126.6-2126.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:2129.6-2129.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "ls180.v:2128.6-2128.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "ls180.v:2130.6-2130.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2260.12-2260.43" + wire width 8 \builder_csrbank6_block_count0_r + attribute \src "ls180.v:2259.6-2259.38" + wire \builder_csrbank6_block_count0_re + attribute \src "ls180.v:2262.12-2262.43" + wire width 8 \builder_csrbank6_block_count0_w + attribute \src "ls180.v:2261.6-2261.38" + wire \builder_csrbank6_block_count0_we + attribute \src "ls180.v:2256.12-2256.43" + wire width 8 \builder_csrbank6_block_count1_r + attribute \src "ls180.v:2255.6-2255.38" + wire \builder_csrbank6_block_count1_re + attribute \src "ls180.v:2258.12-2258.43" + wire width 8 \builder_csrbank6_block_count1_w + attribute \src "ls180.v:2257.6-2257.38" + wire \builder_csrbank6_block_count1_we + attribute \src "ls180.v:2252.12-2252.43" + wire width 8 \builder_csrbank6_block_count2_r + attribute \src "ls180.v:2251.6-2251.38" + wire \builder_csrbank6_block_count2_re + attribute \src "ls180.v:2254.12-2254.43" + wire width 8 \builder_csrbank6_block_count2_w + attribute \src "ls180.v:2253.6-2253.38" + wire \builder_csrbank6_block_count2_we + attribute \src "ls180.v:2248.12-2248.43" + wire width 8 \builder_csrbank6_block_count3_r + attribute \src "ls180.v:2247.6-2247.38" + wire \builder_csrbank6_block_count3_re + attribute \src "ls180.v:2250.12-2250.43" + wire width 8 \builder_csrbank6_block_count3_w + attribute \src "ls180.v:2249.6-2249.38" + wire \builder_csrbank6_block_count3_we + attribute \src "ls180.v:2244.12-2244.44" + wire width 8 \builder_csrbank6_block_length0_r + attribute \src "ls180.v:2243.6-2243.39" + wire \builder_csrbank6_block_length0_re + attribute \src "ls180.v:2246.12-2246.44" + wire width 8 \builder_csrbank6_block_length0_w + attribute \src "ls180.v:2245.6-2245.39" + wire \builder_csrbank6_block_length0_we + attribute \src "ls180.v:2240.12-2240.44" + wire width 2 \builder_csrbank6_block_length1_r + attribute \src "ls180.v:2239.6-2239.39" + wire \builder_csrbank6_block_length1_re + attribute \src "ls180.v:2242.12-2242.44" + wire width 2 \builder_csrbank6_block_length1_w + attribute \src "ls180.v:2241.6-2241.39" + wire \builder_csrbank6_block_length1_we + attribute \src "ls180.v:2148.12-2148.44" + wire width 8 \builder_csrbank6_cmd_argument0_r + attribute \src "ls180.v:2147.6-2147.39" + wire \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:2150.12-2150.44" + wire width 8 \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:2149.6-2149.39" + wire \builder_csrbank6_cmd_argument0_we + attribute \src "ls180.v:2144.12-2144.44" + wire width 8 \builder_csrbank6_cmd_argument1_r + attribute \src "ls180.v:2143.6-2143.39" + wire \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:2146.12-2146.44" + wire width 8 \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:2145.6-2145.39" + wire \builder_csrbank6_cmd_argument1_we + attribute \src "ls180.v:2140.12-2140.44" + wire width 8 \builder_csrbank6_cmd_argument2_r + attribute \src "ls180.v:2139.6-2139.39" + wire \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:2142.12-2142.44" + wire width 8 \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:2141.6-2141.39" + wire \builder_csrbank6_cmd_argument2_we + attribute \src "ls180.v:2136.12-2136.44" + wire width 8 \builder_csrbank6_cmd_argument3_r + attribute \src "ls180.v:2135.6-2135.39" + wire \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:2138.12-2138.44" + wire width 8 \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:2137.6-2137.39" + wire \builder_csrbank6_cmd_argument3_we + attribute \src "ls180.v:2164.12-2164.43" + wire width 8 \builder_csrbank6_cmd_command0_r + attribute \src "ls180.v:2163.6-2163.38" + wire \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:2166.12-2166.43" + wire width 8 \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:2165.6-2165.38" + wire \builder_csrbank6_cmd_command0_we + attribute \src "ls180.v:2160.12-2160.43" + wire width 8 \builder_csrbank6_cmd_command1_r + attribute \src "ls180.v:2159.6-2159.38" + wire \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:2162.12-2162.43" + wire width 8 \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:2161.6-2161.38" + wire \builder_csrbank6_cmd_command1_we + attribute \src "ls180.v:2156.12-2156.43" + wire width 8 \builder_csrbank6_cmd_command2_r + attribute \src "ls180.v:2155.6-2155.38" + wire \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:2158.12-2158.43" + wire width 8 \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:2157.6-2157.38" + wire \builder_csrbank6_cmd_command2_we + attribute \src "ls180.v:2152.12-2152.43" + wire width 8 \builder_csrbank6_cmd_command3_r + attribute \src "ls180.v:2151.6-2151.38" + wire \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:2154.12-2154.43" + wire width 8 \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:2153.6-2153.38" + wire \builder_csrbank6_cmd_command3_we + attribute \src "ls180.v:2232.12-2232.40" + wire width 4 \builder_csrbank6_cmd_event_r + attribute \src "ls180.v:2231.6-2231.35" + wire \builder_csrbank6_cmd_event_re + attribute \src "ls180.v:2234.12-2234.40" + wire width 4 \builder_csrbank6_cmd_event_w + attribute \src "ls180.v:2233.6-2233.35" + wire \builder_csrbank6_cmd_event_we + attribute \src "ls180.v:2228.12-2228.44" + wire width 8 \builder_csrbank6_cmd_response0_r + attribute \src "ls180.v:2227.6-2227.39" + wire \builder_csrbank6_cmd_response0_re + attribute \src "ls180.v:2230.12-2230.44" + wire width 8 \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:2229.6-2229.39" + wire \builder_csrbank6_cmd_response0_we + attribute \src "ls180.v:2188.12-2188.45" + wire width 8 \builder_csrbank6_cmd_response10_r + attribute \src "ls180.v:2187.6-2187.40" + wire \builder_csrbank6_cmd_response10_re + attribute \src "ls180.v:2190.12-2190.45" + wire width 8 \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:2189.6-2189.40" + wire \builder_csrbank6_cmd_response10_we + attribute \src "ls180.v:2184.12-2184.45" + wire width 8 \builder_csrbank6_cmd_response11_r + attribute \src "ls180.v:2183.6-2183.40" + wire \builder_csrbank6_cmd_response11_re + attribute \src "ls180.v:2186.12-2186.45" + wire width 8 \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:2185.6-2185.40" + wire \builder_csrbank6_cmd_response11_we + attribute \src "ls180.v:2180.12-2180.45" + wire width 8 \builder_csrbank6_cmd_response12_r + attribute \src "ls180.v:2179.6-2179.40" + wire \builder_csrbank6_cmd_response12_re + attribute \src "ls180.v:2182.12-2182.45" + wire width 8 \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:2181.6-2181.40" + wire \builder_csrbank6_cmd_response12_we + attribute \src "ls180.v:2176.12-2176.45" + wire width 8 \builder_csrbank6_cmd_response13_r + attribute \src "ls180.v:2175.6-2175.40" + wire \builder_csrbank6_cmd_response13_re + attribute \src "ls180.v:2178.12-2178.45" + wire width 8 \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:2177.6-2177.40" + wire \builder_csrbank6_cmd_response13_we + attribute \src "ls180.v:2172.12-2172.45" + wire width 8 \builder_csrbank6_cmd_response14_r + attribute \src "ls180.v:2171.6-2171.40" + wire \builder_csrbank6_cmd_response14_re + attribute \src "ls180.v:2174.12-2174.45" + wire width 8 \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:2173.6-2173.40" + wire \builder_csrbank6_cmd_response14_we + attribute \src "ls180.v:2168.12-2168.45" + wire width 8 \builder_csrbank6_cmd_response15_r + attribute \src "ls180.v:2167.6-2167.40" + wire \builder_csrbank6_cmd_response15_re + attribute \src "ls180.v:2170.12-2170.45" + wire width 8 \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:2169.6-2169.40" + wire \builder_csrbank6_cmd_response15_we + attribute \src "ls180.v:2224.12-2224.44" + wire width 8 \builder_csrbank6_cmd_response1_r + attribute \src "ls180.v:2223.6-2223.39" + wire \builder_csrbank6_cmd_response1_re + attribute \src "ls180.v:2226.12-2226.44" + wire width 8 \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:2225.6-2225.39" + wire \builder_csrbank6_cmd_response1_we + attribute \src "ls180.v:2220.12-2220.44" + wire width 8 \builder_csrbank6_cmd_response2_r + attribute \src "ls180.v:2219.6-2219.39" + wire \builder_csrbank6_cmd_response2_re + attribute \src "ls180.v:2222.12-2222.44" + wire width 8 \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:2221.6-2221.39" + wire \builder_csrbank6_cmd_response2_we + attribute \src "ls180.v:2216.12-2216.44" + wire width 8 \builder_csrbank6_cmd_response3_r + attribute \src "ls180.v:2215.6-2215.39" + wire \builder_csrbank6_cmd_response3_re + attribute \src "ls180.v:2218.12-2218.44" + wire width 8 \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:2217.6-2217.39" + wire \builder_csrbank6_cmd_response3_we + attribute \src "ls180.v:2212.12-2212.44" + wire width 8 \builder_csrbank6_cmd_response4_r + attribute \src "ls180.v:2211.6-2211.39" + wire \builder_csrbank6_cmd_response4_re + attribute \src "ls180.v:2214.12-2214.44" + wire width 8 \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:2213.6-2213.39" + wire \builder_csrbank6_cmd_response4_we + attribute \src "ls180.v:2208.12-2208.44" + wire width 8 \builder_csrbank6_cmd_response5_r + attribute \src "ls180.v:2207.6-2207.39" + wire \builder_csrbank6_cmd_response5_re + attribute \src "ls180.v:2210.12-2210.44" + wire width 8 \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:2209.6-2209.39" + wire \builder_csrbank6_cmd_response5_we + attribute \src "ls180.v:2204.12-2204.44" + wire width 8 \builder_csrbank6_cmd_response6_r + attribute \src "ls180.v:2203.6-2203.39" + wire \builder_csrbank6_cmd_response6_re + attribute \src "ls180.v:2206.12-2206.44" + wire width 8 \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:2205.6-2205.39" + wire \builder_csrbank6_cmd_response6_we + attribute \src "ls180.v:2200.12-2200.44" + wire width 8 \builder_csrbank6_cmd_response7_r + attribute \src "ls180.v:2199.6-2199.39" + wire \builder_csrbank6_cmd_response7_re + attribute \src "ls180.v:2202.12-2202.44" + wire width 8 \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:2201.6-2201.39" + wire \builder_csrbank6_cmd_response7_we + attribute \src "ls180.v:2196.12-2196.44" + wire width 8 \builder_csrbank6_cmd_response8_r + attribute \src "ls180.v:2195.6-2195.39" + wire \builder_csrbank6_cmd_response8_re + attribute \src "ls180.v:2198.12-2198.44" + wire width 8 \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:2197.6-2197.39" + wire \builder_csrbank6_cmd_response8_we + attribute \src "ls180.v:2192.12-2192.44" + wire width 8 \builder_csrbank6_cmd_response9_r + attribute \src "ls180.v:2191.6-2191.39" + wire \builder_csrbank6_cmd_response9_re + attribute \src "ls180.v:2194.12-2194.44" + wire width 8 \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:2193.6-2193.39" + wire \builder_csrbank6_cmd_response9_we + attribute \src "ls180.v:2236.12-2236.41" + wire width 4 \builder_csrbank6_data_event_r + attribute \src "ls180.v:2235.6-2235.36" + wire \builder_csrbank6_data_event_re + attribute \src "ls180.v:2238.12-2238.41" + wire width 4 \builder_csrbank6_data_event_w + attribute \src "ls180.v:2237.6-2237.36" + wire \builder_csrbank6_data_event_we + attribute \src "ls180.v:2263.6-2263.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2297.12-2297.40" + wire width 8 \builder_csrbank7_dma_base0_r + attribute \src "ls180.v:2296.6-2296.35" + wire \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:2299.12-2299.40" + wire width 8 \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:2298.6-2298.35" + wire \builder_csrbank7_dma_base0_we + attribute \src "ls180.v:2293.12-2293.40" + wire width 8 \builder_csrbank7_dma_base1_r + attribute \src "ls180.v:2292.6-2292.35" + wire \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:2295.12-2295.40" + wire width 8 \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:2294.6-2294.35" + wire \builder_csrbank7_dma_base1_we + attribute \src "ls180.v:2289.12-2289.40" + wire width 8 \builder_csrbank7_dma_base2_r + attribute \src "ls180.v:2288.6-2288.35" + wire \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:2291.12-2291.40" + wire width 8 \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:2290.6-2290.35" + wire \builder_csrbank7_dma_base2_we + attribute \src "ls180.v:2285.12-2285.40" + wire width 8 \builder_csrbank7_dma_base3_r + attribute \src "ls180.v:2284.6-2284.35" + wire \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:2287.12-2287.40" + wire width 8 \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:2286.6-2286.35" + wire \builder_csrbank7_dma_base3_we + attribute \src "ls180.v:2281.12-2281.40" + wire width 8 \builder_csrbank7_dma_base4_r + attribute \src "ls180.v:2280.6-2280.35" + wire \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:2283.12-2283.40" + wire width 8 \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:2282.6-2282.35" + wire \builder_csrbank7_dma_base4_we + attribute \src "ls180.v:2277.12-2277.40" + wire width 8 \builder_csrbank7_dma_base5_r + attribute \src "ls180.v:2276.6-2276.35" + wire \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:2279.12-2279.40" + wire width 8 \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:2278.6-2278.35" + wire \builder_csrbank7_dma_base5_we + attribute \src "ls180.v:2273.12-2273.40" + wire width 8 \builder_csrbank7_dma_base6_r + attribute \src "ls180.v:2272.6-2272.35" + wire \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:2275.12-2275.40" + wire width 8 \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:2274.6-2274.35" + wire \builder_csrbank7_dma_base6_we + attribute \src "ls180.v:2269.12-2269.40" + wire width 8 \builder_csrbank7_dma_base7_r + attribute \src "ls180.v:2268.6-2268.35" + wire \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:2271.12-2271.40" + wire width 8 \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:2270.6-2270.35" + wire \builder_csrbank7_dma_base7_we + attribute \src "ls180.v:2321.6-2321.33" + wire \builder_csrbank7_dma_done_r + attribute \src "ls180.v:2320.6-2320.34" + wire \builder_csrbank7_dma_done_re + attribute \src "ls180.v:2323.6-2323.33" + wire \builder_csrbank7_dma_done_w + attribute \src "ls180.v:2322.6-2322.34" + wire \builder_csrbank7_dma_done_we + attribute \src "ls180.v:2317.6-2317.36" + wire \builder_csrbank7_dma_enable0_r + attribute \src "ls180.v:2316.6-2316.37" + wire \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:2319.6-2319.36" + wire \builder_csrbank7_dma_enable0_w + attribute \src "ls180.v:2318.6-2318.37" + wire \builder_csrbank7_dma_enable0_we + attribute \src "ls180.v:2313.12-2313.42" + wire width 8 \builder_csrbank7_dma_length0_r + attribute \src "ls180.v:2312.6-2312.37" + wire \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:2315.12-2315.42" + wire width 8 \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:2314.6-2314.37" + wire \builder_csrbank7_dma_length0_we + attribute \src "ls180.v:2309.12-2309.42" + wire width 8 \builder_csrbank7_dma_length1_r + attribute \src "ls180.v:2308.6-2308.37" + wire \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:2311.12-2311.42" + wire width 8 \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:2310.6-2310.37" + wire \builder_csrbank7_dma_length1_we + attribute \src "ls180.v:2305.12-2305.42" + wire width 8 \builder_csrbank7_dma_length2_r + attribute \src "ls180.v:2304.6-2304.37" + wire \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:2307.12-2307.42" + wire width 8 \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:2306.6-2306.37" + wire \builder_csrbank7_dma_length2_we + attribute \src "ls180.v:2301.12-2301.42" + wire width 8 \builder_csrbank7_dma_length3_r + attribute \src "ls180.v:2300.6-2300.37" + wire \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:2303.12-2303.42" + wire width 8 \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:2302.6-2302.37" + wire \builder_csrbank7_dma_length3_we + attribute \src "ls180.v:2325.6-2325.34" + wire \builder_csrbank7_dma_loop0_r + attribute \src "ls180.v:2324.6-2324.35" + wire \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:2327.6-2327.34" + wire \builder_csrbank7_dma_loop0_w + attribute \src "ls180.v:2326.6-2326.35" + wire \builder_csrbank7_dma_loop0_we + attribute \src "ls180.v:2341.12-2341.42" + wire width 8 \builder_csrbank7_dma_offset0_r + attribute \src "ls180.v:2340.6-2340.37" + wire \builder_csrbank7_dma_offset0_re + attribute \src "ls180.v:2343.12-2343.42" + wire width 8 \builder_csrbank7_dma_offset0_w + attribute \src "ls180.v:2342.6-2342.37" + wire \builder_csrbank7_dma_offset0_we + attribute \src "ls180.v:2337.12-2337.42" + wire width 8 \builder_csrbank7_dma_offset1_r + attribute \src "ls180.v:2336.6-2336.37" + wire \builder_csrbank7_dma_offset1_re + attribute \src "ls180.v:2339.12-2339.42" + wire width 8 \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:2338.6-2338.37" + wire \builder_csrbank7_dma_offset1_we + attribute \src "ls180.v:2333.12-2333.42" + wire width 8 \builder_csrbank7_dma_offset2_r + attribute \src "ls180.v:2332.6-2332.37" + wire \builder_csrbank7_dma_offset2_re + attribute \src "ls180.v:2335.12-2335.42" + wire width 8 \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:2334.6-2334.37" + wire \builder_csrbank7_dma_offset2_we + attribute \src "ls180.v:2329.12-2329.42" + wire width 8 \builder_csrbank7_dma_offset3_r + attribute \src "ls180.v:2328.6-2328.37" + wire \builder_csrbank7_dma_offset3_re + attribute \src "ls180.v:2331.12-2331.42" + wire width 8 \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:2330.6-2330.37" + wire \builder_csrbank7_dma_offset3_we + attribute \src "ls180.v:2344.6-2344.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2350.6-2350.36" + wire \builder_csrbank8_card_detect_r + attribute \src "ls180.v:2349.6-2349.37" + wire \builder_csrbank8_card_detect_re + attribute \src "ls180.v:2352.6-2352.36" + wire \builder_csrbank8_card_detect_w + attribute \src "ls180.v:2351.6-2351.37" + wire \builder_csrbank8_card_detect_we + attribute \src "ls180.v:2358.12-2358.47" + wire width 8 \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:2357.6-2357.42" + wire \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:2360.12-2360.47" + wire width 8 \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:2359.6-2359.42" + wire \builder_csrbank8_clocker_divider0_we + attribute \src "ls180.v:2354.6-2354.41" + wire \builder_csrbank8_clocker_divider1_r + attribute \src "ls180.v:2353.6-2353.42" + wire \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:2356.6-2356.41" + wire \builder_csrbank8_clocker_divider1_w + attribute \src "ls180.v:2355.6-2355.42" + wire \builder_csrbank8_clocker_divider1_we + attribute \src "ls180.v:2361.6-2361.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2367.12-2367.44" + wire width 4 \builder_csrbank9_dfii_control0_r + attribute \src "ls180.v:2366.6-2366.39" + wire \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:2369.12-2369.44" + wire width 4 \builder_csrbank9_dfii_control0_w + attribute \src "ls180.v:2368.6-2368.39" + wire \builder_csrbank9_dfii_control0_we + attribute \src "ls180.v:2379.12-2379.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_r + attribute \src "ls180.v:2378.6-2378.43" + wire \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:2381.12-2381.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:2380.6-2380.43" + wire \builder_csrbank9_dfii_pi0_address0_we + attribute \src "ls180.v:2375.12-2375.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_r + attribute \src "ls180.v:2374.6-2374.43" + wire \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:2377.12-2377.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_w + attribute \src "ls180.v:2376.6-2376.43" + wire \builder_csrbank9_dfii_pi0_address1_we + attribute \src "ls180.v:2383.12-2383.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r + attribute \src "ls180.v:2382.6-2382.44" + wire \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:2385.12-2385.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w + attribute \src "ls180.v:2384.6-2384.44" + wire \builder_csrbank9_dfii_pi0_baddress0_we + attribute \src "ls180.v:2371.12-2371.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_r + attribute \src "ls180.v:2370.6-2370.43" + wire \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:2373.12-2373.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_w + attribute \src "ls180.v:2372.6-2372.43" + wire \builder_csrbank9_dfii_pi0_command0_we + attribute \src "ls180.v:2399.12-2399.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r + attribute \src "ls180.v:2398.6-2398.42" + wire \builder_csrbank9_dfii_pi0_rddata0_re + attribute \src "ls180.v:2401.12-2401.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w + attribute \src "ls180.v:2400.6-2400.42" + wire \builder_csrbank9_dfii_pi0_rddata0_we + attribute \src "ls180.v:2395.12-2395.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r + attribute \src "ls180.v:2394.6-2394.42" + wire \builder_csrbank9_dfii_pi0_rddata1_re + attribute \src "ls180.v:2397.12-2397.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:2396.6-2396.42" + wire \builder_csrbank9_dfii_pi0_rddata1_we + attribute \src "ls180.v:2391.12-2391.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2390.6-2390.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2393.12-2393.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2392.6-2392.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2387.12-2387.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2386.6-2386.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2389.12-2389.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2388.6-2388.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2402.6-2402.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:1899.6-1899.18" + wire \builder_done + attribute \src "ls180.v:1897.5-1897.18" + wire \builder_error + attribute \src "ls180.v:1894.11-1894.24" + wire width 3 \builder_grant + attribute \src "ls180.v:1901.13-1901.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:1904.11-1904.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:1903.12-1903.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:1902.6-1902.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2403.13-2403.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2406.11-2406.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2405.12-2405.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2404.6-2404.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2436.13-2436.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2439.11-2439.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2438.12-2438.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2437.6-2437.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2477.13-2477.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2480.11-2480.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2479.12-2479.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2478.6-2478.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2542.13-2542.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2545.11-2545.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2544.12-2544.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2543.6-2543.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:2567.13-2567.45" + wire width 14 \builder_interface14_bank_bus_adr + attribute \src "ls180.v:2570.11-2570.45" + wire width 8 \builder_interface14_bank_bus_dat_r + attribute \src "ls180.v:2569.12-2569.46" + wire width 8 \builder_interface14_bank_bus_dat_w + attribute \src "ls180.v:2568.6-2568.37" + wire \builder_interface14_bank_bus_we + attribute \src "ls180.v:1942.13-1942.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:1945.11-1945.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:1944.12-1944.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:1943.6-1943.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:1971.13-1971.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:1974.11-1974.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:1973.12-1973.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:1972.6-1972.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:1984.13-1984.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:1987.11-1987.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:1986.12-1986.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:1985.6-1985.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2025.13-2025.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2028.11-2028.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2027.12-2027.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2026.6-2026.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2066.13-2066.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2069.11-2069.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2068.12-2068.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2067.6-2067.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2131.13-2131.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2134.11-2134.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2133.12-2133.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2132.6-2132.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2264.13-2264.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2267.11-2267.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2266.12-2266.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2265.6-2265.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2345.13-2345.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2348.11-2348.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2347.12-2347.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2346.6-2346.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2362.13-2362.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2365.11-2365.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2364.12-2364.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2363.6-2363.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1867.12-1867.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2596.12-2596.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2597.5-2597.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1870.12-1870.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1869.11-1869.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2594.11-2594.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2595.5-2595.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1868.5-1868.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2598.5-2598.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2599.5-2599.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1877.5-1877.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1871.13-1871.45" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1880.12-1880.44" + wire width 2 \builder_libresocsim_wishbone_bte + attribute \src "ls180.v:1879.12-1879.44" + wire width 3 \builder_libresocsim_wishbone_cti + attribute \src "ls180.v:1875.6-1875.38" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1873.12-1873.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1872.13-1872.47" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1881.5-1881.37" + wire \builder_libresocsim_wishbone_err + attribute \src "ls180.v:1874.12-1874.44" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1876.6-1876.38" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1878.6-1878.37" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1770.5-1770.20" + wire \builder_locked0 + attribute \src "ls180.v:1771.5-1771.20" + wire \builder_locked1 + attribute \src "ls180.v:1772.5-1772.20" + wire \builder_locked2 + attribute \src "ls180.v:1773.5-1773.20" + wire \builder_locked3 + attribute \src "ls180.v:1757.11-1757.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1756.11-1756.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2703.32-2703.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2704.32-2704.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2723.32-2723.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2724.32-2724.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2725.32-2725.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2726.32-2726.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2727.32-2727.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2728.32-2728.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2729.32-2729.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2730.32-2730.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2731.32-2731.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2732.32-2732.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2733.32-2733.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2734.32-2734.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2735.32-2735.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2736.32-2736.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2705.32-2705.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2706.32-2706.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2707.32-2707.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2708.32-2708.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2709.32-2709.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2710.32-2710.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2711.32-2711.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2712.32-2712.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2713.32-2713.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2714.32-2714.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2715.32-2715.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2716.32-2716.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2717.32-2717.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2718.32-2718.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2719.32-2719.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2720.32-2720.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2721.32-2721.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2722.32-2722.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1775.5-1775.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1776.5-1776.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1777.5-1777.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1778.5-1778.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1774.5-1774.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2593.11-2593.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1747.11-1747.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1746.11-1746.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:1893.12-1893.27" + wire width 5 \builder_request + attribute \src "ls180.v:1760.6-1760.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1759.6-1759.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1758.6-1758.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1763.6-1763.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1762.6-1762.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1761.6-1761.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1766.6-1766.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1765.6-1765.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1764.6-1764.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1769.6-1769.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1768.6-1768.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1767.6-1767.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1856.11-1856.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1855.11-1855.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1824.5-1824.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1823.5-1823.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1836.11-1836.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1835.11-1835.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1860.5-1860.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1859.5-1859.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1864.11-1864.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1863.11-1863.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1812.11-1812.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1811.11-1811.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1800.11-1800.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1799.11-1799.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1796.11-1796.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1795.11-1795.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1808.5-1808.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1807.5-1807.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1816.11-1816.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1815.11-1815.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1792.5-1792.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1791.5-1791.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:1888.5-1888.23" + wire \builder_shared_ack + attribute \src "ls180.v:1882.13-1882.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:1891.12-1891.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:1890.12-1890.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1886.6-1886.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1884.12-1884.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1883.13-1883.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:1892.6-1892.24" + wire \builder_shared_err + attribute \src "ls180.v:1885.12-1885.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:1887.6-1887.24" + wire \builder_shared_stb + attribute \src "ls180.v:1889.6-1889.23" + wire \builder_shared_we + attribute \src "ls180.v:1895.11-1895.28" + wire width 5 \builder_slave_sel + attribute \src "ls180.v:1896.11-1896.30" + wire width 5 \builder_slave_sel_r + attribute \src "ls180.v:1784.11-1784.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1783.11-1783.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1788.11-1788.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1787.11-1787.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2592.11-2592.24" + wire width 2 \builder_state + attribute \src "ls180.v:2645.5-2645.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2646.5-2646.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2638.11-2638.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2639.12-2639.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2640.5-2640.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2641.5-2641.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2642.5-2642.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2643.5-2643.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2644.5-2644.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:1898.6-1898.18" + wire \builder_wait + attribute \src "ls180.v:21.20-21.24" + wire width 3 output 17 \eint + attribute \src "ls180.v:140.11-140.17" + wire width 3 \eint_1 + attribute \src "ls180.v:5.21-5.27" + wire width 16 output 1 \gpio_i + attribute \src "ls180.v:6.21-6.27" + wire width 16 output 2 \gpio_o + attribute \src "ls180.v:7.21-7.28" + wire width 16 output 3 \gpio_oe + attribute \src "ls180.v:39.14-39.21" + wire output 35 \i2c_scl + attribute \src "ls180.v:40.14-40.23" + wire output 36 \i2c_sda_i + attribute \src "ls180.v:41.14-41.23" + wire output 37 \i2c_sda_o + attribute \src "ls180.v:42.14-42.24" + wire output 38 \i2c_sda_oe + attribute \src "ls180.v:49.13-49.21" + wire input 45 \jtag_tck + attribute \src "ls180.v:50.13-50.21" + wire input 46 \jtag_tdi + attribute \src "ls180.v:51.14-51.22" + wire output 47 \jtag_tdo + attribute \src "ls180.v:48.13-48.21" + wire input 44 \jtag_tms + attribute \src "ls180.v:838.6-838.18" + wire \main_ack_cmd + attribute \src "ls180.v:840.6-840.20" + wire \main_ack_rdata + attribute \src "ls180.v:839.6-839.20" + wire \main_ack_wdata + attribute \src "ls180.v:836.5-836.22" + wire \main_cmd_consumed + attribute \src "ls180.v:833.5-833.27" + wire \main_converter_counter + attribute \src "ls180.v:1781.5-1781.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1782.5-1782.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:835.12-835.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:834.6-834.26" + wire \main_converter_reset + attribute \src "ls180.v:832.5-832.24" + wire \main_converter_skip + attribute \src "ls180.v:262.6-262.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:253.13-253.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:254.12-254.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:255.6-255.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:259.6-259.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:256.6-256.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:260.6-260.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:257.6-257.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:267.12-267.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:266.6-266.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:268.5-268.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:261.6-261.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:258.6-258.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:263.13-263.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:264.6-264.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:265.12-265.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:1067.12-1067.22" + wire width 36 \main_dummy + attribute \src "ls180.v:984.5-984.20" + wire \main_gpio_oe_re + attribute \src "ls180.v:983.12-983.32" + wire width 16 \main_gpio_oe_storage + attribute \src "ls180.v:988.5-988.21" + wire \main_gpio_out_re + attribute \src "ls180.v:987.12-987.33" + wire width 16 \main_gpio_out_storage + attribute \src "ls180.v:989.13-989.29" + wire width 16 \main_gpio_pads_i + attribute \src "ls180.v:990.13-990.29" + wire width 16 \main_gpio_pads_o + attribute \src "ls180.v:991.13-991.30" + wire width 16 \main_gpio_pads_oe + attribute \src "ls180.v:985.12-985.28" + wire width 16 \main_gpio_status + attribute \src "ls180.v:986.6-986.18" + wire \main_gpio_we + attribute \src "ls180.v:1089.6-1089.17" + wire \main_i2c_oe + attribute \src "ls180.v:1092.5-1092.16" + wire \main_i2c_re + attribute \src "ls180.v:1088.6-1088.18" + wire \main_i2c_scl + attribute \src "ls180.v:1090.6-1090.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1093.6-1093.19" + wire \main_i2c_sda1 + attribute \src "ls180.v:1094.6-1094.21" + wire \main_i2c_status + attribute \src "ls180.v:1091.11-1091.27" + wire width 3 \main_i2c_storage + attribute \src "ls180.v:1095.6-1095.17" + wire \main_i2c_we + attribute \src "ls180.v:252.5-252.17" + wire \main_int_rst + attribute \src "ls180.v:1555.6-1555.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1549.13-1549.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1558.11-1558.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1557.11-1557.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1553.6-1553.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1551.13-1551.38" + wire width 32 \main_interface0_bus_dat_r + attribute \src "ls180.v:1550.13-1550.38" + wire width 32 \main_interface0_bus_dat_w + attribute \src "ls180.v:1559.6-1559.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1552.12-1552.35" + wire width 4 \main_interface0_bus_sel + attribute \src "ls180.v:1554.6-1554.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1556.6-1556.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:1646.6-1646.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1640.12-1640.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1649.11-1649.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1648.11-1648.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1644.5-1644.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1642.13-1642.38" + wire width 32 \main_interface1_bus_dat_r + attribute \src "ls180.v:1641.12-1641.37" + wire width 32 \main_interface1_bus_dat_w + attribute \src "ls180.v:1650.6-1650.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1643.11-1643.34" + wire width 4 \main_interface1_bus_sel + attribute \src "ls180.v:1645.5-1645.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1647.5-1647.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:218.12-218.32" + wire width 7 \main_libresocsim_adr + attribute \src "ls180.v:62.6-62.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:63.12-63.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:59.13-59.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:60.6-60.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:174.5-174.40" + wire \main_libresocsim_converter0_counter + attribute \src "ls180.v:1736.5-1736.62" + wire \main_libresocsim_converter0_counter_converter0_next_value + attribute \src "ls180.v:1737.5-1737.65" + wire \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:176.12-176.45" + wire width 64 \main_libresocsim_converter0_dat_r + attribute \src "ls180.v:175.6-175.39" + wire \main_libresocsim_converter0_reset + attribute \src "ls180.v:173.5-173.37" + wire \main_libresocsim_converter0_skip + attribute \src "ls180.v:189.5-189.40" + wire \main_libresocsim_converter1_counter + attribute \src "ls180.v:1740.5-1740.62" + wire \main_libresocsim_converter1_counter_converter1_next_value + attribute \src "ls180.v:1741.5-1741.65" + wire \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:191.12-191.45" + wire width 64 \main_libresocsim_converter1_dat_r + attribute \src "ls180.v:190.6-190.39" + wire \main_libresocsim_converter1_reset + attribute \src "ls180.v:188.5-188.37" + wire \main_libresocsim_converter1_skip + attribute \src "ls180.v:204.5-204.40" + wire \main_libresocsim_converter2_counter + attribute \src "ls180.v:1744.5-1744.62" + wire \main_libresocsim_converter2_counter_converter2_next_value + attribute \src "ls180.v:1745.5-1745.65" + wire \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:206.12-206.45" + wire width 64 \main_libresocsim_converter2_dat_r + attribute \src "ls180.v:205.6-205.39" + wire \main_libresocsim_converter2_reset + attribute \src "ls180.v:203.5-203.37" + wire \main_libresocsim_converter2_skip + attribute \src "ls180.v:219.13-219.35" + wire width 32 \main_libresocsim_dat_r + attribute \src "ls180.v:221.13-221.35" + wire width 32 \main_libresocsim_dat_w + attribute \src "ls180.v:227.5-227.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:226.5-226.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:243.6-243.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:242.6-242.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:245.6-245.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:244.6-244.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:247.5-247.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:239.6-239.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:238.6-238.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:241.6-241.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:240.6-240.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:246.5-246.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:168.6-168.57" + wire \main_libresocsim_interface0_converted_interface_ack + attribute \src "ls180.v:162.12-162.63" + wire width 30 \main_libresocsim_interface0_converted_interface_adr + attribute \src "ls180.v:171.11-171.62" + wire width 2 \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:170.11-170.62" + wire width 3 \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:166.5-166.56" + wire \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:164.13-164.66" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_r + attribute \src "ls180.v:163.12-163.65" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:172.6-172.57" + wire \main_libresocsim_interface0_converted_interface_err + attribute \src "ls180.v:165.11-165.62" + wire width 4 \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:167.5-167.56" + wire \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:169.5-169.55" + wire \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:183.6-183.57" + wire \main_libresocsim_interface1_converted_interface_ack + attribute \src "ls180.v:177.12-177.63" + wire width 30 \main_libresocsim_interface1_converted_interface_adr + attribute \src "ls180.v:186.11-186.62" + wire width 2 \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:185.11-185.62" + wire width 3 \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:181.5-181.56" + wire \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:179.13-179.66" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_r + attribute \src "ls180.v:178.12-178.65" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:187.6-187.57" + wire \main_libresocsim_interface1_converted_interface_err + attribute \src "ls180.v:180.11-180.62" + wire width 4 \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:182.5-182.56" + wire \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:184.5-184.55" + wire \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:198.6-198.57" + wire \main_libresocsim_interface2_converted_interface_ack + attribute \src "ls180.v:192.12-192.63" + wire width 30 \main_libresocsim_interface2_converted_interface_adr + attribute \src "ls180.v:201.11-201.62" + wire width 2 \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:200.11-200.62" + wire width 3 \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:196.5-196.56" + wire \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:194.13-194.66" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_r + attribute \src "ls180.v:193.12-193.65" + wire width 32 \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:202.6-202.57" + wire \main_libresocsim_interface2_converted_interface_err + attribute \src "ls180.v:195.11-195.62" + wire width 4 \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:197.5-197.56" + wire \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:199.5-199.55" + wire \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:232.6-232.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:123.6-123.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:124.6-124.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:125.13-125.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:127.12-127.45" + wire width 3 \main_libresocsim_libresoc_clk_sel + attribute \src "ls180.v:129.12-129.66" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i + attribute \src "ls180.v:130.13-130.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o + attribute \src "ls180.v:131.13-131.68" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe + attribute \src "ls180.v:158.6-158.61" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + attribute \src "ls180.v:159.5-159.62" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + attribute \src "ls180.v:160.6-160.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + attribute \src "ls180.v:161.6-161.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + attribute \src "ls180.v:136.6-136.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + attribute \src "ls180.v:137.5-137.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + attribute \src "ls180.v:138.6-138.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + attribute \src "ls180.v:139.6-139.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + attribute \src "ls180.v:146.13-146.68" + wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a + attribute \src "ls180.v:155.12-155.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba + attribute \src "ls180.v:152.6-152.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + attribute \src "ls180.v:154.6-154.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + attribute \src "ls180.v:153.6-153.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + attribute \src "ls180.v:156.12-156.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm + attribute \src "ls180.v:147.12-147.70" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i + attribute \src "ls180.v:148.13-148.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o + attribute \src "ls180.v:149.6-149.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + attribute \src "ls180.v:151.6-151.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + attribute \src "ls180.v:150.6-150.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + attribute \src "ls180.v:142.6-142.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + attribute \src "ls180.v:144.6-144.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + attribute \src "ls180.v:145.5-145.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + attribute \src "ls180.v:143.6-143.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + attribute \src "ls180.v:132.6-132.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + attribute \src "ls180.v:134.6-134.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + attribute \src "ls180.v:135.5-135.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + attribute \src "ls180.v:133.6-133.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + attribute \src "ls180.v:72.5-72.39" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:66.13-66.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.12-75.46" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.12-74.46" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:70.6-70.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:68.13-68.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:67.13-67.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:76.5-76.39" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:69.12-69.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:71.6-71.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:73.6-73.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:83.5-83.39" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:77.13-77.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:86.12-86.46" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.12-85.46" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:79.13-79.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:78.13-78.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:87.5-87.39" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:80.12-80.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:82.6-82.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:84.6-84.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:65.12-65.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:119.6-119.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:121.6-121.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:122.6-122.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:120.6-120.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:116.5-116.42" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:110.13-110.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:114.6-114.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:112.13-112.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:111.13-111.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:118.5-118.42" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:113.12-113.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:115.6-115.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:117.6-117.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:126.6-126.40" + wire \main_libresocsim_libresoc_pll_18_o + attribute \src "ls180.v:128.6-128.41" + wire \main_libresocsim_libresoc_pll_lck_o + attribute \src "ls180.v:64.6-64.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:94.6-94.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:88.13-88.51" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:97.12-97.50" + wire width 2 \main_libresocsim_libresoc_xics_icp_bte + attribute \src "ls180.v:96.12-96.50" + wire width 3 \main_libresocsim_libresoc_xics_icp_cti + attribute \src "ls180.v:92.6-92.44" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:90.13-90.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:89.13-89.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:98.6-98.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:91.12-91.50" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:93.6-93.44" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:95.6-95.43" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:105.6-105.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:99.13-99.51" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:108.12-108.50" + wire width 2 \main_libresocsim_libresoc_xics_ics_bte + attribute \src "ls180.v:107.12-107.50" + wire width 3 \main_libresocsim_libresoc_xics_ics_cti + attribute \src "ls180.v:103.6-103.44" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:101.13-101.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:100.13-100.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:109.6-109.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:102.12-102.50" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:104.6-104.44" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:106.6-106.43" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:223.5-223.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:222.12-222.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:213.5-213.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:207.13-207.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:216.12-216.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:215.12-215.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:211.6-211.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:209.13-209.43" + wire width 32 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:208.13-208.43" + wire width 32 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:217.5-217.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:210.12-210.40" + wire width 4 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:212.6-212.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:214.6-214.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:225.5-225.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:224.12-224.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:61.6-61.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:56.5-56.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:55.5-55.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:58.5-58.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:57.12-57.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:229.5-229.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:228.5-228.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:248.12-248.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:230.12-230.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:231.6-231.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:220.11-220.30" + wire width 4 \main_libresocsim_we + attribute \src "ls180.v:236.5-236.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:237.5-237.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:234.5-234.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:233.6-233.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:235.6-235.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:830.6-830.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:824.12-824.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:828.5-828.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:826.13-826.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:825.12-825.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:827.11-827.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:829.5-829.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:831.5-831.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:1066.13-1066.20" + wire width 36 \main_nc + attribute \src "ls180.v:803.6-803.24" + wire \main_port_cmd_last + attribute \src "ls180.v:805.13-805.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:804.6-804.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:802.6-802.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:801.6-801.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:800.6-800.21" + wire \main_port_flush + attribute \src "ls180.v:812.13-812.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:811.6-811.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:810.6-810.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:808.13-808.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:809.12-809.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:807.6-807.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:806.6-806.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1071.12-1071.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:1068.6-1068.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1073.5-1073.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1072.5-1072.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1070.13-1070.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1077.5-1077.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1076.12-1076.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:1069.13-1069.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1075.5-1075.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1074.12-1074.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1081.12-1081.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1078.6-1078.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1083.5-1083.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1082.5-1082.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1080.13-1080.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1087.5-1087.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1086.12-1086.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1079.13-1079.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1085.5-1085.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1084.12-1084.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:269.11-269.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:1609.11-1609.43" + wire width 2 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1610.6-1610.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1600.6-1600.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1601.6-1601.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1602.12-1602.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1599.6-1599.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1598.6-1598.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1605.5-1605.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1606.5-1606.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1607.12-1607.58" + wire width 32 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1608.11-1608.70" + wire width 3 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1604.6-1604.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1603.6-1603.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1611.5-1611.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1584.11-1584.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1589.6-1589.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1593.6-1593.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1594.6-1594.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1592.12-1592.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1596.6-1596.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1597.6-1597.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1595.12-1595.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1581.11-1581.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1583.11-1583.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1590.12-1590.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1591.12-1591.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1582.5-1582.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1567.6-1567.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1568.6-1568.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1569.12-1569.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1566.6-1566.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1565.6-1565.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1572.6-1572.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1573.6-1573.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1574.12-1574.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1571.6-1571.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1570.6-1570.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1579.12-1579.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1580.12-1580.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1577.6-1577.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1578.6-1578.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1575.6-1575.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1576.6-1576.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1585.11-1585.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1586.12-1586.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1588.12-1588.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1587.6-1587.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1562.6-1562.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1563.6-1563.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1619.12-1619.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1564.12-1564.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1620.12-1620.52" + wire width 32 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1561.6-1561.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1618.6-1618.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1560.6-1560.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1617.5-1617.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1614.6-1614.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1615.6-1615.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1616.13-1616.56" + wire width 32 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1613.6-1613.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1612.6-1612.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1636.13-1636.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1627.5-1627.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1626.12-1626.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1631.5-1631.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1630.5-1630.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1638.13-1638.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1629.5-1629.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1628.12-1628.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1635.5-1635.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1634.5-1634.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1637.12-1637.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1857.12-1857.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1858.5-1858.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1639.6-1639.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1623.6-1623.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1624.6-1624.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1625.13-1625.65" + wire width 32 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1622.5-1622.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1621.6-1621.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1632.5-1632.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1633.6-1633.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1401.5-1401.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1400.12-1400.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1399.5-1399.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1398.11-1398.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1385.5-1385.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1384.12-1384.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1387.5-1387.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1386.12-1386.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1540.11-1540.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1841.11-1841.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1842.5-1842.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1541.5-1541.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1837.5-1837.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1838.5-1838.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1542.5-1542.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1845.5-1845.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1846.5-1846.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1394.12-1394.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1395.6-1395.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1392.13-1392.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1853.13-1853.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1854.5-1854.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1393.6-1393.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1389.6-1389.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1388.6-1388.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1391.5-1391.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1390.6-1390.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1543.5-1543.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1847.5-1847.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1848.5-1848.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1539.12-1539.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1501.11-1501.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1507.5-1507.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1506.12-1506.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1502.12-1502.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1503.13-1503.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1504.13-1504.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1508.6-1508.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1505.12-1505.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1514.5-1514.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1513.12-1513.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1509.12-1509.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1510.13-1510.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1511.13-1511.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1515.6-1515.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1512.12-1512.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1521.5-1521.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1520.12-1520.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1516.12-1516.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1517.13-1517.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1518.13-1518.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1522.6-1522.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1519.12-1519.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1528.5-1528.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1527.12-1527.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1523.12-1523.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1524.13-1524.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1525.13-1525.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1529.6-1529.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1526.12-1526.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1530.12-1530.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1531.12-1531.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1532.12-1532.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1533.12-1533.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1535.12-1535.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1536.12-1536.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1537.12-1537.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1538.12-1538.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1492.5-1492.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1493.5-1493.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1494.11-1494.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1491.5-1491.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1490.5-1490.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1497.5-1497.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1498.6-1498.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1499.12-1499.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1496.6-1496.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1495.5-1495.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1500.11-1500.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1534.5-1534.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1457.11-1457.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1833.11-1833.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1834.5-1834.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1463.6-1463.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1462.12-1462.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1458.12-1458.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1459.13-1459.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1460.13-1460.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1464.6-1464.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1461.12-1461.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1470.6-1470.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1469.12-1469.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1465.12-1465.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1466.13-1466.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1467.13-1467.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1471.6-1471.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1468.12-1468.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1477.6-1477.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1476.12-1476.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1472.12-1472.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1473.13-1473.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1474.13-1474.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1478.6-1478.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1475.12-1475.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1484.6-1484.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1483.12-1483.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1479.12-1479.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1480.13-1480.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1481.13-1481.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1485.6-1485.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1482.12-1482.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1486.12-1486.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1825.12-1825.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1826.5-1826.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1487.12-1487.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1827.12-1827.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1828.5-1828.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1488.12-1488.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1829.12-1829.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1830.5-1830.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1489.12-1489.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1831.12-1831.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1832.5-1832.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1449.6-1449.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1450.6-1450.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1451.12-1451.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1448.5-1448.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1447.6-1447.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1454.5-1454.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1455.5-1455.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1456.11-1456.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1453.5-1453.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1452.5-1452.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1445.6-1445.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1444.11-1444.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1402.11-1402.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1403.12-1403.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1412.12-1412.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1413.12-1413.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1414.12-1414.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1415.12-1415.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1416.12-1416.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1417.12-1417.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1418.12-1418.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1419.12-1419.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1420.12-1420.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1421.12-1421.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1404.12-1404.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1422.12-1422.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1423.12-1423.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1424.12-1424.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1425.12-1425.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1426.12-1426.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1427.12-1427.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1428.12-1428.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1429.12-1429.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1430.12-1430.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1431.12-1431.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1405.12-1405.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1432.12-1432.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1433.12-1433.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1434.12-1434.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1435.12-1435.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1436.12-1436.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1437.12-1437.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1438.12-1438.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1439.12-1439.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1440.12-1440.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1441.12-1441.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1406.12-1406.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1442.12-1442.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1407.12-1407.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1408.12-1408.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1409.12-1409.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1410.12-1410.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1411.12-1411.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1446.6-1446.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1443.13-1443.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1545.12-1545.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1843.12-1843.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1844.5-1844.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1546.5-1546.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1839.5-1839.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1840.5-1840.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1547.5-1547.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1849.5-1849.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1850.5-1850.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1396.12-1396.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1397.6-1397.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1548.5-1548.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1851.5-1851.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1852.5-1852.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1544.12-1544.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1376.6-1376.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1377.6-1377.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1378.12-1378.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1375.6-1375.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1374.6-1374.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1381.6-1381.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1382.6-1382.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1383.12-1383.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1380.6-1380.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1379.6-1379.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1694.6-1694.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1695.6-1695.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1693.11-1693.41" + wire width 2 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1684.6-1684.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1685.6-1685.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1686.13-1686.57" + wire width 32 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1683.6-1683.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1682.6-1682.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1689.6-1689.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1690.6-1690.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1691.11-1691.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1692.6-1692.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1688.6-1688.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1687.6-1687.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1678.13-1678.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1667.5-1667.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1666.12-1666.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1665.12-1665.37" + wire width 32 \main_sdmem2block_dma_data + attribute \src "ls180.v:1861.12-1861.67" + wire width 32 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1862.5-1862.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1672.5-1672.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1673.6-1673.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1671.5-1671.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1670.5-1670.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1680.13-1680.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1669.5-1669.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1668.12-1668.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1675.5-1675.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1674.5-1674.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1679.12-1679.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1865.12-1865.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1866.5-1866.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1676.13-1676.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1677.6-1677.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1681.6-1681.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1658.5-1658.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1659.12-1659.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1657.5-1657.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1656.5-1656.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1662.5-1662.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1663.5-1663.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1664.12-1664.52" + wire width 32 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1661.6-1661.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1660.5-1660.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1720.11-1720.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1725.6-1725.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1729.6-1729.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1730.6-1730.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1728.12-1728.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1732.6-1732.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1733.6-1733.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1731.12-1731.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1717.11-1717.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1719.11-1719.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1726.12-1726.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1727.12-1727.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1718.5-1718.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1703.6-1703.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1704.6-1704.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1705.12-1705.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1702.6-1702.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1701.6-1701.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1708.6-1708.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1709.6-1709.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1710.12-1710.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1707.6-1707.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1706.6-1706.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1715.12-1715.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1716.12-1716.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1713.6-1713.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1714.6-1714.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1711.6-1711.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1712.6-1712.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1721.11-1721.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1722.12-1722.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1724.12-1724.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1723.6-1723.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1653.6-1653.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1698.6-1698.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1654.6-1654.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1699.6-1699.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1655.12-1655.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1700.12-1700.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1652.6-1652.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1697.6-1697.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1651.6-1651.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1696.6-1696.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1102.6-1102.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1101.5-1101.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1104.5-1104.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1105.5-1105.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1103.11-1103.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1099.5-1099.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1100.6-1100.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1098.11-1098.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1202.6-1202.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1203.6-1203.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1204.12-1204.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1201.6-1201.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1200.6-1200.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1207.5-1207.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1208.5-1208.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1209.11-1209.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1206.6-1206.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1205.5-1205.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1192.11-1192.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1193.6-1193.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1183.5-1183.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1184.5-1184.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1185.6-1185.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1182.6-1182.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1181.6-1181.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1188.5-1188.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1189.5-1189.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1190.11-1190.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1191.11-1191.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1187.6-1187.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1186.6-1186.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1194.5-1194.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1165.6-1165.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1166.6-1166.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1167.6-1167.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1168.6-1168.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1169.6-1169.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1170.6-1170.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1171.12-1171.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1172.12-1172.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1173.6-1173.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1164.5-1164.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1163.6-1163.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1210.5-1210.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1805.5-1805.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1806.5-1806.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1180.5-1180.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1176.6-1176.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1197.6-1197.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1177.6-1177.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1198.6-1198.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1178.12-1178.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1199.12-1199.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1175.5-1175.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1196.6-1196.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1174.6-1174.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1195.6-1195.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1179.6-1179.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1162.11-1162.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1801.11-1801.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1802.5-1802.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1137.5-1137.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1138.5-1138.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1139.5-1139.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1140.6-1140.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1141.5-1141.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1142.5-1142.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1143.12-1143.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1144.11-1144.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1145.5-1145.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1136.6-1136.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1135.6-1135.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1147.5-1147.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1148.5-1148.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1149.5-1149.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1150.11-1150.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1151.5-1151.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1146.6-1146.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1154.5-1154.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1155.11-1155.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1153.5-1153.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1152.5-1152.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1158.5-1158.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1159.11-1159.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1160.11-1160.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1157.5-1157.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1156.5-1156.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1161.12-1161.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1803.12-1803.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1804.5-1804.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1134.11-1134.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1797.11-1797.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1798.5-1798.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1133.5-1133.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1121.6-1121.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1122.12-1122.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1120.6-1120.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1124.5-1124.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1125.5-1125.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1126.5-1126.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1127.11-1127.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1128.5-1128.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1123.6-1123.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1131.5-1131.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1132.11-1132.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1130.5-1130.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1129.5-1129.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1318.11-1318.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1817.11-1817.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1818.5-1818.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1358.6-1358.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1359.6-1359.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1360.12-1360.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1357.6-1357.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1356.6-1356.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1363.5-1363.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1364.5-1364.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1365.11-1365.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1362.6-1362.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1361.5-1361.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1348.5-1348.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1349.6-1349.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1339.5-1339.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1340.5-1340.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1341.12-1341.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1338.6-1338.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1337.6-1337.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1344.5-1344.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1345.5-1345.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1346.11-1346.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1347.11-1347.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1343.6-1343.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1342.6-1342.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1350.5-1350.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1321.6-1321.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1322.6-1322.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1323.6-1323.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1324.6-1324.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1325.6-1325.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1326.6-1326.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1327.12-1327.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1328.12-1328.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1329.6-1329.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1320.5-1320.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1319.6-1319.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1366.5-1366.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1821.5-1821.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1822.5-1822.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1336.5-1336.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1332.6-1332.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1353.6-1353.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1333.6-1333.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1354.6-1354.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1334.12-1334.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1355.12-1355.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1331.5-1331.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1352.6-1352.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1330.6-1330.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1351.6-1351.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1335.6-1335.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1291.5-1291.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1292.5-1292.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1293.5-1293.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1294.6-1294.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1295.5-1295.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1296.5-1296.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1297.12-1297.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1298.11-1298.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1299.5-1299.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1290.6-1290.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1289.6-1289.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1301.5-1301.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1302.5-1302.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1303.5-1303.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1304.11-1304.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1305.5-1305.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1300.6-1300.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1308.5-1308.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1309.11-1309.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1307.5-1307.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1306.5-1306.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1312.5-1312.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1313.5-1313.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1314.11-1314.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1315.11-1315.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1311.5-1311.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1310.5-1310.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1316.5-1316.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1317.12-1317.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1819.12-1819.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1820.5-1820.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1226.11-1226.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1813.11-1813.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1814.5-1814.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1280.6-1280.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1281.6-1281.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1282.12-1282.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1279.6-1279.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1278.6-1278.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1285.5-1285.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1286.5-1286.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1287.11-1287.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1284.6-1284.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1283.5-1283.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1270.11-1270.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1271.6-1271.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1261.5-1261.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1262.5-1262.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1263.6-1263.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1260.6-1260.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1259.6-1259.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1266.5-1266.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1267.5-1267.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1268.11-1268.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1269.11-1269.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1265.6-1265.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1264.6-1264.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1272.5-1272.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1243.6-1243.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1244.6-1244.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1245.6-1245.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1246.6-1246.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1247.6-1247.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1248.6-1248.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1249.12-1249.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1250.12-1250.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1251.6-1251.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1242.5-1242.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1241.6-1241.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1288.5-1288.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1809.5-1809.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1810.5-1810.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1258.5-1258.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1254.6-1254.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1275.6-1275.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1255.6-1255.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1276.6-1276.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1256.12-1256.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1277.12-1277.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1253.5-1253.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1274.6-1274.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1252.6-1252.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1273.6-1273.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1257.6-1257.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1240.5-1240.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1229.5-1229.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1230.5-1230.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1231.5-1231.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1232.5-1232.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1233.5-1233.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1234.5-1234.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1235.11-1235.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1236.11-1236.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1237.5-1237.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1228.6-1228.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1227.5-1227.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1212.6-1212.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1213.12-1213.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1211.6-1211.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1215.5-1215.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1216.5-1216.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1217.5-1217.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1218.11-1218.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1219.5-1219.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1214.6-1214.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1222.5-1222.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1223.5-1223.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1224.11-1224.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1221.5-1221.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1220.5-1220.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1238.5-1238.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1225.5-1225.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1239.5-1239.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1119.11-1119.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1793.11-1793.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1794.5-1794.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1107.6-1107.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1106.6-1106.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1109.5-1109.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1108.6-1108.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1111.6-1111.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1112.12-1112.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1110.6-1110.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1114.5-1114.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1115.5-1115.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1116.5-1116.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1117.11-1117.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1118.5-1118.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1113.6-1113.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1367.6-1367.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1368.5-1368.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1369.6-1369.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1370.6-1370.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1371.11-1371.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1372.12-1372.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1373.6-1373.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1096.6-1096.23" + wire \main_sdphy_status + attribute \src "ls180.v:1097.6-1097.19" + wire \main_sdphy_we + attribute \src "ls180.v:331.5-331.26" + wire \main_sdram_address_re + attribute \src "ls180.v:330.12-330.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:333.5-333.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:332.11-332.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:429.5-429.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:451.11-451.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:456.6-456.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:461.6-461.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:462.6-462.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:460.13-460.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:459.6-459.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:465.6-465.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:466.6-466.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:464.13-464.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:463.6-463.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:448.11-448.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:450.11-450.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:457.12-457.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:458.13-458.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:449.5-449.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:432.5-432.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:433.5-433.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:435.13-435.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:434.6-434.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:431.6-431.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:430.6-430.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:438.6-438.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:439.6-439.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:441.13-441.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:440.6-440.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:437.6-437.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:436.6-436.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:446.13-446.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:447.13-447.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:444.6-444.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:445.6-445.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:442.6-442.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:443.6-443.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:452.11-452.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:453.13-453.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:455.13-455.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:454.6-454.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:469.6-469.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:470.6-470.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:472.13-472.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:471.6-471.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:468.6-468.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:467.6-467.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:475.5-475.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:476.5-476.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:478.12-478.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:477.5-477.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:474.6-474.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:473.5-473.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:421.12-421.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:422.12-422.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:423.5-423.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:426.5-426.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:427.5-427.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:428.5-428.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:424.5-424.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:425.5-425.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:420.5-420.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:419.5-419.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:418.5-418.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:417.6-417.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:413.13-413.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:414.6-414.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:416.5-416.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:411.6-411.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:410.6-410.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:415.5-415.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:412.6-412.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:479.12-479.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:483.5-483.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:484.5-484.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:481.6-481.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:482.5-482.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:480.5-480.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:491.32-491.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:490.6-490.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:489.32-489.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:488.6-488.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:487.11-487.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:486.32-486.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:485.6-485.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:511.5-511.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:533.11-533.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:538.6-538.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:543.6-543.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:544.6-544.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:542.13-542.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:541.6-541.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:547.6-547.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:548.6-548.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:546.13-546.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:545.6-545.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:530.11-530.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:532.11-532.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:539.12-539.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:540.13-540.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:531.5-531.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:514.5-514.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:515.5-515.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:517.13-517.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:516.6-516.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:513.6-513.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:512.6-512.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:520.6-520.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:521.6-521.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:523.13-523.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:522.6-522.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:519.6-519.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:518.6-518.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:528.13-528.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:529.13-529.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:526.6-526.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:527.6-527.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:524.6-524.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:525.6-525.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:534.11-534.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:535.13-535.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:537.13-537.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:536.6-536.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:551.6-551.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:552.6-552.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:554.13-554.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:553.6-553.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:550.6-550.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:549.6-549.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:557.5-557.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:558.5-558.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:560.12-560.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:559.5-559.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:556.6-556.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:555.5-555.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:503.12-503.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:504.12-504.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:505.5-505.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:508.5-508.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:509.5-509.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:510.5-510.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:506.5-506.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:507.5-507.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:502.5-502.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:501.5-501.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:500.5-500.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:499.6-499.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:495.13-495.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:496.6-496.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:498.5-498.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:493.6-493.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:492.6-492.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:497.5-497.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:494.6-494.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:561.12-561.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:565.5-565.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:566.5-566.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:563.6-563.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:564.5-564.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:562.5-562.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:573.32-573.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:572.6-572.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:571.32-571.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:570.6-570.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:569.11-569.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:568.32-568.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:567.6-567.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:593.5-593.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:615.11-615.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:620.6-620.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:625.6-625.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:626.6-626.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:624.13-624.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:623.6-623.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:629.6-629.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:630.6-630.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:628.13-628.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:627.6-627.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:612.11-612.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:614.11-614.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:621.12-621.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:622.13-622.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:613.5-613.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:596.5-596.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:597.5-597.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:599.13-599.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:598.6-598.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:595.6-595.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:594.6-594.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:602.6-602.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:603.6-603.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:605.13-605.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:604.6-604.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:601.6-601.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:600.6-600.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:610.13-610.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:611.13-611.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:608.6-608.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:609.6-609.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:606.6-606.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:607.6-607.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:616.11-616.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:617.13-617.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:619.13-619.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:618.6-618.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:633.6-633.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:634.6-634.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:636.13-636.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:635.6-635.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:632.6-632.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:631.6-631.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:639.5-639.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:640.5-640.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:642.12-642.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:641.5-641.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:638.6-638.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:637.5-637.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:585.12-585.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:586.12-586.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:587.5-587.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:590.5-590.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:591.5-591.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:592.5-592.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:588.5-588.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:589.5-589.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:584.5-584.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:583.5-583.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:582.5-582.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:581.6-581.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:577.13-577.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:578.6-578.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:580.5-580.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:575.6-575.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:574.6-574.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:579.5-579.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:576.6-576.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:643.12-643.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:647.5-647.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:648.5-648.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:645.6-645.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:646.5-646.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:644.5-644.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:655.32-655.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:654.6-654.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:653.32-653.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:652.6-652.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:651.11-651.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:650.32-650.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:649.6-649.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:675.5-675.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:697.11-697.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:702.6-702.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:707.6-707.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:708.6-708.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:706.13-706.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:705.6-705.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:711.6-711.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:712.6-712.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:710.13-710.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:709.6-709.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:694.11-694.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:696.11-696.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:703.12-703.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:704.13-704.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:695.5-695.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:678.5-678.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:679.5-679.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:681.13-681.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:680.6-680.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:677.6-677.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:676.6-676.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:684.6-684.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:685.6-685.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:687.13-687.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:686.6-686.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:683.6-683.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:682.6-682.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:692.13-692.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:693.13-693.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:690.6-690.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:691.6-691.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:688.6-688.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:689.6-689.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:698.11-698.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:699.13-699.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:701.13-701.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:700.6-700.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:715.6-715.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:716.6-716.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:718.13-718.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:717.6-717.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:714.6-714.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:713.6-713.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:721.5-721.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:722.5-722.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:724.12-724.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:723.5-723.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:720.6-720.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:719.5-719.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:667.12-667.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:668.12-668.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:669.5-669.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:672.5-672.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:673.5-673.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:674.5-674.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:670.5-670.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:671.5-671.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:666.5-666.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:665.5-665.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:664.5-664.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:663.6-663.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:659.13-659.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:660.6-660.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:662.5-662.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:657.6-657.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:656.6-656.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:661.5-661.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:658.6-658.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:725.12-725.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:729.5-729.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:730.5-730.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:727.6-727.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:728.5-728.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:726.5-726.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:737.32-737.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:736.6-736.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:735.32-735.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:734.6-734.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:733.11-733.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:732.32-732.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:731.6-731.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:739.6-739.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:757.6-757.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:746.13-746.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:747.12-747.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:748.5-748.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:751.6-751.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:752.6-752.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:753.6-753.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:749.5-749.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:750.5-750.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:745.5-745.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:744.6-744.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:756.11-756.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:755.12-755.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:754.11-754.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:743.5-743.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:742.5-742.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:740.5-740.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:741.5-741.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:775.6-775.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:764.13-764.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:765.12-765.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:766.5-766.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:769.6-769.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:770.6-770.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:771.6-771.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:767.5-767.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:768.5-768.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:763.5-763.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:762.6-762.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:774.11-774.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:773.12-773.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:772.11-772.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:761.5-761.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:760.6-760.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:758.5-758.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:759.5-759.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:319.6-319.20" + wire \main_sdram_cke + attribute \src "ls180.v:387.5-387.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:388.12-388.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:389.11-389.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:390.5-390.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:393.5-393.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:394.5-394.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:391.5-391.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:392.5-392.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:386.5-386.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:385.5-385.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:327.6-327.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:326.6-326.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:329.5-329.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:328.6-328.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:325.5-325.26" + wire \main_sdram_command_re + attribute \src "ls180.v:324.11-324.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:378.5-378.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:369.12-369.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:370.11-370.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:371.5-371.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:375.6-375.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:372.5-372.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:376.6-376.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:373.5-373.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:383.13-383.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:382.5-382.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:384.6-384.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:377.6-377.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:374.5-374.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:379.13-379.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:380.5-380.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:381.12-381.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:793.5-793.19" + wire \main_sdram_en0 + attribute \src "ls180.v:796.5-796.19" + wire \main_sdram_en1 + attribute \src "ls180.v:799.6-799.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:341.13-341.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:342.6-342.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:344.6-344.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:339.6-339.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:338.6-338.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:343.6-343.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:340.6-340.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:348.13-348.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:349.6-349.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:351.6-351.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:346.6-346.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:345.6-345.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:350.6-350.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:347.6-347.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:355.13-355.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:356.6-356.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:358.6-358.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:353.6-353.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:352.6-352.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:357.6-357.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:354.6-354.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:362.13-362.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:363.6-363.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:365.6-365.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:360.6-360.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:359.6-359.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:364.6-364.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:361.6-361.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:368.13-368.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:366.12-366.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:367.11-367.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:279.5-279.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:270.13-270.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:271.12-271.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:272.5-272.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:276.6-276.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:273.5-273.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:277.6-277.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:274.5-274.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:284.12-284.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:283.6-283.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:285.5-285.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:278.6-278.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:275.5-275.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:280.13-280.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:281.6-281.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:282.12-282.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:311.5-311.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:302.12-302.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:303.11-303.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:304.5-304.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:308.5-308.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:305.5-305.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:309.5-309.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:306.5-306.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:316.13-316.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:315.5-315.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:317.6-317.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:310.5-310.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:307.5-307.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:312.12-312.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:313.5-313.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:314.11-314.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:794.6-794.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:797.6-797.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:776.12-776.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:777.11-777.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:320.6-320.20" + wire \main_sdram_odt + attribute \src "ls180.v:403.5-403.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:401.6-401.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:402.5-402.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:738.6-738.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:323.5-323.18" + wire \main_sdram_re + attribute \src "ls180.v:791.6-791.31" + wire \main_sdram_read_available + attribute \src "ls180.v:321.6-321.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:318.6-318.20" + wire \main_sdram_sel + attribute \src "ls180.v:409.5-409.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:408.11-408.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:405.6-405.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:407.5-407.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:404.5-404.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:406.6-406.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:295.6-295.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:286.13-286.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:287.12-287.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:288.6-288.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:292.6-292.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:289.6-289.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:293.6-293.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:290.6-290.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:300.12-300.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:299.6-299.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:301.5-301.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:294.6-294.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:291.6-291.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:296.13-296.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:297.6-297.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:298.12-298.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:336.12-336.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:779.5-779.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:780.5-780.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:778.11-778.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:322.11-322.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:787.5-787.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:786.32-786.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:785.6-785.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:784.32-784.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:783.6-783.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:795.11-795.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:798.11-798.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:398.12-398.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:400.11-400.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:397.6-397.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:399.6-399.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:396.6-396.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:782.32-782.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:781.6-781.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:790.11-790.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:789.32-789.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:788.6-788.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:395.6-395.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:337.6-337.19" + wire \main_sdram_we + attribute \src "ls180.v:335.5-335.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:334.12-334.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:792.6-792.32" + wire \main_sdram_write_available + attribute \src "ls180.v:992.6-992.27" + wire \main_spimaster0_start + attribute \src "ls180.v:1002.12-1002.35" + wire width 8 \main_spimaster10_length + attribute \src "ls180.v:1003.12-1003.36" + wire width 16 \main_spimaster11_storage + attribute \src "ls180.v:1004.5-1004.24" + wire \main_spimaster12_re + attribute \src "ls180.v:1005.6-1005.27" + wire \main_spimaster13_done + attribute \src "ls180.v:1006.6-1006.29" + wire \main_spimaster14_status + attribute \src "ls180.v:1007.6-1007.25" + wire \main_spimaster15_we + attribute \src "ls180.v:1008.11-1008.35" + wire width 8 \main_spimaster16_storage + attribute \src "ls180.v:1009.5-1009.24" + wire \main_spimaster17_re + attribute \src "ls180.v:1010.12-1010.35" + wire width 8 \main_spimaster18_status + attribute \src "ls180.v:1011.6-1011.25" + wire \main_spimaster19_we + attribute \src "ls180.v:993.12-993.34" + wire width 8 \main_spimaster1_length + attribute \src "ls180.v:1065.5-1065.23" + wire \main_spimaster1_re + attribute \src "ls180.v:1064.12-1064.35" + wire width 16 \main_spimaster1_storage + attribute \src "ls180.v:1012.6-1012.26" + wire \main_spimaster20_sel + attribute \src "ls180.v:1013.5-1013.29" + wire \main_spimaster21_storage + attribute \src "ls180.v:1014.5-1014.24" + wire \main_spimaster22_re + attribute \src "ls180.v:1015.5-1015.29" + wire \main_spimaster23_storage + attribute \src "ls180.v:1016.5-1016.24" + wire \main_spimaster24_re + attribute \src "ls180.v:1017.5-1017.32" + wire \main_spimaster25_clk_enable + attribute \src "ls180.v:1018.5-1018.31" + wire \main_spimaster26_cs_enable + attribute \src "ls180.v:1019.11-1019.33" + wire width 3 \main_spimaster27_count + attribute \src "ls180.v:1785.11-1785.55" + wire width 3 \main_spimaster27_count_spimaster0_next_value + attribute \src "ls180.v:1786.5-1786.52" + wire \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:1020.5-1020.32" + wire \main_spimaster28_mosi_latch + attribute \src "ls180.v:1021.5-1021.32" + wire \main_spimaster29_miso_latch + attribute \src "ls180.v:994.5-994.25" + wire \main_spimaster2_done + attribute \src "ls180.v:1022.12-1022.40" + wire width 16 \main_spimaster30_clk_divider + attribute \src "ls180.v:1023.6-1023.31" + wire \main_spimaster31_clk_rise + attribute \src "ls180.v:1024.6-1024.31" + wire \main_spimaster32_clk_fall + attribute \src "ls180.v:1025.11-1025.37" + wire width 8 \main_spimaster33_mosi_data + attribute \src "ls180.v:1026.11-1026.36" + wire width 3 \main_spimaster34_mosi_sel + attribute \src "ls180.v:1027.11-1027.37" + wire width 8 \main_spimaster35_miso_data + attribute \src "ls180.v:995.5-995.24" + wire \main_spimaster3_irq + attribute \src "ls180.v:996.12-996.32" + wire width 8 \main_spimaster4_mosi + attribute \src "ls180.v:997.11-997.31" + wire width 8 \main_spimaster5_miso + attribute \src "ls180.v:998.6-998.24" + wire \main_spimaster6_cs + attribute \src "ls180.v:999.6-999.30" + wire \main_spimaster7_loopback + attribute \src "ls180.v:1000.12-1000.39" + wire width 16 \main_spimaster8_clk_divider + attribute \src "ls180.v:1001.5-1001.26" + wire \main_spimaster9_start + attribute \src "ls180.v:1036.13-1036.40" + wire width 16 \main_spisdcard_clk_divider0 + attribute \src "ls180.v:1058.12-1058.39" + wire width 16 \main_spisdcard_clk_divider1 + attribute \src "ls180.v:1053.5-1053.30" + wire \main_spisdcard_clk_enable + attribute \src "ls180.v:1060.6-1060.29" + wire \main_spisdcard_clk_fall + attribute \src "ls180.v:1059.6-1059.29" + wire \main_spisdcard_clk_rise + attribute \src "ls180.v:1040.5-1040.30" + wire \main_spisdcard_control_re + attribute \src "ls180.v:1039.12-1039.42" + wire width 16 \main_spisdcard_control_storage + attribute \src "ls180.v:1055.11-1055.31" + wire width 3 \main_spisdcard_count + attribute \src "ls180.v:1789.11-1789.53" + wire width 3 \main_spisdcard_count_spimaster1_next_value + attribute \src "ls180.v:1790.5-1790.50" + wire \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:1034.6-1034.23" + wire \main_spisdcard_cs + attribute \src "ls180.v:1054.5-1054.29" + wire \main_spisdcard_cs_enable + attribute \src "ls180.v:1050.5-1050.25" + wire \main_spisdcard_cs_re + attribute \src "ls180.v:1049.5-1049.30" + wire \main_spisdcard_cs_storage + attribute \src "ls180.v:1030.5-1030.25" + wire \main_spisdcard_done0 + attribute \src "ls180.v:1041.6-1041.26" + wire \main_spisdcard_done1 + attribute \src "ls180.v:1031.5-1031.23" + wire \main_spisdcard_irq + attribute \src "ls180.v:1029.12-1029.34" + wire width 8 \main_spisdcard_length0 + attribute \src "ls180.v:1038.12-1038.34" + wire width 8 \main_spisdcard_length1 + attribute \src "ls180.v:1035.6-1035.29" + wire \main_spisdcard_loopback + attribute \src "ls180.v:1052.5-1052.31" + wire \main_spisdcard_loopback_re + attribute \src "ls180.v:1051.5-1051.36" + wire \main_spisdcard_loopback_storage + attribute \src "ls180.v:1033.11-1033.30" + wire width 8 \main_spisdcard_miso + attribute \src "ls180.v:1063.11-1063.35" + wire width 8 \main_spisdcard_miso_data + attribute \src "ls180.v:1057.5-1057.30" + wire \main_spisdcard_miso_latch + attribute \src "ls180.v:1046.12-1046.38" + wire width 8 \main_spisdcard_miso_status + attribute \src "ls180.v:1047.6-1047.28" + wire \main_spisdcard_miso_we + attribute \src "ls180.v:1032.12-1032.31" + wire width 8 \main_spisdcard_mosi + attribute \src "ls180.v:1061.11-1061.35" + wire width 8 \main_spisdcard_mosi_data + attribute \src "ls180.v:1056.5-1056.30" + wire \main_spisdcard_mosi_latch + attribute \src "ls180.v:1045.5-1045.27" + wire \main_spisdcard_mosi_re + attribute \src "ls180.v:1062.11-1062.34" + wire width 3 \main_spisdcard_mosi_sel + attribute \src "ls180.v:1044.11-1044.38" + wire width 8 \main_spisdcard_mosi_storage + attribute \src "ls180.v:1048.6-1048.24" + wire \main_spisdcard_sel + attribute \src "ls180.v:1028.6-1028.27" + wire \main_spisdcard_start0 + attribute \src "ls180.v:1037.5-1037.26" + wire \main_spisdcard_start1 + attribute \src "ls180.v:1042.6-1042.34" + wire \main_spisdcard_status_status + attribute \src "ls180.v:1043.6-1043.30" + wire \main_spisdcard_status_we + attribute \src "ls180.v:889.12-889.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:888.6-888.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:891.11-891.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:890.6-890.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:893.5-893.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:885.12-885.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:884.6-884.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:887.11-887.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:886.6-886.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:892.11-892.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:873.6-873.19" + wire \main_uart_irq + attribute \src "ls180.v:859.12-859.46" + wire width 32 \main_uart_phy_phase_accumulator_rx + attribute \src "ls180.v:849.12-849.46" + wire width 32 \main_uart_phy_phase_accumulator_tx + attribute \src "ls180.v:842.5-842.21" + wire \main_uart_phy_re + attribute \src "ls180.v:860.6-860.22" + wire \main_uart_phy_rx + attribute \src "ls180.v:863.11-863.36" + wire width 4 \main_uart_phy_rx_bitcount + attribute \src "ls180.v:864.5-864.26" + wire \main_uart_phy_rx_busy + attribute \src "ls180.v:861.5-861.23" + wire \main_uart_phy_rx_r + attribute \src "ls180.v:862.11-862.31" + wire width 8 \main_uart_phy_rx_reg + attribute \src "ls180.v:845.6-845.30" + wire \main_uart_phy_sink_first + attribute \src "ls180.v:846.6-846.29" + wire \main_uart_phy_sink_last + attribute \src "ls180.v:847.12-847.43" + wire width 8 \main_uart_phy_sink_payload_data + attribute \src "ls180.v:844.5-844.29" + wire \main_uart_phy_sink_ready + attribute \src "ls180.v:843.6-843.30" + wire \main_uart_phy_sink_valid + attribute \src "ls180.v:855.5-855.31" + wire \main_uart_phy_source_first + attribute \src "ls180.v:856.5-856.30" + wire \main_uart_phy_source_last + attribute \src "ls180.v:857.11-857.44" + wire width 8 \main_uart_phy_source_payload_data + attribute \src "ls180.v:854.6-854.32" + wire \main_uart_phy_source_ready + attribute \src "ls180.v:853.5-853.31" + wire \main_uart_phy_source_valid + attribute \src "ls180.v:841.12-841.33" + wire width 32 \main_uart_phy_storage + attribute \src "ls180.v:851.11-851.36" + wire width 4 \main_uart_phy_tx_bitcount + attribute \src "ls180.v:852.5-852.26" + wire \main_uart_phy_tx_busy + attribute \src "ls180.v:850.11-850.31" + wire width 8 \main_uart_phy_tx_reg + attribute \src "ls180.v:858.5-858.32" + wire \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:848.5-848.32" + wire \main_uart_phy_uart_clk_txen + attribute \src "ls180.v:982.5-982.20" + wire \main_uart_reset + attribute \src "ls180.v:882.5-882.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:966.11-966.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:971.6-971.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:977.6-977.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:978.6-978.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:976.12-976.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:980.6-980.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:981.6-981.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:979.12-979.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:963.11-963.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:975.12-975.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:965.11-965.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:972.12-972.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:973.12-973.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:974.6-974.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:955.6-955.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:956.5-956.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:964.5-964.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:947.6-947.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:948.6-948.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:949.12-949.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:946.6-946.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:945.6-945.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:952.6-952.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:953.6-953.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:954.12-954.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:951.6-951.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:950.6-950.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:961.12-961.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:962.12-962.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:959.6-959.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:960.6-960.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:957.6-957.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:958.6-958.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:967.11-967.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:968.12-968.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:970.12-970.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:969.6-969.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:883.5-883.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:880.5-880.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:879.6-879.25" + wire \main_uart_rx_status + attribute \src "ls180.v:881.6-881.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:871.6-871.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:872.6-872.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:896.6-896.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:897.6-897.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:866.12-866.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:865.6-865.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:868.12-868.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:867.6-867.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:877.5-877.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:929.11-929.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:934.6-934.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:940.6-940.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:941.6-941.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:939.12-939.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:943.6-943.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:944.6-944.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:942.12-942.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:926.11-926.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:938.12-938.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:928.11-928.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:935.12-935.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:936.12-936.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:937.6-937.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:918.6-918.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:919.5-919.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:927.5-927.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:910.5-910.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:911.5-911.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:912.12-912.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:909.6-909.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:908.6-908.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:915.6-915.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:916.6-916.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:917.12-917.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:914.6-914.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:913.6-913.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:924.12-924.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:925.12-925.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:922.6-922.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:923.6-923.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:920.6-920.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:921.6-921.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:930.11-930.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:931.12-931.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:933.12-933.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:932.6-932.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:878.5-878.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:875.5-875.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:874.6-874.25" + wire \main_uart_tx_status + attribute \src "ls180.v:876.6-876.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:894.6-894.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:895.6-895.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:869.6-869.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:870.6-870.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:900.6-900.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:901.6-901.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:902.12-902.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:899.6-899.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:898.6-898.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:905.6-905.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:906.6-906.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:907.12-907.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:904.6-904.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:903.6-903.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:819.5-819.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:813.13-813.30" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:822.12-822.29" + wire width 2 \main_wb_sdram_bte + attribute \src "ls180.v:821.12-821.29" + wire width 3 \main_wb_sdram_cti + attribute \src "ls180.v:817.6-817.23" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:815.13-815.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:814.13-814.32" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:823.5-823.22" + wire \main_wb_sdram_err + attribute \src "ls180.v:816.12-816.29" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:818.6-818.23" + wire \main_wb_sdram_stb + attribute \src "ls180.v:820.6-820.22" + wire \main_wb_sdram_we + attribute \src "ls180.v:837.5-837.24" + wire \main_wdata_consumed + attribute \src "ls180.v:10058.11-10058.17" + wire width 7 \memadr + attribute \src "ls180.v:10078.12-10078.18" + wire width 25 \memdat + attribute \src "ls180.v:10092.12-10092.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10106.12-10106.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10120.12-10120.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10134.11-10134.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10135.11-10135.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10151.11-10151.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10152.11-10152.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10168.11-10168.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10182.11-10182.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:52.20-52.22" + wire width 36 input 48 \nc + attribute \src "ls180.v:251.6-251.13" wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" - wire input 2 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_a_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_a_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_a_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_a_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_a_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_a_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_a_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_a_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_ba_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_ba_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_ba_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_ba_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_cas_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_cas_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_cke__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_cke__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_clock__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_clock__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dm_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dm_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dm_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dm_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_10__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_10__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_10__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_10__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_10__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_11__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sdr_dq_11__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_11__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_11__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_12__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 167 \sdr_dq_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 168 \sdr_dq_12__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sdr_dq_12__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 323 \sdr_dq_12__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 324 \sdr_dq_13__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sdr_dq_13__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sdr_dq_13__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 169 \sdr_dq_13__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_13__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_13__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 327 \sdr_dq_14__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 173 \sdr_dq_14__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 174 \sdr_dq_14__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sdr_dq_14__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 328 \sdr_dq_14__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 329 \sdr_dq_14__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 330 \sdr_dq_15__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sdr_dq_15__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sdr_dq_15__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 175 \sdr_dq_15__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 331 \sdr_dq_15__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 332 \sdr_dq_15__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dq_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dq_5__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_6__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_dq_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_dq_6__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_dq_6__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_6__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_dq_7__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_dq_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_dq_7__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_dq_7__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_dq_7__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_dq_7__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_8__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_8__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_8__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_8__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_8__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_8__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_9__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_9__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_9__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_9__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_9__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_9__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_ras_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_ras_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_we_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:171" - wire \ti_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" - wire \xics_icp_core_irq_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_icp_ics_i_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_icp_ics_i_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" - wire width 8 \xics_ics_icp_o_pri - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" - wire width 4 \xics_ics_icp_o_src - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" - cell $add $add$libresoc.v:185113$13283 + attribute \src "ls180.v:22.19-22.22" + wire width 2 output 18 \pwm + attribute \src "ls180.v:141.12-141.17" + wire width 2 \pwm_1 + attribute \src "ls180.v:14.13-14.23" + wire output 10 \sdcard_clk + attribute \src "ls180.v:15.14-15.26" + wire output 11 \sdcard_cmd_i + attribute \src "ls180.v:16.13-16.25" + wire output 12 \sdcard_cmd_o + attribute \src "ls180.v:17.13-17.26" + wire output 13 \sdcard_cmd_oe + attribute \src "ls180.v:18.19-18.32" + wire width 4 input 14 \sdcard_data_i + attribute \src "ls180.v:19.19-19.32" + wire width 4 output 15 \sdcard_data_o + attribute \src "ls180.v:20.13-20.27" + wire output 16 \sdcard_data_oe + attribute \src "ls180.v:27.20-27.27" + wire width 13 output 23 \sdram_a + attribute \src "ls180.v:36.19-36.27" + wire width 2 output 32 \sdram_ba + attribute \src "ls180.v:33.13-33.24" + wire output 29 \sdram_cas_n + attribute \src "ls180.v:35.13-35.22" + wire output 31 \sdram_cke + attribute \src "ls180.v:38.13-38.24" + wire output 34 \sdram_clock + attribute \src "ls180.v:157.6-157.19" + wire \sdram_clock_1 + attribute \src "ls180.v:34.13-34.23" + wire output 30 \sdram_cs_n + attribute \src "ls180.v:37.19-37.27" + wire width 2 output 33 \sdram_dm + attribute \src "ls180.v:28.21-28.31" + wire width 16 output 24 \sdram_dq_i + attribute \src "ls180.v:29.20-29.30" + wire width 16 output 25 \sdram_dq_o + attribute \src "ls180.v:30.13-30.24" + wire output 26 \sdram_dq_oe + attribute \src "ls180.v:32.13-32.24" + wire output 28 \sdram_ras_n + attribute \src "ls180.v:31.13-31.23" + wire output 27 \sdram_we_n + attribute \src "ls180.v:2647.6-2647.15" + wire \sdrio_clk + attribute \src "ls180.v:2648.6-2648.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2657.6-2657.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2658.6-2658.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2659.6-2659.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2660.6-2660.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2661.6-2661.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2662.6-2662.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2663.6-2663.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2664.6-2664.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2665.6-2665.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2666.6-2666.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2649.6-2649.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2667.6-2667.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2668.6-2668.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2669.6-2669.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2670.6-2670.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2671.6-2671.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2672.6-2672.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2673.6-2673.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2674.6-2674.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2675.6-2675.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2676.6-2676.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2650.6-2650.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2677.6-2677.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2678.6-2678.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2679.6-2679.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2680.6-2680.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2681.6-2681.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2682.6-2682.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2683.6-2683.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2684.6-2684.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2685.6-2685.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2686.6-2686.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2651.6-2651.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2687.6-2687.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2688.6-2688.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2689.6-2689.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2690.6-2690.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2691.6-2691.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2692.6-2692.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2693.6-2693.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2694.6-2694.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2695.6-2695.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2696.6-2696.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2652.6-2652.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2697.6-2697.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2698.6-2698.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2699.6-2699.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2700.6-2700.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2701.6-2701.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2702.6-2702.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2737.6-2737.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2738.6-2738.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2739.6-2739.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2740.6-2740.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2653.6-2653.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2741.6-2741.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2742.6-2742.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2743.6-2743.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2744.6-2744.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2745.6-2745.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2746.6-2746.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2747.6-2747.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2748.6-2748.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2749.6-2749.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2654.6-2654.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2655.6-2655.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2656.6-2656.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:23.13-23.26" + wire output 19 \spimaster_clk + attribute \src "ls180.v:25.13-25.27" + wire output 21 \spimaster_cs_n + attribute \src "ls180.v:26.14-26.28" + wire output 22 \spimaster_miso + attribute \src "ls180.v:24.13-24.27" + wire output 20 \spimaster_mosi + attribute \src "ls180.v:8.13-8.26" + wire output 4 \spisdcard_clk + attribute \src "ls180.v:10.13-10.27" + wire output 6 \spisdcard_cs_n + attribute \src "ls180.v:11.14-11.28" + wire output 7 \spisdcard_miso + attribute \src "ls180.v:9.13-9.27" + wire output 5 \spisdcard_mosi + attribute \src "ls180.v:43.13-43.20" + wire input 39 \sys_clk + attribute \src "ls180.v:249.6-249.15" + wire \sys_clk_1 + attribute \src "ls180.v:45.19-45.31" + wire width 3 input 41 \sys_clksel_i + attribute \src "ls180.v:46.14-46.26" + wire output 42 \sys_pll_18_o + attribute \src "ls180.v:47.14-47.27" + wire output 43 \sys_pll_lck_o + attribute \src "ls180.v:44.13-44.20" + wire input 40 \sys_rst + attribute \src "ls180.v:250.6-250.15" + wire \sys_rst_1 + attribute \src "ls180.v:13.13-13.20" + wire input 9 \uart_rx + attribute \src "ls180.v:12.13-12.20" + wire output 8 \uart_tx + attribute \src "ls180.v:10057.12-10057.15" + memory width 32 size 128 \mem + attribute \src "ls180.v:10077.12-10077.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10091.12-10091.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10105.12-10105.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10119.12-10119.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10133.11-10133.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10150.11-10150.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10167.11-10167.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10181.11-10181.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2819.68-2819.110" + cell $add $add$ls180.v:2819$22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2819$22_Y + end + attribute \src "ls180.v:2879.68-2879.110" + cell $add $add$ls180.v:2879$33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2879$33_Y + end + attribute \src "ls180.v:2939.68-2939.110" + cell $add $add$ls180.v:2939$44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $add$ls180.v:2939$44_Y + end + attribute \src "ls180.v:4072.54-4072.83" + cell $add $add$ls180.v:4072$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4072$537_Y + end + attribute \src "ls180.v:4172.36-4172.89" + cell $add $add$ls180.v:4172$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4172$583_Y + end + attribute \src "ls180.v:4202.36-4202.89" + cell $add $add$ls180.v:4202$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4202$594_Y + end + attribute \src "ls180.v:4257.54-4257.83" + cell $add $add$ls180.v:4257$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster27_count + connect \B 1'1 + connect \Y $add$ls180.v:4257$607_Y + end + attribute \src "ls180.v:4316.52-4316.79" + cell $add $add$ls180.v:4316$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_count + connect \B 1'1 + connect \Y $add$ls180.v:4316$615_Y + end + attribute \src "ls180.v:4420.58-4420.86" + cell $add $add$ls180.v:4420$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4420$643_Y + end + attribute \src "ls180.v:4477.58-4477.86" + cell $add $add$ls180.v:4477$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4477$646_Y + end + attribute \src "ls180.v:4494.58-4494.86" + cell $add $add$ls180.v:4494$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4494$648_Y + end + attribute \src "ls180.v:4587.59-4587.87" + cell $add $add$ls180.v:4587$665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4587$665_Y + end + attribute \src "ls180.v:4612.59-4612.87" + cell $add $add$ls180.v:4612$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4612$668_Y + end + attribute \src "ls180.v:4734.53-4734.82" + cell $add $add$ls180.v:4734$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4734$685_Y + end + attribute \src "ls180.v:4845.65-4845.114" + cell $add $add$ls180.v:4845$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:4845$699_Y + end + attribute \src "ls180.v:4850.62-4850.91" + cell $add $add$ls180.v:4850$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4850$702_Y + end + attribute \src "ls180.v:4876.61-4876.90" + cell $add $add$ls180.v:4876$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:4876$705_Y + end + attribute \src "ls180.v:5080.80-5080.117" + cell $add $add$ls180.v:5080$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:5080$890_Y + end + attribute \src "ls180.v:5274.54-5274.82" + cell $add $add$ls180.v:5274$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5274$965_Y + end + attribute \src "ls180.v:5326.55-5326.84" + cell $add $add$ls180.v:5326$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5326$975_Y + end + attribute \src "ls180.v:5352.57-5352.86" + cell $add $add$ls180.v:5352$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5352$983_Y + end + attribute \src "ls180.v:5473.51-5473.134" + cell $add $add$ls180.v:5473$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5473$999_Y + end + attribute \src "ls180.v:5476.77-5476.125" + cell $add $add$ls180.v:5476$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5476$1001_Y + end + attribute \src "ls180.v:5569.50-5569.105" + cell $add $add$ls180.v:5569$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5569$1010_Y + end + attribute \src "ls180.v:5571.77-5571.111" + cell $add $add$ls180.v:5571$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5571$1011_Y + end + attribute \src "ls180.v:7503.36-7503.70" + cell $add $add$ls180.v:7503$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7503$2415_Y + end + attribute \src "ls180.v:7588.37-7588.72" + cell $add $add$ls180.v:7588$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7588$2436_Y + end + attribute \src "ls180.v:7605.60-7605.119" + cell $add $add$ls180.v:7605$2440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7605$2440_Y + end + attribute \src "ls180.v:7608.60-7608.119" + cell $add $add$ls180.v:7608$2441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7608$2441_Y + end + attribute \src "ls180.v:7612.59-7612.116" + cell $add $add$ls180.v:7612$2446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7612$2446_Y + end + attribute \src "ls180.v:7651.60-7651.119" + cell $add $add$ls180.v:7651$2456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7651$2456_Y + end + attribute \src "ls180.v:7654.60-7654.119" + cell $add $add$ls180.v:7654$2457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7654$2457_Y + end + attribute \src "ls180.v:7658.59-7658.116" + cell $add $add$ls180.v:7658$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7658$2462_Y + end + attribute \src "ls180.v:7697.60-7697.119" + cell $add $add$ls180.v:7697$2472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7697$2472_Y + end + attribute \src "ls180.v:7700.60-7700.119" + cell $add $add$ls180.v:7700$2473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7700$2473_Y + end + attribute \src "ls180.v:7704.59-7704.116" + cell $add $add$ls180.v:7704$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7704$2478_Y + end + attribute \src "ls180.v:7743.60-7743.119" + cell $add $add$ls180.v:7743$2488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7743$2488_Y + end + attribute \src "ls180.v:7746.60-7746.119" + cell $add $add$ls180.v:7746$2489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7746$2489_Y + end + attribute \src "ls180.v:7750.59-7750.116" + cell $add $add$ls180.v:7750$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7750$2494_Y + end + attribute \src "ls180.v:7980.34-7980.66" + cell $add $add$ls180.v:7980$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:7980$2548_Y + end + attribute \src "ls180.v:7996.73-7996.131" + cell $add $add$ls180.v:7996$2551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_tx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:7996$2551_Y + end + attribute \src "ls180.v:8009.34-8009.66" + cell $add $add$ls180.v:8009$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:8009$2555_Y + end + attribute \src "ls180.v:8028.73-8028.131" + cell $add $add$ls180.v:8028$2558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_rx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8028$2558_Y + end + attribute \src "ls180.v:8054.33-8054.65" + cell $add $add$ls180.v:8054$2566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8054$2566_Y + end + attribute \src "ls180.v:8057.33-8057.65" + cell $add $add$ls180.v:8057$2567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8057$2567_Y + end + attribute \src "ls180.v:8061.33-8061.64" + cell $add $add$ls180.v:8061$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8061$2572_Y + end + attribute \src "ls180.v:8076.33-8076.65" + cell $add $add$ls180.v:8076$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8076$2577_Y + end + attribute \src "ls180.v:8079.33-8079.65" + cell $add $add$ls180.v:8079$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8079$2578_Y + end + attribute \src "ls180.v:8083.33-8083.64" + cell $add $add$ls180.v:8083$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8083$2583_Y + end + attribute \src "ls180.v:8104.35-8104.70" + cell $add $add$ls180.v:8104$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster30_clk_divider + connect \B 1'1 + connect \Y $add$ls180.v:8104$2585_Y + end + attribute \src "ls180.v:8139.34-8139.68" + cell $add $add$ls180.v:8139$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8139$2590_Y + end + attribute \src "ls180.v:8175.25-8175.49" + cell $add $add$ls180.v:8175$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8175$2595_Y + end + attribute \src "ls180.v:8189.25-8189.49" + cell $add $add$ls180.v:8189$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8189$2599_Y + end + attribute \src "ls180.v:8203.31-8203.61" + cell $add $add$ls180.v:8203$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8203$2604_Y + end + attribute \src "ls180.v:8226.45-8226.88" + cell $add $add$ls180.v:8226$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8226$2608_Y + end + attribute \src "ls180.v:8272.71-8272.114" + cell $add $add$ls180.v:8272$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8272$2614_Y + end + attribute \src "ls180.v:8307.46-8307.90" + cell $add $add$ls180.v:8307$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8307$2620_Y + end + attribute \src "ls180.v:8353.72-8353.116" + cell $add $add$ls180.v:8353$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8353$2626_Y + end + attribute \src "ls180.v:8386.47-8386.92" + cell $add $add$ls180.v:8386$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8386$2632_Y + end + attribute \src "ls180.v:8414.73-8414.118" + cell $add $add$ls180.v:8414$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8414$2638_Y + end + attribute \src "ls180.v:8526.39-8526.75" + cell $add $add$ls180.v:8526$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8526$2651_Y + end + attribute \src "ls180.v:8587.37-8587.73" + cell $add $add$ls180.v:8587$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8587$2655_Y + end + attribute \src "ls180.v:8590.37-8590.73" + cell $add $add$ls180.v:8590$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8590$2656_Y + end + attribute \src "ls180.v:8594.36-8594.70" + cell $add $add$ls180.v:8594$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8594$2661_Y + end + attribute \src "ls180.v:8609.41-8609.80" + cell $add $add$ls180.v:8609$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8609$2665_Y + end + attribute \src "ls180.v:8643.67-8643.106" + cell $add $add$ls180.v:8643$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8643$2671_Y + end + attribute \src "ls180.v:8669.39-8669.76" + cell $add $add$ls180.v:8669$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8669$2673_Y + end + attribute \src "ls180.v:8673.37-8673.73" + cell $add $add$ls180.v:8673$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8673$2677_Y + end + attribute \src "ls180.v:8676.37-8676.73" + cell $add $add$ls180.v:8676$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8676$2678_Y + end + attribute \src "ls180.v:8680.36-8680.70" + cell $add $add$ls180.v:8680$2683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8680$2683_Y + end + attribute \src "ls180.v:2813.9-2813.80" + cell $and $and$ls180.v:2813$17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2813$17_Y + end + attribute \src "ls180.v:2831.9-2831.80" + cell $and $and$ls180.v:2831$24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$ls180.v:2831$24_Y + end + attribute \src "ls180.v:2873.9-2873.80" + cell $and $and$ls180.v:2873$28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2873$28_Y + end + attribute \src "ls180.v:2891.9-2891.80" + cell $and $and$ls180.v:2891$35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$ls180.v:2891$35_Y + end + attribute \src "ls180.v:2933.9-2933.86" + cell $and $and$ls180.v:2933$39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2933$39_Y + end + attribute \src "ls180.v:2951.9-2951.86" + cell $and $and$ls180.v:2951$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_stb + connect \B \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $and$ls180.v:2951$46_Y + end + attribute \src "ls180.v:2961.31-2961.90" + cell $and $and$ls180.v:2961$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2961$48_Y + end + attribute \src "ls180.v:2961.30-2961.121" + cell $and $and$ls180.v:2961$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2961$48_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2961$49_Y + end + attribute \src "ls180.v:2961.29-2961.156" + cell $and $and$ls180.v:2961$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2961$49_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:2961$50_Y + end + attribute \src "ls180.v:2962.31-2962.90" + cell $and $and$ls180.v:2962$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2962$51_Y + end + attribute \src "ls180.v:2962.30-2962.121" + cell $and $and$ls180.v:2962$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2962$51_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2962$52_Y + end + attribute \src "ls180.v:2962.29-2962.156" + cell $and $and$ls180.v:2962$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2962$52_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:2962$53_Y + end + attribute \src "ls180.v:2963.31-2963.90" + cell $and $and$ls180.v:2963$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2963$54_Y + end + attribute \src "ls180.v:2963.30-2963.121" + cell $and $and$ls180.v:2963$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2963$54_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2963$55_Y + end + attribute \src "ls180.v:2963.29-2963.156" + cell $and $and$ls180.v:2963$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2963$55_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:2963$56_Y + end + attribute \src "ls180.v:2964.31-2964.90" + cell $and $and$ls180.v:2964$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:2964$57_Y + end + attribute \src "ls180.v:2964.30-2964.121" + cell $and $and$ls180.v:2964$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2964$57_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:2964$58_Y + end + attribute \src "ls180.v:2964.29-2964.156" + cell $and $and$ls180.v:2964$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:2964$58_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:2964$59_Y + end + attribute \src "ls180.v:2973.7-2973.89" + cell $and $and$ls180.v:2973$62 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:2973$62_Y + end + attribute \src "ls180.v:2978.32-2978.111" + cell $and $and$ls180.v:2978$63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:2978$63_Y + end + attribute \src "ls180.v:3092.40-3092.99" + cell $and $and$ls180.v:3092$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3092$70_Y + end + attribute \src "ls180.v:3093.40-3093.99" + cell $and $and$ls180.v:3093$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3093$71_Y + end + attribute \src "ls180.v:3131.38-3131.103" + cell $and $and$ls180.v:3131$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3131$76_Y + connect \Y $and$ls180.v:3131$77_Y + end + attribute \src "ls180.v:3185.50-3185.119" + cell $and $and$ls180.v:3185$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3185$85_Y + end + attribute \src "ls180.v:3185.49-3185.167" + cell $and $and$ls180.v:3185$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3185$85_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3185$86_Y + end + attribute \src "ls180.v:3186.49-3186.118" + cell $and $and$ls180.v:3186$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3186$87_Y + end + attribute \src "ls180.v:3186.48-3186.154" + cell $and $and$ls180.v:3186$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3186$87_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3186$88_Y + end + attribute \src "ls180.v:3187.50-3187.119" + cell $and $and$ls180.v:3187$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3187$89_Y + end + attribute \src "ls180.v:3187.49-3187.155" + cell $and $and$ls180.v:3187$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3187$89_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3187$90_Y + end + attribute \src "ls180.v:3190.7-3190.114" + cell $and $and$ls180.v:3190$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3190$92_Y + end + attribute \src "ls180.v:3219.66-3219.246" + cell $and $and$ls180.v:3219$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3219$97_Y + connect \Y $and$ls180.v:3219$98_Y + end + attribute \src "ls180.v:3220.64-3220.187" + cell $and $and$ls180.v:3220$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3220$99_Y + end + attribute \src "ls180.v:3244.9-3244.86" + cell $and $and$ls180.v:3244$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3244$105_Y + end + attribute \src "ls180.v:3256.9-3256.86" + cell $and $and$ls180.v:3256$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3256$106_Y + end + attribute \src "ls180.v:3306.13-3306.87" + cell $and $and$ls180.v:3306$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3306$108_Y + end + attribute \src "ls180.v:3342.50-3342.119" + cell $and $and$ls180.v:3342$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3342$115_Y + end + attribute \src "ls180.v:3342.49-3342.167" + cell $and $and$ls180.v:3342$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3342$115_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3342$116_Y + end + attribute \src "ls180.v:3343.49-3343.118" + cell $and $and$ls180.v:3343$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3343$117_Y + end + attribute \src "ls180.v:3343.48-3343.154" + cell $and $and$ls180.v:3343$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3343$117_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3343$118_Y + end + attribute \src "ls180.v:3344.50-3344.119" + cell $and $and$ls180.v:3344$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3344$119_Y + end + attribute \src "ls180.v:3344.49-3344.155" + cell $and $and$ls180.v:3344$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3344$119_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3344$120_Y + end + attribute \src "ls180.v:3347.7-3347.114" + cell $and $and$ls180.v:3347$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3347$122_Y + end + attribute \src "ls180.v:3376.66-3376.246" + cell $and $and$ls180.v:3376$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3376$127_Y + connect \Y $and$ls180.v:3376$128_Y + end + attribute \src "ls180.v:3377.64-3377.187" + cell $and $and$ls180.v:3377$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3377$129_Y + end + attribute \src "ls180.v:3401.9-3401.86" + cell $and $and$ls180.v:3401$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3401$135_Y + end + attribute \src "ls180.v:3413.9-3413.86" + cell $and $and$ls180.v:3413$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3413$136_Y + end + attribute \src "ls180.v:3463.13-3463.87" + cell $and $and$ls180.v:3463$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3463$138_Y + end + attribute \src "ls180.v:3499.50-3499.119" + cell $and $and$ls180.v:3499$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3499$145_Y + end + attribute \src "ls180.v:3499.49-3499.167" + cell $and $and$ls180.v:3499$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3499$145_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3499$146_Y + end + attribute \src "ls180.v:3500.49-3500.118" + cell $and $and$ls180.v:3500$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3500$147_Y + end + attribute \src "ls180.v:3500.48-3500.154" + cell $and $and$ls180.v:3500$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3500$147_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3500$148_Y + end + attribute \src "ls180.v:3501.50-3501.119" + cell $and $and$ls180.v:3501$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3501$149_Y + end + attribute \src "ls180.v:3501.49-3501.155" + cell $and $and$ls180.v:3501$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3501$149_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3501$150_Y + end + attribute \src "ls180.v:3504.7-3504.114" + cell $and $and$ls180.v:3504$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3504$152_Y + end + attribute \src "ls180.v:3533.66-3533.246" + cell $and $and$ls180.v:3533$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3533$157_Y + connect \Y $and$ls180.v:3533$158_Y + end + attribute \src "ls180.v:3534.64-3534.187" + cell $and $and$ls180.v:3534$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3534$159_Y + end + attribute \src "ls180.v:3558.9-3558.86" + cell $and $and$ls180.v:3558$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3558$165_Y + end + attribute \src "ls180.v:3570.9-3570.86" + cell $and $and$ls180.v:3570$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3570$166_Y + end + attribute \src "ls180.v:3620.13-3620.87" + cell $and $and$ls180.v:3620$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3620$168_Y + end + attribute \src "ls180.v:3656.50-3656.119" + cell $and $and$ls180.v:3656$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3656$175_Y + end + attribute \src "ls180.v:3656.49-3656.167" + cell $and $and$ls180.v:3656$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3656$175_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3656$176_Y + end + attribute \src "ls180.v:3657.49-3657.118" + cell $and $and$ls180.v:3657$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3657$177_Y + end + attribute \src "ls180.v:3657.48-3657.154" + cell $and $and$ls180.v:3657$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3657$177_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3657$178_Y + end + attribute \src "ls180.v:3658.50-3658.119" + cell $and $and$ls180.v:3658$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3658$179_Y + end + attribute \src "ls180.v:3658.49-3658.155" + cell $and $and$ls180.v:3658$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3658$179_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3658$180_Y + end + attribute \src "ls180.v:3661.7-3661.114" + cell $and $and$ls180.v:3661$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3661$182_Y + end + attribute \src "ls180.v:3690.66-3690.246" + cell $and $and$ls180.v:3690$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3690$187_Y + connect \Y $and$ls180.v:3690$188_Y + end + attribute \src "ls180.v:3691.64-3691.187" + cell $and $and$ls180.v:3691$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3691$189_Y + end + attribute \src "ls180.v:3715.9-3715.86" + cell $and $and$ls180.v:3715$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3715$195_Y + end + attribute \src "ls180.v:3727.9-3727.86" + cell $and $and$ls180.v:3727$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3727$196_Y + end + attribute \src "ls180.v:3777.13-3777.87" + cell $and $and$ls180.v:3777$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3777$198_Y + end + attribute \src "ls180.v:3792.37-3792.102" + cell $and $and$ls180.v:3792$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3792$199_Y + end + attribute \src "ls180.v:3792.108-3792.188" + cell $and $and$ls180.v:3792$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3792$200_Y + connect \Y $and$ls180.v:3792$201_Y + end + attribute \src "ls180.v:3792.107-3792.231" + cell $and $and$ls180.v:3792$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3792$201_Y + connect \B $not$ls180.v:3792$202_Y + connect \Y $and$ls180.v:3792$203_Y + end + attribute \src "ls180.v:3792.36-3792.232" + cell $and $and$ls180.v:3792$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3792$199_Y + connect \B $and$ls180.v:3792$203_Y + connect \Y $and$ls180.v:3792$204_Y + end + attribute \src "ls180.v:3793.37-3793.102" + cell $and $and$ls180.v:3793$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3793$205_Y + end + attribute \src "ls180.v:3793.108-3793.188" + cell $and $and$ls180.v:3793$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3793$206_Y + connect \Y $and$ls180.v:3793$207_Y + end + attribute \src "ls180.v:3793.107-3793.231" + cell $and $and$ls180.v:3793$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3793$207_Y + connect \B $not$ls180.v:3793$208_Y + connect \Y $and$ls180.v:3793$209_Y + end + attribute \src "ls180.v:3793.36-3793.232" + cell $and $and$ls180.v:3793$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3793$205_Y + connect \B $and$ls180.v:3793$209_Y + connect \Y $and$ls180.v:3793$210_Y + end + attribute \src "ls180.v:3794.34-3794.85" + cell $and $and$ls180.v:3794$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3794$211_Y + end + attribute \src "ls180.v:3795.37-3795.102" + cell $and $and$ls180.v:3795$212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3795$212_Y + end + attribute \src "ls180.v:3795.36-3795.194" + cell $and $and$ls180.v:3795$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3795$212_Y + connect \B $or$ls180.v:3795$213_Y + connect \Y $and$ls180.v:3795$214_Y + end + attribute \src "ls180.v:3797.37-3797.102" + cell $and $and$ls180.v:3797$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3797$215_Y + end + attribute \src "ls180.v:3797.36-3797.148" + cell $and $and$ls180.v:3797$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3797$215_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3797$216_Y + end + attribute \src "ls180.v:3798.40-3798.119" + cell $and $and$ls180.v:3798$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3798$217_Y + end + attribute \src "ls180.v:3798.124-3798.203" + cell $and $and$ls180.v:3798$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3798$218_Y + end + attribute \src "ls180.v:3798.209-3798.288" + cell $and $and$ls180.v:3798$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3798$220_Y + end + attribute \src "ls180.v:3798.294-3798.373" + cell $and $and$ls180.v:3798$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3798$222_Y + end + attribute \src "ls180.v:3799.41-3799.121" + cell $and $and$ls180.v:3799$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3799$224_Y + end + attribute \src "ls180.v:3799.126-3799.206" + cell $and $and$ls180.v:3799$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3799$225_Y + end + attribute \src "ls180.v:3799.212-3799.292" + cell $and $and$ls180.v:3799$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3799$227_Y + end + attribute \src "ls180.v:3799.298-3799.378" + cell $and $and$ls180.v:3799$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3799$229_Y + end + attribute \src "ls180.v:3806.38-3806.111" + cell $and $and$ls180.v:3806$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3806$233_Y + end + attribute \src "ls180.v:3806.37-3806.150" + cell $and $and$ls180.v:3806$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3806$233_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3806$234_Y + end + attribute \src "ls180.v:3806.36-3806.189" + cell $and $and$ls180.v:3806$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3806$234_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3806$235_Y + end + attribute \src "ls180.v:3812.77-3812.153" + cell $and $and$ls180.v:3812$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3812$238_Y + end + attribute \src "ls180.v:3812.162-3812.246" + cell $and $and$ls180.v:3812$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3812$239_Y + connect \Y $and$ls180.v:3812$240_Y + end + attribute \src "ls180.v:3812.161-3812.291" + cell $and $and$ls180.v:3812$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3812$240_Y + connect \B $not$ls180.v:3812$241_Y + connect \Y $and$ls180.v:3812$242_Y + end + attribute \src "ls180.v:3812.76-3812.333" + cell $and $and$ls180.v:3812$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3812$238_Y + connect \B $or$ls180.v:3812$244_Y + connect \Y $and$ls180.v:3812$245_Y + end + attribute \src "ls180.v:3812.338-3812.505" + cell $and $and$ls180.v:3812$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3812$246_Y + connect \B $eq$ls180.v:3812$247_Y + connect \Y $and$ls180.v:3812$248_Y + end + attribute \src "ls180.v:3812.38-3812.507" + cell $and $and$ls180.v:3812$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3812$249_Y + connect \Y $and$ls180.v:3812$250_Y + end + attribute \src "ls180.v:3813.77-3813.153" + cell $and $and$ls180.v:3813$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3813$251_Y + end + attribute \src "ls180.v:3813.162-3813.246" + cell $and $and$ls180.v:3813$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3813$252_Y + connect \Y $and$ls180.v:3813$253_Y + end + attribute \src "ls180.v:3813.161-3813.291" + cell $and $and$ls180.v:3813$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3813$253_Y + connect \B $not$ls180.v:3813$254_Y + connect \Y $and$ls180.v:3813$255_Y + end + attribute \src "ls180.v:3813.76-3813.333" + cell $and $and$ls180.v:3813$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3813$251_Y + connect \B $or$ls180.v:3813$257_Y + connect \Y $and$ls180.v:3813$258_Y + end + attribute \src "ls180.v:3813.338-3813.505" + cell $and $and$ls180.v:3813$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3813$259_Y + connect \B $eq$ls180.v:3813$260_Y + connect \Y $and$ls180.v:3813$261_Y + end + attribute \src "ls180.v:3813.38-3813.507" + cell $and $and$ls180.v:3813$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3813$262_Y + connect \Y $and$ls180.v:3813$263_Y + end + attribute \src "ls180.v:3814.77-3814.153" + cell $and $and$ls180.v:3814$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3814$264_Y + end + attribute \src "ls180.v:3814.162-3814.246" + cell $and $and$ls180.v:3814$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3814$265_Y + connect \Y $and$ls180.v:3814$266_Y + end + attribute \src "ls180.v:3814.161-3814.291" + cell $and $and$ls180.v:3814$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3814$266_Y + connect \B $not$ls180.v:3814$267_Y + connect \Y $and$ls180.v:3814$268_Y + end + attribute \src "ls180.v:3814.76-3814.333" + cell $and $and$ls180.v:3814$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3814$264_Y + connect \B $or$ls180.v:3814$270_Y + connect \Y $and$ls180.v:3814$271_Y + end + attribute \src "ls180.v:3814.338-3814.505" + cell $and $and$ls180.v:3814$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3814$272_Y + connect \B $eq$ls180.v:3814$273_Y + connect \Y $and$ls180.v:3814$274_Y + end + attribute \src "ls180.v:3814.38-3814.507" + cell $and $and$ls180.v:3814$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3814$275_Y + connect \Y $and$ls180.v:3814$276_Y + end + attribute \src "ls180.v:3815.77-3815.153" + cell $and $and$ls180.v:3815$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3815$277_Y + end + attribute \src "ls180.v:3815.162-3815.246" + cell $and $and$ls180.v:3815$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3815$278_Y + connect \Y $and$ls180.v:3815$279_Y + end + attribute \src "ls180.v:3815.161-3815.291" + cell $and $and$ls180.v:3815$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3815$279_Y + connect \B $not$ls180.v:3815$280_Y + connect \Y $and$ls180.v:3815$281_Y + end + attribute \src "ls180.v:3815.76-3815.333" + cell $and $and$ls180.v:3815$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3815$277_Y + connect \B $or$ls180.v:3815$283_Y + connect \Y $and$ls180.v:3815$284_Y + end + attribute \src "ls180.v:3815.338-3815.505" + cell $and $and$ls180.v:3815$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3815$285_Y + connect \B $eq$ls180.v:3815$286_Y + connect \Y $and$ls180.v:3815$287_Y + end + attribute \src "ls180.v:3815.38-3815.507" + cell $and $and$ls180.v:3815$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3815$288_Y + connect \Y $and$ls180.v:3815$289_Y + end + attribute \src "ls180.v:3845.77-3845.153" + cell $and $and$ls180.v:3845$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3845$296_Y + end + attribute \src "ls180.v:3845.162-3845.246" + cell $and $and$ls180.v:3845$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3845$297_Y + connect \Y $and$ls180.v:3845$298_Y + end + attribute \src "ls180.v:3845.161-3845.291" + cell $and $and$ls180.v:3845$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3845$298_Y + connect \B $not$ls180.v:3845$299_Y + connect \Y $and$ls180.v:3845$300_Y + end + attribute \src "ls180.v:3845.76-3845.333" + cell $and $and$ls180.v:3845$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3845$296_Y + connect \B $or$ls180.v:3845$302_Y + connect \Y $and$ls180.v:3845$303_Y + end + attribute \src "ls180.v:3845.338-3845.505" + cell $and $and$ls180.v:3845$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3845$304_Y + connect \B $eq$ls180.v:3845$305_Y + connect \Y $and$ls180.v:3845$306_Y + end + attribute \src "ls180.v:3845.38-3845.507" + cell $and $and$ls180.v:3845$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3845$307_Y + connect \Y $and$ls180.v:3845$308_Y + end + attribute \src "ls180.v:3846.77-3846.153" + cell $and $and$ls180.v:3846$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3846$309_Y + end + attribute \src "ls180.v:3846.162-3846.246" + cell $and $and$ls180.v:3846$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3846$310_Y + connect \Y $and$ls180.v:3846$311_Y + end + attribute \src "ls180.v:3846.161-3846.291" + cell $and $and$ls180.v:3846$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3846$311_Y + connect \B $not$ls180.v:3846$312_Y + connect \Y $and$ls180.v:3846$313_Y + end + attribute \src "ls180.v:3846.76-3846.333" + cell $and $and$ls180.v:3846$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3846$309_Y + connect \B $or$ls180.v:3846$315_Y + connect \Y $and$ls180.v:3846$316_Y + end + attribute \src "ls180.v:3846.338-3846.505" + cell $and $and$ls180.v:3846$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3846$317_Y + connect \B $eq$ls180.v:3846$318_Y + connect \Y $and$ls180.v:3846$319_Y + end + attribute \src "ls180.v:3846.38-3846.507" + cell $and $and$ls180.v:3846$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3846$320_Y + connect \Y $and$ls180.v:3846$321_Y + end + attribute \src "ls180.v:3847.77-3847.153" + cell $and $and$ls180.v:3847$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3847$322_Y + end + attribute \src "ls180.v:3847.162-3847.246" + cell $and $and$ls180.v:3847$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3847$323_Y + connect \Y $and$ls180.v:3847$324_Y + end + attribute \src "ls180.v:3847.161-3847.291" + cell $and $and$ls180.v:3847$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3847$324_Y + connect \B $not$ls180.v:3847$325_Y + connect \Y $and$ls180.v:3847$326_Y + end + attribute \src "ls180.v:3847.76-3847.333" + cell $and $and$ls180.v:3847$329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3847$322_Y + connect \B $or$ls180.v:3847$328_Y + connect \Y $and$ls180.v:3847$329_Y + end + attribute \src "ls180.v:3847.338-3847.505" + cell $and $and$ls180.v:3847$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3847$330_Y + connect \B $eq$ls180.v:3847$331_Y + connect \Y $and$ls180.v:3847$332_Y + end + attribute \src "ls180.v:3847.38-3847.507" + cell $and $and$ls180.v:3847$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3847$333_Y + connect \Y $and$ls180.v:3847$334_Y + end + attribute \src "ls180.v:3848.77-3848.153" + cell $and $and$ls180.v:3848$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:3848$335_Y + end + attribute \src "ls180.v:3848.162-3848.246" + cell $and $and$ls180.v:3848$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3848$336_Y + connect \Y $and$ls180.v:3848$337_Y + end + attribute \src "ls180.v:3848.161-3848.291" + cell $and $and$ls180.v:3848$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3848$337_Y + connect \B $not$ls180.v:3848$338_Y + connect \Y $and$ls180.v:3848$339_Y + end + attribute \src "ls180.v:3848.76-3848.333" + cell $and $and$ls180.v:3848$342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3848$335_Y + connect \B $or$ls180.v:3848$341_Y + connect \Y $and$ls180.v:3848$342_Y + end + attribute \src "ls180.v:3848.338-3848.505" + cell $and $and$ls180.v:3848$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3848$343_Y + connect \B $eq$ls180.v:3848$344_Y + connect \Y $and$ls180.v:3848$345_Y + end + attribute \src "ls180.v:3848.38-3848.507" + cell $and $and$ls180.v:3848$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3848$346_Y + connect \Y $and$ls180.v:3848$347_Y + end + attribute \src "ls180.v:3877.8-3877.73" + cell $and $and$ls180.v:3877$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3877$352_Y + end + attribute \src "ls180.v:3877.7-3877.114" + cell $and $and$ls180.v:3877$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3877$352_Y + connect \B $eq$ls180.v:3877$353_Y + connect \Y $and$ls180.v:3877$354_Y + end + attribute \src "ls180.v:3880.8-3880.73" + cell $and $and$ls180.v:3880$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3880$355_Y + end + attribute \src "ls180.v:3880.7-3880.114" + cell $and $and$ls180.v:3880$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3880$355_Y + connect \B $eq$ls180.v:3880$356_Y + connect \Y $and$ls180.v:3880$357_Y + end + attribute \src "ls180.v:3886.8-3886.73" + cell $and $and$ls180.v:3886$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3886$359_Y + end + attribute \src "ls180.v:3886.7-3886.114" + cell $and $and$ls180.v:3886$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3886$359_Y + connect \B $eq$ls180.v:3886$360_Y + connect \Y $and$ls180.v:3886$361_Y + end + attribute \src "ls180.v:3889.8-3889.73" + cell $and $and$ls180.v:3889$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3889$362_Y + end + attribute \src "ls180.v:3889.7-3889.114" + cell $and $and$ls180.v:3889$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3889$362_Y + connect \B $eq$ls180.v:3889$363_Y + connect \Y $and$ls180.v:3889$364_Y + end + attribute \src "ls180.v:3895.8-3895.73" + cell $and $and$ls180.v:3895$366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3895$366_Y + end + attribute \src "ls180.v:3895.7-3895.114" + cell $and $and$ls180.v:3895$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3895$366_Y + connect \B $eq$ls180.v:3895$367_Y + connect \Y $and$ls180.v:3895$368_Y + end + attribute \src "ls180.v:3898.8-3898.73" + cell $and $and$ls180.v:3898$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3898$369_Y + end + attribute \src "ls180.v:3898.7-3898.114" + cell $and $and$ls180.v:3898$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3898$369_Y + connect \B $eq$ls180.v:3898$370_Y + connect \Y $and$ls180.v:3898$371_Y + end + attribute \src "ls180.v:3904.8-3904.73" + cell $and $and$ls180.v:3904$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:3904$373_Y + end + attribute \src "ls180.v:3904.7-3904.114" + cell $and $and$ls180.v:3904$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3904$373_Y + connect \B $eq$ls180.v:3904$374_Y + connect \Y $and$ls180.v:3904$375_Y + end + attribute \src "ls180.v:3907.8-3907.73" + cell $and $and$ls180.v:3907$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3907$376_Y + end + attribute \src "ls180.v:3907.7-3907.114" + cell $and $and$ls180.v:3907$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3907$376_Y + connect \B $eq$ls180.v:3907$377_Y + connect \Y $and$ls180.v:3907$378_Y + end + attribute \src "ls180.v:3932.71-3932.151" + cell $and $and$ls180.v:3932$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3932$382_Y + connect \Y $and$ls180.v:3932$383_Y + end + attribute \src "ls180.v:3932.70-3932.194" + cell $and $and$ls180.v:3932$385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3932$383_Y + connect \B $not$ls180.v:3932$384_Y + connect \Y $and$ls180.v:3932$385_Y + end + attribute \src "ls180.v:3932.41-3932.222" + cell $and $and$ls180.v:3932$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3932$387_Y + connect \Y $and$ls180.v:3932$388_Y + end + attribute \src "ls180.v:3970.71-3970.151" + cell $and $and$ls180.v:3970$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3970$391_Y + connect \Y $and$ls180.v:3970$392_Y + end + attribute \src "ls180.v:3970.70-3970.194" + cell $and $and$ls180.v:3970$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3970$392_Y + connect \B $not$ls180.v:3970$393_Y + connect \Y $and$ls180.v:3970$394_Y + end + attribute \src "ls180.v:3970.41-3970.222" + cell $and $and$ls180.v:3970$397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:3970$396_Y + connect \Y $and$ls180.v:3970$397_Y + end + attribute \src "ls180.v:3988.110-3988.179" + cell $and $and$ls180.v:3988$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3988$401_Y + connect \Y $and$ls180.v:3988$402_Y + end + attribute \src "ls180.v:3988.185-3988.254" + cell $and $and$ls180.v:3988$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3988$404_Y + connect \Y $and$ls180.v:3988$405_Y + end + attribute \src "ls180.v:3988.260-3988.329" + cell $and $and$ls180.v:3988$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3988$407_Y + connect \Y $and$ls180.v:3988$408_Y + end + attribute \src "ls180.v:3988.41-3988.332" + cell $and $and$ls180.v:3988$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$400_Y + connect \B $not$ls180.v:3988$410_Y + connect \Y $and$ls180.v:3988$411_Y + end + attribute \src "ls180.v:3988.40-3988.355" + cell $and $and$ls180.v:3988$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$411_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3988$412_Y + end + attribute \src "ls180.v:3989.34-3989.106" + cell $and $and$ls180.v:3989$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3989$413_Y + connect \B $not$ls180.v:3989$414_Y + connect \Y $and$ls180.v:3989$415_Y + end + attribute \src "ls180.v:3993.110-3993.179" + cell $and $and$ls180.v:3993$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3993$417_Y + connect \Y $and$ls180.v:3993$418_Y + end + attribute \src "ls180.v:3993.185-3993.254" + cell $and $and$ls180.v:3993$421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:3993$420_Y + connect \Y $and$ls180.v:3993$421_Y + end + attribute \src "ls180.v:3993.260-3993.329" + cell $and $and$ls180.v:3993$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3993$423_Y + connect \Y $and$ls180.v:3993$424_Y + end + attribute \src "ls180.v:3993.41-3993.332" + cell $and $and$ls180.v:3993$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3993$416_Y + connect \B $not$ls180.v:3993$426_Y + connect \Y $and$ls180.v:3993$427_Y + end + attribute \src "ls180.v:3993.40-3993.355" + cell $and $and$ls180.v:3993$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3993$427_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3993$428_Y + end + attribute \src "ls180.v:3994.34-3994.106" + cell $and $and$ls180.v:3994$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3994$429_Y + connect \B $not$ls180.v:3994$430_Y + connect \Y $and$ls180.v:3994$431_Y + end + attribute \src "ls180.v:3998.110-3998.179" + cell $and $and$ls180.v:3998$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:3998$433_Y + connect \Y $and$ls180.v:3998$434_Y + end + attribute \src "ls180.v:3998.185-3998.254" + cell $and $and$ls180.v:3998$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:3998$436_Y + connect \Y $and$ls180.v:3998$437_Y + end + attribute \src "ls180.v:3998.260-3998.329" + cell $and $and$ls180.v:3998$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:3998$439_Y + connect \Y $and$ls180.v:3998$440_Y + end + attribute \src "ls180.v:3998.41-3998.332" + cell $and $and$ls180.v:3998$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3998$432_Y + connect \B $not$ls180.v:3998$442_Y + connect \Y $and$ls180.v:3998$443_Y + end + attribute \src "ls180.v:3998.40-3998.355" + cell $and $and$ls180.v:3998$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3998$443_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:3998$444_Y + end + attribute \src "ls180.v:3999.34-3999.106" + cell $and $and$ls180.v:3999$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3999$445_Y + connect \B $not$ls180.v:3999$446_Y + connect \Y $and$ls180.v:3999$447_Y + end + attribute \src "ls180.v:4003.110-4003.179" + cell $and $and$ls180.v:4003$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4003$449_Y + connect \Y $and$ls180.v:4003$450_Y + end + attribute \src "ls180.v:4003.185-4003.254" + cell $and $and$ls180.v:4003$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4003$452_Y + connect \Y $and$ls180.v:4003$453_Y + end + attribute \src "ls180.v:4003.260-4003.329" + cell $and $and$ls180.v:4003$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4003$455_Y + connect \Y $and$ls180.v:4003$456_Y + end + attribute \src "ls180.v:4003.41-4003.332" + cell $and $and$ls180.v:4003$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4003$448_Y + connect \B $not$ls180.v:4003$458_Y + connect \Y $and$ls180.v:4003$459_Y + end + attribute \src "ls180.v:4003.40-4003.355" + cell $and $and$ls180.v:4003$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4003$459_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4003$460_Y + end + attribute \src "ls180.v:4004.34-4004.106" + cell $and $and$ls180.v:4004$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4004$461_Y + connect \B $not$ls180.v:4004$462_Y + connect \Y $and$ls180.v:4004$463_Y + end + attribute \src "ls180.v:4008.151-4008.220" + cell $and $and$ls180.v:4008$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4008$466_Y + connect \Y $and$ls180.v:4008$467_Y + end + attribute \src "ls180.v:4008.226-4008.295" + cell $and $and$ls180.v:4008$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4008$469_Y + connect \Y $and$ls180.v:4008$470_Y + end + attribute \src "ls180.v:4008.301-4008.370" + cell $and $and$ls180.v:4008$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4008$472_Y + connect \Y $and$ls180.v:4008$473_Y + end + attribute \src "ls180.v:4008.82-4008.373" + cell $and $and$ls180.v:4008$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$465_Y + connect \B $not$ls180.v:4008$475_Y + connect \Y $and$ls180.v:4008$476_Y + end + attribute \src "ls180.v:4008.43-4008.374" + cell $and $and$ls180.v:4008$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$464_Y + connect \B $and$ls180.v:4008$476_Y + connect \Y $and$ls180.v:4008$477_Y + end + attribute \src "ls180.v:4008.42-4008.410" + cell $and $and$ls180.v:4008$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4008$477_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:4008$478_Y + end + attribute \src "ls180.v:4008.525-4008.594" + cell $and $and$ls180.v:4008$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4008$482_Y + connect \Y $and$ls180.v:4008$483_Y + end + attribute \src "ls180.v:4008.600-4008.669" + cell $and $and$ls180.v:4008$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4008$485_Y + connect \Y $and$ls180.v:4008$486_Y + end + attribute \src "ls180.v:4008.675-4008.744" + cell $and $and$ls180.v:4008$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4008$488_Y + connect \Y $and$ls180.v:4008$489_Y + end + attribute \src "ls180.v:4008.456-4008.747" + cell $and $and$ls180.v:4008$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$481_Y + connect \B $not$ls180.v:4008$491_Y + connect \Y $and$ls180.v:4008$492_Y + end + attribute \src "ls180.v:4008.417-4008.748" + cell $and $and$ls180.v:4008$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$480_Y + connect \B $and$ls180.v:4008$492_Y + connect \Y $and$ls180.v:4008$493_Y + end + attribute \src "ls180.v:4008.416-4008.784" + cell $and $and$ls180.v:4008$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4008$493_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:4008$494_Y + end + attribute \src "ls180.v:4008.899-4008.968" + cell $and $and$ls180.v:4008$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4008$498_Y + connect \Y $and$ls180.v:4008$499_Y + end + attribute \src "ls180.v:4008.974-4008.1043" + cell $and $and$ls180.v:4008$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4008$501_Y + connect \Y $and$ls180.v:4008$502_Y + end + attribute \src "ls180.v:4008.1049-4008.1118" + cell $and $and$ls180.v:4008$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4008$504_Y + connect \Y $and$ls180.v:4008$505_Y + end + attribute \src "ls180.v:4008.830-4008.1121" + cell $and $and$ls180.v:4008$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$497_Y + connect \B $not$ls180.v:4008$507_Y + connect \Y $and$ls180.v:4008$508_Y + end + attribute \src "ls180.v:4008.791-4008.1122" + cell $and $and$ls180.v:4008$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$496_Y + connect \B $and$ls180.v:4008$508_Y + connect \Y $and$ls180.v:4008$509_Y + end + attribute \src "ls180.v:4008.790-4008.1158" + cell $and $and$ls180.v:4008$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4008$509_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:4008$510_Y + end + attribute \src "ls180.v:4008.1273-4008.1342" + cell $and $and$ls180.v:4008$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4008$514_Y + connect \Y $and$ls180.v:4008$515_Y + end + attribute \src "ls180.v:4008.1348-4008.1417" + cell $and $and$ls180.v:4008$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4008$517_Y + connect \Y $and$ls180.v:4008$518_Y + end + attribute \src "ls180.v:4008.1423-4008.1492" + cell $and $and$ls180.v:4008$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4008$520_Y + connect \Y $and$ls180.v:4008$521_Y + end + attribute \src "ls180.v:4008.1204-4008.1495" + cell $and $and$ls180.v:4008$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$513_Y + connect \B $not$ls180.v:4008$523_Y + connect \Y $and$ls180.v:4008$524_Y + end + attribute \src "ls180.v:4008.1165-4008.1496" + cell $and $and$ls180.v:4008$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4008$512_Y + connect \B $and$ls180.v:4008$524_Y + connect \Y $and$ls180.v:4008$525_Y + end + attribute \src "ls180.v:4008.1164-4008.1532" + cell $and $and$ls180.v:4008$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4008$525_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:4008$526_Y + end + attribute \src "ls180.v:4066.9-4066.46" + cell $and $and$ls180.v:4066$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4066$532_Y + end + attribute \src "ls180.v:4084.9-4084.46" + cell $and $and$ls180.v:4084$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4084$539_Y + end + attribute \src "ls180.v:4097.32-4097.75" + cell $and $and$ls180.v:4097$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4097$543_Y + end + attribute \src "ls180.v:4097.31-4097.99" + cell $and $and$ls180.v:4097$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4097$543_Y + connect \B $not$ls180.v:4097$544_Y + connect \Y $and$ls180.v:4097$545_Y + end + attribute \src "ls180.v:4098.34-4098.102" + cell $and $and$ls180.v:4098$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4098$546_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4098$547_Y + end + attribute \src "ls180.v:4098.33-4098.128" + cell $and $and$ls180.v:4098$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4098$547_Y + connect \B $not$ls180.v:4098$548_Y + connect \Y $and$ls180.v:4098$549_Y + end + attribute \src "ls180.v:4099.33-4099.104" + cell $and $and$ls180.v:4099$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4099$550_Y + connect \B $not$ls180.v:4099$551_Y + connect \Y $and$ls180.v:4099$552_Y + end + attribute \src "ls180.v:4100.49-4100.85" + cell $and $and$ls180.v:4100$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4100$553_Y + end + attribute \src "ls180.v:4100.90-4100.129" + cell $and $and$ls180.v:4100$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4100$554_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4100$555_Y + end + attribute \src "ls180.v:4100.32-4100.131" + cell $and $and$ls180.v:4100$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4100$556_Y + connect \Y $and$ls180.v:4100$557_Y + end + attribute \src "ls180.v:4101.25-4101.66" + cell $and $and$ls180.v:4101$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4101$558_Y + end + attribute \src "ls180.v:4102.27-4102.72" + cell $and $and$ls180.v:4102$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4102$560_Y + end + attribute \src "ls180.v:4103.26-4103.71" + cell $and $and$ls180.v:4103$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4103$562_Y + end + attribute \src "ls180.v:4132.64-4132.88" + cell $and $and$ls180.v:4132$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4132$568_Y + end + attribute \src "ls180.v:4136.7-4136.78" + cell $and $and$ls180.v:4136$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4136$572_Y + end + attribute \src "ls180.v:4147.7-4147.78" + cell $and $and$ls180.v:4147$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4147$575_Y + end + attribute \src "ls180.v:4156.26-4156.97" + cell $and $and$ls180.v:4156$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4156$577_Y + end + attribute \src "ls180.v:4156.102-4156.173" + cell $and $and$ls180.v:4156$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4156$578_Y + end + attribute \src "ls180.v:4171.41-4171.133" + cell $and $and$ls180.v:4171$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4171$581_Y + connect \Y $and$ls180.v:4171$582_Y + end + attribute \src "ls180.v:4182.39-4182.136" + cell $and $and$ls180.v:4182$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4182$586_Y + connect \Y $and$ls180.v:4182$587_Y + end + attribute \src "ls180.v:4183.37-4183.104" + cell $and $and$ls180.v:4183$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4183$588_Y + end + attribute \src "ls180.v:4201.41-4201.133" + cell $and $and$ls180.v:4201$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4201$592_Y + connect \Y $and$ls180.v:4201$593_Y + end + attribute \src "ls180.v:4212.39-4212.136" + cell $and $and$ls180.v:4212$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4212$597_Y + connect \Y $and$ls180.v:4212$598_Y + end + attribute \src "ls180.v:4213.37-4213.104" + cell $and $and$ls180.v:4213$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4213$599_Y + end + attribute \src "ls180.v:4401.33-4401.86" + cell $and $and$ls180.v:4401$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4401$640_Y + connect \Y $and$ls180.v:4401$641_Y + end + attribute \src "ls180.v:4505.9-4505.68" + cell $and $and$ls180.v:4505$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4505$650_Y + end + attribute \src "ls180.v:4525.53-4525.145" + cell $and $and$ls180.v:4525$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4525$652_Y + connect \Y $and$ls180.v:4525$653_Y + end + attribute \src "ls180.v:4544.52-4544.137" + cell $and $and$ls180.v:4544$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4544$656_Y + end + attribute \src "ls180.v:4585.9-4585.68" + cell $and $and$ls180.v:4585$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4585$664_Y + end + attribute \src "ls180.v:4623.9-4623.68" + cell $and $and$ls180.v:4623$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4623$670_Y + end + attribute \src "ls180.v:4632.10-4632.69" + cell $and $and$ls180.v:4632$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4632$671_Y + end + attribute \src "ls180.v:4632.9-4632.93" + cell $and $and$ls180.v:4632$672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4632$671_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4632$672_Y + end + attribute \src "ls180.v:4652.54-4652.117" + cell $and $and$ls180.v:4652$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4652$674_Y + end + attribute \src "ls180.v:4671.53-4671.140" + cell $and $and$ls180.v:4671$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4671$677_Y + end + attribute \src "ls180.v:4768.9-4768.70" + cell $and $and$ls180.v:4768$687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4768$687_Y + end + attribute \src "ls180.v:4786.55-4786.120" + cell $and $and$ls180.v:4786$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4786$689_Y + end + attribute \src "ls180.v:4805.54-4805.143" + cell $and $and$ls180.v:4805$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4805$692_Y + end + attribute \src "ls180.v:4887.9-4887.70" + cell $and $and$ls180.v:4887$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:4887$707_Y + end + attribute \src "ls180.v:4894.9-4894.70" + cell $and $and$ls180.v:4894$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:4894$708_Y + end + attribute \src "ls180.v:4975.48-4975.124" + cell $and $and$ls180.v:4975$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4975$831_Y + end + attribute \src "ls180.v:4975.47-4975.165" + cell $and $and$ls180.v:4975$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4975$831_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4975$832_Y + end + attribute \src "ls180.v:4976.50-4976.127" + cell $and $and$ls180.v:4976$833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4976$833_Y + end + attribute \src "ls180.v:4978.48-4978.124" + cell $and $and$ls180.v:4978$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4978$834_Y + end + attribute \src "ls180.v:4978.47-4978.165" + cell $and $and$ls180.v:4978$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4978$834_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4978$835_Y + end + attribute \src "ls180.v:4979.50-4979.127" + cell $and $and$ls180.v:4979$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4979$836_Y + end + attribute \src "ls180.v:4981.48-4981.124" + cell $and $and$ls180.v:4981$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4981$837_Y + end + attribute \src "ls180.v:4981.47-4981.165" + cell $and $and$ls180.v:4981$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4981$837_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4981$838_Y + end + attribute \src "ls180.v:4982.50-4982.127" + cell $and $and$ls180.v:4982$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4982$839_Y + end + attribute \src "ls180.v:4984.48-4984.124" + cell $and $and$ls180.v:4984$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:4984$840_Y + end + attribute \src "ls180.v:4984.47-4984.165" + cell $and $and$ls180.v:4984$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4984$840_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4984$841_Y + end + attribute \src "ls180.v:4985.50-4985.127" + cell $and $and$ls180.v:4985$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:4985$842_Y + end + attribute \src "ls180.v:5098.10-5098.86" + cell $and $and$ls180.v:5098$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:5098$891_Y + end + attribute \src "ls180.v:5098.9-5098.127" + cell $and $and$ls180.v:5098$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5098$891_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5098$892_Y + end + attribute \src "ls180.v:5108.9-5108.152" + cell $and $and$ls180.v:5108$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:5108$894_Y + connect \B $eq$ls180.v:5108$895_Y + connect \Y $and$ls180.v:5108$896_Y + end + attribute \src "ls180.v:5108.8-5108.226" + cell $and $and$ls180.v:5108$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5108$896_Y + connect \B $eq$ls180.v:5108$897_Y + connect \Y $and$ls180.v:5108$898_Y + end + attribute \src "ls180.v:5108.7-5108.300" + cell $and $and$ls180.v:5108$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5108$898_Y + connect \B $eq$ls180.v:5108$899_Y + connect \Y $and$ls180.v:5108$900_Y + end + attribute \src "ls180.v:5113.49-5113.124" + cell $and $and$ls180.v:5113$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5113$901_Y + end + attribute \src "ls180.v:5123.49-5123.124" + cell $and $and$ls180.v:5123$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5123$904_Y + end + attribute \src "ls180.v:5133.49-5133.124" + cell $and $and$ls180.v:5133$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5133$907_Y + end + attribute \src "ls180.v:5143.49-5143.124" + cell $and $and$ls180.v:5143$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5143$910_Y + end + attribute \src "ls180.v:5155.7-5155.84" + cell $and $and$ls180.v:5155$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5155$914_Y + connect \Y $and$ls180.v:5155$915_Y + end + attribute \src "ls180.v:5273.9-5273.64" + cell $and $and$ls180.v:5273$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5273$964_Y + end + attribute \src "ls180.v:5325.10-5325.66" + cell $and $and$ls180.v:5325$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5325$973_Y + end + attribute \src "ls180.v:5325.9-5325.97" + cell $and $and$ls180.v:5325$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5325$973_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5325$974_Y + end + attribute \src "ls180.v:5351.11-5351.71" + cell $and $and$ls180.v:5351$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5351$982_Y + end + attribute \src "ls180.v:5435.43-5435.152" + cell $and $and$ls180.v:5435$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5435$989_Y + connect \Y $and$ls180.v:5435$990_Y + end + attribute \src "ls180.v:5436.41-5436.116" + cell $and $and$ls180.v:5436$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5436$991_Y + end + attribute \src "ls180.v:5448.48-5448.125" + cell $and $and$ls180.v:5448$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5448$996_Y + end + attribute \src "ls180.v:5475.9-5475.102" + cell $and $and$ls180.v:5475$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5475$1000_Y + end + attribute \src "ls180.v:5548.9-5548.58" + cell $and $and$ls180.v:5548$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5548$1006_Y + end + attribute \src "ls180.v:5601.51-5601.123" + cell $and $and$ls180.v:5601$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5601$1014_Y + end + attribute \src "ls180.v:5602.50-5602.120" + cell $and $and$ls180.v:5602$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5602$1015_Y + end + attribute \src "ls180.v:5603.49-5603.122" + cell $and $and$ls180.v:5603$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5603$1016_Y + end + attribute \src "ls180.v:5643.43-5643.152" + cell $and $and$ls180.v:5643$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5643$1020_Y + connect \Y $and$ls180.v:5643$1021_Y + end + attribute \src "ls180.v:5644.41-5644.116" + cell $and $and$ls180.v:5644$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5644$1022_Y + end + attribute \src "ls180.v:5676.9-5676.76" + cell $and $and$ls180.v:5676$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5676$1026_Y + end + attribute \src "ls180.v:5679.44-5679.120" + cell $and $and$ls180.v:5679$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5679$1027_Y + connect \Y $and$ls180.v:5679$1028_Y + end + attribute \src "ls180.v:5699.63-5699.107" + cell $and $and$ls180.v:5699$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5699$1029_Y + connect \Y $and$ls180.v:5699$1030_Y + end + attribute \src "ls180.v:5700.63-5700.107" + cell $and $and$ls180.v:5700$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5700$1031_Y + connect \Y $and$ls180.v:5700$1032_Y + end + attribute \src "ls180.v:5701.63-5701.107" + cell $and $and$ls180.v:5701$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5701$1033_Y + connect \Y $and$ls180.v:5701$1034_Y + end + attribute \src "ls180.v:5702.35-5702.79" + cell $and $and$ls180.v:5702$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5702$1035_Y + connect \Y $and$ls180.v:5702$1036_Y + end + attribute \src "ls180.v:5703.35-5703.79" + cell $and $and$ls180.v:5703$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5703$1037_Y + connect \Y $and$ls180.v:5703$1038_Y + end + attribute \src "ls180.v:5704.63-5704.107" + cell $and $and$ls180.v:5704$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5704$1039_Y + connect \Y $and$ls180.v:5704$1040_Y + end + attribute \src "ls180.v:5705.63-5705.107" + cell $and $and$ls180.v:5705$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5705$1041_Y + connect \Y $and$ls180.v:5705$1042_Y + end + attribute \src "ls180.v:5706.63-5706.107" + cell $and $and$ls180.v:5706$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5706$1043_Y + connect \Y $and$ls180.v:5706$1044_Y + end + attribute \src "ls180.v:5707.35-5707.79" + cell $and $and$ls180.v:5707$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5707$1045_Y + connect \Y $and$ls180.v:5707$1046_Y + end + attribute \src "ls180.v:5708.35-5708.79" + cell $and $and$ls180.v:5708$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5708$1047_Y + connect \Y $and$ls180.v:5708$1048_Y + end + attribute \src "ls180.v:5753.40-5753.81" + cell $and $and$ls180.v:5753$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:5753$1055_Y + end + attribute \src "ls180.v:5754.50-5754.91" + cell $and $and$ls180.v:5754$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:5754$1056_Y + end + attribute \src "ls180.v:5755.50-5755.91" + cell $and $and$ls180.v:5755$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:5755$1057_Y + end + attribute \src "ls180.v:5756.29-5756.70" + cell $and $and$ls180.v:5756$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:5756$1058_Y + end + attribute \src "ls180.v:5757.44-5757.85" + cell $and $and$ls180.v:5757$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:5757$1059_Y + end + attribute \src "ls180.v:5759.25-5759.64" + cell $and $and$ls180.v:5759$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:5759$1064_Y + end + attribute \src "ls180.v:5759.24-5759.89" + cell $and $and$ls180.v:5759$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5759$1064_Y + connect \B $not$ls180.v:5759$1065_Y + connect \Y $and$ls180.v:5759$1066_Y + end + attribute \src "ls180.v:5765.31-5765.92" + cell $and $and$ls180.v:5765$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:5765$1072_Y + end + attribute \src "ls180.v:5765.97-5765.168" + cell $and $and$ls180.v:5765$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_libresocsim_libresoc_xics_icp_dat_r + connect \Y $and$ls180.v:5765$1073_Y + end + attribute \src "ls180.v:5765.174-5765.245" + cell $and $and$ls180.v:5765$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_libresocsim_libresoc_xics_ics_dat_r + connect \Y $and$ls180.v:5765$1075_Y + end + attribute \src "ls180.v:5765.251-5765.301" + cell $and $and$ls180.v:5765$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_wb_sdram_dat_r + connect \Y $and$ls180.v:5765$1077_Y + end + attribute \src "ls180.v:5765.307-5765.372" + cell $and $and$ls180.v:5765$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \builder_libresocsim_wishbone_dat_r + connect \Y $and$ls180.v:5765$1079_Y + end + attribute \src "ls180.v:5775.39-5775.92" + cell $and $and$ls180.v:5775$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5775$1083_Y + end + attribute \src "ls180.v:5775.38-5775.142" + cell $and $and$ls180.v:5775$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5775$1083_Y + connect \B $eq$ls180.v:5775$1084_Y + connect \Y $and$ls180.v:5775$1085_Y + end + attribute \src "ls180.v:5776.39-5776.95" + cell $and $and$ls180.v:5776$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5776$1086_Y + connect \Y $and$ls180.v:5776$1087_Y + end + attribute \src "ls180.v:5776.38-5776.145" + cell $and $and$ls180.v:5776$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5776$1087_Y + connect \B $eq$ls180.v:5776$1088_Y + connect \Y $and$ls180.v:5776$1089_Y + end + attribute \src "ls180.v:5778.41-5778.94" + cell $and $and$ls180.v:5778$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5778$1090_Y + end + attribute \src "ls180.v:5778.40-5778.144" + cell $and $and$ls180.v:5778$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5778$1090_Y + connect \B $eq$ls180.v:5778$1091_Y + connect \Y $and$ls180.v:5778$1092_Y + end + attribute \src "ls180.v:5779.41-5779.97" + cell $and $and$ls180.v:5779$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5779$1093_Y + connect \Y $and$ls180.v:5779$1094_Y + end + attribute \src "ls180.v:5779.40-5779.147" + cell $and $and$ls180.v:5779$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5779$1094_Y + connect \B $eq$ls180.v:5779$1095_Y + connect \Y $and$ls180.v:5779$1096_Y + end + attribute \src "ls180.v:5781.41-5781.94" + cell $and $and$ls180.v:5781$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5781$1097_Y + end + attribute \src "ls180.v:5781.40-5781.144" + cell $and $and$ls180.v:5781$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5781$1097_Y + connect \B $eq$ls180.v:5781$1098_Y + connect \Y $and$ls180.v:5781$1099_Y + end + attribute \src "ls180.v:5782.41-5782.97" + cell $and $and$ls180.v:5782$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5782$1100_Y + connect \Y $and$ls180.v:5782$1101_Y + end + attribute \src "ls180.v:5782.40-5782.147" + cell $and $and$ls180.v:5782$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5782$1101_Y + connect \B $eq$ls180.v:5782$1102_Y + connect \Y $and$ls180.v:5782$1103_Y + end + attribute \src "ls180.v:5784.41-5784.94" + cell $and $and$ls180.v:5784$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5784$1104_Y + end + attribute \src "ls180.v:5784.40-5784.144" + cell $and $and$ls180.v:5784$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5784$1104_Y + connect \B $eq$ls180.v:5784$1105_Y + connect \Y $and$ls180.v:5784$1106_Y + end + attribute \src "ls180.v:5785.41-5785.97" + cell $and $and$ls180.v:5785$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5785$1107_Y + connect \Y $and$ls180.v:5785$1108_Y + end + attribute \src "ls180.v:5785.40-5785.147" + cell $and $and$ls180.v:5785$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5785$1108_Y + connect \B $eq$ls180.v:5785$1109_Y + connect \Y $and$ls180.v:5785$1110_Y + end + attribute \src "ls180.v:5787.41-5787.94" + cell $and $and$ls180.v:5787$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5787$1111_Y + end + attribute \src "ls180.v:5787.40-5787.144" + cell $and $and$ls180.v:5787$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5787$1111_Y + connect \B $eq$ls180.v:5787$1112_Y + connect \Y $and$ls180.v:5787$1113_Y + end + attribute \src "ls180.v:5788.41-5788.97" + cell $and $and$ls180.v:5788$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5788$1114_Y + connect \Y $and$ls180.v:5788$1115_Y + end + attribute \src "ls180.v:5788.40-5788.147" + cell $and $and$ls180.v:5788$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5788$1115_Y + connect \B $eq$ls180.v:5788$1116_Y + connect \Y $and$ls180.v:5788$1117_Y + end + attribute \src "ls180.v:5790.44-5790.97" + cell $and $and$ls180.v:5790$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5790$1118_Y + end + attribute \src "ls180.v:5790.43-5790.147" + cell $and $and$ls180.v:5790$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5790$1118_Y + connect \B $eq$ls180.v:5790$1119_Y + connect \Y $and$ls180.v:5790$1120_Y + end + attribute \src "ls180.v:5791.44-5791.100" + cell $and $and$ls180.v:5791$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5791$1121_Y + connect \Y $and$ls180.v:5791$1122_Y + end + attribute \src "ls180.v:5791.43-5791.150" + cell $and $and$ls180.v:5791$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5791$1122_Y + connect \B $eq$ls180.v:5791$1123_Y + connect \Y $and$ls180.v:5791$1124_Y + end + attribute \src "ls180.v:5793.44-5793.97" + cell $and $and$ls180.v:5793$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5793$1125_Y + end + attribute \src "ls180.v:5793.43-5793.147" + cell $and $and$ls180.v:5793$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5793$1125_Y + connect \B $eq$ls180.v:5793$1126_Y + connect \Y $and$ls180.v:5793$1127_Y + end + attribute \src "ls180.v:5794.44-5794.100" + cell $and $and$ls180.v:5794$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5794$1128_Y + connect \Y $and$ls180.v:5794$1129_Y + end + attribute \src "ls180.v:5794.43-5794.150" + cell $and $and$ls180.v:5794$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5794$1129_Y + connect \B $eq$ls180.v:5794$1130_Y + connect \Y $and$ls180.v:5794$1131_Y + end + attribute \src "ls180.v:5796.44-5796.97" + cell $and $and$ls180.v:5796$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5796$1132_Y + end + attribute \src "ls180.v:5796.43-5796.147" + cell $and $and$ls180.v:5796$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5796$1132_Y + connect \B $eq$ls180.v:5796$1133_Y + connect \Y $and$ls180.v:5796$1134_Y + end + attribute \src "ls180.v:5797.44-5797.100" + cell $and $and$ls180.v:5797$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5797$1135_Y + connect \Y $and$ls180.v:5797$1136_Y + end + attribute \src "ls180.v:5797.43-5797.150" + cell $and $and$ls180.v:5797$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5797$1136_Y + connect \B $eq$ls180.v:5797$1137_Y + connect \Y $and$ls180.v:5797$1138_Y + end + attribute \src "ls180.v:5799.44-5799.97" + cell $and $and$ls180.v:5799$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:5799$1139_Y + end + attribute \src "ls180.v:5799.43-5799.147" + cell $and $and$ls180.v:5799$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5799$1139_Y + connect \B $eq$ls180.v:5799$1140_Y + connect \Y $and$ls180.v:5799$1141_Y + end + attribute \src "ls180.v:5800.44-5800.100" + cell $and $and$ls180.v:5800$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:5800$1142_Y + connect \Y $and$ls180.v:5800$1143_Y + end + attribute \src "ls180.v:5800.43-5800.150" + cell $and $and$ls180.v:5800$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5800$1143_Y + connect \B $eq$ls180.v:5800$1144_Y + connect \Y $and$ls180.v:5800$1145_Y + end + attribute \src "ls180.v:5813.36-5813.89" + cell $and $and$ls180.v:5813$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5813$1147_Y + end + attribute \src "ls180.v:5813.35-5813.139" + cell $and $and$ls180.v:5813$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5813$1147_Y + connect \B $eq$ls180.v:5813$1148_Y + connect \Y $and$ls180.v:5813$1149_Y + end + attribute \src "ls180.v:5814.36-5814.92" + cell $and $and$ls180.v:5814$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5814$1150_Y + connect \Y $and$ls180.v:5814$1151_Y + end + attribute \src "ls180.v:5814.35-5814.142" + cell $and $and$ls180.v:5814$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5814$1151_Y + connect \B $eq$ls180.v:5814$1152_Y + connect \Y $and$ls180.v:5814$1153_Y + end + attribute \src "ls180.v:5816.36-5816.89" + cell $and $and$ls180.v:5816$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5816$1154_Y + end + attribute \src "ls180.v:5816.35-5816.139" + cell $and $and$ls180.v:5816$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5816$1154_Y + connect \B $eq$ls180.v:5816$1155_Y + connect \Y $and$ls180.v:5816$1156_Y + end + attribute \src "ls180.v:5817.36-5817.92" + cell $and $and$ls180.v:5817$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5817$1157_Y + connect \Y $and$ls180.v:5817$1158_Y + end + attribute \src "ls180.v:5817.35-5817.142" + cell $and $and$ls180.v:5817$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5817$1158_Y + connect \B $eq$ls180.v:5817$1159_Y + connect \Y $and$ls180.v:5817$1160_Y + end + attribute \src "ls180.v:5819.36-5819.89" + cell $and $and$ls180.v:5819$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5819$1161_Y + end + attribute \src "ls180.v:5819.35-5819.139" + cell $and $and$ls180.v:5819$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5819$1161_Y + connect \B $eq$ls180.v:5819$1162_Y + connect \Y $and$ls180.v:5819$1163_Y + end + attribute \src "ls180.v:5820.36-5820.92" + cell $and $and$ls180.v:5820$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5820$1164_Y + connect \Y $and$ls180.v:5820$1165_Y + end + attribute \src "ls180.v:5820.35-5820.142" + cell $and $and$ls180.v:5820$1167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5820$1165_Y + connect \B $eq$ls180.v:5820$1166_Y + connect \Y $and$ls180.v:5820$1167_Y + end + attribute \src "ls180.v:5822.36-5822.89" + cell $and $and$ls180.v:5822$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5822$1168_Y + end + attribute \src "ls180.v:5822.35-5822.139" + cell $and $and$ls180.v:5822$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5822$1168_Y + connect \B $eq$ls180.v:5822$1169_Y + connect \Y $and$ls180.v:5822$1170_Y + end + attribute \src "ls180.v:5823.36-5823.92" + cell $and $and$ls180.v:5823$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5823$1171_Y + connect \Y $and$ls180.v:5823$1172_Y + end + attribute \src "ls180.v:5823.35-5823.142" + cell $and $and$ls180.v:5823$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5823$1172_Y + connect \B $eq$ls180.v:5823$1173_Y + connect \Y $and$ls180.v:5823$1174_Y + end + attribute \src "ls180.v:5825.37-5825.90" + cell $and $and$ls180.v:5825$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5825$1175_Y + end + attribute \src "ls180.v:5825.36-5825.140" + cell $and $and$ls180.v:5825$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5825$1175_Y + connect \B $eq$ls180.v:5825$1176_Y + connect \Y $and$ls180.v:5825$1177_Y + end + attribute \src "ls180.v:5826.37-5826.93" + cell $and $and$ls180.v:5826$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5826$1178_Y + connect \Y $and$ls180.v:5826$1179_Y + end + attribute \src "ls180.v:5826.36-5826.143" + cell $and $and$ls180.v:5826$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5826$1179_Y + connect \B $eq$ls180.v:5826$1180_Y + connect \Y $and$ls180.v:5826$1181_Y + end + attribute \src "ls180.v:5828.37-5828.90" + cell $and $and$ls180.v:5828$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:5828$1182_Y + end + attribute \src "ls180.v:5828.36-5828.140" + cell $and $and$ls180.v:5828$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5828$1182_Y + connect \B $eq$ls180.v:5828$1183_Y + connect \Y $and$ls180.v:5828$1184_Y + end + attribute \src "ls180.v:5829.37-5829.93" + cell $and $and$ls180.v:5829$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:5829$1185_Y + connect \Y $and$ls180.v:5829$1186_Y + end + attribute \src "ls180.v:5829.36-5829.143" + cell $and $and$ls180.v:5829$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5829$1186_Y + connect \B $eq$ls180.v:5829$1187_Y + connect \Y $and$ls180.v:5829$1188_Y + end + attribute \src "ls180.v:5839.35-5839.88" + cell $and $and$ls180.v:5839$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5839$1190_Y + end + attribute \src "ls180.v:5839.34-5839.136" + cell $and $and$ls180.v:5839$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5839$1190_Y + connect \B $eq$ls180.v:5839$1191_Y + connect \Y $and$ls180.v:5839$1192_Y + end + attribute \src "ls180.v:5840.35-5840.91" + cell $and $and$ls180.v:5840$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5840$1193_Y + connect \Y $and$ls180.v:5840$1194_Y + end + attribute \src "ls180.v:5840.34-5840.139" + cell $and $and$ls180.v:5840$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5840$1194_Y + connect \B $eq$ls180.v:5840$1195_Y + connect \Y $and$ls180.v:5840$1196_Y + end + attribute \src "ls180.v:5842.34-5842.87" + cell $and $and$ls180.v:5842$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:5842$1197_Y + end + attribute \src "ls180.v:5842.33-5842.135" + cell $and $and$ls180.v:5842$1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5842$1197_Y + connect \B $eq$ls180.v:5842$1198_Y + connect \Y $and$ls180.v:5842$1199_Y + end + attribute \src "ls180.v:5843.34-5843.90" + cell $and $and$ls180.v:5843$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:5843$1200_Y + connect \Y $and$ls180.v:5843$1201_Y + end + attribute \src "ls180.v:5843.33-5843.138" + cell $and $and$ls180.v:5843$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5843$1201_Y + connect \B $eq$ls180.v:5843$1202_Y + connect \Y $and$ls180.v:5843$1203_Y + end + attribute \src "ls180.v:5853.40-5853.93" + cell $and $and$ls180.v:5853$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5853$1205_Y + end + attribute \src "ls180.v:5853.39-5853.143" + cell $and $and$ls180.v:5853$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5853$1205_Y + connect \B $eq$ls180.v:5853$1206_Y + connect \Y $and$ls180.v:5853$1207_Y + end + attribute \src "ls180.v:5854.40-5854.96" + cell $and $and$ls180.v:5854$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5854$1208_Y + connect \Y $and$ls180.v:5854$1209_Y + end + attribute \src "ls180.v:5854.39-5854.146" + cell $and $and$ls180.v:5854$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5854$1209_Y + connect \B $eq$ls180.v:5854$1210_Y + connect \Y $and$ls180.v:5854$1211_Y + end + attribute \src "ls180.v:5856.39-5856.92" + cell $and $and$ls180.v:5856$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5856$1212_Y + end + attribute \src "ls180.v:5856.38-5856.142" + cell $and $and$ls180.v:5856$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5856$1212_Y + connect \B $eq$ls180.v:5856$1213_Y + connect \Y $and$ls180.v:5856$1214_Y + end + attribute \src "ls180.v:5857.39-5857.95" + cell $and $and$ls180.v:5857$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5857$1215_Y + connect \Y $and$ls180.v:5857$1216_Y + end + attribute \src "ls180.v:5857.38-5857.145" + cell $and $and$ls180.v:5857$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5857$1216_Y + connect \B $eq$ls180.v:5857$1217_Y + connect \Y $and$ls180.v:5857$1218_Y + end + attribute \src "ls180.v:5859.39-5859.92" + cell $and $and$ls180.v:5859$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5859$1219_Y + end + attribute \src "ls180.v:5859.38-5859.142" + cell $and $and$ls180.v:5859$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5859$1219_Y + connect \B $eq$ls180.v:5859$1220_Y + connect \Y $and$ls180.v:5859$1221_Y + end + attribute \src "ls180.v:5860.39-5860.95" + cell $and $and$ls180.v:5860$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5860$1222_Y + connect \Y $and$ls180.v:5860$1223_Y + end + attribute \src "ls180.v:5860.38-5860.145" + cell $and $and$ls180.v:5860$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5860$1223_Y + connect \B $eq$ls180.v:5860$1224_Y + connect \Y $and$ls180.v:5860$1225_Y + end + attribute \src "ls180.v:5862.39-5862.92" + cell $and $and$ls180.v:5862$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5862$1226_Y + end + attribute \src "ls180.v:5862.38-5862.142" + cell $and $and$ls180.v:5862$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5862$1226_Y + connect \B $eq$ls180.v:5862$1227_Y + connect \Y $and$ls180.v:5862$1228_Y + end + attribute \src "ls180.v:5863.39-5863.95" + cell $and $and$ls180.v:5863$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5863$1229_Y + connect \Y $and$ls180.v:5863$1230_Y + end + attribute \src "ls180.v:5863.38-5863.145" + cell $and $and$ls180.v:5863$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5863$1230_Y + connect \B $eq$ls180.v:5863$1231_Y + connect \Y $and$ls180.v:5863$1232_Y + end + attribute \src "ls180.v:5865.39-5865.92" + cell $and $and$ls180.v:5865$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5865$1233_Y + end + attribute \src "ls180.v:5865.38-5865.142" + cell $and $and$ls180.v:5865$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5865$1233_Y + connect \B $eq$ls180.v:5865$1234_Y + connect \Y $and$ls180.v:5865$1235_Y + end + attribute \src "ls180.v:5866.39-5866.95" + cell $and $and$ls180.v:5866$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5866$1236_Y + connect \Y $and$ls180.v:5866$1237_Y + end + attribute \src "ls180.v:5866.38-5866.145" + cell $and $and$ls180.v:5866$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5866$1237_Y + connect \B $eq$ls180.v:5866$1238_Y + connect \Y $and$ls180.v:5866$1239_Y + end + attribute \src "ls180.v:5868.40-5868.93" + cell $and $and$ls180.v:5868$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5868$1240_Y + end + attribute \src "ls180.v:5868.39-5868.143" + cell $and $and$ls180.v:5868$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5868$1240_Y + connect \B $eq$ls180.v:5868$1241_Y + connect \Y $and$ls180.v:5868$1242_Y + end + attribute \src "ls180.v:5869.40-5869.96" + cell $and $and$ls180.v:5869$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5869$1243_Y + connect \Y $and$ls180.v:5869$1244_Y + end + attribute \src "ls180.v:5869.39-5869.146" + cell $and $and$ls180.v:5869$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5869$1244_Y + connect \B $eq$ls180.v:5869$1245_Y + connect \Y $and$ls180.v:5869$1246_Y + end + attribute \src "ls180.v:5871.40-5871.93" + cell $and $and$ls180.v:5871$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5871$1247_Y + end + attribute \src "ls180.v:5871.39-5871.143" + cell $and $and$ls180.v:5871$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5871$1247_Y + connect \B $eq$ls180.v:5871$1248_Y + connect \Y $and$ls180.v:5871$1249_Y + end + attribute \src "ls180.v:5872.40-5872.96" + cell $and $and$ls180.v:5872$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5872$1250_Y + connect \Y $and$ls180.v:5872$1251_Y + end + attribute \src "ls180.v:5872.39-5872.146" + cell $and $and$ls180.v:5872$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5872$1251_Y + connect \B $eq$ls180.v:5872$1252_Y + connect \Y $and$ls180.v:5872$1253_Y + end + attribute \src "ls180.v:5874.40-5874.93" + cell $and $and$ls180.v:5874$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5874$1254_Y + end + attribute \src "ls180.v:5874.39-5874.143" + cell $and $and$ls180.v:5874$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5874$1254_Y + connect \B $eq$ls180.v:5874$1255_Y + connect \Y $and$ls180.v:5874$1256_Y + end + attribute \src "ls180.v:5875.40-5875.96" + cell $and $and$ls180.v:5875$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5875$1257_Y + connect \Y $and$ls180.v:5875$1258_Y + end + attribute \src "ls180.v:5875.39-5875.146" + cell $and $and$ls180.v:5875$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5875$1258_Y + connect \B $eq$ls180.v:5875$1259_Y + connect \Y $and$ls180.v:5875$1260_Y + end + attribute \src "ls180.v:5877.40-5877.93" + cell $and $and$ls180.v:5877$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:5877$1261_Y + end + attribute \src "ls180.v:5877.39-5877.143" + cell $and $and$ls180.v:5877$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5877$1261_Y + connect \B $eq$ls180.v:5877$1262_Y + connect \Y $and$ls180.v:5877$1263_Y + end + attribute \src "ls180.v:5878.40-5878.96" + cell $and $and$ls180.v:5878$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:5878$1264_Y + connect \Y $and$ls180.v:5878$1265_Y + end + attribute \src "ls180.v:5878.39-5878.146" + cell $and $and$ls180.v:5878$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5878$1265_Y + connect \B $eq$ls180.v:5878$1266_Y + connect \Y $and$ls180.v:5878$1267_Y + end + attribute \src "ls180.v:5890.40-5890.93" + cell $and $and$ls180.v:5890$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5890$1269_Y + end + attribute \src "ls180.v:5890.39-5890.143" + cell $and $and$ls180.v:5890$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5890$1269_Y + connect \B $eq$ls180.v:5890$1270_Y + connect \Y $and$ls180.v:5890$1271_Y + end + attribute \src "ls180.v:5891.40-5891.96" + cell $and $and$ls180.v:5891$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5891$1272_Y + connect \Y $and$ls180.v:5891$1273_Y + end + attribute \src "ls180.v:5891.39-5891.146" + cell $and $and$ls180.v:5891$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5891$1273_Y + connect \B $eq$ls180.v:5891$1274_Y + connect \Y $and$ls180.v:5891$1275_Y + end + attribute \src "ls180.v:5893.39-5893.92" + cell $and $and$ls180.v:5893$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5893$1276_Y + end + attribute \src "ls180.v:5893.38-5893.142" + cell $and $and$ls180.v:5893$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5893$1276_Y + connect \B $eq$ls180.v:5893$1277_Y + connect \Y $and$ls180.v:5893$1278_Y + end + attribute \src "ls180.v:5894.39-5894.95" + cell $and $and$ls180.v:5894$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5894$1279_Y + connect \Y $and$ls180.v:5894$1280_Y + end + attribute \src "ls180.v:5894.38-5894.145" + cell $and $and$ls180.v:5894$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5894$1280_Y + connect \B $eq$ls180.v:5894$1281_Y + connect \Y $and$ls180.v:5894$1282_Y + end + attribute \src "ls180.v:5896.39-5896.92" + cell $and $and$ls180.v:5896$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5896$1283_Y + end + attribute \src "ls180.v:5896.38-5896.142" + cell $and $and$ls180.v:5896$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5896$1283_Y + connect \B $eq$ls180.v:5896$1284_Y + connect \Y $and$ls180.v:5896$1285_Y + end + attribute \src "ls180.v:5897.39-5897.95" + cell $and $and$ls180.v:5897$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5897$1286_Y + connect \Y $and$ls180.v:5897$1287_Y + end + attribute \src "ls180.v:5897.38-5897.145" + cell $and $and$ls180.v:5897$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5897$1287_Y + connect \B $eq$ls180.v:5897$1288_Y + connect \Y $and$ls180.v:5897$1289_Y + end + attribute \src "ls180.v:5899.39-5899.92" + cell $and $and$ls180.v:5899$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5899$1290_Y + end + attribute \src "ls180.v:5899.38-5899.142" + cell $and $and$ls180.v:5899$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5899$1290_Y + connect \B $eq$ls180.v:5899$1291_Y + connect \Y $and$ls180.v:5899$1292_Y + end + attribute \src "ls180.v:5900.39-5900.95" + cell $and $and$ls180.v:5900$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5900$1293_Y + connect \Y $and$ls180.v:5900$1294_Y + end + attribute \src "ls180.v:5900.38-5900.145" + cell $and $and$ls180.v:5900$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5900$1294_Y + connect \B $eq$ls180.v:5900$1295_Y + connect \Y $and$ls180.v:5900$1296_Y + end + attribute \src "ls180.v:5902.39-5902.92" + cell $and $and$ls180.v:5902$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5902$1297_Y + end + attribute \src "ls180.v:5902.38-5902.142" + cell $and $and$ls180.v:5902$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5902$1297_Y + connect \B $eq$ls180.v:5902$1298_Y + connect \Y $and$ls180.v:5902$1299_Y + end + attribute \src "ls180.v:5903.39-5903.95" + cell $and $and$ls180.v:5903$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5903$1300_Y + connect \Y $and$ls180.v:5903$1301_Y + end + attribute \src "ls180.v:5903.38-5903.145" + cell $and $and$ls180.v:5903$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5903$1301_Y + connect \B $eq$ls180.v:5903$1302_Y + connect \Y $and$ls180.v:5903$1303_Y + end + attribute \src "ls180.v:5905.40-5905.93" + cell $and $and$ls180.v:5905$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5905$1304_Y + end + attribute \src "ls180.v:5905.39-5905.143" + cell $and $and$ls180.v:5905$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5905$1304_Y + connect \B $eq$ls180.v:5905$1305_Y + connect \Y $and$ls180.v:5905$1306_Y + end + attribute \src "ls180.v:5906.40-5906.96" + cell $and $and$ls180.v:5906$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5906$1307_Y + connect \Y $and$ls180.v:5906$1308_Y + end + attribute \src "ls180.v:5906.39-5906.146" + cell $and $and$ls180.v:5906$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5906$1308_Y + connect \B $eq$ls180.v:5906$1309_Y + connect \Y $and$ls180.v:5906$1310_Y + end + attribute \src "ls180.v:5908.40-5908.93" + cell $and $and$ls180.v:5908$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5908$1311_Y + end + attribute \src "ls180.v:5908.39-5908.143" + cell $and $and$ls180.v:5908$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5908$1311_Y + connect \B $eq$ls180.v:5908$1312_Y + connect \Y $and$ls180.v:5908$1313_Y + end + attribute \src "ls180.v:5909.40-5909.96" + cell $and $and$ls180.v:5909$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5909$1314_Y + connect \Y $and$ls180.v:5909$1315_Y + end + attribute \src "ls180.v:5909.39-5909.146" + cell $and $and$ls180.v:5909$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5909$1315_Y + connect \B $eq$ls180.v:5909$1316_Y + connect \Y $and$ls180.v:5909$1317_Y + end + attribute \src "ls180.v:5911.40-5911.93" + cell $and $and$ls180.v:5911$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5911$1318_Y + end + attribute \src "ls180.v:5911.39-5911.143" + cell $and $and$ls180.v:5911$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5911$1318_Y + connect \B $eq$ls180.v:5911$1319_Y + connect \Y $and$ls180.v:5911$1320_Y + end + attribute \src "ls180.v:5912.40-5912.96" + cell $and $and$ls180.v:5912$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5912$1321_Y + connect \Y $and$ls180.v:5912$1322_Y + end + attribute \src "ls180.v:5912.39-5912.146" + cell $and $and$ls180.v:5912$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5912$1322_Y + connect \B $eq$ls180.v:5912$1323_Y + connect \Y $and$ls180.v:5912$1324_Y + end + attribute \src "ls180.v:5914.40-5914.93" + cell $and $and$ls180.v:5914$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:5914$1325_Y + end + attribute \src "ls180.v:5914.39-5914.143" + cell $and $and$ls180.v:5914$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5914$1325_Y + connect \B $eq$ls180.v:5914$1326_Y + connect \Y $and$ls180.v:5914$1327_Y + end + attribute \src "ls180.v:5915.40-5915.96" + cell $and $and$ls180.v:5915$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:5915$1328_Y + connect \Y $and$ls180.v:5915$1329_Y + end + attribute \src "ls180.v:5915.39-5915.146" + cell $and $and$ls180.v:5915$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5915$1329_Y + connect \B $eq$ls180.v:5915$1330_Y + connect \Y $and$ls180.v:5915$1331_Y + end + attribute \src "ls180.v:5927.42-5927.95" + cell $and $and$ls180.v:5927$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5927$1333_Y + end + attribute \src "ls180.v:5927.41-5927.145" + cell $and $and$ls180.v:5927$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5927$1333_Y + connect \B $eq$ls180.v:5927$1334_Y + connect \Y $and$ls180.v:5927$1335_Y + end + attribute \src "ls180.v:5928.42-5928.98" + cell $and $and$ls180.v:5928$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5928$1336_Y + connect \Y $and$ls180.v:5928$1337_Y + end + attribute \src "ls180.v:5928.41-5928.148" + cell $and $and$ls180.v:5928$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5928$1337_Y + connect \B $eq$ls180.v:5928$1338_Y + connect \Y $and$ls180.v:5928$1339_Y + end + attribute \src "ls180.v:5930.42-5930.95" + cell $and $and$ls180.v:5930$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5930$1340_Y + end + attribute \src "ls180.v:5930.41-5930.145" + cell $and $and$ls180.v:5930$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5930$1340_Y + connect \B $eq$ls180.v:5930$1341_Y + connect \Y $and$ls180.v:5930$1342_Y + end + attribute \src "ls180.v:5931.42-5931.98" + cell $and $and$ls180.v:5931$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5931$1343_Y + connect \Y $and$ls180.v:5931$1344_Y + end + attribute \src "ls180.v:5931.41-5931.148" + cell $and $and$ls180.v:5931$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5931$1344_Y + connect \B $eq$ls180.v:5931$1345_Y + connect \Y $and$ls180.v:5931$1346_Y + end + attribute \src "ls180.v:5933.42-5933.95" + cell $and $and$ls180.v:5933$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5933$1347_Y + end + attribute \src "ls180.v:5933.41-5933.145" + cell $and $and$ls180.v:5933$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5933$1347_Y + connect \B $eq$ls180.v:5933$1348_Y + connect \Y $and$ls180.v:5933$1349_Y + end + attribute \src "ls180.v:5934.42-5934.98" + cell $and $and$ls180.v:5934$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5934$1350_Y + connect \Y $and$ls180.v:5934$1351_Y + end + attribute \src "ls180.v:5934.41-5934.148" + cell $and $and$ls180.v:5934$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5934$1351_Y + connect \B $eq$ls180.v:5934$1352_Y + connect \Y $and$ls180.v:5934$1353_Y + end + attribute \src "ls180.v:5936.42-5936.95" + cell $and $and$ls180.v:5936$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5936$1354_Y + end + attribute \src "ls180.v:5936.41-5936.145" + cell $and $and$ls180.v:5936$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5936$1354_Y + connect \B $eq$ls180.v:5936$1355_Y + connect \Y $and$ls180.v:5936$1356_Y + end + attribute \src "ls180.v:5937.42-5937.98" + cell $and $and$ls180.v:5937$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5937$1357_Y + connect \Y $and$ls180.v:5937$1358_Y + end + attribute \src "ls180.v:5937.41-5937.148" + cell $and $and$ls180.v:5937$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5937$1358_Y + connect \B $eq$ls180.v:5937$1359_Y + connect \Y $and$ls180.v:5937$1360_Y + end + attribute \src "ls180.v:5939.42-5939.95" + cell $and $and$ls180.v:5939$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5939$1361_Y + end + attribute \src "ls180.v:5939.41-5939.145" + cell $and $and$ls180.v:5939$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5939$1361_Y + connect \B $eq$ls180.v:5939$1362_Y + connect \Y $and$ls180.v:5939$1363_Y + end + attribute \src "ls180.v:5940.42-5940.98" + cell $and $and$ls180.v:5940$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5940$1364_Y + connect \Y $and$ls180.v:5940$1365_Y + end + attribute \src "ls180.v:5940.41-5940.148" + cell $and $and$ls180.v:5940$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5940$1365_Y + connect \B $eq$ls180.v:5940$1366_Y + connect \Y $and$ls180.v:5940$1367_Y + end + attribute \src "ls180.v:5942.42-5942.95" + cell $and $and$ls180.v:5942$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5942$1368_Y + end + attribute \src "ls180.v:5942.41-5942.145" + cell $and $and$ls180.v:5942$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5942$1368_Y + connect \B $eq$ls180.v:5942$1369_Y + connect \Y $and$ls180.v:5942$1370_Y + end + attribute \src "ls180.v:5943.42-5943.98" + cell $and $and$ls180.v:5943$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5943$1371_Y + connect \Y $and$ls180.v:5943$1372_Y + end + attribute \src "ls180.v:5943.41-5943.148" + cell $and $and$ls180.v:5943$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5943$1372_Y + connect \B $eq$ls180.v:5943$1373_Y + connect \Y $and$ls180.v:5943$1374_Y + end + attribute \src "ls180.v:5945.42-5945.95" + cell $and $and$ls180.v:5945$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5945$1375_Y + end + attribute \src "ls180.v:5945.41-5945.145" + cell $and $and$ls180.v:5945$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5945$1375_Y + connect \B $eq$ls180.v:5945$1376_Y + connect \Y $and$ls180.v:5945$1377_Y + end + attribute \src "ls180.v:5946.42-5946.98" + cell $and $and$ls180.v:5946$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5946$1378_Y + connect \Y $and$ls180.v:5946$1379_Y + end + attribute \src "ls180.v:5946.41-5946.148" + cell $and $and$ls180.v:5946$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5946$1379_Y + connect \B $eq$ls180.v:5946$1380_Y + connect \Y $and$ls180.v:5946$1381_Y + end + attribute \src "ls180.v:5948.42-5948.95" + cell $and $and$ls180.v:5948$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5948$1382_Y + end + attribute \src "ls180.v:5948.41-5948.145" + cell $and $and$ls180.v:5948$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5948$1382_Y + connect \B $eq$ls180.v:5948$1383_Y + connect \Y $and$ls180.v:5948$1384_Y + end + attribute \src "ls180.v:5949.42-5949.98" + cell $and $and$ls180.v:5949$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5949$1385_Y + connect \Y $and$ls180.v:5949$1386_Y + end + attribute \src "ls180.v:5949.41-5949.148" + cell $and $and$ls180.v:5949$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5949$1386_Y + connect \B $eq$ls180.v:5949$1387_Y + connect \Y $and$ls180.v:5949$1388_Y + end + attribute \src "ls180.v:5951.44-5951.97" + cell $and $and$ls180.v:5951$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5951$1389_Y + end + attribute \src "ls180.v:5951.43-5951.147" + cell $and $and$ls180.v:5951$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5951$1389_Y + connect \B $eq$ls180.v:5951$1390_Y + connect \Y $and$ls180.v:5951$1391_Y + end + attribute \src "ls180.v:5952.44-5952.100" + cell $and $and$ls180.v:5952$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5952$1392_Y + connect \Y $and$ls180.v:5952$1393_Y + end + attribute \src "ls180.v:5952.43-5952.150" + cell $and $and$ls180.v:5952$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5952$1393_Y + connect \B $eq$ls180.v:5952$1394_Y + connect \Y $and$ls180.v:5952$1395_Y + end + attribute \src "ls180.v:5954.44-5954.97" + cell $and $and$ls180.v:5954$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5954$1396_Y + end + attribute \src "ls180.v:5954.43-5954.147" + cell $and $and$ls180.v:5954$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5954$1396_Y + connect \B $eq$ls180.v:5954$1397_Y + connect \Y $and$ls180.v:5954$1398_Y + end + attribute \src "ls180.v:5955.44-5955.100" + cell $and $and$ls180.v:5955$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5955$1399_Y + connect \Y $and$ls180.v:5955$1400_Y + end + attribute \src "ls180.v:5955.43-5955.150" + cell $and $and$ls180.v:5955$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5955$1400_Y + connect \B $eq$ls180.v:5955$1401_Y + connect \Y $and$ls180.v:5955$1402_Y + end + attribute \src "ls180.v:5957.44-5957.97" + cell $and $and$ls180.v:5957$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5957$1403_Y + end + attribute \src "ls180.v:5957.43-5957.148" + cell $and $and$ls180.v:5957$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5957$1403_Y + connect \B $eq$ls180.v:5957$1404_Y + connect \Y $and$ls180.v:5957$1405_Y + end + attribute \src "ls180.v:5958.44-5958.100" + cell $and $and$ls180.v:5958$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5958$1406_Y + connect \Y $and$ls180.v:5958$1407_Y + end + attribute \src "ls180.v:5958.43-5958.151" + cell $and $and$ls180.v:5958$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5958$1407_Y + connect \B $eq$ls180.v:5958$1408_Y + connect \Y $and$ls180.v:5958$1409_Y + end + attribute \src "ls180.v:5960.44-5960.97" + cell $and $and$ls180.v:5960$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5960$1410_Y + end + attribute \src "ls180.v:5960.43-5960.148" + cell $and $and$ls180.v:5960$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5960$1410_Y + connect \B $eq$ls180.v:5960$1411_Y + connect \Y $and$ls180.v:5960$1412_Y + end + attribute \src "ls180.v:5961.44-5961.100" + cell $and $and$ls180.v:5961$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5961$1413_Y + connect \Y $and$ls180.v:5961$1414_Y + end + attribute \src "ls180.v:5961.43-5961.151" + cell $and $and$ls180.v:5961$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5961$1414_Y + connect \B $eq$ls180.v:5961$1415_Y + connect \Y $and$ls180.v:5961$1416_Y + end + attribute \src "ls180.v:5963.44-5963.97" + cell $and $and$ls180.v:5963$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5963$1417_Y + end + attribute \src "ls180.v:5963.43-5963.148" + cell $and $and$ls180.v:5963$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5963$1417_Y + connect \B $eq$ls180.v:5963$1418_Y + connect \Y $and$ls180.v:5963$1419_Y + end + attribute \src "ls180.v:5964.44-5964.100" + cell $and $and$ls180.v:5964$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5964$1420_Y + connect \Y $and$ls180.v:5964$1421_Y + end + attribute \src "ls180.v:5964.43-5964.151" + cell $and $and$ls180.v:5964$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5964$1421_Y + connect \B $eq$ls180.v:5964$1422_Y + connect \Y $and$ls180.v:5964$1423_Y + end + attribute \src "ls180.v:5966.41-5966.94" + cell $and $and$ls180.v:5966$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5966$1424_Y + end + attribute \src "ls180.v:5966.40-5966.145" + cell $and $and$ls180.v:5966$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5966$1424_Y + connect \B $eq$ls180.v:5966$1425_Y + connect \Y $and$ls180.v:5966$1426_Y + end + attribute \src "ls180.v:5967.41-5967.97" + cell $and $and$ls180.v:5967$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5967$1427_Y + connect \Y $and$ls180.v:5967$1428_Y + end + attribute \src "ls180.v:5967.40-5967.148" + cell $and $and$ls180.v:5967$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5967$1428_Y + connect \B $eq$ls180.v:5967$1429_Y + connect \Y $and$ls180.v:5967$1430_Y + end + attribute \src "ls180.v:5969.42-5969.95" + cell $and $and$ls180.v:5969$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:5969$1431_Y + end + attribute \src "ls180.v:5969.41-5969.146" + cell $and $and$ls180.v:5969$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5969$1431_Y + connect \B $eq$ls180.v:5969$1432_Y + connect \Y $and$ls180.v:5969$1433_Y + end + attribute \src "ls180.v:5970.42-5970.98" + cell $and $and$ls180.v:5970$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:5970$1434_Y + connect \Y $and$ls180.v:5970$1435_Y + end + attribute \src "ls180.v:5970.41-5970.149" + cell $and $and$ls180.v:5970$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5970$1435_Y + connect \B $eq$ls180.v:5970$1436_Y + connect \Y $and$ls180.v:5970$1437_Y + end + attribute \src "ls180.v:5989.46-5989.99" + cell $and $and$ls180.v:5989$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5989$1439_Y + end + attribute \src "ls180.v:5989.45-5989.149" + cell $and $and$ls180.v:5989$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5989$1439_Y + connect \B $eq$ls180.v:5989$1440_Y + connect \Y $and$ls180.v:5989$1441_Y + end + attribute \src "ls180.v:5990.46-5990.102" + cell $and $and$ls180.v:5990$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5990$1442_Y + connect \Y $and$ls180.v:5990$1443_Y + end + attribute \src "ls180.v:5990.45-5990.152" + cell $and $and$ls180.v:5990$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5990$1443_Y + connect \B $eq$ls180.v:5990$1444_Y + connect \Y $and$ls180.v:5990$1445_Y + end + attribute \src "ls180.v:5992.46-5992.99" + cell $and $and$ls180.v:5992$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5992$1446_Y + end + attribute \src "ls180.v:5992.45-5992.149" + cell $and $and$ls180.v:5992$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5992$1446_Y + connect \B $eq$ls180.v:5992$1447_Y + connect \Y $and$ls180.v:5992$1448_Y + end + attribute \src "ls180.v:5993.46-5993.102" + cell $and $and$ls180.v:5993$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5993$1449_Y + connect \Y $and$ls180.v:5993$1450_Y + end + attribute \src "ls180.v:5993.45-5993.152" + cell $and $and$ls180.v:5993$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5993$1450_Y + connect \B $eq$ls180.v:5993$1451_Y + connect \Y $and$ls180.v:5993$1452_Y + end + attribute \src "ls180.v:5995.46-5995.99" + cell $and $and$ls180.v:5995$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5995$1453_Y + end + attribute \src "ls180.v:5995.45-5995.149" + cell $and $and$ls180.v:5995$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5995$1453_Y + connect \B $eq$ls180.v:5995$1454_Y + connect \Y $and$ls180.v:5995$1455_Y + end + attribute \src "ls180.v:5996.46-5996.102" + cell $and $and$ls180.v:5996$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5996$1456_Y + connect \Y $and$ls180.v:5996$1457_Y + end + attribute \src "ls180.v:5996.45-5996.152" + cell $and $and$ls180.v:5996$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5996$1457_Y + connect \B $eq$ls180.v:5996$1458_Y + connect \Y $and$ls180.v:5996$1459_Y + end + attribute \src "ls180.v:5998.46-5998.99" + cell $and $and$ls180.v:5998$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:5998$1460_Y + end + attribute \src "ls180.v:5998.45-5998.149" + cell $and $and$ls180.v:5998$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5998$1460_Y + connect \B $eq$ls180.v:5998$1461_Y + connect \Y $and$ls180.v:5998$1462_Y + end + attribute \src "ls180.v:5999.46-5999.102" + cell $and $and$ls180.v:5999$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:5999$1463_Y + connect \Y $and$ls180.v:5999$1464_Y + end + attribute \src "ls180.v:5999.45-5999.152" + cell $and $and$ls180.v:5999$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5999$1464_Y + connect \B $eq$ls180.v:5999$1465_Y + connect \Y $and$ls180.v:5999$1466_Y + end + attribute \src "ls180.v:6001.45-6001.98" + cell $and $and$ls180.v:6001$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6001$1467_Y + end + attribute \src "ls180.v:6001.44-6001.148" + cell $and $and$ls180.v:6001$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6001$1467_Y + connect \B $eq$ls180.v:6001$1468_Y + connect \Y $and$ls180.v:6001$1469_Y + end + attribute \src "ls180.v:6002.45-6002.101" + cell $and $and$ls180.v:6002$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6002$1470_Y + connect \Y $and$ls180.v:6002$1471_Y + end + attribute \src "ls180.v:6002.44-6002.151" + cell $and $and$ls180.v:6002$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6002$1471_Y + connect \B $eq$ls180.v:6002$1472_Y + connect \Y $and$ls180.v:6002$1473_Y + end + attribute \src "ls180.v:6004.45-6004.98" + cell $and $and$ls180.v:6004$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6004$1474_Y + end + attribute \src "ls180.v:6004.44-6004.148" + cell $and $and$ls180.v:6004$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6004$1474_Y + connect \B $eq$ls180.v:6004$1475_Y + connect \Y $and$ls180.v:6004$1476_Y + end + attribute \src "ls180.v:6005.45-6005.101" + cell $and $and$ls180.v:6005$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6005$1477_Y + connect \Y $and$ls180.v:6005$1478_Y + end + attribute \src "ls180.v:6005.44-6005.151" + cell $and $and$ls180.v:6005$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6005$1478_Y + connect \B $eq$ls180.v:6005$1479_Y + connect \Y $and$ls180.v:6005$1480_Y + end + attribute \src "ls180.v:6007.45-6007.98" + cell $and $and$ls180.v:6007$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6007$1481_Y + end + attribute \src "ls180.v:6007.44-6007.148" + cell $and $and$ls180.v:6007$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6007$1481_Y + connect \B $eq$ls180.v:6007$1482_Y + connect \Y $and$ls180.v:6007$1483_Y + end + attribute \src "ls180.v:6008.45-6008.101" + cell $and $and$ls180.v:6008$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6008$1484_Y + connect \Y $and$ls180.v:6008$1485_Y + end + attribute \src "ls180.v:6008.44-6008.151" + cell $and $and$ls180.v:6008$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6008$1485_Y + connect \B $eq$ls180.v:6008$1486_Y + connect \Y $and$ls180.v:6008$1487_Y + end + attribute \src "ls180.v:6010.45-6010.98" + cell $and $and$ls180.v:6010$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6010$1488_Y + end + attribute \src "ls180.v:6010.44-6010.148" + cell $and $and$ls180.v:6010$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6010$1488_Y + connect \B $eq$ls180.v:6010$1489_Y + connect \Y $and$ls180.v:6010$1490_Y + end + attribute \src "ls180.v:6011.45-6011.101" + cell $and $and$ls180.v:6011$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6011$1491_Y + connect \Y $and$ls180.v:6011$1492_Y + end + attribute \src "ls180.v:6011.44-6011.151" + cell $and $and$ls180.v:6011$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6011$1492_Y + connect \B $eq$ls180.v:6011$1493_Y + connect \Y $and$ls180.v:6011$1494_Y + end + attribute \src "ls180.v:6013.36-6013.89" + cell $and $and$ls180.v:6013$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6013$1495_Y + end + attribute \src "ls180.v:6013.35-6013.139" + cell $and $and$ls180.v:6013$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6013$1495_Y + connect \B $eq$ls180.v:6013$1496_Y + connect \Y $and$ls180.v:6013$1497_Y + end + attribute \src "ls180.v:6014.36-6014.92" + cell $and $and$ls180.v:6014$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6014$1498_Y + connect \Y $and$ls180.v:6014$1499_Y + end + attribute \src "ls180.v:6014.35-6014.142" + cell $and $and$ls180.v:6014$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6014$1499_Y + connect \B $eq$ls180.v:6014$1500_Y + connect \Y $and$ls180.v:6014$1501_Y + end + attribute \src "ls180.v:6016.47-6016.100" + cell $and $and$ls180.v:6016$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6016$1502_Y + end + attribute \src "ls180.v:6016.46-6016.150" + cell $and $and$ls180.v:6016$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6016$1502_Y + connect \B $eq$ls180.v:6016$1503_Y + connect \Y $and$ls180.v:6016$1504_Y + end + attribute \src "ls180.v:6017.47-6017.103" + cell $and $and$ls180.v:6017$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6017$1505_Y + connect \Y $and$ls180.v:6017$1506_Y + end + attribute \src "ls180.v:6017.46-6017.153" + cell $and $and$ls180.v:6017$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6017$1506_Y + connect \B $eq$ls180.v:6017$1507_Y + connect \Y $and$ls180.v:6017$1508_Y + end + attribute \src "ls180.v:6019.47-6019.100" + cell $and $and$ls180.v:6019$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6019$1509_Y + end + attribute \src "ls180.v:6019.46-6019.151" + cell $and $and$ls180.v:6019$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6019$1509_Y + connect \B $eq$ls180.v:6019$1510_Y + connect \Y $and$ls180.v:6019$1511_Y + end + attribute \src "ls180.v:6020.47-6020.103" + cell $and $and$ls180.v:6020$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6020$1512_Y + connect \Y $and$ls180.v:6020$1513_Y + end + attribute \src "ls180.v:6020.46-6020.154" + cell $and $and$ls180.v:6020$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6020$1513_Y + connect \B $eq$ls180.v:6020$1514_Y + connect \Y $and$ls180.v:6020$1515_Y + end + attribute \src "ls180.v:6022.47-6022.100" + cell $and $and$ls180.v:6022$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6022$1516_Y + end + attribute \src "ls180.v:6022.46-6022.151" + cell $and $and$ls180.v:6022$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6022$1516_Y + connect \B $eq$ls180.v:6022$1517_Y + connect \Y $and$ls180.v:6022$1518_Y + end + attribute \src "ls180.v:6023.47-6023.103" + cell $and $and$ls180.v:6023$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6023$1519_Y + connect \Y $and$ls180.v:6023$1520_Y + end + attribute \src "ls180.v:6023.46-6023.154" + cell $and $and$ls180.v:6023$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6023$1520_Y + connect \B $eq$ls180.v:6023$1521_Y + connect \Y $and$ls180.v:6023$1522_Y + end + attribute \src "ls180.v:6025.47-6025.100" + cell $and $and$ls180.v:6025$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6025$1523_Y + end + attribute \src "ls180.v:6025.46-6025.151" + cell $and $and$ls180.v:6025$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6025$1523_Y + connect \B $eq$ls180.v:6025$1524_Y + connect \Y $and$ls180.v:6025$1525_Y + end + attribute \src "ls180.v:6026.47-6026.103" + cell $and $and$ls180.v:6026$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6026$1526_Y + connect \Y $and$ls180.v:6026$1527_Y + end + attribute \src "ls180.v:6026.46-6026.154" + cell $and $and$ls180.v:6026$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6026$1527_Y + connect \B $eq$ls180.v:6026$1528_Y + connect \Y $and$ls180.v:6026$1529_Y + end + attribute \src "ls180.v:6028.47-6028.100" + cell $and $and$ls180.v:6028$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6028$1530_Y + end + attribute \src "ls180.v:6028.46-6028.151" + cell $and $and$ls180.v:6028$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6028$1530_Y + connect \B $eq$ls180.v:6028$1531_Y + connect \Y $and$ls180.v:6028$1532_Y + end + attribute \src "ls180.v:6029.47-6029.103" + cell $and $and$ls180.v:6029$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6029$1533_Y + connect \Y $and$ls180.v:6029$1534_Y + end + attribute \src "ls180.v:6029.46-6029.154" + cell $and $and$ls180.v:6029$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6029$1534_Y + connect \B $eq$ls180.v:6029$1535_Y + connect \Y $and$ls180.v:6029$1536_Y + end + attribute \src "ls180.v:6031.47-6031.100" + cell $and $and$ls180.v:6031$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6031$1537_Y + end + attribute \src "ls180.v:6031.46-6031.151" + cell $and $and$ls180.v:6031$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6031$1537_Y + connect \B $eq$ls180.v:6031$1538_Y + connect \Y $and$ls180.v:6031$1539_Y + end + attribute \src "ls180.v:6032.47-6032.103" + cell $and $and$ls180.v:6032$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6032$1540_Y + connect \Y $and$ls180.v:6032$1541_Y + end + attribute \src "ls180.v:6032.46-6032.154" + cell $and $and$ls180.v:6032$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6032$1541_Y + connect \B $eq$ls180.v:6032$1542_Y + connect \Y $and$ls180.v:6032$1543_Y + end + attribute \src "ls180.v:6034.46-6034.99" + cell $and $and$ls180.v:6034$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6034$1544_Y + end + attribute \src "ls180.v:6034.45-6034.150" + cell $and $and$ls180.v:6034$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6034$1544_Y + connect \B $eq$ls180.v:6034$1545_Y + connect \Y $and$ls180.v:6034$1546_Y + end + attribute \src "ls180.v:6035.46-6035.102" + cell $and $and$ls180.v:6035$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6035$1547_Y + connect \Y $and$ls180.v:6035$1548_Y + end + attribute \src "ls180.v:6035.45-6035.153" + cell $and $and$ls180.v:6035$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6035$1548_Y + connect \B $eq$ls180.v:6035$1549_Y + connect \Y $and$ls180.v:6035$1550_Y + end + attribute \src "ls180.v:6037.46-6037.99" + cell $and $and$ls180.v:6037$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6037$1551_Y + end + attribute \src "ls180.v:6037.45-6037.150" + cell $and $and$ls180.v:6037$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6037$1551_Y + connect \B $eq$ls180.v:6037$1552_Y + connect \Y $and$ls180.v:6037$1553_Y + end + attribute \src "ls180.v:6038.46-6038.102" + cell $and $and$ls180.v:6038$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6038$1554_Y + connect \Y $and$ls180.v:6038$1555_Y + end + attribute \src "ls180.v:6038.45-6038.153" + cell $and $and$ls180.v:6038$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6038$1555_Y + connect \B $eq$ls180.v:6038$1556_Y + connect \Y $and$ls180.v:6038$1557_Y + end + attribute \src "ls180.v:6040.46-6040.99" + cell $and $and$ls180.v:6040$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6040$1558_Y + end + attribute \src "ls180.v:6040.45-6040.150" + cell $and $and$ls180.v:6040$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6040$1558_Y + connect \B $eq$ls180.v:6040$1559_Y + connect \Y $and$ls180.v:6040$1560_Y + end + attribute \src "ls180.v:6041.46-6041.102" + cell $and $and$ls180.v:6041$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6041$1561_Y + connect \Y $and$ls180.v:6041$1562_Y + end + attribute \src "ls180.v:6041.45-6041.153" + cell $and $and$ls180.v:6041$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6041$1562_Y + connect \B $eq$ls180.v:6041$1563_Y + connect \Y $and$ls180.v:6041$1564_Y + end + attribute \src "ls180.v:6043.46-6043.99" + cell $and $and$ls180.v:6043$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6043$1565_Y + end + attribute \src "ls180.v:6043.45-6043.150" + cell $and $and$ls180.v:6043$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6043$1565_Y + connect \B $eq$ls180.v:6043$1566_Y + connect \Y $and$ls180.v:6043$1567_Y + end + attribute \src "ls180.v:6044.46-6044.102" + cell $and $and$ls180.v:6044$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6044$1568_Y + connect \Y $and$ls180.v:6044$1569_Y + end + attribute \src "ls180.v:6044.45-6044.153" + cell $and $and$ls180.v:6044$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6044$1569_Y + connect \B $eq$ls180.v:6044$1570_Y + connect \Y $and$ls180.v:6044$1571_Y + end + attribute \src "ls180.v:6046.46-6046.99" + cell $and $and$ls180.v:6046$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6046$1572_Y + end + attribute \src "ls180.v:6046.45-6046.150" + cell $and $and$ls180.v:6046$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6046$1572_Y + connect \B $eq$ls180.v:6046$1573_Y + connect \Y $and$ls180.v:6046$1574_Y + end + attribute \src "ls180.v:6047.46-6047.102" + cell $and $and$ls180.v:6047$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6047$1575_Y + connect \Y $and$ls180.v:6047$1576_Y + end + attribute \src "ls180.v:6047.45-6047.153" + cell $and $and$ls180.v:6047$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6047$1576_Y + connect \B $eq$ls180.v:6047$1577_Y + connect \Y $and$ls180.v:6047$1578_Y + end + attribute \src "ls180.v:6049.46-6049.99" + cell $and $and$ls180.v:6049$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6049$1579_Y + end + attribute \src "ls180.v:6049.45-6049.150" + cell $and $and$ls180.v:6049$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6049$1579_Y + connect \B $eq$ls180.v:6049$1580_Y + connect \Y $and$ls180.v:6049$1581_Y + end + attribute \src "ls180.v:6050.46-6050.102" + cell $and $and$ls180.v:6050$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6050$1582_Y + connect \Y $and$ls180.v:6050$1583_Y + end + attribute \src "ls180.v:6050.45-6050.153" + cell $and $and$ls180.v:6050$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6050$1583_Y + connect \B $eq$ls180.v:6050$1584_Y + connect \Y $and$ls180.v:6050$1585_Y + end + attribute \src "ls180.v:6052.46-6052.99" + cell $and $and$ls180.v:6052$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6052$1586_Y + end + attribute \src "ls180.v:6052.45-6052.150" + cell $and $and$ls180.v:6052$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6052$1586_Y + connect \B $eq$ls180.v:6052$1587_Y + connect \Y $and$ls180.v:6052$1588_Y + end + attribute \src "ls180.v:6053.46-6053.102" + cell $and $and$ls180.v:6053$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6053$1589_Y + connect \Y $and$ls180.v:6053$1590_Y + end + attribute \src "ls180.v:6053.45-6053.153" + cell $and $and$ls180.v:6053$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6053$1590_Y + connect \B $eq$ls180.v:6053$1591_Y + connect \Y $and$ls180.v:6053$1592_Y + end + attribute \src "ls180.v:6055.46-6055.99" + cell $and $and$ls180.v:6055$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6055$1593_Y + end + attribute \src "ls180.v:6055.45-6055.150" + cell $and $and$ls180.v:6055$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6055$1593_Y + connect \B $eq$ls180.v:6055$1594_Y + connect \Y $and$ls180.v:6055$1595_Y + end + attribute \src "ls180.v:6056.46-6056.102" + cell $and $and$ls180.v:6056$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6056$1596_Y + connect \Y $and$ls180.v:6056$1597_Y + end + attribute \src "ls180.v:6056.45-6056.153" + cell $and $and$ls180.v:6056$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6056$1597_Y + connect \B $eq$ls180.v:6056$1598_Y + connect \Y $and$ls180.v:6056$1599_Y + end + attribute \src "ls180.v:6058.46-6058.99" + cell $and $and$ls180.v:6058$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6058$1600_Y + end + attribute \src "ls180.v:6058.45-6058.150" + cell $and $and$ls180.v:6058$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6058$1600_Y + connect \B $eq$ls180.v:6058$1601_Y + connect \Y $and$ls180.v:6058$1602_Y + end + attribute \src "ls180.v:6059.46-6059.102" + cell $and $and$ls180.v:6059$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6059$1603_Y + connect \Y $and$ls180.v:6059$1604_Y + end + attribute \src "ls180.v:6059.45-6059.153" + cell $and $and$ls180.v:6059$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6059$1604_Y + connect \B $eq$ls180.v:6059$1605_Y + connect \Y $and$ls180.v:6059$1606_Y + end + attribute \src "ls180.v:6061.46-6061.99" + cell $and $and$ls180.v:6061$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6061$1607_Y + end + attribute \src "ls180.v:6061.45-6061.150" + cell $and $and$ls180.v:6061$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6061$1607_Y + connect \B $eq$ls180.v:6061$1608_Y + connect \Y $and$ls180.v:6061$1609_Y + end + attribute \src "ls180.v:6062.46-6062.102" + cell $and $and$ls180.v:6062$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6062$1610_Y + connect \Y $and$ls180.v:6062$1611_Y + end + attribute \src "ls180.v:6062.45-6062.153" + cell $and $and$ls180.v:6062$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6062$1611_Y + connect \B $eq$ls180.v:6062$1612_Y + connect \Y $and$ls180.v:6062$1613_Y + end + attribute \src "ls180.v:6064.42-6064.95" + cell $and $and$ls180.v:6064$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6064$1614_Y + end + attribute \src "ls180.v:6064.41-6064.146" + cell $and $and$ls180.v:6064$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6064$1614_Y + connect \B $eq$ls180.v:6064$1615_Y + connect \Y $and$ls180.v:6064$1616_Y + end + attribute \src "ls180.v:6065.42-6065.98" + cell $and $and$ls180.v:6065$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6065$1617_Y + connect \Y $and$ls180.v:6065$1618_Y + end + attribute \src "ls180.v:6065.41-6065.149" + cell $and $and$ls180.v:6065$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6065$1618_Y + connect \B $eq$ls180.v:6065$1619_Y + connect \Y $and$ls180.v:6065$1620_Y + end + attribute \src "ls180.v:6067.43-6067.96" + cell $and $and$ls180.v:6067$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6067$1621_Y + end + attribute \src "ls180.v:6067.42-6067.147" + cell $and $and$ls180.v:6067$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6067$1621_Y + connect \B $eq$ls180.v:6067$1622_Y + connect \Y $and$ls180.v:6067$1623_Y + end + attribute \src "ls180.v:6068.43-6068.99" + cell $and $and$ls180.v:6068$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6068$1624_Y + connect \Y $and$ls180.v:6068$1625_Y + end + attribute \src "ls180.v:6068.42-6068.150" + cell $and $and$ls180.v:6068$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6068$1625_Y + connect \B $eq$ls180.v:6068$1626_Y + connect \Y $and$ls180.v:6068$1627_Y + end + attribute \src "ls180.v:6070.46-6070.99" + cell $and $and$ls180.v:6070$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6070$1628_Y + end + attribute \src "ls180.v:6070.45-6070.150" + cell $and $and$ls180.v:6070$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6070$1628_Y + connect \B $eq$ls180.v:6070$1629_Y + connect \Y $and$ls180.v:6070$1630_Y + end + attribute \src "ls180.v:6071.46-6071.102" + cell $and $and$ls180.v:6071$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6071$1631_Y + connect \Y $and$ls180.v:6071$1632_Y + end + attribute \src "ls180.v:6071.45-6071.153" + cell $and $and$ls180.v:6071$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6071$1632_Y + connect \B $eq$ls180.v:6071$1633_Y + connect \Y $and$ls180.v:6071$1634_Y + end + attribute \src "ls180.v:6073.46-6073.99" + cell $and $and$ls180.v:6073$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6073$1635_Y + end + attribute \src "ls180.v:6073.45-6073.150" + cell $and $and$ls180.v:6073$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6073$1635_Y + connect \B $eq$ls180.v:6073$1636_Y + connect \Y $and$ls180.v:6073$1637_Y + end + attribute \src "ls180.v:6074.46-6074.102" + cell $and $and$ls180.v:6074$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6074$1638_Y + connect \Y $and$ls180.v:6074$1639_Y + end + attribute \src "ls180.v:6074.45-6074.153" + cell $and $and$ls180.v:6074$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6074$1639_Y + connect \B $eq$ls180.v:6074$1640_Y + connect \Y $and$ls180.v:6074$1641_Y + end + attribute \src "ls180.v:6076.45-6076.98" + cell $and $and$ls180.v:6076$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6076$1642_Y + end + attribute \src "ls180.v:6076.44-6076.149" + cell $and $and$ls180.v:6076$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6076$1642_Y + connect \B $eq$ls180.v:6076$1643_Y + connect \Y $and$ls180.v:6076$1644_Y + end + attribute \src "ls180.v:6077.45-6077.101" + cell $and $and$ls180.v:6077$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6077$1645_Y + connect \Y $and$ls180.v:6077$1646_Y + end + attribute \src "ls180.v:6077.44-6077.152" + cell $and $and$ls180.v:6077$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6077$1646_Y + connect \B $eq$ls180.v:6077$1647_Y + connect \Y $and$ls180.v:6077$1648_Y + end + attribute \src "ls180.v:6079.45-6079.98" + cell $and $and$ls180.v:6079$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6079$1649_Y + end + attribute \src "ls180.v:6079.44-6079.149" + cell $and $and$ls180.v:6079$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6079$1649_Y + connect \B $eq$ls180.v:6079$1650_Y + connect \Y $and$ls180.v:6079$1651_Y + end + attribute \src "ls180.v:6080.45-6080.101" + cell $and $and$ls180.v:6080$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6080$1652_Y + connect \Y $and$ls180.v:6080$1653_Y + end + attribute \src "ls180.v:6080.44-6080.152" + cell $and $and$ls180.v:6080$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6080$1653_Y + connect \B $eq$ls180.v:6080$1654_Y + connect \Y $and$ls180.v:6080$1655_Y + end + attribute \src "ls180.v:6082.45-6082.98" + cell $and $and$ls180.v:6082$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6082$1656_Y + end + attribute \src "ls180.v:6082.44-6082.149" + cell $and $and$ls180.v:6082$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6082$1656_Y + connect \B $eq$ls180.v:6082$1657_Y + connect \Y $and$ls180.v:6082$1658_Y + end + attribute \src "ls180.v:6083.45-6083.101" + cell $and $and$ls180.v:6083$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6083$1659_Y + connect \Y $and$ls180.v:6083$1660_Y + end + attribute \src "ls180.v:6083.44-6083.152" + cell $and $and$ls180.v:6083$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6083$1660_Y + connect \B $eq$ls180.v:6083$1661_Y + connect \Y $and$ls180.v:6083$1662_Y + end + attribute \src "ls180.v:6085.45-6085.98" + cell $and $and$ls180.v:6085$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6085$1663_Y + end + attribute \src "ls180.v:6085.44-6085.149" + cell $and $and$ls180.v:6085$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6085$1663_Y + connect \B $eq$ls180.v:6085$1664_Y + connect \Y $and$ls180.v:6085$1665_Y + end + attribute \src "ls180.v:6086.45-6086.101" + cell $and $and$ls180.v:6086$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6086$1666_Y + connect \Y $and$ls180.v:6086$1667_Y + end + attribute \src "ls180.v:6086.44-6086.152" + cell $and $and$ls180.v:6086$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6086$1667_Y + connect \B $eq$ls180.v:6086$1668_Y + connect \Y $and$ls180.v:6086$1669_Y + end + attribute \src "ls180.v:6124.42-6124.95" + cell $and $and$ls180.v:6124$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6124$1671_Y + end + attribute \src "ls180.v:6124.41-6124.145" + cell $and $and$ls180.v:6124$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6124$1671_Y + connect \B $eq$ls180.v:6124$1672_Y + connect \Y $and$ls180.v:6124$1673_Y + end + attribute \src "ls180.v:6125.42-6125.98" + cell $and $and$ls180.v:6125$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6125$1674_Y + connect \Y $and$ls180.v:6125$1675_Y + end + attribute \src "ls180.v:6125.41-6125.148" + cell $and $and$ls180.v:6125$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6125$1675_Y + connect \B $eq$ls180.v:6125$1676_Y + connect \Y $and$ls180.v:6125$1677_Y + end + attribute \src "ls180.v:6127.42-6127.95" + cell $and $and$ls180.v:6127$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6127$1678_Y + end + attribute \src "ls180.v:6127.41-6127.145" + cell $and $and$ls180.v:6127$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6127$1678_Y + connect \B $eq$ls180.v:6127$1679_Y + connect \Y $and$ls180.v:6127$1680_Y + end + attribute \src "ls180.v:6128.42-6128.98" + cell $and $and$ls180.v:6128$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6128$1681_Y + connect \Y $and$ls180.v:6128$1682_Y + end + attribute \src "ls180.v:6128.41-6128.148" + cell $and $and$ls180.v:6128$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6128$1682_Y + connect \B $eq$ls180.v:6128$1683_Y + connect \Y $and$ls180.v:6128$1684_Y + end + attribute \src "ls180.v:6130.42-6130.95" + cell $and $and$ls180.v:6130$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6130$1685_Y + end + attribute \src "ls180.v:6130.41-6130.145" + cell $and $and$ls180.v:6130$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6130$1685_Y + connect \B $eq$ls180.v:6130$1686_Y + connect \Y $and$ls180.v:6130$1687_Y + end + attribute \src "ls180.v:6131.42-6131.98" + cell $and $and$ls180.v:6131$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6131$1688_Y + connect \Y $and$ls180.v:6131$1689_Y + end + attribute \src "ls180.v:6131.41-6131.148" + cell $and $and$ls180.v:6131$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6131$1689_Y + connect \B $eq$ls180.v:6131$1690_Y + connect \Y $and$ls180.v:6131$1691_Y + end + attribute \src "ls180.v:6133.42-6133.95" + cell $and $and$ls180.v:6133$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6133$1692_Y + end + attribute \src "ls180.v:6133.41-6133.145" + cell $and $and$ls180.v:6133$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6133$1692_Y + connect \B $eq$ls180.v:6133$1693_Y + connect \Y $and$ls180.v:6133$1694_Y + end + attribute \src "ls180.v:6134.42-6134.98" + cell $and $and$ls180.v:6134$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6134$1695_Y + connect \Y $and$ls180.v:6134$1696_Y + end + attribute \src "ls180.v:6134.41-6134.148" + cell $and $and$ls180.v:6134$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6134$1696_Y + connect \B $eq$ls180.v:6134$1697_Y + connect \Y $and$ls180.v:6134$1698_Y + end + attribute \src "ls180.v:6136.42-6136.95" + cell $and $and$ls180.v:6136$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6136$1699_Y + end + attribute \src "ls180.v:6136.41-6136.145" + cell $and $and$ls180.v:6136$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6136$1699_Y + connect \B $eq$ls180.v:6136$1700_Y + connect \Y $and$ls180.v:6136$1701_Y + end + attribute \src "ls180.v:6137.42-6137.98" + cell $and $and$ls180.v:6137$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6137$1702_Y + connect \Y $and$ls180.v:6137$1703_Y + end + attribute \src "ls180.v:6137.41-6137.148" + cell $and $and$ls180.v:6137$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6137$1703_Y + connect \B $eq$ls180.v:6137$1704_Y + connect \Y $and$ls180.v:6137$1705_Y + end + attribute \src "ls180.v:6139.42-6139.95" + cell $and $and$ls180.v:6139$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6139$1706_Y + end + attribute \src "ls180.v:6139.41-6139.145" + cell $and $and$ls180.v:6139$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6139$1706_Y + connect \B $eq$ls180.v:6139$1707_Y + connect \Y $and$ls180.v:6139$1708_Y + end + attribute \src "ls180.v:6140.42-6140.98" + cell $and $and$ls180.v:6140$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6140$1709_Y + connect \Y $and$ls180.v:6140$1710_Y + end + attribute \src "ls180.v:6140.41-6140.148" + cell $and $and$ls180.v:6140$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6140$1710_Y + connect \B $eq$ls180.v:6140$1711_Y + connect \Y $and$ls180.v:6140$1712_Y + end + attribute \src "ls180.v:6142.42-6142.95" + cell $and $and$ls180.v:6142$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6142$1713_Y + end + attribute \src "ls180.v:6142.41-6142.145" + cell $and $and$ls180.v:6142$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6142$1713_Y + connect \B $eq$ls180.v:6142$1714_Y + connect \Y $and$ls180.v:6142$1715_Y + end + attribute \src "ls180.v:6143.42-6143.98" + cell $and $and$ls180.v:6143$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6143$1716_Y + connect \Y $and$ls180.v:6143$1717_Y + end + attribute \src "ls180.v:6143.41-6143.148" + cell $and $and$ls180.v:6143$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6143$1717_Y + connect \B $eq$ls180.v:6143$1718_Y + connect \Y $and$ls180.v:6143$1719_Y + end + attribute \src "ls180.v:6145.42-6145.95" + cell $and $and$ls180.v:6145$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6145$1720_Y + end + attribute \src "ls180.v:6145.41-6145.145" + cell $and $and$ls180.v:6145$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6145$1720_Y + connect \B $eq$ls180.v:6145$1721_Y + connect \Y $and$ls180.v:6145$1722_Y + end + attribute \src "ls180.v:6146.42-6146.98" + cell $and $and$ls180.v:6146$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6146$1723_Y + connect \Y $and$ls180.v:6146$1724_Y + end + attribute \src "ls180.v:6146.41-6146.148" + cell $and $and$ls180.v:6146$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6146$1724_Y + connect \B $eq$ls180.v:6146$1725_Y + connect \Y $and$ls180.v:6146$1726_Y + end + attribute \src "ls180.v:6148.44-6148.97" + cell $and $and$ls180.v:6148$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6148$1727_Y + end + attribute \src "ls180.v:6148.43-6148.147" + cell $and $and$ls180.v:6148$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6148$1727_Y + connect \B $eq$ls180.v:6148$1728_Y + connect \Y $and$ls180.v:6148$1729_Y + end + attribute \src "ls180.v:6149.44-6149.100" + cell $and $and$ls180.v:6149$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6149$1730_Y + connect \Y $and$ls180.v:6149$1731_Y + end + attribute \src "ls180.v:6149.43-6149.150" + cell $and $and$ls180.v:6149$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6149$1731_Y + connect \B $eq$ls180.v:6149$1732_Y + connect \Y $and$ls180.v:6149$1733_Y + end + attribute \src "ls180.v:6151.44-6151.97" + cell $and $and$ls180.v:6151$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6151$1734_Y + end + attribute \src "ls180.v:6151.43-6151.147" + cell $and $and$ls180.v:6151$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6151$1734_Y + connect \B $eq$ls180.v:6151$1735_Y + connect \Y $and$ls180.v:6151$1736_Y + end + attribute \src "ls180.v:6152.44-6152.100" + cell $and $and$ls180.v:6152$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6152$1737_Y + connect \Y $and$ls180.v:6152$1738_Y + end + attribute \src "ls180.v:6152.43-6152.150" + cell $and $and$ls180.v:6152$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6152$1738_Y + connect \B $eq$ls180.v:6152$1739_Y + connect \Y $and$ls180.v:6152$1740_Y + end + attribute \src "ls180.v:6154.44-6154.97" + cell $and $and$ls180.v:6154$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6154$1741_Y + end + attribute \src "ls180.v:6154.43-6154.148" + cell $and $and$ls180.v:6154$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6154$1741_Y + connect \B $eq$ls180.v:6154$1742_Y + connect \Y $and$ls180.v:6154$1743_Y + end + attribute \src "ls180.v:6155.44-6155.100" + cell $and $and$ls180.v:6155$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6155$1744_Y + connect \Y $and$ls180.v:6155$1745_Y + end + attribute \src "ls180.v:6155.43-6155.151" + cell $and $and$ls180.v:6155$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6155$1745_Y + connect \B $eq$ls180.v:6155$1746_Y + connect \Y $and$ls180.v:6155$1747_Y + end + attribute \src "ls180.v:6157.44-6157.97" + cell $and $and$ls180.v:6157$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6157$1748_Y + end + attribute \src "ls180.v:6157.43-6157.148" + cell $and $and$ls180.v:6157$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6157$1748_Y + connect \B $eq$ls180.v:6157$1749_Y + connect \Y $and$ls180.v:6157$1750_Y + end + attribute \src "ls180.v:6158.44-6158.100" + cell $and $and$ls180.v:6158$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6158$1751_Y + connect \Y $and$ls180.v:6158$1752_Y + end + attribute \src "ls180.v:6158.43-6158.151" + cell $and $and$ls180.v:6158$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6158$1752_Y + connect \B $eq$ls180.v:6158$1753_Y + connect \Y $and$ls180.v:6158$1754_Y + end + attribute \src "ls180.v:6160.44-6160.97" + cell $and $and$ls180.v:6160$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6160$1755_Y + end + attribute \src "ls180.v:6160.43-6160.148" + cell $and $and$ls180.v:6160$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6160$1755_Y + connect \B $eq$ls180.v:6160$1756_Y + connect \Y $and$ls180.v:6160$1757_Y + end + attribute \src "ls180.v:6161.44-6161.100" + cell $and $and$ls180.v:6161$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6161$1758_Y + connect \Y $and$ls180.v:6161$1759_Y + end + attribute \src "ls180.v:6161.43-6161.151" + cell $and $and$ls180.v:6161$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6161$1759_Y + connect \B $eq$ls180.v:6161$1760_Y + connect \Y $and$ls180.v:6161$1761_Y + end + attribute \src "ls180.v:6163.41-6163.94" + cell $and $and$ls180.v:6163$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6163$1762_Y + end + attribute \src "ls180.v:6163.40-6163.145" + cell $and $and$ls180.v:6163$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6163$1762_Y + connect \B $eq$ls180.v:6163$1763_Y + connect \Y $and$ls180.v:6163$1764_Y + end + attribute \src "ls180.v:6164.41-6164.97" + cell $and $and$ls180.v:6164$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6164$1765_Y + connect \Y $and$ls180.v:6164$1766_Y + end + attribute \src "ls180.v:6164.40-6164.148" + cell $and $and$ls180.v:6164$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6164$1766_Y + connect \B $eq$ls180.v:6164$1767_Y + connect \Y $and$ls180.v:6164$1768_Y + end + attribute \src "ls180.v:6166.42-6166.95" + cell $and $and$ls180.v:6166$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6166$1769_Y + end + attribute \src "ls180.v:6166.41-6166.146" + cell $and $and$ls180.v:6166$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6166$1769_Y + connect \B $eq$ls180.v:6166$1770_Y + connect \Y $and$ls180.v:6166$1771_Y + end + attribute \src "ls180.v:6167.42-6167.98" + cell $and $and$ls180.v:6167$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6167$1772_Y + connect \Y $and$ls180.v:6167$1773_Y + end + attribute \src "ls180.v:6167.41-6167.149" + cell $and $and$ls180.v:6167$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6167$1773_Y + connect \B $eq$ls180.v:6167$1774_Y + connect \Y $and$ls180.v:6167$1775_Y + end + attribute \src "ls180.v:6169.44-6169.97" + cell $and $and$ls180.v:6169$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6169$1776_Y + end + attribute \src "ls180.v:6169.43-6169.148" + cell $and $and$ls180.v:6169$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6169$1776_Y + connect \B $eq$ls180.v:6169$1777_Y + connect \Y $and$ls180.v:6169$1778_Y + end + attribute \src "ls180.v:6170.44-6170.100" + cell $and $and$ls180.v:6170$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6170$1779_Y + connect \Y $and$ls180.v:6170$1780_Y + end + attribute \src "ls180.v:6170.43-6170.151" + cell $and $and$ls180.v:6170$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6170$1780_Y + connect \B $eq$ls180.v:6170$1781_Y + connect \Y $and$ls180.v:6170$1782_Y + end + attribute \src "ls180.v:6172.44-6172.97" + cell $and $and$ls180.v:6172$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6172$1783_Y + end + attribute \src "ls180.v:6172.43-6172.148" + cell $and $and$ls180.v:6172$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6172$1783_Y + connect \B $eq$ls180.v:6172$1784_Y + connect \Y $and$ls180.v:6172$1785_Y + end + attribute \src "ls180.v:6173.44-6173.100" + cell $and $and$ls180.v:6173$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6173$1786_Y + connect \Y $and$ls180.v:6173$1787_Y + end + attribute \src "ls180.v:6173.43-6173.151" + cell $and $and$ls180.v:6173$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6173$1787_Y + connect \B $eq$ls180.v:6173$1788_Y + connect \Y $and$ls180.v:6173$1789_Y + end + attribute \src "ls180.v:6175.44-6175.97" + cell $and $and$ls180.v:6175$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6175$1790_Y + end + attribute \src "ls180.v:6175.43-6175.148" + cell $and $and$ls180.v:6175$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6175$1790_Y + connect \B $eq$ls180.v:6175$1791_Y + connect \Y $and$ls180.v:6175$1792_Y + end + attribute \src "ls180.v:6176.44-6176.100" + cell $and $and$ls180.v:6176$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6176$1793_Y + connect \Y $and$ls180.v:6176$1794_Y + end + attribute \src "ls180.v:6176.43-6176.151" + cell $and $and$ls180.v:6176$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6176$1794_Y + connect \B $eq$ls180.v:6176$1795_Y + connect \Y $and$ls180.v:6176$1796_Y + end + attribute \src "ls180.v:6178.44-6178.97" + cell $and $and$ls180.v:6178$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6178$1797_Y + end + attribute \src "ls180.v:6178.43-6178.148" + cell $and $and$ls180.v:6178$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6178$1797_Y + connect \B $eq$ls180.v:6178$1798_Y + connect \Y $and$ls180.v:6178$1799_Y + end + attribute \src "ls180.v:6179.44-6179.100" + cell $and $and$ls180.v:6179$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6179$1800_Y + connect \Y $and$ls180.v:6179$1801_Y + end + attribute \src "ls180.v:6179.43-6179.151" + cell $and $and$ls180.v:6179$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6179$1801_Y + connect \B $eq$ls180.v:6179$1802_Y + connect \Y $and$ls180.v:6179$1803_Y + end + attribute \src "ls180.v:6203.44-6203.97" + cell $and $and$ls180.v:6203$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6203$1805_Y + end + attribute \src "ls180.v:6203.43-6203.147" + cell $and $and$ls180.v:6203$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6203$1805_Y + connect \B $eq$ls180.v:6203$1806_Y + connect \Y $and$ls180.v:6203$1807_Y + end + attribute \src "ls180.v:6204.44-6204.100" + cell $and $and$ls180.v:6204$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6204$1808_Y + connect \Y $and$ls180.v:6204$1809_Y + end + attribute \src "ls180.v:6204.43-6204.150" + cell $and $and$ls180.v:6204$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6204$1809_Y + connect \B $eq$ls180.v:6204$1810_Y + connect \Y $and$ls180.v:6204$1811_Y + end + attribute \src "ls180.v:6206.49-6206.102" + cell $and $and$ls180.v:6206$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6206$1812_Y + end + attribute \src "ls180.v:6206.48-6206.152" + cell $and $and$ls180.v:6206$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6206$1812_Y + connect \B $eq$ls180.v:6206$1813_Y + connect \Y $and$ls180.v:6206$1814_Y + end + attribute \src "ls180.v:6207.49-6207.105" + cell $and $and$ls180.v:6207$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6207$1815_Y + connect \Y $and$ls180.v:6207$1816_Y + end + attribute \src "ls180.v:6207.48-6207.155" + cell $and $and$ls180.v:6207$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6207$1816_Y + connect \B $eq$ls180.v:6207$1817_Y + connect \Y $and$ls180.v:6207$1818_Y + end + attribute \src "ls180.v:6209.49-6209.102" + cell $and $and$ls180.v:6209$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6209$1819_Y + end + attribute \src "ls180.v:6209.48-6209.152" + cell $and $and$ls180.v:6209$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6209$1819_Y + connect \B $eq$ls180.v:6209$1820_Y + connect \Y $and$ls180.v:6209$1821_Y + end + attribute \src "ls180.v:6210.49-6210.105" + cell $and $and$ls180.v:6210$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6210$1822_Y + connect \Y $and$ls180.v:6210$1823_Y + end + attribute \src "ls180.v:6210.48-6210.155" + cell $and $and$ls180.v:6210$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6210$1823_Y + connect \B $eq$ls180.v:6210$1824_Y + connect \Y $and$ls180.v:6210$1825_Y + end + attribute \src "ls180.v:6212.42-6212.95" + cell $and $and$ls180.v:6212$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6212$1826_Y + end + attribute \src "ls180.v:6212.41-6212.145" + cell $and $and$ls180.v:6212$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6212$1826_Y + connect \B $eq$ls180.v:6212$1827_Y + connect \Y $and$ls180.v:6212$1828_Y + end + attribute \src "ls180.v:6213.42-6213.98" + cell $and $and$ls180.v:6213$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6213$1829_Y + connect \Y $and$ls180.v:6213$1830_Y + end + attribute \src "ls180.v:6213.41-6213.148" + cell $and $and$ls180.v:6213$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6213$1830_Y + connect \B $eq$ls180.v:6213$1831_Y + connect \Y $and$ls180.v:6213$1832_Y + end + attribute \src "ls180.v:6220.46-6220.99" + cell $and $and$ls180.v:6220$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6220$1834_Y + end + attribute \src "ls180.v:6220.45-6220.149" + cell $and $and$ls180.v:6220$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6220$1834_Y + connect \B $eq$ls180.v:6220$1835_Y + connect \Y $and$ls180.v:6220$1836_Y + end + attribute \src "ls180.v:6221.46-6221.102" + cell $and $and$ls180.v:6221$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6221$1837_Y + connect \Y $and$ls180.v:6221$1838_Y + end + attribute \src "ls180.v:6221.45-6221.152" + cell $and $and$ls180.v:6221$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6221$1838_Y + connect \B $eq$ls180.v:6221$1839_Y + connect \Y $and$ls180.v:6221$1840_Y + end + attribute \src "ls180.v:6223.50-6223.103" + cell $and $and$ls180.v:6223$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6223$1841_Y + end + attribute \src "ls180.v:6223.49-6223.153" + cell $and $and$ls180.v:6223$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6223$1841_Y + connect \B $eq$ls180.v:6223$1842_Y + connect \Y $and$ls180.v:6223$1843_Y + end + attribute \src "ls180.v:6224.50-6224.106" + cell $and $and$ls180.v:6224$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6224$1844_Y + connect \Y $and$ls180.v:6224$1845_Y + end + attribute \src "ls180.v:6224.49-6224.156" + cell $and $and$ls180.v:6224$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6224$1845_Y + connect \B $eq$ls180.v:6224$1846_Y + connect \Y $and$ls180.v:6224$1847_Y + end + attribute \src "ls180.v:6226.40-6226.93" + cell $and $and$ls180.v:6226$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6226$1848_Y + end + attribute \src "ls180.v:6226.39-6226.143" + cell $and $and$ls180.v:6226$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6226$1848_Y + connect \B $eq$ls180.v:6226$1849_Y + connect \Y $and$ls180.v:6226$1850_Y + end + attribute \src "ls180.v:6227.40-6227.96" + cell $and $and$ls180.v:6227$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6227$1851_Y + connect \Y $and$ls180.v:6227$1852_Y + end + attribute \src "ls180.v:6227.39-6227.146" + cell $and $and$ls180.v:6227$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6227$1852_Y + connect \B $eq$ls180.v:6227$1853_Y + connect \Y $and$ls180.v:6227$1854_Y + end + attribute \src "ls180.v:6229.50-6229.103" + cell $and $and$ls180.v:6229$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6229$1855_Y + end + attribute \src "ls180.v:6229.49-6229.153" + cell $and $and$ls180.v:6229$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6229$1855_Y + connect \B $eq$ls180.v:6229$1856_Y + connect \Y $and$ls180.v:6229$1857_Y + end + attribute \src "ls180.v:6230.50-6230.106" + cell $and $and$ls180.v:6230$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6230$1858_Y + connect \Y $and$ls180.v:6230$1859_Y + end + attribute \src "ls180.v:6230.49-6230.156" + cell $and $and$ls180.v:6230$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6230$1859_Y + connect \B $eq$ls180.v:6230$1860_Y + connect \Y $and$ls180.v:6230$1861_Y + end + attribute \src "ls180.v:6232.50-6232.103" + cell $and $and$ls180.v:6232$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6232$1862_Y + end + attribute \src "ls180.v:6232.49-6232.153" + cell $and $and$ls180.v:6232$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6232$1862_Y + connect \B $eq$ls180.v:6232$1863_Y + connect \Y $and$ls180.v:6232$1864_Y + end + attribute \src "ls180.v:6233.50-6233.106" + cell $and $and$ls180.v:6233$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6233$1865_Y + connect \Y $and$ls180.v:6233$1866_Y + end + attribute \src "ls180.v:6233.49-6233.156" + cell $and $and$ls180.v:6233$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6233$1866_Y + connect \B $eq$ls180.v:6233$1867_Y + connect \Y $and$ls180.v:6233$1868_Y + end + attribute \src "ls180.v:6235.51-6235.104" + cell $and $and$ls180.v:6235$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6235$1869_Y + end + attribute \src "ls180.v:6235.50-6235.154" + cell $and $and$ls180.v:6235$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6235$1869_Y + connect \B $eq$ls180.v:6235$1870_Y + connect \Y $and$ls180.v:6235$1871_Y + end + attribute \src "ls180.v:6236.51-6236.107" + cell $and $and$ls180.v:6236$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6236$1872_Y + connect \Y $and$ls180.v:6236$1873_Y + end + attribute \src "ls180.v:6236.50-6236.157" + cell $and $and$ls180.v:6236$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6236$1873_Y + connect \B $eq$ls180.v:6236$1874_Y + connect \Y $and$ls180.v:6236$1875_Y + end + attribute \src "ls180.v:6238.49-6238.102" + cell $and $and$ls180.v:6238$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6238$1876_Y + end + attribute \src "ls180.v:6238.48-6238.152" + cell $and $and$ls180.v:6238$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6238$1876_Y + connect \B $eq$ls180.v:6238$1877_Y + connect \Y $and$ls180.v:6238$1878_Y + end + attribute \src "ls180.v:6239.49-6239.105" + cell $and $and$ls180.v:6239$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6239$1879_Y + connect \Y $and$ls180.v:6239$1880_Y + end + attribute \src "ls180.v:6239.48-6239.155" + cell $and $and$ls180.v:6239$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6239$1880_Y + connect \B $eq$ls180.v:6239$1881_Y + connect \Y $and$ls180.v:6239$1882_Y + end + attribute \src "ls180.v:6241.49-6241.102" + cell $and $and$ls180.v:6241$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6241$1883_Y + end + attribute \src "ls180.v:6241.48-6241.152" + cell $and $and$ls180.v:6241$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6241$1883_Y + connect \B $eq$ls180.v:6241$1884_Y + connect \Y $and$ls180.v:6241$1885_Y + end + attribute \src "ls180.v:6242.49-6242.105" + cell $and $and$ls180.v:6242$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6242$1886_Y + connect \Y $and$ls180.v:6242$1887_Y + end + attribute \src "ls180.v:6242.48-6242.155" + cell $and $and$ls180.v:6242$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6242$1887_Y + connect \B $eq$ls180.v:6242$1888_Y + connect \Y $and$ls180.v:6242$1889_Y + end + attribute \src "ls180.v:6244.49-6244.102" + cell $and $and$ls180.v:6244$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6244$1890_Y + end + attribute \src "ls180.v:6244.48-6244.152" + cell $and $and$ls180.v:6244$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6244$1890_Y + connect \B $eq$ls180.v:6244$1891_Y + connect \Y $and$ls180.v:6244$1892_Y + end + attribute \src "ls180.v:6245.49-6245.105" + cell $and $and$ls180.v:6245$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6245$1893_Y + connect \Y $and$ls180.v:6245$1894_Y + end + attribute \src "ls180.v:6245.48-6245.155" + cell $and $and$ls180.v:6245$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6245$1894_Y + connect \B $eq$ls180.v:6245$1895_Y + connect \Y $and$ls180.v:6245$1896_Y + end + attribute \src "ls180.v:6247.49-6247.102" + cell $and $and$ls180.v:6247$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6247$1897_Y + end + attribute \src "ls180.v:6247.48-6247.152" + cell $and $and$ls180.v:6247$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6247$1897_Y + connect \B $eq$ls180.v:6247$1898_Y + connect \Y $and$ls180.v:6247$1899_Y + end + attribute \src "ls180.v:6248.49-6248.105" + cell $and $and$ls180.v:6248$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6248$1900_Y + connect \Y $and$ls180.v:6248$1901_Y + end + attribute \src "ls180.v:6248.48-6248.155" + cell $and $and$ls180.v:6248$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6248$1901_Y + connect \B $eq$ls180.v:6248$1902_Y + connect \Y $and$ls180.v:6248$1903_Y + end + attribute \src "ls180.v:6265.42-6265.97" + cell $and $and$ls180.v:6265$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6265$1905_Y + end + attribute \src "ls180.v:6265.41-6265.148" + cell $and $and$ls180.v:6265$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6265$1905_Y + connect \B $eq$ls180.v:6265$1906_Y + connect \Y $and$ls180.v:6265$1907_Y + end + attribute \src "ls180.v:6266.42-6266.100" + cell $and $and$ls180.v:6266$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6266$1908_Y + connect \Y $and$ls180.v:6266$1909_Y + end + attribute \src "ls180.v:6266.41-6266.151" + cell $and $and$ls180.v:6266$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6266$1909_Y + connect \B $eq$ls180.v:6266$1910_Y + connect \Y $and$ls180.v:6266$1911_Y + end + attribute \src "ls180.v:6268.42-6268.97" + cell $and $and$ls180.v:6268$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6268$1912_Y + end + attribute \src "ls180.v:6268.41-6268.148" + cell $and $and$ls180.v:6268$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6268$1912_Y + connect \B $eq$ls180.v:6268$1913_Y + connect \Y $and$ls180.v:6268$1914_Y + end + attribute \src "ls180.v:6269.42-6269.100" + cell $and $and$ls180.v:6269$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6269$1915_Y + connect \Y $and$ls180.v:6269$1916_Y + end + attribute \src "ls180.v:6269.41-6269.151" + cell $and $and$ls180.v:6269$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6269$1916_Y + connect \B $eq$ls180.v:6269$1917_Y + connect \Y $and$ls180.v:6269$1918_Y + end + attribute \src "ls180.v:6271.40-6271.95" + cell $and $and$ls180.v:6271$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6271$1919_Y + end + attribute \src "ls180.v:6271.39-6271.146" + cell $and $and$ls180.v:6271$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6271$1919_Y + connect \B $eq$ls180.v:6271$1920_Y + connect \Y $and$ls180.v:6271$1921_Y + end + attribute \src "ls180.v:6272.40-6272.98" + cell $and $and$ls180.v:6272$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6272$1922_Y + connect \Y $and$ls180.v:6272$1923_Y + end + attribute \src "ls180.v:6272.39-6272.149" + cell $and $and$ls180.v:6272$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6272$1923_Y + connect \B $eq$ls180.v:6272$1924_Y + connect \Y $and$ls180.v:6272$1925_Y + end + attribute \src "ls180.v:6274.39-6274.94" + cell $and $and$ls180.v:6274$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6274$1926_Y + end + attribute \src "ls180.v:6274.38-6274.145" + cell $and $and$ls180.v:6274$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6274$1926_Y + connect \B $eq$ls180.v:6274$1927_Y + connect \Y $and$ls180.v:6274$1928_Y + end + attribute \src "ls180.v:6275.39-6275.97" + cell $and $and$ls180.v:6275$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6275$1929_Y + connect \Y $and$ls180.v:6275$1930_Y + end + attribute \src "ls180.v:6275.38-6275.148" + cell $and $and$ls180.v:6275$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6275$1930_Y + connect \B $eq$ls180.v:6275$1931_Y + connect \Y $and$ls180.v:6275$1932_Y + end + attribute \src "ls180.v:6277.38-6277.93" + cell $and $and$ls180.v:6277$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6277$1933_Y + end + attribute \src "ls180.v:6277.37-6277.144" + cell $and $and$ls180.v:6277$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6277$1933_Y + connect \B $eq$ls180.v:6277$1934_Y + connect \Y $and$ls180.v:6277$1935_Y + end + attribute \src "ls180.v:6278.38-6278.96" + cell $and $and$ls180.v:6278$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6278$1936_Y + connect \Y $and$ls180.v:6278$1937_Y + end + attribute \src "ls180.v:6278.37-6278.147" + cell $and $and$ls180.v:6278$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6278$1937_Y + connect \B $eq$ls180.v:6278$1938_Y + connect \Y $and$ls180.v:6278$1939_Y + end + attribute \src "ls180.v:6280.37-6280.92" + cell $and $and$ls180.v:6280$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6280$1940_Y + end + attribute \src "ls180.v:6280.36-6280.143" + cell $and $and$ls180.v:6280$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6280$1940_Y + connect \B $eq$ls180.v:6280$1941_Y + connect \Y $and$ls180.v:6280$1942_Y + end + attribute \src "ls180.v:6281.37-6281.95" + cell $and $and$ls180.v:6281$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6281$1943_Y + connect \Y $and$ls180.v:6281$1944_Y + end + attribute \src "ls180.v:6281.36-6281.146" + cell $and $and$ls180.v:6281$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6281$1944_Y + connect \B $eq$ls180.v:6281$1945_Y + connect \Y $and$ls180.v:6281$1946_Y + end + attribute \src "ls180.v:6283.43-6283.98" + cell $and $and$ls180.v:6283$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6283$1947_Y + end + attribute \src "ls180.v:6283.42-6283.149" + cell $and $and$ls180.v:6283$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6283$1947_Y + connect \B $eq$ls180.v:6283$1948_Y + connect \Y $and$ls180.v:6283$1949_Y + end + attribute \src "ls180.v:6284.43-6284.101" + cell $and $and$ls180.v:6284$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6284$1950_Y + connect \Y $and$ls180.v:6284$1951_Y + end + attribute \src "ls180.v:6284.42-6284.152" + cell $and $and$ls180.v:6284$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6284$1951_Y + connect \B $eq$ls180.v:6284$1952_Y + connect \Y $and$ls180.v:6284$1953_Y + end + attribute \src "ls180.v:6305.42-6305.97" + cell $and $and$ls180.v:6305$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6305$1956_Y + end + attribute \src "ls180.v:6305.41-6305.148" + cell $and $and$ls180.v:6305$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6305$1956_Y + connect \B $eq$ls180.v:6305$1957_Y + connect \Y $and$ls180.v:6305$1958_Y + end + attribute \src "ls180.v:6306.42-6306.100" + cell $and $and$ls180.v:6306$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6306$1959_Y + connect \Y $and$ls180.v:6306$1960_Y + end + attribute \src "ls180.v:6306.41-6306.151" + cell $and $and$ls180.v:6306$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6306$1960_Y + connect \B $eq$ls180.v:6306$1961_Y + connect \Y $and$ls180.v:6306$1962_Y + end + attribute \src "ls180.v:6308.42-6308.97" + cell $and $and$ls180.v:6308$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6308$1963_Y + end + attribute \src "ls180.v:6308.41-6308.148" + cell $and $and$ls180.v:6308$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6308$1963_Y + connect \B $eq$ls180.v:6308$1964_Y + connect \Y $and$ls180.v:6308$1965_Y + end + attribute \src "ls180.v:6309.42-6309.100" + cell $and $and$ls180.v:6309$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6309$1966_Y + connect \Y $and$ls180.v:6309$1967_Y + end + attribute \src "ls180.v:6309.41-6309.151" + cell $and $and$ls180.v:6309$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6309$1967_Y + connect \B $eq$ls180.v:6309$1968_Y + connect \Y $and$ls180.v:6309$1969_Y + end + attribute \src "ls180.v:6311.40-6311.95" + cell $and $and$ls180.v:6311$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6311$1970_Y + end + attribute \src "ls180.v:6311.39-6311.146" + cell $and $and$ls180.v:6311$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6311$1970_Y + connect \B $eq$ls180.v:6311$1971_Y + connect \Y $and$ls180.v:6311$1972_Y + end + attribute \src "ls180.v:6312.40-6312.98" + cell $and $and$ls180.v:6312$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6312$1973_Y + connect \Y $and$ls180.v:6312$1974_Y + end + attribute \src "ls180.v:6312.39-6312.149" + cell $and $and$ls180.v:6312$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6312$1974_Y + connect \B $eq$ls180.v:6312$1975_Y + connect \Y $and$ls180.v:6312$1976_Y + end + attribute \src "ls180.v:6314.39-6314.94" + cell $and $and$ls180.v:6314$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6314$1977_Y + end + attribute \src "ls180.v:6314.38-6314.145" + cell $and $and$ls180.v:6314$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6314$1977_Y + connect \B $eq$ls180.v:6314$1978_Y + connect \Y $and$ls180.v:6314$1979_Y + end + attribute \src "ls180.v:6315.39-6315.97" + cell $and $and$ls180.v:6315$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6315$1980_Y + connect \Y $and$ls180.v:6315$1981_Y + end + attribute \src "ls180.v:6315.38-6315.148" + cell $and $and$ls180.v:6315$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6315$1981_Y + connect \B $eq$ls180.v:6315$1982_Y + connect \Y $and$ls180.v:6315$1983_Y + end + attribute \src "ls180.v:6317.38-6317.93" + cell $and $and$ls180.v:6317$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6317$1984_Y + end + attribute \src "ls180.v:6317.37-6317.144" + cell $and $and$ls180.v:6317$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6317$1984_Y + connect \B $eq$ls180.v:6317$1985_Y + connect \Y $and$ls180.v:6317$1986_Y + end + attribute \src "ls180.v:6318.38-6318.96" + cell $and $and$ls180.v:6318$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6318$1987_Y + connect \Y $and$ls180.v:6318$1988_Y + end + attribute \src "ls180.v:6318.37-6318.147" + cell $and $and$ls180.v:6318$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6318$1988_Y + connect \B $eq$ls180.v:6318$1989_Y + connect \Y $and$ls180.v:6318$1990_Y + end + attribute \src "ls180.v:6320.37-6320.92" + cell $and $and$ls180.v:6320$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6320$1991_Y + end + attribute \src "ls180.v:6320.36-6320.143" + cell $and $and$ls180.v:6320$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6320$1991_Y + connect \B $eq$ls180.v:6320$1992_Y + connect \Y $and$ls180.v:6320$1993_Y + end + attribute \src "ls180.v:6321.37-6321.95" + cell $and $and$ls180.v:6321$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6321$1994_Y + connect \Y $and$ls180.v:6321$1995_Y + end + attribute \src "ls180.v:6321.36-6321.146" + cell $and $and$ls180.v:6321$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6321$1995_Y + connect \B $eq$ls180.v:6321$1996_Y + connect \Y $and$ls180.v:6321$1997_Y + end + attribute \src "ls180.v:6323.43-6323.98" + cell $and $and$ls180.v:6323$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6323$1998_Y + end + attribute \src "ls180.v:6323.42-6323.149" + cell $and $and$ls180.v:6323$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6323$1998_Y + connect \B $eq$ls180.v:6323$1999_Y + connect \Y $and$ls180.v:6323$2000_Y + end + attribute \src "ls180.v:6324.43-6324.101" + cell $and $and$ls180.v:6324$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6324$2001_Y + connect \Y $and$ls180.v:6324$2002_Y + end + attribute \src "ls180.v:6324.42-6324.152" + cell $and $and$ls180.v:6324$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6324$2002_Y + connect \B $eq$ls180.v:6324$2003_Y + connect \Y $and$ls180.v:6324$2004_Y + end + attribute \src "ls180.v:6326.46-6326.101" + cell $and $and$ls180.v:6326$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6326$2005_Y + end + attribute \src "ls180.v:6326.45-6326.152" + cell $and $and$ls180.v:6326$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6326$2005_Y + connect \B $eq$ls180.v:6326$2006_Y + connect \Y $and$ls180.v:6326$2007_Y + end + attribute \src "ls180.v:6327.46-6327.104" + cell $and $and$ls180.v:6327$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6327$2008_Y + connect \Y $and$ls180.v:6327$2009_Y + end + attribute \src "ls180.v:6327.45-6327.155" + cell $and $and$ls180.v:6327$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6327$2009_Y + connect \B $eq$ls180.v:6327$2010_Y + connect \Y $and$ls180.v:6327$2011_Y + end + attribute \src "ls180.v:6329.46-6329.101" + cell $and $and$ls180.v:6329$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6329$2012_Y + end + attribute \src "ls180.v:6329.45-6329.152" + cell $and $and$ls180.v:6329$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6329$2012_Y + connect \B $eq$ls180.v:6329$2013_Y + connect \Y $and$ls180.v:6329$2014_Y + end + attribute \src "ls180.v:6330.46-6330.104" + cell $and $and$ls180.v:6330$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6330$2015_Y + connect \Y $and$ls180.v:6330$2016_Y + end + attribute \src "ls180.v:6330.45-6330.155" + cell $and $and$ls180.v:6330$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6330$2016_Y + connect \B $eq$ls180.v:6330$2017_Y + connect \Y $and$ls180.v:6330$2018_Y + end + attribute \src "ls180.v:6353.39-6353.94" + cell $and $and$ls180.v:6353$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6353$2021_Y + end + attribute \src "ls180.v:6353.38-6353.145" + cell $and $and$ls180.v:6353$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6353$2021_Y + connect \B $eq$ls180.v:6353$2022_Y + connect \Y $and$ls180.v:6353$2023_Y + end + attribute \src "ls180.v:6354.39-6354.97" + cell $and $and$ls180.v:6354$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6354$2024_Y + connect \Y $and$ls180.v:6354$2025_Y + end + attribute \src "ls180.v:6354.38-6354.148" + cell $and $and$ls180.v:6354$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6354$2025_Y + connect \B $eq$ls180.v:6354$2026_Y + connect \Y $and$ls180.v:6354$2027_Y + end + attribute \src "ls180.v:6356.39-6356.94" + cell $and $and$ls180.v:6356$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6356$2028_Y + end + attribute \src "ls180.v:6356.38-6356.145" + cell $and $and$ls180.v:6356$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6356$2028_Y + connect \B $eq$ls180.v:6356$2029_Y + connect \Y $and$ls180.v:6356$2030_Y + end + attribute \src "ls180.v:6357.39-6357.97" + cell $and $and$ls180.v:6357$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6357$2031_Y + connect \Y $and$ls180.v:6357$2032_Y + end + attribute \src "ls180.v:6357.38-6357.148" + cell $and $and$ls180.v:6357$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6357$2032_Y + connect \B $eq$ls180.v:6357$2033_Y + connect \Y $and$ls180.v:6357$2034_Y + end + attribute \src "ls180.v:6359.39-6359.94" + cell $and $and$ls180.v:6359$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6359$2035_Y + end + attribute \src "ls180.v:6359.38-6359.145" + cell $and $and$ls180.v:6359$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6359$2035_Y + connect \B $eq$ls180.v:6359$2036_Y + connect \Y $and$ls180.v:6359$2037_Y + end + attribute \src "ls180.v:6360.39-6360.97" + cell $and $and$ls180.v:6360$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6360$2038_Y + connect \Y $and$ls180.v:6360$2039_Y + end + attribute \src "ls180.v:6360.38-6360.148" + cell $and $and$ls180.v:6360$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6360$2039_Y + connect \B $eq$ls180.v:6360$2040_Y + connect \Y $and$ls180.v:6360$2041_Y + end + attribute \src "ls180.v:6362.39-6362.94" + cell $and $and$ls180.v:6362$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6362$2042_Y + end + attribute \src "ls180.v:6362.38-6362.145" + cell $and $and$ls180.v:6362$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6362$2042_Y + connect \B $eq$ls180.v:6362$2043_Y + connect \Y $and$ls180.v:6362$2044_Y + end + attribute \src "ls180.v:6363.39-6363.97" + cell $and $and$ls180.v:6363$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6363$2045_Y + connect \Y $and$ls180.v:6363$2046_Y + end + attribute \src "ls180.v:6363.38-6363.148" + cell $and $and$ls180.v:6363$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6363$2046_Y + connect \B $eq$ls180.v:6363$2047_Y + connect \Y $and$ls180.v:6363$2048_Y + end + attribute \src "ls180.v:6365.41-6365.96" + cell $and $and$ls180.v:6365$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6365$2049_Y + end + attribute \src "ls180.v:6365.40-6365.147" + cell $and $and$ls180.v:6365$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6365$2049_Y + connect \B $eq$ls180.v:6365$2050_Y + connect \Y $and$ls180.v:6365$2051_Y + end + attribute \src "ls180.v:6366.41-6366.99" + cell $and $and$ls180.v:6366$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6366$2052_Y + connect \Y $and$ls180.v:6366$2053_Y + end + attribute \src "ls180.v:6366.40-6366.150" + cell $and $and$ls180.v:6366$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6366$2053_Y + connect \B $eq$ls180.v:6366$2054_Y + connect \Y $and$ls180.v:6366$2055_Y + end + attribute \src "ls180.v:6368.41-6368.96" + cell $and $and$ls180.v:6368$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6368$2056_Y + end + attribute \src "ls180.v:6368.40-6368.147" + cell $and $and$ls180.v:6368$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6368$2056_Y + connect \B $eq$ls180.v:6368$2057_Y + connect \Y $and$ls180.v:6368$2058_Y + end + attribute \src "ls180.v:6369.41-6369.99" + cell $and $and$ls180.v:6369$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6369$2059_Y + connect \Y $and$ls180.v:6369$2060_Y + end + attribute \src "ls180.v:6369.40-6369.150" + cell $and $and$ls180.v:6369$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6369$2060_Y + connect \B $eq$ls180.v:6369$2061_Y + connect \Y $and$ls180.v:6369$2062_Y + end + attribute \src "ls180.v:6371.41-6371.96" + cell $and $and$ls180.v:6371$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6371$2063_Y + end + attribute \src "ls180.v:6371.40-6371.147" + cell $and $and$ls180.v:6371$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6371$2063_Y + connect \B $eq$ls180.v:6371$2064_Y + connect \Y $and$ls180.v:6371$2065_Y + end + attribute \src "ls180.v:6372.41-6372.99" + cell $and $and$ls180.v:6372$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6372$2066_Y + connect \Y $and$ls180.v:6372$2067_Y + end + attribute \src "ls180.v:6372.40-6372.150" + cell $and $and$ls180.v:6372$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6372$2067_Y + connect \B $eq$ls180.v:6372$2068_Y + connect \Y $and$ls180.v:6372$2069_Y + end + attribute \src "ls180.v:6374.41-6374.96" + cell $and $and$ls180.v:6374$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6374$2070_Y + end + attribute \src "ls180.v:6374.40-6374.147" + cell $and $and$ls180.v:6374$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6374$2070_Y + connect \B $eq$ls180.v:6374$2071_Y + connect \Y $and$ls180.v:6374$2072_Y + end + attribute \src "ls180.v:6375.41-6375.99" + cell $and $and$ls180.v:6375$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6375$2073_Y + connect \Y $and$ls180.v:6375$2074_Y + end + attribute \src "ls180.v:6375.40-6375.150" + cell $and $and$ls180.v:6375$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6375$2074_Y + connect \B $eq$ls180.v:6375$2075_Y + connect \Y $and$ls180.v:6375$2076_Y + end + attribute \src "ls180.v:6377.37-6377.92" + cell $and $and$ls180.v:6377$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6377$2077_Y + end + attribute \src "ls180.v:6377.36-6377.143" + cell $and $and$ls180.v:6377$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6377$2077_Y + connect \B $eq$ls180.v:6377$2078_Y + connect \Y $and$ls180.v:6377$2079_Y + end + attribute \src "ls180.v:6378.37-6378.95" + cell $and $and$ls180.v:6378$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6378$2080_Y + connect \Y $and$ls180.v:6378$2081_Y + end + attribute \src "ls180.v:6378.36-6378.146" + cell $and $and$ls180.v:6378$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6378$2081_Y + connect \B $eq$ls180.v:6378$2082_Y + connect \Y $and$ls180.v:6378$2083_Y + end + attribute \src "ls180.v:6380.47-6380.102" + cell $and $and$ls180.v:6380$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6380$2084_Y + end + attribute \src "ls180.v:6380.46-6380.153" + cell $and $and$ls180.v:6380$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6380$2084_Y + connect \B $eq$ls180.v:6380$2085_Y + connect \Y $and$ls180.v:6380$2086_Y + end + attribute \src "ls180.v:6381.47-6381.105" + cell $and $and$ls180.v:6381$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6381$2087_Y + connect \Y $and$ls180.v:6381$2088_Y + end + attribute \src "ls180.v:6381.46-6381.156" + cell $and $and$ls180.v:6381$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6381$2088_Y + connect \B $eq$ls180.v:6381$2089_Y + connect \Y $and$ls180.v:6381$2090_Y + end + attribute \src "ls180.v:6383.40-6383.95" + cell $and $and$ls180.v:6383$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6383$2091_Y + end + attribute \src "ls180.v:6383.39-6383.147" + cell $and $and$ls180.v:6383$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6383$2091_Y + connect \B $eq$ls180.v:6383$2092_Y + connect \Y $and$ls180.v:6383$2093_Y + end + attribute \src "ls180.v:6384.40-6384.98" + cell $and $and$ls180.v:6384$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6384$2094_Y + connect \Y $and$ls180.v:6384$2095_Y + end + attribute \src "ls180.v:6384.39-6384.150" + cell $and $and$ls180.v:6384$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6384$2095_Y + connect \B $eq$ls180.v:6384$2096_Y + connect \Y $and$ls180.v:6384$2097_Y + end + attribute \src "ls180.v:6386.40-6386.95" + cell $and $and$ls180.v:6386$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6386$2098_Y + end + attribute \src "ls180.v:6386.39-6386.147" + cell $and $and$ls180.v:6386$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6386$2098_Y + connect \B $eq$ls180.v:6386$2099_Y + connect \Y $and$ls180.v:6386$2100_Y + end + attribute \src "ls180.v:6387.40-6387.98" + cell $and $and$ls180.v:6387$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6387$2101_Y + connect \Y $and$ls180.v:6387$2102_Y + end + attribute \src "ls180.v:6387.39-6387.150" + cell $and $and$ls180.v:6387$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6387$2102_Y + connect \B $eq$ls180.v:6387$2103_Y + connect \Y $and$ls180.v:6387$2104_Y + end + attribute \src "ls180.v:6389.40-6389.95" + cell $and $and$ls180.v:6389$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6389$2105_Y + end + attribute \src "ls180.v:6389.39-6389.147" + cell $and $and$ls180.v:6389$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6389$2105_Y + connect \B $eq$ls180.v:6389$2106_Y + connect \Y $and$ls180.v:6389$2107_Y + end + attribute \src "ls180.v:6390.40-6390.98" + cell $and $and$ls180.v:6390$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6390$2108_Y + connect \Y $and$ls180.v:6390$2109_Y + end + attribute \src "ls180.v:6390.39-6390.150" + cell $and $and$ls180.v:6390$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6390$2109_Y + connect \B $eq$ls180.v:6390$2110_Y + connect \Y $and$ls180.v:6390$2111_Y + end + attribute \src "ls180.v:6392.40-6392.95" + cell $and $and$ls180.v:6392$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6392$2112_Y + end + attribute \src "ls180.v:6392.39-6392.147" + cell $and $and$ls180.v:6392$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6392$2112_Y + connect \B $eq$ls180.v:6392$2113_Y + connect \Y $and$ls180.v:6392$2114_Y + end + attribute \src "ls180.v:6393.40-6393.98" + cell $and $and$ls180.v:6393$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6393$2115_Y + connect \Y $and$ls180.v:6393$2116_Y + end + attribute \src "ls180.v:6393.39-6393.150" + cell $and $and$ls180.v:6393$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6393$2116_Y + connect \B $eq$ls180.v:6393$2117_Y + connect \Y $and$ls180.v:6393$2118_Y + end + attribute \src "ls180.v:6395.52-6395.107" + cell $and $and$ls180.v:6395$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6395$2119_Y + end + attribute \src "ls180.v:6395.51-6395.159" + cell $and $and$ls180.v:6395$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6395$2119_Y + connect \B $eq$ls180.v:6395$2120_Y + connect \Y $and$ls180.v:6395$2121_Y + end + attribute \src "ls180.v:6396.52-6396.110" + cell $and $and$ls180.v:6396$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6396$2122_Y + connect \Y $and$ls180.v:6396$2123_Y + end + attribute \src "ls180.v:6396.51-6396.162" + cell $and $and$ls180.v:6396$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6396$2123_Y + connect \B $eq$ls180.v:6396$2124_Y + connect \Y $and$ls180.v:6396$2125_Y + end + attribute \src "ls180.v:6398.53-6398.108" + cell $and $and$ls180.v:6398$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6398$2126_Y + end + attribute \src "ls180.v:6398.52-6398.160" + cell $and $and$ls180.v:6398$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6398$2126_Y + connect \B $eq$ls180.v:6398$2127_Y + connect \Y $and$ls180.v:6398$2128_Y + end + attribute \src "ls180.v:6399.53-6399.111" + cell $and $and$ls180.v:6399$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6399$2129_Y + connect \Y $and$ls180.v:6399$2130_Y + end + attribute \src "ls180.v:6399.52-6399.163" + cell $and $and$ls180.v:6399$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6399$2130_Y + connect \B $eq$ls180.v:6399$2131_Y + connect \Y $and$ls180.v:6399$2132_Y + end + attribute \src "ls180.v:6401.44-6401.99" + cell $and $and$ls180.v:6401$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6401$2133_Y + end + attribute \src "ls180.v:6401.43-6401.151" + cell $and $and$ls180.v:6401$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6401$2133_Y + connect \B $eq$ls180.v:6401$2134_Y + connect \Y $and$ls180.v:6401$2135_Y + end + attribute \src "ls180.v:6402.44-6402.102" + cell $and $and$ls180.v:6402$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6402$2136_Y + connect \Y $and$ls180.v:6402$2137_Y + end + attribute \src "ls180.v:6402.43-6402.154" + cell $and $and$ls180.v:6402$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6402$2137_Y + connect \B $eq$ls180.v:6402$2138_Y + connect \Y $and$ls180.v:6402$2139_Y + end + attribute \src "ls180.v:6421.30-6421.85" + cell $and $and$ls180.v:6421$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6421$2141_Y + end + attribute \src "ls180.v:6421.29-6421.136" + cell $and $and$ls180.v:6421$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6421$2141_Y + connect \B $eq$ls180.v:6421$2142_Y + connect \Y $and$ls180.v:6421$2143_Y + end + attribute \src "ls180.v:6422.30-6422.88" + cell $and $and$ls180.v:6422$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6422$2144_Y + connect \Y $and$ls180.v:6422$2145_Y + end + attribute \src "ls180.v:6422.29-6422.139" + cell $and $and$ls180.v:6422$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6422$2145_Y + connect \B $eq$ls180.v:6422$2146_Y + connect \Y $and$ls180.v:6422$2147_Y + end + attribute \src "ls180.v:6424.40-6424.95" + cell $and $and$ls180.v:6424$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6424$2148_Y + end + attribute \src "ls180.v:6424.39-6424.146" + cell $and $and$ls180.v:6424$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6424$2148_Y + connect \B $eq$ls180.v:6424$2149_Y + connect \Y $and$ls180.v:6424$2150_Y + end + attribute \src "ls180.v:6425.40-6425.98" + cell $and $and$ls180.v:6425$2152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6425$2151_Y + connect \Y $and$ls180.v:6425$2152_Y + end + attribute \src "ls180.v:6425.39-6425.149" + cell $and $and$ls180.v:6425$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6425$2152_Y + connect \B $eq$ls180.v:6425$2153_Y + connect \Y $and$ls180.v:6425$2154_Y + end + attribute \src "ls180.v:6427.41-6427.96" + cell $and $and$ls180.v:6427$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6427$2155_Y + end + attribute \src "ls180.v:6427.40-6427.147" + cell $and $and$ls180.v:6427$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6427$2155_Y + connect \B $eq$ls180.v:6427$2156_Y + connect \Y $and$ls180.v:6427$2157_Y + end + attribute \src "ls180.v:6428.41-6428.99" + cell $and $and$ls180.v:6428$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6428$2158_Y + connect \Y $and$ls180.v:6428$2159_Y + end + attribute \src "ls180.v:6428.40-6428.150" + cell $and $and$ls180.v:6428$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6428$2159_Y + connect \B $eq$ls180.v:6428$2160_Y + connect \Y $and$ls180.v:6428$2161_Y + end + attribute \src "ls180.v:6430.45-6430.100" + cell $and $and$ls180.v:6430$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6430$2162_Y + end + attribute \src "ls180.v:6430.44-6430.151" + cell $and $and$ls180.v:6430$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6430$2162_Y + connect \B $eq$ls180.v:6430$2163_Y + connect \Y $and$ls180.v:6430$2164_Y + end + attribute \src "ls180.v:6431.45-6431.103" + cell $and $and$ls180.v:6431$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6431$2165_Y + connect \Y $and$ls180.v:6431$2166_Y + end + attribute \src "ls180.v:6431.44-6431.154" + cell $and $and$ls180.v:6431$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6431$2166_Y + connect \B $eq$ls180.v:6431$2167_Y + connect \Y $and$ls180.v:6431$2168_Y + end + attribute \src "ls180.v:6433.46-6433.101" + cell $and $and$ls180.v:6433$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6433$2169_Y + end + attribute \src "ls180.v:6433.45-6433.152" + cell $and $and$ls180.v:6433$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6433$2169_Y + connect \B $eq$ls180.v:6433$2170_Y + connect \Y $and$ls180.v:6433$2171_Y + end + attribute \src "ls180.v:6434.46-6434.104" + cell $and $and$ls180.v:6434$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6434$2172_Y + connect \Y $and$ls180.v:6434$2173_Y + end + attribute \src "ls180.v:6434.45-6434.155" + cell $and $and$ls180.v:6434$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6434$2173_Y + connect \B $eq$ls180.v:6434$2174_Y + connect \Y $and$ls180.v:6434$2175_Y + end + attribute \src "ls180.v:6436.44-6436.99" + cell $and $and$ls180.v:6436$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6436$2176_Y + end + attribute \src "ls180.v:6436.43-6436.150" + cell $and $and$ls180.v:6436$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6436$2176_Y + connect \B $eq$ls180.v:6436$2177_Y + connect \Y $and$ls180.v:6436$2178_Y + end + attribute \src "ls180.v:6437.44-6437.102" + cell $and $and$ls180.v:6437$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6437$2179_Y + connect \Y $and$ls180.v:6437$2180_Y + end + attribute \src "ls180.v:6437.43-6437.153" + cell $and $and$ls180.v:6437$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6437$2180_Y + connect \B $eq$ls180.v:6437$2181_Y + connect \Y $and$ls180.v:6437$2182_Y + end + attribute \src "ls180.v:6439.41-6439.96" + cell $and $and$ls180.v:6439$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6439$2183_Y + end + attribute \src "ls180.v:6439.40-6439.147" + cell $and $and$ls180.v:6439$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6439$2183_Y + connect \B $eq$ls180.v:6439$2184_Y + connect \Y $and$ls180.v:6439$2185_Y + end + attribute \src "ls180.v:6440.41-6440.99" + cell $and $and$ls180.v:6440$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6440$2186_Y + connect \Y $and$ls180.v:6440$2187_Y + end + attribute \src "ls180.v:6440.40-6440.150" + cell $and $and$ls180.v:6440$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6440$2187_Y + connect \B $eq$ls180.v:6440$2188_Y + connect \Y $and$ls180.v:6440$2189_Y + end + attribute \src "ls180.v:6442.40-6442.95" + cell $and $and$ls180.v:6442$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6442$2190_Y + end + attribute \src "ls180.v:6442.39-6442.146" + cell $and $and$ls180.v:6442$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6442$2190_Y + connect \B $eq$ls180.v:6442$2191_Y + connect \Y $and$ls180.v:6442$2192_Y + end + attribute \src "ls180.v:6443.40-6443.98" + cell $and $and$ls180.v:6443$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6443$2193_Y + connect \Y $and$ls180.v:6443$2194_Y + end + attribute \src "ls180.v:6443.39-6443.149" + cell $and $and$ls180.v:6443$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6443$2194_Y + connect \B $eq$ls180.v:6443$2195_Y + connect \Y $and$ls180.v:6443$2196_Y + end + attribute \src "ls180.v:6455.46-6455.101" + cell $and $and$ls180.v:6455$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6455$2198_Y + end + attribute \src "ls180.v:6455.45-6455.152" + cell $and $and$ls180.v:6455$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6455$2198_Y + connect \B $eq$ls180.v:6455$2199_Y + connect \Y $and$ls180.v:6455$2200_Y + end + attribute \src "ls180.v:6456.46-6456.104" + cell $and $and$ls180.v:6456$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6456$2201_Y + connect \Y $and$ls180.v:6456$2202_Y + end + attribute \src "ls180.v:6456.45-6456.155" + cell $and $and$ls180.v:6456$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6456$2202_Y + connect \B $eq$ls180.v:6456$2203_Y + connect \Y $and$ls180.v:6456$2204_Y + end + attribute \src "ls180.v:6458.46-6458.101" + cell $and $and$ls180.v:6458$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6458$2205_Y + end + attribute \src "ls180.v:6458.45-6458.152" + cell $and $and$ls180.v:6458$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6458$2205_Y + connect \B $eq$ls180.v:6458$2206_Y + connect \Y $and$ls180.v:6458$2207_Y + end + attribute \src "ls180.v:6459.46-6459.104" + cell $and $and$ls180.v:6459$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6459$2208_Y + connect \Y $and$ls180.v:6459$2209_Y + end + attribute \src "ls180.v:6459.45-6459.155" + cell $and $and$ls180.v:6459$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6459$2209_Y + connect \B $eq$ls180.v:6459$2210_Y + connect \Y $and$ls180.v:6459$2211_Y + end + attribute \src "ls180.v:6461.46-6461.101" + cell $and $and$ls180.v:6461$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6461$2212_Y + end + attribute \src "ls180.v:6461.45-6461.152" + cell $and $and$ls180.v:6461$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6461$2212_Y + connect \B $eq$ls180.v:6461$2213_Y + connect \Y $and$ls180.v:6461$2214_Y + end + attribute \src "ls180.v:6462.46-6462.104" + cell $and $and$ls180.v:6462$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6462$2215_Y + connect \Y $and$ls180.v:6462$2216_Y + end + attribute \src "ls180.v:6462.45-6462.155" + cell $and $and$ls180.v:6462$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6462$2216_Y + connect \B $eq$ls180.v:6462$2217_Y + connect \Y $and$ls180.v:6462$2218_Y + end + attribute \src "ls180.v:6464.46-6464.101" + cell $and $and$ls180.v:6464$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6464$2219_Y + end + attribute \src "ls180.v:6464.45-6464.152" + cell $and $and$ls180.v:6464$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6464$2219_Y + connect \B $eq$ls180.v:6464$2220_Y + connect \Y $and$ls180.v:6464$2221_Y + end + attribute \src "ls180.v:6465.46-6465.104" + cell $and $and$ls180.v:6465$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6465$2222_Y + connect \Y $and$ls180.v:6465$2223_Y + end + attribute \src "ls180.v:6465.45-6465.155" + cell $and $and$ls180.v:6465$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6465$2223_Y + connect \B $eq$ls180.v:6465$2224_Y + connect \Y $and$ls180.v:6465$2225_Y + end + attribute \src "ls180.v:6846.109-6846.178" + cell $and $and$ls180.v:6846$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6846$2262_Y + connect \Y $and$ls180.v:6846$2263_Y + end + attribute \src "ls180.v:6846.184-6846.253" + cell $and $and$ls180.v:6846$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6846$2265_Y + connect \Y $and$ls180.v:6846$2266_Y + end + attribute \src "ls180.v:6846.259-6846.328" + cell $and $and$ls180.v:6846$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6846$2268_Y + connect \Y $and$ls180.v:6846$2269_Y + end + attribute \src "ls180.v:6846.40-6846.331" + cell $and $and$ls180.v:6846$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6846$2261_Y + connect \B $not$ls180.v:6846$2271_Y + connect \Y $and$ls180.v:6846$2272_Y + end + attribute \src "ls180.v:6846.39-6846.354" + cell $and $and$ls180.v:6846$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6846$2272_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6846$2273_Y + end + attribute \src "ls180.v:6870.109-6870.178" + cell $and $and$ls180.v:6870$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6870$2278_Y + connect \Y $and$ls180.v:6870$2279_Y + end + attribute \src "ls180.v:6870.184-6870.253" + cell $and $and$ls180.v:6870$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6870$2281_Y + connect \Y $and$ls180.v:6870$2282_Y + end + attribute \src "ls180.v:6870.259-6870.328" + cell $and $and$ls180.v:6870$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6870$2284_Y + connect \Y $and$ls180.v:6870$2285_Y + end + attribute \src "ls180.v:6870.40-6870.331" + cell $and $and$ls180.v:6870$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6870$2277_Y + connect \B $not$ls180.v:6870$2287_Y + connect \Y $and$ls180.v:6870$2288_Y + end + attribute \src "ls180.v:6870.39-6870.354" + cell $and $and$ls180.v:6870$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6870$2288_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6870$2289_Y + end + attribute \src "ls180.v:6894.109-6894.178" + cell $and $and$ls180.v:6894$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6894$2294_Y + connect \Y $and$ls180.v:6894$2295_Y + end + attribute \src "ls180.v:6894.184-6894.253" + cell $and $and$ls180.v:6894$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6894$2297_Y + connect \Y $and$ls180.v:6894$2298_Y + end + attribute \src "ls180.v:6894.259-6894.328" + cell $and $and$ls180.v:6894$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:6894$2300_Y + connect \Y $and$ls180.v:6894$2301_Y + end + attribute \src "ls180.v:6894.40-6894.331" + cell $and $and$ls180.v:6894$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6894$2293_Y + connect \B $not$ls180.v:6894$2303_Y + connect \Y $and$ls180.v:6894$2304_Y + end + attribute \src "ls180.v:6894.39-6894.354" + cell $and $and$ls180.v:6894$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6894$2304_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6894$2305_Y + end + attribute \src "ls180.v:6918.109-6918.178" + cell $and $and$ls180.v:6918$2311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:6918$2310_Y + connect \Y $and$ls180.v:6918$2311_Y + end + attribute \src "ls180.v:6918.184-6918.253" + cell $and $and$ls180.v:6918$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:6918$2313_Y + connect \Y $and$ls180.v:6918$2314_Y + end + attribute \src "ls180.v:6918.259-6918.328" + cell $and $and$ls180.v:6918$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:6918$2316_Y + connect \Y $and$ls180.v:6918$2317_Y + end + attribute \src "ls180.v:6918.40-6918.331" + cell $and $and$ls180.v:6918$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:6918$2309_Y + connect \B $not$ls180.v:6918$2319_Y + connect \Y $and$ls180.v:6918$2320_Y + end + attribute \src "ls180.v:6918.39-6918.354" + cell $and $and$ls180.v:6918$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6918$2320_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:6918$2321_Y + end + attribute \src "ls180.v:7123.39-7123.104" + cell $and $and$ls180.v:7123$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7123$2333_Y + end + attribute \src "ls180.v:7123.38-7123.145" + cell $and $and$ls180.v:7123$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7123$2333_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7123$2334_Y + end + attribute \src "ls180.v:7126.39-7126.104" + cell $and $and$ls180.v:7126$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7126$2335_Y + end + attribute \src "ls180.v:7126.38-7126.145" + cell $and $and$ls180.v:7126$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7126$2335_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7126$2336_Y + end + attribute \src "ls180.v:7129.39-7129.82" + cell $and $and$ls180.v:7129$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7129$2337_Y + end + attribute \src "ls180.v:7129.38-7129.112" + cell $and $and$ls180.v:7129$2338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7129$2337_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7129$2338_Y + end + attribute \src "ls180.v:7140.39-7140.104" + cell $and $and$ls180.v:7140$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7140$2340_Y + end + attribute \src "ls180.v:7140.38-7140.145" + cell $and $and$ls180.v:7140$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7140$2340_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7140$2341_Y + end + attribute \src "ls180.v:7143.39-7143.104" + cell $and $and$ls180.v:7143$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7143$2342_Y + end + attribute \src "ls180.v:7143.38-7143.145" + cell $and $and$ls180.v:7143$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7143$2342_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7143$2343_Y + end + attribute \src "ls180.v:7146.39-7146.82" + cell $and $and$ls180.v:7146$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7146$2344_Y + end + attribute \src "ls180.v:7146.38-7146.112" + cell $and $and$ls180.v:7146$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7146$2344_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7146$2345_Y + end + attribute \src "ls180.v:7157.39-7157.104" + cell $and $and$ls180.v:7157$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7157$2347_Y + end + attribute \src "ls180.v:7157.38-7157.144" + cell $and $and$ls180.v:7157$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7157$2347_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7157$2348_Y + end + attribute \src "ls180.v:7160.39-7160.104" + cell $and $and$ls180.v:7160$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7160$2349_Y + end + attribute \src "ls180.v:7160.38-7160.144" + cell $and $and$ls180.v:7160$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7160$2349_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7160$2350_Y + end + attribute \src "ls180.v:7163.39-7163.82" + cell $and $and$ls180.v:7163$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7163$2351_Y + end + attribute \src "ls180.v:7163.38-7163.111" + cell $and $and$ls180.v:7163$2352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7163$2351_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7163$2352_Y + end + attribute \src "ls180.v:7174.39-7174.104" + cell $and $and$ls180.v:7174$2354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7174$2354_Y + end + attribute \src "ls180.v:7174.38-7174.149" + cell $and $and$ls180.v:7174$2355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7174$2354_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7174$2355_Y + end + attribute \src "ls180.v:7177.39-7177.104" + cell $and $and$ls180.v:7177$2356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7177$2356_Y + end + attribute \src "ls180.v:7177.38-7177.149" + cell $and $and$ls180.v:7177$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7177$2356_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7177$2357_Y + end + attribute \src "ls180.v:7180.39-7180.82" + cell $and $and$ls180.v:7180$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7180$2358_Y + end + attribute \src "ls180.v:7180.38-7180.116" + cell $and $and$ls180.v:7180$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7180$2358_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7180$2359_Y + end + attribute \src "ls180.v:7191.39-7191.104" + cell $and $and$ls180.v:7191$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7191$2361_Y + end + attribute \src "ls180.v:7191.38-7191.150" + cell $and $and$ls180.v:7191$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7191$2361_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7191$2362_Y + end + attribute \src "ls180.v:7194.39-7194.104" + cell $and $and$ls180.v:7194$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7194$2363_Y + end + attribute \src "ls180.v:7194.38-7194.150" + cell $and $and$ls180.v:7194$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7194$2363_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7194$2364_Y + end + attribute \src "ls180.v:7197.39-7197.82" + cell $and $and$ls180.v:7197$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7197$2365_Y + end + attribute \src "ls180.v:7197.38-7197.117" + cell $and $and$ls180.v:7197$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7197$2365_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7197$2366_Y + end + attribute \src "ls180.v:7416.17-7416.67" + cell $and $and$ls180.v:7416$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7416$2372_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7416$2373_Y + end + attribute \src "ls180.v:7507.8-7507.67" + cell $and $and$ls180.v:7507$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7507$2416_Y + end + attribute \src "ls180.v:7507.7-7507.102" + cell $and $and$ls180.v:7507$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7507$2416_Y + connect \B $not$ls180.v:7507$2417_Y + connect \Y $and$ls180.v:7507$2418_Y + end + attribute \src "ls180.v:7526.7-7526.75" + cell $and $and$ls180.v:7526$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7526$2421_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7526$2422_Y + end + attribute \src "ls180.v:7534.7-7534.56" + cell $and $and$ls180.v:7534$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7534$2423_Y + connect \Y $and$ls180.v:7534$2424_Y + end + attribute \src "ls180.v:7562.7-7562.75" + cell $and $and$ls180.v:7562$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7562$2430_Y + connect \Y $and$ls180.v:7562$2431_Y + end + attribute \src "ls180.v:7604.8-7604.131" + cell $and $and$ls180.v:7604$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7604$2437_Y + end + attribute \src "ls180.v:7604.7-7604.190" + cell $and $and$ls180.v:7604$2439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7604$2437_Y + connect \B $not$ls180.v:7604$2438_Y + connect \Y $and$ls180.v:7604$2439_Y + end + attribute \src "ls180.v:7610.8-7610.131" + cell $and $and$ls180.v:7610$2442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7610$2442_Y + end + attribute \src "ls180.v:7610.7-7610.190" + cell $and $and$ls180.v:7610$2444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7610$2442_Y + connect \B $not$ls180.v:7610$2443_Y + connect \Y $and$ls180.v:7610$2444_Y + end + attribute \src "ls180.v:7650.8-7650.131" + cell $and $and$ls180.v:7650$2453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7650$2453_Y + end + attribute \src "ls180.v:7650.7-7650.190" + cell $and $and$ls180.v:7650$2455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7650$2453_Y + connect \B $not$ls180.v:7650$2454_Y + connect \Y $and$ls180.v:7650$2455_Y + end + attribute \src "ls180.v:7656.8-7656.131" + cell $and $and$ls180.v:7656$2458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7656$2458_Y + end + attribute \src "ls180.v:7656.7-7656.190" + cell $and $and$ls180.v:7656$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7656$2458_Y + connect \B $not$ls180.v:7656$2459_Y + connect \Y $and$ls180.v:7656$2460_Y + end + attribute \src "ls180.v:7696.8-7696.131" + cell $and $and$ls180.v:7696$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7696$2469_Y + end + attribute \src "ls180.v:7696.7-7696.190" + cell $and $and$ls180.v:7696$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7696$2469_Y + connect \B $not$ls180.v:7696$2470_Y + connect \Y $and$ls180.v:7696$2471_Y + end + attribute \src "ls180.v:7702.8-7702.131" + cell $and $and$ls180.v:7702$2474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7702$2474_Y + end + attribute \src "ls180.v:7702.7-7702.190" + cell $and $and$ls180.v:7702$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7702$2474_Y + connect \B $not$ls180.v:7702$2475_Y + connect \Y $and$ls180.v:7702$2476_Y + end + attribute \src "ls180.v:7742.8-7742.131" + cell $and $and$ls180.v:7742$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7742$2485_Y + end + attribute \src "ls180.v:7742.7-7742.190" + cell $and $and$ls180.v:7742$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7742$2485_Y + connect \B $not$ls180.v:7742$2486_Y + connect \Y $and$ls180.v:7742$2487_Y + end + attribute \src "ls180.v:7748.8-7748.131" + cell $and $and$ls180.v:7748$2490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:7748$2490_Y + end + attribute \src "ls180.v:7748.7-7748.190" + cell $and $and$ls180.v:7748$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7748$2490_Y + connect \B $not$ls180.v:7748$2491_Y + connect \Y $and$ls180.v:7748$2492_Y + end + attribute \src "ls180.v:7945.48-7945.124" + cell $and $and$ls180.v:7945$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7945$2516_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:7945$2517_Y + end + attribute \src "ls180.v:7945.130-7945.206" + cell $and $and$ls180.v:7945$2520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7945$2519_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:7945$2520_Y + end + attribute \src "ls180.v:7945.212-7945.288" + cell $and $and$ls180.v:7945$2523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7945$2522_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:7945$2523_Y + end + attribute \src "ls180.v:7945.294-7945.370" + cell $and $and$ls180.v:7945$2526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7945$2525_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:7945$2526_Y + end + attribute \src "ls180.v:7946.49-7946.125" + cell $and $and$ls180.v:7946$2529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7946$2528_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:7946$2529_Y + end + attribute \src "ls180.v:7946.131-7946.207" + cell $and $and$ls180.v:7946$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7946$2531_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:7946$2532_Y + end + attribute \src "ls180.v:7946.213-7946.289" + cell $and $and$ls180.v:7946$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7946$2534_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:7946$2535_Y + end + attribute \src "ls180.v:7946.295-7946.371" + cell $and $and$ls180.v:7946$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7946$2537_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:7946$2538_Y + end + attribute \src "ls180.v:7965.8-7965.49" + cell $and $and$ls180.v:7965$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:7965$2541_Y + end + attribute \src "ls180.v:7968.8-7968.53" + cell $and $and$ls180.v:7968$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:7968$2542_Y + end + attribute \src "ls180.v:7973.8-7973.59" + cell $and $and$ls180.v:7973$2544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_valid + connect \B $not$ls180.v:7973$2543_Y + connect \Y $and$ls180.v:7973$2544_Y + end + attribute \src "ls180.v:7973.7-7973.90" + cell $and $and$ls180.v:7973$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7973$2544_Y + connect \B $not$ls180.v:7973$2545_Y + connect \Y $and$ls180.v:7973$2546_Y + end + attribute \src "ls180.v:7979.8-7979.59" + cell $and $and$ls180.v:7979$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_uart_clk_txen + connect \B \main_uart_phy_tx_busy + connect \Y $and$ls180.v:7979$2547_Y + end + attribute \src "ls180.v:8003.8-8003.48" + cell $and $and$ls180.v:8003$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8003$2553_Y + connect \B \main_uart_phy_rx_r + connect \Y $and$ls180.v:8003$2554_Y + end + attribute \src "ls180.v:8036.7-8036.57" + cell $and $and$ls180.v:8036$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8036$2559_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:8036$2560_Y + end + attribute \src "ls180.v:8043.7-8043.57" + cell $and $and$ls180.v:8043$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8043$2561_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:8043$2562_Y + end + attribute \src "ls180.v:8053.8-8053.75" + cell $and $and$ls180.v:8053$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8053$2563_Y + end + attribute \src "ls180.v:8053.7-8053.107" + cell $and $and$ls180.v:8053$2565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8053$2563_Y + connect \B $not$ls180.v:8053$2564_Y + connect \Y $and$ls180.v:8053$2565_Y + end + attribute \src "ls180.v:8059.8-8059.75" + cell $and $and$ls180.v:8059$2568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8059$2568_Y + end + attribute \src "ls180.v:8059.7-8059.107" + cell $and $and$ls180.v:8059$2570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8059$2568_Y + connect \B $not$ls180.v:8059$2569_Y + connect \Y $and$ls180.v:8059$2570_Y + end + attribute \src "ls180.v:8075.8-8075.75" + cell $and $and$ls180.v:8075$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8075$2574_Y + end + attribute \src "ls180.v:8075.7-8075.107" + cell $and $and$ls180.v:8075$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8075$2574_Y + connect \B $not$ls180.v:8075$2575_Y + connect \Y $and$ls180.v:8075$2576_Y + end + attribute \src "ls180.v:8081.8-8081.75" + cell $and $and$ls180.v:8081$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8081$2579_Y + end + attribute \src "ls180.v:8081.7-8081.107" + cell $and $and$ls180.v:8081$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8081$2579_Y + connect \B $not$ls180.v:8081$2580_Y + connect \Y $and$ls180.v:8081$2581_Y + end + attribute \src "ls180.v:8229.7-8229.96" + cell $and $and$ls180.v:8229$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8229$2609_Y + end + attribute \src "ls180.v:8230.8-8230.93" + cell $and $and$ls180.v:8230$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8230$2610_Y + end + attribute \src "ls180.v:8238.8-8238.93" + cell $and $and$ls180.v:8238$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8238$2611_Y + end + attribute \src "ls180.v:8310.7-8310.98" + cell $and $and$ls180.v:8310$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8310$2621_Y + end + attribute \src "ls180.v:8311.8-8311.95" + cell $and $and$ls180.v:8311$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8311$2622_Y + end + attribute \src "ls180.v:8319.8-8319.95" + cell $and $and$ls180.v:8319$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8319$2623_Y + end + attribute \src "ls180.v:8389.7-8389.100" + cell $and $and$ls180.v:8389$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8389$2633_Y + end + attribute \src "ls180.v:8390.8-8390.97" + cell $and $and$ls180.v:8390$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8390$2634_Y + end + attribute \src "ls180.v:8398.8-8398.97" + cell $and $and$ls180.v:8398$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8398$2635_Y + end + attribute \src "ls180.v:8489.7-8489.82" + cell $and $and$ls180.v:8489$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8489$2641_Y + end + attribute \src "ls180.v:8492.7-8492.82" + cell $and $and$ls180.v:8492$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8492$2642_Y + end + attribute \src "ls180.v:8495.7-8495.82" + cell $and $and$ls180.v:8495$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8495$2643_Y + end + attribute \src "ls180.v:8498.7-8498.82" + cell $and $and$ls180.v:8498$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8498$2644_Y + end + attribute \src "ls180.v:8501.7-8501.82" + cell $and $and$ls180.v:8501$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8501$2645_Y + end + attribute \src "ls180.v:8506.7-8506.82" + cell $and $and$ls180.v:8506$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8506$2646_Y + end + attribute \src "ls180.v:8511.7-8511.82" + cell $and $and$ls180.v:8511$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8511$2647_Y + end + attribute \src "ls180.v:8516.7-8516.82" + cell $and $and$ls180.v:8516$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8516$2648_Y + end + attribute \src "ls180.v:8521.7-8521.82" + cell $and $and$ls180.v:8521$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8521$2649_Y + end + attribute \src "ls180.v:8586.8-8586.83" + cell $and $and$ls180.v:8586$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8586$2652_Y + end + attribute \src "ls180.v:8586.7-8586.119" + cell $and $and$ls180.v:8586$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8586$2652_Y + connect \B $not$ls180.v:8586$2653_Y + connect \Y $and$ls180.v:8586$2654_Y + end + attribute \src "ls180.v:8592.8-8592.83" + cell $and $and$ls180.v:8592$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8592$2657_Y + end + attribute \src "ls180.v:8592.7-8592.119" + cell $and $and$ls180.v:8592$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8592$2657_Y + connect \B $not$ls180.v:8592$2658_Y + connect \Y $and$ls180.v:8592$2659_Y + end + attribute \src "ls180.v:8612.7-8612.88" + cell $and $and$ls180.v:8612$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8612$2666_Y + end + attribute \src "ls180.v:8613.8-8613.85" + cell $and $and$ls180.v:8613$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8613$2667_Y + end + attribute \src "ls180.v:8621.8-8621.85" + cell $and $and$ls180.v:8621$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8621$2668_Y + end + attribute \src "ls180.v:8665.7-8665.88" + cell $and $and$ls180.v:8665$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8665$2672_Y + end + attribute \src "ls180.v:8672.8-8672.83" + cell $and $and$ls180.v:8672$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8672$2674_Y + end + attribute \src "ls180.v:8672.7-8672.119" + cell $and $and$ls180.v:8672$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8672$2674_Y + connect \B $not$ls180.v:8672$2675_Y + connect \Y $and$ls180.v:8672$2676_Y + end + attribute \src "ls180.v:8678.8-8678.83" + cell $and $and$ls180.v:8678$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8678$2679_Y + end + attribute \src "ls180.v:8678.7-8678.119" + cell $and $and$ls180.v:8678$2681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8678$2679_Y + connect \B $not$ls180.v:8678$2680_Y + connect \Y $and$ls180.v:8678$2681_Y + end + attribute \src "ls180.v:2814.42-2814.101" + cell $eq $eq$ls180.v:2814$18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2814$18_Y + end + attribute \src "ls180.v:2821.11-2821.54" + cell $eq $eq$ls180.v:2821$23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2821$23_Y + end + attribute \src "ls180.v:2874.42-2874.101" + cell $eq $eq$ls180.v:2874$29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2874$29_Y + end + attribute \src "ls180.v:2881.11-2881.54" + cell $eq $eq$ls180.v:2881$34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2881$34_Y + end + attribute \src "ls180.v:2934.42-2934.101" + cell $eq $eq$ls180.v:2934$40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2934$40_Y + end + attribute \src "ls180.v:2941.11-2941.54" + cell $eq $eq$ls180.v:2941$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2941$45_Y + end + attribute \src "ls180.v:3127.34-3127.65" + cell $eq $eq$ls180.v:3127$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3127$73_Y + end + attribute \src "ls180.v:3131.68-3131.102" + cell $eq $eq$ls180.v:3131$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3131$76_Y + end + attribute \src "ls180.v:3175.43-3175.134" + cell $eq $eq$ls180.v:3175$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3175$81_Y + end + attribute \src "ls180.v:3192.47-3192.88" + cell $eq $eq$ls180.v:3192$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3192$94_Y + end + attribute \src "ls180.v:3332.43-3332.134" + cell $eq $eq$ls180.v:3332$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3332$111_Y + end + attribute \src "ls180.v:3349.47-3349.88" + cell $eq $eq$ls180.v:3349$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3349$124_Y + end + attribute \src "ls180.v:3489.43-3489.134" + cell $eq $eq$ls180.v:3489$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3489$141_Y + end + attribute \src "ls180.v:3506.47-3506.88" + cell $eq $eq$ls180.v:3506$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3506$154_Y + end + attribute \src "ls180.v:3646.43-3646.134" + cell $eq $eq$ls180.v:3646$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3646$171_Y + end + attribute \src "ls180.v:3663.47-3663.88" + cell $eq $eq$ls180.v:3663$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3663$184_Y + end + attribute \src "ls180.v:3800.32-3800.56" + cell $eq $eq$ls180.v:3800$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3800$231_Y + end + attribute \src "ls180.v:3801.32-3801.56" + cell $eq $eq$ls180.v:3801$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3801$232_Y + end + attribute \src "ls180.v:3812.339-3812.418" + cell $eq $eq$ls180.v:3812$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3812$246_Y + end + attribute \src "ls180.v:3812.423-3812.504" + cell $eq $eq$ls180.v:3812$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3812$247_Y + end + attribute \src "ls180.v:3813.339-3813.418" + cell $eq $eq$ls180.v:3813$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3813$259_Y + end + attribute \src "ls180.v:3813.423-3813.504" + cell $eq $eq$ls180.v:3813$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3813$260_Y + end + attribute \src "ls180.v:3814.339-3814.418" + cell $eq $eq$ls180.v:3814$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3814$272_Y + end + attribute \src "ls180.v:3814.423-3814.504" + cell $eq $eq$ls180.v:3814$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3814$273_Y + end + attribute \src "ls180.v:3815.339-3815.418" + cell $eq $eq$ls180.v:3815$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3815$285_Y + end + attribute \src "ls180.v:3815.423-3815.504" + cell $eq $eq$ls180.v:3815$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3815$286_Y + end + attribute \src "ls180.v:3845.339-3845.418" + cell $eq $eq$ls180.v:3845$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3845$304_Y + end + attribute \src "ls180.v:3845.423-3845.504" + cell $eq $eq$ls180.v:3845$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3845$305_Y + end + attribute \src "ls180.v:3846.339-3846.418" + cell $eq $eq$ls180.v:3846$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3846$317_Y + end + attribute \src "ls180.v:3846.423-3846.504" + cell $eq $eq$ls180.v:3846$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3846$318_Y + end + attribute \src "ls180.v:3847.339-3847.418" + cell $eq $eq$ls180.v:3847$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3847$330_Y + end + attribute \src "ls180.v:3847.423-3847.504" + cell $eq $eq$ls180.v:3847$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3847$331_Y + end + attribute \src "ls180.v:3848.339-3848.418" + cell $eq $eq$ls180.v:3848$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:3848$343_Y + end + attribute \src "ls180.v:3848.423-3848.504" + cell $eq $eq$ls180.v:3848$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:3848$344_Y + end + attribute \src "ls180.v:3877.78-3877.113" + cell $eq $eq$ls180.v:3877$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3877$353_Y + end + attribute \src "ls180.v:3880.78-3880.113" + cell $eq $eq$ls180.v:3880$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3880$356_Y + end + attribute \src "ls180.v:3886.78-3886.113" + cell $eq $eq$ls180.v:3886$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3886$360_Y + end + attribute \src "ls180.v:3889.78-3889.113" + cell $eq $eq$ls180.v:3889$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3889$363_Y + end + attribute \src "ls180.v:3895.78-3895.113" + cell $eq $eq$ls180.v:3895$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3895$367_Y + end + attribute \src "ls180.v:3898.78-3898.113" + cell $eq $eq$ls180.v:3898$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3898$370_Y + end + attribute \src "ls180.v:3904.78-3904.113" + cell $eq $eq$ls180.v:3904$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3904$374_Y + end + attribute \src "ls180.v:3907.78-3907.113" + cell $eq $eq$ls180.v:3907$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:3907$377_Y + end + attribute \src "ls180.v:3988.42-3988.82" + cell $eq $eq$ls180.v:3988$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3988$400_Y + end + attribute \src "ls180.v:3988.145-3988.178" + cell $eq $eq$ls180.v:3988$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$401_Y + end + attribute \src "ls180.v:3988.220-3988.253" + cell $eq $eq$ls180.v:3988$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$404_Y + end + attribute \src "ls180.v:3988.295-3988.328" + cell $eq $eq$ls180.v:3988$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3988$407_Y + end + attribute \src "ls180.v:3993.42-3993.82" + cell $eq $eq$ls180.v:3993$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3993$416_Y + end + attribute \src "ls180.v:3993.145-3993.178" + cell $eq $eq$ls180.v:3993$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3993$417_Y + end + attribute \src "ls180.v:3993.220-3993.253" + cell $eq $eq$ls180.v:3993$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3993$420_Y + end + attribute \src "ls180.v:3993.295-3993.328" + cell $eq $eq$ls180.v:3993$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3993$423_Y + end + attribute \src "ls180.v:3998.42-3998.82" + cell $eq $eq$ls180.v:3998$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3998$432_Y + end + attribute \src "ls180.v:3998.145-3998.178" + cell $eq $eq$ls180.v:3998$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3998$433_Y + end + attribute \src "ls180.v:3998.220-3998.253" + cell $eq $eq$ls180.v:3998$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3998$436_Y + end + attribute \src "ls180.v:3998.295-3998.328" + cell $eq $eq$ls180.v:3998$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3998$439_Y + end + attribute \src "ls180.v:4003.42-4003.82" + cell $eq $eq$ls180.v:4003$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4003$448_Y + end + attribute \src "ls180.v:4003.145-4003.178" + cell $eq $eq$ls180.v:4003$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4003$449_Y + end + attribute \src "ls180.v:4003.220-4003.253" + cell $eq $eq$ls180.v:4003$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4003$452_Y + end + attribute \src "ls180.v:4003.295-4003.328" + cell $eq $eq$ls180.v:4003$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4003$455_Y + end + attribute \src "ls180.v:4008.44-4008.77" + cell $eq $eq$ls180.v:4008$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$464_Y + end + attribute \src "ls180.v:4008.83-4008.123" + cell $eq $eq$ls180.v:4008$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4008$465_Y + end + attribute \src "ls180.v:4008.186-4008.219" + cell $eq $eq$ls180.v:4008$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$466_Y + end + attribute \src "ls180.v:4008.261-4008.294" + cell $eq $eq$ls180.v:4008$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$469_Y + end + attribute \src "ls180.v:4008.336-4008.369" + cell $eq $eq$ls180.v:4008$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$472_Y + end + attribute \src "ls180.v:4008.418-4008.451" + cell $eq $eq$ls180.v:4008$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$480_Y + end + attribute \src "ls180.v:4008.457-4008.497" + cell $eq $eq$ls180.v:4008$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4008$481_Y + end + attribute \src "ls180.v:4008.560-4008.593" + cell $eq $eq$ls180.v:4008$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$482_Y + end + attribute \src "ls180.v:4008.635-4008.668" + cell $eq $eq$ls180.v:4008$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$485_Y + end + attribute \src "ls180.v:4008.710-4008.743" + cell $eq $eq$ls180.v:4008$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$488_Y + end + attribute \src "ls180.v:4008.792-4008.825" + cell $eq $eq$ls180.v:4008$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$496_Y + end + attribute \src "ls180.v:4008.831-4008.871" + cell $eq $eq$ls180.v:4008$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4008$497_Y + end + attribute \src "ls180.v:4008.934-4008.967" + cell $eq $eq$ls180.v:4008$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$498_Y + end + attribute \src "ls180.v:4008.1009-4008.1042" + cell $eq $eq$ls180.v:4008$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$501_Y + end + attribute \src "ls180.v:4008.1084-4008.1117" + cell $eq $eq$ls180.v:4008$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$504_Y + end + attribute \src "ls180.v:4008.1166-4008.1199" + cell $eq $eq$ls180.v:4008$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$512_Y + end + attribute \src "ls180.v:4008.1205-4008.1245" + cell $eq $eq$ls180.v:4008$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4008$513_Y + end + attribute \src "ls180.v:4008.1308-4008.1341" + cell $eq $eq$ls180.v:4008$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$514_Y + end + attribute \src "ls180.v:4008.1383-4008.1416" + cell $eq $eq$ls180.v:4008$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$517_Y + end + attribute \src "ls180.v:4008.1458-4008.1491" + cell $eq $eq$ls180.v:4008$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4008$520_Y + end + attribute \src "ls180.v:4067.29-4067.57" + cell $eq $eq$ls180.v:4067$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4067$533_Y + end + attribute \src "ls180.v:4074.11-4074.41" + cell $eq $eq$ls180.v:4074$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4074$538_Y + end + attribute \src "ls180.v:4231.37-4231.111" + cell $eq $eq$ls180.v:4231$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4231$602_Y + connect \Y $eq$ls180.v:4231$603_Y + end + attribute \src "ls180.v:4232.37-4232.105" + cell $eq $eq$ls180.v:4232$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4232$604_Y + connect \Y $eq$ls180.v:4232$605_Y + end + attribute \src "ls180.v:4259.10-4259.67" + cell $eq $eq$ls180.v:4259$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spimaster27_count + connect \B $sub$ls180.v:4259$608_Y + connect \Y $eq$ls180.v:4259$609_Y + end + attribute \src "ls180.v:4289.35-4289.108" + cell $eq $eq$ls180.v:4289$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4289$610_Y + connect \Y $eq$ls180.v:4289$611_Y + end + attribute \src "ls180.v:4290.35-4290.102" + cell $eq $eq$ls180.v:4290$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4290$612_Y + connect \Y $eq$ls180.v:4290$613_Y + end + attribute \src "ls180.v:4318.10-4318.65" + cell $eq $eq$ls180.v:4318$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_count + connect \B $sub$ls180.v:4318$616_Y + connect \Y $eq$ls180.v:4318$617_Y + end + attribute \src "ls180.v:4422.10-4422.40" + cell $eq $eq$ls180.v:4422$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4422$644_Y + end + attribute \src "ls180.v:4479.10-4479.39" + cell $eq $eq$ls180.v:4479$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4479$647_Y + end + attribute \src "ls180.v:4496.10-4496.39" + cell $eq $eq$ls180.v:4496$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4496$649_Y + end + attribute \src "ls180.v:4524.38-4524.88" + cell $eq $eq$ls180.v:4524$651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4524$651_Y + end + attribute \src "ls180.v:4574.9-4574.40" + cell $eq $eq$ls180.v:4574$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4574$661_Y + end + attribute \src "ls180.v:4583.36-4583.105" + cell $eq $eq$ls180.v:4583$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4583$662_Y + connect \Y $eq$ls180.v:4583$663_Y + end + attribute \src "ls180.v:4602.9-4602.40" + cell $eq $eq$ls180.v:4602$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4602$667_Y + end + attribute \src "ls180.v:4614.10-4614.39" + cell $eq $eq$ls180.v:4614$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4614$669_Y + end + attribute \src "ls180.v:4651.39-4651.94" + cell $eq $eq$ls180.v:4651$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4651$673_Y + end + attribute \src "ls180.v:4688.32-4688.89" + cell $eq $eq$ls180.v:4688$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4688$682_Y + end + attribute \src "ls180.v:4736.10-4736.40" + cell $eq $eq$ls180.v:4736$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4736$686_Y + end + attribute \src "ls180.v:4785.40-4785.98" + cell $eq $eq$ls180.v:4785$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4785$688_Y + end + attribute \src "ls180.v:4836.9-4836.41" + cell $eq $eq$ls180.v:4836$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4836$698_Y + end + attribute \src "ls180.v:4845.37-4845.123" + cell $eq $eq$ls180.v:4845$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:4845$700_Y + connect \Y $eq$ls180.v:4845$701_Y + end + attribute \src "ls180.v:4868.9-4868.41" + cell $eq $eq$ls180.v:4868$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4868$704_Y + end + attribute \src "ls180.v:4878.10-4878.41" + cell $eq $eq$ls180.v:4878$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:4878$706_Y + end + attribute \src "ls180.v:5047.9-5047.47" + cell $eq $eq$ls180.v:5047$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5047$888_Y + end + attribute \src "ls180.v:5077.10-5077.48" + cell $eq $eq$ls180.v:5077$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5077$889_Y + end + attribute \src "ls180.v:5108.10-5108.78" + cell $eq $eq$ls180.v:5108$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:5108$894_Y + end + attribute \src "ls180.v:5108.83-5108.151" + cell $eq $eq$ls180.v:5108$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:5108$895_Y + end + attribute \src "ls180.v:5108.157-5108.225" + cell $eq $eq$ls180.v:5108$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:5108$897_Y + end + attribute \src "ls180.v:5108.231-5108.299" + cell $eq $eq$ls180.v:5108$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:5108$899_Y + end + attribute \src "ls180.v:5116.7-5116.44" + cell $eq $eq$ls180.v:5116$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5116$903_Y + end + attribute \src "ls180.v:5126.7-5126.44" + cell $eq $eq$ls180.v:5126$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5126$906_Y + end + attribute \src "ls180.v:5136.7-5136.44" + cell $eq $eq$ls180.v:5136$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5136$909_Y + end + attribute \src "ls180.v:5146.7-5146.44" + cell $eq $eq$ls180.v:5146$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5146$912_Y + end + attribute \src "ls180.v:5270.36-5270.64" + cell $eq $eq$ls180.v:5270$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5270$963_Y + end + attribute \src "ls180.v:5276.10-5276.39" + cell $eq $eq$ls180.v:5276$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5276$966_Y + end + attribute \src "ls180.v:5277.11-5277.39" + cell $eq $eq$ls180.v:5277$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5277$967_Y + end + attribute \src "ls180.v:5289.34-5289.63" + cell $eq $eq$ls180.v:5289$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5289$968_Y + end + attribute \src "ls180.v:5290.9-5290.37" + cell $eq $eq$ls180.v:5290$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5290$969_Y + end + attribute \src "ls180.v:5297.10-5297.55" + cell $eq $eq$ls180.v:5297$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5297$970_Y + end + attribute \src "ls180.v:5303.12-5303.41" + cell $eq $eq$ls180.v:5303$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5303$971_Y + end + attribute \src "ls180.v:5306.13-5306.42" + cell $eq $eq$ls180.v:5306$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5306$972_Y + end + attribute \src "ls180.v:5328.10-5328.76" + cell $eq $eq$ls180.v:5328$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5328$976_Y + connect \Y $eq$ls180.v:5328$977_Y + end + attribute \src "ls180.v:5343.35-5343.101" + cell $eq $eq$ls180.v:5343$980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5343$979_Y + connect \Y $eq$ls180.v:5343$980_Y + end + attribute \src "ls180.v:5345.10-5345.56" + cell $eq $eq$ls180.v:5345$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5345$981_Y + end + attribute \src "ls180.v:5354.12-5354.78" + cell $eq $eq$ls180.v:5354$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5354$984_Y + connect \Y $eq$ls180.v:5354$985_Y + end + attribute \src "ls180.v:5361.11-5361.57" + cell $eq $eq$ls180.v:5361$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5361$986_Y + end + attribute \src "ls180.v:5478.10-5478.105" + cell $eq $eq$ls180.v:5478$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5478$1002_Y + connect \Y $eq$ls180.v:5478$1003_Y + end + attribute \src "ls180.v:5568.39-5568.106" + cell $eq $eq$ls180.v:5568$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5568$1008_Y + connect \Y $eq$ls180.v:5568$1009_Y + end + attribute \src "ls180.v:5598.44-5598.82" + cell $eq $eq$ls180.v:5598$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5598$1012_Y + end + attribute \src "ls180.v:5599.43-5599.81" + cell $eq $eq$ls180.v:5599$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 2'11 + connect \Y $eq$ls180.v:5599$1013_Y + end + attribute \src "ls180.v:5699.85-5699.106" + cell $eq $eq$ls180.v:5699$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5699$1029_Y + end + attribute \src "ls180.v:5700.85-5700.106" + cell $eq $eq$ls180.v:5700$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5700$1031_Y + end + attribute \src "ls180.v:5701.85-5701.106" + cell $eq $eq$ls180.v:5701$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5701$1033_Y + end + attribute \src "ls180.v:5702.57-5702.78" + cell $eq $eq$ls180.v:5702$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5702$1035_Y + end + attribute \src "ls180.v:5703.57-5703.78" + cell $eq $eq$ls180.v:5703$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5703$1037_Y + end + attribute \src "ls180.v:5704.85-5704.106" + cell $eq $eq$ls180.v:5704$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5704$1039_Y + end + attribute \src "ls180.v:5705.85-5705.106" + cell $eq $eq$ls180.v:5705$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5705$1041_Y + end + attribute \src "ls180.v:5706.85-5706.106" + cell $eq $eq$ls180.v:5706$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5706$1043_Y + end + attribute \src "ls180.v:5707.57-5707.78" + cell $eq $eq$ls180.v:5707$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5707$1045_Y + end + attribute \src "ls180.v:5708.57-5708.78" + cell $eq $eq$ls180.v:5708$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5708$1047_Y + end + attribute \src "ls180.v:5712.27-5712.59" + cell $eq $eq$ls180.v:5712$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 23 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:7] + connect \B 1'0 + connect \Y $eq$ls180.v:5712$1050_Y + end + attribute \src "ls180.v:5713.27-5713.68" + cell $eq $eq$ls180.v:5713$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 27 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:3] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5713$1051_Y + end + attribute \src "ls180.v:5714.27-5714.66" + cell $eq $eq$ls180.v:5714$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:10] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5714$1052_Y + end + attribute \src "ls180.v:5715.27-5715.61" + cell $eq $eq$ls180.v:5715$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:23] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5715$1053_Y + end + attribute \src "ls180.v:5716.27-5716.65" + cell $eq $eq$ls180.v:5716$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:14] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5716$1054_Y + end + attribute \src "ls180.v:5772.24-5772.45" + cell $eq $eq$ls180.v:5772$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:5772$1081_Y + end + attribute \src "ls180.v:5773.32-5773.77" + cell $eq $eq$ls180.v:5773$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:9] + connect \B 1'0 + connect \Y $eq$ls180.v:5773$1082_Y + end + attribute \src "ls180.v:5775.97-5775.141" + cell $eq $eq$ls180.v:5775$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5775$1084_Y + end + attribute \src "ls180.v:5776.100-5776.144" + cell $eq $eq$ls180.v:5776$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5776$1088_Y + end + attribute \src "ls180.v:5778.99-5778.143" + cell $eq $eq$ls180.v:5778$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5778$1091_Y + end + attribute \src "ls180.v:5779.102-5779.146" + cell $eq $eq$ls180.v:5779$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5779$1095_Y + end + attribute \src "ls180.v:5781.99-5781.143" + cell $eq $eq$ls180.v:5781$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5781$1098_Y + end + attribute \src "ls180.v:5782.102-5782.146" + cell $eq $eq$ls180.v:5782$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5782$1102_Y + end + attribute \src "ls180.v:5784.99-5784.143" + cell $eq $eq$ls180.v:5784$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5784$1105_Y + end + attribute \src "ls180.v:5785.102-5785.146" + cell $eq $eq$ls180.v:5785$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5785$1109_Y + end + attribute \src "ls180.v:5787.99-5787.143" + cell $eq $eq$ls180.v:5787$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5787$1112_Y + end + attribute \src "ls180.v:5788.102-5788.146" + cell $eq $eq$ls180.v:5788$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5788$1116_Y + end + attribute \src "ls180.v:5790.102-5790.146" + cell $eq $eq$ls180.v:5790$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5790$1119_Y + end + attribute \src "ls180.v:5791.105-5791.149" + cell $eq $eq$ls180.v:5791$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5791$1123_Y + end + attribute \src "ls180.v:5793.102-5793.146" + cell $eq $eq$ls180.v:5793$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5793$1126_Y + end + attribute \src "ls180.v:5794.105-5794.149" + cell $eq $eq$ls180.v:5794$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5794$1130_Y + end + attribute \src "ls180.v:5796.102-5796.146" + cell $eq $eq$ls180.v:5796$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5796$1133_Y + end + attribute \src "ls180.v:5797.105-5797.149" + cell $eq $eq$ls180.v:5797$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5797$1137_Y + end + attribute \src "ls180.v:5799.102-5799.146" + cell $eq $eq$ls180.v:5799$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5799$1140_Y + end + attribute \src "ls180.v:5800.105-5800.149" + cell $eq $eq$ls180.v:5800$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5800$1144_Y + end + attribute \src "ls180.v:5811.32-5811.77" + cell $eq $eq$ls180.v:5811$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:9] + connect \B 3'110 + connect \Y $eq$ls180.v:5811$1146_Y + end + attribute \src "ls180.v:5813.94-5813.138" + cell $eq $eq$ls180.v:5813$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5813$1148_Y + end + attribute \src "ls180.v:5814.97-5814.141" + cell $eq $eq$ls180.v:5814$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5814$1152_Y + end + attribute \src "ls180.v:5816.94-5816.138" + cell $eq $eq$ls180.v:5816$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5816$1155_Y + end + attribute \src "ls180.v:5817.97-5817.141" + cell $eq $eq$ls180.v:5817$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5817$1159_Y + end + attribute \src "ls180.v:5819.94-5819.138" + cell $eq $eq$ls180.v:5819$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5819$1162_Y + end + attribute \src "ls180.v:5820.97-5820.141" + cell $eq $eq$ls180.v:5820$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5820$1166_Y + end + attribute \src "ls180.v:5822.94-5822.138" + cell $eq $eq$ls180.v:5822$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5822$1169_Y + end + attribute \src "ls180.v:5823.97-5823.141" + cell $eq $eq$ls180.v:5823$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5823$1173_Y + end + attribute \src "ls180.v:5825.95-5825.139" + cell $eq $eq$ls180.v:5825$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5825$1176_Y + end + attribute \src "ls180.v:5826.98-5826.142" + cell $eq $eq$ls180.v:5826$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5826$1180_Y + end + attribute \src "ls180.v:5828.95-5828.139" + cell $eq $eq$ls180.v:5828$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5828$1183_Y + end + attribute \src "ls180.v:5829.98-5829.142" + cell $eq $eq$ls180.v:5829$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5829$1187_Y + end + attribute \src "ls180.v:5837.32-5837.78" + cell $eq $eq$ls180.v:5837$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:9] + connect \B 4'1011 + connect \Y $eq$ls180.v:5837$1189_Y + end + attribute \src "ls180.v:5839.93-5839.135" + cell $eq $eq$ls180.v:5839$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5839$1191_Y + end + attribute \src "ls180.v:5840.96-5840.138" + cell $eq $eq$ls180.v:5840$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:5840$1195_Y + end + attribute \src "ls180.v:5842.92-5842.134" + cell $eq $eq$ls180.v:5842$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5842$1198_Y + end + attribute \src "ls180.v:5843.95-5843.137" + cell $eq $eq$ls180.v:5843$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:5843$1202_Y + end + attribute \src "ls180.v:5851.32-5851.77" + cell $eq $eq$ls180.v:5851$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:9] + connect \B 4'1001 + connect \Y $eq$ls180.v:5851$1204_Y + end + attribute \src "ls180.v:5853.98-5853.142" + cell $eq $eq$ls180.v:5853$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5853$1206_Y + end + attribute \src "ls180.v:5854.101-5854.145" + cell $eq $eq$ls180.v:5854$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5854$1210_Y + end + attribute \src "ls180.v:5856.97-5856.141" + cell $eq $eq$ls180.v:5856$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5856$1213_Y + end + attribute \src "ls180.v:5857.100-5857.144" + cell $eq $eq$ls180.v:5857$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5857$1217_Y + end + attribute \src "ls180.v:5859.97-5859.141" + cell $eq $eq$ls180.v:5859$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5859$1220_Y + end + attribute \src "ls180.v:5860.100-5860.144" + cell $eq $eq$ls180.v:5860$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5860$1224_Y + end + attribute \src "ls180.v:5862.97-5862.141" + cell $eq $eq$ls180.v:5862$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5862$1227_Y + end + attribute \src "ls180.v:5863.100-5863.144" + cell $eq $eq$ls180.v:5863$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5863$1231_Y + end + attribute \src "ls180.v:5865.97-5865.141" + cell $eq $eq$ls180.v:5865$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5865$1234_Y + end + attribute \src "ls180.v:5866.100-5866.144" + cell $eq $eq$ls180.v:5866$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5866$1238_Y + end + attribute \src "ls180.v:5868.98-5868.142" + cell $eq $eq$ls180.v:5868$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5868$1241_Y + end + attribute \src "ls180.v:5869.101-5869.145" + cell $eq $eq$ls180.v:5869$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5869$1245_Y + end + attribute \src "ls180.v:5871.98-5871.142" + cell $eq $eq$ls180.v:5871$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5871$1248_Y + end + attribute \src "ls180.v:5872.101-5872.145" + cell $eq $eq$ls180.v:5872$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5872$1252_Y + end + attribute \src "ls180.v:5874.98-5874.142" + cell $eq $eq$ls180.v:5874$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5874$1255_Y + end + attribute \src "ls180.v:5875.101-5875.145" + cell $eq $eq$ls180.v:5875$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5875$1259_Y + end + attribute \src "ls180.v:5877.98-5877.142" + cell $eq $eq$ls180.v:5877$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5877$1262_Y + end + attribute \src "ls180.v:5878.101-5878.145" + cell $eq $eq$ls180.v:5878$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5878$1266_Y + end + attribute \src "ls180.v:5888.32-5888.78" + cell $eq $eq$ls180.v:5888$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:9] + connect \B 4'1010 + connect \Y $eq$ls180.v:5888$1268_Y + end + attribute \src "ls180.v:5890.98-5890.142" + cell $eq $eq$ls180.v:5890$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5890$1270_Y + end + attribute \src "ls180.v:5891.101-5891.145" + cell $eq $eq$ls180.v:5891$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5891$1274_Y + end + attribute \src "ls180.v:5893.97-5893.141" + cell $eq $eq$ls180.v:5893$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5893$1277_Y + end + attribute \src "ls180.v:5894.100-5894.144" + cell $eq $eq$ls180.v:5894$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5894$1281_Y + end + attribute \src "ls180.v:5896.97-5896.141" + cell $eq $eq$ls180.v:5896$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5896$1284_Y + end + attribute \src "ls180.v:5897.100-5897.144" + cell $eq $eq$ls180.v:5897$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5897$1288_Y + end + attribute \src "ls180.v:5899.97-5899.141" + cell $eq $eq$ls180.v:5899$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5899$1291_Y + end + attribute \src "ls180.v:5900.100-5900.144" + cell $eq $eq$ls180.v:5900$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5900$1295_Y + end + attribute \src "ls180.v:5902.97-5902.141" + cell $eq $eq$ls180.v:5902$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5902$1298_Y + end + attribute \src "ls180.v:5903.100-5903.144" + cell $eq $eq$ls180.v:5903$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5903$1302_Y + end + attribute \src "ls180.v:5905.98-5905.142" + cell $eq $eq$ls180.v:5905$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5905$1305_Y + end + attribute \src "ls180.v:5906.101-5906.145" + cell $eq $eq$ls180.v:5906$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5906$1309_Y + end + attribute \src "ls180.v:5908.98-5908.142" + cell $eq $eq$ls180.v:5908$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5908$1312_Y + end + attribute \src "ls180.v:5909.101-5909.145" + cell $eq $eq$ls180.v:5909$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5909$1316_Y + end + attribute \src "ls180.v:5911.98-5911.142" + cell $eq $eq$ls180.v:5911$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5911$1319_Y + end + attribute \src "ls180.v:5912.101-5912.145" + cell $eq $eq$ls180.v:5912$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5912$1323_Y + end + attribute \src "ls180.v:5914.98-5914.142" + cell $eq $eq$ls180.v:5914$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5914$1326_Y + end + attribute \src "ls180.v:5915.101-5915.145" + cell $eq $eq$ls180.v:5915$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5915$1330_Y + end + attribute \src "ls180.v:5925.32-5925.78" + cell $eq $eq$ls180.v:5925$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:9] + connect \B 4'1110 + connect \Y $eq$ls180.v:5925$1332_Y + end + attribute \src "ls180.v:5927.100-5927.144" + cell $eq $eq$ls180.v:5927$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5927$1334_Y + end + attribute \src "ls180.v:5928.103-5928.147" + cell $eq $eq$ls180.v:5928$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5928$1338_Y + end + attribute \src "ls180.v:5930.100-5930.144" + cell $eq $eq$ls180.v:5930$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5930$1341_Y + end + attribute \src "ls180.v:5931.103-5931.147" + cell $eq $eq$ls180.v:5931$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5931$1345_Y + end + attribute \src "ls180.v:5933.100-5933.144" + cell $eq $eq$ls180.v:5933$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5933$1348_Y + end + attribute \src "ls180.v:5934.103-5934.147" + cell $eq $eq$ls180.v:5934$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5934$1352_Y + end + attribute \src "ls180.v:5936.100-5936.144" + cell $eq $eq$ls180.v:5936$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5936$1355_Y + end + attribute \src "ls180.v:5937.103-5937.147" + cell $eq $eq$ls180.v:5937$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5937$1359_Y + end + attribute \src "ls180.v:5939.100-5939.144" + cell $eq $eq$ls180.v:5939$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5939$1362_Y + end + attribute \src "ls180.v:5940.103-5940.147" + cell $eq $eq$ls180.v:5940$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:5940$1366_Y + end + attribute \src "ls180.v:5942.100-5942.144" + cell $eq $eq$ls180.v:5942$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5942$1369_Y + end + attribute \src "ls180.v:5943.103-5943.147" + cell $eq $eq$ls180.v:5943$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:5943$1373_Y + end + attribute \src "ls180.v:5945.100-5945.144" + cell $eq $eq$ls180.v:5945$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5945$1376_Y + end + attribute \src "ls180.v:5946.103-5946.147" + cell $eq $eq$ls180.v:5946$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:5946$1380_Y + end + attribute \src "ls180.v:5948.100-5948.144" + cell $eq $eq$ls180.v:5948$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5948$1383_Y + end + attribute \src "ls180.v:5949.103-5949.147" + cell $eq $eq$ls180.v:5949$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:5949$1387_Y + end + attribute \src "ls180.v:5951.102-5951.146" + cell $eq $eq$ls180.v:5951$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5951$1390_Y + end + attribute \src "ls180.v:5952.105-5952.149" + cell $eq $eq$ls180.v:5952$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:5952$1394_Y + end + attribute \src "ls180.v:5954.102-5954.146" + cell $eq $eq$ls180.v:5954$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5954$1397_Y + end + attribute \src "ls180.v:5955.105-5955.149" + cell $eq $eq$ls180.v:5955$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:5955$1401_Y + end + attribute \src "ls180.v:5957.102-5957.147" + cell $eq $eq$ls180.v:5957$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5957$1404_Y + end + attribute \src "ls180.v:5958.105-5958.150" + cell $eq $eq$ls180.v:5958$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:5958$1408_Y + end + attribute \src "ls180.v:5960.102-5960.147" + cell $eq $eq$ls180.v:5960$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5960$1411_Y + end + attribute \src "ls180.v:5961.105-5961.150" + cell $eq $eq$ls180.v:5961$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:5961$1415_Y + end + attribute \src "ls180.v:5963.102-5963.147" + cell $eq $eq$ls180.v:5963$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5963$1418_Y + end + attribute \src "ls180.v:5964.105-5964.150" + cell $eq $eq$ls180.v:5964$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:5964$1422_Y + end + attribute \src "ls180.v:5966.99-5966.144" + cell $eq $eq$ls180.v:5966$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5966$1425_Y + end + attribute \src "ls180.v:5967.102-5967.147" + cell $eq $eq$ls180.v:5967$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:5967$1429_Y + end + attribute \src "ls180.v:5969.100-5969.145" + cell $eq $eq$ls180.v:5969$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5969$1432_Y + end + attribute \src "ls180.v:5970.103-5970.148" + cell $eq $eq$ls180.v:5970$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:5970$1436_Y + end + attribute \src "ls180.v:5987.32-5987.78" + cell $eq $eq$ls180.v:5987$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:9] + connect \B 4'1101 + connect \Y $eq$ls180.v:5987$1438_Y + end + attribute \src "ls180.v:5989.104-5989.148" + cell $eq $eq$ls180.v:5989$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5989$1440_Y + end + attribute \src "ls180.v:5990.107-5990.151" + cell $eq $eq$ls180.v:5990$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:5990$1444_Y + end + attribute \src "ls180.v:5992.104-5992.148" + cell $eq $eq$ls180.v:5992$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5992$1447_Y + end + attribute \src "ls180.v:5993.107-5993.151" + cell $eq $eq$ls180.v:5993$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:5993$1451_Y + end + attribute \src "ls180.v:5995.104-5995.148" + cell $eq $eq$ls180.v:5995$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5995$1454_Y + end + attribute \src "ls180.v:5996.107-5996.151" + cell $eq $eq$ls180.v:5996$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:5996$1458_Y + end + attribute \src "ls180.v:5998.104-5998.148" + cell $eq $eq$ls180.v:5998$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5998$1461_Y + end + attribute \src "ls180.v:5999.107-5999.151" + cell $eq $eq$ls180.v:5999$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:5999$1465_Y + end + attribute \src "ls180.v:6001.103-6001.147" + cell $eq $eq$ls180.v:6001$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6001$1468_Y + end + attribute \src "ls180.v:6002.106-6002.150" + cell $eq $eq$ls180.v:6002$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6002$1472_Y + end + attribute \src "ls180.v:6004.103-6004.147" + cell $eq $eq$ls180.v:6004$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6004$1475_Y + end + attribute \src "ls180.v:6005.106-6005.150" + cell $eq $eq$ls180.v:6005$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6005$1479_Y + end + attribute \src "ls180.v:6007.103-6007.147" + cell $eq $eq$ls180.v:6007$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6007$1482_Y + end + attribute \src "ls180.v:6008.106-6008.150" + cell $eq $eq$ls180.v:6008$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6008$1486_Y + end + attribute \src "ls180.v:6010.103-6010.147" + cell $eq $eq$ls180.v:6010$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6010$1489_Y + end + attribute \src "ls180.v:6011.106-6011.150" + cell $eq $eq$ls180.v:6011$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6011$1493_Y + end + attribute \src "ls180.v:6013.94-6013.138" + cell $eq $eq$ls180.v:6013$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6013$1496_Y + end + attribute \src "ls180.v:6014.97-6014.141" + cell $eq $eq$ls180.v:6014$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6014$1500_Y + end + attribute \src "ls180.v:6016.105-6016.149" + cell $eq $eq$ls180.v:6016$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6016$1503_Y + end + attribute \src "ls180.v:6017.108-6017.152" + cell $eq $eq$ls180.v:6017$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6017$1507_Y + end + attribute \src "ls180.v:6019.105-6019.150" + cell $eq $eq$ls180.v:6019$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6019$1510_Y + end + attribute \src "ls180.v:6020.108-6020.153" + cell $eq $eq$ls180.v:6020$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6020$1514_Y + end + attribute \src "ls180.v:6022.105-6022.150" + cell $eq $eq$ls180.v:6022$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6022$1517_Y + end + attribute \src "ls180.v:6023.108-6023.153" + cell $eq $eq$ls180.v:6023$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6023$1521_Y + end + attribute \src "ls180.v:6025.105-6025.150" + cell $eq $eq$ls180.v:6025$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6025$1524_Y + end + attribute \src "ls180.v:6026.108-6026.153" + cell $eq $eq$ls180.v:6026$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6026$1528_Y + end + attribute \src "ls180.v:6028.105-6028.150" + cell $eq $eq$ls180.v:6028$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6028$1531_Y + end + attribute \src "ls180.v:6029.108-6029.153" + cell $eq $eq$ls180.v:6029$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6029$1535_Y + end + attribute \src "ls180.v:6031.105-6031.150" + cell $eq $eq$ls180.v:6031$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6031$1538_Y + end + attribute \src "ls180.v:6032.108-6032.153" + cell $eq $eq$ls180.v:6032$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6032$1542_Y + end + attribute \src "ls180.v:6034.104-6034.149" + cell $eq $eq$ls180.v:6034$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6034$1545_Y + end + attribute \src "ls180.v:6035.107-6035.152" + cell $eq $eq$ls180.v:6035$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6035$1549_Y + end + attribute \src "ls180.v:6037.104-6037.149" + cell $eq $eq$ls180.v:6037$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6037$1552_Y + end + attribute \src "ls180.v:6038.107-6038.152" + cell $eq $eq$ls180.v:6038$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6038$1556_Y + end + attribute \src "ls180.v:6040.104-6040.149" + cell $eq $eq$ls180.v:6040$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6040$1559_Y + end + attribute \src "ls180.v:6041.107-6041.152" + cell $eq $eq$ls180.v:6041$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6041$1563_Y + end + attribute \src "ls180.v:6043.104-6043.149" + cell $eq $eq$ls180.v:6043$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6043$1566_Y + end + attribute \src "ls180.v:6044.107-6044.152" + cell $eq $eq$ls180.v:6044$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6044$1570_Y + end + attribute \src "ls180.v:6046.104-6046.149" + cell $eq $eq$ls180.v:6046$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6046$1573_Y + end + attribute \src "ls180.v:6047.107-6047.152" + cell $eq $eq$ls180.v:6047$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6047$1577_Y + end + attribute \src "ls180.v:6049.104-6049.149" + cell $eq $eq$ls180.v:6049$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6049$1580_Y + end + attribute \src "ls180.v:6050.107-6050.152" + cell $eq $eq$ls180.v:6050$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6050$1584_Y + end + attribute \src "ls180.v:6052.104-6052.149" + cell $eq $eq$ls180.v:6052$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6052$1587_Y + end + attribute \src "ls180.v:6053.107-6053.152" + cell $eq $eq$ls180.v:6053$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6053$1591_Y + end + attribute \src "ls180.v:6055.104-6055.149" + cell $eq $eq$ls180.v:6055$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6055$1594_Y + end + attribute \src "ls180.v:6056.107-6056.152" + cell $eq $eq$ls180.v:6056$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6056$1598_Y + end + attribute \src "ls180.v:6058.104-6058.149" + cell $eq $eq$ls180.v:6058$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6058$1601_Y + end + attribute \src "ls180.v:6059.107-6059.152" + cell $eq $eq$ls180.v:6059$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6059$1605_Y + end + attribute \src "ls180.v:6061.104-6061.149" + cell $eq $eq$ls180.v:6061$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6061$1608_Y + end + attribute \src "ls180.v:6062.107-6062.152" + cell $eq $eq$ls180.v:6062$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6062$1612_Y + end + attribute \src "ls180.v:6064.100-6064.145" + cell $eq $eq$ls180.v:6064$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6064$1615_Y + end + attribute \src "ls180.v:6065.103-6065.148" + cell $eq $eq$ls180.v:6065$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6065$1619_Y + end + attribute \src "ls180.v:6067.101-6067.146" + cell $eq $eq$ls180.v:6067$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6067$1622_Y + end + attribute \src "ls180.v:6068.104-6068.149" + cell $eq $eq$ls180.v:6068$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6068$1626_Y + end + attribute \src "ls180.v:6070.104-6070.149" + cell $eq $eq$ls180.v:6070$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6070$1629_Y + end + attribute \src "ls180.v:6071.107-6071.152" + cell $eq $eq$ls180.v:6071$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6071$1633_Y + end + attribute \src "ls180.v:6073.104-6073.149" + cell $eq $eq$ls180.v:6073$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6073$1636_Y + end + attribute \src "ls180.v:6074.107-6074.152" + cell $eq $eq$ls180.v:6074$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6074$1640_Y + end + attribute \src "ls180.v:6076.103-6076.148" + cell $eq $eq$ls180.v:6076$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6076$1643_Y + end + attribute \src "ls180.v:6077.106-6077.151" + cell $eq $eq$ls180.v:6077$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6077$1647_Y + end + attribute \src "ls180.v:6079.103-6079.148" + cell $eq $eq$ls180.v:6079$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6079$1650_Y + end + attribute \src "ls180.v:6080.106-6080.151" + cell $eq $eq$ls180.v:6080$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6080$1654_Y + end + attribute \src "ls180.v:6082.103-6082.148" + cell $eq $eq$ls180.v:6082$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6082$1657_Y + end + attribute \src "ls180.v:6083.106-6083.151" + cell $eq $eq$ls180.v:6083$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6083$1661_Y + end + attribute \src "ls180.v:6085.103-6085.148" + cell $eq $eq$ls180.v:6085$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6085$1664_Y + end + attribute \src "ls180.v:6086.106-6086.151" + cell $eq $eq$ls180.v:6086$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6086$1668_Y + end + attribute \src "ls180.v:6122.32-6122.78" + cell $eq $eq$ls180.v:6122$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:9] + connect \B 4'1111 + connect \Y $eq$ls180.v:6122$1670_Y + end + attribute \src "ls180.v:6124.100-6124.144" + cell $eq $eq$ls180.v:6124$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6124$1672_Y + end + attribute \src "ls180.v:6125.103-6125.147" + cell $eq $eq$ls180.v:6125$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6125$1676_Y + end + attribute \src "ls180.v:6127.100-6127.144" + cell $eq $eq$ls180.v:6127$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6127$1679_Y + end + attribute \src "ls180.v:6128.103-6128.147" + cell $eq $eq$ls180.v:6128$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6128$1683_Y + end + attribute \src "ls180.v:6130.100-6130.144" + cell $eq $eq$ls180.v:6130$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6130$1686_Y + end + attribute \src "ls180.v:6131.103-6131.147" + cell $eq $eq$ls180.v:6131$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6131$1690_Y + end + attribute \src "ls180.v:6133.100-6133.144" + cell $eq $eq$ls180.v:6133$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6133$1693_Y + end + attribute \src "ls180.v:6134.103-6134.147" + cell $eq $eq$ls180.v:6134$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6134$1697_Y + end + attribute \src "ls180.v:6136.100-6136.144" + cell $eq $eq$ls180.v:6136$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6136$1700_Y + end + attribute \src "ls180.v:6137.103-6137.147" + cell $eq $eq$ls180.v:6137$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6137$1704_Y + end + attribute \src "ls180.v:6139.100-6139.144" + cell $eq $eq$ls180.v:6139$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6139$1707_Y + end + attribute \src "ls180.v:6140.103-6140.147" + cell $eq $eq$ls180.v:6140$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6140$1711_Y + end + attribute \src "ls180.v:6142.100-6142.144" + cell $eq $eq$ls180.v:6142$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6142$1714_Y + end + attribute \src "ls180.v:6143.103-6143.147" + cell $eq $eq$ls180.v:6143$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6143$1718_Y + end + attribute \src "ls180.v:6145.100-6145.144" + cell $eq $eq$ls180.v:6145$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6145$1721_Y + end + attribute \src "ls180.v:6146.103-6146.147" + cell $eq $eq$ls180.v:6146$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6146$1725_Y + end + attribute \src "ls180.v:6148.102-6148.146" + cell $eq $eq$ls180.v:6148$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6148$1728_Y + end + attribute \src "ls180.v:6149.105-6149.149" + cell $eq $eq$ls180.v:6149$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6149$1732_Y + end + attribute \src "ls180.v:6151.102-6151.146" + cell $eq $eq$ls180.v:6151$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6151$1735_Y + end + attribute \src "ls180.v:6152.105-6152.149" + cell $eq $eq$ls180.v:6152$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6152$1739_Y + end + attribute \src "ls180.v:6154.102-6154.147" + cell $eq $eq$ls180.v:6154$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6154$1742_Y + end + attribute \src "ls180.v:6155.105-6155.150" + cell $eq $eq$ls180.v:6155$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6155$1746_Y + end + attribute \src "ls180.v:6157.102-6157.147" + cell $eq $eq$ls180.v:6157$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6157$1749_Y + end + attribute \src "ls180.v:6158.105-6158.150" + cell $eq $eq$ls180.v:6158$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6158$1753_Y + end + attribute \src "ls180.v:6160.102-6160.147" + cell $eq $eq$ls180.v:6160$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6160$1756_Y + end + attribute \src "ls180.v:6161.105-6161.150" + cell $eq $eq$ls180.v:6161$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6161$1760_Y + end + attribute \src "ls180.v:6163.99-6163.144" + cell $eq $eq$ls180.v:6163$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6163$1763_Y + end + attribute \src "ls180.v:6164.102-6164.147" + cell $eq $eq$ls180.v:6164$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6164$1767_Y + end + attribute \src "ls180.v:6166.100-6166.145" + cell $eq $eq$ls180.v:6166$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6166$1770_Y + end + attribute \src "ls180.v:6167.103-6167.148" + cell $eq $eq$ls180.v:6167$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6167$1774_Y + end + attribute \src "ls180.v:6169.102-6169.147" + cell $eq $eq$ls180.v:6169$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6169$1777_Y + end + attribute \src "ls180.v:6170.105-6170.150" + cell $eq $eq$ls180.v:6170$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6170$1781_Y + end + attribute \src "ls180.v:6172.102-6172.147" + cell $eq $eq$ls180.v:6172$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6172$1784_Y + end + attribute \src "ls180.v:6173.105-6173.150" + cell $eq $eq$ls180.v:6173$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6173$1788_Y + end + attribute \src "ls180.v:6175.102-6175.147" + cell $eq $eq$ls180.v:6175$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6175$1791_Y + end + attribute \src "ls180.v:6176.105-6176.150" + cell $eq $eq$ls180.v:6176$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6176$1795_Y + end + attribute \src "ls180.v:6178.102-6178.147" + cell $eq $eq$ls180.v:6178$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6178$1798_Y + end + attribute \src "ls180.v:6179.105-6179.150" + cell $eq $eq$ls180.v:6179$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6179$1802_Y + end + attribute \src "ls180.v:6201.32-6201.78" + cell $eq $eq$ls180.v:6201$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:9] + connect \B 4'1100 + connect \Y $eq$ls180.v:6201$1804_Y + end + attribute \src "ls180.v:6203.102-6203.146" + cell $eq $eq$ls180.v:6203$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6203$1806_Y + end + attribute \src "ls180.v:6204.105-6204.149" + cell $eq $eq$ls180.v:6204$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6204$1810_Y + end + attribute \src "ls180.v:6206.107-6206.151" + cell $eq $eq$ls180.v:6206$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6206$1813_Y + end + attribute \src "ls180.v:6207.110-6207.154" + cell $eq $eq$ls180.v:6207$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6207$1817_Y + end + attribute \src "ls180.v:6209.107-6209.151" + cell $eq $eq$ls180.v:6209$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6209$1820_Y + end + attribute \src "ls180.v:6210.110-6210.154" + cell $eq $eq$ls180.v:6210$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6210$1824_Y + end + attribute \src "ls180.v:6212.100-6212.144" + cell $eq $eq$ls180.v:6212$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6212$1827_Y + end + attribute \src "ls180.v:6213.103-6213.147" + cell $eq $eq$ls180.v:6213$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6213$1831_Y + end + attribute \src "ls180.v:6218.32-6218.77" + cell $eq $eq$ls180.v:6218$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6218$1833_Y + end + attribute \src "ls180.v:6220.104-6220.148" + cell $eq $eq$ls180.v:6220$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6220$1835_Y + end + attribute \src "ls180.v:6221.107-6221.151" + cell $eq $eq$ls180.v:6221$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6221$1839_Y + end + attribute \src "ls180.v:6223.108-6223.152" + cell $eq $eq$ls180.v:6223$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6223$1842_Y + end + attribute \src "ls180.v:6224.111-6224.155" + cell $eq $eq$ls180.v:6224$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6224$1846_Y + end + attribute \src "ls180.v:6226.98-6226.142" + cell $eq $eq$ls180.v:6226$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6226$1849_Y + end + attribute \src "ls180.v:6227.101-6227.145" + cell $eq $eq$ls180.v:6227$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6227$1853_Y + end + attribute \src "ls180.v:6229.108-6229.152" + cell $eq $eq$ls180.v:6229$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6229$1856_Y + end + attribute \src "ls180.v:6230.111-6230.155" + cell $eq $eq$ls180.v:6230$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6230$1860_Y + end + attribute \src "ls180.v:6232.108-6232.152" + cell $eq $eq$ls180.v:6232$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6232$1863_Y + end + attribute \src "ls180.v:6233.111-6233.155" + cell $eq $eq$ls180.v:6233$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6233$1867_Y + end + attribute \src "ls180.v:6235.109-6235.153" + cell $eq $eq$ls180.v:6235$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6235$1870_Y + end + attribute \src "ls180.v:6236.112-6236.156" + cell $eq $eq$ls180.v:6236$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6236$1874_Y + end + attribute \src "ls180.v:6238.107-6238.151" + cell $eq $eq$ls180.v:6238$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6238$1877_Y + end + attribute \src "ls180.v:6239.110-6239.154" + cell $eq $eq$ls180.v:6239$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6239$1881_Y + end + attribute \src "ls180.v:6241.107-6241.151" + cell $eq $eq$ls180.v:6241$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6241$1884_Y + end + attribute \src "ls180.v:6242.110-6242.154" + cell $eq $eq$ls180.v:6242$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6242$1888_Y + end + attribute \src "ls180.v:6244.107-6244.151" + cell $eq $eq$ls180.v:6244$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6244$1891_Y + end + attribute \src "ls180.v:6245.110-6245.154" + cell $eq $eq$ls180.v:6245$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6245$1895_Y + end + attribute \src "ls180.v:6247.107-6247.151" + cell $eq $eq$ls180.v:6247$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6247$1898_Y + end + attribute \src "ls180.v:6248.110-6248.154" + cell $eq $eq$ls180.v:6248$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6248$1902_Y + end + attribute \src "ls180.v:6263.33-6263.79" + cell $eq $eq$ls180.v:6263$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:9] + connect \B 3'111 + connect \Y $eq$ls180.v:6263$1904_Y + end + attribute \src "ls180.v:6265.102-6265.147" + cell $eq $eq$ls180.v:6265$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6265$1906_Y + end + attribute \src "ls180.v:6266.105-6266.150" + cell $eq $eq$ls180.v:6266$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6266$1910_Y + end + attribute \src "ls180.v:6268.102-6268.147" + cell $eq $eq$ls180.v:6268$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6268$1913_Y + end + attribute \src "ls180.v:6269.105-6269.150" + cell $eq $eq$ls180.v:6269$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6269$1917_Y + end + attribute \src "ls180.v:6271.100-6271.145" + cell $eq $eq$ls180.v:6271$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6271$1920_Y + end + attribute \src "ls180.v:6272.103-6272.148" + cell $eq $eq$ls180.v:6272$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6272$1924_Y + end + attribute \src "ls180.v:6274.99-6274.144" + cell $eq $eq$ls180.v:6274$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6274$1927_Y + end + attribute \src "ls180.v:6275.102-6275.147" + cell $eq $eq$ls180.v:6275$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6275$1931_Y + end + attribute \src "ls180.v:6277.98-6277.143" + cell $eq $eq$ls180.v:6277$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6277$1934_Y + end + attribute \src "ls180.v:6278.101-6278.146" + cell $eq $eq$ls180.v:6278$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6278$1938_Y + end + attribute \src "ls180.v:6280.97-6280.142" + cell $eq $eq$ls180.v:6280$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6280$1941_Y + end + attribute \src "ls180.v:6281.100-6281.145" + cell $eq $eq$ls180.v:6281$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6281$1945_Y + end + attribute \src "ls180.v:6283.103-6283.148" + cell $eq $eq$ls180.v:6283$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6283$1948_Y + end + attribute \src "ls180.v:6284.106-6284.151" + cell $eq $eq$ls180.v:6284$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6284$1952_Y + end + attribute \src "ls180.v:6303.33-6303.79" + cell $eq $eq$ls180.v:6303$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$ls180.v:6303$1955_Y + end + attribute \src "ls180.v:6305.102-6305.147" + cell $eq $eq$ls180.v:6305$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6305$1957_Y + end + attribute \src "ls180.v:6306.105-6306.150" + cell $eq $eq$ls180.v:6306$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6306$1961_Y + end + attribute \src "ls180.v:6308.102-6308.147" + cell $eq $eq$ls180.v:6308$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6308$1964_Y + end + attribute \src "ls180.v:6309.105-6309.150" + cell $eq $eq$ls180.v:6309$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6309$1968_Y + end + attribute \src "ls180.v:6311.100-6311.145" + cell $eq $eq$ls180.v:6311$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6311$1971_Y + end + attribute \src "ls180.v:6312.103-6312.148" + cell $eq $eq$ls180.v:6312$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6312$1975_Y + end + attribute \src "ls180.v:6314.99-6314.144" + cell $eq $eq$ls180.v:6314$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6314$1978_Y + end + attribute \src "ls180.v:6315.102-6315.147" + cell $eq $eq$ls180.v:6315$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6315$1982_Y + end + attribute \src "ls180.v:6317.98-6317.143" + cell $eq $eq$ls180.v:6317$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6317$1985_Y + end + attribute \src "ls180.v:6318.101-6318.146" + cell $eq $eq$ls180.v:6318$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6318$1989_Y + end + attribute \src "ls180.v:6320.97-6320.142" + cell $eq $eq$ls180.v:6320$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6320$1992_Y + end + attribute \src "ls180.v:6321.100-6321.145" + cell $eq $eq$ls180.v:6321$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6321$1996_Y + end + attribute \src "ls180.v:6323.103-6323.148" + cell $eq $eq$ls180.v:6323$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6323$1999_Y + end + attribute \src "ls180.v:6324.106-6324.151" + cell $eq $eq$ls180.v:6324$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6324$2003_Y + end + attribute \src "ls180.v:6326.106-6326.151" + cell $eq $eq$ls180.v:6326$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6326$2006_Y + end + attribute \src "ls180.v:6327.109-6327.154" + cell $eq $eq$ls180.v:6327$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6327$2010_Y + end + attribute \src "ls180.v:6329.106-6329.151" + cell $eq $eq$ls180.v:6329$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6329$2013_Y + end + attribute \src "ls180.v:6330.109-6330.154" + cell $eq $eq$ls180.v:6330$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6330$2017_Y + end + attribute \src "ls180.v:6351.33-6351.79" + cell $eq $eq$ls180.v:6351$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6351$2020_Y + end + attribute \src "ls180.v:6353.99-6353.144" + cell $eq $eq$ls180.v:6353$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6353$2022_Y + end + attribute \src "ls180.v:6354.102-6354.147" + cell $eq $eq$ls180.v:6354$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6354$2026_Y + end + attribute \src "ls180.v:6356.99-6356.144" + cell $eq $eq$ls180.v:6356$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6356$2029_Y + end + attribute \src "ls180.v:6357.102-6357.147" + cell $eq $eq$ls180.v:6357$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6357$2033_Y + end + attribute \src "ls180.v:6359.99-6359.144" + cell $eq $eq$ls180.v:6359$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6359$2036_Y + end + attribute \src "ls180.v:6360.102-6360.147" + cell $eq $eq$ls180.v:6360$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6360$2040_Y + end + attribute \src "ls180.v:6362.99-6362.144" + cell $eq $eq$ls180.v:6362$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6362$2043_Y + end + attribute \src "ls180.v:6363.102-6363.147" + cell $eq $eq$ls180.v:6363$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6363$2047_Y + end + attribute \src "ls180.v:6365.101-6365.146" + cell $eq $eq$ls180.v:6365$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6365$2050_Y + end + attribute \src "ls180.v:6366.104-6366.149" + cell $eq $eq$ls180.v:6366$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6366$2054_Y + end + attribute \src "ls180.v:6368.101-6368.146" + cell $eq $eq$ls180.v:6368$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6368$2057_Y + end + attribute \src "ls180.v:6369.104-6369.149" + cell $eq $eq$ls180.v:6369$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6369$2061_Y + end + attribute \src "ls180.v:6371.101-6371.146" + cell $eq $eq$ls180.v:6371$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6371$2064_Y + end + attribute \src "ls180.v:6372.104-6372.149" + cell $eq $eq$ls180.v:6372$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6372$2068_Y + end + attribute \src "ls180.v:6374.101-6374.146" + cell $eq $eq$ls180.v:6374$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6374$2071_Y + end + attribute \src "ls180.v:6375.104-6375.149" + cell $eq $eq$ls180.v:6375$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6375$2075_Y + end + attribute \src "ls180.v:6377.97-6377.142" + cell $eq $eq$ls180.v:6377$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6377$2078_Y + end + attribute \src "ls180.v:6378.100-6378.145" + cell $eq $eq$ls180.v:6378$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6378$2082_Y + end + attribute \src "ls180.v:6380.107-6380.152" + cell $eq $eq$ls180.v:6380$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6380$2085_Y + end + attribute \src "ls180.v:6381.110-6381.155" + cell $eq $eq$ls180.v:6381$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6381$2089_Y + end + attribute \src "ls180.v:6383.100-6383.146" + cell $eq $eq$ls180.v:6383$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6383$2092_Y + end + attribute \src "ls180.v:6384.103-6384.149" + cell $eq $eq$ls180.v:6384$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6384$2096_Y + end + attribute \src "ls180.v:6386.100-6386.146" + cell $eq $eq$ls180.v:6386$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6386$2099_Y + end + attribute \src "ls180.v:6387.103-6387.149" + cell $eq $eq$ls180.v:6387$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6387$2103_Y + end + attribute \src "ls180.v:6389.100-6389.146" + cell $eq $eq$ls180.v:6389$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6389$2106_Y + end + attribute \src "ls180.v:6390.103-6390.149" + cell $eq $eq$ls180.v:6390$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6390$2110_Y + end + attribute \src "ls180.v:6392.100-6392.146" + cell $eq $eq$ls180.v:6392$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6392$2113_Y + end + attribute \src "ls180.v:6393.103-6393.149" + cell $eq $eq$ls180.v:6393$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6393$2117_Y + end + attribute \src "ls180.v:6395.112-6395.158" + cell $eq $eq$ls180.v:6395$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6395$2120_Y + end + attribute \src "ls180.v:6396.115-6396.161" + cell $eq $eq$ls180.v:6396$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6396$2124_Y + end + attribute \src "ls180.v:6398.113-6398.159" + cell $eq $eq$ls180.v:6398$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6398$2127_Y + end + attribute \src "ls180.v:6399.116-6399.162" + cell $eq $eq$ls180.v:6399$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6399$2131_Y + end + attribute \src "ls180.v:6401.104-6401.150" + cell $eq $eq$ls180.v:6401$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6401$2134_Y + end + attribute \src "ls180.v:6402.107-6402.153" + cell $eq $eq$ls180.v:6402$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6402$2138_Y + end + attribute \src "ls180.v:6419.33-6419.79" + cell $eq $eq$ls180.v:6419$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:9] + connect \B 3'101 + connect \Y $eq$ls180.v:6419$2140_Y + end + attribute \src "ls180.v:6421.90-6421.135" + cell $eq $eq$ls180.v:6421$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6421$2142_Y + end + attribute \src "ls180.v:6422.93-6422.138" + cell $eq $eq$ls180.v:6422$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6422$2146_Y + end + attribute \src "ls180.v:6424.100-6424.145" + cell $eq $eq$ls180.v:6424$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6424$2149_Y + end + attribute \src "ls180.v:6425.103-6425.148" + cell $eq $eq$ls180.v:6425$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6425$2153_Y + end + attribute \src "ls180.v:6427.101-6427.146" + cell $eq $eq$ls180.v:6427$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6427$2156_Y + end + attribute \src "ls180.v:6428.104-6428.149" + cell $eq $eq$ls180.v:6428$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6428$2160_Y + end + attribute \src "ls180.v:6430.105-6430.150" + cell $eq $eq$ls180.v:6430$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6430$2163_Y + end + attribute \src "ls180.v:6431.108-6431.153" + cell $eq $eq$ls180.v:6431$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6431$2167_Y + end + attribute \src "ls180.v:6433.106-6433.151" + cell $eq $eq$ls180.v:6433$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6433$2170_Y + end + attribute \src "ls180.v:6434.109-6434.154" + cell $eq $eq$ls180.v:6434$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6434$2174_Y + end + attribute \src "ls180.v:6436.104-6436.149" + cell $eq $eq$ls180.v:6436$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6436$2177_Y + end + attribute \src "ls180.v:6437.107-6437.152" + cell $eq $eq$ls180.v:6437$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6437$2181_Y + end + attribute \src "ls180.v:6439.101-6439.146" + cell $eq $eq$ls180.v:6439$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6439$2184_Y + end + attribute \src "ls180.v:6440.104-6440.149" + cell $eq $eq$ls180.v:6440$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6440$2188_Y + end + attribute \src "ls180.v:6442.100-6442.145" + cell $eq $eq$ls180.v:6442$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6442$2191_Y + end + attribute \src "ls180.v:6443.103-6443.148" + cell $eq $eq$ls180.v:6443$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6443$2195_Y + end + attribute \src "ls180.v:6453.33-6453.79" + cell $eq $eq$ls180.v:6453$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [13:9] + connect \B 3'100 + connect \Y $eq$ls180.v:6453$2197_Y + end + attribute \src "ls180.v:6455.106-6455.151" + cell $eq $eq$ls180.v:6455$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6455$2199_Y + end + attribute \src "ls180.v:6456.109-6456.154" + cell $eq $eq$ls180.v:6456$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6456$2203_Y + end + attribute \src "ls180.v:6458.106-6458.151" + cell $eq $eq$ls180.v:6458$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6458$2206_Y + end + attribute \src "ls180.v:6459.109-6459.154" + cell $eq $eq$ls180.v:6459$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6459$2210_Y + end + attribute \src "ls180.v:6461.106-6461.151" + cell $eq $eq$ls180.v:6461$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6461$2213_Y + end + attribute \src "ls180.v:6462.109-6462.154" + cell $eq $eq$ls180.v:6462$2217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6462$2217_Y + end + attribute \src "ls180.v:6464.106-6464.151" + cell $eq $eq$ls180.v:6464$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6464$2220_Y + end + attribute \src "ls180.v:6465.109-6465.154" + cell $eq $eq$ls180.v:6465$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6465$2224_Y + end + attribute \src "ls180.v:6846.41-6846.81" + cell $eq $eq$ls180.v:6846$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:6846$2261_Y + end + attribute \src "ls180.v:6846.144-6846.177" + cell $eq $eq$ls180.v:6846$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6846$2262_Y + end + attribute \src "ls180.v:6846.219-6846.252" + cell $eq $eq$ls180.v:6846$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6846$2265_Y + end + attribute \src "ls180.v:6846.294-6846.327" + cell $eq $eq$ls180.v:6846$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6846$2268_Y + end + attribute \src "ls180.v:6870.41-6870.81" + cell $eq $eq$ls180.v:6870$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:6870$2277_Y + end + attribute \src "ls180.v:6870.144-6870.177" + cell $eq $eq$ls180.v:6870$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6870$2278_Y + end + attribute \src "ls180.v:6870.219-6870.252" + cell $eq $eq$ls180.v:6870$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6870$2281_Y + end + attribute \src "ls180.v:6870.294-6870.327" + cell $eq $eq$ls180.v:6870$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6870$2284_Y + end + attribute \src "ls180.v:6894.41-6894.81" + cell $eq $eq$ls180.v:6894$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:6894$2293_Y + end + attribute \src "ls180.v:6894.144-6894.177" + cell $eq $eq$ls180.v:6894$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6894$2294_Y + end + attribute \src "ls180.v:6894.219-6894.252" + cell $eq $eq$ls180.v:6894$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6894$2297_Y + end + attribute \src "ls180.v:6894.294-6894.327" + cell $eq $eq$ls180.v:6894$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6894$2300_Y + end + attribute \src "ls180.v:6918.41-6918.81" + cell $eq $eq$ls180.v:6918$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:6918$2309_Y + end + attribute \src "ls180.v:6918.144-6918.177" + cell $eq $eq$ls180.v:6918$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6918$2310_Y + end + attribute \src "ls180.v:6918.219-6918.252" + cell $eq $eq$ls180.v:6918$2313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6918$2313_Y + end + attribute \src "ls180.v:6918.294-6918.327" + cell $eq $eq$ls180.v:6918$2316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:6918$2316_Y + end + attribute \src "ls180.v:7511.8-7511.38" + cell $eq $eq$ls180.v:7511$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7511$2419_Y + end + attribute \src "ls180.v:7542.8-7542.42" + cell $eq $eq$ls180.v:7542$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7542$2427_Y + end + attribute \src "ls180.v:7562.38-7562.74" + cell $eq $eq$ls180.v:7562$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7562$2430_Y + end + attribute \src "ls180.v:7569.7-7569.43" + cell $eq $eq$ls180.v:7569$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7569$2432_Y + end + attribute \src "ls180.v:7576.7-7576.43" + cell $eq $eq$ls180.v:7576$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7576$2433_Y + end + attribute \src "ls180.v:7584.7-7584.43" + cell $eq $eq$ls180.v:7584$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7584$2434_Y + end + attribute \src "ls180.v:7636.9-7636.54" + cell $eq $eq$ls180.v:7636$2452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7636$2452_Y + end + attribute \src "ls180.v:7682.9-7682.54" + cell $eq $eq$ls180.v:7682$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7682$2468_Y + end + attribute \src "ls180.v:7728.9-7728.54" + cell $eq $eq$ls180.v:7728$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7728$2484_Y + end + attribute \src "ls180.v:7774.9-7774.54" + cell $eq $eq$ls180.v:7774$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7774$2500_Y + end + attribute \src "ls180.v:7924.9-7924.41" + cell $eq $eq$ls180.v:7924$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7924$2512_Y + end + attribute \src "ls180.v:7939.9-7939.41" + cell $eq $eq$ls180.v:7939$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7939$2515_Y + end + attribute \src "ls180.v:7945.49-7945.82" + cell $eq $eq$ls180.v:7945$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7945$2516_Y + end + attribute \src "ls180.v:7945.131-7945.164" + cell $eq $eq$ls180.v:7945$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7945$2519_Y + end + attribute \src "ls180.v:7945.213-7945.246" + cell $eq $eq$ls180.v:7945$2522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7945$2522_Y + end + attribute \src "ls180.v:7945.295-7945.328" + cell $eq $eq$ls180.v:7945$2525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7945$2525_Y + end + attribute \src "ls180.v:7946.50-7946.83" + cell $eq $eq$ls180.v:7946$2528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7946$2528_Y + end + attribute \src "ls180.v:7946.132-7946.165" + cell $eq $eq$ls180.v:7946$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7946$2531_Y + end + attribute \src "ls180.v:7946.214-7946.247" + cell $eq $eq$ls180.v:7946$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7946$2534_Y + end + attribute \src "ls180.v:7946.296-7946.329" + cell $eq $eq$ls180.v:7946$2537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7946$2537_Y + end + attribute \src "ls180.v:7981.9-7981.42" + cell $eq $eq$ls180.v:7981$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:7981$2549_Y + end + attribute \src "ls180.v:7984.10-7984.43" + cell $eq $eq$ls180.v:7984$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:7984$2550_Y + end + attribute \src "ls180.v:8010.9-8010.42" + cell $eq $eq$ls180.v:8010$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:8010$2556_Y + end + attribute \src "ls180.v:8015.10-8015.43" + cell $eq $eq$ls180.v:8015$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:8015$2557_Y + end + attribute \src "ls180.v:8222.9-8222.53" + cell $eq $eq$ls180.v:8222$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8222$2606_Y + end + attribute \src "ls180.v:8303.9-8303.54" + cell $eq $eq$ls180.v:8303$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8303$2618_Y + end + attribute \src "ls180.v:8382.9-8382.55" + cell $eq $eq$ls180.v:8382$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8382$2630_Y + end + attribute \src "ls180.v:8605.9-8605.49" + cell $eq $eq$ls180.v:8605$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 2'11 + connect \Y $eq$ls180.v:8605$2663_Y + end + attribute \src "ls180.v:8181.8-8181.54" + cell $ge $ge$ls180.v:8181$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8181$2597_Y + connect \Y $ge$ls180.v:8181$2598_Y + end + attribute \src "ls180.v:8195.8-8195.54" + cell $ge $ge$ls180.v:8195$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8195$2601_Y + connect \Y $ge$ls180.v:8195$2602_Y + end + attribute \src "ls180.v:5155.47-5155.83" + cell $gt $gt$ls180.v:5155$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5155$914_Y + end + attribute \src "ls180.v:5161.7-5161.43" + cell $lt $lt$ls180.v:5161$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5161$917_Y + end + attribute \src "ls180.v:8176.8-8176.43" + cell $lt $lt$ls180.v:8176$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8176$2596_Y + end + attribute \src "ls180.v:8190.8-8190.43" + cell $lt $lt$ls180.v:8190$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8190$2600_Y + end + attribute \src "ls180.v:10071.33-10071.36" + cell $memrd $memrd$\mem$ls180.v:10071$2705 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:10071$2705_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10082.12-10082.19" + cell $memrd $memrd$\storage$ls180.v:10082$2710 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10082$2710_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10089.68-10089.75" + cell $memrd $memrd$\storage$ls180.v:10089$2712 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10089$2712_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10096.14-10096.23" + cell $memrd $memrd$\storage_1$ls180.v:10096$2717 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10096$2717_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10103.68-10103.77" + cell $memrd $memrd$\storage_1$ls180.v:10103$2719 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10103$2719_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10110.14-10110.23" + cell $memrd $memrd$\storage_2$ls180.v:10110$2724 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10110$2724_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10117.68-10117.77" + cell $memrd $memrd$\storage_2$ls180.v:10117$2726 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10117$2726_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10124.14-10124.23" + cell $memrd $memrd$\storage_3$ls180.v:10124$2731 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10124$2731_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10131.68-10131.77" + cell $memrd $memrd$\storage_3$ls180.v:10131$2733 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10131$2733_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10139.14-10139.23" + cell $memrd $memrd$\storage_4$ls180.v:10139$2738 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10139$2738_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10144.15-10144.24" + cell $memrd $memrd$\storage_4$ls180.v:10144$2740 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10144$2740_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10156.14-10156.23" + cell $memrd $memrd$\storage_5$ls180.v:10156$2745 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10156$2745_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10161.15-10161.24" + cell $memrd $memrd$\storage_5$ls180.v:10161$2747 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10161$2747_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10172.14-10172.23" + cell $memrd $memrd$\storage_6$ls180.v:10172$2752 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10172$2752_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10179.45-10179.54" + cell $memrd $memrd$\storage_6$ls180.v:10179$2754 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10179$2754_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10186.14-10186.23" + cell $memrd $memrd$\storage_7$ls180.v:10186$2759 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10186$2759_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10193.45-10193.54" + cell $memrd $memrd$\storage_7$ls180.v:10193$2761 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10193$2761_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2763 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2763 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10061$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10061$1_DATA + connect \EN $memwr$\mem$ls180.v:10061$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2764 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2764 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10063$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10063$2_DATA + connect \EN $memwr$\mem$ls180.v:10063$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2765 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2765 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10065$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10065$3_DATA + connect \EN $memwr$\mem$ls180.v:10065$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$2766 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2766 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$ls180.v:10067$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10067$4_DATA + connect \EN $memwr$\mem$ls180.v:10067$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$2767 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 2767 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:10081$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:10081$5_DATA + connect \EN $memwr$\storage$ls180.v:10081$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$2768 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 2768 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10095$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10095$6_DATA + connect \EN $memwr$\storage_1$ls180.v:10095$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$2769 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 2769 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10109$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10109$7_DATA + connect \EN $memwr$\storage_2$ls180.v:10109$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$2770 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 2770 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10123$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10123$8_DATA + connect \EN $memwr$\storage_3$ls180.v:10123$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$2771 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 2771 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10138$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10138$9_DATA + connect \EN $memwr$\storage_4$ls180.v:10138$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$2772 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 2772 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10155$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10155$10_DATA + connect \EN $memwr$\storage_5$ls180.v:10155$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$2773 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 2773 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10171$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10171$11_DATA + connect \EN $memwr$\storage_6$ls180.v:10171$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$2774 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 2774 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10185$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10185$12_DATA + connect \EN $memwr$\storage_7$ls180.v:10185$12_EN + end + attribute \src "ls180.v:2969.41-2969.71" + cell $ne $ne$ls180.v:2969$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:2969$60_Y + end + attribute \src "ls180.v:3130.70-3130.104" + cell $ne $ne$ls180.v:3130$74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3130$74_Y + end + attribute \src "ls180.v:3191.8-3191.142" + cell $ne $ne$ls180.v:3191$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3191$93_Y + end + attribute \src "ls180.v:3223.75-3223.133" + cell $ne $ne$ls180.v:3223$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3223$100_Y + end + attribute \src "ls180.v:3224.75-3224.133" + cell $ne $ne$ls180.v:3224$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3224$101_Y + end + attribute \src "ls180.v:3348.8-3348.142" + cell $ne $ne$ls180.v:3348$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3348$123_Y + end + attribute \src "ls180.v:3380.75-3380.133" + cell $ne $ne$ls180.v:3380$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3380$130_Y + end + attribute \src "ls180.v:3381.75-3381.133" + cell $ne $ne$ls180.v:3381$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3381$131_Y + end + attribute \src "ls180.v:3505.8-3505.142" + cell $ne $ne$ls180.v:3505$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3505$153_Y + end + attribute \src "ls180.v:3537.75-3537.133" + cell $ne $ne$ls180.v:3537$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3537$160_Y + end + attribute \src "ls180.v:3538.75-3538.133" + cell $ne $ne$ls180.v:3538$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3538$161_Y + end + attribute \src "ls180.v:3662.8-3662.142" + cell $ne $ne$ls180.v:3662$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3662$183_Y + end + attribute \src "ls180.v:3694.75-3694.133" + cell $ne $ne$ls180.v:3694$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3694$190_Y + end + attribute \src "ls180.v:3695.75-3695.133" + cell $ne $ne$ls180.v:3695$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3695$191_Y + end + attribute \src "ls180.v:4187.47-4187.80" + cell $ne $ne$ls180.v:4187$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4187$589_Y + end + attribute \src "ls180.v:4188.47-4188.79" + cell $ne $ne$ls180.v:4188$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4188$590_Y + end + attribute \src "ls180.v:4217.47-4217.80" + cell $ne $ne$ls180.v:4217$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4217$600_Y + end + attribute \src "ls180.v:4218.47-4218.79" + cell $ne $ne$ls180.v:4218$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4218$601_Y + end + attribute \src "ls180.v:4687.32-4687.89" + cell $ne $ne$ls180.v:4687$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4687$681_Y + end + attribute \src "ls180.v:5334.10-5334.56" + cell $ne $ne$ls180.v:5334$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5334$978_Y + end + attribute \src "ls180.v:5439.51-5439.87" + cell $ne $ne$ls180.v:5439$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5439$992_Y + end + attribute \src "ls180.v:5440.51-5440.86" + cell $ne $ne$ls180.v:5440$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5440$993_Y + end + attribute \src "ls180.v:5647.51-5647.87" + cell $ne $ne$ls180.v:5647$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5647$1023_Y + end + attribute \src "ls180.v:5648.51-5648.86" + cell $ne $ne$ls180.v:5648$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5648$1024_Y + end + attribute \src "ls180.v:5679.79-5679.119" + cell $ne $ne$ls180.v:5679$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5679$1027_Y + end + attribute \src "ls180.v:7501.7-7501.52" + cell $ne $ne$ls180.v:7501$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7501$2414_Y + end + attribute \src "ls180.v:7551.9-7551.43" + cell $ne $ne$ls180.v:7551$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7551$2428_Y + end + attribute \src "ls180.v:7587.8-7587.44" + cell $ne $ne$ls180.v:7587$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7587$2435_Y + end + attribute \src "ls180.v:8525.9-8525.47" + cell $ne $ne$ls180.v:8525$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8525$2650_Y + end + attribute \src "ls180.v:2777.45-2777.80" + cell $not $not$ls180.v:2777$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_cyc + connect \Y $not$ls180.v:2777$14_Y + end + attribute \src "ls180.v:2816.61-2816.94" + cell $not $not$ls180.v:2816$19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2816$19_Y + end + attribute \src "ls180.v:2817.61-2817.94" + cell $not $not$ls180.v:2817$20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$ls180.v:2817$20_Y + end + attribute \src "ls180.v:2837.45-2837.80" + cell $not $not$ls180.v:2837$25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_cyc + connect \Y $not$ls180.v:2837$25_Y + end + attribute \src "ls180.v:2876.61-2876.94" + cell $not $not$ls180.v:2876$30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2876$30_Y + end + attribute \src "ls180.v:2877.61-2877.94" + cell $not $not$ls180.v:2877$31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$ls180.v:2877$31_Y + end + attribute \src "ls180.v:2897.45-2897.83" + cell $not $not$ls180.v:2897$36 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_jtag_wb_cyc + connect \Y $not$ls180.v:2897$36_Y + end + attribute \src "ls180.v:2936.61-2936.94" + cell $not $not$ls180.v:2936$41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2936$41_Y + end + attribute \src "ls180.v:2937.61-2937.94" + cell $not $not$ls180.v:2937$42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter2_skip + connect \Y $not$ls180.v:2937$42_Y + end + attribute \src "ls180.v:3079.34-3079.64" + cell $not $not$ls180.v:3079$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3079$66_Y + end + attribute \src "ls180.v:3080.31-3080.61" + cell $not $not$ls180.v:3080$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3080$67_Y + end + attribute \src "ls180.v:3081.32-3081.62" + cell $not $not$ls180.v:3081$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3081$68_Y + end + attribute \src "ls180.v:3082.32-3082.62" + cell $not $not$ls180.v:3082$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3082$69_Y + end + attribute \src "ls180.v:3124.33-3124.56" + cell $not $not$ls180.v:3124$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3124$72_Y + end + attribute \src "ls180.v:3225.58-3225.106" + cell $not $not$ls180.v:3225$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3225$102_Y + end + attribute \src "ls180.v:3279.9-3279.45" + cell $not $not$ls180.v:3279$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3279$107_Y + end + attribute \src "ls180.v:3382.58-3382.106" + cell $not $not$ls180.v:3382$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3382$132_Y + end + attribute \src "ls180.v:3436.9-3436.45" + cell $not $not$ls180.v:3436$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3436$137_Y + end + attribute \src "ls180.v:3539.58-3539.106" + cell $not $not$ls180.v:3539$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3539$162_Y + end + attribute \src "ls180.v:3593.9-3593.45" + cell $not $not$ls180.v:3593$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3593$167_Y + end + attribute \src "ls180.v:3696.58-3696.106" + cell $not $not$ls180.v:3696$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3696$192_Y + end + attribute \src "ls180.v:3750.9-3750.45" + cell $not $not$ls180.v:3750$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3750$197_Y + end + attribute \src "ls180.v:3792.149-3792.187" + cell $not $not$ls180.v:3792$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3792$200_Y + end + attribute \src "ls180.v:3792.193-3792.230" + cell $not $not$ls180.v:3792$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3792$202_Y + end + attribute \src "ls180.v:3793.149-3793.187" + cell $not $not$ls180.v:3793$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3793$206_Y + end + attribute \src "ls180.v:3793.193-3793.230" + cell $not $not$ls180.v:3793$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3793$208_Y + end + attribute \src "ls180.v:3809.43-3809.73" + cell $not $not$ls180.v:3809$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3809$236_Y + end + attribute \src "ls180.v:3812.205-3812.245" + cell $not $not$ls180.v:3812$239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3812$239_Y + end + attribute \src "ls180.v:3812.251-3812.290" + cell $not $not$ls180.v:3812$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3812$241_Y + end + attribute \src "ls180.v:3812.159-3812.292" + cell $not $not$ls180.v:3812$243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3812$242_Y + connect \Y $not$ls180.v:3812$243_Y + end + attribute \src "ls180.v:3813.205-3813.245" + cell $not $not$ls180.v:3813$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3813$252_Y + end + attribute \src "ls180.v:3813.251-3813.290" + cell $not $not$ls180.v:3813$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3813$254_Y + end + attribute \src "ls180.v:3813.159-3813.292" + cell $not $not$ls180.v:3813$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3813$255_Y + connect \Y $not$ls180.v:3813$256_Y + end + attribute \src "ls180.v:3814.205-3814.245" + cell $not $not$ls180.v:3814$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3814$265_Y + end + attribute \src "ls180.v:3814.251-3814.290" + cell $not $not$ls180.v:3814$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3814$267_Y + end + attribute \src "ls180.v:3814.159-3814.292" + cell $not $not$ls180.v:3814$269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3814$268_Y + connect \Y $not$ls180.v:3814$269_Y + end + attribute \src "ls180.v:3815.205-3815.245" + cell $not $not$ls180.v:3815$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3815$278_Y + end + attribute \src "ls180.v:3815.251-3815.290" + cell $not $not$ls180.v:3815$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3815$280_Y + end + attribute \src "ls180.v:3815.159-3815.292" + cell $not $not$ls180.v:3815$282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3815$281_Y + connect \Y $not$ls180.v:3815$282_Y + end + attribute \src "ls180.v:3842.71-3842.103" + cell $not $not$ls180.v:3842$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:3842$293_Y + end + attribute \src "ls180.v:3845.205-3845.245" + cell $not $not$ls180.v:3845$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3845$297_Y + end + attribute \src "ls180.v:3845.251-3845.290" + cell $not $not$ls180.v:3845$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3845$299_Y + end + attribute \src "ls180.v:3845.159-3845.292" + cell $not $not$ls180.v:3845$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3845$300_Y + connect \Y $not$ls180.v:3845$301_Y + end + attribute \src "ls180.v:3846.205-3846.245" + cell $not $not$ls180.v:3846$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3846$310_Y + end + attribute \src "ls180.v:3846.251-3846.290" + cell $not $not$ls180.v:3846$312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3846$312_Y + end + attribute \src "ls180.v:3846.159-3846.292" + cell $not $not$ls180.v:3846$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3846$313_Y + connect \Y $not$ls180.v:3846$314_Y + end + attribute \src "ls180.v:3847.205-3847.245" + cell $not $not$ls180.v:3847$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3847$323_Y + end + attribute \src "ls180.v:3847.251-3847.290" + cell $not $not$ls180.v:3847$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3847$325_Y + end + attribute \src "ls180.v:3847.159-3847.292" + cell $not $not$ls180.v:3847$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3847$326_Y + connect \Y $not$ls180.v:3847$327_Y + end + attribute \src "ls180.v:3848.205-3848.245" + cell $not $not$ls180.v:3848$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3848$336_Y + end + attribute \src "ls180.v:3848.251-3848.290" + cell $not $not$ls180.v:3848$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3848$338_Y + end + attribute \src "ls180.v:3848.159-3848.292" + cell $not $not$ls180.v:3848$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3848$339_Y + connect \Y $not$ls180.v:3848$340_Y + end + attribute \src "ls180.v:3911.71-3911.103" + cell $not $not$ls180.v:3911$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:3911$379_Y + end + attribute \src "ls180.v:3932.112-3932.150" + cell $not $not$ls180.v:3932$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3932$382_Y + end + attribute \src "ls180.v:3932.156-3932.193" + cell $not $not$ls180.v:3932$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3932$384_Y + end + attribute \src "ls180.v:3932.68-3932.195" + cell $not $not$ls180.v:3932$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3932$385_Y + connect \Y $not$ls180.v:3932$386_Y + end + attribute \src "ls180.v:3940.11-3940.38" + cell $not $not$ls180.v:3940$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:3940$389_Y + end + attribute \src "ls180.v:3970.112-3970.150" + cell $not $not$ls180.v:3970$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3970$391_Y + end + attribute \src "ls180.v:3970.156-3970.193" + cell $not $not$ls180.v:3970$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3970$393_Y + end + attribute \src "ls180.v:3970.68-3970.195" + cell $not $not$ls180.v:3970$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3970$394_Y + connect \Y $not$ls180.v:3970$395_Y + end + attribute \src "ls180.v:3978.11-3978.37" + cell $not $not$ls180.v:3978$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:3978$398_Y + end + attribute \src "ls180.v:3988.87-3988.331" + cell $not $not$ls180.v:3988$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$409_Y + connect \Y $not$ls180.v:3988$410_Y + end + attribute \src "ls180.v:3989.35-3989.68" + cell $not $not$ls180.v:3989$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:3989$413_Y + end + attribute \src "ls180.v:3989.73-3989.105" + cell $not $not$ls180.v:3989$414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:3989$414_Y + end + attribute \src "ls180.v:3993.87-3993.331" + cell $not $not$ls180.v:3993$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3993$425_Y + connect \Y $not$ls180.v:3993$426_Y + end + attribute \src "ls180.v:3994.35-3994.68" + cell $not $not$ls180.v:3994$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:3994$429_Y + end + attribute \src "ls180.v:3994.73-3994.105" + cell $not $not$ls180.v:3994$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:3994$430_Y + end + attribute \src "ls180.v:3998.87-3998.331" + cell $not $not$ls180.v:3998$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3998$441_Y + connect \Y $not$ls180.v:3998$442_Y + end + attribute \src "ls180.v:3999.35-3999.68" + cell $not $not$ls180.v:3999$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:3999$445_Y + end + attribute \src "ls180.v:3999.73-3999.105" + cell $not $not$ls180.v:3999$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:3999$446_Y + end + attribute \src "ls180.v:4003.87-4003.331" + cell $not $not$ls180.v:4003$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4003$457_Y + connect \Y $not$ls180.v:4003$458_Y + end + attribute \src "ls180.v:4004.35-4004.68" + cell $not $not$ls180.v:4004$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:4004$461_Y + end + attribute \src "ls180.v:4004.73-4004.105" + cell $not $not$ls180.v:4004$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:4004$462_Y + end + attribute \src "ls180.v:4008.128-4008.372" + cell $not $not$ls180.v:4008$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$474_Y + connect \Y $not$ls180.v:4008$475_Y + end + attribute \src "ls180.v:4008.502-4008.746" + cell $not $not$ls180.v:4008$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$490_Y + connect \Y $not$ls180.v:4008$491_Y + end + attribute \src "ls180.v:4008.876-4008.1120" + cell $not $not$ls180.v:4008$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$506_Y + connect \Y $not$ls180.v:4008$507_Y + end + attribute \src "ls180.v:4008.1250-4008.1494" + cell $not $not$ls180.v:4008$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$522_Y + connect \Y $not$ls180.v:4008$523_Y + end + attribute \src "ls180.v:4030.32-4030.50" + cell $not $not$ls180.v:4030$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:4030$529_Y + end + attribute \src "ls180.v:4069.30-4069.50" + cell $not $not$ls180.v:4069$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4069$534_Y + end + attribute \src "ls180.v:4070.30-4070.50" + cell $not $not$ls180.v:4070$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4070$535_Y + end + attribute \src "ls180.v:4095.27-4095.48" + cell $not $not$ls180.v:4095$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4095$541_Y + end + attribute \src "ls180.v:4096.30-4096.50" + cell $not $not$ls180.v:4096$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4096$542_Y + end + attribute \src "ls180.v:4097.80-4097.98" + cell $not $not$ls180.v:4097$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4097$544_Y + end + attribute \src "ls180.v:4098.107-4098.127" + cell $not $not$ls180.v:4098$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4098$548_Y + end + attribute \src "ls180.v:4099.78-4099.103" + cell $not $not$ls180.v:4099$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4099$551_Y + end + attribute \src "ls180.v:4100.91-4100.111" + cell $not $not$ls180.v:4100$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4100$554_Y + end + attribute \src "ls180.v:4116.35-4116.64" + cell $not $not$ls180.v:4116$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4116$563_Y + end + attribute \src "ls180.v:4117.36-4117.67" + cell $not $not$ls180.v:4117$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4117$564_Y + end + attribute \src "ls180.v:4123.32-4123.61" + cell $not $not$ls180.v:4123$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4123$565_Y + end + attribute \src "ls180.v:4129.36-4129.67" + cell $not $not$ls180.v:4129$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4129$566_Y + end + attribute \src "ls180.v:4130.35-4130.64" + cell $not $not$ls180.v:4130$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4130$567_Y + end + attribute \src "ls180.v:4133.32-4133.63" + cell $not $not$ls180.v:4133$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4133$570_Y + end + attribute \src "ls180.v:4171.81-4171.108" + cell $not $not$ls180.v:4171$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4171$580_Y + end + attribute \src "ls180.v:4201.81-4201.108" + cell $not $not$ls180.v:4201$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4201$591_Y + end + attribute \src "ls180.v:4401.60-4401.85" + cell $not $not$ls180.v:4401$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4401$640_Y + end + attribute \src "ls180.v:4542.54-4542.96" + cell $not $not$ls180.v:4542$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4542$654_Y + end + attribute \src "ls180.v:4545.48-4545.86" + cell $not $not$ls180.v:4545$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4545$657_Y + end + attribute \src "ls180.v:4669.55-4669.98" + cell $not $not$ls180.v:4669$675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4669$675_Y + end + attribute \src "ls180.v:4672.49-4672.88" + cell $not $not$ls180.v:4672$678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4672$678_Y + end + attribute \src "ls180.v:4722.30-4722.58" + cell $not $not$ls180.v:4722$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4722$684_Y + end + attribute \src "ls180.v:4803.56-4803.100" + cell $not $not$ls180.v:4803$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4803$690_Y + end + attribute \src "ls180.v:4806.50-4806.90" + cell $not $not$ls180.v:4806$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4806$693_Y + end + attribute \src "ls180.v:4922.42-4922.74" + cell $not $not$ls180.v:4922$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:4922$709_Y + end + attribute \src "ls180.v:5446.50-5446.88" + cell $not $not$ls180.v:5446$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5446$994_Y + end + attribute \src "ls180.v:5458.52-5458.102" + cell $not $not$ls180.v:5458$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5458$997_Y + end + attribute \src "ls180.v:5517.38-5517.74" + cell $not $not$ls180.v:5517$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5517$1004_Y + end + attribute \src "ls180.v:5759.69-5759.88" + cell $not $not$ls180.v:5759$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:5759$1065_Y + end + attribute \src "ls180.v:5776.63-5776.94" + cell $not $not$ls180.v:5776$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5776$1086_Y + end + attribute \src "ls180.v:5779.65-5779.96" + cell $not $not$ls180.v:5779$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5779$1093_Y + end + attribute \src "ls180.v:5782.65-5782.96" + cell $not $not$ls180.v:5782$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5782$1100_Y + end + attribute \src "ls180.v:5785.65-5785.96" + cell $not $not$ls180.v:5785$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5785$1107_Y + end + attribute \src "ls180.v:5788.65-5788.96" + cell $not $not$ls180.v:5788$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5788$1114_Y + end + attribute \src "ls180.v:5791.68-5791.99" + cell $not $not$ls180.v:5791$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5791$1121_Y + end + attribute \src "ls180.v:5794.68-5794.99" + cell $not $not$ls180.v:5794$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5794$1128_Y + end + attribute \src "ls180.v:5797.68-5797.99" + cell $not $not$ls180.v:5797$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5797$1135_Y + end + attribute \src "ls180.v:5800.68-5800.99" + cell $not $not$ls180.v:5800$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:5800$1142_Y + end + attribute \src "ls180.v:5814.60-5814.91" + cell $not $not$ls180.v:5814$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5814$1150_Y + end + attribute \src "ls180.v:5817.60-5817.91" + cell $not $not$ls180.v:5817$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5817$1157_Y + end + attribute \src "ls180.v:5820.60-5820.91" + cell $not $not$ls180.v:5820$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5820$1164_Y + end + attribute \src "ls180.v:5823.60-5823.91" + cell $not $not$ls180.v:5823$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5823$1171_Y + end + attribute \src "ls180.v:5826.61-5826.92" + cell $not $not$ls180.v:5826$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5826$1178_Y + end + attribute \src "ls180.v:5829.61-5829.92" + cell $not $not$ls180.v:5829$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:5829$1185_Y + end + attribute \src "ls180.v:5840.59-5840.90" + cell $not $not$ls180.v:5840$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5840$1193_Y + end + attribute \src "ls180.v:5843.58-5843.89" + cell $not $not$ls180.v:5843$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:5843$1200_Y + end + attribute \src "ls180.v:5854.64-5854.95" + cell $not $not$ls180.v:5854$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5854$1208_Y + end + attribute \src "ls180.v:5857.63-5857.94" + cell $not $not$ls180.v:5857$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5857$1215_Y + end + attribute \src "ls180.v:5860.63-5860.94" + cell $not $not$ls180.v:5860$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5860$1222_Y + end + attribute \src "ls180.v:5863.63-5863.94" + cell $not $not$ls180.v:5863$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5863$1229_Y + end + attribute \src "ls180.v:5866.63-5866.94" + cell $not $not$ls180.v:5866$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5866$1236_Y + end + attribute \src "ls180.v:5869.64-5869.95" + cell $not $not$ls180.v:5869$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5869$1243_Y + end + attribute \src "ls180.v:5872.64-5872.95" + cell $not $not$ls180.v:5872$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5872$1250_Y + end + attribute \src "ls180.v:5875.64-5875.95" + cell $not $not$ls180.v:5875$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5875$1257_Y + end + attribute \src "ls180.v:5878.64-5878.95" + cell $not $not$ls180.v:5878$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:5878$1264_Y + end + attribute \src "ls180.v:5891.64-5891.95" + cell $not $not$ls180.v:5891$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5891$1272_Y + end + attribute \src "ls180.v:5894.63-5894.94" + cell $not $not$ls180.v:5894$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5894$1279_Y + end + attribute \src "ls180.v:5897.63-5897.94" + cell $not $not$ls180.v:5897$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5897$1286_Y + end + attribute \src "ls180.v:5900.63-5900.94" + cell $not $not$ls180.v:5900$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5900$1293_Y + end + attribute \src "ls180.v:5903.63-5903.94" + cell $not $not$ls180.v:5903$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5903$1300_Y + end + attribute \src "ls180.v:5906.64-5906.95" + cell $not $not$ls180.v:5906$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5906$1307_Y + end + attribute \src "ls180.v:5909.64-5909.95" + cell $not $not$ls180.v:5909$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5909$1314_Y + end + attribute \src "ls180.v:5912.64-5912.95" + cell $not $not$ls180.v:5912$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5912$1321_Y + end + attribute \src "ls180.v:5915.64-5915.95" + cell $not $not$ls180.v:5915$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:5915$1328_Y + end + attribute \src "ls180.v:5928.66-5928.97" + cell $not $not$ls180.v:5928$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5928$1336_Y + end + attribute \src "ls180.v:5931.66-5931.97" + cell $not $not$ls180.v:5931$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5931$1343_Y + end + attribute \src "ls180.v:5934.66-5934.97" + cell $not $not$ls180.v:5934$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5934$1350_Y + end + attribute \src "ls180.v:5937.66-5937.97" + cell $not $not$ls180.v:5937$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5937$1357_Y + end + attribute \src "ls180.v:5940.66-5940.97" + cell $not $not$ls180.v:5940$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5940$1364_Y + end + attribute \src "ls180.v:5943.66-5943.97" + cell $not $not$ls180.v:5943$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5943$1371_Y + end + attribute \src "ls180.v:5946.66-5946.97" + cell $not $not$ls180.v:5946$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5946$1378_Y + end + attribute \src "ls180.v:5949.66-5949.97" + cell $not $not$ls180.v:5949$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5949$1385_Y + end + attribute \src "ls180.v:5952.68-5952.99" + cell $not $not$ls180.v:5952$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5952$1392_Y + end + attribute \src "ls180.v:5955.68-5955.99" + cell $not $not$ls180.v:5955$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5955$1399_Y + end + attribute \src "ls180.v:5958.68-5958.99" + cell $not $not$ls180.v:5958$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5958$1406_Y + end + attribute \src "ls180.v:5961.68-5961.99" + cell $not $not$ls180.v:5961$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5961$1413_Y + end + attribute \src "ls180.v:5964.68-5964.99" + cell $not $not$ls180.v:5964$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5964$1420_Y + end + attribute \src "ls180.v:5967.65-5967.96" + cell $not $not$ls180.v:5967$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5967$1427_Y + end + attribute \src "ls180.v:5970.66-5970.97" + cell $not $not$ls180.v:5970$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:5970$1434_Y + end + attribute \src "ls180.v:5990.70-5990.101" + cell $not $not$ls180.v:5990$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5990$1442_Y + end + attribute \src "ls180.v:5993.70-5993.101" + cell $not $not$ls180.v:5993$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5993$1449_Y + end + attribute \src "ls180.v:5996.70-5996.101" + cell $not $not$ls180.v:5996$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5996$1456_Y + end + attribute \src "ls180.v:5999.70-5999.101" + cell $not $not$ls180.v:5999$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:5999$1463_Y + end + attribute \src "ls180.v:6002.69-6002.100" + cell $not $not$ls180.v:6002$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6002$1470_Y + end + attribute \src "ls180.v:6005.69-6005.100" + cell $not $not$ls180.v:6005$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6005$1477_Y + end + attribute \src "ls180.v:6008.69-6008.100" + cell $not $not$ls180.v:6008$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6008$1484_Y + end + attribute \src "ls180.v:6011.69-6011.100" + cell $not $not$ls180.v:6011$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6011$1491_Y + end + attribute \src "ls180.v:6014.60-6014.91" + cell $not $not$ls180.v:6014$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6014$1498_Y + end + attribute \src "ls180.v:6017.71-6017.102" + cell $not $not$ls180.v:6017$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6017$1505_Y + end + attribute \src "ls180.v:6020.71-6020.102" + cell $not $not$ls180.v:6020$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6020$1512_Y + end + attribute \src "ls180.v:6023.71-6023.102" + cell $not $not$ls180.v:6023$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6023$1519_Y + end + attribute \src "ls180.v:6026.71-6026.102" + cell $not $not$ls180.v:6026$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6026$1526_Y + end + attribute \src "ls180.v:6029.71-6029.102" + cell $not $not$ls180.v:6029$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6029$1533_Y + end + attribute \src "ls180.v:6032.71-6032.102" + cell $not $not$ls180.v:6032$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6032$1540_Y + end + attribute \src "ls180.v:6035.70-6035.101" + cell $not $not$ls180.v:6035$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6035$1547_Y + end + attribute \src "ls180.v:6038.70-6038.101" + cell $not $not$ls180.v:6038$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6038$1554_Y + end + attribute \src "ls180.v:6041.70-6041.101" + cell $not $not$ls180.v:6041$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6041$1561_Y + end + attribute \src "ls180.v:6044.70-6044.101" + cell $not $not$ls180.v:6044$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6044$1568_Y + end + attribute \src "ls180.v:6047.70-6047.101" + cell $not $not$ls180.v:6047$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6047$1575_Y + end + attribute \src "ls180.v:6050.70-6050.101" + cell $not $not$ls180.v:6050$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6050$1582_Y + end + attribute \src "ls180.v:6053.70-6053.101" + cell $not $not$ls180.v:6053$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6053$1589_Y + end + attribute \src "ls180.v:6056.70-6056.101" + cell $not $not$ls180.v:6056$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6056$1596_Y + end + attribute \src "ls180.v:6059.70-6059.101" + cell $not $not$ls180.v:6059$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6059$1603_Y + end + attribute \src "ls180.v:6062.70-6062.101" + cell $not $not$ls180.v:6062$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6062$1610_Y + end + attribute \src "ls180.v:6065.66-6065.97" + cell $not $not$ls180.v:6065$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6065$1617_Y + end + attribute \src "ls180.v:6068.67-6068.98" + cell $not $not$ls180.v:6068$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6068$1624_Y + end + attribute \src "ls180.v:6071.70-6071.101" + cell $not $not$ls180.v:6071$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6071$1631_Y + end + attribute \src "ls180.v:6074.70-6074.101" + cell $not $not$ls180.v:6074$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6074$1638_Y + end + attribute \src "ls180.v:6077.69-6077.100" + cell $not $not$ls180.v:6077$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6077$1645_Y + end + attribute \src "ls180.v:6080.69-6080.100" + cell $not $not$ls180.v:6080$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6080$1652_Y + end + attribute \src "ls180.v:6083.69-6083.100" + cell $not $not$ls180.v:6083$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6083$1659_Y + end + attribute \src "ls180.v:6086.69-6086.100" + cell $not $not$ls180.v:6086$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6086$1666_Y + end + attribute \src "ls180.v:6125.66-6125.97" + cell $not $not$ls180.v:6125$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6125$1674_Y + end + attribute \src "ls180.v:6128.66-6128.97" + cell $not $not$ls180.v:6128$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6128$1681_Y + end + attribute \src "ls180.v:6131.66-6131.97" + cell $not $not$ls180.v:6131$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6131$1688_Y + end + attribute \src "ls180.v:6134.66-6134.97" + cell $not $not$ls180.v:6134$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6134$1695_Y + end + attribute \src "ls180.v:6137.66-6137.97" + cell $not $not$ls180.v:6137$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6137$1702_Y + end + attribute \src "ls180.v:6140.66-6140.97" + cell $not $not$ls180.v:6140$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6140$1709_Y + end + attribute \src "ls180.v:6143.66-6143.97" + cell $not $not$ls180.v:6143$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6143$1716_Y + end + attribute \src "ls180.v:6146.66-6146.97" + cell $not $not$ls180.v:6146$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6146$1723_Y + end + attribute \src "ls180.v:6149.68-6149.99" + cell $not $not$ls180.v:6149$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6149$1730_Y + end + attribute \src "ls180.v:6152.68-6152.99" + cell $not $not$ls180.v:6152$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6152$1737_Y + end + attribute \src "ls180.v:6155.68-6155.99" + cell $not $not$ls180.v:6155$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6155$1744_Y + end + attribute \src "ls180.v:6158.68-6158.99" + cell $not $not$ls180.v:6158$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6158$1751_Y + end + attribute \src "ls180.v:6161.68-6161.99" + cell $not $not$ls180.v:6161$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6161$1758_Y + end + attribute \src "ls180.v:6164.65-6164.96" + cell $not $not$ls180.v:6164$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6164$1765_Y + end + attribute \src "ls180.v:6167.66-6167.97" + cell $not $not$ls180.v:6167$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6167$1772_Y + end + attribute \src "ls180.v:6170.68-6170.99" + cell $not $not$ls180.v:6170$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6170$1779_Y + end + attribute \src "ls180.v:6173.68-6173.99" + cell $not $not$ls180.v:6173$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6173$1786_Y + end + attribute \src "ls180.v:6176.68-6176.99" + cell $not $not$ls180.v:6176$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6176$1793_Y + end + attribute \src "ls180.v:6179.68-6179.99" + cell $not $not$ls180.v:6179$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6179$1800_Y + end + attribute \src "ls180.v:6204.68-6204.99" + cell $not $not$ls180.v:6204$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6204$1808_Y + end + attribute \src "ls180.v:6207.73-6207.104" + cell $not $not$ls180.v:6207$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6207$1815_Y + end + attribute \src "ls180.v:6210.73-6210.104" + cell $not $not$ls180.v:6210$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6210$1822_Y + end + attribute \src "ls180.v:6213.66-6213.97" + cell $not $not$ls180.v:6213$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6213$1829_Y + end + attribute \src "ls180.v:6221.70-6221.101" + cell $not $not$ls180.v:6221$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6221$1837_Y + end + attribute \src "ls180.v:6224.74-6224.105" + cell $not $not$ls180.v:6224$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6224$1844_Y + end + attribute \src "ls180.v:6227.64-6227.95" + cell $not $not$ls180.v:6227$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6227$1851_Y + end + attribute \src "ls180.v:6230.74-6230.105" + cell $not $not$ls180.v:6230$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6230$1858_Y + end + attribute \src "ls180.v:6233.74-6233.105" + cell $not $not$ls180.v:6233$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6233$1865_Y + end + attribute \src "ls180.v:6236.75-6236.106" + cell $not $not$ls180.v:6236$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6236$1872_Y + end + attribute \src "ls180.v:6239.73-6239.104" + cell $not $not$ls180.v:6239$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6239$1879_Y + end + attribute \src "ls180.v:6242.73-6242.104" + cell $not $not$ls180.v:6242$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6242$1886_Y + end + attribute \src "ls180.v:6245.73-6245.104" + cell $not $not$ls180.v:6245$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6245$1893_Y + end + attribute \src "ls180.v:6248.73-6248.104" + cell $not $not$ls180.v:6248$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6248$1900_Y + end + attribute \src "ls180.v:6266.67-6266.99" + cell $not $not$ls180.v:6266$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6266$1908_Y + end + attribute \src "ls180.v:6269.67-6269.99" + cell $not $not$ls180.v:6269$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6269$1915_Y + end + attribute \src "ls180.v:6272.65-6272.97" + cell $not $not$ls180.v:6272$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6272$1922_Y + end + attribute \src "ls180.v:6275.64-6275.96" + cell $not $not$ls180.v:6275$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6275$1929_Y + end + attribute \src "ls180.v:6278.63-6278.95" + cell $not $not$ls180.v:6278$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6278$1936_Y + end + attribute \src "ls180.v:6281.62-6281.94" + cell $not $not$ls180.v:6281$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6281$1943_Y + end + attribute \src "ls180.v:6284.68-6284.100" + cell $not $not$ls180.v:6284$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6284$1950_Y + end + attribute \src "ls180.v:6306.67-6306.99" + cell $not $not$ls180.v:6306$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6306$1959_Y + end + attribute \src "ls180.v:6309.67-6309.99" + cell $not $not$ls180.v:6309$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6309$1966_Y + end + attribute \src "ls180.v:6312.65-6312.97" + cell $not $not$ls180.v:6312$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6312$1973_Y + end + attribute \src "ls180.v:6315.64-6315.96" + cell $not $not$ls180.v:6315$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6315$1980_Y + end + attribute \src "ls180.v:6318.63-6318.95" + cell $not $not$ls180.v:6318$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6318$1987_Y + end + attribute \src "ls180.v:6321.62-6321.94" + cell $not $not$ls180.v:6321$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6321$1994_Y + end + attribute \src "ls180.v:6324.68-6324.100" + cell $not $not$ls180.v:6324$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6324$2001_Y + end + attribute \src "ls180.v:6327.71-6327.103" + cell $not $not$ls180.v:6327$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6327$2008_Y + end + attribute \src "ls180.v:6330.71-6330.103" + cell $not $not$ls180.v:6330$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6330$2015_Y + end + attribute \src "ls180.v:6354.64-6354.96" + cell $not $not$ls180.v:6354$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6354$2024_Y + end + attribute \src "ls180.v:6357.64-6357.96" + cell $not $not$ls180.v:6357$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6357$2031_Y + end + attribute \src "ls180.v:6360.64-6360.96" + cell $not $not$ls180.v:6360$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6360$2038_Y + end + attribute \src "ls180.v:6363.64-6363.96" + cell $not $not$ls180.v:6363$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6363$2045_Y + end + attribute \src "ls180.v:6366.66-6366.98" + cell $not $not$ls180.v:6366$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6366$2052_Y + end + attribute \src "ls180.v:6369.66-6369.98" + cell $not $not$ls180.v:6369$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6369$2059_Y + end + attribute \src "ls180.v:6372.66-6372.98" + cell $not $not$ls180.v:6372$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6372$2066_Y + end + attribute \src "ls180.v:6375.66-6375.98" + cell $not $not$ls180.v:6375$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6375$2073_Y + end + attribute \src "ls180.v:6378.62-6378.94" + cell $not $not$ls180.v:6378$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6378$2080_Y + end + attribute \src "ls180.v:6381.72-6381.104" + cell $not $not$ls180.v:6381$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6381$2087_Y + end + attribute \src "ls180.v:6384.65-6384.97" + cell $not $not$ls180.v:6384$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6384$2094_Y + end + attribute \src "ls180.v:6387.65-6387.97" + cell $not $not$ls180.v:6387$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6387$2101_Y + end + attribute \src "ls180.v:6390.65-6390.97" + cell $not $not$ls180.v:6390$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6390$2108_Y + end + attribute \src "ls180.v:6393.65-6393.97" + cell $not $not$ls180.v:6393$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6393$2115_Y + end + attribute \src "ls180.v:6396.77-6396.109" + cell $not $not$ls180.v:6396$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6396$2122_Y + end + attribute \src "ls180.v:6399.78-6399.110" + cell $not $not$ls180.v:6399$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6399$2129_Y + end + attribute \src "ls180.v:6402.69-6402.101" + cell $not $not$ls180.v:6402$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6402$2136_Y + end + attribute \src "ls180.v:6422.55-6422.87" + cell $not $not$ls180.v:6422$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6422$2144_Y + end + attribute \src "ls180.v:6425.65-6425.97" + cell $not $not$ls180.v:6425$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6425$2151_Y + end + attribute \src "ls180.v:6428.66-6428.98" + cell $not $not$ls180.v:6428$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6428$2158_Y + end + attribute \src "ls180.v:6431.70-6431.102" + cell $not $not$ls180.v:6431$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6431$2165_Y + end + attribute \src "ls180.v:6434.71-6434.103" + cell $not $not$ls180.v:6434$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6434$2172_Y + end + attribute \src "ls180.v:6437.69-6437.101" + cell $not $not$ls180.v:6437$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6437$2179_Y + end + attribute \src "ls180.v:6440.66-6440.98" + cell $not $not$ls180.v:6440$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6440$2186_Y + end + attribute \src "ls180.v:6443.65-6443.97" + cell $not $not$ls180.v:6443$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6443$2193_Y + end + attribute \src "ls180.v:6456.71-6456.103" + cell $not $not$ls180.v:6456$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6456$2201_Y + end + attribute \src "ls180.v:6459.71-6459.103" + cell $not $not$ls180.v:6459$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6459$2208_Y + end + attribute \src "ls180.v:6462.71-6462.103" + cell $not $not$ls180.v:6462$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6462$2215_Y + end + attribute \src "ls180.v:6465.71-6465.103" + cell $not $not$ls180.v:6465$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6465$2222_Y + end + attribute \src "ls180.v:6846.86-6846.330" + cell $not $not$ls180.v:6846$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6846$2270_Y + connect \Y $not$ls180.v:6846$2271_Y + end + attribute \src "ls180.v:6870.86-6870.330" + cell $not $not$ls180.v:6870$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6870$2286_Y + connect \Y $not$ls180.v:6870$2287_Y + end + attribute \src "ls180.v:6894.86-6894.330" + cell $not $not$ls180.v:6894$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6894$2302_Y + connect \Y $not$ls180.v:6894$2303_Y + end + attribute \src "ls180.v:6918.86-6918.330" + cell $not $not$ls180.v:6918$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6918$2318_Y + connect \Y $not$ls180.v:6918$2319_Y + end + attribute \src "ls180.v:7416.18-7416.42" + cell $not $not$ls180.v:7416$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7416$2372_Y + end + attribute \src "ls180.v:7507.72-7507.101" + cell $not $not$ls180.v:7507$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7507$2417_Y + end + attribute \src "ls180.v:7526.8-7526.38" + cell $not $not$ls180.v:7526$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7526$2421_Y + end + attribute \src "ls180.v:7534.32-7534.55" + cell $not $not$ls180.v:7534$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7534$2423_Y + end + attribute \src "ls180.v:7604.136-7604.189" + cell $not $not$ls180.v:7604$2438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7604$2438_Y + end + attribute \src "ls180.v:7610.136-7610.189" + cell $not $not$ls180.v:7610$2443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7610$2443_Y + end + attribute \src "ls180.v:7611.8-7611.61" + cell $not $not$ls180.v:7611$2445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7611$2445_Y + end + attribute \src "ls180.v:7619.8-7619.56" + cell $not $not$ls180.v:7619$2448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7619$2448_Y + end + attribute \src "ls180.v:7634.8-7634.46" + cell $not $not$ls180.v:7634$2450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7634$2450_Y + end + attribute \src "ls180.v:7650.136-7650.189" + cell $not $not$ls180.v:7650$2454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7650$2454_Y + end + attribute \src "ls180.v:7656.136-7656.189" + cell $not $not$ls180.v:7656$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7656$2459_Y + end + attribute \src "ls180.v:7657.8-7657.61" + cell $not $not$ls180.v:7657$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7657$2461_Y + end + attribute \src "ls180.v:7665.8-7665.56" + cell $not $not$ls180.v:7665$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7665$2464_Y + end + attribute \src "ls180.v:7680.8-7680.46" + cell $not $not$ls180.v:7680$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7680$2466_Y + end + attribute \src "ls180.v:7696.136-7696.189" + cell $not $not$ls180.v:7696$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7696$2470_Y + end + attribute \src "ls180.v:7702.136-7702.189" + cell $not $not$ls180.v:7702$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7702$2475_Y + end + attribute \src "ls180.v:7703.8-7703.61" + cell $not $not$ls180.v:7703$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7703$2477_Y + end + attribute \src "ls180.v:7711.8-7711.56" + cell $not $not$ls180.v:7711$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7711$2480_Y + end + attribute \src "ls180.v:7726.8-7726.46" + cell $not $not$ls180.v:7726$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:7726$2482_Y + end + attribute \src "ls180.v:7742.136-7742.189" + cell $not $not$ls180.v:7742$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7742$2486_Y + end + attribute \src "ls180.v:7748.136-7748.189" + cell $not $not$ls180.v:7748$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7748$2491_Y + end + attribute \src "ls180.v:7749.8-7749.61" + cell $not $not$ls180.v:7749$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7749$2493_Y + end + attribute \src "ls180.v:7757.8-7757.56" + cell $not $not$ls180.v:7757$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:7757$2496_Y + end + attribute \src "ls180.v:7772.8-7772.46" + cell $not $not$ls180.v:7772$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:7772$2498_Y + end + attribute \src "ls180.v:7780.7-7780.22" + cell $not $not$ls180.v:7780$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:7780$2501_Y + end + attribute \src "ls180.v:7783.8-7783.29" + cell $not $not$ls180.v:7783$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:7783$2502_Y + end + attribute \src "ls180.v:7787.7-7787.22" + cell $not $not$ls180.v:7787$2504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:7787$2504_Y + end + attribute \src "ls180.v:7790.8-7790.29" + cell $not $not$ls180.v:7790$2505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:7790$2505_Y + end + attribute \src "ls180.v:7909.30-7909.60" + cell $not $not$ls180.v:7909$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:7909$2507_Y + end + attribute \src "ls180.v:7910.30-7910.60" + cell $not $not$ls180.v:7910$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:7910$2508_Y + end + attribute \src "ls180.v:7911.29-7911.59" + cell $not $not$ls180.v:7911$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:7911$2509_Y + end + attribute \src "ls180.v:7922.8-7922.33" + cell $not $not$ls180.v:7922$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:7922$2510_Y + end + attribute \src "ls180.v:7937.8-7937.33" + cell $not $not$ls180.v:7937$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:7937$2513_Y + end + attribute \src "ls180.v:7973.36-7973.58" + cell $not $not$ls180.v:7973$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_busy + connect \Y $not$ls180.v:7973$2543_Y + end + attribute \src "ls180.v:7973.64-7973.89" + cell $not $not$ls180.v:7973$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_ready + connect \Y $not$ls180.v:7973$2545_Y + end + attribute \src "ls180.v:8002.7-8002.29" + cell $not $not$ls180.v:8002$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_busy + connect \Y $not$ls180.v:8002$2552_Y + end + attribute \src "ls180.v:8003.9-8003.26" + cell $not $not$ls180.v:8003$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx + connect \Y $not$ls180.v:8003$2553_Y + end + attribute \src "ls180.v:8036.8-8036.29" + cell $not $not$ls180.v:8036$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:8036$2559_Y + end + attribute \src "ls180.v:8043.8-8043.29" + cell $not $not$ls180.v:8043$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:8043$2561_Y + end + attribute \src "ls180.v:8053.80-8053.106" + cell $not $not$ls180.v:8053$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8053$2564_Y + end + attribute \src "ls180.v:8059.80-8059.106" + cell $not $not$ls180.v:8059$2569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8059$2569_Y + end + attribute \src "ls180.v:8060.8-8060.34" + cell $not $not$ls180.v:8060$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:8060$2571_Y + end + attribute \src "ls180.v:8075.80-8075.106" + cell $not $not$ls180.v:8075$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8075$2575_Y + end + attribute \src "ls180.v:8081.80-8081.106" + cell $not $not$ls180.v:8081$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8081$2580_Y + end + attribute \src "ls180.v:8082.8-8082.34" + cell $not $not$ls180.v:8082$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8082$2582_Y + end + attribute \src "ls180.v:8113.22-8113.41" + cell $not $not$ls180.v:8113$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster6_cs + connect \Y $not$ls180.v:8113$2586_Y + end + attribute \src "ls180.v:8113.46-8113.73" + cell $not $not$ls180.v:8113$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster26_cs_enable + connect \Y $not$ls180.v:8113$2587_Y + end + attribute \src "ls180.v:8148.22-8148.40" + cell $not $not$ls180.v:8148$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs + connect \Y $not$ls180.v:8148$2591_Y + end + attribute \src "ls180.v:8148.45-8148.70" + cell $not $not$ls180.v:8148$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs_enable + connect \Y $not$ls180.v:8148$2592_Y + end + attribute \src "ls180.v:8202.7-8202.31" + cell $not $not$ls180.v:8202$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8202$2603_Y + end + attribute \src "ls180.v:8274.8-8274.46" + cell $not $not$ls180.v:8274$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8274$2615_Y + end + attribute \src "ls180.v:8355.8-8355.47" + cell $not $not$ls180.v:8355$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8355$2627_Y + end + attribute \src "ls180.v:8416.8-8416.48" + cell $not $not$ls180.v:8416$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8416$2639_Y + end + attribute \src "ls180.v:8586.88-8586.118" + cell $not $not$ls180.v:8586$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8586$2653_Y + end + attribute \src "ls180.v:8592.88-8592.118" + cell $not $not$ls180.v:8592$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8592$2658_Y + end + attribute \src "ls180.v:8593.8-8593.38" + cell $not $not$ls180.v:8593$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8593$2660_Y + end + attribute \src "ls180.v:8672.88-8672.118" + cell $not $not$ls180.v:8672$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8672$2675_Y + end + attribute \src "ls180.v:8678.88-8678.118" + cell $not $not$ls180.v:8678$2680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8678$2680_Y + end + attribute \src "ls180.v:8679.8-8679.38" + cell $not $not$ls180.v:8679$2682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8679$2682_Y + end + attribute \src "ls180.v:8699.9-8699.28" + cell $not $not$ls180.v:8699$2685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8699$2685_Y + end + attribute \src "ls180.v:8718.9-8718.28" + cell $not $not$ls180.v:8718$2686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:8718$2686_Y + end + attribute \src "ls180.v:8737.9-8737.28" + cell $not $not$ls180.v:8737$2687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:8737$2687_Y + end + attribute \src "ls180.v:8756.9-8756.28" + cell $not $not$ls180.v:8756$2688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:8756$2688_Y + end + attribute \src "ls180.v:8775.9-8775.28" + cell $not $not$ls180.v:8775$2689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:8775$2689_Y + end + attribute \src "ls180.v:8796.8-8796.21" + cell $not $not$ls180.v:8796$2690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:8796$2690_Y + end + attribute \src "ls180.v:10295.8-10295.51" + cell $or $or$ls180.v:10295$2762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10295$2762_Y + end + attribute \src "ls180.v:2818.10-2818.96" + cell $or $or$ls180.v:2818$21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:2818$21_Y + end + attribute \src "ls180.v:2878.10-2878.96" + cell $or $or$ls180.v:2878$32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:2878$32_Y + end + attribute \src "ls180.v:2938.10-2938.96" + cell $or $or$ls180.v:2938$43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:2938$43_Y + end + attribute \src "ls180.v:3130.39-3130.105" + cell $or $or$ls180.v:3130$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3130$74_Y + connect \Y $or$ls180.v:3130$75_Y + end + attribute \src "ls180.v:3173.59-3173.140" + cell $or $or$ls180.v:3173$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3173$79_Y + end + attribute \src "ls180.v:3174.44-3174.151" + cell $or $or$ls180.v:3174$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3174$80_Y + end + attribute \src "ls180.v:3182.45-3182.170" + cell $or $or$ls180.v:3182$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3182$83_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3182$84_Y + end + attribute \src "ls180.v:3219.127-3219.245" + cell $or $or$ls180.v:3219$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3219$97_Y + end + attribute \src "ls180.v:3225.57-3225.157" + cell $or $or$ls180.v:3225$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3225$102_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3225$103_Y + end + attribute \src "ls180.v:3330.59-3330.140" + cell $or $or$ls180.v:3330$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3330$109_Y + end + attribute \src "ls180.v:3331.44-3331.151" + cell $or $or$ls180.v:3331$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3331$110_Y + end + attribute \src "ls180.v:3339.45-3339.170" + cell $or $or$ls180.v:3339$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3339$113_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3339$114_Y + end + attribute \src "ls180.v:3376.127-3376.245" + cell $or $or$ls180.v:3376$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3376$127_Y + end + attribute \src "ls180.v:3382.57-3382.157" + cell $or $or$ls180.v:3382$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3382$132_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3382$133_Y + end + attribute \src "ls180.v:3487.59-3487.140" + cell $or $or$ls180.v:3487$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3487$139_Y + end + attribute \src "ls180.v:3488.44-3488.151" + cell $or $or$ls180.v:3488$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3488$140_Y + end + attribute \src "ls180.v:3496.45-3496.170" + cell $or $or$ls180.v:3496$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3496$143_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3496$144_Y + end + attribute \src "ls180.v:3533.127-3533.245" + cell $or $or$ls180.v:3533$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3533$157_Y + end + attribute \src "ls180.v:3539.57-3539.157" + cell $or $or$ls180.v:3539$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3539$162_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3539$163_Y + end + attribute \src "ls180.v:3644.59-3644.140" + cell $or $or$ls180.v:3644$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3644$169_Y + end + attribute \src "ls180.v:3645.44-3645.151" + cell $or $or$ls180.v:3645$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3645$170_Y + end + attribute \src "ls180.v:3653.45-3653.170" + cell $or $or$ls180.v:3653$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3653$173_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3653$174_Y + end + attribute \src "ls180.v:3690.127-3690.245" + cell $or $or$ls180.v:3690$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3690$187_Y + end + attribute \src "ls180.v:3696.57-3696.157" + cell $or $or$ls180.v:3696$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3696$192_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3696$193_Y + end + attribute \src "ls180.v:3795.107-3795.193" + cell $or $or$ls180.v:3795$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3795$213_Y + end + attribute \src "ls180.v:3798.39-3798.204" + cell $or $or$ls180.v:3798$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3798$217_Y + connect \B $and$ls180.v:3798$218_Y + connect \Y $or$ls180.v:3798$219_Y + end + attribute \src "ls180.v:3798.38-3798.289" + cell $or $or$ls180.v:3798$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3798$219_Y + connect \B $and$ls180.v:3798$220_Y + connect \Y $or$ls180.v:3798$221_Y + end + attribute \src "ls180.v:3798.37-3798.374" + cell $or $or$ls180.v:3798$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3798$221_Y + connect \B $and$ls180.v:3798$222_Y + connect \Y $or$ls180.v:3798$223_Y + end + attribute \src "ls180.v:3799.40-3799.207" + cell $or $or$ls180.v:3799$226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3799$224_Y + connect \B $and$ls180.v:3799$225_Y + connect \Y $or$ls180.v:3799$226_Y + end + attribute \src "ls180.v:3799.39-3799.293" + cell $or $or$ls180.v:3799$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3799$226_Y + connect \B $and$ls180.v:3799$227_Y + connect \Y $or$ls180.v:3799$228_Y + end + attribute \src "ls180.v:3799.38-3799.379" + cell $or $or$ls180.v:3799$230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3799$228_Y + connect \B $and$ls180.v:3799$229_Y + connect \Y $or$ls180.v:3799$230_Y + end + attribute \src "ls180.v:3812.158-3812.332" + cell $or $or$ls180.v:3812$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3812$243_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3812$244_Y + end + attribute \src "ls180.v:3812.75-3812.506" + cell $or $or$ls180.v:3812$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3812$245_Y + connect \B $and$ls180.v:3812$248_Y + connect \Y $or$ls180.v:3812$249_Y + end + attribute \src "ls180.v:3813.158-3813.332" + cell $or $or$ls180.v:3813$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3813$256_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3813$257_Y + end + attribute \src "ls180.v:3813.75-3813.506" + cell $or $or$ls180.v:3813$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3813$258_Y + connect \B $and$ls180.v:3813$261_Y + connect \Y $or$ls180.v:3813$262_Y + end + attribute \src "ls180.v:3814.158-3814.332" + cell $or $or$ls180.v:3814$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3814$269_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3814$270_Y + end + attribute \src "ls180.v:3814.75-3814.506" + cell $or $or$ls180.v:3814$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3814$271_Y + connect \B $and$ls180.v:3814$274_Y + connect \Y $or$ls180.v:3814$275_Y + end + attribute \src "ls180.v:3815.158-3815.332" + cell $or $or$ls180.v:3815$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3815$282_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3815$283_Y + end + attribute \src "ls180.v:3815.75-3815.506" + cell $or $or$ls180.v:3815$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3815$284_Y + connect \B $and$ls180.v:3815$287_Y + connect \Y $or$ls180.v:3815$288_Y + end + attribute \src "ls180.v:3842.36-3842.104" + cell $or $or$ls180.v:3842$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:3842$293_Y + connect \Y $or$ls180.v:3842$294_Y + end + attribute \src "ls180.v:3845.158-3845.332" + cell $or $or$ls180.v:3845$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3845$301_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3845$302_Y + end + attribute \src "ls180.v:3845.75-3845.506" + cell $or $or$ls180.v:3845$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3845$303_Y + connect \B $and$ls180.v:3845$306_Y + connect \Y $or$ls180.v:3845$307_Y + end + attribute \src "ls180.v:3846.158-3846.332" + cell $or $or$ls180.v:3846$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3846$314_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3846$315_Y + end + attribute \src "ls180.v:3846.75-3846.506" + cell $or $or$ls180.v:3846$320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3846$316_Y + connect \B $and$ls180.v:3846$319_Y + connect \Y $or$ls180.v:3846$320_Y + end + attribute \src "ls180.v:3847.158-3847.332" + cell $or $or$ls180.v:3847$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3847$327_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3847$328_Y + end + attribute \src "ls180.v:3847.75-3847.506" + cell $or $or$ls180.v:3847$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3847$329_Y + connect \B $and$ls180.v:3847$332_Y + connect \Y $or$ls180.v:3847$333_Y + end + attribute \src "ls180.v:3848.158-3848.332" + cell $or $or$ls180.v:3848$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3848$340_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:3848$341_Y + end + attribute \src "ls180.v:3848.75-3848.506" + cell $or $or$ls180.v:3848$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3848$342_Y + connect \B $and$ls180.v:3848$345_Y + connect \Y $or$ls180.v:3848$346_Y + end + attribute \src "ls180.v:3911.36-3911.104" + cell $or $or$ls180.v:3911$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:3911$379_Y + connect \Y $or$ls180.v:3911$380_Y + end + attribute \src "ls180.v:3932.67-3932.221" + cell $or $or$ls180.v:3932$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3932$386_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3932$387_Y + end + attribute \src "ls180.v:3940.10-3940.62" + cell $or $or$ls180.v:3940$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3940$389_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:3940$390_Y + end + attribute \src "ls180.v:3970.67-3970.221" + cell $or $or$ls180.v:3970$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3970$395_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:3970$396_Y + end + attribute \src "ls180.v:3978.10-3978.61" + cell $or $or$ls180.v:3978$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3978$398_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:3978$399_Y + end + attribute \src "ls180.v:3988.91-3988.180" + cell $or $or$ls180.v:3988$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:3988$402_Y + connect \Y $or$ls180.v:3988$403_Y + end + attribute \src "ls180.v:3988.90-3988.255" + cell $or $or$ls180.v:3988$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$403_Y + connect \B $and$ls180.v:3988$405_Y + connect \Y $or$ls180.v:3988$406_Y + end + attribute \src "ls180.v:3988.89-3988.330" + cell $or $or$ls180.v:3988$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3988$406_Y + connect \B $and$ls180.v:3988$408_Y + connect \Y $or$ls180.v:3988$409_Y + end + attribute \src "ls180.v:3993.91-3993.180" + cell $or $or$ls180.v:3993$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:3993$418_Y + connect \Y $or$ls180.v:3993$419_Y + end + attribute \src "ls180.v:3993.90-3993.255" + cell $or $or$ls180.v:3993$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3993$419_Y + connect \B $and$ls180.v:3993$421_Y + connect \Y $or$ls180.v:3993$422_Y + end + attribute \src "ls180.v:3993.89-3993.330" + cell $or $or$ls180.v:3993$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3993$422_Y + connect \B $and$ls180.v:3993$424_Y + connect \Y $or$ls180.v:3993$425_Y + end + attribute \src "ls180.v:3998.91-3998.180" + cell $or $or$ls180.v:3998$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:3998$434_Y + connect \Y $or$ls180.v:3998$435_Y + end + attribute \src "ls180.v:3998.90-3998.255" + cell $or $or$ls180.v:3998$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3998$435_Y + connect \B $and$ls180.v:3998$437_Y + connect \Y $or$ls180.v:3998$438_Y + end + attribute \src "ls180.v:3998.89-3998.330" + cell $or $or$ls180.v:3998$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3998$438_Y + connect \B $and$ls180.v:3998$440_Y + connect \Y $or$ls180.v:3998$441_Y + end + attribute \src "ls180.v:4003.91-4003.180" + cell $or $or$ls180.v:4003$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4003$450_Y + connect \Y $or$ls180.v:4003$451_Y + end + attribute \src "ls180.v:4003.90-4003.255" + cell $or $or$ls180.v:4003$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4003$451_Y + connect \B $and$ls180.v:4003$453_Y + connect \Y $or$ls180.v:4003$454_Y + end + attribute \src "ls180.v:4003.89-4003.330" + cell $or $or$ls180.v:4003$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4003$454_Y + connect \B $and$ls180.v:4003$456_Y + connect \Y $or$ls180.v:4003$457_Y + end + attribute \src "ls180.v:4008.132-4008.221" + cell $or $or$ls180.v:4008$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4008$467_Y + connect \Y $or$ls180.v:4008$468_Y + end + attribute \src "ls180.v:4008.131-4008.296" + cell $or $or$ls180.v:4008$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$468_Y + connect \B $and$ls180.v:4008$470_Y + connect \Y $or$ls180.v:4008$471_Y + end + attribute \src "ls180.v:4008.130-4008.371" + cell $or $or$ls180.v:4008$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$471_Y + connect \B $and$ls180.v:4008$473_Y + connect \Y $or$ls180.v:4008$474_Y + end + attribute \src "ls180.v:4008.34-4008.411" + cell $or $or$ls180.v:4008$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:4008$478_Y + connect \Y $or$ls180.v:4008$479_Y + end + attribute \src "ls180.v:4008.506-4008.595" + cell $or $or$ls180.v:4008$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4008$483_Y + connect \Y $or$ls180.v:4008$484_Y + end + attribute \src "ls180.v:4008.505-4008.670" + cell $or $or$ls180.v:4008$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$484_Y + connect \B $and$ls180.v:4008$486_Y + connect \Y $or$ls180.v:4008$487_Y + end + attribute \src "ls180.v:4008.504-4008.745" + cell $or $or$ls180.v:4008$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$487_Y + connect \B $and$ls180.v:4008$489_Y + connect \Y $or$ls180.v:4008$490_Y + end + attribute \src "ls180.v:4008.33-4008.785" + cell $or $or$ls180.v:4008$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$479_Y + connect \B $and$ls180.v:4008$494_Y + connect \Y $or$ls180.v:4008$495_Y + end + attribute \src "ls180.v:4008.880-4008.969" + cell $or $or$ls180.v:4008$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4008$499_Y + connect \Y $or$ls180.v:4008$500_Y + end + attribute \src "ls180.v:4008.879-4008.1044" + cell $or $or$ls180.v:4008$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$500_Y + connect \B $and$ls180.v:4008$502_Y + connect \Y $or$ls180.v:4008$503_Y + end + attribute \src "ls180.v:4008.878-4008.1119" + cell $or $or$ls180.v:4008$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$503_Y + connect \B $and$ls180.v:4008$505_Y + connect \Y $or$ls180.v:4008$506_Y + end + attribute \src "ls180.v:4008.32-4008.1159" + cell $or $or$ls180.v:4008$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$495_Y + connect \B $and$ls180.v:4008$510_Y + connect \Y $or$ls180.v:4008$511_Y + end + attribute \src "ls180.v:4008.1254-4008.1343" + cell $or $or$ls180.v:4008$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4008$515_Y + connect \Y $or$ls180.v:4008$516_Y + end + attribute \src "ls180.v:4008.1253-4008.1418" + cell $or $or$ls180.v:4008$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$516_Y + connect \B $and$ls180.v:4008$518_Y + connect \Y $or$ls180.v:4008$519_Y + end + attribute \src "ls180.v:4008.1252-4008.1493" + cell $or $or$ls180.v:4008$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$519_Y + connect \B $and$ls180.v:4008$521_Y + connect \Y $or$ls180.v:4008$522_Y + end + attribute \src "ls180.v:4008.31-4008.1533" + cell $or $or$ls180.v:4008$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4008$511_Y + connect \B $and$ls180.v:4008$526_Y + connect \Y $or$ls180.v:4008$527_Y + end + attribute \src "ls180.v:4071.10-4071.52" + cell $or $or$ls180.v:4071$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4071$536_Y + end + attribute \src "ls180.v:4098.35-4098.74" + cell $or $or$ls180.v:4098$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4098$546_Y + end + attribute \src "ls180.v:4099.34-4099.73" + cell $or $or$ls180.v:4099$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4099$550_Y + end + attribute \src "ls180.v:4100.48-4100.130" + cell $or $or$ls180.v:4100$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4100$553_Y + connect \B $and$ls180.v:4100$555_Y + connect \Y $or$ls180.v:4100$556_Y + end + attribute \src "ls180.v:4101.24-4101.87" + cell $or $or$ls180.v:4101$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4101$558_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4101$559_Y + end + attribute \src "ls180.v:4102.26-4102.95" + cell $or $or$ls180.v:4102$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4102$560_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4102$561_Y + end + attribute \src "ls180.v:4132.42-4132.89" + cell $or $or$ls180.v:4132$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4132$568_Y + connect \Y $or$ls180.v:4132$569_Y + end + attribute \src "ls180.v:4156.25-4156.174" + cell $or $or$ls180.v:4156$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4156$577_Y + connect \B $and$ls180.v:4156$578_Y + connect \Y $or$ls180.v:4156$579_Y + end + attribute \src "ls180.v:4171.80-4171.132" + cell $or $or$ls180.v:4171$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4171$580_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4171$581_Y + end + attribute \src "ls180.v:4182.72-4182.135" + cell $or $or$ls180.v:4182$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4182$586_Y + end + attribute \src "ls180.v:4201.80-4201.132" + cell $or $or$ls180.v:4201$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4201$591_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4201$592_Y + end + attribute \src "ls180.v:4212.72-4212.135" + cell $or $or$ls180.v:4212$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4212$597_Y + end + attribute \src "ls180.v:4346.36-4346.111" + cell $or $or$ls180.v:4346$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4346$618_Y + end + attribute \src "ls180.v:4346.35-4346.151" + cell $or $or$ls180.v:4346$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4346$618_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4346$619_Y + end + attribute \src "ls180.v:4346.34-4346.192" + cell $or $or$ls180.v:4346$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4346$619_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4346$620_Y + end + attribute \src "ls180.v:4346.33-4346.233" + cell $or $or$ls180.v:4346$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4346$620_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4346$621_Y + end + attribute \src "ls180.v:4347.39-4347.120" + cell $or $or$ls180.v:4347$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4347$622_Y + end + attribute \src "ls180.v:4347.38-4347.163" + cell $or $or$ls180.v:4347$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4347$622_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4347$623_Y + end + attribute \src "ls180.v:4347.37-4347.207" + cell $or $or$ls180.v:4347$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4347$623_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4347$624_Y + end + attribute \src "ls180.v:4347.36-4347.251" + cell $or $or$ls180.v:4347$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4347$624_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4347$625_Y + end + attribute \src "ls180.v:4348.38-4348.117" + cell $or $or$ls180.v:4348$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4348$626_Y + end + attribute \src "ls180.v:4348.37-4348.159" + cell $or $or$ls180.v:4348$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4348$626_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4348$627_Y + end + attribute \src "ls180.v:4348.36-4348.202" + cell $or $or$ls180.v:4348$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4348$627_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4348$628_Y + end + attribute \src "ls180.v:4348.35-4348.245" + cell $or $or$ls180.v:4348$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4348$628_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4348$629_Y + end + attribute \src "ls180.v:4349.40-4349.123" + cell $or $or$ls180.v:4349$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4349$630_Y + end + attribute \src "ls180.v:4349.39-4349.167" + cell $or $or$ls180.v:4349$631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4349$630_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4349$631_Y + end + attribute \src "ls180.v:4349.38-4349.212" + cell $or $or$ls180.v:4349$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4349$631_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4349$632_Y + end + attribute \src "ls180.v:4349.37-4349.257" + cell $or $or$ls180.v:4349$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4349$632_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4349$633_Y + end + attribute \src "ls180.v:4350.39-4350.120" + cell $or $or$ls180.v:4350$634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4350$634_Y + end + attribute \src "ls180.v:4350.38-4350.163" + cell $or $or$ls180.v:4350$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4350$634_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4350$635_Y + end + attribute \src "ls180.v:4350.37-4350.207" + cell $or $or$ls180.v:4350$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4350$635_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4350$636_Y + end + attribute \src "ls180.v:4350.36-4350.251" + cell $or $or$ls180.v:4350$637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4350$636_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4350$637_Y + end + attribute \src "ls180.v:4371.35-4371.80" + cell $or $or$ls180.v:4371$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4371$638_Y + end + attribute \src "ls180.v:4525.91-4525.144" + cell $or $or$ls180.v:4525$652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4525$652_Y + end + attribute \src "ls180.v:4542.53-4542.143" + cell $or $or$ls180.v:4542$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4542$654_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4542$655_Y + end + attribute \src "ls180.v:4545.47-4545.127" + cell $or $or$ls180.v:4545$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4545$657_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4545$658_Y + end + attribute \src "ls180.v:4669.54-4669.146" + cell $or $or$ls180.v:4669$676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4669$675_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4669$676_Y + end + attribute \src "ls180.v:4672.48-4672.130" + cell $or $or$ls180.v:4672$679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4672$678_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4672$679_Y + end + attribute \src "ls180.v:4803.55-4803.149" + cell $or $or$ls180.v:4803$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4803$690_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4803$691_Y + end + attribute \src "ls180.v:4806.49-4806.133" + cell $or $or$ls180.v:4806$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4806$693_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4806$694_Y + end + attribute \src "ls180.v:5435.80-5435.151" + cell $or $or$ls180.v:5435$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5435$989_Y + end + attribute \src "ls180.v:5446.49-5446.131" + cell $or $or$ls180.v:5446$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5446$994_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5446$995_Y + end + attribute \src "ls180.v:5643.80-5643.151" + cell $or $or$ls180.v:5643$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5643$1020_Y + end + attribute \src "ls180.v:5758.33-5758.102" + cell $or $or$ls180.v:5758$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_libresocsim_libresoc_xics_icp_err + connect \Y $or$ls180.v:5758$1060_Y + end + attribute \src "ls180.v:5758.32-5758.144" + cell $or $or$ls180.v:5758$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5758$1060_Y + connect \B \main_libresocsim_libresoc_xics_ics_err + connect \Y $or$ls180.v:5758$1061_Y + end + attribute \src "ls180.v:5758.31-5758.165" + cell $or $or$ls180.v:5758$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5758$1061_Y + connect \B \main_wb_sdram_err + connect \Y $or$ls180.v:5758$1062_Y + end + attribute \src "ls180.v:5758.30-5758.201" + cell $or $or$ls180.v:5758$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5758$1062_Y + connect \B \builder_libresocsim_wishbone_err + connect \Y $or$ls180.v:5758$1063_Y + end + attribute \src "ls180.v:5764.28-5764.97" + cell $or $or$ls180.v:5764$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_libresocsim_libresoc_xics_icp_ack + connect \Y $or$ls180.v:5764$1068_Y + end + attribute \src "ls180.v:5764.27-5764.139" + cell $or $or$ls180.v:5764$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5764$1068_Y + connect \B \main_libresocsim_libresoc_xics_ics_ack + connect \Y $or$ls180.v:5764$1069_Y + end + attribute \src "ls180.v:5764.26-5764.160" + cell $or $or$ls180.v:5764$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5764$1069_Y + connect \B \main_wb_sdram_ack + connect \Y $or$ls180.v:5764$1070_Y + end + attribute \src "ls180.v:5764.25-5764.196" + cell $or $or$ls180.v:5764$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:5764$1070_Y + connect \B \builder_libresocsim_wishbone_ack + connect \Y $or$ls180.v:5764$1071_Y + end + attribute \src "ls180.v:5765.30-5765.169" + cell $or $or$ls180.v:5765$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $and$ls180.v:5765$1072_Y + connect \B $and$ls180.v:5765$1073_Y + connect \Y $or$ls180.v:5765$1074_Y + end + attribute \src "ls180.v:5765.29-5765.246" + cell $or $or$ls180.v:5765$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5765$1074_Y + connect \B $and$ls180.v:5765$1075_Y + connect \Y $or$ls180.v:5765$1076_Y + end + attribute \src "ls180.v:5765.28-5765.302" + cell $or $or$ls180.v:5765$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5765$1076_Y + connect \B $and$ls180.v:5765$1077_Y + connect \Y $or$ls180.v:5765$1078_Y + end + attribute \src "ls180.v:5765.27-5765.373" + cell $or $or$ls180.v:5765$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$ls180.v:5765$1078_Y + connect \B $and$ls180.v:5765$1079_Y + connect \Y $or$ls180.v:5765$1080_Y + end + attribute \src "ls180.v:6519.55-6519.124" + cell $or $or$ls180.v:6519$2226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2226_Y + end + attribute \src "ls180.v:6519.54-6519.161" + cell $or $or$ls180.v:6519$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2226_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2227_Y + end + attribute \src "ls180.v:6519.53-6519.198" + cell $or $or$ls180.v:6519$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2227_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2228_Y + end + attribute \src "ls180.v:6519.52-6519.235" + cell $or $or$ls180.v:6519$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2228_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2229_Y + end + attribute \src "ls180.v:6519.51-6519.272" + cell $or $or$ls180.v:6519$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2229_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2230_Y + end + attribute \src "ls180.v:6519.50-6519.309" + cell $or $or$ls180.v:6519$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2230_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2231_Y + end + attribute \src "ls180.v:6519.49-6519.346" + cell $or $or$ls180.v:6519$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2231_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2232_Y + end + attribute \src "ls180.v:6519.48-6519.383" + cell $or $or$ls180.v:6519$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2232_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2233_Y + end + attribute \src "ls180.v:6519.47-6519.420" + cell $or $or$ls180.v:6519$2234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2233_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2234_Y + end + attribute \src "ls180.v:6519.46-6519.458" + cell $or $or$ls180.v:6519$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2234_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2235_Y + end + attribute \src "ls180.v:6519.45-6519.496" + cell $or $or$ls180.v:6519$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2235_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2236_Y + end + attribute \src "ls180.v:6519.44-6519.534" + cell $or $or$ls180.v:6519$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2236_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2237_Y + end + attribute \src "ls180.v:6519.43-6519.572" + cell $or $or$ls180.v:6519$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2237_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2238_Y + end + attribute \src "ls180.v:6519.42-6519.610" + cell $or $or$ls180.v:6519$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6519$2238_Y + connect \B \builder_interface14_bank_bus_dat_r + connect \Y $or$ls180.v:6519$2239_Y + end + attribute \src "ls180.v:6846.90-6846.179" + cell $or $or$ls180.v:6846$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:6846$2263_Y + connect \Y $or$ls180.v:6846$2264_Y + end + attribute \src "ls180.v:6846.89-6846.254" + cell $or $or$ls180.v:6846$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6846$2264_Y + connect \B $and$ls180.v:6846$2266_Y + connect \Y $or$ls180.v:6846$2267_Y + end + attribute \src "ls180.v:6846.88-6846.329" + cell $or $or$ls180.v:6846$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6846$2267_Y + connect \B $and$ls180.v:6846$2269_Y + connect \Y $or$ls180.v:6846$2270_Y + end + attribute \src "ls180.v:6870.90-6870.179" + cell $or $or$ls180.v:6870$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:6870$2279_Y + connect \Y $or$ls180.v:6870$2280_Y + end + attribute \src "ls180.v:6870.89-6870.254" + cell $or $or$ls180.v:6870$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6870$2280_Y + connect \B $and$ls180.v:6870$2282_Y + connect \Y $or$ls180.v:6870$2283_Y + end + attribute \src "ls180.v:6870.88-6870.329" + cell $or $or$ls180.v:6870$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6870$2283_Y + connect \B $and$ls180.v:6870$2285_Y + connect \Y $or$ls180.v:6870$2286_Y + end + attribute \src "ls180.v:6894.90-6894.179" + cell $or $or$ls180.v:6894$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:6894$2295_Y + connect \Y $or$ls180.v:6894$2296_Y + end + attribute \src "ls180.v:6894.89-6894.254" + cell $or $or$ls180.v:6894$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6894$2296_Y + connect \B $and$ls180.v:6894$2298_Y + connect \Y $or$ls180.v:6894$2299_Y + end + attribute \src "ls180.v:6894.88-6894.329" + cell $or $or$ls180.v:6894$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6894$2299_Y + connect \B $and$ls180.v:6894$2301_Y + connect \Y $or$ls180.v:6894$2302_Y + end + attribute \src "ls180.v:6918.90-6918.179" + cell $or $or$ls180.v:6918$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:6918$2311_Y + connect \Y $or$ls180.v:6918$2312_Y + end + attribute \src "ls180.v:6918.89-6918.254" + cell $or $or$ls180.v:6918$2315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6918$2312_Y + connect \B $and$ls180.v:6918$2314_Y + connect \Y $or$ls180.v:6918$2315_Y + end + attribute \src "ls180.v:6918.88-6918.329" + cell $or $or$ls180.v:6918$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6918$2315_Y + connect \B $and$ls180.v:6918$2317_Y + connect \Y $or$ls180.v:6918$2318_Y + end + attribute \src "ls180.v:7432.20-7432.71" + cell $or $or$ls180.v:7432$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7432$2375_Y + end + attribute \src "ls180.v:7433.20-7433.71" + cell $or $or$ls180.v:7433$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7433$2376_Y + end + attribute \src "ls180.v:7434.20-7434.71" + cell $or $or$ls180.v:7434$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7434$2377_Y + end + attribute \src "ls180.v:7435.20-7435.71" + cell $or $or$ls180.v:7435$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7435$2378_Y + end + attribute \src "ls180.v:7436.20-7436.71" + cell $or $or$ls180.v:7436$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7436$2379_Y + end + attribute \src "ls180.v:7437.20-7437.71" + cell $or $or$ls180.v:7437$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7437$2380_Y + end + attribute \src "ls180.v:7438.20-7438.71" + cell $or $or$ls180.v:7438$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7438$2381_Y + end + attribute \src "ls180.v:7439.20-7439.71" + cell $or $or$ls180.v:7439$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7439$2382_Y + end + attribute \src "ls180.v:7440.20-7440.71" + cell $or $or$ls180.v:7440$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7440$2383_Y + end + attribute \src "ls180.v:7441.20-7441.71" + cell $or $or$ls180.v:7441$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7441$2384_Y + end + attribute \src "ls180.v:7442.21-7442.73" + cell $or $or$ls180.v:7442$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7442$2385_Y + end + attribute \src "ls180.v:7443.21-7443.73" + cell $or $or$ls180.v:7443$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7443$2386_Y + end + attribute \src "ls180.v:7444.21-7444.73" + cell $or $or$ls180.v:7444$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7444$2387_Y + end + attribute \src "ls180.v:7445.21-7445.73" + cell $or $or$ls180.v:7445$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7445$2388_Y + end + attribute \src "ls180.v:7446.21-7446.73" + cell $or $or$ls180.v:7446$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7446$2389_Y + end + attribute \src "ls180.v:7447.21-7447.73" + cell $or $or$ls180.v:7447$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7447$2390_Y + end + attribute \src "ls180.v:7448.21-7448.73" + cell $or $or$ls180.v:7448$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7448$2391_Y + end + attribute \src "ls180.v:7449.21-7449.73" + cell $or $or$ls180.v:7449$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7449$2392_Y + end + attribute \src "ls180.v:7450.21-7450.73" + cell $or $or$ls180.v:7450$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7450$2393_Y + end + attribute \src "ls180.v:7451.21-7451.73" + cell $or $or$ls180.v:7451$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7451$2394_Y + end + attribute \src "ls180.v:7452.21-7452.73" + cell $or $or$ls180.v:7452$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7452$2395_Y + end + attribute \src "ls180.v:7453.21-7453.73" + cell $or $or$ls180.v:7453$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7453$2396_Y + end + attribute \src "ls180.v:7454.21-7454.73" + cell $or $or$ls180.v:7454$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7454$2397_Y + end + attribute \src "ls180.v:7455.21-7455.73" + cell $or $or$ls180.v:7455$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7455$2398_Y + end + attribute \src "ls180.v:7456.21-7456.73" + cell $or $or$ls180.v:7456$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [24] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7456$2399_Y + end + attribute \src "ls180.v:7457.21-7457.73" + cell $or $or$ls180.v:7457$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [25] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7457$2400_Y + end + attribute \src "ls180.v:7458.21-7458.73" + cell $or $or$ls180.v:7458$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [26] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7458$2401_Y + end + attribute \src "ls180.v:7459.21-7459.73" + cell $or $or$ls180.v:7459$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [27] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7459$2402_Y + end + attribute \src "ls180.v:7460.21-7460.73" + cell $or $or$ls180.v:7460$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [28] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7460$2403_Y + end + attribute \src "ls180.v:7461.21-7461.73" + cell $or $or$ls180.v:7461$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [29] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7461$2404_Y + end + attribute \src "ls180.v:7462.21-7462.73" + cell $or $or$ls180.v:7462$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [30] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7462$2405_Y + end + attribute \src "ls180.v:7463.21-7463.73" + cell $or $or$ls180.v:7463$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [31] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7463$2406_Y + end + attribute \src "ls180.v:7464.21-7464.73" + cell $or $or$ls180.v:7464$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [32] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7464$2407_Y + end + attribute \src "ls180.v:7465.21-7465.73" + cell $or $or$ls180.v:7465$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [33] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7465$2408_Y + end + attribute \src "ls180.v:7466.21-7466.73" + cell $or $or$ls180.v:7466$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [34] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7466$2409_Y + end + attribute \src "ls180.v:7467.21-7467.73" + cell $or $or$ls180.v:7467$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [35] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7467$2410_Y + end + attribute \src "ls180.v:7468.7-7468.93" + cell $or $or$ls180.v:7468$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$ls180.v:7468$2411_Y + end + attribute \src "ls180.v:7479.7-7479.93" + cell $or $or$ls180.v:7479$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$ls180.v:7479$2412_Y + end + attribute \src "ls180.v:7490.7-7490.93" + cell $or $or$ls180.v:7490$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface2_converted_interface_ack + connect \B \main_libresocsim_converter2_skip + connect \Y $or$ls180.v:7490$2413_Y + end + attribute \src "ls180.v:7619.7-7619.107" + cell $or $or$ls180.v:7619$2449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7619$2448_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7619$2449_Y + end + attribute \src "ls180.v:7665.7-7665.107" + cell $or $or$ls180.v:7665$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7665$2464_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7665$2465_Y + end + attribute \src "ls180.v:7711.7-7711.107" + cell $or $or$ls180.v:7711$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7711$2480_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7711$2481_Y + end + attribute \src "ls180.v:7757.7-7757.107" + cell $or $or$ls180.v:7757$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7757$2496_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:7757$2497_Y + end + attribute \src "ls180.v:7945.40-7945.125" + cell $or $or$ls180.v:7945$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7945$2517_Y + connect \Y $or$ls180.v:7945$2518_Y + end + attribute \src "ls180.v:7945.39-7945.207" + cell $or $or$ls180.v:7945$2521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7945$2518_Y + connect \B $and$ls180.v:7945$2520_Y + connect \Y $or$ls180.v:7945$2521_Y + end + attribute \src "ls180.v:7945.38-7945.289" + cell $or $or$ls180.v:7945$2524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7945$2521_Y + connect \B $and$ls180.v:7945$2523_Y + connect \Y $or$ls180.v:7945$2524_Y + end + attribute \src "ls180.v:7945.37-7945.371" + cell $or $or$ls180.v:7945$2527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7945$2524_Y + connect \B $and$ls180.v:7945$2526_Y + connect \Y $or$ls180.v:7945$2527_Y + end + attribute \src "ls180.v:7946.41-7946.126" + cell $or $or$ls180.v:7946$2530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:7946$2529_Y + connect \Y $or$ls180.v:7946$2530_Y + end + attribute \src "ls180.v:7946.40-7946.208" + cell $or $or$ls180.v:7946$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7946$2530_Y + connect \B $and$ls180.v:7946$2532_Y + connect \Y $or$ls180.v:7946$2533_Y + end + attribute \src "ls180.v:7946.39-7946.290" + cell $or $or$ls180.v:7946$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7946$2533_Y + connect \B $and$ls180.v:7946$2535_Y + connect \Y $or$ls180.v:7946$2536_Y + end + attribute \src "ls180.v:7946.38-7946.372" + cell $or $or$ls180.v:7946$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7946$2536_Y + connect \B $and$ls180.v:7946$2538_Y + connect \Y $or$ls180.v:7946$2539_Y + end + attribute \src "ls180.v:7950.7-7950.49" + cell $or $or$ls180.v:7950$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:7950$2540_Y + end + attribute \src "ls180.v:8113.21-8113.74" + cell $or $or$ls180.v:8113$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8113$2586_Y + connect \B $not$ls180.v:8113$2587_Y + connect \Y $or$ls180.v:8113$2588_Y + end + attribute \src "ls180.v:8148.21-8148.71" + cell $or $or$ls180.v:8148$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8148$2591_Y + connect \B $not$ls180.v:8148$2592_Y + connect \Y $or$ls180.v:8148$2593_Y + end + attribute \src "ls180.v:8216.32-8216.85" + cell $or $or$ls180.v:8216$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8216$2605_Y + end + attribute \src "ls180.v:8222.8-8222.97" + cell $or $or$ls180.v:8222$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8222$2606_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8222$2607_Y + end + attribute \src "ls180.v:8239.52-8239.139" + cell $or $or$ls180.v:8239$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8239$2612_Y + end + attribute \src "ls180.v:8240.51-8240.136" + cell $or $or$ls180.v:8240$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8240$2613_Y + end + attribute \src "ls180.v:8274.7-8274.87" + cell $or $or$ls180.v:8274$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8274$2615_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8274$2616_Y + end + attribute \src "ls180.v:8297.33-8297.88" + cell $or $or$ls180.v:8297$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8297$2617_Y + end + attribute \src "ls180.v:8303.8-8303.99" + cell $or $or$ls180.v:8303$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8303$2618_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8303$2619_Y + end + attribute \src "ls180.v:8320.53-8320.142" + cell $or $or$ls180.v:8320$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8320$2624_Y + end + attribute \src "ls180.v:8321.52-8321.139" + cell $or $or$ls180.v:8321$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8321$2625_Y + end + attribute \src "ls180.v:8355.7-8355.89" + cell $or $or$ls180.v:8355$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8355$2627_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8355$2628_Y + end + attribute \src "ls180.v:8376.34-8376.91" + cell $or $or$ls180.v:8376$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8376$2629_Y + end + attribute \src "ls180.v:8382.8-8382.101" + cell $or $or$ls180.v:8382$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8382$2630_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8382$2631_Y + end + attribute \src "ls180.v:8399.54-8399.145" + cell $or $or$ls180.v:8399$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8399$2636_Y + end + attribute \src "ls180.v:8400.53-8400.142" + cell $or $or$ls180.v:8400$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8400$2637_Y + end + attribute \src "ls180.v:8416.7-8416.91" + cell $or $or$ls180.v:8416$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8416$2639_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8416$2640_Y + end + attribute \src "ls180.v:8605.8-8605.89" + cell $or $or$ls180.v:8605$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8605$2663_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8605$2664_Y + end + attribute \src "ls180.v:8622.48-8622.127" + cell $or $or$ls180.v:8622$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8622$2669_Y + end + attribute \src "ls180.v:8623.47-8623.124" + cell $or $or$ls180.v:8623$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8623$2670_Y + end + attribute \src "ls180.v:3182.46-3182.94" + cell $sshl $sshl$ls180.v:3182$83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3182$83_Y + end + attribute \src "ls180.v:3339.46-3339.94" + cell $sshl $sshl$ls180.v:3339$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3339$113_Y + end + attribute \src "ls180.v:3496.46-3496.94" + cell $sshl $sshl$ls180.v:3496$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3496$143_Y + end + attribute \src "ls180.v:3653.46-3653.94" + cell $sshl $sshl$ls180.v:3653$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3653$173_Y + end + attribute \src "ls180.v:3213.63-3213.122" + cell $sub $sub$ls180.v:3213$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3213$96_Y + end + attribute \src "ls180.v:3370.63-3370.122" + cell $sub $sub$ls180.v:3370$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3370$126_Y + end + attribute \src "ls180.v:3527.63-3527.122" + cell $sub $sub$ls180.v:3527$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3527$156_Y + end + attribute \src "ls180.v:3684.63-3684.122" + cell $sub $sub$ls180.v:3684$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3684$186_Y + end + attribute \src "ls180.v:4090.38-4090.75" + cell $sub $sub$ls180.v:4090$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4090$540_Y + end + attribute \src "ls180.v:4176.36-4176.68" + cell $sub $sub$ls180.v:4176$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4176$585_Y + end + attribute \src "ls180.v:4206.36-4206.68" + cell $sub $sub$ls180.v:4206$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4206$596_Y + end + attribute \src "ls180.v:4231.70-4231.110" + cell $sub $sub$ls180.v:4231$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4231$602_Y + end + attribute \src "ls180.v:4232.70-4232.104" + cell $sub $sub$ls180.v:4232$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider + connect \B 1'1 + connect \Y $sub$ls180.v:4232$604_Y + end + attribute \src "ls180.v:4259.37-4259.66" + cell $sub $sub$ls180.v:4259$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spimaster1_length + connect \B 1'1 + connect \Y $sub$ls180.v:4259$608_Y + end + attribute \src "ls180.v:4289.67-4289.107" + cell $sub $sub$ls180.v:4289$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4289$610_Y + end + attribute \src "ls180.v:4290.67-4290.101" + cell $sub $sub$ls180.v:4290$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4290$612_Y + end + attribute \src "ls180.v:4318.35-4318.64" + cell $sub $sub$ls180.v:4318$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spisdcard_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4318$616_Y + end + attribute \src "ls180.v:4572.60-4572.90" + cell $sub $sub$ls180.v:4572$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4572$660_Y + end + attribute \src "ls180.v:4583.62-4583.104" + cell $sub $sub$ls180.v:4583$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4583$662_Y + end + attribute \src "ls180.v:4600.60-4600.90" + cell $sub $sub$ls180.v:4600$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4600$666_Y + end + attribute \src "ls180.v:4829.62-4829.93" + cell $sub $sub$ls180.v:4829$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4829$696_Y + end + attribute \src "ls180.v:4834.62-4834.93" + cell $sub $sub$ls180.v:4834$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4834$697_Y + end + attribute \src "ls180.v:4845.64-4845.122" + cell $sub $sub$ls180.v:4845$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:4845$699_Y + connect \B 1'1 + connect \Y $sub$ls180.v:4845$700_Y + end + attribute \src "ls180.v:4866.62-4866.93" + cell $sub $sub$ls180.v:4866$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4866$703_Y + end + attribute \src "ls180.v:5328.37-5328.75" + cell $sub $sub$ls180.v:5328$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5328$976_Y + end + attribute \src "ls180.v:5343.62-5343.100" + cell $sub $sub$ls180.v:5343$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5343$979_Y + end + attribute \src "ls180.v:5354.39-5354.77" + cell $sub $sub$ls180.v:5354$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5354$984_Y + end + attribute \src "ls180.v:5429.40-5429.76" + cell $sub $sub$ls180.v:5429$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5429$988_Y + end + attribute \src "ls180.v:5478.56-5478.104" + cell $sub $sub$ls180.v:5478$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5478$1002_Y + end + attribute \src "ls180.v:5568.71-5568.105" + cell $sub $sub$ls180.v:5568$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5568$1008_Y + end + attribute \src "ls180.v:5637.40-5637.76" + cell $sub $sub$ls180.v:5637$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5637$1019_Y + end + attribute \src "ls180.v:7514.31-7514.60" + cell $sub $sub$ls180.v:7514$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7514$2420_Y + end + attribute \src "ls180.v:7535.31-7535.61" + cell $sub $sub$ls180.v:7535$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7535$2425_Y + end + attribute \src "ls180.v:7541.34-7541.67" + cell $sub $sub$ls180.v:7541$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7541$2426_Y + end + attribute \src "ls180.v:7552.36-7552.69" + cell $sub $sub$ls180.v:7552$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7552$2429_Y + end + attribute \src "ls180.v:7616.59-7616.116" + cell $sub $sub$ls180.v:7616$2447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7616$2447_Y + end + attribute \src "ls180.v:7635.46-7635.90" + cell $sub $sub$ls180.v:7635$2451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7635$2451_Y + end + attribute \src "ls180.v:7662.59-7662.116" + cell $sub $sub$ls180.v:7662$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7662$2463_Y + end + attribute \src "ls180.v:7681.46-7681.90" + cell $sub $sub$ls180.v:7681$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7681$2467_Y + end + attribute \src "ls180.v:7708.59-7708.116" + cell $sub $sub$ls180.v:7708$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7708$2479_Y + end + attribute \src "ls180.v:7727.46-7727.90" + cell $sub $sub$ls180.v:7727$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7727$2483_Y + end + attribute \src "ls180.v:7754.59-7754.116" + cell $sub $sub$ls180.v:7754$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7754$2495_Y + end + attribute \src "ls180.v:7773.46-7773.90" + cell $sub $sub$ls180.v:7773$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7773$2499_Y + end + attribute \src "ls180.v:7784.25-7784.48" + cell $sub $sub$ls180.v:7784$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:7784$2503_Y + end + attribute \src "ls180.v:7791.25-7791.48" + cell $sub $sub$ls180.v:7791$2506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:7791$2506_Y + end + attribute \src "ls180.v:7923.33-7923.64" + cell $sub $sub$ls180.v:7923$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7923$2511_Y + end + attribute \src "ls180.v:7938.33-7938.64" + cell $sub $sub$ls180.v:7938$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7938$2514_Y + end + attribute \src "ls180.v:8065.33-8065.64" + cell $sub $sub$ls180.v:8065$2573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8065$2573_Y + end + attribute \src "ls180.v:8087.33-8087.64" + cell $sub $sub$ls180.v:8087$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8087$2584_Y + end + attribute \src "ls180.v:8122.34-8122.66" + cell $sub $sub$ls180.v:8122$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster34_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8122$2589_Y + end + attribute \src "ls180.v:8157.32-8157.62" + cell $sub $sub$ls180.v:8157$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8157$2594_Y + end + attribute \src "ls180.v:8181.30-8181.53" + cell $sub $sub$ls180.v:8181$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8181$2597_Y + end + attribute \src "ls180.v:8195.30-8195.53" + cell $sub $sub$ls180.v:8195$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8195$2601_Y + end + attribute \src "ls180.v:8598.36-8598.70" + cell $sub $sub$ls180.v:8598$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8598$2662_Y + end + attribute \src "ls180.v:8684.36-8684.70" + cell $sub $sub$ls180.v:8684$2684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8684$2684_Y + end + attribute \src "ls180.v:8797.22-8797.42" + cell $sub $sub$ls180.v:8797$2691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:8797$2691_Y + end + attribute \src "ls180.v:4926.353-4926.425" + cell $xor $xor$ls180.v:4926$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4926$710_Y + end + attribute \src "ls180.v:4926.200-4926.272" + cell $xor $xor$ls180.v:4926$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:4926$711_Y + end + attribute \src "ls180.v:4926.160-4926.273" + cell $xor $xor$ls180.v:4926$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:4926$711_Y + connect \Y $xor$ls180.v:4926$712_Y + end + attribute \src "ls180.v:4927.353-4927.425" + cell $xor $xor$ls180.v:4927$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4927$713_Y + end + attribute \src "ls180.v:4927.200-4927.272" + cell $xor $xor$ls180.v:4927$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:4927$714_Y + end + attribute \src "ls180.v:4927.160-4927.273" + cell $xor $xor$ls180.v:4927$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:4927$714_Y + connect \Y $xor$ls180.v:4927$715_Y + end + attribute \src "ls180.v:4928.353-4928.425" + cell $xor $xor$ls180.v:4928$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4928$716_Y + end + attribute \src "ls180.v:4928.200-4928.272" + cell $xor $xor$ls180.v:4928$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:4928$717_Y + end + attribute \src "ls180.v:4928.160-4928.273" + cell $xor $xor$ls180.v:4928$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:4928$717_Y + connect \Y $xor$ls180.v:4928$718_Y + end + attribute \src "ls180.v:4929.353-4929.425" + cell $xor $xor$ls180.v:4929$719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4929$719_Y + end + attribute \src "ls180.v:4929.200-4929.272" + cell $xor $xor$ls180.v:4929$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:4929$720_Y + end + attribute \src "ls180.v:4929.160-4929.273" + cell $xor $xor$ls180.v:4929$721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:4929$720_Y + connect \Y $xor$ls180.v:4929$721_Y + end + attribute \src "ls180.v:4930.353-4930.425" + cell $xor $xor$ls180.v:4930$722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4930$722_Y + end + attribute \src "ls180.v:4930.200-4930.272" + cell $xor $xor$ls180.v:4930$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:4930$723_Y + end + attribute \src "ls180.v:4930.160-4930.273" + cell $xor $xor$ls180.v:4930$724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:4930$723_Y + connect \Y $xor$ls180.v:4930$724_Y + end + attribute \src "ls180.v:4931.353-4931.425" + cell $xor $xor$ls180.v:4931$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4931$725_Y + end + attribute \src "ls180.v:4931.200-4931.272" + cell $xor $xor$ls180.v:4931$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:4931$726_Y + end + attribute \src "ls180.v:4931.160-4931.273" + cell $xor $xor$ls180.v:4931$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:4931$726_Y + connect \Y $xor$ls180.v:4931$727_Y + end + attribute \src "ls180.v:4932.353-4932.425" + cell $xor $xor$ls180.v:4932$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4932$728_Y + end + attribute \src "ls180.v:4932.200-4932.272" + cell $xor $xor$ls180.v:4932$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:4932$729_Y + end + attribute \src "ls180.v:4932.160-4932.273" + cell $xor $xor$ls180.v:4932$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:4932$729_Y + connect \Y $xor$ls180.v:4932$730_Y + end + attribute \src "ls180.v:4933.353-4933.425" + cell $xor $xor$ls180.v:4933$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4933$731_Y + end + attribute \src "ls180.v:4933.200-4933.272" + cell $xor $xor$ls180.v:4933$732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:4933$732_Y + end + attribute \src "ls180.v:4933.160-4933.273" + cell $xor $xor$ls180.v:4933$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:4933$732_Y + connect \Y $xor$ls180.v:4933$733_Y + end + attribute \src "ls180.v:4934.353-4934.425" + cell $xor $xor$ls180.v:4934$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4934$734_Y + end + attribute \src "ls180.v:4934.200-4934.272" + cell $xor $xor$ls180.v:4934$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:4934$735_Y + end + attribute \src "ls180.v:4934.160-4934.273" + cell $xor $xor$ls180.v:4934$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:4934$735_Y + connect \Y $xor$ls180.v:4934$736_Y + end + attribute \src "ls180.v:4935.354-4935.426" + cell $xor $xor$ls180.v:4935$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4935$737_Y + end + attribute \src "ls180.v:4935.201-4935.273" + cell $xor $xor$ls180.v:4935$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:4935$738_Y + end + attribute \src "ls180.v:4935.161-4935.274" + cell $xor $xor$ls180.v:4935$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:4935$738_Y + connect \Y $xor$ls180.v:4935$739_Y + end + attribute \src "ls180.v:4936.361-4936.434" + cell $xor $xor$ls180.v:4936$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4936$740_Y + end + attribute \src "ls180.v:4936.205-4936.278" + cell $xor $xor$ls180.v:4936$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:4936$741_Y + end + attribute \src "ls180.v:4936.164-4936.279" + cell $xor $xor$ls180.v:4936$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:4936$741_Y + connect \Y $xor$ls180.v:4936$742_Y + end + attribute \src "ls180.v:4937.361-4937.434" + cell $xor $xor$ls180.v:4937$743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4937$743_Y + end + attribute \src "ls180.v:4937.205-4937.278" + cell $xor $xor$ls180.v:4937$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:4937$744_Y + end + attribute \src "ls180.v:4937.164-4937.279" + cell $xor $xor$ls180.v:4937$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:4937$744_Y + connect \Y $xor$ls180.v:4937$745_Y + end + attribute \src "ls180.v:4938.361-4938.434" + cell $xor $xor$ls180.v:4938$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4938$746_Y + end + attribute \src "ls180.v:4938.205-4938.278" + cell $xor $xor$ls180.v:4938$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:4938$747_Y + end + attribute \src "ls180.v:4938.164-4938.279" + cell $xor $xor$ls180.v:4938$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:4938$747_Y + connect \Y $xor$ls180.v:4938$748_Y + end + attribute \src "ls180.v:4939.361-4939.434" + cell $xor $xor$ls180.v:4939$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4939$749_Y + end + attribute \src "ls180.v:4939.205-4939.278" + cell $xor $xor$ls180.v:4939$750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:4939$750_Y + end + attribute \src "ls180.v:4939.164-4939.279" + cell $xor $xor$ls180.v:4939$751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:4939$750_Y + connect \Y $xor$ls180.v:4939$751_Y + end + attribute \src "ls180.v:4940.361-4940.434" + cell $xor $xor$ls180.v:4940$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4940$752_Y + end + attribute \src "ls180.v:4940.205-4940.278" + cell $xor $xor$ls180.v:4940$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:4940$753_Y + end + attribute \src "ls180.v:4940.164-4940.279" + cell $xor $xor$ls180.v:4940$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:4940$753_Y + connect \Y $xor$ls180.v:4940$754_Y + end + attribute \src "ls180.v:4941.361-4941.434" + cell $xor $xor$ls180.v:4941$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4941$755_Y + end + attribute \src "ls180.v:4941.205-4941.278" + cell $xor $xor$ls180.v:4941$756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:4941$756_Y + end + attribute \src "ls180.v:4941.164-4941.279" + cell $xor $xor$ls180.v:4941$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:4941$756_Y + connect \Y $xor$ls180.v:4941$757_Y + end + attribute \src "ls180.v:4942.361-4942.434" + cell $xor $xor$ls180.v:4942$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4942$758_Y + end + attribute \src "ls180.v:4942.205-4942.278" + cell $xor $xor$ls180.v:4942$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:4942$759_Y + end + attribute \src "ls180.v:4942.164-4942.279" + cell $xor $xor$ls180.v:4942$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:4942$759_Y + connect \Y $xor$ls180.v:4942$760_Y + end + attribute \src "ls180.v:4943.361-4943.434" + cell $xor $xor$ls180.v:4943$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4943$761_Y + end + attribute \src "ls180.v:4943.205-4943.278" + cell $xor $xor$ls180.v:4943$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:4943$762_Y + end + attribute \src "ls180.v:4943.164-4943.279" + cell $xor $xor$ls180.v:4943$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:4943$762_Y + connect \Y $xor$ls180.v:4943$763_Y + end + attribute \src "ls180.v:4944.361-4944.434" + cell $xor $xor$ls180.v:4944$764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4944$764_Y + end + attribute \src "ls180.v:4944.205-4944.278" + cell $xor $xor$ls180.v:4944$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:4944$765_Y + end + attribute \src "ls180.v:4944.164-4944.279" + cell $xor $xor$ls180.v:4944$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:4944$765_Y + connect \Y $xor$ls180.v:4944$766_Y + end + attribute \src "ls180.v:4945.361-4945.434" + cell $xor $xor$ls180.v:4945$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4945$767_Y + end + attribute \src "ls180.v:4945.205-4945.278" + cell $xor $xor$ls180.v:4945$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:4945$768_Y + end + attribute \src "ls180.v:4945.164-4945.279" + cell $xor $xor$ls180.v:4945$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:4945$768_Y + connect \Y $xor$ls180.v:4945$769_Y + end + attribute \src "ls180.v:4946.361-4946.434" + cell $xor $xor$ls180.v:4946$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4946$770_Y + end + attribute \src "ls180.v:4946.205-4946.278" + cell $xor $xor$ls180.v:4946$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:4946$771_Y + end + attribute \src "ls180.v:4946.164-4946.279" + cell $xor $xor$ls180.v:4946$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:4946$771_Y + connect \Y $xor$ls180.v:4946$772_Y + end + attribute \src "ls180.v:4947.361-4947.434" + cell $xor $xor$ls180.v:4947$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4947$773_Y + end + attribute \src "ls180.v:4947.205-4947.278" + cell $xor $xor$ls180.v:4947$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:4947$774_Y + end + attribute \src "ls180.v:4947.164-4947.279" + cell $xor $xor$ls180.v:4947$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:4947$774_Y + connect \Y $xor$ls180.v:4947$775_Y + end + attribute \src "ls180.v:4948.361-4948.434" + cell $xor $xor$ls180.v:4948$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4948$776_Y + end + attribute \src "ls180.v:4948.205-4948.278" + cell $xor $xor$ls180.v:4948$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:4948$777_Y + end + attribute \src "ls180.v:4948.164-4948.279" + cell $xor $xor$ls180.v:4948$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:4948$777_Y + connect \Y $xor$ls180.v:4948$778_Y + end + attribute \src "ls180.v:4949.361-4949.434" + cell $xor $xor$ls180.v:4949$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4949$779_Y + end + attribute \src "ls180.v:4949.205-4949.278" + cell $xor $xor$ls180.v:4949$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:4949$780_Y + end + attribute \src "ls180.v:4949.164-4949.279" + cell $xor $xor$ls180.v:4949$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:4949$780_Y + connect \Y $xor$ls180.v:4949$781_Y + end + attribute \src "ls180.v:4950.361-4950.434" + cell $xor $xor$ls180.v:4950$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4950$782_Y + end + attribute \src "ls180.v:4950.205-4950.278" + cell $xor $xor$ls180.v:4950$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:4950$783_Y + end + attribute \src "ls180.v:4950.164-4950.279" + cell $xor $xor$ls180.v:4950$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:4950$783_Y + connect \Y $xor$ls180.v:4950$784_Y + end + attribute \src "ls180.v:4951.361-4951.434" + cell $xor $xor$ls180.v:4951$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4951$785_Y + end + attribute \src "ls180.v:4951.205-4951.278" + cell $xor $xor$ls180.v:4951$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:4951$786_Y + end + attribute \src "ls180.v:4951.164-4951.279" + cell $xor $xor$ls180.v:4951$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:4951$786_Y + connect \Y $xor$ls180.v:4951$787_Y + end + attribute \src "ls180.v:4952.361-4952.434" + cell $xor $xor$ls180.v:4952$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4952$788_Y + end + attribute \src "ls180.v:4952.205-4952.278" + cell $xor $xor$ls180.v:4952$789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:4952$789_Y + end + attribute \src "ls180.v:4952.164-4952.279" + cell $xor $xor$ls180.v:4952$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:4952$789_Y + connect \Y $xor$ls180.v:4952$790_Y + end + attribute \src "ls180.v:4953.361-4953.434" + cell $xor $xor$ls180.v:4953$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4953$791_Y + end + attribute \src "ls180.v:4953.205-4953.278" + cell $xor $xor$ls180.v:4953$792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:4953$792_Y + end + attribute \src "ls180.v:4953.164-4953.279" + cell $xor $xor$ls180.v:4953$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:4953$792_Y + connect \Y $xor$ls180.v:4953$793_Y + end + attribute \src "ls180.v:4954.361-4954.434" + cell $xor $xor$ls180.v:4954$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4954$794_Y + end + attribute \src "ls180.v:4954.205-4954.278" + cell $xor $xor$ls180.v:4954$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:4954$795_Y + end + attribute \src "ls180.v:4954.164-4954.279" + cell $xor $xor$ls180.v:4954$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:4954$795_Y + connect \Y $xor$ls180.v:4954$796_Y + end + attribute \src "ls180.v:4955.361-4955.434" + cell $xor $xor$ls180.v:4955$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4955$797_Y + end + attribute \src "ls180.v:4955.205-4955.278" + cell $xor $xor$ls180.v:4955$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:4955$798_Y + end + attribute \src "ls180.v:4955.164-4955.279" + cell $xor $xor$ls180.v:4955$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:4955$798_Y + connect \Y $xor$ls180.v:4955$799_Y + end + attribute \src "ls180.v:4956.360-4956.432" + cell $xor $xor$ls180.v:4956$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4956$800_Y + end + attribute \src "ls180.v:4956.205-4956.277" + cell $xor $xor$ls180.v:4956$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:4956$801_Y + end + attribute \src "ls180.v:4956.164-4956.278" + cell $xor $xor$ls180.v:4956$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:4956$801_Y + connect \Y $xor$ls180.v:4956$802_Y + end + attribute \src "ls180.v:4957.360-4957.432" + cell $xor $xor$ls180.v:4957$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4957$803_Y + end + attribute \src "ls180.v:4957.205-4957.277" + cell $xor $xor$ls180.v:4957$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:4957$804_Y + end + attribute \src "ls180.v:4957.164-4957.278" + cell $xor $xor$ls180.v:4957$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:4957$804_Y + connect \Y $xor$ls180.v:4957$805_Y + end + attribute \src "ls180.v:4958.360-4958.432" + cell $xor $xor$ls180.v:4958$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4958$806_Y + end + attribute \src "ls180.v:4958.205-4958.277" + cell $xor $xor$ls180.v:4958$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:4958$807_Y + end + attribute \src "ls180.v:4958.164-4958.278" + cell $xor $xor$ls180.v:4958$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:4958$807_Y + connect \Y $xor$ls180.v:4958$808_Y + end + attribute \src "ls180.v:4959.360-4959.432" + cell $xor $xor$ls180.v:4959$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4959$809_Y + end + attribute \src "ls180.v:4959.205-4959.277" + cell $xor $xor$ls180.v:4959$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:4959$810_Y + end + attribute \src "ls180.v:4959.164-4959.278" + cell $xor $xor$ls180.v:4959$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:4959$810_Y + connect \Y $xor$ls180.v:4959$811_Y + end + attribute \src "ls180.v:4960.360-4960.432" + cell $xor $xor$ls180.v:4960$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4960$812_Y + end + attribute \src "ls180.v:4960.205-4960.277" + cell $xor $xor$ls180.v:4960$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:4960$813_Y + end + attribute \src "ls180.v:4960.164-4960.278" + cell $xor $xor$ls180.v:4960$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:4960$813_Y + connect \Y $xor$ls180.v:4960$814_Y + end + attribute \src "ls180.v:4961.360-4961.432" + cell $xor $xor$ls180.v:4961$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4961$815_Y + end + attribute \src "ls180.v:4961.205-4961.277" + cell $xor $xor$ls180.v:4961$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:4961$816_Y + end + attribute \src "ls180.v:4961.164-4961.278" + cell $xor $xor$ls180.v:4961$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:4961$816_Y + connect \Y $xor$ls180.v:4961$817_Y + end + attribute \src "ls180.v:4962.360-4962.432" + cell $xor $xor$ls180.v:4962$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4962$818_Y + end + attribute \src "ls180.v:4962.205-4962.277" + cell $xor $xor$ls180.v:4962$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:4962$819_Y + end + attribute \src "ls180.v:4962.164-4962.278" + cell $xor $xor$ls180.v:4962$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:4962$819_Y + connect \Y $xor$ls180.v:4962$820_Y + end + attribute \src "ls180.v:4963.360-4963.432" + cell $xor $xor$ls180.v:4963$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4963$821_Y + end + attribute \src "ls180.v:4963.205-4963.277" + cell $xor $xor$ls180.v:4963$822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:4963$822_Y + end + attribute \src "ls180.v:4963.164-4963.278" + cell $xor $xor$ls180.v:4963$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:4963$822_Y + connect \Y $xor$ls180.v:4963$823_Y + end + attribute \src "ls180.v:4964.360-4964.432" + cell $xor $xor$ls180.v:4964$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4964$824_Y + end + attribute \src "ls180.v:4964.205-4964.277" + cell $xor $xor$ls180.v:4964$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:4964$825_Y + end + attribute \src "ls180.v:4964.164-4964.278" + cell $xor $xor$ls180.v:4964$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:4964$825_Y + connect \Y $xor$ls180.v:4964$826_Y + end + attribute \src "ls180.v:4965.360-4965.432" + cell $xor $xor$ls180.v:4965$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4965$827_Y + end + attribute \src "ls180.v:4965.205-4965.277" + cell $xor $xor$ls180.v:4965$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:4965$828_Y + end + attribute \src "ls180.v:4965.164-4965.278" + cell $xor $xor$ls180.v:4965$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:4965$828_Y + connect \Y $xor$ls180.v:4965$829_Y + end + attribute \src "ls180.v:4986.899-4986.983" + cell $xor $xor$ls180.v:4986$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4986$843_Y + end + attribute \src "ls180.v:4986.634-4986.718" + cell $xor $xor$ls180.v:4986$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4986$844_Y + end + attribute \src "ls180.v:4986.588-4986.719" + cell $xor $xor$ls180.v:4986$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:4986$844_Y + connect \Y $xor$ls180.v:4986$845_Y + end + attribute \src "ls180.v:4986.234-4986.318" + cell $xor $xor$ls180.v:4986$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:4986$846_Y + end + attribute \src "ls180.v:4986.187-4986.319" + cell $xor $xor$ls180.v:4986$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:4986$846_Y + connect \Y $xor$ls180.v:4986$847_Y + end + attribute \src "ls180.v:4987.899-4987.983" + cell $xor $xor$ls180.v:4987$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4987$848_Y + end + attribute \src "ls180.v:4987.634-4987.718" + cell $xor $xor$ls180.v:4987$849 parameter \A_SIGNED 0 - parameter \A_WIDTH 64 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o - connect \B 1'1 - connect \Y $add$libresoc.v:185113$13283_Y + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4987$849_Y + end + attribute \src "ls180.v:4987.588-4987.719" + cell $xor $xor$ls180.v:4987$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:4987$849_Y + connect \Y $xor$ls180.v:4987$850_Y + end + attribute \src "ls180.v:4987.234-4987.318" + cell $xor $xor$ls180.v:4987$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:4987$851_Y + end + attribute \src "ls180.v:4987.187-4987.319" + cell $xor $xor$ls180.v:4987$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:4987$851_Y + connect \Y $xor$ls180.v:4987$852_Y + end + attribute \src "ls180.v:4996.899-4996.983" + cell $xor $xor$ls180.v:4996$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4996$854_Y + end + attribute \src "ls180.v:4996.634-4996.718" + cell $xor $xor$ls180.v:4996$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4996$855_Y + end + attribute \src "ls180.v:4996.588-4996.719" + cell $xor $xor$ls180.v:4996$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:4996$855_Y + connect \Y $xor$ls180.v:4996$856_Y + end + attribute \src "ls180.v:4996.234-4996.318" + cell $xor $xor$ls180.v:4996$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:4996$857_Y + end + attribute \src "ls180.v:4996.187-4996.319" + cell $xor $xor$ls180.v:4996$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:4996$857_Y + connect \Y $xor$ls180.v:4996$858_Y + end + attribute \src "ls180.v:4997.899-4997.983" + cell $xor $xor$ls180.v:4997$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4997$859_Y + end + attribute \src "ls180.v:4997.634-4997.718" + cell $xor $xor$ls180.v:4997$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4997$860_Y + end + attribute \src "ls180.v:4997.588-4997.719" + cell $xor $xor$ls180.v:4997$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:4997$860_Y + connect \Y $xor$ls180.v:4997$861_Y + end + attribute \src "ls180.v:4997.234-4997.318" + cell $xor $xor$ls180.v:4997$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:4997$862_Y + end + attribute \src "ls180.v:4997.187-4997.319" + cell $xor $xor$ls180.v:4997$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:4997$862_Y + connect \Y $xor$ls180.v:4997$863_Y + end + attribute \src "ls180.v:5006.899-5006.983" + cell $xor $xor$ls180.v:5006$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5006$865_Y + end + attribute \src "ls180.v:5006.634-5006.718" + cell $xor $xor$ls180.v:5006$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5006$866_Y + end + attribute \src "ls180.v:5006.588-5006.719" + cell $xor $xor$ls180.v:5006$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5006$866_Y + connect \Y $xor$ls180.v:5006$867_Y + end + attribute \src "ls180.v:5006.234-5006.318" + cell $xor $xor$ls180.v:5006$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5006$868_Y + end + attribute \src "ls180.v:5006.187-5006.319" + cell $xor $xor$ls180.v:5006$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5006$868_Y + connect \Y $xor$ls180.v:5006$869_Y + end + attribute \src "ls180.v:5007.899-5007.983" + cell $xor $xor$ls180.v:5007$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5007$870_Y + end + attribute \src "ls180.v:5007.634-5007.718" + cell $xor $xor$ls180.v:5007$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5007$871_Y + end + attribute \src "ls180.v:5007.588-5007.719" + cell $xor $xor$ls180.v:5007$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5007$871_Y + connect \Y $xor$ls180.v:5007$872_Y + end + attribute \src "ls180.v:5007.234-5007.318" + cell $xor $xor$ls180.v:5007$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5007$873_Y + end + attribute \src "ls180.v:5007.187-5007.319" + cell $xor $xor$ls180.v:5007$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5007$873_Y + connect \Y $xor$ls180.v:5007$874_Y + end + attribute \src "ls180.v:5016.899-5016.983" + cell $xor $xor$ls180.v:5016$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5016$876_Y + end + attribute \src "ls180.v:5016.634-5016.718" + cell $xor $xor$ls180.v:5016$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5016$877_Y + end + attribute \src "ls180.v:5016.588-5016.719" + cell $xor $xor$ls180.v:5016$878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5016$877_Y + connect \Y $xor$ls180.v:5016$878_Y + end + attribute \src "ls180.v:5016.234-5016.318" + cell $xor $xor$ls180.v:5016$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5016$879_Y + end + attribute \src "ls180.v:5016.187-5016.319" + cell $xor $xor$ls180.v:5016$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5016$879_Y + connect \Y $xor$ls180.v:5016$880_Y + end + attribute \src "ls180.v:5017.899-5017.983" + cell $xor $xor$ls180.v:5017$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5017$881_Y + end + attribute \src "ls180.v:5017.634-5017.718" + cell $xor $xor$ls180.v:5017$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5017$882_Y + end + attribute \src "ls180.v:5017.588-5017.719" + cell $xor $xor$ls180.v:5017$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5017$882_Y + connect \Y $xor$ls180.v:5017$883_Y + end + attribute \src "ls180.v:5017.234-5017.318" + cell $xor $xor$ls180.v:5017$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5017$884_Y + end + attribute \src "ls180.v:5017.187-5017.319" + cell $xor $xor$ls180.v:5017$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5017$884_Y + connect \Y $xor$ls180.v:5017$885_Y + end + attribute \src "ls180.v:5168.879-5168.961" + cell $xor $xor$ls180.v:5168$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5168$918_Y + end + attribute \src "ls180.v:5168.620-5168.702" + cell $xor $xor$ls180.v:5168$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5168$919_Y + end + attribute \src "ls180.v:5168.575-5168.703" + cell $xor $xor$ls180.v:5168$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5168$919_Y + connect \Y $xor$ls180.v:5168$920_Y + end + attribute \src "ls180.v:5168.229-5168.311" + cell $xor $xor$ls180.v:5168$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5168$921_Y + end + attribute \src "ls180.v:5168.183-5168.312" + cell $xor $xor$ls180.v:5168$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5168$921_Y + connect \Y $xor$ls180.v:5168$922_Y + end + attribute \src "ls180.v:5169.879-5169.961" + cell $xor $xor$ls180.v:5169$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5169$923_Y + end + attribute \src "ls180.v:5169.620-5169.702" + cell $xor $xor$ls180.v:5169$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5169$924_Y + end + attribute \src "ls180.v:5169.575-5169.703" + cell $xor $xor$ls180.v:5169$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5169$924_Y + connect \Y $xor$ls180.v:5169$925_Y + end + attribute \src "ls180.v:5169.229-5169.311" + cell $xor $xor$ls180.v:5169$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5169$926_Y + end + attribute \src "ls180.v:5169.183-5169.312" + cell $xor $xor$ls180.v:5169$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5169$926_Y + connect \Y $xor$ls180.v:5169$927_Y + end + attribute \src "ls180.v:5178.879-5178.961" + cell $xor $xor$ls180.v:5178$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5178$929_Y + end + attribute \src "ls180.v:5178.620-5178.702" + cell $xor $xor$ls180.v:5178$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5178$930_Y + end + attribute \src "ls180.v:5178.575-5178.703" + cell $xor $xor$ls180.v:5178$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5178$930_Y + connect \Y $xor$ls180.v:5178$931_Y + end + attribute \src "ls180.v:5178.229-5178.311" + cell $xor $xor$ls180.v:5178$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5178$932_Y + end + attribute \src "ls180.v:5178.183-5178.312" + cell $xor $xor$ls180.v:5178$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5178$932_Y + connect \Y $xor$ls180.v:5178$933_Y + end + attribute \src "ls180.v:5179.879-5179.961" + cell $xor $xor$ls180.v:5179$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5179$934_Y + end + attribute \src "ls180.v:5179.620-5179.702" + cell $xor $xor$ls180.v:5179$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5179$935_Y + end + attribute \src "ls180.v:5179.575-5179.703" + cell $xor $xor$ls180.v:5179$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5179$935_Y + connect \Y $xor$ls180.v:5179$936_Y + end + attribute \src "ls180.v:5179.229-5179.311" + cell $xor $xor$ls180.v:5179$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5179$937_Y + end + attribute \src "ls180.v:5179.183-5179.312" + cell $xor $xor$ls180.v:5179$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5179$937_Y + connect \Y $xor$ls180.v:5179$938_Y + end + attribute \src "ls180.v:5188.879-5188.961" + cell $xor $xor$ls180.v:5188$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5188$940_Y + end + attribute \src "ls180.v:5188.620-5188.702" + cell $xor $xor$ls180.v:5188$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5188$941_Y + end + attribute \src "ls180.v:5188.575-5188.703" + cell $xor $xor$ls180.v:5188$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5188$941_Y + connect \Y $xor$ls180.v:5188$942_Y + end + attribute \src "ls180.v:5188.229-5188.311" + cell $xor $xor$ls180.v:5188$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5188$943_Y + end + attribute \src "ls180.v:5188.183-5188.312" + cell $xor $xor$ls180.v:5188$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5188$943_Y + connect \Y $xor$ls180.v:5188$944_Y + end + attribute \src "ls180.v:5189.879-5189.961" + cell $xor $xor$ls180.v:5189$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5189$945_Y + end + attribute \src "ls180.v:5189.620-5189.702" + cell $xor $xor$ls180.v:5189$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5189$946_Y + end + attribute \src "ls180.v:5189.575-5189.703" + cell $xor $xor$ls180.v:5189$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5189$946_Y + connect \Y $xor$ls180.v:5189$947_Y + end + attribute \src "ls180.v:5189.229-5189.311" + cell $xor $xor$ls180.v:5189$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5189$948_Y + end + attribute \src "ls180.v:5189.183-5189.312" + cell $xor $xor$ls180.v:5189$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5189$948_Y + connect \Y $xor$ls180.v:5189$949_Y + end + attribute \src "ls180.v:5198.879-5198.961" + cell $xor $xor$ls180.v:5198$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5198$951_Y + end + attribute \src "ls180.v:5198.620-5198.702" + cell $xor $xor$ls180.v:5198$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5198$952_Y + end + attribute \src "ls180.v:5198.575-5198.703" + cell $xor $xor$ls180.v:5198$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5198$952_Y + connect \Y $xor$ls180.v:5198$953_Y + end + attribute \src "ls180.v:5198.229-5198.311" + cell $xor $xor$ls180.v:5198$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5198$954_Y + end + attribute \src "ls180.v:5198.183-5198.312" + cell $xor $xor$ls180.v:5198$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5198$954_Y + connect \Y $xor$ls180.v:5198$955_Y + end + attribute \src "ls180.v:5199.879-5199.961" + cell $xor $xor$ls180.v:5199$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5199$956_Y + end + attribute \src "ls180.v:5199.620-5199.702" + cell $xor $xor$ls180.v:5199$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5199$957_Y + end + attribute \src "ls180.v:5199.575-5199.703" + cell $xor $xor$ls180.v:5199$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5199$957_Y + connect \Y $xor$ls180.v:5199$958_Y + end + attribute \src "ls180.v:5199.229-5199.311" + cell $xor $xor$ls180.v:5199$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5199$959_Y + end + attribute \src "ls180.v:5199.183-5199.312" + cell $xor $xor$ls180.v:5199$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5199$959_Y + connect \Y $xor$ls180.v:5199$960_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10195.13-10573.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \main_libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte \main_libresocsim_libresoc_dbus_bte + connect \dbus__cti \main_libresocsim_libresoc_dbus_cti + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \eint_0__core__i \eint [0] + connect \eint_0__pad__i \eint_1 [0] + connect \eint_1__core__i \eint [1] + connect \eint_1__pad__i \eint_1 [1] + connect \eint_2__core__i \eint [2] + connect \eint_2__pad__i \eint_1 [2] + connect \gpio_e10__core__i \gpio_i [10] + connect \gpio_e10__core__o \gpio_o [10] + connect \gpio_e10__core__oe \gpio_oe [10] + connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] + connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] + connect \gpio_e11__core__i \gpio_i [11] + connect \gpio_e11__core__o \gpio_o [11] + connect \gpio_e11__core__oe \gpio_oe [11] + connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] + connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] + connect \gpio_e12__core__i \gpio_i [12] + connect \gpio_e12__core__o \gpio_o [12] + connect \gpio_e12__core__oe \gpio_oe [12] + connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] + connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] + connect \gpio_e13__core__i \gpio_i [13] + connect \gpio_e13__core__o \gpio_o [13] + connect \gpio_e13__core__oe \gpio_oe [13] + connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] + connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] + connect \gpio_e14__core__i \gpio_i [14] + connect \gpio_e14__core__o \gpio_o [14] + connect \gpio_e14__core__oe \gpio_oe [14] + connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] + connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] + connect \gpio_e15__core__i \gpio_i [15] + connect \gpio_e15__core__o \gpio_o [15] + connect \gpio_e15__core__oe \gpio_oe [15] + connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] + connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] + connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] + connect \gpio_e8__core__i \gpio_i [8] + connect \gpio_e8__core__o \gpio_o [8] + connect \gpio_e8__core__oe \gpio_oe [8] + connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] + connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] + connect \gpio_e9__core__i \gpio_i [9] + connect \gpio_e9__core__o \gpio_o [9] + connect \gpio_e9__core__oe \gpio_oe [9] + connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] + connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] + connect \gpio_s0__core__i \gpio_i [0] + connect \gpio_s0__core__o \gpio_o [0] + connect \gpio_s0__core__oe \gpio_oe [0] + connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] + connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] + connect \gpio_s1__core__i \gpio_i [1] + connect \gpio_s1__core__o \gpio_o [1] + connect \gpio_s1__core__oe \gpio_oe [1] + connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] + connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] + connect \gpio_s2__core__i \gpio_i [2] + connect \gpio_s2__core__o \gpio_o [2] + connect \gpio_s2__core__oe \gpio_oe [2] + connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] + connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] + connect \gpio_s3__core__i \gpio_i [3] + connect \gpio_s3__core__o \gpio_o [3] + connect \gpio_s3__core__oe \gpio_oe [3] + connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] + connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] + connect \gpio_s4__core__i \gpio_i [4] + connect \gpio_s4__core__o \gpio_o [4] + connect \gpio_s4__core__oe \gpio_oe [4] + connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] + connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] + connect \gpio_s5__core__i \gpio_i [5] + connect \gpio_s5__core__o \gpio_o [5] + connect \gpio_s5__core__oe \gpio_oe [5] + connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] + connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] + connect \gpio_s6__core__i \gpio_i [6] + connect \gpio_s6__core__o \gpio_o [6] + connect \gpio_s6__core__oe \gpio_oe [6] + connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] + connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] + connect \gpio_s7__core__i \gpio_i [7] + connect \gpio_s7__core__o \gpio_o [7] + connect \gpio_s7__core__oe \gpio_oe [7] + connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] + connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] + connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte \main_libresocsim_libresoc_ibus_bte + connect \ibus__cti \main_libresocsim_libresoc_ibus_cti + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte + connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte + connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \mspi0_clk__core__o \spimaster_clk + connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + connect \mspi0_cs_n__core__o \spimaster_cs_n + connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + connect \mspi0_miso__core__i \spimaster_miso + connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + connect \mspi0_mosi__core__o \spimaster_mosi + connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + connect \mspi1_clk__core__o \spisdcard_clk + connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + connect \mspi1_cs_n__core__o \spisdcard_cs_n + connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + connect \mspi1_miso__core__i \spisdcard_miso + connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + connect \mspi1_mosi__core__o \spisdcard_mosi + connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + connect \mtwi_scl__core__o \i2c_scl + connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + connect \mtwi_sda__core__i \i2c_sda_i + connect \mtwi_sda__core__o \i2c_sda_o + connect \mtwi_sda__core__oe \i2c_sda_oe + connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \pwm_0__core__o \pwm [0] + connect \pwm_0__pad__o \pwm_1 [0] + connect \pwm_1__core__o \pwm [1] + connect \pwm_1__pad__o \pwm_1 [1] + connect \rst $or$ls180.v:10295$2762_Y + connect \sd0_clk__core__o \sdcard_clk + connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + connect \sd0_cmd__core__i \sdcard_cmd_i + connect \sd0_cmd__core__o \sdcard_cmd_o + connect \sd0_cmd__core__oe \sdcard_cmd_oe + connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_cmd_i + connect \sd0_data0__core__o \sdcard_cmd_o + connect \sd0_data0__core__oe \sdcard_cmd_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data1__core__i \sdcard_cmd_i + connect \sd0_data1__core__o \sdcard_cmd_o + connect \sd0_data1__core__oe \sdcard_cmd_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data2__core__i \sdcard_cmd_i + connect \sd0_data2__core__o \sdcard_cmd_o + connect \sd0_data2__core__oe \sdcard_cmd_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data3__core__i \sdcard_cmd_i + connect \sd0_data3__core__o \sdcard_cmd_o + connect \sd0_data3__core__oe \sdcard_cmd_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sdr_a_0__core__o \sdram_a [0] + connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] + connect \sdr_a_10__core__o \sdram_a [10] + connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] + connect \sdr_a_11__core__o \sdram_a [11] + connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] + connect \sdr_a_12__core__o \sdram_a [12] + connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] + connect \sdr_a_1__core__o \sdram_a [1] + connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] + connect \sdr_a_2__core__o \sdram_a [2] + connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] + connect \sdr_a_3__core__o \sdram_a [3] + connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] + connect \sdr_a_4__core__o \sdram_a [4] + connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] + connect \sdr_a_5__core__o \sdram_a [5] + connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] + connect \sdr_a_6__core__o \sdram_a [6] + connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] + connect \sdr_a_7__core__o \sdram_a [7] + connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] + connect \sdr_a_8__core__o \sdram_a [8] + connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] + connect \sdr_a_9__core__o \sdram_a [9] + connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] + connect \sdr_ba_0__core__o \sdram_ba [0] + connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] + connect \sdr_ba_1__core__o \sdram_ba [1] + connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] + connect \sdr_cas_n__core__o \sdram_cas_n + connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + connect \sdr_cke__core__o \sdram_cke + connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + connect \sdr_clock__core__o \sdram_clock + connect \sdr_clock__pad__o \sdram_clock_1 + connect \sdr_cs_n__core__o \sdram_cs_n + connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + connect \sdr_dm_0__core__o \sdram_dm [0] + connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] + connect \sdr_dm_1__core__i \sdram_dq_i [1] + connect \sdr_dm_1__core__o \sdram_dq_o [1] + connect \sdr_dm_1__core__oe \sdram_dq_oe + connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_0__core__i \sdram_dq_i [0] + connect \sdr_dq_0__core__o \sdram_dq_o [0] + connect \sdr_dq_0__core__oe \sdram_dq_oe + connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_10__core__i \sdram_dq_i [10] + connect \sdr_dq_10__core__o \sdram_dq_o [10] + connect \sdr_dq_10__core__oe \sdram_dq_oe + connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_11__core__i \sdram_dq_i [11] + connect \sdr_dq_11__core__o \sdram_dq_o [11] + connect \sdr_dq_11__core__oe \sdram_dq_oe + connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_12__core__i \sdram_dq_i [12] + connect \sdr_dq_12__core__o \sdram_dq_o [12] + connect \sdr_dq_12__core__oe \sdram_dq_oe + connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_13__core__i \sdram_dq_i [13] + connect \sdr_dq_13__core__o \sdram_dq_o [13] + connect \sdr_dq_13__core__oe \sdram_dq_oe + connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_14__core__i \sdram_dq_i [14] + connect \sdr_dq_14__core__o \sdram_dq_o [14] + connect \sdr_dq_14__core__oe \sdram_dq_oe + connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_15__core__i \sdram_dq_i [15] + connect \sdr_dq_15__core__o \sdram_dq_o [15] + connect \sdr_dq_15__core__oe \sdram_dq_oe + connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_1__core__i \sdram_dq_i [1] + connect \sdr_dq_1__core__o \sdram_dq_o [1] + connect \sdr_dq_1__core__oe \sdram_dq_oe + connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_2__core__i \sdram_dq_i [2] + connect \sdr_dq_2__core__o \sdram_dq_o [2] + connect \sdr_dq_2__core__oe \sdram_dq_oe + connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_3__core__i \sdram_dq_i [3] + connect \sdr_dq_3__core__o \sdram_dq_o [3] + connect \sdr_dq_3__core__oe \sdram_dq_oe + connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_4__core__i \sdram_dq_i [4] + connect \sdr_dq_4__core__o \sdram_dq_o [4] + connect \sdr_dq_4__core__oe \sdram_dq_oe + connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_5__core__i \sdram_dq_i [5] + connect \sdr_dq_5__core__o \sdram_dq_o [5] + connect \sdr_dq_5__core__oe \sdram_dq_oe + connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_6__core__i \sdram_dq_i [6] + connect \sdr_dq_6__core__o \sdram_dq_o [6] + connect \sdr_dq_6__core__oe \sdram_dq_oe + connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_7__core__i \sdram_dq_i [7] + connect \sdr_dq_7__core__o \sdram_dq_o [7] + connect \sdr_dq_7__core__oe \sdram_dq_oe + connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_8__core__i \sdram_dq_i [8] + connect \sdr_dq_8__core__o \sdram_dq_o [8] + connect \sdr_dq_8__core__oe \sdram_dq_oe + connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_9__core__i \sdram_dq_i [9] + connect \sdr_dq_9__core__o \sdram_dq_o [9] + connect \sdr_dq_9__core__oe \sdram_dq_oe + connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_ras_n__core__o \sdram_ras_n + connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + connect \sdr_we_n__core__o \sdram_we_n + connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$3720 + sync always + sync init + end + attribute \src "ls180.v:1000.12-1000.47" + process $proc$ls180.v:1000$3146 + assign { } { } + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 + sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] + sync init + end + attribute \src "ls180.v:1001.5-1001.33" + process $proc$ls180.v:1001$3147 + assign { } { } + assign $1\main_spimaster9_start[0:0] 1'0 + sync always + sync init + update \main_spimaster9_start $1\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:1003.12-1003.44" + process $proc$ls180.v:1003$3148 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] + end + attribute \src "ls180.v:1004.5-1004.31" + process $proc$ls180.v:1004$3149 + assign { } { } + assign $1\main_spimaster12_re[0:0] 1'0 + sync always + sync init + update \main_spimaster12_re $1\main_spimaster12_re[0:0] + end + attribute \src "ls180.v:10059.1-10069.4" + process $proc$ls180.v:10059$2692 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 0 + assign $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 0 + assign $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 0 + assign $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 7'xxxxxxx + assign $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 0 + assign $0\memadr[6:0] \main_libresocsim_adr + attribute \src "ls180.v:10060.2-10061.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10060.6-10060.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 255 + case + end + attribute \src "ls180.v:10062.2-10063.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10062.6-10062.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 65280 + case + end + attribute \src "ls180.v:10064.2-10065.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10064.6-10064.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 16711680 + case + end + attribute \src "ls180.v:10066.2-10067.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10066.6-10066.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 32'11111111000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[6:0] + update $memwr$\mem$ls180.v:10061$1_ADDR $0$memwr$\mem$ls180.v:10061$1_ADDR[6:0]$2693 + update $memwr$\mem$ls180.v:10061$1_DATA $0$memwr$\mem$ls180.v:10061$1_DATA[31:0]$2694 + update $memwr$\mem$ls180.v:10061$1_EN $0$memwr$\mem$ls180.v:10061$1_EN[31:0]$2695 + update $memwr$\mem$ls180.v:10063$2_ADDR $0$memwr$\mem$ls180.v:10063$2_ADDR[6:0]$2696 + update $memwr$\mem$ls180.v:10063$2_DATA $0$memwr$\mem$ls180.v:10063$2_DATA[31:0]$2697 + update $memwr$\mem$ls180.v:10063$2_EN $0$memwr$\mem$ls180.v:10063$2_EN[31:0]$2698 + update $memwr$\mem$ls180.v:10065$3_ADDR $0$memwr$\mem$ls180.v:10065$3_ADDR[6:0]$2699 + update $memwr$\mem$ls180.v:10065$3_DATA $0$memwr$\mem$ls180.v:10065$3_DATA[31:0]$2700 + update $memwr$\mem$ls180.v:10065$3_EN $0$memwr$\mem$ls180.v:10065$3_EN[31:0]$2701 + update $memwr$\mem$ls180.v:10067$4_ADDR $0$memwr$\mem$ls180.v:10067$4_ADDR[6:0]$2702 + update $memwr$\mem$ls180.v:10067$4_DATA $0$memwr$\mem$ls180.v:10067$4_DATA[31:0]$2703 + update $memwr$\mem$ls180.v:10067$4_EN $0$memwr$\mem$ls180.v:10067$4_EN[31:0]$2704 + end + attribute \src "ls180.v:10079.1-10083.4" + process $proc$ls180.v:10079$2706 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 3'xxx + assign $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10082$2710_DATA + attribute \src "ls180.v:10080.2-10081.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10080.6-10080.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10081$5_ADDR $0$memwr$\storage$ls180.v:10081$5_ADDR[2:0]$2707 + update $memwr$\storage$ls180.v:10081$5_DATA $0$memwr$\storage$ls180.v:10081$5_DATA[24:0]$2708 + update $memwr$\storage$ls180.v:10081$5_EN $0$memwr$\storage$ls180.v:10081$5_EN[24:0]$2709 + end + attribute \src "ls180.v:1008.11-1008.42" + process $proc$ls180.v:1008$3150 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + end + attribute \src "ls180.v:10085.1-10086.4" + process $proc$ls180.v:10085$2711 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1009.5-1009.31" + process $proc$ls180.v:1009$3151 + assign { } { } + assign $1\main_spimaster17_re[0:0] 1'0 + sync always + sync init + update \main_spimaster17_re $1\main_spimaster17_re[0:0] + end + attribute \src "ls180.v:10093.1-10097.4" + process $proc$ls180.v:10093$2713 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 3'xxx + assign $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10096$2717_DATA + attribute \src "ls180.v:10094.2-10095.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10094.6-10094.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10095$6_ADDR $0$memwr$\storage_1$ls180.v:10095$6_ADDR[2:0]$2714 + update $memwr$\storage_1$ls180.v:10095$6_DATA $0$memwr$\storage_1$ls180.v:10095$6_DATA[24:0]$2715 + update $memwr$\storage_1$ls180.v:10095$6_EN $0$memwr$\storage_1$ls180.v:10095$6_EN[24:0]$2716 + end + attribute \src "ls180.v:10099.1-10100.4" + process $proc$ls180.v:10099$2718 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10107.1-10111.4" + process $proc$ls180.v:10107$2720 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 3'xxx + assign $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10110$2724_DATA + attribute \src "ls180.v:10108.2-10109.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10108.6-10108.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10109$7_ADDR $0$memwr$\storage_2$ls180.v:10109$7_ADDR[2:0]$2721 + update $memwr$\storage_2$ls180.v:10109$7_DATA $0$memwr$\storage_2$ls180.v:10109$7_DATA[24:0]$2722 + update $memwr$\storage_2$ls180.v:10109$7_EN $0$memwr$\storage_2$ls180.v:10109$7_EN[24:0]$2723 + end + attribute \src "ls180.v:10113.1-10114.4" + process $proc$ls180.v:10113$2725 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10121.1-10125.4" + process $proc$ls180.v:10121$2727 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 3'xxx + assign $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10124$2731_DATA + attribute \src "ls180.v:10122.2-10123.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10122.6-10122.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10123$8_ADDR $0$memwr$\storage_3$ls180.v:10123$8_ADDR[2:0]$2728 + update $memwr$\storage_3$ls180.v:10123$8_DATA $0$memwr$\storage_3$ls180.v:10123$8_DATA[24:0]$2729 + update $memwr$\storage_3$ls180.v:10123$8_EN $0$memwr$\storage_3$ls180.v:10123$8_EN[24:0]$2730 + end + attribute \src "ls180.v:10127.1-10128.4" + process $proc$ls180.v:10127$2732 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1013.5-1013.36" + process $proc$ls180.v:1013$3152 + assign { } { } + assign $1\main_spimaster21_storage[0:0] 1'1 + sync always + sync init + update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] + end + attribute \src "ls180.v:10136.1-10140.4" + process $proc$ls180.v:10136$2734 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10139$2738_DATA + attribute \src "ls180.v:10137.2-10138.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10137.6-10137.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10138$9_ADDR $0$memwr$\storage_4$ls180.v:10138$9_ADDR[3:0]$2735 + update $memwr$\storage_4$ls180.v:10138$9_DATA $0$memwr$\storage_4$ls180.v:10138$9_DATA[9:0]$2736 + update $memwr$\storage_4$ls180.v:10138$9_EN $0$memwr$\storage_4$ls180.v:10138$9_EN[9:0]$2737 + end + attribute \src "ls180.v:1014.5-1014.31" + process $proc$ls180.v:1014$3153 + assign { } { } + assign $1\main_spimaster22_re[0:0] 1'0 + sync always + sync init + update \main_spimaster22_re $1\main_spimaster22_re[0:0] + end + attribute \src "ls180.v:10142.1-10145.4" + process $proc$ls180.v:10142$2739 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10143.2-10144.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10143.6-10143.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10144$2740_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:1015.5-1015.36" + process $proc$ls180.v:1015$3154 + assign { } { } + assign $1\main_spimaster23_storage[0:0] 1'0 + sync always + sync init + update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] + end + attribute \src "ls180.v:10153.1-10157.4" + process $proc$ls180.v:10153$2741 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10156$2745_DATA + attribute \src "ls180.v:10154.2-10155.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10154.6-10154.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10155$10_ADDR $0$memwr$\storage_5$ls180.v:10155$10_ADDR[3:0]$2742 + update $memwr$\storage_5$ls180.v:10155$10_DATA $0$memwr$\storage_5$ls180.v:10155$10_DATA[9:0]$2743 + update $memwr$\storage_5$ls180.v:10155$10_EN $0$memwr$\storage_5$ls180.v:10155$10_EN[9:0]$2744 + end + attribute \src "ls180.v:10159.1-10162.4" + process $proc$ls180.v:10159$2746 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10160.2-10161.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10160.6-10160.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10161$2747_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:1016.5-1016.31" + process $proc$ls180.v:1016$3155 + assign { } { } + assign $1\main_spimaster24_re[0:0] 1'0 + sync always + sync init + update \main_spimaster24_re $1\main_spimaster24_re[0:0] + end + attribute \src "ls180.v:10169.1-10173.4" + process $proc$ls180.v:10169$2748 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10172$2752_DATA + attribute \src "ls180.v:10170.2-10171.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10170.6-10170.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10171$11_ADDR $0$memwr$\storage_6$ls180.v:10171$11_ADDR[4:0]$2749 + update $memwr$\storage_6$ls180.v:10171$11_DATA $0$memwr$\storage_6$ls180.v:10171$11_DATA[9:0]$2750 + update $memwr$\storage_6$ls180.v:10171$11_EN $0$memwr$\storage_6$ls180.v:10171$11_EN[9:0]$2751 + end + attribute \src "ls180.v:1017.5-1017.39" + process $proc$ls180.v:1017$3156 + assign { } { } + assign $1\main_spimaster25_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] + end + attribute \src "ls180.v:10175.1-10176.4" + process $proc$ls180.v:10175$2753 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1018.5-1018.38" + process $proc$ls180.v:1018$3157 + assign { } { } + assign $1\main_spimaster26_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] + end + attribute \src "ls180.v:10183.1-10187.4" + process $proc$ls180.v:10183$2755 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10186$2759_DATA + attribute \src "ls180.v:10184.2-10185.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10184.6-10184.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10185$12_ADDR $0$memwr$\storage_7$ls180.v:10185$12_ADDR[4:0]$2756 + update $memwr$\storage_7$ls180.v:10185$12_DATA $0$memwr$\storage_7$ls180.v:10185$12_DATA[9:0]$2757 + update $memwr$\storage_7$ls180.v:10185$12_EN $0$memwr$\storage_7$ls180.v:10185$12_EN[9:0]$2758 + end + attribute \src "ls180.v:10189.1-10190.4" + process $proc$ls180.v:10189$2760 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1019.11-1019.40" + process $proc$ls180.v:1019$3158 + assign { } { } + assign $1\main_spimaster27_count[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count $1\main_spimaster27_count[2:0] + end + attribute \src "ls180.v:1020.5-1020.39" + process $proc$ls180.v:1020$3159 + assign { } { } + assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + end + attribute \src "ls180.v:1021.5-1021.39" + process $proc$ls180.v:1021$3160 + assign { } { } + assign $1\main_spimaster29_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] + end + attribute \src "ls180.v:1022.12-1022.48" + process $proc$ls180.v:1022$3161 + assign { } { } + assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] + end + attribute \src "ls180.v:1025.11-1025.44" + process $proc$ls180.v:1025$3162 + assign { } { } + assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] + end + attribute \src "ls180.v:1026.11-1026.43" + process $proc$ls180.v:1026$3163 + assign { } { } + assign $1\main_spimaster34_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] + end + attribute \src "ls180.v:1027.11-1027.44" + process $proc$ls180.v:1027$3164 + assign { } { } + assign $1\main_spimaster35_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] + end + attribute \src "ls180.v:1030.5-1030.32" + process $proc$ls180.v:1030$3165 + assign { } { } + assign $1\main_spisdcard_done0[0:0] 1'0 + sync always + sync init + update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] + end + attribute \src "ls180.v:1031.5-1031.30" + process $proc$ls180.v:1031$3166 + assign { } { } + assign $1\main_spisdcard_irq[0:0] 1'0 + sync always + sync init + update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] + end + attribute \src "ls180.v:1033.11-1033.37" + process $proc$ls180.v:1033$3167 + assign { } { } + assign $1\main_spisdcard_miso[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] + end + attribute \src "ls180.v:1037.5-1037.33" + process $proc$ls180.v:1037$3168 + assign { } { } + assign $1\main_spisdcard_start1[0:0] 1'0 + sync always + sync init + update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:1039.12-1039.50" + process $proc$ls180.v:1039$3169 + assign { } { } + assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] + end + attribute \src "ls180.v:1040.5-1040.37" + process $proc$ls180.v:1040$3170 + assign { } { } + assign $1\main_spisdcard_control_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] + end + attribute \src "ls180.v:1044.11-1044.45" + process $proc$ls180.v:1044$3171 + assign { } { } + assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] + end + attribute \src "ls180.v:1045.5-1045.34" + process $proc$ls180.v:1045$3172 + assign { } { } + assign $1\main_spisdcard_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] + end + attribute \src "ls180.v:1049.5-1049.37" + process $proc$ls180.v:1049$3173 + assign { } { } + assign $1\main_spisdcard_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] + end + attribute \src "ls180.v:1050.5-1050.32" + process $proc$ls180.v:1050$3174 + assign { } { } + assign $1\main_spisdcard_cs_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] + end + attribute \src "ls180.v:1051.5-1051.43" + process $proc$ls180.v:1051$3175 + assign { } { } + assign $1\main_spisdcard_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] + end + attribute \src "ls180.v:1052.5-1052.38" + process $proc$ls180.v:1052$3176 + assign { } { } + assign $1\main_spisdcard_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] + end + attribute \src "ls180.v:1053.5-1053.37" + process $proc$ls180.v:1053$3177 + assign { } { } + assign $1\main_spisdcard_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] + end + attribute \src "ls180.v:1054.5-1054.36" + process $proc$ls180.v:1054$3178 + assign { } { } + assign $1\main_spisdcard_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] + end + attribute \src "ls180.v:1055.11-1055.38" + process $proc$ls180.v:1055$3179 + assign { } { } + assign $1\main_spisdcard_count[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count $1\main_spisdcard_count[2:0] + end + attribute \src "ls180.v:1056.5-1056.37" + process $proc$ls180.v:1056$3180 + assign { } { } + assign $1\main_spisdcard_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] + end + attribute \src "ls180.v:1057.5-1057.37" + process $proc$ls180.v:1057$3181 + assign { } { } + assign $1\main_spisdcard_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] + end + attribute \src "ls180.v:1058.12-1058.47" + process $proc$ls180.v:1058$3182 + assign { } { } + assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] + end + attribute \src "ls180.v:1061.11-1061.42" + process $proc$ls180.v:1061$3183 + assign { } { } + assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] + end + attribute \src "ls180.v:1062.11-1062.41" + process $proc$ls180.v:1062$3184 + assign { } { } + assign $1\main_spisdcard_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] + end + attribute \src "ls180.v:1063.11-1063.42" + process $proc$ls180.v:1063$3185 + assign { } { } + assign $1\main_spisdcard_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] + end + attribute \src "ls180.v:1064.12-1064.45" + process $proc$ls180.v:1064$3186 + assign { } { } + assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 + sync always + sync init + update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] + end + attribute \src "ls180.v:1065.5-1065.30" + process $proc$ls180.v:1065$3187 + assign { } { } + assign $1\main_spimaster1_re[0:0] 1'0 + sync always + sync init + update \main_spimaster1_re $1\main_spimaster1_re[0:0] + end + attribute \src "ls180.v:1067.12-1067.30" + process $proc$ls180.v:1067$3188 + assign { } { } + assign $1\main_dummy[35:0] 36'000000000000000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[35:0] + end + attribute \src "ls180.v:1071.12-1071.37" + process $proc$ls180.v:1071$3189 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:1072.5-1072.36" + process $proc$ls180.v:1072$3190 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:1073.5-1073.31" + process $proc$ls180.v:1073$3191 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:1074.12-1074.43" + process $proc$ls180.v:1074$3192 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:1075.5-1075.30" + process $proc$ls180.v:1075$3193 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:1076.12-1076.44" + process $proc$ls180.v:1076$3194 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:1077.5-1077.31" + process $proc$ls180.v:1077$3195 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:1081.12-1081.37" + process $proc$ls180.v:1081$3196 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1082.5-1082.36" + process $proc$ls180.v:1082$3197 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1083.5-1083.31" + process $proc$ls180.v:1083$3198 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1084.12-1084.43" + process $proc$ls180.v:1084$3199 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1085.5-1085.30" + process $proc$ls180.v:1085$3200 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1086.12-1086.44" + process $proc$ls180.v:1086$3201 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:1087.5-1087.31" + process $proc$ls180.v:1087$3202 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1091.11-1091.34" + process $proc$ls180.v:1091$3203 + assign { } { } + assign $1\main_i2c_storage[2:0] 3'000 + sync always + sync init + update \main_i2c_storage $1\main_i2c_storage[2:0] + end + attribute \src "ls180.v:1092.5-1092.23" + process $proc$ls180.v:1092$3204 + assign { } { } + assign $1\main_i2c_re[0:0] 1'0 + sync always + sync init + update \main_i2c_re $1\main_i2c_re[0:0] + end + attribute \src "ls180.v:1098.11-1098.46" + process $proc$ls180.v:1098$3205 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1099.5-1099.33" + process $proc$ls180.v:1099$3206 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1101.5-1101.35" + process $proc$ls180.v:1101$3207 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1103.11-1103.41" + process $proc$ls180.v:1103$3208 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1104.5-1104.35" + process $proc$ls180.v:1104$3209 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1105.5-1105.36" + process $proc$ls180.v:1105$3210 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1109.5-1109.40" + process $proc$ls180.v:1109$3211 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1114.5-1114.48" + process $proc$ls180.v:1114$3212 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1115.5-1115.50" + process $proc$ls180.v:1115$3213 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1116.5-1116.51" + process $proc$ls180.v:1116$3214 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1117.11-1117.57" + process $proc$ls180.v:1117$3215 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1118.5-1118.52" + process $proc$ls180.v:1118$3216 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1119.11-1119.39" + process $proc$ls180.v:1119$3217 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:1124.5-1124.48" + process $proc$ls180.v:1124$3218 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1125.5-1125.50" + process $proc$ls180.v:1125$3219 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1126.5-1126.51" + process $proc$ls180.v:1126$3220 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1127.11-1127.57" + process $proc$ls180.v:1127$3221 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1128.5-1128.52" + process $proc$ls180.v:1128$3222 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1129.5-1129.38" + process $proc$ls180.v:1129$3223 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1130.5-1130.38" + process $proc$ls180.v:1130$3224 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1131.5-1131.37" + process $proc$ls180.v:1131$3225 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1132.11-1132.51" + process $proc$ls180.v:1132$3226 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1133.5-1133.32" + process $proc$ls180.v:1133$3227 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1134.11-1134.39" + process $proc$ls180.v:1134$3228 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1137.5-1137.49" + process $proc$ls180.v:1137$3229 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1138.5-1138.48" + process $proc$ls180.v:1138$3230 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1139.5-1139.55" + process $proc$ls180.v:1139$3231 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1141.5-1141.57" + process $proc$ls180.v:1141$3232 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1142.5-1142.58" + process $proc$ls180.v:1142$3233 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1144.11-1144.64" + process $proc$ls180.v:1144$3234 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1145.5-1145.59" + process $proc$ls180.v:1145$3235 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1147.5-1147.48" + process $proc$ls180.v:1147$3236 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1148.5-1148.50" + process $proc$ls180.v:1148$3237 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1149.5-1149.51" + process $proc$ls180.v:1149$3238 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1150.11-1150.57" + process $proc$ls180.v:1150$3239 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1151.5-1151.52" + process $proc$ls180.v:1151$3240 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1152.5-1152.38" + process $proc$ls180.v:1152$3241 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1153.5-1153.38" + process $proc$ls180.v:1153$3242 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1154.5-1154.37" + process $proc$ls180.v:1154$3243 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1155.11-1155.53" + process $proc$ls180.v:1155$3244 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1156.5-1156.40" + process $proc$ls180.v:1156$3245 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1157.5-1157.40" + process $proc$ls180.v:1157$3246 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1158.5-1158.39" + process $proc$ls180.v:1158$3247 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1159.11-1159.53" + process $proc$ls180.v:1159$3248 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:116.5-116.49" + process $proc$ls180.v:116$2785 + assign { } { } + assign $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_jtag_wb_ack $1\main_libresocsim_libresoc_jtag_wb_ack[0:0] + end + attribute \src "ls180.v:1160.11-1160.55" + process $proc$ls180.v:1160$3249 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1161.12-1161.48" + process $proc$ls180.v:1161$3250 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1162.11-1162.39" + process $proc$ls180.v:1162$3251 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1164.5-1164.46" + process $proc$ls180.v:1164$3252 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1175.5-1175.53" + process $proc$ls180.v:1175$3253 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:118.5-118.49" + process $proc$ls180.v:118$2786 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_jtag_wb_err $0\main_libresocsim_libresoc_jtag_wb_err[0:0] + sync init + end + attribute \src "ls180.v:1180.5-1180.36" + process $proc$ls180.v:1180$3254 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1183.5-1183.53" + process $proc$ls180.v:1183$3255 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1184.5-1184.52" + process $proc$ls180.v:1184$3256 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1188.5-1188.55" + process $proc$ls180.v:1188$3257 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1189.5-1189.54" + process $proc$ls180.v:1189$3258 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1190.11-1190.68" + process $proc$ls180.v:1190$3259 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1191.11-1191.81" + process $proc$ls180.v:1191$3260 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1192.11-1192.54" + process $proc$ls180.v:1192$3261 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1194.5-1194.53" + process $proc$ls180.v:1194$3262 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1205.5-1205.49" + process $proc$ls180.v:1205$3263 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1207.5-1207.49" + process $proc$ls180.v:1207$3264 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1208.5-1208.48" + process $proc$ls180.v:1208$3265 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1209.11-1209.62" + process $proc$ls180.v:1209$3266 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1210.5-1210.38" + process $proc$ls180.v:1210$3267 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1215.5-1215.49" + process $proc$ls180.v:1215$3268 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1216.5-1216.51" + process $proc$ls180.v:1216$3269 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1217.5-1217.52" + process $proc$ls180.v:1217$3270 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1218.11-1218.58" + process $proc$ls180.v:1218$3271 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1219.5-1219.53" + process $proc$ls180.v:1219$3272 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1220.5-1220.39" + process $proc$ls180.v:1220$3273 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1221.5-1221.39" + process $proc$ls180.v:1221$3274 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:1222.5-1222.39" + process $proc$ls180.v:1222$3275 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1223.5-1223.38" + process $proc$ls180.v:1223$3276 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1224.11-1224.52" + process $proc$ls180.v:1224$3277 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1225.5-1225.33" + process $proc$ls180.v:1225$3278 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1226.11-1226.40" + process $proc$ls180.v:1226$3279 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1227.5-1227.50" + process $proc$ls180.v:1227$3280 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1229.5-1229.50" + process $proc$ls180.v:1229$3281 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1230.5-1230.49" + process $proc$ls180.v:1230$3282 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1231.5-1231.56" + process $proc$ls180.v:1231$3283 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1232.5-1232.58" + process $proc$ls180.v:1232$3284 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1233.5-1233.58" + process $proc$ls180.v:1233$3285 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1234.5-1234.59" + process $proc$ls180.v:1234$3286 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1235.11-1235.65" + process $proc$ls180.v:1235$3287 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1236.11-1236.65" + process $proc$ls180.v:1236$3288 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1237.5-1237.60" + process $proc$ls180.v:1237$3289 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1238.5-1238.34" + process $proc$ls180.v:1238$3290 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1239.5-1239.34" + process $proc$ls180.v:1239$3291 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1240.5-1240.34" + process $proc$ls180.v:1240$3292 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:1242.5-1242.47" + process $proc$ls180.v:1242$3293 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1253.5-1253.54" + process $proc$ls180.v:1253$3294 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1258.5-1258.37" + process $proc$ls180.v:1258$3295 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1261.5-1261.54" + process $proc$ls180.v:1261$3296 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1262.5-1262.53" + process $proc$ls180.v:1262$3297 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1266.5-1266.56" + process $proc$ls180.v:1266$3298 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1267.5-1267.55" + process $proc$ls180.v:1267$3299 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1268.11-1268.69" + process $proc$ls180.v:1268$3300 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1269.11-1269.82" + process $proc$ls180.v:1269$3301 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1270.11-1270.55" + process $proc$ls180.v:1270$3302 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1272.5-1272.54" + process $proc$ls180.v:1272$3303 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1283.5-1283.50" + process $proc$ls180.v:1283$3304 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1285.5-1285.50" + process $proc$ls180.v:1285$3305 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1286.5-1286.49" + process $proc$ls180.v:1286$3306 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1287.11-1287.63" + process $proc$ls180.v:1287$3307 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1288.5-1288.39" + process $proc$ls180.v:1288$3308 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:129.12-129.74" + process $proc$ls180.v:129$2787 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] + sync init + end + attribute \src "ls180.v:1291.5-1291.50" + process $proc$ls180.v:1291$3309 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1292.5-1292.49" + process $proc$ls180.v:1292$3310 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1293.5-1293.56" + process $proc$ls180.v:1293$3311 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1295.5-1295.58" + process $proc$ls180.v:1295$3312 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1296.5-1296.59" + process $proc$ls180.v:1296$3313 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1298.11-1298.65" + process $proc$ls180.v:1298$3314 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1299.5-1299.60" + process $proc$ls180.v:1299$3315 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1301.5-1301.49" + process $proc$ls180.v:1301$3316 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1302.5-1302.51" + process $proc$ls180.v:1302$3317 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1303.5-1303.52" + process $proc$ls180.v:1303$3318 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1304.11-1304.58" + process $proc$ls180.v:1304$3319 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1305.5-1305.53" + process $proc$ls180.v:1305$3320 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1306.5-1306.39" + process $proc$ls180.v:1306$3321 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1307.5-1307.39" + process $proc$ls180.v:1307$3322 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1308.5-1308.38" + process $proc$ls180.v:1308$3323 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1309.11-1309.61" + process $proc$ls180.v:1309$3324 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1310.5-1310.41" + process $proc$ls180.v:1310$3325 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1311.5-1311.41" + process $proc$ls180.v:1311$3326 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1312.5-1312.41" + process $proc$ls180.v:1312$3327 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1313.5-1313.40" + process $proc$ls180.v:1313$3328 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1314.11-1314.54" + process $proc$ls180.v:1314$3329 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1315.11-1315.56" + process $proc$ls180.v:1315$3330 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1316.5-1316.33" + process $proc$ls180.v:1316$3331 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1317.12-1317.49" + process $proc$ls180.v:1317$3332 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1318.11-1318.41" + process $proc$ls180.v:1318$3333 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1320.5-1320.48" + process $proc$ls180.v:1320$3334 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1331.5-1331.55" + process $proc$ls180.v:1331$3335 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1336.5-1336.38" + process $proc$ls180.v:1336$3336 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1339.5-1339.55" + process $proc$ls180.v:1339$3337 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1340.5-1340.54" + process $proc$ls180.v:1340$3338 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1344.5-1344.57" + process $proc$ls180.v:1344$3339 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1345.5-1345.56" + process $proc$ls180.v:1345$3340 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1346.11-1346.70" + process $proc$ls180.v:1346$3341 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1347.11-1347.83" + process $proc$ls180.v:1347$3342 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1348.5-1348.50" + process $proc$ls180.v:1348$3343 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:135.5-135.74" + process $proc$ls180.v:135$2788 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] + sync init + end + attribute \src "ls180.v:1350.5-1350.55" + process $proc$ls180.v:1350$3344 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1361.5-1361.51" + process $proc$ls180.v:1361$3345 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1363.5-1363.51" + process $proc$ls180.v:1363$3346 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1364.5-1364.50" + process $proc$ls180.v:1364$3347 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1365.11-1365.64" + process $proc$ls180.v:1365$3348 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1366.5-1366.40" + process $proc$ls180.v:1366$3349 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1368.5-1368.35" + process $proc$ls180.v:1368$3350 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:137.5-137.72" + process $proc$ls180.v:137$2789 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1371.11-1371.42" + process $proc$ls180.v:1371$3351 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:1384.12-1384.52" + process $proc$ls180.v:1384$3352 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1385.5-1385.39" + process $proc$ls180.v:1385$3353 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1386.12-1386.51" + process $proc$ls180.v:1386$3354 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:1387.5-1387.38" + process $proc$ls180.v:1387$3355 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:1391.5-1391.34" + process $proc$ls180.v:1391$3356 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1392.13-1392.53" + process $proc$ls180.v:1392$3357 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1398.11-1398.51" + process $proc$ls180.v:1398$3358 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1399.5-1399.39" + process $proc$ls180.v:1399$3359 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:140.11-140.24" + process $proc$ls180.v:140$2790 + assign { } { } + assign $0\eint_1[2:0] 3'000 + sync always + update \eint_1 $0\eint_1[2:0] + sync init + end + attribute \src "ls180.v:1400.12-1400.51" + process $proc$ls180.v:1400$3360 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1401.5-1401.38" + process $proc$ls180.v:1401$3361 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1402.11-1402.51" + process $proc$ls180.v:1402$3362 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:1444.11-1444.47" + process $proc$ls180.v:1444$3363 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:1448.5-1448.49" + process $proc$ls180.v:1448$3364 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:145.5-145.74" + process $proc$ls180.v:145$2791 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] + sync init + end + attribute \src "ls180.v:1452.5-1452.51" + process $proc$ls180.v:1452$3365 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1453.5-1453.51" + process $proc$ls180.v:1453$3366 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1454.5-1454.51" + process $proc$ls180.v:1454$3367 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1455.5-1455.50" + process $proc$ls180.v:1455$3368 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1456.11-1456.64" + process $proc$ls180.v:1456$3369 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:1457.11-1457.48" + process $proc$ls180.v:1457$3370 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:1458.12-1458.59" + process $proc$ls180.v:1458$3371 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1462.12-1462.55" + process $proc$ls180.v:1462$3372 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1465.12-1465.59" + process $proc$ls180.v:1465$3373 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1469.12-1469.55" + process $proc$ls180.v:1469$3374 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:147.12-147.78" + process $proc$ls180.v:147$2792 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] + sync init + end + attribute \src "ls180.v:1472.12-1472.59" + process $proc$ls180.v:1472$3375 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1476.12-1476.55" + process $proc$ls180.v:1476$3376 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1479.12-1479.59" + process $proc$ls180.v:1479$3377 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1483.12-1483.55" + process $proc$ls180.v:1483$3378 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1486.12-1486.54" + process $proc$ls180.v:1486$3379 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:1487.12-1487.54" + process $proc$ls180.v:1487$3380 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:1488.12-1488.54" + process $proc$ls180.v:1488$3381 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1489.12-1489.54" + process $proc$ls180.v:1489$3382 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1490.5-1490.48" + process $proc$ls180.v:1490$3383 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1491.5-1491.48" + process $proc$ls180.v:1491$3384 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:1492.5-1492.48" + process $proc$ls180.v:1492$3385 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1493.5-1493.47" + process $proc$ls180.v:1493$3386 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1494.11-1494.61" + process $proc$ls180.v:1494$3387 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1495.5-1495.50" + process $proc$ls180.v:1495$3388 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:1497.5-1497.50" + process $proc$ls180.v:1497$3389 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:1500.11-1500.47" + process $proc$ls180.v:1500$3390 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1501.11-1501.47" + process $proc$ls180.v:1501$3391 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1502.12-1502.58" + process $proc$ls180.v:1502$3392 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1506.12-1506.54" + process $proc$ls180.v:1506$3393 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1507.5-1507.46" + process $proc$ls180.v:1507$3394 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1509.12-1509.58" + process $proc$ls180.v:1509$3395 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1513.12-1513.54" + process $proc$ls180.v:1513$3396 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1514.5-1514.46" + process $proc$ls180.v:1514$3397 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1516.12-1516.58" + process $proc$ls180.v:1516$3398 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1520.12-1520.54" + process $proc$ls180.v:1520$3399 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1521.5-1521.46" + process $proc$ls180.v:1521$3400 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:1523.12-1523.58" + process $proc$ls180.v:1523$3401 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1527.12-1527.54" + process $proc$ls180.v:1527$3402 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:1528.5-1528.46" + process $proc$ls180.v:1528$3403 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1530.12-1530.53" + process $proc$ls180.v:1530$3404 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1531.12-1531.53" + process $proc$ls180.v:1531$3405 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:1532.12-1532.53" + process $proc$ls180.v:1532$3406 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1533.12-1533.53" + process $proc$ls180.v:1533$3407 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1534.5-1534.43" + process $proc$ls180.v:1534$3408 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1535.12-1535.51" + process $proc$ls180.v:1535$3409 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1536.12-1536.51" + process $proc$ls180.v:1536$3410 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:1537.12-1537.51" + process $proc$ls180.v:1537$3411 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:1538.12-1538.51" + process $proc$ls180.v:1538$3412 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1540.11-1540.39" + process $proc$ls180.v:1540$3413 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1541.5-1541.32" + process $proc$ls180.v:1541$3414 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1542.5-1542.33" + process $proc$ls180.v:1542$3415 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1543.5-1543.35" + process $proc$ls180.v:1543$3416 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1545.12-1545.42" + process $proc$ls180.v:1545$3417 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1546.5-1546.33" + process $proc$ls180.v:1546$3418 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1547.5-1547.34" + process $proc$ls180.v:1547$3419 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1548.5-1548.36" + process $proc$ls180.v:1548$3420 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:1557.11-1557.41" + process $proc$ls180.v:1557$3421 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1558.11-1558.41" + process $proc$ls180.v:1558$3422 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1581.11-1581.45" + process $proc$ls180.v:1581$3423 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:1582.5-1582.41" + process $proc$ls180.v:1582$3424 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1583.11-1583.47" + process $proc$ls180.v:1583$3425 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:1584.11-1584.47" + process $proc$ls180.v:1584$3426 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1585.11-1585.50" + process $proc$ls180.v:1585$3427 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:159.5-159.69" + process $proc$ls180.v:159$2793 + assign { } { } + assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] + sync init + end + attribute \src "ls180.v:1605.5-1605.51" + process $proc$ls180.v:1605$3428 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1606.5-1606.50" + process $proc$ls180.v:1606$3429 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:1607.12-1607.66" + process $proc$ls180.v:1607$3430 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[31:0] + end + attribute \src "ls180.v:1608.11-1608.77" + process $proc$ls180.v:1608$3431 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + end + attribute \src "ls180.v:1609.11-1609.50" + process $proc$ls180.v:1609$3432 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[1:0] 2'00 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0] + end + attribute \src "ls180.v:1611.5-1611.49" + process $proc$ls180.v:1611$3433 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1617.5-1617.45" + process $proc$ls180.v:1617$3434 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:1619.12-1619.62" + process $proc$ls180.v:1619$3435 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:162.12-162.71" + process $proc$ls180.v:162$2794 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1620.12-1620.60" + process $proc$ls180.v:1620$3436 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[31:0] + end + attribute \src "ls180.v:1622.5-1622.57" + process $proc$ls180.v:1622$3437 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:1626.12-1626.67" + process $proc$ls180.v:1626$3438 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1627.5-1627.54" + process $proc$ls180.v:1627$3439 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1628.12-1628.69" + process $proc$ls180.v:1628$3440 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1629.5-1629.56" + process $proc$ls180.v:1629$3441 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:163.12-163.73" + process $proc$ls180.v:163$2795 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1630.5-1630.61" + process $proc$ls180.v:1630$3442 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1631.5-1631.56" + process $proc$ls180.v:1631$3443 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:1632.5-1632.53" + process $proc$ls180.v:1632$3444 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:1634.5-1634.59" + process $proc$ls180.v:1634$3445 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1635.5-1635.54" + process $proc$ls180.v:1635$3446 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:1637.12-1637.61" + process $proc$ls180.v:1637$3447 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:1640.12-1640.43" + process $proc$ls180.v:1640$3448 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1641.12-1641.45" + process $proc$ls180.v:1641$3449 + assign { } { } + assign $0\main_interface1_bus_dat_w[31:0] 0 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[31:0] + sync init + end + attribute \src "ls180.v:1643.11-1643.41" + process $proc$ls180.v:1643$3450 + assign { } { } + assign $1\main_interface1_bus_sel[3:0] 4'0000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[3:0] + end + attribute \src "ls180.v:1644.5-1644.35" + process $proc$ls180.v:1644$3451 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1645.5-1645.35" + process $proc$ls180.v:1645$3452 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:1647.5-1647.34" + process $proc$ls180.v:1647$3453 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:1648.11-1648.41" + process $proc$ls180.v:1648$3454 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1649.11-1649.41" + process $proc$ls180.v:1649$3455 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:165.11-165.69" + process $proc$ls180.v:165$2796 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1656.5-1656.43" + process $proc$ls180.v:1656$3456 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1657.5-1657.43" + process $proc$ls180.v:1657$3457 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1658.5-1658.42" + process $proc$ls180.v:1658$3458 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1659.12-1659.61" + process $proc$ls180.v:1659$3459 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:166.5-166.63" + process $proc$ls180.v:166$2797 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1660.5-1660.45" + process $proc$ls180.v:1660$3460 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:1662.5-1662.45" + process $proc$ls180.v:1662$3461 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1663.5-1663.44" + process $proc$ls180.v:1663$3462 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:1664.12-1664.60" + process $proc$ls180.v:1664$3463 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[31:0] + end + attribute \src "ls180.v:1665.12-1665.45" + process $proc$ls180.v:1665$3464 + assign { } { } + assign $1\main_sdmem2block_dma_data[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[31:0] + end + attribute \src "ls180.v:1666.12-1666.53" + process $proc$ls180.v:1666$3465 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:1667.5-1667.40" + process $proc$ls180.v:1667$3466 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:1668.12-1668.55" + process $proc$ls180.v:1668$3467 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1669.5-1669.42" + process $proc$ls180.v:1669$3468 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:167.5-167.63" + process $proc$ls180.v:167$2798 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1670.5-1670.47" + process $proc$ls180.v:1670$3469 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1671.5-1671.42" + process $proc$ls180.v:1671$3470 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:1672.5-1672.44" + process $proc$ls180.v:1672$3471 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:1674.5-1674.45" + process $proc$ls180.v:1674$3472 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1675.5-1675.40" + process $proc$ls180.v:1675$3473 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:1679.12-1679.47" + process $proc$ls180.v:1679$3474 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:169.5-169.62" + process $proc$ls180.v:169$2799 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + end + attribute \src "ls180.v:1691.11-1691.64" + process $proc$ls180.v:1691$3475 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1693.11-1693.48" + process $proc$ls180.v:1693$3476 + assign { } { } + assign $1\main_sdmem2block_converter_mux[1:0] 2'00 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[1:0] + end + attribute \src "ls180.v:170.11-170.69" + process $proc$ls180.v:170$2800 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:171.11-171.69" + process $proc$ls180.v:171$2801 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1717.11-1717.45" + process $proc$ls180.v:1717$3477 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:1718.5-1718.41" + process $proc$ls180.v:1718$3478 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1719.11-1719.47" + process $proc$ls180.v:1719$3479 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1720.11-1720.47" + process $proc$ls180.v:1720$3480 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1721.11-1721.50" + process $proc$ls180.v:1721$3481 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:173.5-173.44" + process $proc$ls180.v:173$2802 + assign { } { } + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + end + attribute \src "ls180.v:1734.5-1734.36" + process $proc$ls180.v:1734$3482 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1735.5-1735.41" + process $proc$ls180.v:1735$3483 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1736.5-1736.69" + process $proc$ls180.v:1736$3484 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1737.5-1737.72" + process $proc$ls180.v:1737$3485 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1738.5-1738.36" + process $proc$ls180.v:1738$3486 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1739.5-1739.41" + process $proc$ls180.v:1739$3487 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:174.5-174.47" + process $proc$ls180.v:174$2803 + assign { } { } + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] + end + attribute \src "ls180.v:1740.5-1740.69" + process $proc$ls180.v:1740$3488 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1741.5-1741.72" + process $proc$ls180.v:1741$3489 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1742.5-1742.36" + process $proc$ls180.v:1742$3490 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1743.5-1743.41" + process $proc$ls180.v:1743$3491 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:1744.5-1744.69" + process $proc$ls180.v:1744$3492 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value $1\main_libresocsim_converter2_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1745.5-1745.72" + process $proc$ls180.v:1745$3493 + assign { } { } + assign $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter_converter2_next_value_ce $1\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1746.11-1746.41" + process $proc$ls180.v:1746$3494 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1747.11-1747.46" + process $proc$ls180.v:1747$3495 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1748.11-1748.44" + process $proc$ls180.v:1748$3496 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:1749.11-1749.49" + process $proc$ls180.v:1749$3497 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:1750.11-1750.44" + process $proc$ls180.v:1750$3498 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1751.11-1751.49" + process $proc$ls180.v:1751$3499 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1752.11-1752.44" + process $proc$ls180.v:1752$3500 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1753.11-1753.49" + process $proc$ls180.v:1753$3501 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:1754.11-1754.44" + process $proc$ls180.v:1754$3502 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1755.11-1755.49" + process $proc$ls180.v:1755$3503 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1756.11-1756.43" + process $proc$ls180.v:1756$3504 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1757.11-1757.48" + process $proc$ls180.v:1757$3505 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:176.12-176.53" + process $proc$ls180.v:176$2804 + assign { } { } + assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + end + attribute \src "ls180.v:177.12-177.71" + process $proc$ls180.v:177$2805 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "ls180.v:1770.5-1770.27" + process $proc$ls180.v:1770$3506 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1771.5-1771.27" + process $proc$ls180.v:1771$3507 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1772.5-1772.27" + process $proc$ls180.v:1772$3508 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1773.5-1773.27" + process $proc$ls180.v:1773$3509 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:1774.5-1774.42" + process $proc$ls180.v:1774$3510 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1775.5-1775.43" + process $proc$ls180.v:1775$3511 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1776.5-1776.43" + process $proc$ls180.v:1776$3512 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1777.5-1777.43" + process $proc$ls180.v:1777$3513 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1778.5-1778.43" + process $proc$ls180.v:1778$3514 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:1779.5-1779.35" + process $proc$ls180.v:1779$3515 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:178.12-178.73" + process $proc$ls180.v:178$2806 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1780.5-1780.40" + process $proc$ls180.v:1780$3516 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1781.5-1781.55" + process $proc$ls180.v:1781$3517 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1782.5-1782.58" + process $proc$ls180.v:1782$3518 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1783.11-1783.42" + process $proc$ls180.v:1783$3519 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:1784.11-1784.47" + process $proc$ls180.v:1784$3520 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1785.11-1785.62" + process $proc$ls180.v:1785$3521 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1786.5-1786.59" + process $proc$ls180.v:1786$3522 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:1787.11-1787.42" + process $proc$ls180.v:1787$3523 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1788.11-1788.47" + process $proc$ls180.v:1788$3524 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1789.11-1789.60" + process $proc$ls180.v:1789$3525 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1790.5-1790.57" + process $proc$ls180.v:1790$3526 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1791.5-1791.41" + process $proc$ls180.v:1791$3527 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1792.5-1792.46" + process $proc$ls180.v:1792$3528 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1793.11-1793.66" + process $proc$ls180.v:1793$3529 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1794.5-1794.63" + process $proc$ls180.v:1794$3530 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1795.11-1795.47" + process $proc$ls180.v:1795$3531 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1796.11-1796.52" + process $proc$ls180.v:1796$3532 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1797.11-1797.66" + process $proc$ls180.v:1797$3533 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:1798.5-1798.63" + process $proc$ls180.v:1798$3534 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1799.11-1799.47" + process $proc$ls180.v:1799$3535 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:180.11-180.69" + process $proc$ls180.v:180$2807 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + end + attribute \src "ls180.v:1800.11-1800.52" + process $proc$ls180.v:1800$3536 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1801.11-1801.67" + process $proc$ls180.v:1801$3537 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1802.5-1802.64" + process $proc$ls180.v:1802$3538 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1803.12-1803.71" + process $proc$ls180.v:1803$3539 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:1804.5-1804.66" + process $proc$ls180.v:1804$3540 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1805.5-1805.66" + process $proc$ls180.v:1805$3541 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1806.5-1806.69" + process $proc$ls180.v:1806$3542 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1807.5-1807.41" + process $proc$ls180.v:1807$3543 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1808.5-1808.46" + process $proc$ls180.v:1808$3544 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1809.5-1809.66" + process $proc$ls180.v:1809$3545 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:181.5-181.63" + process $proc$ls180.v:181$2808 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:1810.5-1810.69" + process $proc$ls180.v:1810$3546 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1811.11-1811.41" + process $proc$ls180.v:1811$3547 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1812.11-1812.46" + process $proc$ls180.v:1812$3548 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1813.11-1813.61" + process $proc$ls180.v:1813$3549 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:1814.5-1814.58" + process $proc$ls180.v:1814$3550 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1815.11-1815.48" + process $proc$ls180.v:1815$3551 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1816.11-1816.53" + process $proc$ls180.v:1816$3552 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:1817.11-1817.70" + process $proc$ls180.v:1817$3553 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:1818.5-1818.66" + process $proc$ls180.v:1818$3554 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1819.12-1819.73" + process $proc$ls180.v:1819$3555 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:182.5-182.63" + process $proc$ls180.v:182$2809 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1820.5-1820.68" + process $proc$ls180.v:1820$3556 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1821.5-1821.69" + process $proc$ls180.v:1821$3557 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1822.5-1822.72" + process $proc$ls180.v:1822$3558 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1823.5-1823.52" + process $proc$ls180.v:1823$3559 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:1824.5-1824.57" + process $proc$ls180.v:1824$3560 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1825.12-1825.93" + process $proc$ls180.v:1825$3561 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1826.5-1826.88" + process $proc$ls180.v:1826$3562 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1827.12-1827.93" + process $proc$ls180.v:1827$3563 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:1828.5-1828.88" + process $proc$ls180.v:1828$3564 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1829.12-1829.93" + process $proc$ls180.v:1829$3565 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1830.5-1830.88" + process $proc$ls180.v:1830$3566 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1831.12-1831.93" + process $proc$ls180.v:1831$3567 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1832.5-1832.88" + process $proc$ls180.v:1832$3568 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1833.11-1833.87" + process $proc$ls180.v:1833$3569 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1834.5-1834.84" + process $proc$ls180.v:1834$3570 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1835.11-1835.42" + process $proc$ls180.v:1835$3571 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1836.11-1836.47" + process $proc$ls180.v:1836$3572 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1837.5-1837.55" + process $proc$ls180.v:1837$3573 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1838.5-1838.58" + process $proc$ls180.v:1838$3574 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1839.5-1839.56" + process $proc$ls180.v:1839$3575 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:184.5-184.62" + process $proc$ls180.v:184$2810 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] + end + attribute \src "ls180.v:1840.5-1840.59" + process $proc$ls180.v:1840$3576 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1841.11-1841.62" + process $proc$ls180.v:1841$3577 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1842.5-1842.59" + process $proc$ls180.v:1842$3578 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1843.12-1843.65" + process $proc$ls180.v:1843$3579 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:1844.5-1844.60" + process $proc$ls180.v:1844$3580 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1845.5-1845.56" + process $proc$ls180.v:1845$3581 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1846.5-1846.59" + process $proc$ls180.v:1846$3582 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1847.5-1847.58" + process $proc$ls180.v:1847$3583 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:1848.5-1848.61" + process $proc$ls180.v:1848$3584 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1849.5-1849.57" + process $proc$ls180.v:1849$3585 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:185.11-185.69" + process $proc$ls180.v:185$2811 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:1850.5-1850.60" + process $proc$ls180.v:1850$3586 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1851.5-1851.59" + process $proc$ls180.v:1851$3587 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1852.5-1852.62" + process $proc$ls180.v:1852$3588 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:1853.13-1853.76" + process $proc$ls180.v:1853$3589 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:1854.5-1854.69" + process $proc$ls180.v:1854$3590 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1855.11-1855.46" + process $proc$ls180.v:1855$3591 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1856.11-1856.51" + process $proc$ls180.v:1856$3592 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1857.12-1857.87" + process $proc$ls180.v:1857$3593 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1858.5-1858.82" + process $proc$ls180.v:1858$3594 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1859.5-1859.44" + process $proc$ls180.v:1859$3595 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:186.11-186.69" + process $proc$ls180.v:186$2812 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:1860.5-1860.49" + process $proc$ls180.v:1860$3596 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1861.12-1861.75" + process $proc$ls180.v:1861$3597 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + end + attribute \src "ls180.v:1862.5-1862.70" + process $proc$ls180.v:1862$3598 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1863.11-1863.60" + process $proc$ls180.v:1863$3599 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1864.11-1864.65" + process $proc$ls180.v:1864$3600 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1865.12-1865.87" + process $proc$ls180.v:1865$3601 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1866.5-1866.82" + process $proc$ls180.v:1866$3602 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1867.12-1867.43" + process $proc$ls180.v:1867$3603 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1868.5-1868.34" + process $proc$ls180.v:1868$3604 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1869.11-1869.43" + process $proc$ls180.v:1869$3605 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1873.12-1873.54" + process $proc$ls180.v:1873$3606 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:1877.5-1877.44" + process $proc$ls180.v:1877$3607 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:188.5-188.44" + process $proc$ls180.v:188$2813 + assign { } { } + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + end + attribute \src "ls180.v:1881.5-1881.44" + process $proc$ls180.v:1881$3608 + assign { } { } + assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + sync init + end + attribute \src "ls180.v:1884.12-1884.40" + process $proc$ls180.v:1884$3609 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:1888.5-1888.30" + process $proc$ls180.v:1888$3610 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "ls180.v:189.5-189.47" + process $proc$ls180.v:189$2814 + assign { } { } + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + end + attribute \src "ls180.v:1894.11-1894.31" + process $proc$ls180.v:1894$3611 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:1895.11-1895.35" + process $proc$ls180.v:1895$3612 + assign { } { } + assign $1\builder_slave_sel[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[4:0] + end + attribute \src "ls180.v:1896.11-1896.37" + process $proc$ls180.v:1896$3613 + assign { } { } + assign $1\builder_slave_sel_r[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] + end + attribute \src "ls180.v:1897.5-1897.25" + process $proc$ls180.v:1897$3614 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:1900.12-1900.39" + process $proc$ls180.v:1900$3615 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:1904.11-1904.51" + process $proc$ls180.v:1904$3616 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:191.12-191.53" + process $proc$ls180.v:191$2815 + assign { } { } + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] + end + attribute \src "ls180.v:192.12-192.71" + process $proc$ls180.v:192$2816 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_adr $1\main_libresocsim_interface2_converted_interface_adr[29:0] + end + attribute \src "ls180.v:193.12-193.73" + process $proc$ls180.v:193$2817 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_dat_w $1\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:1945.11-1945.51" + process $proc$ls180.v:1945$3617 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:195.11-195.69" + process $proc$ls180.v:195$2818 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_sel $1\main_libresocsim_interface2_converted_interface_sel[3:0] + end + attribute \src "ls180.v:196.5-196.63" + process $proc$ls180.v:196$2819 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_cyc $1\main_libresocsim_interface2_converted_interface_cyc[0:0] + end + attribute \src "ls180.v:197.5-197.63" + process $proc$ls180.v:197$2820 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_stb $1\main_libresocsim_interface2_converted_interface_stb[0:0] + end + attribute \src "ls180.v:1974.11-1974.51" + process $proc$ls180.v:1974$3618 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:1987.11-1987.51" + process $proc$ls180.v:1987$3619 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:199.5-199.62" + process $proc$ls180.v:199$2821 + assign { } { } + assign $1\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface2_converted_interface_we $1\main_libresocsim_interface2_converted_interface_we[0:0] + end + attribute \src "ls180.v:200.11-200.69" + process $proc$ls180.v:200$2822 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface2_converted_interface_cti $0\main_libresocsim_interface2_converted_interface_cti[2:0] + sync init + end + attribute \src "ls180.v:201.11-201.69" + process $proc$ls180.v:201$2823 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface2_converted_interface_bte $0\main_libresocsim_interface2_converted_interface_bte[1:0] + sync init + end + attribute \src "ls180.v:2028.11-2028.51" + process $proc$ls180.v:2028$3620 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:203.5-203.44" + process $proc$ls180.v:203$2824 + assign { } { } + assign $1\main_libresocsim_converter2_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_skip $1\main_libresocsim_converter2_skip[0:0] + end + attribute \src "ls180.v:204.5-204.47" + process $proc$ls180.v:204$2825 + assign { } { } + assign $1\main_libresocsim_converter2_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter2_counter $1\main_libresocsim_converter2_counter[0:0] + end + attribute \src "ls180.v:206.12-206.53" + process $proc$ls180.v:206$2826 + assign { } { } + assign $1\main_libresocsim_converter2_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter2_dat_r $1\main_libresocsim_converter2_dat_r[63:0] + end + attribute \src "ls180.v:2069.11-2069.51" + process $proc$ls180.v:2069$3621 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:213.5-213.40" + process $proc$ls180.v:213$2827 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2134.11-2134.51" + process $proc$ls180.v:2134$3622 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:217.5-217.40" + process $proc$ls180.v:217$2828 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:220.11-220.37" + process $proc$ls180.v:220$2829 + assign { } { } + assign $1\main_libresocsim_we[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:222.12-222.49" + process $proc$ls180.v:222$2830 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:223.5-223.36" + process $proc$ls180.v:223$2831 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:224.12-224.51" + process $proc$ls180.v:224$2832 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:225.5-225.38" + process $proc$ls180.v:225$2833 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:226.5-226.39" + process $proc$ls180.v:226$2834 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:2267.11-2267.51" + process $proc$ls180.v:2267$3623 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:227.5-227.34" + process $proc$ls180.v:227$2835 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:228.5-228.49" + process $proc$ls180.v:228$2836 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:229.5-229.44" + process $proc$ls180.v:229$2837 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:230.12-230.49" + process $proc$ls180.v:230$2838 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:234.5-234.41" + process $proc$ls180.v:234$2839 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:2348.11-2348.51" + process $proc$ls180.v:2348$3624 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:236.5-236.39" + process $proc$ls180.v:236$2840 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:2365.11-2365.51" + process $proc$ls180.v:2365$3625 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:237.5-237.45" + process $proc$ls180.v:237$2841 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2406.11-2406.52" + process $proc$ls180.v:2406$3626 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2439.11-2439.52" + process $proc$ls180.v:2439$3627 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:246.5-246.49" + process $proc$ls180.v:246$2842 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:247.5-247.44" + process $proc$ls180.v:247$2843 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:248.12-248.42" + process $proc$ls180.v:248$2844 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:2480.11-2480.52" + process $proc$ls180.v:2480$3628 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:252.5-252.24" + process $proc$ls180.v:252$2845 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:2545.11-2545.52" + process $proc$ls180.v:2545$3629 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2570.11-2570.52" + process $proc$ls180.v:2570$3630 + assign { } { } + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2592.11-2592.31" + process $proc$ls180.v:2592$3631 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2593.11-2593.36" + process $proc$ls180.v:2593$3632 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2594.11-2594.55" + process $proc$ls180.v:2594$3633 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2595.5-2595.52" + process $proc$ls180.v:2595$3634 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2596.12-2596.55" + process $proc$ls180.v:2596$3635 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:2597.5-2597.50" + process $proc$ls180.v:2597$3636 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2598.5-2598.46" + process $proc$ls180.v:2598$3637 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2599.5-2599.49" + process $proc$ls180.v:2599$3638 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2600.5-2600.41" + process $proc$ls180.v:2600$3639 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2601.12-2601.49" + process $proc$ls180.v:2601$3640 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2602.11-2602.47" + process $proc$ls180.v:2602$3641 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2603.5-2603.41" + process $proc$ls180.v:2603$3642 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2604.5-2604.41" + process $proc$ls180.v:2604$3643 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2605.5-2605.41" + process $proc$ls180.v:2605$3644 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2606.5-2606.39" + process $proc$ls180.v:2606$3645 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2607.5-2607.39" + process $proc$ls180.v:2607$3646 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2608.5-2608.39" + process $proc$ls180.v:2608$3647 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2609.5-2609.41" + process $proc$ls180.v:2609$3648 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2610.12-2610.49" + process $proc$ls180.v:2610$3649 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2611.11-2611.47" + process $proc$ls180.v:2611$3650 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2612.5-2612.41" + process $proc$ls180.v:2612$3651 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2613.5-2613.42" + process $proc$ls180.v:2613$3652 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2614.5-2614.42" + process $proc$ls180.v:2614$3653 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2615.5-2615.39" + process $proc$ls180.v:2615$3654 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2616.5-2616.39" + process $proc$ls180.v:2616$3655 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2617.5-2617.39" + process $proc$ls180.v:2617$3656 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2618.12-2618.50" + process $proc$ls180.v:2618$3657 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2619.5-2619.42" + process $proc$ls180.v:2619$3658 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2620.5-2620.42" + process $proc$ls180.v:2620$3659 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2621.12-2621.50" + process $proc$ls180.v:2621$3660 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2622.5-2622.42" + process $proc$ls180.v:2622$3661 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2623.5-2623.42" + process $proc$ls180.v:2623$3662 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:2624.12-2624.50" + process $proc$ls180.v:2624$3663 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2625.5-2625.42" + process $proc$ls180.v:2625$3664 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2626.5-2626.42" + process $proc$ls180.v:2626$3665 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:2627.12-2627.50" + process $proc$ls180.v:2627$3666 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2628.5-2628.42" + process $proc$ls180.v:2628$3667 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:2629.5-2629.42" + process $proc$ls180.v:2629$3668 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2630.12-2630.50" + process $proc$ls180.v:2630$3669 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2631.12-2631.50" + process $proc$ls180.v:2631$3670 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:2632.11-2632.48" + process $proc$ls180.v:2632$3671 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:2633.5-2633.42" + process $proc$ls180.v:2633$3672 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:2634.5-2634.42" + process $proc$ls180.v:2634$3673 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2635.5-2635.42" + process $proc$ls180.v:2635$3674 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2636.11-2636.48" + process $proc$ls180.v:2636$3675 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2637.11-2637.48" + process $proc$ls180.v:2637$3676 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2638.11-2638.47" + process $proc$ls180.v:2638$3677 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2639.12-2639.49" + process $proc$ls180.v:2639$3678 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2640.5-2640.41" + process $proc$ls180.v:2640$3679 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2641.5-2641.41" + process $proc$ls180.v:2641$3680 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2642.5-2642.41" + process $proc$ls180.v:2642$3681 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2643.5-2643.41" + process $proc$ls180.v:2643$3682 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2644.5-2644.41" + process $proc$ls180.v:2644$3683 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2645.5-2645.39" + process $proc$ls180.v:2645$3684 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2646.5-2646.39" + process $proc$ls180.v:2646$3685 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:267.12-267.38" + process $proc$ls180.v:267$2846 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:268.5-268.36" + process $proc$ls180.v:268$2847 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:269.11-269.32" + process $proc$ls180.v:269$2848 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:2703.32-2703.66" + process $proc$ls180.v:2703$3686 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:2704.32-2704.66" + process $proc$ls180.v:2704$3687 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2705.32-2705.66" + process $proc$ls180.v:2705$3688 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2706.32-2706.66" + process $proc$ls180.v:2706$3689 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:2707.32-2707.66" + process $proc$ls180.v:2707$3690 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2708.32-2708.66" + process $proc$ls180.v:2708$3691 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:2709.32-2709.66" + process $proc$ls180.v:2709$3692 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2710.32-2710.66" + process $proc$ls180.v:2710$3693 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2711.32-2711.66" + process $proc$ls180.v:2711$3694 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2712.32-2712.66" + process $proc$ls180.v:2712$3695 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2713.32-2713.66" + process $proc$ls180.v:2713$3696 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:2714.32-2714.66" + process $proc$ls180.v:2714$3697 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2715.32-2715.66" + process $proc$ls180.v:2715$3698 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2716.32-2716.66" + process $proc$ls180.v:2716$3699 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2717.32-2717.66" + process $proc$ls180.v:2717$3700 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2718.32-2718.66" + process $proc$ls180.v:2718$3701 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2719.32-2719.66" + process $proc$ls180.v:2719$3702 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:272.5-272.36" + process $proc$ls180.v:272$2849 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:2720.32-2720.66" + process $proc$ls180.v:2720$3703 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2721.32-2721.66" + process $proc$ls180.v:2721$3704 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2722.32-2722.66" + process $proc$ls180.v:2722$3705 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2723.32-2723.67" + process $proc$ls180.v:2723$3706 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2724.32-2724.67" + process $proc$ls180.v:2724$3707 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2725.32-2725.67" + process $proc$ls180.v:2725$3708 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2726.32-2726.67" + process $proc$ls180.v:2726$3709 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2727.32-2727.67" + process $proc$ls180.v:2727$3710 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2728.32-2728.67" + process $proc$ls180.v:2728$3711 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2729.32-2729.67" + process $proc$ls180.v:2729$3712 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + end + attribute \src "ls180.v:273.5-273.35" + process $proc$ls180.v:273$2850 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:2730.32-2730.67" + process $proc$ls180.v:2730$3713 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + end + attribute \src "ls180.v:2731.32-2731.67" + process $proc$ls180.v:2731$3714 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + end + attribute \src "ls180.v:2732.32-2732.67" + process $proc$ls180.v:2732$3715 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + end + attribute \src "ls180.v:2733.32-2733.67" + process $proc$ls180.v:2733$3716 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + end + attribute \src "ls180.v:2734.32-2734.67" + process $proc$ls180.v:2734$3717 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + end + attribute \src "ls180.v:2735.32-2735.67" + process $proc$ls180.v:2735$3718 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + end + attribute \src "ls180.v:2736.32-2736.67" + process $proc$ls180.v:2736$3719 + assign { } { } + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:274.5-274.36" + process $proc$ls180.v:274$2851 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:275.5-275.35" + process $proc$ls180.v:275$2852 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:2771.1-2776.4" + process $proc$ls180.v:2771$13 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:2778.1-2788.4" + process $proc$ls180.v:2778$15 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2780.2-2787.9" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:279.5-279.36" + process $proc$ls180.v:279$2853 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:2790.1-2836.4" + process $proc$ls180.v:2790$16 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign $0\main_libresocsim_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2802.2-2835.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } + attribute \src "ls180.v:2805.4-2812.11" + switch \main_libresocsim_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + case + end + attribute \src "ls180.v:2813.4-2826.7" + switch $and$ls180.v:2813$17_Y + attribute \src "ls180.v:2813.8-2813.81" + case 1'1 + assign $0\main_libresocsim_converter0_skip[0:0] $eq$ls180.v:2814$18_Y + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$ls180.v:2816$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$ls180.v:2817$20_Y + attribute \src "ls180.v:2818.5-2825.8" + switch $or$ls180.v:2818$21_Y + attribute \src "ls180.v:2818.9-2818.97" + case 1'1 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2819$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2821.6-2824.9" + switch $eq$ls180.v:2821$23_Y + attribute \src "ls180.v:2821.10-2821.55" + case 1'1 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2831.4-2833.7" + switch $and$ls180.v:2831$24_Y + attribute \src "ls180.v:2831.8-2831.81" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] + update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] + update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] + update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:2838.1-2848.4" + process $proc$ls180.v:2838$26 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2840.2-2847.9" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:284.12-284.45" + process $proc$ls180.v:284$2854 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:285.5-285.43" + process $proc$ls180.v:285$2855 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:2850.1-2896.4" + process $proc$ls180.v:2850$27 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_converter1_skip[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2862.2-2895.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } + attribute \src "ls180.v:2865.4-2872.11" + switch \main_libresocsim_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + case + end + attribute \src "ls180.v:2873.4-2886.7" + switch $and$ls180.v:2873$28_Y + attribute \src "ls180.v:2873.8-2873.81" + case 1'1 + assign $0\main_libresocsim_converter1_skip[0:0] $eq$ls180.v:2874$29_Y + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$ls180.v:2876$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$ls180.v:2877$31_Y + attribute \src "ls180.v:2878.5-2885.8" + switch $or$ls180.v:2878$32_Y + attribute \src "ls180.v:2878.9-2878.97" + case 1'1 + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2879$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2881.6-2884.9" + switch $eq$ls180.v:2881$34_Y + attribute \src "ls180.v:2881.10-2881.55" + case 1'1 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2891.4-2893.7" + switch $and$ls180.v:2891$35_Y + attribute \src "ls180.v:2891.8-2891.81" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] + update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] + update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] + update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:2898.1-2908.4" + process $proc$ls180.v:2898$37 + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] 0 + attribute \src "ls180.v:2900.2-2907.9" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_jtag_wb_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface2_converted_interface_dat_w $0\main_libresocsim_interface2_converted_interface_dat_w[31:0] + end + attribute \src "ls180.v:2910.1-2956.4" + process $proc$ls180.v:2910$38 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_converter2_skip[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:2922.2-2955.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_adr[29:0] { \main_libresocsim_libresoc_jtag_wb_adr \main_libresocsim_converter2_counter } + attribute \src "ls180.v:2925.4-2932.11" + switch \main_libresocsim_converter2_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface2_converted_interface_sel[3:0] \main_libresocsim_libresoc_jtag_wb_sel [7:4] + case + end + attribute \src "ls180.v:2933.4-2946.7" + switch $and$ls180.v:2933$39_Y + attribute \src "ls180.v:2933.8-2933.87" + case 1'1 + assign $0\main_libresocsim_converter2_skip[0:0] $eq$ls180.v:2934$40_Y + assign $0\main_libresocsim_interface2_converted_interface_we[0:0] \main_libresocsim_libresoc_jtag_wb_we + assign $0\main_libresocsim_interface2_converted_interface_cyc[0:0] $not$ls180.v:2936$41_Y + assign $0\main_libresocsim_interface2_converted_interface_stb[0:0] $not$ls180.v:2937$42_Y + attribute \src "ls180.v:2938.5-2945.8" + switch $or$ls180.v:2938$43_Y + attribute \src "ls180.v:2938.9-2938.97" + case 1'1 + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] $add$ls180.v:2939$44_Y + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2941.6-2944.9" + switch $eq$ls180.v:2941$45_Y + attribute \src "ls180.v:2941.10-2941.55" + case 1'1 + assign $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2951.4-2953.7" + switch $and$ls180.v:2951$46_Y + attribute \src "ls180.v:2951.8-2951.87" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_jtag_wb_ack $0\main_libresocsim_libresoc_jtag_wb_ack[0:0] + update \main_libresocsim_interface2_converted_interface_adr $0\main_libresocsim_interface2_converted_interface_adr[29:0] + update \main_libresocsim_interface2_converted_interface_sel $0\main_libresocsim_interface2_converted_interface_sel[3:0] + update \main_libresocsim_interface2_converted_interface_cyc $0\main_libresocsim_interface2_converted_interface_cyc[0:0] + update \main_libresocsim_interface2_converted_interface_stb $0\main_libresocsim_interface2_converted_interface_stb[0:0] + update \main_libresocsim_interface2_converted_interface_we $0\main_libresocsim_interface2_converted_interface_we[0:0] + update \main_libresocsim_converter2_skip $0\main_libresocsim_converter2_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value $0\main_libresocsim_converter2_counter_converter2_next_value[0:0] + update \main_libresocsim_converter2_counter_converter2_next_value_ce $0\main_libresocsim_converter2_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:2959.1-2965.4" + process $proc$ls180.v:2959$47 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$ls180.v:2961$50_Y + assign $0\main_libresocsim_we[3:0] [1] $and$ls180.v:2962$53_Y + assign $0\main_libresocsim_we[3:0] [2] $and$ls180.v:2963$56_Y + assign $0\main_libresocsim_we[3:0] [3] $and$ls180.v:2964$59_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[3:0] + end + attribute \src "ls180.v:2971.1-2976.4" + process $proc$ls180.v:2971$61 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:2973.2-2975.5" + switch $and$ls180.v:2973$62_Y + attribute \src "ls180.v:2973.6-2973.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:300.12-300.46" + process $proc$ls180.v:300$2856 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:301.5-301.44" + process $proc$ls180.v:301$2857 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:3015.1-3069.4" + process $proc$ls180.v:3015$64 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + attribute \src "ls180.v:3034.2-3068.5" + switch \main_sdram_sel + attribute \src "ls180.v:3034.6-3034.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3051.6-3051.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:302.12-302.48" + process $proc$ls180.v:302$2858 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:303.11-303.43" + process $proc$ls180.v:303$2859 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:304.5-304.38" + process $proc$ls180.v:304$2860 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:305.5-305.37" + process $proc$ls180.v:305$2861 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:306.5-306.38" + process $proc$ls180.v:306$2862 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:307.5-307.37" + process $proc$ls180.v:307$2863 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:3073.1-3089.4" + process $proc$ls180.v:3073$65 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + attribute \src "ls180.v:3078.2-3088.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3078.6-3078.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3079$66_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3080$67_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3081$68_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3082$69_Y + attribute \src "ls180.v:3083.6-3083.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:308.5-308.36" + process $proc$ls180.v:308$2864 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:309.5-309.36" + process $proc$ls180.v:309$2865 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:310.5-310.40" + process $proc$ls180.v:310$2866 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:311.5-311.38" + process $proc$ls180.v:311$2867 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:312.12-312.47" + process $proc$ls180.v:312$2868 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:313.5-313.42" + process $proc$ls180.v:313$2869 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:3132.1-3162.4" + process $proc$ls180.v:3132$78 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3138.2-3161.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3141.4-3144.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3141.8-3141.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3148.4-3152.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3148.8-3148.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3155.4-3159.7" + switch 1'1 + attribute \src "ls180.v:3155.8-3155.12" + case 1'1 + attribute \src "ls180.v:3156.5-3158.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3156.9-3156.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:314.11-314.50" + process $proc$ls180.v:314$2870 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:315.5-315.42" + process $proc$ls180.v:315$2871 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3177.1-3184.4" + process $proc$ls180.v:3177$82 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3179.2-3183.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3179.6-3179.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3181.6-3181.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3182$84_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3188.1-3195.4" + process $proc$ls180.v:3188$91 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3190.2-3194.5" + switch $and$ls180.v:3190$92_Y + attribute \src "ls180.v:3190.6-3190.115" + case 1'1 + attribute \src "ls180.v:3191.3-3193.6" + switch $ne$ls180.v:3191$93_Y + attribute \src "ls180.v:3191.7-3191.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3192$94_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:3210.1-3217.4" + process $proc$ls180.v:3210$95 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3212.2-3216.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3212.6-3212.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3213$96_Y + attribute \src "ls180.v:3214.6-3214.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:322.11-322.36" + process $proc$ls180.v:322$2872 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:3226.1-3319.4" + process $proc$ls180.v:3226$104 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3242.2-3318.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3244.4-3252.7" + switch $and$ls180.v:3244$105_Y + attribute \src "ls180.v:3244.8-3244.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3246.5-3248.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3246.9-3246.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3256.4-3258.7" + switch $and$ls180.v:3256$106_Y + attribute \src "ls180.v:3256.8-3256.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3262.4-3271.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3262.8-3262.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3267.5-3269.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3267.9-3267.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3274.4-3276.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3274.8-3274.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3279.4-3281.7" + switch $not$ls180.v:3279$107_Y + attribute \src "ls180.v:3279.8-3279.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3290.4-3316.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3290.8-3290.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3292.8-3292.12" + case + attribute \src "ls180.v:3293.5-3315.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3293.9-3293.56" + case 1'1 + attribute \src "ls180.v:3294.6-3314.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3294.10-3294.44" + case 1'1 + attribute \src "ls180.v:3295.7-3311.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3295.11-3295.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3297.8-3304.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3297.12-3297.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3301.12-3301.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3306.8-3308.11" + switch $and$ls180.v:3306$108_Y + attribute \src "ls180.v:3306.12-3306.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3309.11-3309.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3312.10-3312.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:323.5-323.25" + process $proc$ls180.v:323$2873 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:324.11-324.44" + process $proc$ls180.v:324$2874 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:325.5-325.33" + process $proc$ls180.v:325$2875 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:329.5-329.38" + process $proc$ls180.v:329$2876 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:330.12-330.46" + process $proc$ls180.v:330$2877 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:331.5-331.33" + process $proc$ls180.v:331$2878 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:332.11-332.45" + process $proc$ls180.v:332$2879 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:333.5-333.34" + process $proc$ls180.v:333$2880 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:3334.1-3341.4" + process $proc$ls180.v:3334$112 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3336.2-3340.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3336.6-3336.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3338.6-3338.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3339$114_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:334.12-334.45" + process $proc$ls180.v:334$2881 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:3345.1-3352.4" + process $proc$ls180.v:3345$121 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3347.2-3351.5" + switch $and$ls180.v:3347$122_Y + attribute \src "ls180.v:3347.6-3347.115" + case 1'1 + attribute \src "ls180.v:3348.3-3350.6" + switch $ne$ls180.v:3348$123_Y + attribute \src "ls180.v:3348.7-3348.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3349$124_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:335.5-335.32" + process $proc$ls180.v:335$2882 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:336.12-336.37" + process $proc$ls180.v:336$2883 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:3367.1-3374.4" + process $proc$ls180.v:3367$125 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3369.2-3373.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3369.6-3369.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3370$126_Y + attribute \src "ls180.v:3371.6-3371.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3383.1-3476.4" + process $proc$ls180.v:3383$134 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3399.2-3475.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3401.4-3409.7" + switch $and$ls180.v:3401$135_Y + attribute \src "ls180.v:3401.8-3401.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3403.5-3405.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3403.9-3403.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3413.4-3415.7" + switch $and$ls180.v:3413$136_Y + attribute \src "ls180.v:3413.8-3413.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3419.4-3428.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3419.8-3419.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3424.5-3426.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3424.9-3424.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3431.4-3433.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3431.8-3431.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3436.4-3438.7" + switch $not$ls180.v:3436$137_Y + attribute \src "ls180.v:3436.8-3436.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3447.4-3473.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3447.8-3447.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3449.8-3449.12" + case + attribute \src "ls180.v:3450.5-3472.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3450.9-3450.56" + case 1'1 + attribute \src "ls180.v:3451.6-3471.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3451.10-3451.44" + case 1'1 + attribute \src "ls180.v:3452.7-3468.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3452.11-3452.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3454.8-3461.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3454.12-3454.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3458.12-3458.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3463.8-3465.11" + switch $and$ls180.v:3463$138_Y + attribute \src "ls180.v:3463.12-3463.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3466.11-3466.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3469.10-3469.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:3491.1-3498.4" + process $proc$ls180.v:3491$142 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3493.2-3497.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3493.6-3493.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3495.6-3495.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3496$144_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3502.1-3509.4" + process $proc$ls180.v:3502$151 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3504.2-3508.5" + switch $and$ls180.v:3504$152_Y + attribute \src "ls180.v:3504.6-3504.115" + case 1'1 + attribute \src "ls180.v:3505.3-3507.6" + switch $ne$ls180.v:3505$153_Y + attribute \src "ls180.v:3505.7-3505.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3506$154_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:3524.1-3531.4" + process $proc$ls180.v:3524$155 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3526.2-3530.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3526.6-3526.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3527$156_Y + attribute \src "ls180.v:3528.6-3528.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:3540.1-3633.4" + process $proc$ls180.v:3540$164 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3556.2-3632.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3558.4-3566.7" + switch $and$ls180.v:3558$165_Y + attribute \src "ls180.v:3558.8-3558.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3560.5-3562.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3560.9-3560.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3570.4-3572.7" + switch $and$ls180.v:3570$166_Y + attribute \src "ls180.v:3570.8-3570.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3576.4-3585.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3576.8-3576.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3581.5-3583.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3581.9-3581.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3588.4-3590.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3588.8-3588.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3593.4-3595.7" + switch $not$ls180.v:3593$167_Y + attribute \src "ls180.v:3593.8-3593.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3604.4-3630.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3604.8-3604.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3606.8-3606.12" + case + attribute \src "ls180.v:3607.5-3629.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3607.9-3607.56" + case 1'1 + attribute \src "ls180.v:3608.6-3628.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3608.10-3608.44" + case 1'1 + attribute \src "ls180.v:3609.7-3625.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3609.11-3609.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3611.8-3618.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3611.12-3611.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3615.12-3615.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3620.8-3622.11" + switch $and$ls180.v:3620$168_Y + attribute \src "ls180.v:3620.12-3620.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3623.11-3623.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3626.10-3626.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:3648.1-3655.4" + process $proc$ls180.v:3648$172 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3650.2-3654.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3650.6-3650.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3652.6-3652.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3653$174_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3659.1-3666.4" + process $proc$ls180.v:3659$181 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3661.2-3665.5" + switch $and$ls180.v:3661$182_Y + attribute \src "ls180.v:3661.6-3661.115" + case 1'1 + attribute \src "ls180.v:3662.3-3664.6" + switch $ne$ls180.v:3662$183_Y + attribute \src "ls180.v:3662.7-3662.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3663$184_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:366.12-366.46" + process $proc$ls180.v:366$2884 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:367.11-367.47" + process $proc$ls180.v:367$2885 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:3681.1-3688.4" + process $proc$ls180.v:3681$185 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3683.2-3687.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3683.6-3683.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3684$186_Y + attribute \src "ls180.v:3685.6-3685.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:369.12-369.45" + process $proc$ls180.v:369$2886 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:3697.1-3790.4" + process $proc$ls180.v:3697$194 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3713.2-3789.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3715.4-3723.7" + switch $and$ls180.v:3715$195_Y + attribute \src "ls180.v:3715.8-3715.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3717.5-3719.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3717.9-3717.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3727.4-3729.7" + switch $and$ls180.v:3727$196_Y + attribute \src "ls180.v:3727.8-3727.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3733.4-3742.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3733.8-3733.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3738.5-3740.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3738.9-3738.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3745.4-3747.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3745.8-3745.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3750.4-3752.7" + switch $not$ls180.v:3750$197_Y + attribute \src "ls180.v:3750.8-3750.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3761.4-3787.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3761.8-3761.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3763.8-3763.12" + case + attribute \src "ls180.v:3764.5-3786.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3764.9-3764.56" + case 1'1 + attribute \src "ls180.v:3765.6-3785.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3765.10-3765.44" + case 1'1 + attribute \src "ls180.v:3766.7-3782.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3766.11-3766.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3768.8-3775.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3768.12-3768.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3772.12-3772.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3777.8-3779.11" + switch $and$ls180.v:3777$198_Y + attribute \src "ls180.v:3777.12-3777.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3780.11-3780.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3783.10-3783.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:370.11-370.40" + process $proc$ls180.v:370$2887 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:371.5-371.35" + process $proc$ls180.v:371$2888 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:372.5-372.34" + process $proc$ls180.v:372$2889 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:373.5-373.35" + process $proc$ls180.v:373$2890 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:374.5-374.34" + process $proc$ls180.v:374$2891 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "ls180.v:378.5-378.35" + process $proc$ls180.v:378$2892 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:380.5-380.39" + process $proc$ls180.v:380$2893 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:3810.1-3816.4" + process $proc$ls180.v:3810$237 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3812$250_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3813$263_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3814$276_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3815$289_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:382.5-382.39" + process $proc$ls180.v:382$2894 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:3824.1-3829.4" + process $proc$ls180.v:3824$290 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3826.2-3828.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3826.6-3826.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3830.1-3835.4" + process $proc$ls180.v:3830$291 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3832.2-3834.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3832.6-3832.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3836.1-3841.4" + process $proc$ls180.v:3836$292 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3838.2-3840.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3838.6-3838.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:3843.1-3849.4" + process $proc$ls180.v:3843$295 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3845$308_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3846$321_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3847$334_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3848$347_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:385.5-385.32" + process $proc$ls180.v:385$2895 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:3857.1-3862.4" + process $proc$ls180.v:3857$348 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3859.2-3861.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3859.6-3859.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:386.5-386.32" + process $proc$ls180.v:386$2896 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:3863.1-3868.4" + process $proc$ls180.v:3863$349 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:3865.2-3867.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3865.6-3865.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3869.1-3874.4" + process $proc$ls180.v:3869$350 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:3871.2-3873.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:3871.6-3871.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:387.5-387.31" + process $proc$ls180.v:387$2897 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:3875.1-3883.4" + process $proc$ls180.v:3875$351 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3877.2-3879.5" + switch $and$ls180.v:3877$354_Y + attribute \src "ls180.v:3877.6-3877.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3880.2-3882.5" + switch $and$ls180.v:3880$357_Y + attribute \src "ls180.v:3880.6-3880.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:388.12-388.44" + process $proc$ls180.v:388$2898 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3884.1-3892.4" + process $proc$ls180.v:3884$358 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3886.2-3888.5" + switch $and$ls180.v:3886$361_Y + attribute \src "ls180.v:3886.6-3886.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3889.2-3891.5" + switch $and$ls180.v:3889$364_Y + attribute \src "ls180.v:3889.6-3889.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:389.11-389.43" + process $proc$ls180.v:389$2899 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:3893.1-3901.4" + process $proc$ls180.v:3893$365 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3895.2-3897.5" + switch $and$ls180.v:3895$368_Y + attribute \src "ls180.v:3895.6-3895.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3898.2-3900.5" + switch $and$ls180.v:3898$371_Y + attribute \src "ls180.v:3898.6-3898.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:390.5-390.38" + process $proc$ls180.v:390$2900 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:3902.1-3910.4" + process $proc$ls180.v:3902$372 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:3904.2-3906.5" + switch $and$ls180.v:3904$375_Y + attribute \src "ls180.v:3904.6-3904.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:3907.2-3909.5" + switch $and$ls180.v:3907$378_Y + attribute \src "ls180.v:3907.6-3907.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:391.5-391.38" + process $proc$ls180.v:391$2901 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:3915.1-3987.4" + process $proc$ls180.v:3915$381 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:3927.2-3986.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3931.4-3937.7" + switch 1'1 + attribute \src "ls180.v:3931.8-3931.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3932$388_Y + case + end + attribute \src "ls180.v:3939.4-3943.7" + switch \main_sdram_read_available + attribute \src "ls180.v:3939.8-3939.33" + case 1'1 + attribute \src "ls180.v:3940.5-3942.8" + switch $or$ls180.v:3940$390_Y + attribute \src "ls180.v:3940.9-3940.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "ls180.v:3944.4-3946.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3944.8-3944.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:3951.4-3953.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:3951.8-3951.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3956.4-3958.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:3956.8-3956.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:3969.4-3975.7" + switch 1'1 + attribute \src "ls180.v:3969.8-3969.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3970$397_Y + case + end + attribute \src "ls180.v:3977.4-3981.7" + switch \main_sdram_write_available + attribute \src "ls180.v:3977.8-3977.34" + case 1'1 + attribute \src "ls180.v:3978.5-3980.8" + switch $or$ls180.v:3978$399_Y + attribute \src "ls180.v:3978.9-3978.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:3982.4-3984.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:3982.8-3982.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:392.5-392.37" + process $proc$ls180.v:392$2902 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:393.5-393.42" + process $proc$ls180.v:393$2903 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:394.5-394.43" + process $proc$ls180.v:394$2904 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:400.11-400.44" + process $proc$ls180.v:400$2905 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:4011.1-4024.4" + process $proc$ls180.v:4011$528 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:4014.2-4023.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:402.5-402.38" + process $proc$ls180.v:402$2906 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:403.5-403.38" + process $proc$ls180.v:403$2907 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:4031.1-4041.4" + process $proc$ls180.v:4031$530 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:4033.2-4040.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:404.5-404.39" + process $proc$ls180.v:404$2908 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:4043.1-4089.4" + process $proc$ls180.v:4043$531 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign { } { } + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4055.2-4088.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4058.4-4065.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4066.4-4079.7" + switch $and$ls180.v:4066$532_Y + attribute \src "ls180.v:4066.8-4066.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4067$533_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4069$534_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4070$535_Y + attribute \src "ls180.v:4071.5-4078.8" + switch $or$ls180.v:4071$536_Y + attribute \src "ls180.v:4071.9-4071.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4072$537_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4074.6-4077.9" + switch $eq$ls180.v:4074$538_Y + attribute \src "ls180.v:4074.10-4074.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4084.4-4086.7" + switch $and$ls180.v:4084$539_Y + attribute \src "ls180.v:4084.8-4084.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:407.5-407.38" + process $proc$ls180.v:407$2909 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:408.11-408.46" + process $proc$ls180.v:408$2910 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:409.5-409.38" + process $proc$ls180.v:409$2911 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:4134.1-4139.4" + process $proc$ls180.v:4134$571 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4136.2-4138.5" + switch $and$ls180.v:4136$572_Y + attribute \src "ls180.v:4136.6-4136.79" + case 1'1 + assign $0\main_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:4140.1-4144.4" + process $proc$ls180.v:4140$573 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:4145.1-4150.4" + process $proc$ls180.v:4145$574 + assign { } { } + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4147.2-4149.5" + switch $and$ls180.v:4147$575_Y + attribute \src "ls180.v:4147.6-4147.79" + case 1'1 + assign $0\main_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:415.5-415.51" + process $proc$ls180.v:415$2912 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:4151.1-4155.4" + process $proc$ls180.v:4151$576 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:416.5-416.51" + process $proc$ls180.v:416$2913 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:4173.1-4180.4" + process $proc$ls180.v:4173$584 + assign { } { } + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4175.2-4179.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4175.6-4175.31" + case 1'1 + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4176$585_Y + attribute \src "ls180.v:4177.6-4177.10" + case + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce + end + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:418.5-418.47" + process $proc$ls180.v:418$2914 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:419.5-419.45" + process $proc$ls180.v:419$2915 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:420.5-420.45" + process $proc$ls180.v:420$2916 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:4203.1-4210.4" + process $proc$ls180.v:4203$595 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4205.2-4209.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4205.6-4205.31" + case 1'1 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4206$596_Y + attribute \src "ls180.v:4207.6-4207.10" + case + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce + end + sync always + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:421.12-421.57" + process $proc$ls180.v:421$2917 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:423.5-423.51" + process $proc$ls180.v:423$2918 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:4233.1-4281.4" + process $proc$ls180.v:4233$606 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spimaster25_clk_enable[0:0] 1'0 + assign $0\main_spimaster26_cs_enable[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'0 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster29_miso_latch[0:0] 1'0 + assign $0\main_spimaster3_irq[0:0] 1'0 + assign { } { } + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4244.2-4280.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4248.4-4251.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4248.8-4248.33" + case 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spimaster25_clk_enable[0:0] 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4256.4-4262.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4256.8-4256.33" + case 1'1 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4257$607_Y + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4259.5-4261.8" + switch $eq$ls180.v:4259$609_Y + attribute \src "ls180.v:4259.9-4259.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4266.4-4270.7" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:4266.8-4266.33" + case 1'1 + assign $0\main_spimaster29_miso_latch[0:0] 1'1 + assign $0\main_spimaster3_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spimaster2_done[0:0] 1'1 + attribute \src "ls180.v:4274.4-4278.7" + switch \main_spimaster0_start + attribute \src "ls180.v:4274.8-4274.29" + case 1'1 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spimaster2_done $0\main_spimaster2_done[0:0] + update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] + update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] + update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] + update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] + update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] + update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:424.5-424.51" + process $proc$ls180.v:424$2919 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:425.5-425.50" + process $proc$ls180.v:425$2920 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:426.5-426.54" + process $proc$ls180.v:426$2921 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:427.5-427.55" + process $proc$ls180.v:427$2922 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:428.5-428.56" + process $proc$ls180.v:428$2923 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:429.5-429.50" + process $proc$ls180.v:429$2924 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:4292.1-4340.4" + process $proc$ls180.v:4292$614 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'0 + assign { } { } + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_miso_latch[0:0] 1'0 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_irq[0:0] 1'0 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:4303.2-4339.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4307.4-4310.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4307.8-4307.31" + case 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spisdcard_clk_enable[0:0] 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4315.4-4321.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4315.8-4315.31" + case 1'1 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4316$615_Y + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4318.5-4320.8" + switch $eq$ls180.v:4318$617_Y + attribute \src "ls180.v:4318.9-4318.66" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4325.4-4329.7" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:4325.8-4325.31" + case 1'1 + assign $0\main_spisdcard_miso_latch[0:0] 1'1 + assign $0\main_spisdcard_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spisdcard_done0[0:0] 1'1 + attribute \src "ls180.v:4333.4-4337.7" + switch \main_spisdcard_start0 + attribute \src "ls180.v:4333.8-4333.29" + case 1'1 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] + update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] + update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] + update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] + update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] + update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] + update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:432.5-432.67" + process $proc$ls180.v:432$2925 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:433.5-433.66" + process $proc$ls180.v:433$2926 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4372.1-4400.4" + process $proc$ls180.v:4372$639 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4374.2-4399.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:4402.1-4435.4" + process $proc$ls180.v:4402$642 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4412.2-4434.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4419.4-4425.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4419.8-4419.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4420$643_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4422.5-4424.8" + switch $eq$ls180.v:4422$644_Y + attribute \src "ls180.v:4422.9-4422.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4430.4-4432.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4430.8-4430.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:4436.1-4512.4" + process $proc$ls180.v:4436$645 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4446.2-4511.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4450.4-4475.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4476.4-4487.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4476.8-4476.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4477$646_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4479.5-4486.8" + switch $eq$ls180.v:4479$647_Y + attribute \src "ls180.v:4479.9-4479.40" + case 1'1 + attribute \src "ls180.v:4480.6-4485.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4480.10-4480.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4482.10-4482.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4493.4-4500.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4493.8-4493.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4494$648_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4496.5-4499.8" + switch $eq$ls180.v:4496$649_Y + attribute \src "ls180.v:4496.9-4496.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4505.4-4509.7" + switch $and$ls180.v:4505$650_Y + attribute \src "ls180.v:4505.8-4505.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4507.8-4507.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:448.11-448.68" + process $proc$ls180.v:448$2927 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:449.5-449.64" + process $proc$ls180.v:449$2928 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:450.11-450.70" + process $proc$ls180.v:450$2929 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:451.11-451.70" + process $proc$ls180.v:451$2930 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:452.11-452.73" + process $proc$ls180.v:452$2931 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:4546.1-4639.4" + process $proc$ls180.v:4546$659 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4564.2-4638.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4572$660_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4569.4-4571.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4569.8-4569.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4574.4-4577.7" + switch $eq$ls180.v:4574$661_Y + attribute \src "ls180.v:4574.8-4574.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4583$663_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4600$666_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4585.4-4599.7" + switch $and$ls180.v:4585$664_Y + attribute \src "ls180.v:4585.8-4585.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4587$665_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4589.5-4598.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4589.9-4589.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4591.6-4597.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4591.10-4591.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4595.10-4595.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4602.4-4605.7" + switch $eq$ls180.v:4602$667_Y + attribute \src "ls180.v:4602.8-4602.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4611.4-4617.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4611.8-4611.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4612$668_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4614.5-4616.8" + switch $eq$ls180.v:4614$669_Y + attribute \src "ls180.v:4614.9-4614.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4623.4-4625.7" + switch $and$ls180.v:4623$670_Y + attribute \src "ls180.v:4623.8-4623.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4632.4-4636.7" + switch $and$ls180.v:4632$672_Y + attribute \src "ls180.v:4632.8-4632.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:4673.1-4700.4" + process $proc$ls180.v:4673$680 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4681.2-4699.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4686.4-4690.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4686.8-4686.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4687$681_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4688$682_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4693.4-4697.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4693.8-4693.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:4701.1-4773.4" + process $proc$ls180.v:4701$683 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4712.2-4772.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4717.4-4719.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4717.8-4717.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4722$684_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4725.4-4732.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4733.4-4745.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4733.8-4733.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4734$685_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4736.5-4744.8" + switch $eq$ls180.v:4736$686_Y + attribute \src "ls180.v:4736.9-4736.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4739.6-4743.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4739.10-4739.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4741.10-4741.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4751.4-4754.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4751.8-4751.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4758.4-4763.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4758.8-4758.39" + case 1'1 + attribute \src "ls180.v:4759.5-4762.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4759.9-4759.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4768.4-4770.7" + switch $and$ls180.v:4768$687_Y + attribute \src "ls180.v:4768.8-4768.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:473.5-473.59" + process $proc$ls180.v:473$2932 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:475.5-475.59" + process $proc$ls180.v:475$2933 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:476.5-476.58" + process $proc$ls180.v:476$2934 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:477.5-477.64" + process $proc$ls180.v:477$2935 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:478.12-478.74" + process $proc$ls180.v:478$2936 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:479.12-479.47" + process $proc$ls180.v:479$2937 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:480.5-480.46" + process $proc$ls180.v:480$2938 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:4807.1-4908.4" + process $proc$ls180.v:4807$695 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:4824.2-4907.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4834$697_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4831.4-4833.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:4831.8-4831.51" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4836.4-4839.7" + switch $eq$ls180.v:4836$698_Y + attribute \src "ls180.v:4836.8-4836.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4845$701_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4866$703_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4847.4-4865.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:4847.8-4847.37" + case 1'1 + attribute \src "ls180.v:4848.5-4864.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:4848.9-4848.38" + case 1'1 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4850$702_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4852.6-4861.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:4852.10-4852.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4854.7-4860.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:4854.11-4854.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:4858.11-4858.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:4862.9-4862.13" + case + assign $0\main_sdphy_datar_stop[0:0] 1'1 + end + case + end + attribute \src "ls180.v:4868.4-4871.7" + switch $eq$ls180.v:4868$704_Y + attribute \src "ls180.v:4868.8-4868.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4875.4-4881.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4875.8-4875.39" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4876$705_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4878.5-4880.8" + switch $eq$ls180.v:4878$706_Y + attribute \src "ls180.v:4878.9-4878.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:4887.4-4889.7" + switch $and$ls180.v:4887$707_Y + attribute \src "ls180.v:4887.8-4887.71" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4894.4-4905.7" + switch $and$ls180.v:4894$708_Y + attribute \src "ls180.v:4894.8-4894.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4896.5-4904.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:4896.9-4896.40" + case 1'1 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:482.5-482.44" + process $proc$ls180.v:482$2939 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:483.5-483.45" + process $proc$ls180.v:483$2940 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:484.5-484.54" + process $proc$ls180.v:484$2941 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:486.32-486.76" + process $proc$ls180.v:486$2942 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:487.11-487.55" + process $proc$ls180.v:487$2943 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:489.32-489.75" + process $proc$ls180.v:489$2944 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:491.32-491.76" + process $proc$ls180.v:491$2945 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:4966.1-4973.4" + process $proc$ls180.v:4966$830 + assign { } { } + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:4968.2-4972.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:4968.6-4968.38" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:4970.6-4970.10" + case + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 + end + sync always + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:497.5-497.51" + process $proc$ls180.v:497$2946 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:498.5-498.51" + process $proc$ls180.v:498$2947 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:4988.1-4995.4" + process $proc$ls180.v:4988$853 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:4990.2-4994.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:4990.6-4990.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:4992.6-4992.10" + case + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:4998.1-5005.4" + process $proc$ls180.v:4998$864 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5000.2-5004.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:5000.6-5000.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:5002.6-5002.10" + case + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:500.5-500.47" + process $proc$ls180.v:500$2948 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:5008.1-5015.4" + process $proc$ls180.v:5008$875 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5010.2-5014.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:5010.6-5010.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:5012.6-5012.10" + case + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:501.5-501.45" + process $proc$ls180.v:501$2949 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:5018.1-5025.4" + process $proc$ls180.v:5018$886 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5020.2-5024.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:5020.6-5020.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:5022.6-5022.10" + case + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:502.5-502.45" + process $proc$ls180.v:502$2950 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:5026.1-5105.4" + process $proc$ls180.v:5026$887 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:5043.2-5104.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:5047.4-5049.7" + switch $eq$ls180.v:5047$888_Y + attribute \src "ls180.v:5047.8-5047.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:5050.4-5075.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:5076.4-5083.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:5076.8-5076.47" + case 1'1 + attribute \src "ls180.v:5077.5-5082.8" + switch $eq$ls180.v:5077$889_Y + attribute \src "ls180.v:5077.9-5077.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:5079.9-5079.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5080$890_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5098.4-5102.7" + switch $and$ls180.v:5098$892_Y + attribute \src "ls180.v:5098.8-5098.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:503.12-503.57" + process $proc$ls180.v:503$2951 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:505.5-505.51" + process $proc$ls180.v:505$2952 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:506.5-506.51" + process $proc$ls180.v:506$2953 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:507.5-507.50" + process $proc$ls180.v:507$2954 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:508.5-508.54" + process $proc$ls180.v:508$2955 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:509.5-509.55" + process $proc$ls180.v:509$2956 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:510.5-510.56" + process $proc$ls180.v:510$2957 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:5106.1-5111.4" + process $proc$ls180.v:5106$893 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:5108.2-5110.5" + switch $and$ls180.v:5108$900_Y + attribute \src "ls180.v:5108.6-5108.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:511.5-511.50" + process $proc$ls180.v:511$2958 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:5114.1-5121.4" + process $proc$ls180.v:5114$902 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5116.2-5120.5" + switch $eq$ls180.v:5116$903_Y + attribute \src "ls180.v:5116.6-5116.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5118.6-5118.10" + case + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:5124.1-5131.4" + process $proc$ls180.v:5124$905 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5126.2-5130.5" + switch $eq$ls180.v:5126$906_Y + attribute \src "ls180.v:5126.6-5126.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5128.6-5128.10" + case + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:5134.1-5141.4" + process $proc$ls180.v:5134$908 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5136.2-5140.5" + switch $eq$ls180.v:5136$909_Y + attribute \src "ls180.v:5136.6-5136.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5138.6-5138.10" + case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:514.5-514.67" + process $proc$ls180.v:514$2959 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:5144.1-5151.4" + process $proc$ls180.v:5144$911 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5146.2-5150.5" + switch $eq$ls180.v:5146$912_Y + attribute \src "ls180.v:5146.6-5146.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5148.6-5148.10" + case + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:515.5-515.66" + process $proc$ls180.v:515$2960 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5153.1-5158.4" + process $proc$ls180.v:5153$913 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5155.2-5157.5" + switch $and$ls180.v:5155$915_Y + attribute \src "ls180.v:5155.6-5155.85" + case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:5159.1-5166.4" + process $proc$ls180.v:5159$916 + assign { } { } + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5161.2-5165.5" + switch $lt$ls180.v:5161$917_Y + attribute \src "ls180.v:5161.6-5161.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5163.6-5163.10" + case + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready + end + sync always + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:5170.1-5177.4" + process $proc$ls180.v:5170$928 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5172.2-5176.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5172.6-5172.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5174.6-5174.10" + case + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:5180.1-5187.4" + process $proc$ls180.v:5180$939 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5182.2-5186.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5182.6-5182.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5184.6-5184.10" + case + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:5190.1-5197.4" + process $proc$ls180.v:5190$950 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5192.2-5196.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5192.6-5192.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5194.6-5194.10" + case + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:5200.1-5207.4" + process $proc$ls180.v:5200$961 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5202.2-5206.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5202.6-5202.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5204.6-5204.10" + case + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:5208.1-5398.4" + process $proc$ls180.v:5208$962 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5249.2-5397.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5252.4-5272.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5270$963_Y + case + end + attribute \src "ls180.v:5273.4-5285.7" + switch $and$ls180.v:5273$964_Y + attribute \src "ls180.v:5273.8-5273.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5274$965_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5276.5-5284.8" + switch $eq$ls180.v:5276$966_Y + attribute \src "ls180.v:5276.9-5276.40" + case 1'1 + attribute \src "ls180.v:5277.6-5283.9" + switch $eq$ls180.v:5277$967_Y + attribute \src "ls180.v:5277.10-5277.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5281.10-5281.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5289$968_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5290.4-5294.7" + switch $eq$ls180.v:5290$969_Y + attribute \src "ls180.v:5290.8-5290.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5292.8-5292.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5296.4-5317.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5296.8-5296.36" + case 1'1 + attribute \src "ls180.v:5297.5-5316.8" + switch $eq$ls180.v:5297$970_Y + attribute \src "ls180.v:5297.9-5297.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5301.9-5301.13" + case + attribute \src "ls180.v:5302.6-5315.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5302.10-5302.37" + case 1'1 + attribute \src "ls180.v:5303.7-5311.10" + switch $eq$ls180.v:5303$971_Y + attribute \src "ls180.v:5303.11-5303.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5305.11-5305.15" + case + attribute \src "ls180.v:5306.8-5310.11" + switch $eq$ls180.v:5306$972_Y + attribute \src "ls180.v:5306.12-5306.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5308.12-5308.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5312.10-5312.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5325.4-5331.7" + switch $and$ls180.v:5325$974_Y + attribute \src "ls180.v:5325.8-5325.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5326$975_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5328.5-5330.8" + switch $eq$ls180.v:5328$977_Y + attribute \src "ls180.v:5328.9-5328.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5333.4-5338.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5333.8-5333.37" + case 1'1 + attribute \src "ls180.v:5334.5-5337.8" + switch $ne$ls180.v:5334$978_Y + attribute \src "ls180.v:5334.9-5334.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5343$980_Y + attribute \src "ls180.v:5344.4-5370.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5344.8-5344.37" + case 1'1 + attribute \src "ls180.v:5345.5-5369.8" + switch $eq$ls180.v:5345$981_Y + attribute \src "ls180.v:5345.9-5345.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5351.6-5359.9" + switch $and$ls180.v:5351$982_Y + attribute \src "ls180.v:5351.10-5351.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5352$983_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5354.7-5358.10" + switch $eq$ls180.v:5354$985_Y + attribute \src "ls180.v:5354.11-5354.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5356.11-5356.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5360.9-5360.13" + case + attribute \src "ls180.v:5361.6-5368.9" + switch $eq$ls180.v:5361$986_Y + attribute \src "ls180.v:5361.10-5361.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5381.4-5395.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5381.8-5381.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:530.11-530.68" + process $proc$ls180.v:530$2961 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:531.5-531.64" + process $proc$ls180.v:531$2962 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:532.11-532.70" + process $proc$ls180.v:532$2963 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:533.11-533.70" + process $proc$ls180.v:533$2964 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:534.11-534.73" + process $proc$ls180.v:534$2965 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5426.1-5433.4" + process $proc$ls180.v:5426$987 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5428.2-5432.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5428.6-5428.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5429$988_Y + attribute \src "ls180.v:5430.6-5430.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:5459.1-5498.4" + process $proc$ls180.v:5459$998 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5469.2-5497.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[31:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5473$999_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5475.4-5486.7" + switch $and$ls180.v:5475$1000_Y + attribute \src "ls180.v:5475.8-5475.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5476$1001_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5478.5-5485.8" + switch $eq$ls180.v:5478$1003_Y + attribute \src "ls180.v:5478.9-5478.106" + case 1'1 + attribute \src "ls180.v:5479.6-5484.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5479.10-5479.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5482.10-5482.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[31:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$2775 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:5518.1-5555.4" + process $proc$ls180.v:5518$1005 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign { } { } + assign $0\main_sdmem2block_dma_source_payload_data[31:0] 0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_adr[31:0] 0 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign $0\main_interface1_bus_sel[3:0] 4'0000 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5532.2-5554.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[31:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5537.4-5540.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5537.8-5537.41" + case 1'1 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[3:0] 4'1111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5548.4-5552.7" + switch $and$ls180.v:5548$1006_Y + attribute \src "ls180.v:5548.8-5548.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[3:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[31:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:555.5-555.59" + process $proc$ls180.v:555$2966 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:5556.1-5592.4" + process $proc$ls180.v:5556$1007 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5565.2-5591.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5568$1009_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5569$1010_Y + attribute \src "ls180.v:5570.4-5581.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5570.8-5570.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5571$1011_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5573.5-5580.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5573.9-5573.39" + case 1'1 + attribute \src "ls180.v:5574.6-5579.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5574.10-5574.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5577.10-5577.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:557.5-557.59" + process $proc$ls180.v:557$2967 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:558.5-558.58" + process $proc$ls180.v:558$2968 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:559.5-559.64" + process $proc$ls180.v:559$2969 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$2776 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.12-560.74" + process $proc$ls180.v:560$2970 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:5604.1-5620.4" + process $proc$ls180.v:5604$1017 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5606.2-5619.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:561.12-561.47" + process $proc$ls180.v:561$2971 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:562.5-562.46" + process $proc$ls180.v:562$2972 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:5634.1-5641.4" + process $proc$ls180.v:5634$1018 + assign { } { } + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5636.2-5640.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5636.6-5636.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5637$1019_Y + attribute \src "ls180.v:5638.6-5638.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end + sync always + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:564.5-564.44" + process $proc$ls180.v:564$2973 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:5649.1-5685.4" + process $proc$ls180.v:5649$1025 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5660.2-5684.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5676.4-5682.7" + switch $and$ls180.v:5676$1026_Y + attribute \src "ls180.v:5676.8-5676.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5679$1028_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:565.5-565.45" + process $proc$ls180.v:565$2974 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:566.5-566.54" + process $proc$ls180.v:566$2975 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:568.32-568.76" + process $proc$ls180.v:568$2976 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:569.11-569.55" + process $proc$ls180.v:569$2977 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$2777 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:571.32-571.75" + process $proc$ls180.v:571$2978 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:5710.1-5717.4" + process $proc$ls180.v:5710$1049 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[4:0] [0] $eq$ls180.v:5712$1050_Y + assign $0\builder_slave_sel[4:0] [1] $eq$ls180.v:5713$1051_Y + assign $0\builder_slave_sel[4:0] [2] $eq$ls180.v:5714$1052_Y + assign $0\builder_slave_sel[4:0] [3] $eq$ls180.v:5715$1053_Y + assign $0\builder_slave_sel[4:0] [4] $eq$ls180.v:5716$1054_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[4:0] + end + attribute \src "ls180.v:573.32-573.76" + process $proc$ls180.v:573$2979 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:5760.1-5771.4" + process $proc$ls180.v:5760$1067 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign $0\builder_shared_ack[0:0] $or$ls180.v:5764$1071_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5765$1080_Y + attribute \src "ls180.v:5766.2-5770.5" + switch \builder_done + attribute \src "ls180.v:5766.6-5766.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:579.5-579.51" + process $proc$ls180.v:579$2980 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$2778 + assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:580.5-580.51" + process $proc$ls180.v:580$2981 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:582.5-582.47" + process $proc$ls180.v:582$2982 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:583.5-583.45" + process $proc$ls180.v:583$2983 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:584.5-584.45" + process $proc$ls180.v:584$2984 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:585.12-585.57" + process $proc$ls180.v:585$2985 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:587.5-587.51" + process $proc$ls180.v:587$2986 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:588.5-588.51" + process $proc$ls180.v:588$2987 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:589.5-589.50" + process $proc$ls180.v:589$2988 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:590.5-590.54" + process $proc$ls180.v:590$2989 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:591.5-591.55" + process $proc$ls180.v:591$2990 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:592.5-592.56" + process $proc$ls180.v:592$2991 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:593.5-593.50" + process $proc$ls180.v:593$2992 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:596.5-596.67" + process $proc$ls180.v:596$2993 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:597.5-597.66" + process $proc$ls180.v:597$2994 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:612.11-612.68" + process $proc$ls180.v:612$2995 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:613.5-613.64" + process $proc$ls180.v:613$2996 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:614.11-614.70" + process $proc$ls180.v:614$2997 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:615.11-615.70" + process $proc$ls180.v:615$2998 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:616.11-616.73" + process $proc$ls180.v:616$2999 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6285.1-6290.4" + process $proc$ls180.v:6285$1954 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6287.2-6289.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6287.6-6287.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$2779 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:6331.1-6336.4" + process $proc$ls180.v:6331$2019 + assign { } { } + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6333.2-6335.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6333.6-6333.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:637.5-637.59" + process $proc$ls180.v:637$3000 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:639.5-639.59" + process $proc$ls180.v:639$3001 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:640.5-640.58" + process $proc$ls180.v:640$3002 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:641.5-641.64" + process $proc$ls180.v:641$3003 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:642.12-642.74" + process $proc$ls180.v:642$3004 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:643.12-643.47" + process $proc$ls180.v:643$3005 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:644.5-644.46" + process $proc$ls180.v:644$3006 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:646.5-646.44" + process $proc$ls180.v:646$3007 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:647.5-647.45" + process $proc$ls180.v:647$3008 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:648.5-648.54" + process $proc$ls180.v:648$3009 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$2780 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:650.32-650.76" + process $proc$ls180.v:650$3010 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:651.11-651.55" + process $proc$ls180.v:651$3011 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:6520.1-6536.4" + process $proc$ls180.v:6520$2240 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6522.2-6535.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:653.32-653.75" + process $proc$ls180.v:653$3012 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:6537.1-6553.4" + process $proc$ls180.v:6537$2241 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6539.2-6552.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:655.32-655.76" + process $proc$ls180.v:655$3013 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:6554.1-6570.4" + process $proc$ls180.v:6554$2242 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6556.2-6569.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" - cell $add $add$libresoc.v:185121$13291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \dec2_cur_pc - connect \B 3'100 - connect \Y $add$libresoc.v:185121$13291_Y + attribute \src "ls180.v:6571.1-6587.4" + process $proc$ls180.v:6571$2243 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6573.2-6586.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185096$13264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$97 - connect \B \$99 - connect \Y $and$libresoc.v:185096$13264_Y + attribute \src "ls180.v:6588.1-6604.4" + process $proc$ls180.v:6588$2244 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6590.2-6603.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185100$13268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$105 - connect \B \$107 - connect \Y $and$libresoc.v:185100$13268_Y + attribute \src "ls180.v:6605.1-6621.4" + process $proc$ls180.v:6605$2245 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6607.2-6620.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185103$13271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$111 - connect \B \$113 - connect \Y $and$libresoc.v:185103$13271_Y + attribute \src "ls180.v:661.5-661.51" + process $proc$ls180.v:661$3014 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:185120$13290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_cu_st__rel_o - connect \B \$32 - connect \Y $and$libresoc.v:185120$13290_Y + attribute \src "ls180.v:662.5-662.51" + process $proc$ls180.v:662$3015 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185129$13299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \$51 - connect \Y $and$libresoc.v:185129$13299_Y + attribute \src "ls180.v:6622.1-6638.4" + process $proc$ls180.v:6622$2246 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6624.2-6637.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" - cell $and $and$libresoc.v:185130$13300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \core_state_nia_wen - connect \B 1'1 - connect \Y $and$libresoc.v:185130$13300_Y + attribute \src "ls180.v:6639.1-6655.4" + process $proc$ls180.v:6639$2247 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6641.2-6654.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185137$13307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$65 - connect \B \$67 - connect \Y $and$libresoc.v:185137$13307_Y + attribute \src "ls180.v:664.5-664.47" + process $proc$ls180.v:664$3016 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185140$13310 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$71 - connect \B \$73 - connect \Y $and$libresoc.v:185140$13310_Y + attribute \src "ls180.v:665.5-665.45" + process $proc$ls180.v:665$3017 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185143$13313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$77 - connect \B \$79 - connect \Y $and$libresoc.v:185143$13313_Y + attribute \src "ls180.v:6656.1-6672.4" + process $proc$ls180.v:6656$2248 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6658.2-6671.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185146$13316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$83 - connect \B \$85 - connect \Y $and$libresoc.v:185146$13316_Y + attribute \src "ls180.v:666.5-666.45" + process $proc$ls180.v:666$3018 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $and $and$libresoc.v:185149$13319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$89 - connect \B \$91 - connect \Y $and$libresoc.v:185149$13319_Y + attribute \src "ls180.v:667.12-667.57" + process $proc$ls180.v:667$3019 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:185110$13278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:185110$13278_Y + attribute \src "ls180.v:6673.1-6689.4" + process $proc$ls180.v:6673$2249 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6675.2-6688.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $extend$libresoc.v:185111$13280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:185111$13280_Y + attribute \src "ls180.v:669.5-669.51" + process $proc$ls180.v:669$3020 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:185105$13273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$libresoc.v:185105$13273_Y + attribute \src "ls180.v:6690.1-6706.4" + process $proc$ls180.v:6690$2250 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6692.2-6705.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:185107$13275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $mul$libresoc.v:185107$13275_Y + attribute \src "ls180.v:670.5-670.51" + process $proc$ls180.v:670$3021 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306" - cell $ne $ne$libresoc.v:185109$13277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \core_core_core_insn_type - connect \B 7'0000001 - connect \Y $ne$libresoc.v:185109$13277_Y + attribute \src "ls180.v:6707.1-6723.4" + process $proc$ls180.v:6707$2251 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6709.2-6722.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" - cell $ne $ne$libresoc.v:185114$13284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B 1'0 - connect \Y $ne$libresoc.v:185114$13284_Y + attribute \src "ls180.v:671.5-671.50" + process $proc$ls180.v:671$3022 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - cell $ne $ne$libresoc.v:185118$13288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B \$28 - connect \Y $ne$libresoc.v:185118$13288_Y + attribute \src "ls180.v:672.5-672.54" + process $proc$ls180.v:672$3023 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185095$13263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185095$13263_Y + attribute \src "ls180.v:6724.1-6740.4" + process $proc$ls180.v:6724$2252 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6726.2-6739.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - cell $not $not$libresoc.v:185097$13265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:185097$13265_Y + attribute \src "ls180.v:673.5-673.55" + process $proc$ls180.v:673$3024 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185098$13266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185098$13266_Y + attribute \src "ls180.v:674.5-674.56" + process $proc$ls180.v:674$3025 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185099$13267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185099$13267_Y + attribute \src "ls180.v:6741.1-6757.4" + process $proc$ls180.v:6741$2253 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:6743.2-6756.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185101$13269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185101$13269_Y + attribute \src "ls180.v:675.5-675.50" + process $proc$ls180.v:675$3026 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185102$13270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185102$13270_Y + attribute \src "ls180.v:6758.1-6774.4" + process $proc$ls180.v:6758$2254 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:6760.2-6773.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" - cell $not $not$libresoc.v:185104$13272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:185104$13272_Y + attribute \src "ls180.v:6775.1-6791.4" + process $proc$ls180.v:6775$2255 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6777.2-6790.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:185119$13289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:185119$13289_Y + attribute \src "ls180.v:678.5-678.67" + process $proc$ls180.v:678$3027 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" - cell $not $not$libresoc.v:185122$13292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $not$libresoc.v:185122$13292_Y + attribute \src "ls180.v:679.5-679.66" + process $proc$ls180.v:679$3028 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - cell $not $not$libresoc.v:185123$13293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:185123$13293_Y + attribute \src "ls180.v:6792.1-6808.4" + process $proc$ls180.v:6792$2256 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6794.2-6807.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - cell $not $not$libresoc.v:185124$13294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:185124$13294_Y + attribute \src "ls180.v:6809.1-6825.4" + process $proc$ls180.v:6809$2257 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6811.2-6824.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - cell $not $not$libresoc.v:185125$13295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:185125$13295_Y + attribute \src "ls180.v:6826.1-6833.4" + process $proc$ls180.v:6826$2258 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6828.2-6832.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - cell $not $not$libresoc.v:185126$13296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $not$libresoc.v:185126$13296_Y + attribute \src "ls180.v:6834.1-6841.4" + process $proc$ls180.v:6834$2259 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:6836.2-6840.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185127$13297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185127$13297_Y + attribute \src "ls180.v:6842.1-6849.4" + process $proc$ls180.v:6842$2260 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:6844.2-6848.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6846$2273_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185128$13298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185128$13298_Y + attribute \src "ls180.v:6850.1-6857.4" + process $proc$ls180.v:6850$2274 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6852.2-6856.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:6858.1-6865.4" + process $proc$ls180.v:6858$2275 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:6860.2-6864.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:6866.1-6873.4" + process $proc$ls180.v:6866$2276 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:6868.2-6872.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6870$2289_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:6874.1-6881.4" + process $proc$ls180.v:6874$2290 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6876.2-6880.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:6882.1-6889.4" + process $proc$ls180.v:6882$2291 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:6884.2-6888.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:6890.1-6897.4" + process $proc$ls180.v:6890$2292 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:6892.2-6896.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6894$2305_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:6898.1-6905.4" + process $proc$ls180.v:6898$2306 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:6900.2-6904.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:6906.1-6913.4" + process $proc$ls180.v:6906$2307 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:6908.2-6912.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:6914.1-6921.4" + process $proc$ls180.v:6914$2308 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:6916.2-6920.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6918$2321_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:6922.1-6941.4" + process $proc$ls180.v:6922$2322 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:6924.2-6940.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface2_converted_interface_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:694.11-694.68" + process $proc$ls180.v:694$3029 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:6942.1-6961.4" + process $proc$ls180.v:6942$2323 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[31:0] 0 + attribute \src "ls180.v:6944.2-6960.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface2_converted_interface_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "ls180.v:695.5-695.64" + process $proc$ls180.v:695$3030 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:696.11-696.70" + process $proc$ls180.v:696$3031 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:6962.1-6981.4" + process $proc$ls180.v:6962$2324 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 + attribute \src "ls180.v:6964.2-6980.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface2_converted_interface_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "ls180.v:697.11-697.70" + process $proc$ls180.v:697$3032 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:698.11-698.73" + process $proc$ls180.v:698$3033 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:6982.1-7001.4" + process $proc$ls180.v:6982$2325 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:6984.2-7000.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface2_converted_interface_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:7002.1-7021.4" + process $proc$ls180.v:7002$2326 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:7004.2-7020.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface2_converted_interface_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:7022.1-7041.4" + process $proc$ls180.v:7022$2327 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:7024.2-7040.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface2_converted_interface_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:7042.1-7061.4" + process $proc$ls180.v:7042$2328 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:7044.2-7060.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface2_converted_interface_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:7062.1-7081.4" + process $proc$ls180.v:7062$2329 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:7064.2-7080.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface2_converted_interface_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:7082.1-7098.4" + process $proc$ls180.v:7082$2330 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7084.2-7097.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:7099.1-7115.4" + process $proc$ls180.v:7099$2331 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7101.2-7114.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:7116.1-7132.4" + process $proc$ls180.v:7116$2332 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7118.2-7131.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7123$2334_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7126$2336_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7129$2338_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:7133.1-7149.4" + process $proc$ls180.v:7133$2339 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7135.2-7148.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7140$2341_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7143$2343_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7146$2345_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:7150.1-7166.4" + process $proc$ls180.v:7150$2346 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7152.2-7165.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7157$2348_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7160$2350_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7163$2352_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:7167.1-7183.4" + process $proc$ls180.v:7167$2353 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7169.2-7182.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7174$2355_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7177$2357_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7180$2359_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:7184.1-7200.4" + process $proc$ls180.v:7184$2360 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7186.2-7199.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7191$2362_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7194$2364_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7197$2366_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:719.5-719.59" + process $proc$ls180.v:719$3034 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:72.5-72.46" + process $proc$ls180.v:72$2781 + assign { } { } + assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "ls180.v:7201.1-7229.4" + process $proc$ls180.v:7201$2367 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7203.2-7228.9" + switch \main_spimaster34_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:721.5-721.59" + process $proc$ls180.v:721$3035 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:722.5-722.58" + process $proc$ls180.v:722$3036 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:723.5-723.64" + process $proc$ls180.v:723$3037 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:7230.1-7258.4" + process $proc$ls180.v:7230$2368 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7232.2-7257.9" + switch \main_spisdcard_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - cell $not $not$libresoc.v:185132$13302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:185132$13302_Y + attribute \src "ls180.v:724.12-724.74" + process $proc$ls180.v:724$3038 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - cell $not $not$libresoc.v:185133$13303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:185133$13303_Y + attribute \src "ls180.v:725.12-725.47" + process $proc$ls180.v:725$3039 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - cell $not $not$libresoc.v:185134$13304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $not$libresoc.v:185134$13304_Y + attribute \src "ls180.v:726.5-726.46" + process $proc$ls180.v:726$3040 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185135$13305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185135$13305_Y + attribute \src "ls180.v:728.5-728.44" + process $proc$ls180.v:728$3041 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185136$13306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185136$13306_Y + attribute \src "ls180.v:729.5-729.45" + process $proc$ls180.v:729$3042 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185138$13308 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185138$13308_Y + attribute \src "ls180.v:730.5-730.54" + process $proc$ls180.v:730$3043 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185139$13309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185139$13309_Y + attribute \src "ls180.v:7316.1-7334.4" + process $proc$ls180.v:7316$2369 + assign { } { } + assign { } { } + assign $0\main_gpio_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpio_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpio_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpio_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpio_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpio_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpio_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpio_status[15:0] [7] \builder_multiregimpl8_regs1 + assign $0\main_gpio_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpio_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpio_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpio_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpio_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpio_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpio_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpio_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpio_status $0\main_gpio_status[15:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185141$13311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185141$13311_Y + attribute \src "ls180.v:732.32-732.76" + process $proc$ls180.v:732$3044 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185142$13312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185142$13312_Y + attribute \src "ls180.v:733.11-733.55" + process $proc$ls180.v:733$3045 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185144$13314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185144$13314_Y + attribute \src "ls180.v:735.32-735.75" + process $proc$ls180.v:735$3046 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185145$13315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185145$13315_Y + attribute \src "ls180.v:7355.1-7357.4" + process $proc$ls180.v:7355$2370 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185147$13317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185147$13317_Y + attribute \src "ls180.v:7359.1-7429.4" + process $proc$ls180.v:7359$2371 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] + assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7416$2373_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185148$13318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_coresync_rst - connect \Y $not$libresoc.v:185148$13318_Y + attribute \src "ls180.v:737.32-737.76" + process $proc$ls180.v:737$3047 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" - cell $not $not$libresoc.v:185150$13320 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $not$libresoc.v:185150$13320_Y + attribute \src "ls180.v:740.5-740.44" + process $proc$ls180.v:740$3048 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - cell $not $not$libresoc.v:185151$13321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:185151$13321_Y + attribute \src "ls180.v:741.5-741.45" + process $proc$ls180.v:741$3049 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - cell $or $or$libresoc.v:185116$13286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:185116$13286_Y + attribute \src "ls180.v:742.5-742.43" + process $proc$ls180.v:742$3050 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:179" - cell $or $or$libresoc.v:185117$13287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$26 - connect \B \rst - connect \Y $or$libresoc.v:185117$13287_Y + attribute \src "ls180.v:743.5-743.48" + process $proc$ls180.v:743$3051 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:185110$13279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:185110$13278_Y - connect \Y $pos$libresoc.v:185110$13279_Y + attribute \src "ls180.v:7431.1-10055.4" + process $proc$ls180.v:7431$2374 + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\uart_tx[0:0] \uart_tx + assign $0\pwm[1:0] \pwm + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_converter2_dat_r + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage + assign { } { } + assign { } { } + assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen + assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg + assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount + assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy + assign { } { } + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data + assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen + assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx + assign { } { } + assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount + assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpio_oe_storage[15:0] \main_gpio_oe_storage + assign { } { } + assign $0\main_gpio_out_storage[15:0] \main_gpio_out_storage + assign { } { } + assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso + assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage + assign { } { } + assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage + assign { } { } + assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage + assign { } { } + assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage + assign { } { } + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count + assign { } { } + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data + assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel + assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso + assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage + assign { } { } + assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage + assign { } { } + assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage + assign { } { } + assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage + assign { } { } + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count + assign { } { } + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data + assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel + assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data + assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage + assign { } { } + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_i2c_storage[2:0] \main_i2c_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[1:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[1:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[35:0] [0] $or$ls180.v:7432$2375_Y + assign $0\main_dummy[35:0] [1] $or$ls180.v:7433$2376_Y + assign $0\main_dummy[35:0] [2] $or$ls180.v:7434$2377_Y + assign $0\main_dummy[35:0] [3] $or$ls180.v:7435$2378_Y + assign $0\main_dummy[35:0] [4] $or$ls180.v:7436$2379_Y + assign $0\main_dummy[35:0] [5] $or$ls180.v:7437$2380_Y + assign $0\main_dummy[35:0] [6] $or$ls180.v:7438$2381_Y + assign $0\main_dummy[35:0] [7] $or$ls180.v:7439$2382_Y + assign $0\main_dummy[35:0] [8] $or$ls180.v:7440$2383_Y + assign $0\main_dummy[35:0] [9] $or$ls180.v:7441$2384_Y + assign $0\main_dummy[35:0] [10] $or$ls180.v:7442$2385_Y + assign $0\main_dummy[35:0] [11] $or$ls180.v:7443$2386_Y + assign $0\main_dummy[35:0] [12] $or$ls180.v:7444$2387_Y + assign $0\main_dummy[35:0] [13] $or$ls180.v:7445$2388_Y + assign $0\main_dummy[35:0] [14] $or$ls180.v:7446$2389_Y + assign $0\main_dummy[35:0] [15] $or$ls180.v:7447$2390_Y + assign $0\main_dummy[35:0] [16] $or$ls180.v:7448$2391_Y + assign $0\main_dummy[35:0] [17] $or$ls180.v:7449$2392_Y + assign $0\main_dummy[35:0] [18] $or$ls180.v:7450$2393_Y + assign $0\main_dummy[35:0] [19] $or$ls180.v:7451$2394_Y + assign $0\main_dummy[35:0] [20] $or$ls180.v:7452$2395_Y + assign $0\main_dummy[35:0] [21] $or$ls180.v:7453$2396_Y + assign $0\main_dummy[35:0] [22] $or$ls180.v:7454$2397_Y + assign $0\main_dummy[35:0] [23] $or$ls180.v:7455$2398_Y + assign $0\main_dummy[35:0] [24] $or$ls180.v:7456$2399_Y + assign $0\main_dummy[35:0] [25] $or$ls180.v:7457$2400_Y + assign $0\main_dummy[35:0] [26] $or$ls180.v:7458$2401_Y + assign $0\main_dummy[35:0] [27] $or$ls180.v:7459$2402_Y + assign $0\main_dummy[35:0] [28] $or$ls180.v:7460$2403_Y + assign $0\main_dummy[35:0] [29] $or$ls180.v:7461$2404_Y + assign $0\main_dummy[35:0] [30] $or$ls180.v:7462$2405_Y + assign $0\main_dummy[35:0] [31] $or$ls180.v:7463$2406_Y + assign $0\main_dummy[35:0] [32] $or$ls180.v:7464$2407_Y + assign $0\main_dummy[35:0] [33] $or$ls180.v:7465$2408_Y + assign $0\main_dummy[35:0] [34] $or$ls180.v:7466$2409_Y + assign $0\main_dummy[35:0] [35] $or$ls180.v:7467$2410_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7909$2507_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7910$2508_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7911$2509_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:7945$2527_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:7946$2539_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8104$2585_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8113$2588_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8139$2590_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8148$2593_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[4:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpio_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpio_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re + assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re + assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re + assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re + assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re + assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re + assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re + assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re + assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpio_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpio_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpio_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpio_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpio_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpio_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpio_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpio_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpio_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpio_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpio_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpio_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpio_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpio_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpio_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpio_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7468.2-7470.5" + switch $or$ls180.v:7468$2411_Y + attribute \src "ls180.v:7468.6-7468.94" + case 1'1 + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + case + end + attribute \src "ls180.v:7472.2-7474.5" + switch \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7472.6-7472.66" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7475.2-7478.5" + switch \main_libresocsim_converter0_reset + attribute \src "ls180.v:7475.6-7475.39" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7479.2-7481.5" + switch $or$ls180.v:7479$2412_Y + attribute \src "ls180.v:7479.6-7479.94" + case 1'1 + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + case + end + attribute \src "ls180.v:7483.2-7485.5" + switch \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7483.6-7483.66" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7486.2-7489.5" + switch \main_libresocsim_converter1_reset + attribute \src "ls180.v:7486.6-7486.39" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7490.2-7492.5" + switch $or$ls180.v:7490$2413_Y + attribute \src "ls180.v:7490.6-7490.94" + case 1'1 + assign $0\main_libresocsim_converter2_dat_r[63:0] \main_libresocsim_libresoc_jtag_wb_dat_r + case + end + attribute \src "ls180.v:7494.2-7496.5" + switch \main_libresocsim_converter2_counter_converter2_next_value_ce + attribute \src "ls180.v:7494.6-7494.66" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] \main_libresocsim_converter2_counter_converter2_next_value + case + end + attribute \src "ls180.v:7497.2-7500.5" + switch \main_libresocsim_converter2_reset + attribute \src "ls180.v:7497.6-7497.39" + case 1'1 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7501.2-7505.5" + switch $ne$ls180.v:7501$2414_Y + attribute \src "ls180.v:7501.6-7501.53" + case 1'1 + attribute \src "ls180.v:7502.3-7504.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7502.7-7502.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7503$2415_Y + case + end + case + end + attribute \src "ls180.v:7507.2-7509.5" + switch $and$ls180.v:7507$2418_Y + attribute \src "ls180.v:7507.6-7507.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7510.2-7518.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7510.6-7510.33" + case 1'1 + attribute \src "ls180.v:7511.3-7515.6" + switch $eq$ls180.v:7511$2419_Y + attribute \src "ls180.v:7511.7-7511.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7513.7-7513.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7514$2420_Y + end + attribute \src "ls180.v:7516.6-7516.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7519.2-7521.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7519.6-7519.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7522.2-7524.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7522.6-7522.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7526.2-7528.5" + switch $and$ls180.v:7526$2422_Y + attribute \src "ls180.v:7526.6-7526.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7531.2-7533.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7531.6-7531.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7534.2-7538.5" + switch $and$ls180.v:7534$2424_Y + attribute \src "ls180.v:7534.6-7534.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7535$2425_Y + attribute \src "ls180.v:7536.6-7536.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7540.2-7546.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7540.6-7540.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7541$2426_Y + attribute \src "ls180.v:7542.3-7545.6" + switch $eq$ls180.v:7542$2427_Y + attribute \src "ls180.v:7542.7-7542.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7547.2-7555.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7547.6-7547.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7549.6-7549.10" + case + attribute \src "ls180.v:7550.3-7554.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7550.7-7550.33" + case 1'1 + attribute \src "ls180.v:7551.4-7553.7" + switch $ne$ls180.v:7551$2428_Y + attribute \src "ls180.v:7551.8-7551.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7552$2429_Y + case + end + case + end + end + attribute \src "ls180.v:7562.2-7568.5" + switch $and$ls180.v:7562$2431_Y + attribute \src "ls180.v:7562.6-7562.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7569.2-7575.5" + switch $eq$ls180.v:7569$2432_Y + attribute \src "ls180.v:7569.6-7569.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7576.2-7583.5" + switch $eq$ls180.v:7576$2433_Y + attribute \src "ls180.v:7576.6-7576.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7584.2-7594.5" + switch $eq$ls180.v:7584$2434_Y + attribute \src "ls180.v:7584.6-7584.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7586.6-7586.10" + case + attribute \src "ls180.v:7587.3-7593.6" + switch $ne$ls180.v:7587$2435_Y + attribute \src "ls180.v:7587.7-7587.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7588$2436_Y + attribute \src "ls180.v:7589.7-7589.11" + case + attribute \src "ls180.v:7590.4-7592.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7590.8-7590.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7596.2-7603.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7596.6-7596.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7598.6-7598.10" + case + attribute \src "ls180.v:7599.3-7602.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7599.7-7599.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7604.2-7606.5" + switch $and$ls180.v:7604$2439_Y + attribute \src "ls180.v:7604.6-7604.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7605$2440_Y + case + end + attribute \src "ls180.v:7607.2-7609.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7607.6-7607.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7608$2441_Y + case + end + attribute \src "ls180.v:7610.2-7618.5" + switch $and$ls180.v:7610$2444_Y + attribute \src "ls180.v:7610.6-7610.191" + case 1'1 + attribute \src "ls180.v:7611.3-7613.6" + switch $not$ls180.v:7611$2445_Y + attribute \src "ls180.v:7611.7-7611.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7612$2446_Y + case + end + attribute \src "ls180.v:7614.6-7614.10" + case + attribute \src "ls180.v:7615.3-7617.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7615.7-7615.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7616$2447_Y + case + end + end + attribute \src "ls180.v:7619.2-7625.5" + switch $or$ls180.v:7619$2449_Y + attribute \src "ls180.v:7619.6-7619.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7626.2-7640.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7626.6-7626.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7628.3-7632.6" + switch 1'0 + attribute \src "ls180.v:7630.7-7630.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7633.6-7633.10" + case + attribute \src "ls180.v:7634.3-7639.6" + switch $not$ls180.v:7634$2450_Y + attribute \src "ls180.v:7634.7-7634.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7635$2451_Y + attribute \src "ls180.v:7636.4-7638.7" + switch $eq$ls180.v:7636$2452_Y + attribute \src "ls180.v:7636.8-7636.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7642.2-7649.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7642.6-7642.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7644.6-7644.10" + case + attribute \src "ls180.v:7645.3-7648.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7645.7-7645.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7650.2-7652.5" + switch $and$ls180.v:7650$2455_Y + attribute \src "ls180.v:7650.6-7650.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7651$2456_Y + case + end + attribute \src "ls180.v:7653.2-7655.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7653.6-7653.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7654$2457_Y + case + end + attribute \src "ls180.v:7656.2-7664.5" + switch $and$ls180.v:7656$2460_Y + attribute \src "ls180.v:7656.6-7656.191" + case 1'1 + attribute \src "ls180.v:7657.3-7659.6" + switch $not$ls180.v:7657$2461_Y + attribute \src "ls180.v:7657.7-7657.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7658$2462_Y + case + end + attribute \src "ls180.v:7660.6-7660.10" + case + attribute \src "ls180.v:7661.3-7663.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7661.7-7661.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7662$2463_Y + case + end + end + attribute \src "ls180.v:7665.2-7671.5" + switch $or$ls180.v:7665$2465_Y + attribute \src "ls180.v:7665.6-7665.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7672.2-7686.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7672.6-7672.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7674.3-7678.6" + switch 1'0 + attribute \src "ls180.v:7676.7-7676.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7679.6-7679.10" + case + attribute \src "ls180.v:7680.3-7685.6" + switch $not$ls180.v:7680$2466_Y + attribute \src "ls180.v:7680.7-7680.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7681$2467_Y + attribute \src "ls180.v:7682.4-7684.7" + switch $eq$ls180.v:7682$2468_Y + attribute \src "ls180.v:7682.8-7682.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7688.2-7695.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7688.6-7688.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7690.6-7690.10" + case + attribute \src "ls180.v:7691.3-7694.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7691.7-7691.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7696.2-7698.5" + switch $and$ls180.v:7696$2471_Y + attribute \src "ls180.v:7696.6-7696.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7697$2472_Y + case + end + attribute \src "ls180.v:7699.2-7701.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7699.6-7699.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7700$2473_Y + case + end + attribute \src "ls180.v:7702.2-7710.5" + switch $and$ls180.v:7702$2476_Y + attribute \src "ls180.v:7702.6-7702.191" + case 1'1 + attribute \src "ls180.v:7703.3-7705.6" + switch $not$ls180.v:7703$2477_Y + attribute \src "ls180.v:7703.7-7703.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7704$2478_Y + case + end + attribute \src "ls180.v:7706.6-7706.10" + case + attribute \src "ls180.v:7707.3-7709.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7707.7-7707.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7708$2479_Y + case + end + end + attribute \src "ls180.v:7711.2-7717.5" + switch $or$ls180.v:7711$2481_Y + attribute \src "ls180.v:7711.6-7711.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7718.2-7732.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7718.6-7718.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7720.3-7724.6" + switch 1'0 + attribute \src "ls180.v:7722.7-7722.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7725.6-7725.10" + case + attribute \src "ls180.v:7726.3-7731.6" + switch $not$ls180.v:7726$2482_Y + attribute \src "ls180.v:7726.7-7726.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7727$2483_Y + attribute \src "ls180.v:7728.4-7730.7" + switch $eq$ls180.v:7728$2484_Y + attribute \src "ls180.v:7728.8-7728.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7734.2-7741.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:7734.6-7734.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:7736.6-7736.10" + case + attribute \src "ls180.v:7737.3-7740.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:7737.7-7737.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7742.2-7744.5" + switch $and$ls180.v:7742$2487_Y + attribute \src "ls180.v:7742.6-7742.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7743$2488_Y + case + end + attribute \src "ls180.v:7745.2-7747.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7745.6-7745.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7746$2489_Y + case + end + attribute \src "ls180.v:7748.2-7756.5" + switch $and$ls180.v:7748$2492_Y + attribute \src "ls180.v:7748.6-7748.191" + case 1'1 + attribute \src "ls180.v:7749.3-7751.6" + switch $not$ls180.v:7749$2493_Y + attribute \src "ls180.v:7749.7-7749.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7750$2494_Y + case + end + attribute \src "ls180.v:7752.6-7752.10" + case + attribute \src "ls180.v:7753.3-7755.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7753.7-7753.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7754$2495_Y + case + end + end + attribute \src "ls180.v:7757.2-7763.5" + switch $or$ls180.v:7757$2497_Y + attribute \src "ls180.v:7757.6-7757.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7764.2-7778.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:7764.6-7764.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7766.3-7770.6" + switch 1'0 + attribute \src "ls180.v:7768.7-7768.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7771.6-7771.10" + case + attribute \src "ls180.v:7772.3-7777.6" + switch $not$ls180.v:7772$2498_Y + attribute \src "ls180.v:7772.7-7772.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7773$2499_Y + attribute \src "ls180.v:7774.4-7776.7" + switch $eq$ls180.v:7774$2500_Y + attribute \src "ls180.v:7774.8-7774.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7780.2-7786.5" + switch $not$ls180.v:7780$2501_Y + attribute \src "ls180.v:7780.6-7780.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:7782.6-7782.10" + case + attribute \src "ls180.v:7783.3-7785.6" + switch $not$ls180.v:7783$2502_Y + attribute \src "ls180.v:7783.7-7783.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:7784$2503_Y + case + end + end + attribute \src "ls180.v:7787.2-7793.5" + switch $not$ls180.v:7787$2504_Y + attribute \src "ls180.v:7787.6-7787.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:7789.6-7789.10" + case + attribute \src "ls180.v:7790.3-7792.6" + switch $not$ls180.v:7790$2505_Y + attribute \src "ls180.v:7790.7-7790.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:7791$2506_Y + case + end + end + attribute \src "ls180.v:7794.2-7849.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:7794.6-7794.30" + case 1'1 + attribute \src "ls180.v:7795.3-7848.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7797.5-7807.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7797.9-7797.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7799.9-7799.13" + case + attribute \src "ls180.v:7800.6-7806.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7800.10-7800.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7802.10-7802.14" + case + attribute \src "ls180.v:7803.7-7805.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7803.11-7803.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7810.5-7820.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7810.9-7810.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:7812.9-7812.13" + case + attribute \src "ls180.v:7813.6-7819.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7813.10-7813.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7815.10-7815.14" + case + attribute \src "ls180.v:7816.7-7818.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7816.11-7816.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7823.5-7833.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:7823.9-7823.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:7825.9-7825.13" + case + attribute \src "ls180.v:7826.6-7832.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7826.10-7826.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7828.10-7828.14" + case + attribute \src "ls180.v:7829.7-7831.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7829.11-7829.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7836.5-7846.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:7836.9-7836.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:7838.9-7838.13" + case + attribute \src "ls180.v:7839.6-7845.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:7839.10-7839.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:7841.10-7841.14" + case + attribute \src "ls180.v:7842.7-7844.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:7842.11-7842.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7850.2-7905.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:7850.6-7850.30" + case 1'1 + attribute \src "ls180.v:7851.3-7904.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:7853.5-7863.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7853.9-7853.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7855.9-7855.13" + case + attribute \src "ls180.v:7856.6-7862.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7856.10-7856.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7858.10-7858.14" + case + attribute \src "ls180.v:7859.7-7861.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7859.11-7859.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:7866.5-7876.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7866.9-7866.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:7868.9-7868.13" + case + attribute \src "ls180.v:7869.6-7875.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7869.10-7869.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7871.10-7871.14" + case + attribute \src "ls180.v:7872.7-7874.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7872.11-7872.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:7879.5-7889.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:7879.9-7879.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:7881.9-7881.13" + case + attribute \src "ls180.v:7882.6-7888.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7882.10-7882.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7884.10-7884.14" + case + attribute \src "ls180.v:7885.7-7887.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7885.11-7885.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:7892.5-7902.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:7892.9-7892.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:7894.9-7894.13" + case + attribute \src "ls180.v:7895.6-7901.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:7895.10-7895.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:7897.10-7897.14" + case + attribute \src "ls180.v:7898.7-7900.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:7898.11-7898.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:7914.2-7928.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:7914.6-7914.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:7916.3-7920.6" + switch 1'1 + attribute \src "ls180.v:7916.7-7916.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:7921.6-7921.10" + case + attribute \src "ls180.v:7922.3-7927.6" + switch $not$ls180.v:7922$2510_Y + attribute \src "ls180.v:7922.7-7922.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7923$2511_Y + attribute \src "ls180.v:7924.4-7926.7" + switch $eq$ls180.v:7924$2512_Y + attribute \src "ls180.v:7924.8-7924.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7929.2-7943.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:7929.6-7929.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:7931.3-7935.6" + switch 1'0 + attribute \src "ls180.v:7933.7-7933.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7936.6-7936.10" + case + attribute \src "ls180.v:7937.3-7942.6" + switch $not$ls180.v:7937$2513_Y + attribute \src "ls180.v:7937.7-7937.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:7938$2514_Y + attribute \src "ls180.v:7939.4-7941.7" + switch $eq$ls180.v:7939$2515_Y + attribute \src "ls180.v:7939.8-7939.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7950.2-7952.5" + switch $or$ls180.v:7950$2540_Y + attribute \src "ls180.v:7950.6-7950.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:7954.2-7956.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:7954.6-7954.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:7957.2-7960.5" + switch \main_converter_reset + attribute \src "ls180.v:7957.6-7957.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7961.2-7971.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:7961.6-7961.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:7964.6-7964.10" + case + attribute \src "ls180.v:7965.3-7967.6" + switch $and$ls180.v:7965$2541_Y + attribute \src "ls180.v:7965.7-7965.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:7968.3-7970.6" + switch $and$ls180.v:7968$2542_Y + attribute \src "ls180.v:7968.7-7968.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:7973.2-7994.5" + switch $and$ls180.v:7973$2546_Y + attribute \src "ls180.v:7973.6-7973.91" + case 1'1 + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data + assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_tx_busy[0:0] 1'1 + assign $0\uart_tx[0:0] 1'0 + attribute \src "ls180.v:7978.6-7978.10" + case + attribute \src "ls180.v:7979.3-7993.6" + switch $and$ls180.v:7979$2547_Y + attribute \src "ls180.v:7979.7-7979.60" + case 1'1 + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:7980$2548_Y + attribute \src "ls180.v:7981.4-7992.7" + switch $eq$ls180.v:7981$2549_Y + attribute \src "ls180.v:7981.8-7981.43" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + attribute \src "ls180.v:7983.8-7983.12" + case + attribute \src "ls180.v:7984.5-7991.8" + switch $eq$ls180.v:7984$2550_Y + attribute \src "ls180.v:7984.9-7984.44" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:7988.9-7988.13" + case + assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] + assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:7995.2-7999.5" + switch \main_uart_phy_tx_busy + attribute \src "ls180.v:7995.6-7995.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:7996$2551_Y + attribute \src "ls180.v:7997.6-7997.10" + case + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + end + attribute \src "ls180.v:8002.2-8026.5" + switch $not$ls180.v:8002$2552_Y + attribute \src "ls180.v:8002.6-8002.30" + case 1'1 + attribute \src "ls180.v:8003.3-8006.6" + switch $and$ls180.v:8003$2554_Y + attribute \src "ls180.v:8003.7-8003.49" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:8007.6-8007.10" + case + attribute \src "ls180.v:8008.3-8025.6" + switch \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:8008.7-8008.34" + case 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8009$2555_Y + attribute \src "ls180.v:8010.4-8024.7" + switch $eq$ls180.v:8010$2556_Y + attribute \src "ls180.v:8010.8-8010.43" + case 1'1 + attribute \src "ls180.v:8011.5-8013.8" + switch \main_uart_phy_rx + attribute \src "ls180.v:8011.9-8011.25" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:8014.8-8014.12" + case + attribute \src "ls180.v:8015.5-8023.8" + switch $eq$ls180.v:8015$2557_Y + attribute \src "ls180.v:8015.9-8015.44" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:8017.6-8020.9" + switch \main_uart_phy_rx + attribute \src "ls180.v:8017.10-8017.26" + case 1'1 + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:8021.9-8021.13" + case + assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8027.2-8031.5" + switch \main_uart_phy_rx_busy + attribute \src "ls180.v:8027.6-8027.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8028$2558_Y + attribute \src "ls180.v:8029.6-8029.10" + case + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:8032.2-8034.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:8032.6-8032.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8036.2-8038.5" + switch $and$ls180.v:8036$2560_Y + attribute \src "ls180.v:8036.6-8036.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8039.2-8041.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:8039.6-8039.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8043.2-8045.5" + switch $and$ls180.v:8043$2562_Y + attribute \src "ls180.v:8043.6-8043.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8046.2-8052.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:8046.6-8046.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8048.6-8048.10" + case + attribute \src "ls180.v:8049.3-8051.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:8049.7-8049.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8053.2-8055.5" + switch $and$ls180.v:8053$2565_Y + attribute \src "ls180.v:8053.6-8053.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8054$2566_Y + case + end + attribute \src "ls180.v:8056.2-8058.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8056.6-8056.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8057$2567_Y + case + end + attribute \src "ls180.v:8059.2-8067.5" + switch $and$ls180.v:8059$2570_Y + attribute \src "ls180.v:8059.6-8059.108" + case 1'1 + attribute \src "ls180.v:8060.3-8062.6" + switch $not$ls180.v:8060$2571_Y + attribute \src "ls180.v:8060.7-8060.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8061$2572_Y + case + end + attribute \src "ls180.v:8063.6-8063.10" + case + attribute \src "ls180.v:8064.3-8066.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8064.7-8064.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8065$2573_Y + case + end + end + attribute \src "ls180.v:8068.2-8074.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8068.6-8068.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8070.6-8070.10" + case + attribute \src "ls180.v:8071.3-8073.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8071.7-8071.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8075.2-8077.5" + switch $and$ls180.v:8075$2576_Y + attribute \src "ls180.v:8075.6-8075.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8076$2577_Y + case + end + attribute \src "ls180.v:8078.2-8080.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8078.6-8078.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8079$2578_Y + case + end + attribute \src "ls180.v:8081.2-8089.5" + switch $and$ls180.v:8081$2581_Y + attribute \src "ls180.v:8081.6-8081.108" + case 1'1 + attribute \src "ls180.v:8082.3-8084.6" + switch $not$ls180.v:8082$2582_Y + attribute \src "ls180.v:8082.7-8082.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8083$2583_Y + case + end + attribute \src "ls180.v:8085.6-8085.10" + case + attribute \src "ls180.v:8086.3-8088.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8086.7-8086.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8087$2584_Y + case + end + end + attribute \src "ls180.v:8090.2-8103.5" + switch \main_uart_reset + attribute \src "ls180.v:8090.6-8090.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8105.2-8112.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8105.6-8105.31" + case 1'1 + assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable + attribute \src "ls180.v:8107.6-8107.10" + case + attribute \src "ls180.v:8108.3-8111.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8108.7-8108.32" + case 1'1 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8114.2-8124.5" + switch \main_spimaster28_mosi_latch + attribute \src "ls180.v:8114.6-8114.33" + case 1'1 + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi + assign $0\main_spimaster34_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8117.6-8117.10" + case + attribute \src "ls180.v:8118.3-8123.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8118.7-8118.32" + case 1'1 + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8122$2589_Y + attribute \src "ls180.v:8119.4-8121.7" + switch \main_spimaster26_cs_enable + attribute \src "ls180.v:8119.8-8119.34" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8125.2-8131.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8125.6-8125.31" + case 1'1 + attribute \src "ls180.v:8126.3-8130.6" + switch \main_spimaster7_loopback + attribute \src "ls180.v:8126.7-8126.31" + case 1'1 + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8128.7-8128.11" + case + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8132.2-8134.5" + switch \main_spimaster29_miso_latch + attribute \src "ls180.v:8132.6-8132.33" + case 1'1 + assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data + case + end + attribute \src "ls180.v:8136.2-8138.5" + switch \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:8136.6-8136.53" + case 1'1 + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8140.2-8147.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8140.6-8140.29" + case 1'1 + assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable + attribute \src "ls180.v:8142.6-8142.10" + case + attribute \src "ls180.v:8143.3-8146.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8143.7-8143.30" + case 1'1 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\spimaster_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8149.2-8159.5" + switch \main_spisdcard_mosi_latch + attribute \src "ls180.v:8149.6-8149.31" + case 1'1 + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi + assign $0\main_spisdcard_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8152.6-8152.10" + case + attribute \src "ls180.v:8153.3-8158.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8153.7-8153.30" + case 1'1 + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8157$2594_Y + attribute \src "ls180.v:8154.4-8156.7" + switch \main_spisdcard_cs_enable + attribute \src "ls180.v:8154.8-8154.32" + case 1'1 + assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8160.2-8166.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8160.6-8160.29" + case 1'1 + attribute \src "ls180.v:8161.3-8165.6" + switch \main_spisdcard_loopback + attribute \src "ls180.v:8161.7-8161.30" + case 1'1 + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } + attribute \src "ls180.v:8163.7-8163.11" + case + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } + end + case + end + attribute \src "ls180.v:8167.2-8169.5" + switch \main_spisdcard_miso_latch + attribute \src "ls180.v:8167.6-8167.31" + case 1'1 + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data + case + end + attribute \src "ls180.v:8171.2-8173.5" + switch \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:8171.6-8171.51" + case 1'1 + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8174.2-8187.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8174.6-8174.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8175$2595_Y + attribute \src "ls180.v:8176.3-8180.6" + switch $lt$ls180.v:8176$2596_Y + attribute \src "ls180.v:8176.7-8176.44" + case 1'1 + assign $0\pwm[1:0] [0] 1'1 + attribute \src "ls180.v:8178.7-8178.11" + case + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8181.3-8183.6" + switch $ge$ls180.v:8181$2598_Y + attribute \src "ls180.v:8181.7-8181.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8184.6-8184.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8188.2-8201.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8188.6-8188.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8189$2599_Y + attribute \src "ls180.v:8190.3-8194.6" + switch $lt$ls180.v:8190$2600_Y + attribute \src "ls180.v:8190.7-8190.44" + case 1'1 + assign $0\pwm[1:0] [1] 1'1 + attribute \src "ls180.v:8192.7-8192.11" + case + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8195.3-8197.6" + switch $ge$ls180.v:8195$2602_Y + attribute \src "ls180.v:8195.7-8195.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8198.6-8198.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8202.2-8204.5" + switch $not$ls180.v:8202$2603_Y + attribute \src "ls180.v:8202.6-8202.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8203$2604_Y + case + end + attribute \src "ls180.v:8208.2-8210.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8208.6-8208.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8212.2-8214.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8212.6-8212.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8215.2-8217.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8215.6-8215.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8216$2605_Y + case + end + attribute \src "ls180.v:8218.2-8220.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8218.6-8218.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8221.2-8228.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8221.6-8221.46" + case 1'1 + attribute \src "ls180.v:8222.3-8227.6" + switch $or$ls180.v:8222$2607_Y + attribute \src "ls180.v:8222.7-8222.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8225.7-8225.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8226$2608_Y + end + case + end + attribute \src "ls180.v:8229.2-8242.5" + switch $and$ls180.v:8229$2609_Y + attribute \src "ls180.v:8229.6-8229.97" + case 1'1 + attribute \src "ls180.v:8230.3-8236.6" + switch $and$ls180.v:8230$2610_Y + attribute \src "ls180.v:8230.7-8230.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8233.7-8233.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8237.6-8237.10" + case + attribute \src "ls180.v:8238.3-8241.6" + switch $and$ls180.v:8238$2611_Y + attribute \src "ls180.v:8238.7-8238.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8239$2612_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8240$2613_Y + case + end + end + attribute \src "ls180.v:8243.2-8270.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8243.6-8243.46" + case 1'1 + attribute \src "ls180.v:8244.3-8269.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8271.2-8273.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8271.6-8271.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8272$2614_Y + case + end + attribute \src "ls180.v:8274.2-8279.5" + switch $or$ls180.v:8274$2616_Y + attribute \src "ls180.v:8274.6-8274.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8280.2-8285.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8280.6-8280.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8287.2-8289.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8287.6-8287.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8290.2-8292.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8290.6-8290.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8293.2-8295.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8293.6-8293.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8296.2-8298.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8296.6-8296.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8297$2617_Y + case + end + attribute \src "ls180.v:8299.2-8301.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8299.6-8299.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8302.2-8309.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8302.6-8302.47" + case 1'1 + attribute \src "ls180.v:8303.3-8308.6" + switch $or$ls180.v:8303$2619_Y + attribute \src "ls180.v:8303.7-8303.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8306.7-8306.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8307$2620_Y + end + case + end + attribute \src "ls180.v:8310.2-8323.5" + switch $and$ls180.v:8310$2621_Y + attribute \src "ls180.v:8310.6-8310.99" + case 1'1 + attribute \src "ls180.v:8311.3-8317.6" + switch $and$ls180.v:8311$2622_Y + attribute \src "ls180.v:8311.7-8311.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8314.7-8314.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8318.6-8318.10" + case + attribute \src "ls180.v:8319.3-8322.6" + switch $and$ls180.v:8319$2623_Y + attribute \src "ls180.v:8319.7-8319.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8320$2624_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8321$2625_Y + case + end + end + attribute \src "ls180.v:8324.2-8351.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8324.6-8324.47" + case 1'1 + attribute \src "ls180.v:8325.3-8350.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8352.2-8354.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8352.6-8352.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8353$2626_Y + case + end + attribute \src "ls180.v:8355.2-8360.5" + switch $or$ls180.v:8355$2628_Y + attribute \src "ls180.v:8355.6-8355.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8361.2-8366.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8361.6-8361.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8368.2-8370.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8368.6-8368.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8372.2-8374.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8372.6-8372.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8375.2-8377.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8375.6-8375.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8376$2629_Y + case + end + attribute \src "ls180.v:8378.2-8380.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8378.6-8378.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8381.2-8388.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8381.6-8381.48" + case 1'1 + attribute \src "ls180.v:8382.3-8387.6" + switch $or$ls180.v:8382$2631_Y + attribute \src "ls180.v:8382.7-8382.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8385.7-8385.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8386$2632_Y + end + case + end + attribute \src "ls180.v:8389.2-8402.5" + switch $and$ls180.v:8389$2633_Y + attribute \src "ls180.v:8389.6-8389.101" + case 1'1 + attribute \src "ls180.v:8390.3-8396.6" + switch $and$ls180.v:8390$2634_Y + attribute \src "ls180.v:8390.7-8390.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8393.7-8393.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8397.6-8397.10" + case + attribute \src "ls180.v:8398.3-8401.6" + switch $and$ls180.v:8398$2635_Y + attribute \src "ls180.v:8398.7-8398.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8399$2636_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8400$2637_Y + case + end + end + attribute \src "ls180.v:8403.2-8412.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8403.6-8403.48" + case 1'1 + attribute \src "ls180.v:8404.3-8411.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8413.2-8415.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8413.6-8413.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8414$2638_Y + case + end + attribute \src "ls180.v:8416.2-8421.5" + switch $or$ls180.v:8416$2640_Y + attribute \src "ls180.v:8416.6-8416.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8422.2-8427.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8422.6-8422.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8429.2-8431.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8429.6-8429.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8432.2-8434.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8432.6-8432.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8435.2-8437.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8435.6-8435.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8438.2-8444.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8438.6-8438.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8440.6-8440.10" + case + attribute \src "ls180.v:8441.3-8443.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8441.7-8441.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8445.2-8451.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8445.6-8445.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8447.6-8447.10" + case + attribute \src "ls180.v:8448.3-8450.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8448.7-8448.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8452.2-8458.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8452.6-8452.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8454.6-8454.10" + case + attribute \src "ls180.v:8455.3-8457.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8455.7-8455.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8459.2-8465.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8459.6-8459.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8461.6-8461.10" + case + attribute \src "ls180.v:8462.3-8464.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8462.7-8462.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8466.2-8472.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8466.6-8466.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8468.6-8468.10" + case + attribute \src "ls180.v:8469.3-8471.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8469.7-8469.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8474.2-8476.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8474.6-8474.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8477.2-8479.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8477.6-8477.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8480.2-8482.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8480.6-8480.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8483.2-8485.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8483.6-8483.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8486.2-8488.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8486.6-8486.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8489.2-8491.5" + switch $and$ls180.v:8489$2641_Y + attribute \src "ls180.v:8489.6-8489.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8492.2-8494.5" + switch $and$ls180.v:8492$2642_Y + attribute \src "ls180.v:8492.6-8492.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8495.2-8497.5" + switch $and$ls180.v:8495$2643_Y + attribute \src "ls180.v:8495.6-8495.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8498.2-8500.5" + switch $and$ls180.v:8498$2644_Y + attribute \src "ls180.v:8498.6-8498.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8501.2-8505.5" + switch $and$ls180.v:8501$2645_Y + attribute \src "ls180.v:8501.6-8501.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8506.2-8510.5" + switch $and$ls180.v:8506$2646_Y + attribute \src "ls180.v:8506.6-8506.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8511.2-8515.5" + switch $and$ls180.v:8511$2647_Y + attribute \src "ls180.v:8511.6-8511.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8516.2-8520.5" + switch $and$ls180.v:8516$2648_Y + attribute \src "ls180.v:8516.6-8516.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8521.2-8529.5" + switch $and$ls180.v:8521$2649_Y + attribute \src "ls180.v:8521.6-8521.83" + case 1'1 + attribute \src "ls180.v:8522.3-8528.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8522.7-8522.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8524.7-8524.11" + case + attribute \src "ls180.v:8525.4-8527.7" + switch $ne$ls180.v:8525$2650_Y + attribute \src "ls180.v:8525.8-8525.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8526$2651_Y + case + end + end + case + end + attribute \src "ls180.v:8530.2-8536.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8530.6-8530.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8532.6-8532.10" + case + attribute \src "ls180.v:8533.3-8535.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8533.7-8533.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8537.2-8543.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8537.6-8537.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8539.6-8539.10" + case + attribute \src "ls180.v:8540.3-8542.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8540.7-8540.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8544.2-8550.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8544.6-8544.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8546.6-8546.10" + case + attribute \src "ls180.v:8547.3-8549.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8547.7-8547.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8551.2-8557.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8551.6-8551.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8553.6-8553.10" + case + attribute \src "ls180.v:8554.3-8556.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8554.7-8554.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8559.2-8561.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8559.6-8559.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8562.2-8564.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8562.6-8562.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8565.2-8567.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8565.6-8565.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8568.2-8570.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8568.6-8568.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8571.2-8573.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8571.6-8571.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8574.2-8576.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8574.6-8574.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8577.2-8579.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8577.6-8577.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8580.2-8582.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8580.6-8580.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8583.2-8585.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8583.6-8583.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8586.2-8588.5" + switch $and$ls180.v:8586$2654_Y + attribute \src "ls180.v:8586.6-8586.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8587$2655_Y + case + end + attribute \src "ls180.v:8589.2-8591.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8589.6-8589.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8590$2656_Y + case + end + attribute \src "ls180.v:8592.2-8600.5" + switch $and$ls180.v:8592$2659_Y + attribute \src "ls180.v:8592.6-8592.120" + case 1'1 + attribute \src "ls180.v:8593.3-8595.6" + switch $not$ls180.v:8593$2660_Y + attribute \src "ls180.v:8593.7-8593.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8594$2661_Y + case + end + attribute \src "ls180.v:8596.6-8596.10" + case + attribute \src "ls180.v:8597.3-8599.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8597.7-8597.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8598$2662_Y + case + end + end + attribute \src "ls180.v:8601.2-8603.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8601.6-8601.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8604.2-8611.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8604.6-8604.42" + case 1'1 + attribute \src "ls180.v:8605.3-8610.6" + switch $or$ls180.v:8605$2664_Y + attribute \src "ls180.v:8605.7-8605.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8608.7-8608.11" + case + assign $0\main_sdblock2mem_converter_demux[1:0] $add$ls180.v:8609$2665_Y + end + case + end + attribute \src "ls180.v:8612.2-8625.5" + switch $and$ls180.v:8612$2666_Y + attribute \src "ls180.v:8612.6-8612.89" + case 1'1 + attribute \src "ls180.v:8613.3-8619.6" + switch $and$ls180.v:8613$2667_Y + attribute \src "ls180.v:8613.7-8613.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8616.7-8616.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8620.6-8620.10" + case + attribute \src "ls180.v:8621.3-8624.6" + switch $and$ls180.v:8621$2668_Y + attribute \src "ls180.v:8621.7-8621.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8622$2669_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8623$2670_Y + case + end + end + attribute \src "ls180.v:8626.2-8641.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8626.6-8626.42" + case 1'1 + attribute \src "ls180.v:8627.3-8640.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_sdblock2mem_converter_source_payload_data[31:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8642.2-8644.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8642.6-8642.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$ls180.v:8643$2671_Y + case + end + attribute \src "ls180.v:8646.2-8648.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8646.6-8646.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8649.2-8652.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8649.6-8649.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8654.2-8656.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8654.6-8654.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[31:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8658.2-8660.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8658.6-8658.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8661.2-8664.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8661.6-8661.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8665.2-8671.5" + switch $and$ls180.v:8665$2672_Y + attribute \src "ls180.v:8665.6-8665.89" + case 1'1 + attribute \src "ls180.v:8666.3-8670.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8666.7-8666.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + attribute \src "ls180.v:8668.7-8668.11" + case + assign $0\main_sdmem2block_converter_mux[1:0] $add$ls180.v:8669$2673_Y + end + case + end + attribute \src "ls180.v:8672.2-8674.5" + switch $and$ls180.v:8672$2676_Y + attribute \src "ls180.v:8672.6-8672.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8673$2677_Y + case + end + attribute \src "ls180.v:8675.2-8677.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8675.6-8675.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8676$2678_Y + case + end + attribute \src "ls180.v:8678.2-8686.5" + switch $and$ls180.v:8678$2681_Y + attribute \src "ls180.v:8678.6-8678.120" + case 1'1 + attribute \src "ls180.v:8679.3-8681.6" + switch $not$ls180.v:8679$2682_Y + attribute \src "ls180.v:8679.7-8679.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8680$2683_Y + case + end + attribute \src "ls180.v:8682.6-8682.10" + case + attribute \src "ls180.v:8683.3-8685.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8683.7-8683.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8684$2684_Y + case + end + end + attribute \src "ls180.v:8688.2-8690.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8688.6-8688.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8691.2-8693.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8691.6-8691.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8694.2-8696.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8694.6-8694.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8697.2-8793.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8699.4-8715.7" + switch $not$ls180.v:8699$2685_Y + attribute \src "ls180.v:8699.8-8699.29" + case 1'1 + attribute \src "ls180.v:8700.5-8714.8" + switch \builder_request [1] + attribute \src "ls180.v:8700.9-8700.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8702.9-8702.13" + case + attribute \src "ls180.v:8703.6-8713.9" + switch \builder_request [2] + attribute \src "ls180.v:8703.10-8703.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8705.10-8705.14" + case + attribute \src "ls180.v:8706.7-8712.10" + switch \builder_request [3] + attribute \src "ls180.v:8706.11-8706.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8708.11-8708.15" + case + attribute \src "ls180.v:8709.8-8711.11" + switch \builder_request [4] + attribute \src "ls180.v:8709.12-8709.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:8718.4-8734.7" + switch $not$ls180.v:8718$2686_Y + attribute \src "ls180.v:8718.8-8718.29" + case 1'1 + attribute \src "ls180.v:8719.5-8733.8" + switch \builder_request [2] + attribute \src "ls180.v:8719.9-8719.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8721.9-8721.13" + case + attribute \src "ls180.v:8722.6-8732.9" + switch \builder_request [3] + attribute \src "ls180.v:8722.10-8722.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8724.10-8724.14" + case + attribute \src "ls180.v:8725.7-8731.10" + switch \builder_request [4] + attribute \src "ls180.v:8725.11-8725.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8727.11-8727.15" + case + attribute \src "ls180.v:8728.8-8730.11" + switch \builder_request [0] + attribute \src "ls180.v:8728.12-8728.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:8737.4-8753.7" + switch $not$ls180.v:8737$2687_Y + attribute \src "ls180.v:8737.8-8737.29" + case 1'1 + attribute \src "ls180.v:8738.5-8752.8" + switch \builder_request [3] + attribute \src "ls180.v:8738.9-8738.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8740.9-8740.13" + case + attribute \src "ls180.v:8741.6-8751.9" + switch \builder_request [4] + attribute \src "ls180.v:8741.10-8741.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8743.10-8743.14" + case + attribute \src "ls180.v:8744.7-8750.10" + switch \builder_request [0] + attribute \src "ls180.v:8744.11-8744.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8746.11-8746.15" + case + attribute \src "ls180.v:8747.8-8749.11" + switch \builder_request [1] + attribute \src "ls180.v:8747.12-8747.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:8756.4-8772.7" + switch $not$ls180.v:8756$2688_Y + attribute \src "ls180.v:8756.8-8756.29" + case 1'1 + attribute \src "ls180.v:8757.5-8771.8" + switch \builder_request [4] + attribute \src "ls180.v:8757.9-8757.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:8759.9-8759.13" + case + attribute \src "ls180.v:8760.6-8770.9" + switch \builder_request [0] + attribute \src "ls180.v:8760.10-8760.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8762.10-8762.14" + case + attribute \src "ls180.v:8763.7-8769.10" + switch \builder_request [1] + attribute \src "ls180.v:8763.11-8763.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8765.11-8765.15" + case + attribute \src "ls180.v:8766.8-8768.11" + switch \builder_request [2] + attribute \src "ls180.v:8766.12-8766.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:8775.4-8791.7" + switch $not$ls180.v:8775$2689_Y + attribute \src "ls180.v:8775.8-8775.29" + case 1'1 + attribute \src "ls180.v:8776.5-8790.8" + switch \builder_request [0] + attribute \src "ls180.v:8776.9-8776.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:8778.9-8778.13" + case + attribute \src "ls180.v:8779.6-8789.9" + switch \builder_request [1] + attribute \src "ls180.v:8779.10-8779.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8781.10-8781.14" + case + attribute \src "ls180.v:8782.7-8788.10" + switch \builder_request [2] + attribute \src "ls180.v:8782.11-8782.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8784.11-8784.15" + case + attribute \src "ls180.v:8785.8-8787.11" + switch \builder_request [3] + attribute \src "ls180.v:8785.12-8785.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:8795.2-8801.5" + switch \builder_wait + attribute \src "ls180.v:8795.6-8795.18" + case 1'1 + attribute \src "ls180.v:8796.3-8798.6" + switch $not$ls180.v:8796$2690_Y + attribute \src "ls180.v:8796.7-8796.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:8797$2691_Y + case + end + attribute \src "ls180.v:8799.6-8799.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:8803.2-8833.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:8803.6-8803.26" + case 1'1 + attribute \src "ls180.v:8804.3-8832.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:8834.2-8836.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:8834.6-8834.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:8838.2-8840.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:8838.6-8838.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:8841.2-8843.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:8841.6-8841.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:8844.2-8846.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:8844.6-8844.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:8847.2-8849.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:8847.6-8847.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:8852.2-8873.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:8852.6-8852.26" + case 1'1 + attribute \src "ls180.v:8853.3-8872.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:8874.2-8876.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:8874.6-8874.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:8877.2-8879.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:8877.6-8877.29" + case 1'1 + assign $0\main_gpio_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:8881.2-8883.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:8881.6-8881.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:8884.2-8886.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:8884.6-8884.30" + case 1'1 + assign $0\main_gpio_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:8889.2-8898.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:8889.6-8889.26" + case 1'1 + attribute \src "ls180.v:8890.3-8897.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } + case + end + case + end + attribute \src "ls180.v:8899.2-8901.5" + switch \builder_csrbank2_w0_re + attribute \src "ls180.v:8899.6-8899.28" + case 1'1 + assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r + case + end + attribute \src "ls180.v:8904.2-8934.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:8904.6-8904.26" + case 1'1 + attribute \src "ls180.v:8905.3-8933.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:8935.2-8937.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:8935.6-8935.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:8939.2-8941.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:8939.6-8939.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:8942.2-8944.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:8942.6-8942.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:8945.2-8947.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:8945.6-8945.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:8948.2-8950.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:8948.6-8948.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:8952.2-8954.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:8952.6-8952.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:8955.2-8957.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:8955.6-8955.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:8958.2-8960.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:8958.6-8958.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:8961.2-8963.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:8961.6-8961.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:8966.2-8996.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:8966.6-8966.26" + case 1'1 + attribute \src "ls180.v:8967.3-8995.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w + case + end + case + end + attribute \src "ls180.v:8997.2-8999.5" + switch \builder_csrbank4_enable0_re + attribute \src "ls180.v:8997.6-8997.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r + case + end + attribute \src "ls180.v:9001.2-9003.5" + switch \builder_csrbank4_width3_re + attribute \src "ls180.v:9001.6-9001.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r + case + end + attribute \src "ls180.v:9004.2-9006.5" + switch \builder_csrbank4_width2_re + attribute \src "ls180.v:9004.6-9004.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r + case + end + attribute \src "ls180.v:9007.2-9009.5" + switch \builder_csrbank4_width1_re + attribute \src "ls180.v:9007.6-9007.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r + case + end + attribute \src "ls180.v:9010.2-9012.5" + switch \builder_csrbank4_width0_re + attribute \src "ls180.v:9010.6-9010.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r + case + end + attribute \src "ls180.v:9014.2-9016.5" + switch \builder_csrbank4_period3_re + attribute \src "ls180.v:9014.6-9014.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r + case + end + attribute \src "ls180.v:9017.2-9019.5" + switch \builder_csrbank4_period2_re + attribute \src "ls180.v:9017.6-9017.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r + case + end + attribute \src "ls180.v:9020.2-9022.5" + switch \builder_csrbank4_period1_re + attribute \src "ls180.v:9020.6-9020.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r + case + end + attribute \src "ls180.v:9023.2-9025.5" + switch \builder_csrbank4_period0_re + attribute \src "ls180.v:9023.6-9023.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r + case + end + attribute \src "ls180.v:9028.2-9076.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9028.6-9028.26" + case 1'1 + attribute \src "ls180.v:9029.3-9075.10" + switch \builder_interface5_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:9077.2-9079.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:9077.6-9077.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r + case + end + attribute \src "ls180.v:9080.2-9082.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:9080.6-9080.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r + case + end + attribute \src "ls180.v:9083.2-9085.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:9083.6-9083.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r + case + end + attribute \src "ls180.v:9086.2-9088.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:9086.6-9086.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r + case + end + attribute \src "ls180.v:9089.2-9091.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:9089.6-9089.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r + case + end + attribute \src "ls180.v:9092.2-9094.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:9092.6-9092.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r + case + end + attribute \src "ls180.v:9095.2-9097.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:9095.6-9095.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r + case + end + attribute \src "ls180.v:9098.2-9100.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:9098.6-9098.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r + case + end + attribute \src "ls180.v:9102.2-9104.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:9102.6-9102.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r + case + end + attribute \src "ls180.v:9105.2-9107.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:9105.6-9105.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r + case + end + attribute \src "ls180.v:9108.2-9110.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:9108.6-9108.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r + case + end + attribute \src "ls180.v:9111.2-9113.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:9111.6-9111.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r + case + end + attribute \src "ls180.v:9115.2-9117.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:9115.6-9115.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r + case + end + attribute \src "ls180.v:9119.2-9121.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:9119.6-9119.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r + case + end + attribute \src "ls180.v:9124.2-9226.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9124.6-9124.26" + case 1'1 + attribute \src "ls180.v:9125.3-9225.10" + switch \builder_interface6_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w + case + end + case + end + attribute \src "ls180.v:9227.2-9229.5" + switch \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:9227.6-9227.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r + case + end + attribute \src "ls180.v:9230.2-9232.5" + switch \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:9230.6-9230.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r + case + end + attribute \src "ls180.v:9233.2-9235.5" + switch \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:9233.6-9233.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r + case + end + attribute \src "ls180.v:9236.2-9238.5" + switch \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:9236.6-9236.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r + case + end + attribute \src "ls180.v:9240.2-9242.5" + switch \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:9240.6-9240.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r + case + end + attribute \src "ls180.v:9243.2-9245.5" + switch \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:9243.6-9243.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r + case + end + attribute \src "ls180.v:9246.2-9248.5" + switch \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:9246.6-9246.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r + case + end + attribute \src "ls180.v:9249.2-9251.5" + switch \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:9249.6-9249.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r + case + end + attribute \src "ls180.v:9253.2-9255.5" + switch \builder_csrbank6_block_length1_re + attribute \src "ls180.v:9253.6-9253.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r + case + end + attribute \src "ls180.v:9256.2-9258.5" + switch \builder_csrbank6_block_length0_re + attribute \src "ls180.v:9256.6-9256.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r + case + end + attribute \src "ls180.v:9260.2-9262.5" + switch \builder_csrbank6_block_count3_re + attribute \src "ls180.v:9260.6-9260.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r + case + end + attribute \src "ls180.v:9263.2-9265.5" + switch \builder_csrbank6_block_count2_re + attribute \src "ls180.v:9263.6-9263.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r + case + end + attribute \src "ls180.v:9266.2-9268.5" + switch \builder_csrbank6_block_count1_re + attribute \src "ls180.v:9266.6-9266.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r + case + end + attribute \src "ls180.v:9269.2-9271.5" + switch \builder_csrbank6_block_count0_re + attribute \src "ls180.v:9269.6-9269.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r + case + end + attribute \src "ls180.v:9274.2-9334.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9274.6-9274.26" + case 1'1 + attribute \src "ls180.v:9275.3-9333.10" + switch \builder_interface7_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9335.2-9337.5" + switch \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:9335.6-9335.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r + case + end + attribute \src "ls180.v:9338.2-9340.5" + switch \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:9338.6-9338.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r + case + end + attribute \src "ls180.v:9341.2-9343.5" + switch \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:9341.6-9341.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r + case + end + attribute \src "ls180.v:9344.2-9346.5" + switch \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:9344.6-9344.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r + case + end + attribute \src "ls180.v:9347.2-9349.5" + switch \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:9347.6-9347.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r + case + end + attribute \src "ls180.v:9350.2-9352.5" + switch \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:9350.6-9350.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r + case + end + attribute \src "ls180.v:9353.2-9355.5" + switch \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:9353.6-9353.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r + case + end + attribute \src "ls180.v:9356.2-9358.5" + switch \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:9356.6-9356.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r + case + end + attribute \src "ls180.v:9360.2-9362.5" + switch \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:9360.6-9360.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r + case + end + attribute \src "ls180.v:9363.2-9365.5" + switch \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:9363.6-9363.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r + case + end + attribute \src "ls180.v:9366.2-9368.5" + switch \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:9366.6-9366.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r + case + end + attribute \src "ls180.v:9369.2-9371.5" + switch \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:9369.6-9369.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r + case + end + attribute \src "ls180.v:9373.2-9375.5" + switch \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:9373.6-9373.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r + case + end + attribute \src "ls180.v:9377.2-9379.5" + switch \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:9377.6-9377.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r + case + end + attribute \src "ls180.v:9382.2-9397.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9382.6-9382.26" + case 1'1 + attribute \src "ls180.v:9383.3-9396.10" + switch \builder_interface8_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9398.2-9400.5" + switch \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:9398.6-9398.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r + case + end + attribute \src "ls180.v:9401.2-9403.5" + switch \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:9401.6-9401.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + case + end + attribute \src "ls180.v:9406.2-9439.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9406.6-9406.26" + case 1'1 + attribute \src "ls180.v:9407.3-9438.10" + switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9440.2-9442.5" + switch \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:9440.6-9440.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r + case + end + attribute \src "ls180.v:9444.2-9446.5" + switch \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:9444.6-9444.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9448.2-9450.5" + switch \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:9448.6-9448.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9451.2-9453.5" + switch \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:9451.6-9451.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9455.2-9457.5" + switch \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:9455.6-9455.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9459.2-9461.5" + switch \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9459.6-9459.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9462.2-9464.5" + switch \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9462.6-9462.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9467.2-9491.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9467.6-9467.27" + case 1'1 + attribute \src "ls180.v:9468.3-9490.10" + switch \builder_interface10_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9492.2-9494.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9492.6-9492.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9495.2-9497.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9495.6-9495.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9499.2-9501.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9499.6-9499.32" + case 1'1 + assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9503.2-9505.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9503.6-9503.30" + case 1'1 + assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9507.2-9509.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9507.6-9507.36" + case 1'1 + assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9512.2-9542.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9512.6-9512.27" + case 1'1 + attribute \src "ls180.v:9513.3-9541.10" + switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9543.2-9545.5" + switch \builder_csrbank11_control1_re + attribute \src "ls180.v:9543.6-9543.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + case + end + attribute \src "ls180.v:9546.2-9548.5" + switch \builder_csrbank11_control0_re + attribute \src "ls180.v:9546.6-9546.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + case + end + attribute \src "ls180.v:9550.2-9552.5" + switch \builder_csrbank11_mosi0_re + attribute \src "ls180.v:9550.6-9550.32" + case 1'1 + assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r + case + end + attribute \src "ls180.v:9554.2-9556.5" + switch \builder_csrbank11_cs0_re + attribute \src "ls180.v:9554.6-9554.30" + case 1'1 + assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r + case + end + attribute \src "ls180.v:9558.2-9560.5" + switch \builder_csrbank11_loopback0_re + attribute \src "ls180.v:9558.6-9558.36" + case 1'1 + assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r + case + end + attribute \src "ls180.v:9562.2-9564.5" + switch \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:9562.6-9562.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + case + end + attribute \src "ls180.v:9565.2-9567.5" + switch \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:9565.6-9565.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + case + end + attribute \src "ls180.v:9570.2-9624.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9570.6-9570.27" + case 1'1 + attribute \src "ls180.v:9571.3-9623.10" + switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9625.2-9627.5" + switch \builder_csrbank12_load3_re + attribute \src "ls180.v:9625.6-9625.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + case + end + attribute \src "ls180.v:9628.2-9630.5" + switch \builder_csrbank12_load2_re + attribute \src "ls180.v:9628.6-9628.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + case + end + attribute \src "ls180.v:9631.2-9633.5" + switch \builder_csrbank12_load1_re + attribute \src "ls180.v:9631.6-9631.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + case + end + attribute \src "ls180.v:9634.2-9636.5" + switch \builder_csrbank12_load0_re + attribute \src "ls180.v:9634.6-9634.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + case + end + attribute \src "ls180.v:9638.2-9640.5" + switch \builder_csrbank12_reload3_re + attribute \src "ls180.v:9638.6-9638.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + case + end + attribute \src "ls180.v:9641.2-9643.5" + switch \builder_csrbank12_reload2_re + attribute \src "ls180.v:9641.6-9641.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + case + end + attribute \src "ls180.v:9644.2-9646.5" + switch \builder_csrbank12_reload1_re + attribute \src "ls180.v:9644.6-9644.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + case + end + attribute \src "ls180.v:9647.2-9649.5" + switch \builder_csrbank12_reload0_re + attribute \src "ls180.v:9647.6-9647.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + case + end + attribute \src "ls180.v:9651.2-9653.5" + switch \builder_csrbank12_en0_re + attribute \src "ls180.v:9651.6-9651.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + case + end + attribute \src "ls180.v:9655.2-9657.5" + switch \builder_csrbank12_update_value0_re + attribute \src "ls180.v:9655.6-9655.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + case + end + attribute \src "ls180.v:9659.2-9661.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9659.6-9659.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9664.2-9691.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9664.6-9664.27" + case 1'1 + attribute \src "ls180.v:9665.3-9690.10" + switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9692.2-9694.5" + switch \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:9692.6-9692.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + case + end + attribute \src "ls180.v:9697.2-9712.5" + switch \builder_csrbank14_sel + attribute \src "ls180.v:9697.6-9697.27" + case 1'1 + attribute \src "ls180.v:9698.3-9711.10" + switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:9713.2-9715.5" + switch \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:9713.6-9713.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + case + end + attribute \src "ls180.v:9716.2-9718.5" + switch \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:9716.6-9716.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + case + end + attribute \src "ls180.v:9719.2-9721.5" + switch \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:9719.6-9719.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + case + end + attribute \src "ls180.v:9722.2-9724.5" + switch \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:9722.6-9722.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + case + end + attribute \src "ls180.v:9726.2-10020.5" + switch \sys_rst_1 + attribute \src "ls180.v:9726.6-9726.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 + assign $0\pwm[1:0] 2'00 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_libresocsim_converter2_counter[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_uart_phy_storage[31:0] 9895604 + assign $0\main_uart_phy_re[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpio_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_oe_re[0:0] 1'0 + assign $0\main_gpio_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpio_out_re[0:0] 1'0 + assign $0\main_spimaster5_miso[7:0] 8'00000000 + assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 + assign $0\main_spimaster12_re[0:0] 1'0 + assign $0\main_spimaster17_re[0:0] 1'0 + assign $0\main_spimaster21_storage[0:0] 1'1 + assign $0\main_spimaster22_re[0:0] 1'0 + assign $0\main_spimaster23_storage[0:0] 1'0 + assign $0\main_spimaster24_re[0:0] 1'0 + assign $0\main_spimaster27_count[2:0] 3'000 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 + assign $0\main_spimaster34_mosi_sel[2:0] 3'000 + assign $0\main_spimaster35_miso_data[7:0] 8'00000000 + assign $0\main_spisdcard_miso[7:0] 8'00000000 + assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 + assign $0\main_spisdcard_control_re[0:0] 1'0 + assign $0\main_spisdcard_mosi_re[0:0] 1'0 + assign $0\main_spisdcard_cs_storage[0:0] 1'1 + assign $0\main_spisdcard_cs_re[0:0] 1'0 + assign $0\main_spisdcard_loopback_storage[0:0] 1'0 + assign $0\main_spisdcard_loopback_re[0:0] 1'0 + assign $0\main_spisdcard_count[2:0] 3'000 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 + assign $0\main_spisdcard_mosi_sel[2:0] 3'000 + assign $0\main_spisdcard_miso_data[7:0] 8'00000000 + assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 + assign $0\main_spimaster1_re[0:0] 1'0 + assign $0\main_dummy[35:0] 36'000000000000000000000000000000000000 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_i2c_storage[2:0] 3'000 + assign $0\main_i2c_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[31:0] 0 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[1:0] 2'00 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] + update \pwm $0\pwm[1:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] + update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] + update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] + update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] + update \main_libresocsim_converter2_counter $0\main_libresocsim_converter2_counter[0:0] + update \main_libresocsim_converter2_dat_r $0\main_libresocsim_converter2_dat_r[63:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] + update \main_uart_phy_re $0\main_uart_phy_re[0:0] + update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] + update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] + update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] + update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] + update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] + update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpio_oe_storage $0\main_gpio_oe_storage[15:0] + update \main_gpio_oe_re $0\main_gpio_oe_re[0:0] + update \main_gpio_out_storage $0\main_gpio_out_storage[15:0] + update \main_gpio_out_re $0\main_gpio_out_re[0:0] + update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] + update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] + update \main_spimaster12_re $0\main_spimaster12_re[0:0] + update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] + update \main_spimaster17_re $0\main_spimaster17_re[0:0] + update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] + update \main_spimaster22_re $0\main_spimaster22_re[0:0] + update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] + update \main_spimaster24_re $0\main_spimaster24_re[0:0] + update \main_spimaster27_count $0\main_spimaster27_count[2:0] + update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] + update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] + update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] + update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] + update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] + update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] + update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] + update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] + update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] + update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] + update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] + update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] + update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] + update \main_spisdcard_count $0\main_spisdcard_count[2:0] + update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] + update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] + update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] + update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] + update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] + update \main_spimaster1_re $0\main_spimaster1_re[0:0] + update \main_dummy $0\main_dummy[35:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_i2c_storage $0\main_i2c_storage[2:0] + update \main_i2c_re $0\main_i2c_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[31:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[1:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[31:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[1:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $pos$libresoc.v:185111$13281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:185111$13280_Y - connect \Y $pos$libresoc.v:185111$13281_Y + attribute \src "ls180.v:745.5-745.43" + process $proc$ls180.v:745$3052 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:185131$13301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$56 - connect \Y $reduce_or$libresoc.v:185131$13301_Y + attribute \src "ls180.v:748.5-748.49" + process $proc$ls180.v:748$3053 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] end - attribute \src "libresoc.v:185106.19-185106.42" - cell $shr $shr$libresoc.v:185106$13274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$120 - connect \Y $shr$libresoc.v:185106$13274_Y + attribute \src "ls180.v:749.5-749.49" + process $proc$ls180.v:749$3054 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "libresoc.v:185108.19-185108.42" - cell $shr $shr$libresoc.v:185108$13276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \imem_f_instr_o - connect \B \$124 - connect \Y $shr$libresoc.v:185108$13276_Y + attribute \src "ls180.v:750.5-750.48" + process $proc$ls180.v:750$3055 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:392" - cell $sub $sub$libresoc.v:185112$13282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o - connect \B 1'1 - connect \Y $sub$libresoc.v:185112$13282_Y + attribute \src "ls180.v:754.11-754.46" + process $proc$ls180.v:754$3056 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" - cell $sub $sub$libresoc.v:185115$13285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \delay - connect \B 1'1 - connect \Y $sub$libresoc.v:185115$13285_Y + attribute \src "ls180.v:756.11-756.45" + process $proc$ls180.v:756$3057 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:185324.8-185417.4" - cell \core \core - connect \bigendian_i \core_bigendian_i$10 - connect \cia__data_o \core_cia__data_o - connect \cia__ren \core_cia__ren - connect \core_core_cia \core_core_core_cia - connect \core_core_cr_rd \core_core_core_cr_rd - connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok - connect \core_core_cr_wr \core_core_core_cr_wr - connect \core_core_exc_$signal \core_core_core_exc_$signal - connect \core_core_exc_$signal$3 \core_core_core_exc_$signal$3 - connect \core_core_exc_$signal$4 \core_core_core_exc_$signal$4 - connect \core_core_exc_$signal$5 \core_core_core_exc_$signal$5 - connect \core_core_exc_$signal$6 \core_core_core_exc_$signal$6 - connect \core_core_exc_$signal$7 \core_core_core_exc_$signal$7 - connect \core_core_exc_$signal$8 \core_core_core_exc_$signal$8 - connect \core_core_exc_$signal$9 \core_core_core_exc_$signal$9 - connect \core_core_fn_unit \core_core_core_fn_unit - connect \core_core_input_carry \core_core_core_input_carry - connect \core_core_insn \core_core_core_insn - connect \core_core_insn_type \core_core_core_insn_type - connect \core_core_is_32bit \core_core_core_is_32bit - connect \core_core_msr \core_core_core_msr - connect \core_core_oe \core_core_core_oe - connect \core_core_oe_ok \core_core_core_oe_ok - connect \core_core_rc \core_core_core_rc - connect \core_core_rc_ok \core_core_core_rc_ok - connect \core_core_trapaddr \core_core_core_trapaddr - connect \core_core_traptype \core_core_core_traptype - connect \core_cr_in1 \core_core_cr_in1 - connect \core_cr_in1_ok \core_core_cr_in1_ok - connect \core_cr_in2 \core_core_cr_in2 - connect \core_cr_in2$1 \core_core_cr_in2$1 - connect \core_cr_in2_ok \core_core_cr_in2_ok - connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 - connect \core_cr_out \core_core_cr_out - connect \core_ea \core_core_ea - connect \core_fast1 \core_core_fast1 - connect \core_fast1_ok \core_core_fast1_ok - connect \core_fast2 \core_core_fast2 - connect \core_fast2_ok \core_core_fast2_ok - connect \core_fasto1 \core_core_fasto1 - connect \core_fasto2 \core_core_fasto2 - connect \core_pc \core_core_pc - connect \core_reg1 \core_core_reg1 - connect \core_reg1_ok \core_core_reg1_ok - connect \core_reg2 \core_core_reg2 - connect \core_reg2_ok \core_core_reg2_ok - connect \core_reg3 \core_core_reg3 - connect \core_reg3_ok \core_core_reg3_ok - connect \core_rego \core_core_rego - connect \core_spr1 \core_core_spr1 - connect \core_spr1_ok \core_core_spr1_ok - connect \core_spro \core_core_spro - connect \core_terminate_o \core_core_terminate_o - connect \core_xer_in \core_core_xer_in - connect \corebusy_o \core_corebusy_o - connect \coresync_clk \coresync_clk - connect \coresync_rst \core_coresync_rst - connect \cu_ad__go_i \core_cu_ad__go_i - connect \cu_ad__rel_o \core_cu_ad__rel_o - connect \cu_st__go_i \core_cu_st__go_i - connect \cu_st__rel_o \core_cu_st__rel_o - connect \data_i \core_data_i - connect \dbus__ack \dbus__ack - connect \dbus__adr \dbus__adr - connect \dbus__cyc \dbus__cyc - connect \dbus__dat_r \dbus__dat_r - connect \dbus__dat_w \dbus__dat_w - connect \dbus__err \dbus__err - connect \dbus__sel \dbus__sel - connect \dbus__stb \dbus__stb - connect \dbus__we \dbus__we - connect \dmi__addr \core_dmi__addr - connect \dmi__data_o \core_dmi__data_o - connect \dmi__ren \core_dmi__ren - connect \full_rd2__data_o \core_full_rd2__data_o - connect \full_rd2__ren \core_full_rd2__ren - connect \full_rd__data_o \core_full_rd__data_o - connect \full_rd__ren \core_full_rd__ren - connect \issue__addr \core_issue__addr - connect \issue__addr$10 \core_issue__addr$11 - connect \issue__data_i \core_issue__data_i - connect \issue__data_o \core_issue__data_o - connect \issue__ren \core_issue__ren - connect \issue__wen \core_issue__wen - connect \issue_i \core_issue_i - connect \ivalid_i \core_ivalid_i - connect \msr__data_o \core_msr__data_o - connect \msr__ren \core_msr__ren - connect \raw_insn_i \core_raw_insn_i - connect \state_nia_wen \core_state_nia_wen - connect \wb_dcache_en \core_wb_dcache_en - connect \wen \core_wen + attribute \src "ls180.v:758.5-758.44" + process $proc$ls180.v:758$3058 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:185418.7-185443.4" - cell \dbg \dbg - connect \clk \clk - connect \core_dbg_msr \dbg_core_dbg_msr - connect \core_dbg_pc \dbg_core_dbg_pc - connect \core_rst_o \dbg_core_rst_o - connect \core_stop_o \dbg_core_stop_o - connect \core_stopped_i \dbg_core_stopped_i - connect \d_cr_ack \dbg_d_cr_ack - connect \d_cr_data \dbg_d_cr_data - connect \d_cr_req \dbg_d_cr_req - connect \d_gpr_ack \dbg_d_gpr_ack - connect \d_gpr_addr \dbg_d_gpr_addr - connect \d_gpr_data \dbg_d_gpr_data - connect \d_gpr_req \dbg_d_gpr_req - connect \d_xer_ack \dbg_d_xer_ack - connect \d_xer_data \dbg_d_xer_data - connect \d_xer_req \dbg_d_xer_req - connect \dmi_ack_o \dbg_dmi_ack_o - connect \dmi_addr_i \dbg_dmi_addr_i - connect \dmi_din \dbg_dmi_din - connect \dmi_dout \dbg_dmi_dout - connect \dmi_req_i \dbg_dmi_req_i - connect \dmi_we_i \dbg_dmi_we_i - connect \rst \rst - connect \terminate_i \dbg_terminate_i + attribute \src "ls180.v:759.5-759.45" + process $proc$ls180.v:759$3059 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:185444.8-185510.4" - cell \dec2 \dec2 - connect \asmcode \dec2_asmcode - connect \bigendian \dec2_bigendian - connect \cia \dec2_cia - connect \cr_in1 \dec2_cr_in1 - connect \cr_in1_ok \dec2_cr_in1_ok - connect \cr_in2 \dec2_cr_in2 - connect \cr_in2$1 \dec2_cr_in2$12 - connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2_ok$2 \dec2_cr_in2_ok$13 - connect \cr_out \dec2_cr_out - connect \cr_out_ok \dec2_cr_out_ok - connect \cr_rd \dec2_cr_rd - connect \cr_rd_ok \dec2_cr_rd_ok - connect \cr_wr \dec2_cr_wr - connect \cr_wr_ok \dec2_cr_wr_ok - connect \cur_dec \dec2_cur_dec - connect \cur_eint \dec2_cur_eint - connect \cur_msr \dec2_cur_msr - connect \cur_pc \dec2_cur_pc - connect \ea \dec2_ea - connect \ea_ok \dec2_ea_ok - connect \exc_$signal \dec2_exc_$signal - connect \exc_$signal$3 \dec2_exc_$signal$14 - connect \exc_$signal$4 \dec2_exc_$signal$15 - connect \exc_$signal$5 \dec2_exc_$signal$16 - connect \exc_$signal$6 \dec2_exc_$signal$17 - connect \exc_$signal$7 \dec2_exc_$signal$18 - connect \exc_$signal$8 \dec2_exc_$signal$19 - connect \exc_$signal$9 \dec2_exc_$signal$20 - connect \fast1 \dec2_fast1 - connect \fast1_ok \dec2_fast1_ok - connect \fast2 \dec2_fast2 - connect \fast2_ok \dec2_fast2_ok - connect \fasto1 \dec2_fasto1 - connect \fasto1_ok \dec2_fasto1_ok - connect \fasto2 \dec2_fasto2 - connect \fasto2_ok \dec2_fasto2_ok - connect \fn_unit \dec2_fn_unit - connect \input_carry \dec2_input_carry - connect \insn \dec2_insn - connect \insn_type \dec2_insn_type - connect \is_32bit \dec2_is_32bit - connect \lk \dec2_lk - connect \msr \dec2_msr - connect \oe \dec2_oe - connect \oe_ok \dec2_oe_ok - connect \raw_opcode_in \dec2_raw_opcode_in - connect \rc \dec2_rc - connect \rc_ok \dec2_rc_ok - connect \reg1 \dec2_reg1 - connect \reg1_ok \dec2_reg1_ok - connect \reg2 \dec2_reg2 - connect \reg2_ok \dec2_reg2_ok - connect \reg3 \dec2_reg3 - connect \reg3_ok \dec2_reg3_ok - connect \rego \dec2_rego - connect \rego_ok \dec2_rego_ok - connect \spr1 \dec2_spr1 - connect \spr1_ok \dec2_spr1_ok - connect \spro \dec2_spro - connect \spro_ok \dec2_spro_ok - connect \trapaddr \dec2_trapaddr - connect \traptype \dec2_traptype - connect \xer_in \dec2_xer_in - connect \xer_out \dec2_xer_out + attribute \src "ls180.v:76.5-76.46" + process $proc$ls180.v:76$2782 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + sync init end - attribute \module_not_derived 1 - attribute \src "libresoc.v:185511.8-185527.4" - cell \imem \imem - connect \a_pc_i \imem_a_pc_i - connect \a_valid_i \imem_a_valid_i - connect \clk \clk - connect \f_busy_o \imem_f_busy_o - connect \f_instr_o \imem_f_instr_o - connect \f_valid_i \imem_f_valid_i - connect \ibus__ack \ibus__ack - connect \ibus__adr \ibus__adr - connect \ibus__cyc \ibus__cyc - connect \ibus__dat_r \ibus__dat_r - connect \ibus__err \ibus__err - connect \ibus__sel \ibus__sel - connect \ibus__stb \ibus__stb - connect \rst \rst - connect \wb_icache_en \imem_wb_icache_en + attribute \src "ls180.v:761.5-761.48" + process $proc$ls180.v:761$3060 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:185528.8-185859.4" - cell \jtag \jtag - connect \TAP_bus__tck \TAP_bus__tck - connect \TAP_bus__tdi \TAP_bus__tdi - connect \TAP_bus__tdo \TAP_bus__tdo - connect \TAP_bus__tms \TAP_bus__tms - connect \clk \clk - connect \dmi0__ack_o \jtag_dmi0__ack_o - connect \dmi0__addr_i \jtag_dmi0__addr_i - connect \dmi0__din \jtag_dmi0__din - connect \dmi0__dout \jtag_dmi0__dout - connect \dmi0__req_i \jtag_dmi0__req_i - connect \dmi0__we_i \jtag_dmi0__we_i - connect \eint_0__core__i \eint_0__core__i - connect \eint_0__pad__i \eint_0__pad__i - connect \eint_1__core__i \eint_1__core__i - connect \eint_1__pad__i \eint_1__pad__i - connect \eint_2__core__i \eint_2__core__i - connect \eint_2__pad__i \eint_2__pad__i - connect \gpio_e10__core__i \gpio_e10__core__i - connect \gpio_e10__core__o \gpio_e10__core__o - connect \gpio_e10__core__oe \gpio_e10__core__oe - connect \gpio_e10__pad__i \gpio_e10__pad__i - connect \gpio_e10__pad__o \gpio_e10__pad__o - connect \gpio_e10__pad__oe \gpio_e10__pad__oe - connect \gpio_e11__core__i \gpio_e11__core__i - connect \gpio_e11__core__o \gpio_e11__core__o - connect \gpio_e11__core__oe \gpio_e11__core__oe - connect \gpio_e11__pad__i \gpio_e11__pad__i - connect \gpio_e11__pad__o \gpio_e11__pad__o - connect \gpio_e11__pad__oe \gpio_e11__pad__oe - connect \gpio_e12__core__i \gpio_e12__core__i - connect \gpio_e12__core__o \gpio_e12__core__o - connect \gpio_e12__core__oe \gpio_e12__core__oe - connect \gpio_e12__pad__i \gpio_e12__pad__i - connect \gpio_e12__pad__o \gpio_e12__pad__o - connect \gpio_e12__pad__oe \gpio_e12__pad__oe - connect \gpio_e13__core__i \gpio_e13__core__i - connect \gpio_e13__core__o \gpio_e13__core__o - connect \gpio_e13__core__oe \gpio_e13__core__oe - connect \gpio_e13__pad__i \gpio_e13__pad__i - connect \gpio_e13__pad__o \gpio_e13__pad__o - connect \gpio_e13__pad__oe \gpio_e13__pad__oe - connect \gpio_e14__core__i \gpio_e14__core__i - connect \gpio_e14__core__o \gpio_e14__core__o - connect \gpio_e14__core__oe \gpio_e14__core__oe - connect \gpio_e14__pad__i \gpio_e14__pad__i - connect \gpio_e14__pad__o \gpio_e14__pad__o - connect \gpio_e14__pad__oe \gpio_e14__pad__oe - connect \gpio_e15__core__i \gpio_e15__core__i - connect \gpio_e15__core__o \gpio_e15__core__o - connect \gpio_e15__core__oe \gpio_e15__core__oe - connect \gpio_e15__pad__i \gpio_e15__pad__i - connect \gpio_e15__pad__o \gpio_e15__pad__o - connect \gpio_e15__pad__oe \gpio_e15__pad__oe - connect \gpio_e8__core__i \gpio_e8__core__i - connect \gpio_e8__core__o \gpio_e8__core__o - connect \gpio_e8__core__oe \gpio_e8__core__oe - connect \gpio_e8__pad__i \gpio_e8__pad__i - connect \gpio_e8__pad__o \gpio_e8__pad__o - connect \gpio_e8__pad__oe \gpio_e8__pad__oe - connect \gpio_e9__core__i \gpio_e9__core__i - connect \gpio_e9__core__o \gpio_e9__core__o - connect \gpio_e9__core__oe \gpio_e9__core__oe - connect \gpio_e9__pad__i \gpio_e9__pad__i - connect \gpio_e9__pad__o \gpio_e9__pad__o - connect \gpio_e9__pad__oe \gpio_e9__pad__oe - connect \gpio_s0__core__i \gpio_s0__core__i - connect \gpio_s0__core__o \gpio_s0__core__o - connect \gpio_s0__core__oe \gpio_s0__core__oe - connect \gpio_s0__pad__i \gpio_s0__pad__i - connect \gpio_s0__pad__o \gpio_s0__pad__o - connect \gpio_s0__pad__oe \gpio_s0__pad__oe - connect \gpio_s1__core__i \gpio_s1__core__i - connect \gpio_s1__core__o \gpio_s1__core__o - connect \gpio_s1__core__oe \gpio_s1__core__oe - connect \gpio_s1__pad__i \gpio_s1__pad__i - connect \gpio_s1__pad__o \gpio_s1__pad__o - connect \gpio_s1__pad__oe \gpio_s1__pad__oe - connect \gpio_s2__core__i \gpio_s2__core__i - connect \gpio_s2__core__o \gpio_s2__core__o - connect \gpio_s2__core__oe \gpio_s2__core__oe - connect \gpio_s2__pad__i \gpio_s2__pad__i - connect \gpio_s2__pad__o \gpio_s2__pad__o - connect \gpio_s2__pad__oe \gpio_s2__pad__oe - connect \gpio_s3__core__i \gpio_s3__core__i - connect \gpio_s3__core__o \gpio_s3__core__o - connect \gpio_s3__core__oe \gpio_s3__core__oe - connect \gpio_s3__pad__i \gpio_s3__pad__i - connect \gpio_s3__pad__o \gpio_s3__pad__o - connect \gpio_s3__pad__oe \gpio_s3__pad__oe - connect \gpio_s4__core__i \gpio_s4__core__i - connect \gpio_s4__core__o \gpio_s4__core__o - connect \gpio_s4__core__oe \gpio_s4__core__oe - connect \gpio_s4__pad__i \gpio_s4__pad__i - connect \gpio_s4__pad__o \gpio_s4__pad__o - connect \gpio_s4__pad__oe \gpio_s4__pad__oe - connect \gpio_s5__core__i \gpio_s5__core__i - connect \gpio_s5__core__o \gpio_s5__core__o - connect \gpio_s5__core__oe \gpio_s5__core__oe - connect \gpio_s5__pad__i \gpio_s5__pad__i - connect \gpio_s5__pad__o \gpio_s5__pad__o - connect \gpio_s5__pad__oe \gpio_s5__pad__oe - connect \gpio_s6__core__i \gpio_s6__core__i - connect \gpio_s6__core__o \gpio_s6__core__o - connect \gpio_s6__core__oe \gpio_s6__core__oe - connect \gpio_s6__pad__i \gpio_s6__pad__i - connect \gpio_s6__pad__o \gpio_s6__pad__o - connect \gpio_s6__pad__oe \gpio_s6__pad__oe - connect \gpio_s7__core__i \gpio_s7__core__i - connect \gpio_s7__core__o \gpio_s7__core__o - connect \gpio_s7__core__oe \gpio_s7__core__oe - connect \gpio_s7__pad__i \gpio_s7__pad__i - connect \gpio_s7__pad__o \gpio_s7__pad__o - connect \gpio_s7__pad__oe \gpio_s7__pad__oe - connect \jtag_wb__ack \jtag_wb__ack - connect \jtag_wb__adr \jtag_wb__adr - connect \jtag_wb__cyc \jtag_wb__cyc - connect \jtag_wb__dat_r \jtag_wb__dat_r - connect \jtag_wb__dat_w \jtag_wb__dat_w - connect \jtag_wb__sel \jtag_wb__sel - connect \jtag_wb__stb \jtag_wb__stb - connect \jtag_wb__we \jtag_wb__we - connect \mspi0_clk__core__o \mspi0_clk__core__o - connect \mspi0_clk__pad__o \mspi0_clk__pad__o - connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o - connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o - connect \mspi0_miso__core__i \mspi0_miso__core__i - connect \mspi0_miso__pad__i \mspi0_miso__pad__i - connect \mspi0_mosi__core__o \mspi0_mosi__core__o - connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o - connect \mtwi_scl__core__o \mtwi_scl__core__o - connect \mtwi_scl__pad__o \mtwi_scl__pad__o - connect \mtwi_sda__core__i \mtwi_sda__core__i - connect \mtwi_sda__core__o \mtwi_sda__core__o - connect \mtwi_sda__core__oe \mtwi_sda__core__oe - connect \mtwi_sda__pad__i \mtwi_sda__pad__i - connect \mtwi_sda__pad__o \mtwi_sda__pad__o - connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o - connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe - connect \sdr_a_0__core__o \sdr_a_0__core__o - connect \sdr_a_0__pad__o \sdr_a_0__pad__o - connect \sdr_a_10__core__o \sdr_a_10__core__o - connect \sdr_a_10__pad__o \sdr_a_10__pad__o - connect \sdr_a_11__core__o \sdr_a_11__core__o - connect \sdr_a_11__pad__o \sdr_a_11__pad__o - connect \sdr_a_12__core__o \sdr_a_12__core__o - connect \sdr_a_12__pad__o \sdr_a_12__pad__o - connect \sdr_a_1__core__o \sdr_a_1__core__o - connect \sdr_a_1__pad__o \sdr_a_1__pad__o - connect \sdr_a_2__core__o \sdr_a_2__core__o - connect \sdr_a_2__pad__o \sdr_a_2__pad__o - connect \sdr_a_3__core__o \sdr_a_3__core__o - connect \sdr_a_3__pad__o \sdr_a_3__pad__o - connect \sdr_a_4__core__o \sdr_a_4__core__o - connect \sdr_a_4__pad__o \sdr_a_4__pad__o - connect \sdr_a_5__core__o \sdr_a_5__core__o - connect \sdr_a_5__pad__o \sdr_a_5__pad__o - connect \sdr_a_6__core__o \sdr_a_6__core__o - connect \sdr_a_6__pad__o \sdr_a_6__pad__o - connect \sdr_a_7__core__o \sdr_a_7__core__o - connect \sdr_a_7__pad__o \sdr_a_7__pad__o - connect \sdr_a_8__core__o \sdr_a_8__core__o - connect \sdr_a_8__pad__o \sdr_a_8__pad__o - connect \sdr_a_9__core__o \sdr_a_9__core__o - connect \sdr_a_9__pad__o \sdr_a_9__pad__o - connect \sdr_ba_0__core__o \sdr_ba_0__core__o - connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o - connect \sdr_ba_1__core__o \sdr_ba_1__core__o - connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o - connect \sdr_cas_n__core__o \sdr_cas_n__core__o - connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o - connect \sdr_cke__core__o \sdr_cke__core__o - connect \sdr_cke__pad__o \sdr_cke__pad__o - connect \sdr_clock__core__o \sdr_clock__core__o - connect \sdr_clock__pad__o \sdr_clock__pad__o - connect \sdr_cs_n__core__o \sdr_cs_n__core__o - connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o - connect \sdr_dm_0__core__o \sdr_dm_0__core__o - connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o - connect \sdr_dm_1__core__i \sdr_dm_1__core__i - connect \sdr_dm_1__core__o \sdr_dm_1__core__o - connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe - connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i - connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o - connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe - connect \sdr_dq_0__core__i \sdr_dq_0__core__i - connect \sdr_dq_0__core__o \sdr_dq_0__core__o - connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe - connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i - connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o - connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe - connect \sdr_dq_10__core__i \sdr_dq_10__core__i - connect \sdr_dq_10__core__o \sdr_dq_10__core__o - connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe - connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i - connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o - connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe - connect \sdr_dq_11__core__i \sdr_dq_11__core__i - connect \sdr_dq_11__core__o \sdr_dq_11__core__o - connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe - connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i - connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o - connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe - connect \sdr_dq_12__core__i \sdr_dq_12__core__i - connect \sdr_dq_12__core__o \sdr_dq_12__core__o - connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe - connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i - connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o - connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe - connect \sdr_dq_13__core__i \sdr_dq_13__core__i - connect \sdr_dq_13__core__o \sdr_dq_13__core__o - connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe - connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i - connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o - connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe - connect \sdr_dq_14__core__i \sdr_dq_14__core__i - connect \sdr_dq_14__core__o \sdr_dq_14__core__o - connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe - connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i - connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o - connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe - connect \sdr_dq_15__core__i \sdr_dq_15__core__i - connect \sdr_dq_15__core__o \sdr_dq_15__core__o - connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe - connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i - connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o - connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe - connect \sdr_dq_1__core__i \sdr_dq_1__core__i - connect \sdr_dq_1__core__o \sdr_dq_1__core__o - connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe - connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i - connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o - connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe - connect \sdr_dq_2__core__i \sdr_dq_2__core__i - connect \sdr_dq_2__core__o \sdr_dq_2__core__o - connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe - connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i - connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o - connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe - connect \sdr_dq_3__core__i \sdr_dq_3__core__i - connect \sdr_dq_3__core__o \sdr_dq_3__core__o - connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe - connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i - connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o - connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe - connect \sdr_dq_4__core__i \sdr_dq_4__core__i - connect \sdr_dq_4__core__o \sdr_dq_4__core__o - connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe - connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i - connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o - connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe - connect \sdr_dq_5__core__i \sdr_dq_5__core__i - connect \sdr_dq_5__core__o \sdr_dq_5__core__o - connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe - connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i - connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o - connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe - connect \sdr_dq_6__core__i \sdr_dq_6__core__i - connect \sdr_dq_6__core__o \sdr_dq_6__core__o - connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe - connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i - connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o - connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe - connect \sdr_dq_7__core__i \sdr_dq_7__core__i - connect \sdr_dq_7__core__o \sdr_dq_7__core__o - connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe - connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i - connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o - connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe - connect \sdr_dq_8__core__i \sdr_dq_8__core__i - connect \sdr_dq_8__core__o \sdr_dq_8__core__o - connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe - connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i - connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o - connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe - connect \sdr_dq_9__core__i \sdr_dq_9__core__i - connect \sdr_dq_9__core__o \sdr_dq_9__core__o - connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe - connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i - connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o - connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe - connect \sdr_ras_n__core__o \sdr_ras_n__core__o - connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o - connect \sdr_we_n__core__o \sdr_we_n__core__o - connect \sdr_we_n__pad__o \sdr_we_n__pad__o - connect \wb_dcache_en \core_wb_dcache_en - connect \wb_icache_en \imem_wb_icache_en + attribute \src "ls180.v:763.5-763.43" + process $proc$ls180.v:763$3061 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:185860.12-185874.4" - cell \xics_icp \xics_icp - connect \clk \clk - connect \core_irq_o \xics_icp_core_irq_o - connect \icp_wb__ack \icp_wb__ack - connect \icp_wb__adr \icp_wb__adr - connect \icp_wb__cyc \icp_wb__cyc - connect \icp_wb__dat_r \icp_wb__dat_r - connect \icp_wb__dat_w \icp_wb__dat_w - connect \icp_wb__sel \icp_wb__sel - connect \icp_wb__stb \icp_wb__stb - connect \icp_wb__we \icp_wb__we - connect \ics_i_pri \xics_icp_ics_i_pri - connect \ics_i_src \xics_icp_ics_i_src - connect \rst \rst + attribute \src "ls180.v:766.5-766.49" + process $proc$ls180.v:766$3062 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:185875.12-185888.4" - cell \xics_ics \xics_ics - connect \clk \clk - connect \icp_o_pri \xics_ics_icp_o_pri - connect \icp_o_src \xics_ics_icp_o_src - connect \ics_wb__ack \ics_wb__ack - connect \ics_wb__adr \ics_wb__adr - connect \ics_wb__cyc \ics_wb__cyc - connect \ics_wb__dat_r \ics_wb__dat_r - connect \ics_wb__dat_w \ics_wb__dat_w - connect \ics_wb__stb \ics_wb__stb - connect \ics_wb__we \ics_wb__we - connect \int_level_i \int_level_i - connect \rst \rst + attribute \src "ls180.v:767.5-767.49" + process $proc$ls180.v:767$3063 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "libresoc.v:183018.7-183018.20" - process $proc$libresoc.v:183018$13822 + attribute \src "ls180.v:768.5-768.48" + process $proc$ls180.v:768$3064 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "libresoc.v:183154.13-183154.33" - process $proc$libresoc.v:183154$13823 + attribute \src "ls180.v:772.11-772.46" + process $proc$ls180.v:772$3065 assign { } { } - assign $1\core_asmcode[7:0] 8'00000000 + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 sync always sync init - update \core_asmcode $1\core_asmcode[7:0] + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] end - attribute \src "libresoc.v:183160.7-183160.35" - process $proc$libresoc.v:183160$13824 + attribute \src "ls180.v:774.11-774.45" + process $proc$ls180.v:774$3066 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13825 1'0 + assign $1\main_sdram_choose_req_grant[1:0] 2'00 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13825 + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] end - attribute \src "libresoc.v:183168.14-183168.55" - process $proc$libresoc.v:183168$13826 + attribute \src "ls180.v:776.12-776.36" + process $proc$ls180.v:776$3067 assign { } { } - assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init - update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:183172.13-183172.41" - process $proc$libresoc.v:183172$13827 + attribute \src "ls180.v:777.11-777.35" + process $proc$ls180.v:777$3068 assign { } { } - assign $1\core_core_core_cr_rd[7:0] 8'00000000 + assign $0\main_sdram_nop_ba[1:0] 2'00 sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init - update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:183176.7-183176.37" - process $proc$libresoc.v:183176$13828 + attribute \src "ls180.v:778.11-778.40" + process $proc$ls180.v:778$3069 assign { } { } - assign $1\core_core_core_cr_rd_ok[0:0] 1'0 + assign $1\main_sdram_steerer_sel[1:0] 2'00 sync always sync init - update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] end - attribute \src "libresoc.v:183180.13-183180.41" - process $proc$libresoc.v:183180$13829 + attribute \src "ls180.v:779.5-779.31" + process $proc$ls180.v:779$3070 assign { } { } - assign $1\core_core_core_cr_wr[7:0] 8'00000000 + assign $0\main_sdram_steerer0[0:0] 1'1 sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init - update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:183184.7-183184.42" - process $proc$libresoc.v:183184$13830 + attribute \src "ls180.v:780.5-780.31" + process $proc$ls180.v:780$3071 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13831 1'0 + assign $0\main_sdram_steerer1[0:0] 1'1 sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13831 end - attribute \src "libresoc.v:183186.7-183186.44" - process $proc$libresoc.v:183186$13832 + attribute \src "ls180.v:782.32-782.63" + process $proc$ls180.v:782$3072 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13833 1'0 + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13833 end - attribute \src "libresoc.v:183190.7-183190.44" - process $proc$libresoc.v:183190$13834 + attribute \src "ls180.v:784.32-784.63" + process $proc$ls180.v:784$3073 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13835 1'0 + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13835 end - attribute \src "libresoc.v:183194.7-183194.44" - process $proc$libresoc.v:183194$13836 + attribute \src "ls180.v:786.32-786.63" + process $proc$ls180.v:786$3074 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13837 1'0 + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13837 + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] end - attribute \src "libresoc.v:183198.7-183198.44" - process $proc$libresoc.v:183198$13838 + attribute \src "ls180.v:787.5-787.36" + process $proc$ls180.v:787$3075 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13839 1'0 + assign $1\main_sdram_tccdcon_count[0:0] 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13839 + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] end - attribute \src "libresoc.v:183202.7-183202.44" - process $proc$libresoc.v:183202$13840 + attribute \src "ls180.v:789.32-789.63" + process $proc$ls180.v:789$3076 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13841 1'0 + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13841 + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] end - attribute \src "libresoc.v:183206.7-183206.44" - process $proc$libresoc.v:183206$13842 + attribute \src "ls180.v:790.11-790.42" + process $proc$ls180.v:790$3077 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13843 1'0 + assign $1\main_sdram_twtrcon_count[2:0] 3'000 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13843 + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] end - attribute \src "libresoc.v:183210.7-183210.44" - process $proc$libresoc.v:183210$13844 + attribute \src "ls180.v:793.5-793.26" + process $proc$ls180.v:793$3078 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13845 1'0 + assign $1\main_sdram_en0[0:0] 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13845 + update \main_sdram_en0 $1\main_sdram_en0[0:0] end - attribute \src "libresoc.v:183229.14-183229.46" - process $proc$libresoc.v:183229$13846 + attribute \src "ls180.v:795.11-795.34" + process $proc$ls180.v:795$3079 assign { } { } - assign $1\core_core_core_fn_unit[11:0] 12'000000000000 + assign $1\main_sdram_time0[4:0] 5'00000 sync always sync init - update \core_core_core_fn_unit $1\core_core_core_fn_unit[11:0] + update \main_sdram_time0 $1\main_sdram_time0[4:0] end - attribute \src "libresoc.v:183237.13-183237.46" - process $proc$libresoc.v:183237$13847 + attribute \src "ls180.v:796.5-796.26" + process $proc$ls180.v:796$3080 assign { } { } - assign $1\core_core_core_input_carry[1:0] 2'00 + assign $1\main_sdram_en1[0:0] 1'0 sync always sync init - update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] + update \main_sdram_en1 $1\main_sdram_en1[0:0] end - attribute \src "libresoc.v:183241.14-183241.41" - process $proc$libresoc.v:183241$13848 + attribute \src "ls180.v:798.11-798.34" + process $proc$ls180.v:798$3081 assign { } { } - assign $1\core_core_core_insn[31:0] 0 + assign $1\main_sdram_time1[3:0] 4'0000 sync always sync init - update \core_core_core_insn $1\core_core_core_insn[31:0] + update \main_sdram_time1 $1\main_sdram_time1[3:0] end - attribute \src "libresoc.v:183319.13-183319.45" - process $proc$libresoc.v:183319$13849 + attribute \src "ls180.v:819.5-819.29" + process $proc$ls180.v:819$3082 assign { } { } - assign $1\core_core_core_insn_type[6:0] 7'0000000 + assign $1\main_wb_sdram_ack[0:0] 1'0 sync always sync init - update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] end - attribute \src "libresoc.v:183323.7-183323.37" - process $proc$libresoc.v:183323$13850 + attribute \src "ls180.v:823.5-823.29" + process $proc$ls180.v:823$3083 assign { } { } - assign $1\core_core_core_is_32bit[0:0] 1'0 + assign $0\main_wb_sdram_err[0:0] 1'0 sync always + update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] sync init - update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:183327.14-183327.55" - process $proc$libresoc.v:183327$13851 + attribute \src "ls180.v:824.12-824.40" + process $proc$ls180.v:824$3084 assign { } { } - assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \core_core_core_msr $1\core_core_core_msr[63:0] + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] end - attribute \src "libresoc.v:183331.7-183331.31" - process $proc$libresoc.v:183331$13852 + attribute \src "ls180.v:825.12-825.42" + process $proc$ls180.v:825$3085 assign { } { } - assign $1\core_core_core_oe[0:0] 1'0 + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init - update \core_core_core_oe $1\core_core_core_oe[0:0] + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] end - attribute \src "libresoc.v:183335.7-183335.34" - process $proc$libresoc.v:183335$13853 + attribute \src "ls180.v:827.11-827.38" + process $proc$ls180.v:827$3086 assign { } { } - assign $1\core_core_core_oe_ok[0:0] 1'0 + assign $1\main_litedram_wb_sel[1:0] 2'00 sync always sync init - update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] end - attribute \src "libresoc.v:183339.7-183339.31" - process $proc$libresoc.v:183339$13854 + attribute \src "ls180.v:828.5-828.32" + process $proc$ls180.v:828$3087 assign { } { } - assign $1\core_core_core_rc[0:0] 1'0 + assign $1\main_litedram_wb_cyc[0:0] 1'0 sync always sync init - update \core_core_core_rc $1\core_core_core_rc[0:0] + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] end - attribute \src "libresoc.v:183343.7-183343.34" - process $proc$libresoc.v:183343$13855 + attribute \src "ls180.v:829.5-829.32" + process $proc$ls180.v:829$3088 assign { } { } - assign $1\core_core_core_rc_ok[0:0] 1'0 + assign $1\main_litedram_wb_stb[0:0] 1'0 sync always sync init - update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "libresoc.v:183347.14-183347.48" - process $proc$libresoc.v:183347$13856 + attribute \src "ls180.v:83.5-83.46" + process $proc$ls180.v:83$2783 assign { } { } - assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 + assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 sync always sync init - update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] + update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] end - attribute \src "libresoc.v:183351.13-183351.44" - process $proc$libresoc.v:183351$13857 + attribute \src "ls180.v:831.5-831.31" + process $proc$ls180.v:831$3089 assign { } { } - assign $1\core_core_core_traptype[7:0] 8'00000000 + assign $1\main_litedram_wb_we[0:0] 1'0 sync always sync init - update \core_core_core_traptype $1\core_core_core_traptype[7:0] + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "libresoc.v:183355.13-183355.36" - process $proc$libresoc.v:183355$13858 + attribute \src "ls180.v:832.5-832.31" + process $proc$ls180.v:832$3090 assign { } { } - assign $1\core_core_cr_in1[2:0] 3'000 + assign $1\main_converter_skip[0:0] 1'0 sync always sync init - update \core_core_cr_in1 $1\core_core_cr_in1[2:0] + update \main_converter_skip $1\main_converter_skip[0:0] end - attribute \src "libresoc.v:183359.7-183359.33" - process $proc$libresoc.v:183359$13859 + attribute \src "ls180.v:833.5-833.34" + process $proc$ls180.v:833$3091 assign { } { } - assign $1\core_core_cr_in1_ok[0:0] 1'0 + assign $1\main_converter_counter[0:0] 1'0 sync always sync init - update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] + update \main_converter_counter $1\main_converter_counter[0:0] end - attribute \src "libresoc.v:183363.13-183363.36" - process $proc$libresoc.v:183363$13860 + attribute \src "ls180.v:835.12-835.40" + process $proc$ls180.v:835$3092 assign { } { } - assign $1\core_core_cr_in2[2:0] 3'000 + assign $1\main_converter_dat_r[31:0] 0 sync always sync init - update \core_core_cr_in2 $1\core_core_cr_in2[2:0] + update \main_converter_dat_r $1\main_converter_dat_r[31:0] end - attribute \src "libresoc.v:183365.13-183365.40" - process $proc$libresoc.v:183365$13861 + attribute \src "ls180.v:836.5-836.29" + process $proc$ls180.v:836$3093 assign { } { } - assign $0\core_core_cr_in2$1[2:0]$13862 3'000 + assign $1\main_cmd_consumed[0:0] 1'0 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13862 + update \main_cmd_consumed $1\main_cmd_consumed[0:0] end - attribute \src "libresoc.v:183371.7-183371.33" - process $proc$libresoc.v:183371$13863 + attribute \src "ls180.v:837.5-837.31" + process $proc$ls180.v:837$3094 assign { } { } - assign $1\core_core_cr_in2_ok[0:0] 1'0 + assign $1\main_wdata_consumed[0:0] 1'0 sync always sync init - update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] + update \main_wdata_consumed $1\main_wdata_consumed[0:0] end - attribute \src "libresoc.v:183373.7-183373.37" - process $proc$libresoc.v:183373$13864 + attribute \src "ls180.v:841.12-841.47" + process $proc$ls180.v:841$3095 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13865 1'0 + assign $1\main_uart_phy_storage[31:0] 9895604 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13865 + update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] end - attribute \src "libresoc.v:183379.13-183379.36" - process $proc$libresoc.v:183379$13866 + attribute \src "ls180.v:842.5-842.28" + process $proc$ls180.v:842$3096 assign { } { } - assign $1\core_core_cr_out[2:0] 3'000 + assign $1\main_uart_phy_re[0:0] 1'0 sync always sync init - update \core_core_cr_out $1\core_core_cr_out[2:0] + update \main_uart_phy_re $1\main_uart_phy_re[0:0] end - attribute \src "libresoc.v:183383.7-183383.32" - process $proc$libresoc.v:183383$13867 + attribute \src "ls180.v:844.5-844.36" + process $proc$ls180.v:844$3097 assign { } { } - assign $1\core_core_cr_wr_ok[0:0] 1'0 + assign $1\main_uart_phy_sink_ready[0:0] 1'0 sync always sync init - update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] end - attribute \src "libresoc.v:183387.13-183387.33" - process $proc$libresoc.v:183387$13868 + attribute \src "ls180.v:848.5-848.39" + process $proc$ls180.v:848$3098 assign { } { } - assign $1\core_core_ea[4:0] 5'00000 + assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init - update \core_core_ea $1\core_core_ea[4:0] + update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] end - attribute \src "libresoc.v:183391.13-183391.35" - process $proc$libresoc.v:183391$13869 + attribute \src "ls180.v:849.12-849.54" + process $proc$ls180.v:849$3099 assign { } { } - assign $1\core_core_fast1[2:0] 3'000 + assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init - update \core_core_fast1 $1\core_core_fast1[2:0] + update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] end - attribute \src "libresoc.v:183395.7-183395.32" - process $proc$libresoc.v:183395$13870 + attribute \src "ls180.v:850.11-850.38" + process $proc$ls180.v:850$3100 assign { } { } - assign $1\core_core_fast1_ok[0:0] 1'0 + assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 sync always sync init - update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] + update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] end - attribute \src "libresoc.v:183399.13-183399.35" - process $proc$libresoc.v:183399$13871 + attribute \src "ls180.v:851.11-851.43" + process $proc$ls180.v:851$3101 assign { } { } - assign $1\core_core_fast2[2:0] 3'000 + assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init - update \core_core_fast2 $1\core_core_fast2[2:0] + update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] end - attribute \src "libresoc.v:183403.7-183403.32" - process $proc$libresoc.v:183403$13872 + attribute \src "ls180.v:852.5-852.33" + process $proc$ls180.v:852$3102 assign { } { } - assign $1\core_core_fast2_ok[0:0] 1'0 + assign $1\main_uart_phy_tx_busy[0:0] 1'0 sync always sync init - update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] + update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] end - attribute \src "libresoc.v:183407.13-183407.36" - process $proc$libresoc.v:183407$13873 + attribute \src "ls180.v:853.5-853.38" + process $proc$ls180.v:853$3103 assign { } { } - assign $1\core_core_fasto1[2:0] 3'000 + assign $1\main_uart_phy_source_valid[0:0] 1'0 sync always sync init - update \core_core_fasto1 $1\core_core_fasto1[2:0] + update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] end - attribute \src "libresoc.v:183411.13-183411.36" - process $proc$libresoc.v:183411$13874 + attribute \src "ls180.v:855.5-855.38" + process $proc$ls180.v:855$3104 assign { } { } - assign $1\core_core_fasto2[2:0] 3'000 + assign $0\main_uart_phy_source_first[0:0] 1'0 sync always + update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init - update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:183415.7-183415.26" - process $proc$libresoc.v:183415$13875 + attribute \src "ls180.v:856.5-856.37" + process $proc$ls180.v:856$3105 assign { } { } - assign $1\core_core_lk[0:0] 1'0 + assign $0\main_uart_phy_source_last[0:0] 1'0 sync always + update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init - update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:183419.14-183419.49" - process $proc$libresoc.v:183419$13876 + attribute \src "ls180.v:857.11-857.51" + process $proc$ls180.v:857$3106 assign { } { } - assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init - update \core_core_pc $1\core_core_pc[63:0] + update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] end - attribute \src "libresoc.v:183423.13-183423.35" - process $proc$libresoc.v:183423$13877 + attribute \src "ls180.v:858.5-858.39" + process $proc$ls180.v:858$3107 assign { } { } - assign $1\core_core_reg1[4:0] 5'00000 + assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init - update \core_core_reg1 $1\core_core_reg1[4:0] + update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] end - attribute \src "libresoc.v:183427.7-183427.31" - process $proc$libresoc.v:183427$13878 + attribute \src "ls180.v:859.12-859.54" + process $proc$ls180.v:859$3108 assign { } { } - assign $1\core_core_reg1_ok[0:0] 1'0 + assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init - update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] + update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] end - attribute \src "libresoc.v:183431.13-183431.35" - process $proc$libresoc.v:183431$13879 + attribute \src "ls180.v:861.5-861.30" + process $proc$ls180.v:861$3109 assign { } { } - assign $1\core_core_reg2[4:0] 5'00000 + assign $1\main_uart_phy_rx_r[0:0] 1'0 sync always sync init - update \core_core_reg2 $1\core_core_reg2[4:0] + update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] end - attribute \src "libresoc.v:183435.7-183435.31" - process $proc$libresoc.v:183435$13880 + attribute \src "ls180.v:862.11-862.38" + process $proc$ls180.v:862$3110 assign { } { } - assign $1\core_core_reg2_ok[0:0] 1'0 + assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 sync always sync init - update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] + update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "libresoc.v:183439.13-183439.35" - process $proc$libresoc.v:183439$13881 + attribute \src "ls180.v:863.11-863.43" + process $proc$ls180.v:863$3111 assign { } { } - assign $1\core_core_reg3[4:0] 5'00000 + assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init - update \core_core_reg3 $1\core_core_reg3[4:0] + update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "libresoc.v:183443.7-183443.31" - process $proc$libresoc.v:183443$13882 + attribute \src "ls180.v:864.5-864.33" + process $proc$ls180.v:864$3112 assign { } { } - assign $1\core_core_reg3_ok[0:0] 1'0 + assign $1\main_uart_phy_rx_busy[0:0] 1'0 sync always sync init - update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] + update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] end - attribute \src "libresoc.v:183447.13-183447.35" - process $proc$libresoc.v:183447$13883 + attribute \src "ls180.v:87.5-87.46" + process $proc$ls180.v:87$2784 assign { } { } - assign $1\core_core_rego[4:0] 5'00000 + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] sync init - update \core_core_rego $1\core_core_rego[4:0] end - attribute \src "libresoc.v:183562.13-183562.37" - process $proc$libresoc.v:183562$13884 + attribute \src "ls180.v:875.5-875.32" + process $proc$ls180.v:875$3113 assign { } { } - assign $1\core_core_spr1[9:0] 10'0000000000 + assign $1\main_uart_tx_pending[0:0] 1'0 sync always sync init - update \core_core_spr1 $1\core_core_spr1[9:0] + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "libresoc.v:183566.7-183566.31" - process $proc$libresoc.v:183566$13885 + attribute \src "ls180.v:877.5-877.30" + process $proc$ls180.v:877$3114 assign { } { } - assign $1\core_core_spr1_ok[0:0] 1'0 + assign $1\main_uart_tx_clear[0:0] 1'0 sync always sync init - update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] end - attribute \src "libresoc.v:183681.13-183681.37" - process $proc$libresoc.v:183681$13886 + attribute \src "ls180.v:878.5-878.36" + process $proc$ls180.v:878$3115 assign { } { } - assign $1\core_core_spro[9:0] 10'0000000000 + assign $1\main_uart_tx_old_trigger[0:0] 1'0 sync always sync init - update \core_core_spro $1\core_core_spro[9:0] + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] end - attribute \src "libresoc.v:183687.13-183687.36" - process $proc$libresoc.v:183687$13887 + attribute \src "ls180.v:880.5-880.32" + process $proc$ls180.v:880$3116 assign { } { } - assign $1\core_core_xer_in[2:0] 3'000 + assign $1\main_uart_rx_pending[0:0] 1'0 sync always sync init - update \core_core_xer_in $1\core_core_xer_in[2:0] + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] end - attribute \src "libresoc.v:183695.7-183695.28" - process $proc$libresoc.v:183695$13888 + attribute \src "ls180.v:882.5-882.30" + process $proc$ls180.v:882$3117 assign { } { } - assign $1\core_cr_out_ok[0:0] 1'0 + assign $1\main_uart_rx_clear[0:0] 1'0 sync always sync init - update \core_cr_out_ok $1\core_cr_out_ok[0:0] + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] end - attribute \src "libresoc.v:183709.14-183709.45" - process $proc$libresoc.v:183709$13889 + attribute \src "ls180.v:883.5-883.36" + process $proc$ls180.v:883$3118 assign { } { } - assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_uart_rx_old_trigger[0:0] 1'0 sync always sync init - update \core_dec $1\core_dec[63:0] + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] end - attribute \src "libresoc.v:183719.7-183719.24" - process $proc$libresoc.v:183719$13890 + attribute \src "ls180.v:887.11-887.49" + process $proc$ls180.v:887$3119 assign { } { } - assign $1\core_ea_ok[0:0] 1'0 + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 sync always sync init - update \core_ea_ok $1\core_ea_ok[0:0] + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "libresoc.v:183723.7-183723.23" - process $proc$libresoc.v:183723$13891 + attribute \src "ls180.v:891.11-891.50" + process $proc$ls180.v:891$3120 assign { } { } - assign $1\core_eint[0:0] 1'0 + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 sync always sync init - update \core_eint $1\core_eint[0:0] + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] end - attribute \src "libresoc.v:183727.7-183727.28" - process $proc$libresoc.v:183727$13892 + attribute \src "ls180.v:892.11-892.48" + process $proc$ls180.v:892$3121 assign { } { } - assign $1\core_fasto1_ok[0:0] 1'0 + assign $1\main_uart_eventmanager_storage[1:0] 2'00 sync always sync init - update \core_fasto1_ok $1\core_fasto1_ok[0:0] + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] end - attribute \src "libresoc.v:183731.7-183731.28" - process $proc$libresoc.v:183731$13893 + attribute \src "ls180.v:893.5-893.37" + process $proc$ls180.v:893$3122 assign { } { } - assign $1\core_fasto2_ok[0:0] 1'0 + assign $1\main_uart_eventmanager_re[0:0] 1'0 sync always sync init - update \core_fasto2_ok $1\core_fasto2_ok[0:0] + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] end - attribute \src "libresoc.v:183759.14-183759.45" - process $proc$libresoc.v:183759$13894 + attribute \src "ls180.v:910.5-910.40" + process $proc$ls180.v:910$3123 assign { } { } - assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init - update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:183767.14-183767.37" - process $proc$libresoc.v:183767$13895 + attribute \src "ls180.v:911.5-911.39" + process $proc$ls180.v:911$3124 assign { } { } - assign $1\core_raw_insn_i[31:0] 0 + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init - update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:183771.7-183771.26" - process $proc$libresoc.v:183771$13896 + attribute \src "ls180.v:919.5-919.38" + process $proc$ls180.v:919$3125 assign { } { } - assign $1\core_rego_ok[0:0] 1'0 + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 sync always sync init - update \core_rego_ok $1\core_rego_ok[0:0] + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] end - attribute \src "libresoc.v:183775.7-183775.26" - process $proc$libresoc.v:183775$13897 + attribute \src "ls180.v:926.11-926.42" + process $proc$ls180.v:926$3126 assign { } { } - assign $1\core_spro_ok[0:0] 1'0 + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 sync always sync init - update \core_spro_ok $1\core_spro_ok[0:0] + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] end - attribute \src "libresoc.v:183787.7-183787.26" - process $proc$libresoc.v:183787$13898 + attribute \src "ls180.v:927.5-927.37" + process $proc$ls180.v:927$3127 assign { } { } - assign $1\core_xer_out[0:0] 1'0 + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init - update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:183793.7-183793.30" - process $proc$libresoc.v:183793$13899 + attribute \src "ls180.v:928.11-928.43" + process $proc$ls180.v:928$3128 assign { } { } - assign $1\cu_st__rel_o_dly[0:0] 1'0 + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 sync always sync init - update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] end - attribute \src "libresoc.v:183799.7-183799.24" - process $proc$libresoc.v:183799$13900 + attribute \src "ls180.v:929.11-929.43" + process $proc$ls180.v:929$3129 assign { } { } - assign $1\d_cr_delay[0:0] 1'0 + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 sync always sync init - update \d_cr_delay $1\d_cr_delay[0:0] + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] end - attribute \src "libresoc.v:183803.7-183803.25" - process $proc$libresoc.v:183803$13901 + attribute \src "ls180.v:930.11-930.46" + process $proc$ls180.v:930$3130 assign { } { } - assign $1\d_reg_delay[0:0] 1'0 + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init - update \d_reg_delay $1\d_reg_delay[0:0] + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] end - attribute \src "libresoc.v:183807.7-183807.25" - process $proc$libresoc.v:183807$13902 + attribute \src "ls180.v:956.5-956.38" + process $proc$ls180.v:956$3131 assign { } { } - assign $1\d_xer_delay[0:0] 1'0 + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 sync always sync init - update \d_xer_delay $1\d_xer_delay[0:0] + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] end - attribute \src "libresoc.v:183843.13-183843.34" - process $proc$libresoc.v:183843$13903 + attribute \src "ls180.v:963.11-963.42" + process $proc$ls180.v:963$3132 assign { } { } - assign $1\dbg_dmi_addr_i[3:0] 4'0000 + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 sync always sync init - update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] end - attribute \src "libresoc.v:183847.14-183847.48" - process $proc$libresoc.v:183847$13904 + attribute \src "ls180.v:964.5-964.37" + process $proc$ls180.v:964$3133 assign { } { } - assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init - update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:183853.7-183853.27" - process $proc$libresoc.v:183853$13905 + attribute \src "ls180.v:965.11-965.43" + process $proc$ls180.v:965$3134 assign { } { } - assign $1\dbg_dmi_req_i[0:0] 1'0 + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 sync always sync init - update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] end - attribute \src "libresoc.v:183857.7-183857.26" - process $proc$libresoc.v:183857$13906 + attribute \src "ls180.v:966.11-966.43" + process $proc$ls180.v:966$3135 assign { } { } - assign $1\dbg_dmi_we_i[0:0] 1'0 + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 sync always sync init - update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] end - attribute \src "libresoc.v:183911.14-183911.49" - process $proc$libresoc.v:183911$13907 + attribute \src "ls180.v:967.11-967.46" + process $proc$ls180.v:967$3136 assign { } { } - assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init - update \dec2_cur_dec $1\dec2_cur_dec[63:0] + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] end - attribute \src "libresoc.v:183915.7-183915.27" - process $proc$libresoc.v:183915$13908 + attribute \src "ls180.v:982.5-982.27" + process $proc$ls180.v:982$3137 assign { } { } - assign $1\dec2_cur_eint[0:0] 1'0 + assign $0\main_uart_reset[0:0] 1'0 sync always + update \main_uart_reset $0\main_uart_reset[0:0] sync init - update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:183919.14-183919.49" - process $proc$libresoc.v:183919$13909 + attribute \src "ls180.v:983.12-983.40" + process $proc$ls180.v:983$3138 assign { } { } - assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_gpio_oe_storage[15:0] 16'0000000000000000 sync always sync init - update \dec2_cur_msr $1\dec2_cur_msr[63:0] + update \main_gpio_oe_storage $1\main_gpio_oe_storage[15:0] end - attribute \src "libresoc.v:183923.14-183923.48" - process $proc$libresoc.v:183923$13910 + attribute \src "ls180.v:984.5-984.27" + process $proc$ls180.v:984$3139 assign { } { } - assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_gpio_oe_re[0:0] 1'0 sync always sync init - update \dec2_cur_pc $1\dec2_cur_pc[63:0] + update \main_gpio_oe_re $1\main_gpio_oe_re[0:0] end - attribute \src "libresoc.v:184332.13-184332.25" - process $proc$libresoc.v:184332$13911 + attribute \src "ls180.v:985.12-985.36" + process $proc$ls180.v:985$3140 assign { } { } - assign $1\delay[1:0] 2'11 + assign $1\main_gpio_status[15:0] 16'0000000000000000 sync always sync init - update \delay $1\delay[1:0] + update \main_gpio_status $1\main_gpio_status[15:0] end - attribute \src "libresoc.v:184348.13-184348.29" - process $proc$libresoc.v:184348$13912 + attribute \src "ls180.v:987.12-987.41" + process $proc$ls180.v:987$3141 assign { } { } - assign $1\fsm_state[1:0] 2'00 + assign $1\main_gpio_out_storage[15:0] 16'0000000000000000 sync always sync init - update \fsm_state $1\fsm_state[1:0] + update \main_gpio_out_storage $1\main_gpio_out_storage[15:0] end - attribute \src "libresoc.v:184350.13-184350.35" - process $proc$libresoc.v:184350$13913 + attribute \src "ls180.v:988.5-988.28" + process $proc$ls180.v:988$3142 assign { } { } - assign $0\fsm_state$133[1:0]$13914 2'00 + assign $1\main_gpio_out_re[0:0] 1'0 sync always sync init - update \fsm_state$133 $0\fsm_state$133[1:0]$13914 + update \main_gpio_out_re $1\main_gpio_out_re[0:0] end - attribute \src "libresoc.v:184592.14-184592.28" - process $proc$libresoc.v:184592$13915 + attribute \src "ls180.v:994.5-994.32" + process $proc$ls180.v:994$3143 assign { } { } - assign $1\ilatch[31:0] 0 + assign $1\main_spimaster2_done[0:0] 1'0 sync always sync init - update \ilatch $1\ilatch[31:0] + update \main_spimaster2_done $1\main_spimaster2_done[0:0] end - attribute \src "libresoc.v:184610.7-184610.30" - process $proc$libresoc.v:184610$13916 + attribute \src "ls180.v:995.5-995.31" + process $proc$ls180.v:995$3144 assign { } { } - assign $1\jtag_dmi0__ack_o[0:0] 1'0 + assign $1\main_spimaster3_irq[0:0] 1'0 sync always sync init - update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] end - attribute \src "libresoc.v:184618.14-184618.52" - process $proc$libresoc.v:184618$13917 + attribute \src "ls180.v:997.11-997.38" + process $proc$ls180.v:997$3145 assign { } { } - assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\main_spimaster5_miso[7:0] 8'00000000 sync always sync init - update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_libresocsim_converter0_reset $not$ls180.v:2777$14_Y + connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } + connect \main_libresocsim_converter1_reset $not$ls180.v:2837$25_Y + connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } + connect \main_libresocsim_converter2_reset $not$ls180.v:2897$36_Y + connect \main_libresocsim_libresoc_jtag_wb_dat_r { \main_libresocsim_interface2_converted_interface_dat_r \main_libresocsim_converter2_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [6:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:2969$60_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:2978$63_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3092$70_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3093$71_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3124$72_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3127$73_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3130$75_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3131$77_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3173$79_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3174$80_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3175$81_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3185$86_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3186$88_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3187$90_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3219$98_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3220$99_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3223$100_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3224$101_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3225$103_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3330$109_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3331$110_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3332$111_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3342$116_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3343$118_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3344$120_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3376$128_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3377$129_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3380$130_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3381$131_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3382$133_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3487$139_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3488$140_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3489$141_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3499$146_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3500$148_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3501$150_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3533$158_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3534$159_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3537$160_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3538$161_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3539$163_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3644$169_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3645$170_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3646$171_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3656$176_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3657$178_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3658$180_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3690$188_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3691$189_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3694$190_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3695$191_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3696$193_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3792$204_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3793$210_Y + connect \main_sdram_ras_allowed $and$ls180.v:3794$211_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3795$214_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3797$216_Y + connect \main_sdram_read_available $or$ls180.v:3798$223_Y + connect \main_sdram_write_available $or$ls180.v:3799$230_Y + connect \main_sdram_max_time0 $eq$ls180.v:3800$231_Y + connect \main_sdram_max_time1 $eq$ls180.v:3801$232_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3806$235_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3809$236_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:3842$294_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:3911$380_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:3988$412_Y + connect \builder_roundrobin0_ce $and$ls180.v:3989$415_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:3993$428_Y + connect \builder_roundrobin1_ce $and$ls180.v:3994$431_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:3998$444_Y + connect \builder_roundrobin2_ce $and$ls180.v:3999$447_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:4003$460_Y + connect \builder_roundrobin3_ce $and$ls180.v:4004$463_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:4008$527_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:4030$529_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4090$540_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4095$541_Y + connect \main_port_cmd_last $not$ls180.v:4096$542_Y + connect \main_port_cmd_valid $and$ls180.v:4097$545_Y + connect \main_port_wdata_valid $and$ls180.v:4098$549_Y + connect \main_port_rdata_ready $and$ls180.v:4099$552_Y + connect \main_litedram_wb_ack $and$ls180.v:4100$557_Y + connect \main_ack_cmd $or$ls180.v:4101$559_Y + connect \main_ack_wdata $or$ls180.v:4102$561_Y + connect \main_ack_rdata $and$ls180.v:4103$562_Y + connect \main_uart_uart_sink_valid \main_uart_phy_source_valid + connect \main_uart_phy_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_uart_phy_source_first + connect \main_uart_uart_sink_last \main_uart_phy_source_last + connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data + connect \main_uart_phy_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_uart_phy_sink_ready + connect \main_uart_phy_sink_first \main_uart_uart_source_first + connect \main_uart_phy_sink_last \main_uart_uart_source_last + connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4116$563_Y + connect \main_uart_txempty_status $not$ls180.v:4117$564_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4123$565_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4129$566_Y + connect \main_uart_rxfull_status $not$ls180.v:4130$567_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4132$569_Y + connect \main_uart_rx_trigger $not$ls180.v:4133$570_Y + connect \main_uart_irq $or$ls180.v:4156$579_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4171$582_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4172$583_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4182$587_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4183$588_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4187$589_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4188$590_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4201$593_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4202$594_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4212$598_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4213$599_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4217$600_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4218$601_Y + connect \main_gpio_pads_i \gpio_i + connect \gpio_o \main_gpio_pads_o + connect \gpio_oe \main_gpio_pads_oe + connect \main_gpio_pads_oe \main_gpio_oe_storage + connect \main_gpio_pads_o \main_gpio_out_storage + connect \main_spimaster0_start \main_spimaster9_start + connect \main_spimaster1_length \main_spimaster10_length + connect \main_spimaster4_mosi \main_spimaster16_storage + connect \main_spimaster13_done \main_spimaster2_done + connect \main_spimaster18_status \main_spimaster5_miso + connect \main_spimaster6_cs \main_spimaster21_storage + connect \main_spimaster7_loopback \main_spimaster23_storage + connect \main_spimaster31_clk_rise $eq$ls180.v:4231$603_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4232$605_Y + connect \main_spisdcard_start0 \main_spisdcard_start1 + connect \main_spisdcard_length0 \main_spisdcard_length1 + connect \main_spisdcard_mosi \main_spisdcard_mosi_storage + connect \main_spisdcard_done1 \main_spisdcard_done0 + connect \main_spisdcard_miso_status \main_spisdcard_miso + connect \main_spisdcard_cs \main_spisdcard_cs_storage + connect \main_spisdcard_loopback \main_spisdcard_loopback_storage + connect \main_spisdcard_clk_rise $eq$ls180.v:4289$611_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4290$613_Y + connect \main_spisdcard_clk_divider0 \main_spimaster1_storage + connect \i2c_scl \main_i2c_scl + connect \i2c_sda_oe \main_i2c_oe + connect \i2c_sda_o \main_i2c_sda0 + connect \main_i2c_sda1 \i2c_sda_i + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4346$621_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4347$625_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4348$629_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4349$633_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4350$637_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4371$638_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4401$641_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4524$651_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4525$653_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4542$655_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4544$656_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4545$658_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4651$673_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4652$674_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4669$676_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4671$677_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4672$679_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4785$688_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4786$689_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4803$691_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4805$692_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4806$694_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:4922$709_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4926$712_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4926$710_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4927$715_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4927$713_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4928$718_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4928$716_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4929$721_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4929$719_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4930$724_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4930$722_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4931$727_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4931$725_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4932$730_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4932$728_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4933$733_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4933$731_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4934$736_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4934$734_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4935$739_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4935$737_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4936$742_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4936$740_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4937$745_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4937$743_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4938$748_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4938$746_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4939$751_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4939$749_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4940$754_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4940$752_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4941$757_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4941$755_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4942$760_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4942$758_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4943$763_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4943$761_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:4944$766_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:4944$764_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:4945$769_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:4945$767_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:4946$772_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:4946$770_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:4947$775_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:4947$773_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:4948$778_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:4948$776_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:4949$781_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:4949$779_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:4950$784_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:4950$782_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:4951$787_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:4951$785_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:4952$790_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:4952$788_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:4953$793_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:4953$791_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:4954$796_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:4954$794_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:4955$799_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:4955$797_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:4956$802_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:4956$800_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:4957$805_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:4957$803_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:4958$808_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:4958$806_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:4959$811_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:4959$809_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:4960$814_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:4960$812_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:4961$817_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:4961$815_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:4962$820_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:4962$818_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:4963$823_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:4963$821_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:4964$826_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:4964$824_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:4965$829_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:4965$827_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:4975$832_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:4976$833_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:4978$835_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:4979$836_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:4981$838_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:4982$839_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:4984$841_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:4985$842_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:4986$847_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:4986$845_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:4986$843_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:4987$852_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:4987$850_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:4987$848_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:4996$858_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:4996$856_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:4996$854_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:4997$863_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:4997$861_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:4997$859_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5006$869_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5006$867_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5006$865_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5007$874_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5007$872_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5007$870_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5016$880_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5016$878_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5016$876_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5017$885_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5017$883_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5017$881_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5113$901_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5123$904_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5133$907_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5143$910_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5168$922_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5168$920_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5168$918_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5169$927_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5169$925_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5169$923_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5178$933_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5178$931_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5178$929_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5179$938_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5179$936_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5179$934_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5188$944_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5188$942_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5188$940_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5189$949_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5189$947_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5189$945_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5198$955_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5198$953_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5198$951_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5199$960_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5199$958_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5199$956_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5435$990_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5436$991_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5439$992_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5440$993_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5446$995_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5448$996_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 4'1111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [33:2] + connect \main_sdblock2mem_wishbonedmawriter_length { 2'00 \main_sdblock2mem_wishbonedmawriter_length_storage [31:2] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5458$997_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [33:2] + connect \main_sdmem2block_dma_length { 2'00 \main_sdmem2block_dma_length_storage [31:2] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5517$1004_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5598$1012_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5599$1013_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5601$1014_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5602$1015_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5603$1016_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5643$1021_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5644$1022_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5647$1023_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5648$1024_Y + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface2_converted_interface_dat_r \builder_shared_dat_r + connect \main_interface0_bus_dat_r \builder_shared_dat_r + connect \main_interface1_bus_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface0_converted_interface_ack $and$ls180.v:5699$1030_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$ls180.v:5700$1032_Y + connect \main_libresocsim_interface2_converted_interface_ack $and$ls180.v:5701$1034_Y + connect \main_interface0_bus_ack $and$ls180.v:5702$1036_Y + connect \main_interface1_bus_ack $and$ls180.v:5703$1038_Y + connect \main_libresocsim_interface0_converted_interface_err $and$ls180.v:5704$1040_Y + connect \main_libresocsim_interface1_converted_interface_err $and$ls180.v:5705$1042_Y + connect \main_libresocsim_interface2_converted_interface_err $and$ls180.v:5706$1044_Y + connect \main_interface0_bus_err $and$ls180.v:5707$1046_Y + connect \main_interface1_bus_err $and$ls180.v:5708$1048_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_interface2_converted_interface_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w + connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte + connect \main_wb_sdram_adr \builder_shared_adr + connect \main_wb_sdram_dat_w \builder_shared_dat_w + connect \main_wb_sdram_sel \builder_shared_sel + connect \main_wb_sdram_stb \builder_shared_stb + connect \main_wb_sdram_we \builder_shared_we + connect \main_wb_sdram_cti \builder_shared_cti + connect \main_wb_sdram_bte \builder_shared_bte + connect \builder_libresocsim_wishbone_adr \builder_shared_adr + connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w + connect \builder_libresocsim_wishbone_sel \builder_shared_sel + connect \builder_libresocsim_wishbone_stb \builder_shared_stb + connect \builder_libresocsim_wishbone_we \builder_shared_we + connect \builder_libresocsim_wishbone_cti \builder_shared_cti + connect \builder_libresocsim_wishbone_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5753$1055_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$ls180.v:5754$1056_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$ls180.v:5755$1057_Y + connect \main_wb_sdram_cyc $and$ls180.v:5756$1058_Y + connect \builder_libresocsim_wishbone_cyc $and$ls180.v:5757$1059_Y + connect \builder_shared_err $or$ls180.v:5758$1063_Y + connect \builder_wait $and$ls180.v:5759$1066_Y + connect \builder_done $eq$ls180.v:5772$1081_Y + connect \builder_csrbank0_sel $eq$ls180.v:5773$1082_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:5775$1085_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:5776$1089_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:5778$1092_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:5779$1096_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:5781$1099_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:5782$1103_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:5784$1106_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:5785$1110_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:5787$1113_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:5788$1117_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5790$1120_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5791$1124_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5793$1127_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5794$1131_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5796$1134_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5797$1138_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5799$1141_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5800$1145_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:5811$1146_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:5813$1149_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:5814$1153_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:5816$1156_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:5817$1160_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:5819$1163_Y + connect \builder_csrbank1_in1_we $and$ls180.v:5820$1167_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:5822$1170_Y + connect \builder_csrbank1_in0_we $and$ls180.v:5823$1174_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:5825$1177_Y + connect \builder_csrbank1_out1_we $and$ls180.v:5826$1181_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:5828$1184_Y + connect \builder_csrbank1_out0_we $and$ls180.v:5829$1188_Y + connect \builder_csrbank1_oe1_w \main_gpio_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpio_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpio_status [15:8] + connect \builder_csrbank1_in0_w \main_gpio_status [7:0] + connect \main_gpio_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpio_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpio_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:5837$1189_Y + connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] + connect \builder_csrbank2_w0_re $and$ls180.v:5839$1192_Y + connect \builder_csrbank2_w0_we $and$ls180.v:5840$1196_Y + connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_r_re $and$ls180.v:5842$1199_Y + connect \builder_csrbank2_r_we $and$ls180.v:5843$1203_Y + connect \main_i2c_scl \main_i2c_storage [0] + connect \main_i2c_oe \main_i2c_storage [1] + connect \main_i2c_sda0 \main_i2c_storage [2] + connect \builder_csrbank2_w0_w \main_i2c_storage + connect \main_i2c_status \main_i2c_sda1 + connect \builder_csrbank2_r_w \main_i2c_status + connect \main_i2c_we \builder_csrbank2_r_we + connect \builder_csrbank3_sel $eq$ls180.v:5851$1204_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:5853$1207_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:5854$1211_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:5856$1214_Y + connect \builder_csrbank3_width3_we $and$ls180.v:5857$1218_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:5859$1221_Y + connect \builder_csrbank3_width2_we $and$ls180.v:5860$1225_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:5862$1228_Y + connect \builder_csrbank3_width1_we $and$ls180.v:5863$1232_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:5865$1235_Y + connect \builder_csrbank3_width0_we $and$ls180.v:5866$1239_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:5868$1242_Y + connect \builder_csrbank3_period3_we $and$ls180.v:5869$1246_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:5871$1249_Y + connect \builder_csrbank3_period2_we $and$ls180.v:5872$1253_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:5874$1256_Y + connect \builder_csrbank3_period1_we $and$ls180.v:5875$1260_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:5877$1263_Y + connect \builder_csrbank3_period0_we $and$ls180.v:5878$1267_Y + connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:5888$1268_Y + connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_enable0_re $and$ls180.v:5890$1271_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:5891$1275_Y + connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width3_re $and$ls180.v:5893$1278_Y + connect \builder_csrbank4_width3_we $and$ls180.v:5894$1282_Y + connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width2_re $and$ls180.v:5896$1285_Y + connect \builder_csrbank4_width2_we $and$ls180.v:5897$1289_Y + connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width1_re $and$ls180.v:5899$1292_Y + connect \builder_csrbank4_width1_we $and$ls180.v:5900$1296_Y + connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width0_re $and$ls180.v:5902$1299_Y + connect \builder_csrbank4_width0_we $and$ls180.v:5903$1303_Y + connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period3_re $and$ls180.v:5905$1306_Y + connect \builder_csrbank4_period3_we $and$ls180.v:5906$1310_Y + connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period2_re $and$ls180.v:5908$1313_Y + connect \builder_csrbank4_period2_we $and$ls180.v:5909$1317_Y + connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period1_re $and$ls180.v:5911$1320_Y + connect \builder_csrbank4_period1_we $and$ls180.v:5912$1324_Y + connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period0_re $and$ls180.v:5914$1327_Y + connect \builder_csrbank4_period0_we $and$ls180.v:5915$1331_Y + connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank5_sel $eq$ls180.v:5925$1332_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$ls180.v:5927$1335_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:5928$1339_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$ls180.v:5930$1342_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:5931$1346_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$ls180.v:5933$1349_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:5934$1353_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$ls180.v:5936$1356_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:5937$1360_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$ls180.v:5939$1363_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:5940$1367_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$ls180.v:5942$1370_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:5943$1374_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$ls180.v:5945$1377_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:5946$1381_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$ls180.v:5948$1384_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:5949$1388_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$ls180.v:5951$1391_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:5952$1395_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$ls180.v:5954$1398_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:5955$1402_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$ls180.v:5957$1405_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:5958$1409_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$ls180.v:5960$1412_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:5961$1416_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:5963$1419_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:5964$1423_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$ls180.v:5966$1426_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:5967$1430_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:5969$1433_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:5970$1437_Y + connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank6_sel $eq$ls180.v:5987$1438_Y + connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:5989$1441_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:5990$1445_Y + connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:5992$1448_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:5993$1452_Y + connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:5995$1455_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:5996$1459_Y + connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:5998$1462_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:5999$1466_Y + connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6001$1469_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6002$1473_Y + connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6004$1476_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6005$1480_Y + connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6007$1483_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6008$1487_Y + connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6010$1490_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6011$1494_Y + connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:6013$1497_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6014$1501_Y + connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6016$1504_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6017$1508_Y + connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6019$1511_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6020$1515_Y + connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6022$1518_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6023$1522_Y + connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6025$1525_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6026$1529_Y + connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6028$1532_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6029$1536_Y + connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6031$1539_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6032$1543_Y + connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6034$1546_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6035$1550_Y + connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6037$1553_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6038$1557_Y + connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6040$1560_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6041$1564_Y + connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6043$1567_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6044$1571_Y + connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6046$1574_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6047$1578_Y + connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6049$1581_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6050$1585_Y + connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6052$1588_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6053$1592_Y + connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6055$1595_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6056$1599_Y + connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6058$1602_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6059$1606_Y + connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6061$1609_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6062$1613_Y + connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6064$1616_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6065$1620_Y + connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_data_event_re $and$ls180.v:6067$1623_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6068$1627_Y + connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] + connect \builder_csrbank6_block_length1_re $and$ls180.v:6070$1630_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6071$1634_Y + connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_length0_re $and$ls180.v:6073$1637_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6074$1641_Y + connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count3_re $and$ls180.v:6076$1644_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6077$1648_Y + connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count2_re $and$ls180.v:6079$1651_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6080$1655_Y + connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count1_re $and$ls180.v:6082$1658_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6083$1662_Y + connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count0_re $and$ls180.v:6085$1665_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6086$1669_Y + connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we + connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we + connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we + connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank7_sel $eq$ls180.v:6122$1670_Y + connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6124$1673_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6125$1677_Y + connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6127$1680_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6128$1684_Y + connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6130$1687_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6131$1691_Y + connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6133$1694_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6134$1698_Y + connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6136$1701_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6137$1705_Y + connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6139$1708_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6140$1712_Y + connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6142$1715_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6143$1719_Y + connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6145$1722_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6146$1726_Y + connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6148$1729_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6149$1733_Y + connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6151$1736_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6152$1740_Y + connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6154$1743_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6155$1747_Y + connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6157$1750_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6158$1754_Y + connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6160$1757_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6161$1761_Y + connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_done_re $and$ls180.v:6163$1764_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6164$1768_Y + connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6166$1771_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6167$1775_Y + connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6169$1778_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6170$1782_Y + connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6172$1785_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6173$1789_Y + connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6175$1792_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6176$1796_Y + connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6178$1799_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6179$1803_Y + connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we + connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we + connect \builder_csrbank8_sel $eq$ls180.v:6201$1804_Y + connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_card_detect_re $and$ls180.v:6203$1807_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6204$1811_Y + connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6206$1814_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6207$1818_Y + connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6209$1821_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6210$1825_Y + connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6212$1828_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6213$1832_Y + connect \builder_csrbank8_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank8_card_detect_we + connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank9_sel $eq$ls180.v:6218$1833_Y + connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6220$1836_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6221$1840_Y + connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6223$1843_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6224$1847_Y + connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6226$1850_Y + connect \main_sdram_command_issue_we $and$ls180.v:6227$1854_Y + connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6229$1857_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6230$1861_Y + connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6232$1864_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6233$1868_Y + connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6235$1871_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6236$1875_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6238$1878_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6239$1882_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6241$1885_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6242$1889_Y + connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6244$1892_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6245$1896_Y + connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6247$1899_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6248$1903_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank9_dfii_control0_w \main_sdram_storage + connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we + connect \builder_csrbank10_sel $eq$ls180.v:6263$1904_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6265$1907_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6266$1911_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6268$1914_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6269$1918_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6271$1921_Y + connect \builder_csrbank10_status_we $and$ls180.v:6272$1925_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6274$1928_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6275$1932_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6277$1935_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6278$1939_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6280$1942_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6281$1946_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6283$1949_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6284$1953_Y + connect \main_spimaster10_length \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] + connect \main_spimaster14_status \main_spimaster13_done + connect \builder_csrbank10_status_w \main_spimaster14_status + connect \main_spimaster15_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \main_spimaster16_storage + connect \builder_csrbank10_miso_w \main_spimaster18_status + connect \main_spimaster19_we \builder_csrbank10_miso_we + connect \main_spimaster20_sel \main_spimaster21_storage + connect \builder_csrbank10_cs0_w \main_spimaster21_storage + connect \builder_csrbank10_loopback0_w \main_spimaster23_storage + connect \builder_csrbank11_sel $eq$ls180.v:6303$1955_Y + connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control1_re $and$ls180.v:6305$1958_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6306$1962_Y + connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control0_re $and$ls180.v:6308$1965_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6309$1969_Y + connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_status_re $and$ls180.v:6311$1972_Y + connect \builder_csrbank11_status_we $and$ls180.v:6312$1976_Y + connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_mosi0_re $and$ls180.v:6314$1979_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6315$1983_Y + connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_miso_re $and$ls180.v:6317$1986_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6318$1990_Y + connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_cs0_re $and$ls180.v:6320$1993_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6321$1997_Y + connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_loopback0_re $and$ls180.v:6323$2000_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6324$2004_Y + connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6326$2007_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6327$2011_Y + connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6329$2014_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6330$2018_Y + connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] + connect \main_spisdcard_status_status \main_spisdcard_done1 + connect \builder_csrbank11_status_w \main_spisdcard_status_status + connect \main_spisdcard_status_we \builder_csrbank11_status_we + connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage + connect \builder_csrbank11_miso_w \main_spisdcard_miso_status + connect \main_spisdcard_miso_we \builder_csrbank11_miso_we + connect \main_spisdcard_sel \main_spisdcard_cs_storage + connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage + connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage + connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] + connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] + connect \builder_csrbank12_sel $eq$ls180.v:6351$2020_Y + connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load3_re $and$ls180.v:6353$2023_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6354$2027_Y + connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load2_re $and$ls180.v:6356$2030_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6357$2034_Y + connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load1_re $and$ls180.v:6359$2037_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6360$2041_Y + connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load0_re $and$ls180.v:6362$2044_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6363$2048_Y + connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload3_re $and$ls180.v:6365$2051_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6366$2055_Y + connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload2_re $and$ls180.v:6368$2058_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6369$2062_Y + connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload1_re $and$ls180.v:6371$2065_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6372$2069_Y + connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload0_re $and$ls180.v:6374$2072_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6375$2076_Y + connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_en0_re $and$ls180.v:6377$2079_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6378$2083_Y + connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_update_value0_re $and$ls180.v:6380$2086_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6381$2090_Y + connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value3_re $and$ls180.v:6383$2093_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6384$2097_Y + connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value2_re $and$ls180.v:6386$2100_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6387$2104_Y + connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value1_re $and$ls180.v:6389$2107_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6390$2111_Y + connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value0_re $and$ls180.v:6392$2114_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6393$2118_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6395$2121_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6396$2125_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6398$2128_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6399$2132_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6401$2135_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6402$2139_Y + connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank12_en0_w \main_libresocsim_en_storage + connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank12_value0_we + connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank13_sel $eq$ls180.v:6419$2140_Y + connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6421$2143_Y + connect \main_uart_rxtx_we $and$ls180.v:6422$2147_Y + connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txfull_re $and$ls180.v:6424$2150_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6425$2154_Y + connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxempty_re $and$ls180.v:6427$2157_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6428$2161_Y + connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6430$2164_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6431$2168_Y + connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6433$2171_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6434$2175_Y + connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6436$2178_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6437$2182_Y + connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txempty_re $and$ls180.v:6439$2185_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6440$2189_Y + connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxfull_re $and$ls180.v:6442$2192_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6443$2196_Y + connect \builder_csrbank13_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank13_txfull_we + connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we + connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank13_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank13_txempty_we + connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we + connect \builder_csrbank14_sel $eq$ls180.v:6453$2197_Y + connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6455$2200_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6456$2204_Y + connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6458$2207_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6459$2211_Y + connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6461$2214_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6462$2218_Y + connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6464$2221_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6465$2225_Y + connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] + connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] + connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] + connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6519$2239_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \main_uart_phy_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10071$2705_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10089$2712_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10103$2719_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10117$2726_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10131$2733_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10179$2754_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10193$2761_DATA +end +attribute \src "libresoc.v:45741.1-45769.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "libresoc.v:45742.7-45742.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:45757.3-45766.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:45757.3-45766.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:45756.17-45756.105" + wire $eq$libresoc.v:45756$1558_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:45742.7-45742.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" + cell $eq $eq$libresoc.v:45756$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:45756$1558_Y end - attribute \src "libresoc.v:184674.7-184674.22" - process $proc$libresoc.v:184674$13918 + attribute \src "libresoc.v:45742.7-45742.20" + process $proc$libresoc.v:45742$1560 assign { } { } - assign $1\msr_read[0:0] 1'1 + assign $0\initial[0:0] 1'0 sync always + update \initial $0\initial[0:0] sync init - update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:184702.7-184702.24" - process $proc$libresoc.v:184702$13919 + attribute \src "libresoc.v:45757.3-45766.6" + process $proc$libresoc.v:45757$1559 assign { } { } - assign $1\pc_changed[0:0] 1'0 - sync always - sync init - update \pc_changed $1\pc_changed[0:0] - end - attribute \src "libresoc.v:184712.7-184712.25" - process $proc$libresoc.v:184712$13920 assign { } { } - assign $1\pc_ok_delay[0:0] 1'0 + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:45758.5-45758.29" + switch \initial + attribute \src "libresoc.v:45758.9-45758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:20" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_lck_o[0:0] \clk_24_i + case + assign $1\pll_lck_o[0:0] 1'0 + end sync always - sync init - update \pc_ok_delay $1\pc_ok_delay[0:0] - end - attribute \src "libresoc.v:185152.3-185153.39" - process $proc$libresoc.v:185152$13322 - assign { } { } - assign $0\d_reg_delay[0:0] \d_reg_delay$next - sync posedge \clk - update \d_reg_delay $0\d_reg_delay[0:0] - end - attribute \src "libresoc.v:185154.3-185155.29" - process $proc$libresoc.v:185154$13323 - assign { } { } - assign $0\ilatch[31:0] \ilatch$next - sync posedge \clk - update \ilatch $0\ilatch[31:0] - end - attribute \src "libresoc.v:185156.3-185157.41" - process $proc$libresoc.v:185156$13324 - assign { } { } - assign $0\core_core_pc[63:0] \core_core_pc$next - sync posedge \clk - update \core_core_pc $0\core_core_pc[63:0] - end - attribute \src "libresoc.v:185158.3-185159.33" - process $proc$libresoc.v:185158$13325 - assign { } { } - assign $0\core_msr[63:0] \core_msr$next - sync posedge \clk - update \core_msr $0\core_msr[63:0] - end - attribute \src "libresoc.v:185160.3-185161.35" - process $proc$libresoc.v:185160$13326 - assign { } { } - assign $0\core_eint[0:0] \core_eint$next - sync posedge \clk - update \core_eint $0\core_eint[0:0] - end - attribute \src "libresoc.v:185162.3-185163.33" - process $proc$libresoc.v:185162$13327 - assign { } { } - assign $0\core_dec[63:0] \core_dec$next - sync posedge \clk - update \core_dec $0\core_dec[63:0] - end - attribute \src "libresoc.v:185164.3-185165.41" - process $proc$libresoc.v:185164$13328 - assign { } { } - assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next - sync posedge \clk - update \dec2_cur_msr $0\dec2_cur_msr[63:0] - end - attribute \src "libresoc.v:185166.3-185167.35" - process $proc$libresoc.v:185166$13329 - assign { } { } - assign $0\fsm_state[1:0] \fsm_state$next - sync posedge \clk - update \fsm_state $0\fsm_state[1:0] - end - attribute \src "libresoc.v:185168.3-185169.33" - process $proc$libresoc.v:185168$13330 - assign { } { } - assign $0\msr_read[0:0] \msr_read$next - sync posedge \clk - update \msr_read $0\msr_read[0:0] - end - attribute \src "libresoc.v:185170.3-185171.39" - process $proc$libresoc.v:185170$13331 - assign { } { } - assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next - sync posedge \clk - update \dec2_cur_pc $0\dec2_cur_pc[63:0] - end - attribute \src "libresoc.v:185172.3-185173.57" - process $proc$libresoc.v:185172$13332 - assign { } { } - assign $0\core_bigendian_i$10[0:0]$13333 \core_bigendian_i$10$next - sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13333 - end - attribute \src "libresoc.v:185174.3-185175.47" - process $proc$libresoc.v:185174$13334 - assign { } { } - assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next - sync posedge \clk - update \core_raw_insn_i $0\core_raw_insn_i[31:0] - end - attribute \src "libresoc.v:185176.3-185177.41" - process $proc$libresoc.v:185176$13335 - assign { } { } - assign $0\core_asmcode[7:0] \core_asmcode$next - sync posedge \clk - update \core_asmcode $0\core_asmcode[7:0] - end - attribute \src "libresoc.v:185178.3-185179.45" - process $proc$libresoc.v:185178$13336 - assign { } { } - assign $0\core_core_rego[4:0] \core_core_rego$next - sync posedge \clk - update \core_core_rego $0\core_core_rego[4:0] - end - attribute \src "libresoc.v:185180.3-185181.41" - process $proc$libresoc.v:185180$13337 - assign { } { } - assign $0\core_rego_ok[0:0] \core_rego_ok$next - sync posedge \clk - update \core_rego_ok $0\core_rego_ok[0:0] - end - attribute \src "libresoc.v:185182.3-185183.41" - process $proc$libresoc.v:185182$13338 - assign { } { } - assign $0\core_core_ea[4:0] \core_core_ea$next - sync posedge \clk - update \core_core_ea $0\core_core_ea[4:0] - end - attribute \src "libresoc.v:185184.3-185185.37" - process $proc$libresoc.v:185184$13339 - assign { } { } - assign $0\core_ea_ok[0:0] \core_ea_ok$next - sync posedge \clk - update \core_ea_ok $0\core_ea_ok[0:0] - end - attribute \src "libresoc.v:185186.3-185187.45" - process $proc$libresoc.v:185186$13340 - assign { } { } - assign $0\core_core_reg1[4:0] \core_core_reg1$next - sync posedge \clk - update \core_core_reg1 $0\core_core_reg1[4:0] - end - attribute \src "libresoc.v:185188.3-185189.51" - process $proc$libresoc.v:185188$13341 - assign { } { } - assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next - sync posedge \clk - update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] - end - attribute \src "libresoc.v:185190.3-185191.45" - process $proc$libresoc.v:185190$13342 - assign { } { } - assign $0\core_core_reg2[4:0] \core_core_reg2$next - sync posedge \clk - update \core_core_reg2 $0\core_core_reg2[4:0] - end - attribute \src "libresoc.v:185192.3-185193.51" - process $proc$libresoc.v:185192$13343 - assign { } { } - assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next - sync posedge \clk - update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] - end - attribute \src "libresoc.v:185194.3-185195.45" - process $proc$libresoc.v:185194$13344 - assign { } { } - assign $0\core_core_reg3[4:0] \core_core_reg3$next - sync posedge \clk - update \core_core_reg3 $0\core_core_reg3[4:0] - end - attribute \src "libresoc.v:185196.3-185197.51" - process $proc$libresoc.v:185196$13345 - assign { } { } - assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next - sync posedge \clk - update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] - end - attribute \src "libresoc.v:185198.3-185199.45" - process $proc$libresoc.v:185198$13346 - assign { } { } - assign $0\core_core_spro[9:0] \core_core_spro$next - sync posedge \clk - update \core_core_spro $0\core_core_spro[9:0] - end - attribute \src "libresoc.v:185200.3-185201.41" - process $proc$libresoc.v:185200$13347 - assign { } { } - assign $0\core_spro_ok[0:0] \core_spro_ok$next - sync posedge \clk - update \core_spro_ok $0\core_spro_ok[0:0] - end - attribute \src "libresoc.v:185202.3-185203.45" - process $proc$libresoc.v:185202$13348 - assign { } { } - assign $0\core_core_spr1[9:0] \core_core_spr1$next - sync posedge \clk - update \core_core_spr1 $0\core_core_spr1[9:0] - end - attribute \src "libresoc.v:185204.3-185205.51" - process $proc$libresoc.v:185204$13349 - assign { } { } - assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next - sync posedge \clk - update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] - end - attribute \src "libresoc.v:185206.3-185207.49" - process $proc$libresoc.v:185206$13350 - assign { } { } - assign $0\core_core_xer_in[2:0] \core_core_xer_in$next - sync posedge \clk - update \core_core_xer_in $0\core_core_xer_in[2:0] - end - attribute \src "libresoc.v:185208.3-185209.41" - process $proc$libresoc.v:185208$13351 - assign { } { } - assign $0\core_xer_out[0:0] \core_xer_out$next - sync posedge \clk - update \core_xer_out $0\core_xer_out[0:0] - end - attribute \src "libresoc.v:185210.3-185211.47" - process $proc$libresoc.v:185210$13352 - assign { } { } - assign $0\core_core_fast1[2:0] \core_core_fast1$next - sync posedge \clk - update \core_core_fast1 $0\core_core_fast1[2:0] - end - attribute \src "libresoc.v:185212.3-185213.53" - process $proc$libresoc.v:185212$13353 - assign { } { } - assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next - sync posedge \clk - update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] - end - attribute \src "libresoc.v:185214.3-185215.47" - process $proc$libresoc.v:185214$13354 - assign { } { } - assign $0\core_core_fast2[2:0] \core_core_fast2$next - sync posedge \clk - update \core_core_fast2 $0\core_core_fast2[2:0] - end - attribute \src "libresoc.v:185216.3-185217.53" - process $proc$libresoc.v:185216$13355 - assign { } { } - assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next - sync posedge \clk - update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] - end - attribute \src "libresoc.v:185218.3-185219.49" - process $proc$libresoc.v:185218$13356 - assign { } { } - assign $0\core_core_fasto1[2:0] \core_core_fasto1$next - sync posedge \clk - update \core_core_fasto1 $0\core_core_fasto1[2:0] - end - attribute \src "libresoc.v:185220.3-185221.45" - process $proc$libresoc.v:185220$13357 - assign { } { } - assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next - sync posedge \clk - update \core_fasto1_ok $0\core_fasto1_ok[0:0] - end - attribute \src "libresoc.v:185222.3-185223.49" - process $proc$libresoc.v:185222$13358 - assign { } { } - assign $0\core_core_fasto2[2:0] \core_core_fasto2$next - sync posedge \clk - update \core_core_fasto2 $0\core_core_fasto2[2:0] - end - attribute \src "libresoc.v:185224.3-185225.45" - process $proc$libresoc.v:185224$13359 - assign { } { } - assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next - sync posedge \clk - update \core_fasto2_ok $0\core_fasto2_ok[0:0] - end - attribute \src "libresoc.v:185226.3-185227.49" - process $proc$libresoc.v:185226$13360 - assign { } { } - assign $0\core_core_cr_in1[2:0] \core_core_cr_in1$next - sync posedge \clk - update \core_core_cr_in1 $0\core_core_cr_in1[2:0] - end - attribute \src "libresoc.v:185228.3-185229.55" - process $proc$libresoc.v:185228$13361 - assign { } { } - assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next - sync posedge \clk - update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] - end - attribute \src "libresoc.v:185230.3-185231.49" - process $proc$libresoc.v:185230$13362 - assign { } { } - assign $0\core_core_cr_in2[2:0] \core_core_cr_in2$next - sync posedge \clk - update \core_core_cr_in2 $0\core_core_cr_in2[2:0] - end - attribute \src "libresoc.v:185232.3-185233.55" - process $proc$libresoc.v:185232$13363 - assign { } { } - assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next - sync posedge \clk - update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] - end - attribute \src "libresoc.v:185234.3-185235.55" - process $proc$libresoc.v:185234$13364 - assign { } { } - assign $0\core_core_cr_in2$1[2:0]$13365 \core_core_cr_in2$1$next - sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$13365 - end - attribute \src "libresoc.v:185236.3-185237.61" - process $proc$libresoc.v:185236$13366 - assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13367 \core_core_cr_in2_ok$2$next - sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13367 - end - attribute \src "libresoc.v:185238.3-185239.49" - process $proc$libresoc.v:185238$13368 - assign { } { } - assign $0\core_core_cr_out[2:0] \core_core_cr_out$next - sync posedge \clk - update \core_core_cr_out $0\core_core_cr_out[2:0] - end - attribute \src "libresoc.v:185240.3-185241.45" - process $proc$libresoc.v:185240$13369 - assign { } { } - assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next - sync posedge \clk - update \core_cr_out_ok $0\core_cr_out_ok[0:0] - end - attribute \src "libresoc.v:185242.3-185243.53" - process $proc$libresoc.v:185242$13370 - assign { } { } - assign $0\core_core_core_msr[63:0] \core_core_core_msr$next - sync posedge \clk - update \core_core_core_msr $0\core_core_core_msr[63:0] - end - attribute \src "libresoc.v:185244.3-185245.53" - process $proc$libresoc.v:185244$13371 - assign { } { } - assign $0\core_core_core_cia[63:0] \core_core_core_cia$next - sync posedge \clk - update \core_core_core_cia $0\core_core_core_cia[63:0] - end - attribute \src "libresoc.v:185246.3-185247.55" - process $proc$libresoc.v:185246$13372 - assign { } { } - assign $0\core_core_core_insn[31:0] \core_core_core_insn$next - sync posedge \clk - update \core_core_core_insn $0\core_core_core_insn[31:0] - end - attribute \src "libresoc.v:185248.3-185249.65" - process $proc$libresoc.v:185248$13373 - assign { } { } - assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next - sync posedge \clk - update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] - end - attribute \src "libresoc.v:185250.3-185251.61" - process $proc$libresoc.v:185250$13374 - assign { } { } - assign $0\core_core_core_fn_unit[11:0] \core_core_core_fn_unit$next - sync posedge \clk - update \core_core_core_fn_unit $0\core_core_core_fn_unit[11:0] - end - attribute \src "libresoc.v:185252.3-185253.41" - process $proc$libresoc.v:185252$13375 - assign { } { } - assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next - sync posedge \clk - update \dec2_cur_dec $0\dec2_cur_dec[63:0] - end - attribute \src "libresoc.v:185254.3-185255.41" - process $proc$libresoc.v:185254$13376 - assign { } { } - assign $0\core_core_lk[0:0] \core_core_lk$next - sync posedge \clk - update \core_core_lk $0\core_core_lk[0:0] - end - attribute \src "libresoc.v:185256.3-185257.51" - process $proc$libresoc.v:185256$13377 - assign { } { } - assign $0\core_core_core_rc[0:0] \core_core_core_rc$next - sync posedge \clk - update \core_core_core_rc $0\core_core_core_rc[0:0] - end - attribute \src "libresoc.v:185258.3-185259.57" - process $proc$libresoc.v:185258$13378 - assign { } { } - assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next - sync posedge \clk - update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] - end - attribute \src "libresoc.v:185260.3-185261.51" - process $proc$libresoc.v:185260$13379 - assign { } { } - assign $0\core_core_core_oe[0:0] \core_core_core_oe$next - sync posedge \clk - update \core_core_core_oe $0\core_core_core_oe[0:0] - end - attribute \src "libresoc.v:185262.3-185263.57" - process $proc$libresoc.v:185262$13380 - assign { } { } - assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next - sync posedge \clk - update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] + update \pll_lck_o $0\pll_lck_o[0:0] end - attribute \src "libresoc.v:185264.3-185265.69" - process $proc$libresoc.v:185264$13381 - assign { } { } - assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next - sync posedge \clk - update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] - end - attribute \src "libresoc.v:185266.3-185267.63" - process $proc$libresoc.v:185266$13382 - assign { } { } - assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next - sync posedge \clk - update \core_core_core_traptype $0\core_core_core_traptype[7:0] + connect \$1 $eq$libresoc.v:45756$1558_Y + connect \pll_18_o \clk_24_i + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:45773.1-45857.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:45830.17-45830.91" + wire $not$libresoc.v:45830$1561_Y + attribute \src "libresoc.v:45832.18-45832.93" + wire $not$libresoc.v:45832$1563_Y + attribute \src "libresoc.v:45834.18-45834.93" + wire $not$libresoc.v:45834$1565_Y + attribute \src "libresoc.v:45835.17-45835.138" + wire width 8 $not$libresoc.v:45835$1566_Y + attribute \src "libresoc.v:45837.18-45837.93" + wire $not$libresoc.v:45837$1568_Y + attribute \src "libresoc.v:45839.18-45839.93" + wire $not$libresoc.v:45839$1570_Y + attribute \src "libresoc.v:45841.18-45841.93" + wire $not$libresoc.v:45841$1572_Y + attribute \src "libresoc.v:45844.17-45844.91" + wire $not$libresoc.v:45844$1575_Y + attribute \src "libresoc.v:45831.18-45831.116" + wire $reduce_or$libresoc.v:45831$1562_Y + attribute \src "libresoc.v:45833.18-45833.122" + wire $reduce_or$libresoc.v:45833$1564_Y + attribute \src "libresoc.v:45836.18-45836.128" + wire $reduce_or$libresoc.v:45836$1567_Y + attribute \src "libresoc.v:45838.18-45838.134" + wire $reduce_or$libresoc.v:45838$1569_Y + attribute \src "libresoc.v:45840.18-45840.140" + wire $reduce_or$libresoc.v:45840$1571_Y + attribute \src "libresoc.v:45842.18-45842.90" + wire $reduce_or$libresoc.v:45842$1573_Y + attribute \src "libresoc.v:45843.17-45843.103" + wire $reduce_or$libresoc.v:45843$1574_Y + attribute \src "libresoc.v:45845.17-45845.109" + wire $reduce_or$libresoc.v:45845$1576_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45830$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:45830$1561_Y end - attribute \src "libresoc.v:185268.3-185269.71" - process $proc$libresoc.v:185268$13383 - assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13384 \core_core_core_exc_$signal$next - sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13384 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45832$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:45832$1563_Y end - attribute \src "libresoc.v:185270.3-185271.75" - process $proc$libresoc.v:185270$13385 - assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13386 \core_core_core_exc_$signal$3$next - sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13386 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45834$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:45834$1565_Y end - attribute \src "libresoc.v:185272.3-185273.75" - process $proc$libresoc.v:185272$13387 - assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13388 \core_core_core_exc_$signal$4$next - sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13388 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:45835$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:45835$1566_Y end - attribute \src "libresoc.v:185274.3-185275.45" - process $proc$libresoc.v:185274$13389 - assign { } { } - assign $0\fsm_state$133[1:0]$13390 \fsm_state$133$next - sync posedge \clk - update \fsm_state$133 $0\fsm_state$133[1:0]$13390 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45837$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:45837$1568_Y end - attribute \src "libresoc.v:185276.3-185277.75" - process $proc$libresoc.v:185276$13391 - assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13392 \core_core_core_exc_$signal$5$next - sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13392 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45839$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:45839$1570_Y end - attribute \src "libresoc.v:185278.3-185279.75" - process $proc$libresoc.v:185278$13393 - assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13394 \core_core_core_exc_$signal$6$next - sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13394 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45841$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:45841$1572_Y end - attribute \src "libresoc.v:185280.3-185281.75" - process $proc$libresoc.v:185280$13395 - assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13396 \core_core_core_exc_$signal$7$next - sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13396 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45844$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:45844$1575_Y end - attribute \src "libresoc.v:185282.3-185283.75" - process $proc$libresoc.v:185282$13397 - assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13398 \core_core_core_exc_$signal$8$next - sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13398 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45831$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:45831$1562_Y end - attribute \src "libresoc.v:185284.3-185285.75" - process $proc$libresoc.v:185284$13399 - assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13400 \core_core_core_exc_$signal$9$next - sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13400 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45833$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:45833$1564_Y end - attribute \src "libresoc.v:185286.3-185287.63" - process $proc$libresoc.v:185286$13401 - assign { } { } - assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next - sync posedge \clk - update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45836$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:45836$1567_Y end - attribute \src "libresoc.v:185288.3-185289.57" - process $proc$libresoc.v:185288$13402 - assign { } { } - assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next - sync posedge \clk - update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45838$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:45838$1569_Y end - attribute \src "libresoc.v:185290.3-185291.63" - process $proc$libresoc.v:185290$13403 - assign { } { } - assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next - sync posedge \clk - update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45840$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:45840$1571_Y end - attribute \src "libresoc.v:185292.3-185293.57" - process $proc$libresoc.v:185292$13404 - assign { } { } - assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next - sync posedge \clk - update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:45842$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:45842$1573_Y end - attribute \src "libresoc.v:185294.3-185295.53" - process $proc$libresoc.v:185294$13405 - assign { } { } - assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next - sync posedge \clk - update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45843$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:45843$1574_Y end - attribute \src "libresoc.v:185296.3-185297.39" - process $proc$libresoc.v:185296$13406 - assign { } { } - assign $0\d_xer_delay[0:0] \d_xer_delay$next - sync posedge \clk - update \d_xer_delay $0\d_xer_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45845$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:45845$1576_Y + end + connect \$7 $not$libresoc.v:45830$1561_Y + connect \$12 $reduce_or$libresoc.v:45831$1562_Y + connect \$11 $not$libresoc.v:45832$1563_Y + connect \$16 $reduce_or$libresoc.v:45833$1564_Y + connect \$15 $not$libresoc.v:45834$1565_Y + connect \$1 $not$libresoc.v:45835$1566_Y + connect \$20 $reduce_or$libresoc.v:45836$1567_Y + connect \$19 $not$libresoc.v:45837$1568_Y + connect \$24 $reduce_or$libresoc.v:45838$1569_Y + connect \$23 $not$libresoc.v:45839$1570_Y + connect \$28 $reduce_or$libresoc.v:45840$1571_Y + connect \$27 $not$libresoc.v:45841$1572_Y + connect \$31 $reduce_or$libresoc.v:45842$1573_Y + connect \$4 $reduce_or$libresoc.v:45843$1574_Y + connect \$3 $not$libresoc.v:45844$1575_Y + connect \$8 $reduce_or$libresoc.v:45845$1576_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:45861.1-45945.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$1 + attribute \src "libresoc.v:45918.17-45918.91" + wire $not$libresoc.v:45918$1577_Y + attribute \src "libresoc.v:45920.18-45920.93" + wire $not$libresoc.v:45920$1579_Y + attribute \src "libresoc.v:45922.18-45922.93" + wire $not$libresoc.v:45922$1581_Y + attribute \src "libresoc.v:45923.17-45923.138" + wire width 8 $not$libresoc.v:45923$1582_Y + attribute \src "libresoc.v:45925.18-45925.93" + wire $not$libresoc.v:45925$1584_Y + attribute \src "libresoc.v:45927.18-45927.93" + wire $not$libresoc.v:45927$1586_Y + attribute \src "libresoc.v:45929.18-45929.93" + wire $not$libresoc.v:45929$1588_Y + attribute \src "libresoc.v:45932.17-45932.91" + wire $not$libresoc.v:45932$1591_Y + attribute \src "libresoc.v:45919.18-45919.116" + wire $reduce_or$libresoc.v:45919$1578_Y + attribute \src "libresoc.v:45921.18-45921.122" + wire $reduce_or$libresoc.v:45921$1580_Y + attribute \src "libresoc.v:45924.18-45924.128" + wire $reduce_or$libresoc.v:45924$1583_Y + attribute \src "libresoc.v:45926.18-45926.134" + wire $reduce_or$libresoc.v:45926$1585_Y + attribute \src "libresoc.v:45928.18-45928.140" + wire $reduce_or$libresoc.v:45928$1587_Y + attribute \src "libresoc.v:45930.18-45930.90" + wire $reduce_or$libresoc.v:45930$1589_Y + attribute \src "libresoc.v:45931.17-45931.103" + wire $reduce_or$libresoc.v:45931$1590_Y + attribute \src "libresoc.v:45933.17-45933.109" + wire $reduce_or$libresoc.v:45933$1592_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45918$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:45918$1577_Y end - attribute \src "libresoc.v:185298.3-185299.63" - process $proc$libresoc.v:185298$13407 - assign { } { } - assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next - sync posedge \clk - update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45920$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:45920$1579_Y end - attribute \src "libresoc.v:185300.3-185301.37" - process $proc$libresoc.v:185300$13408 - assign { } { } - assign $0\pc_changed[0:0] \pc_changed$next - sync posedge \clk - update \pc_changed $0\pc_changed[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45922$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:45922$1581_Y end - attribute \src "libresoc.v:185302.3-185303.39" - process $proc$libresoc.v:185302$13409 - assign { } { } - assign $0\pc_ok_delay[0:0] \pc_ok_delay$next - sync posedge \clk - update \pc_ok_delay $0\pc_ok_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$libresoc.v:45923$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:45923$1582_Y end - attribute \src "libresoc.v:185304.3-185305.43" - process $proc$libresoc.v:185304$13410 - assign { } { } - assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o - sync posedge \clk - update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45925$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:45925$1584_Y end - attribute \src "libresoc.v:185306.3-185307.27" - process $proc$libresoc.v:185306$13411 - assign { } { } - assign $0\delay[1:0] \delay$next - sync posedge \por_clk - update \delay $0\delay[1:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45927$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:45927$1586_Y end - attribute \src "libresoc.v:185308.3-185309.43" - process $proc$libresoc.v:185308$13412 - assign { } { } - assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next - sync posedge \clk - update \dec2_cur_eint $0\dec2_cur_eint[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45929$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:45929$1588_Y end - attribute \src "libresoc.v:185310.3-185311.47" - process $proc$libresoc.v:185310$13413 - assign { } { } - assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next - sync posedge \clk - update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$libresoc.v:45932$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:45932$1591_Y end - attribute \src "libresoc.v:185312.3-185313.49" - process $proc$libresoc.v:185312$13414 - assign { } { } - assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next - sync posedge \clk - update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45919$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:45919$1578_Y end - attribute \src "libresoc.v:185314.3-185315.39" - process $proc$libresoc.v:185314$13415 - assign { } { } - assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next - sync posedge \clk - update \dbg_dmi_din $0\dbg_dmi_din[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45921$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:45921$1580_Y end - attribute \src "libresoc.v:185316.3-185317.41" - process $proc$libresoc.v:185316$13416 - assign { } { } - assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next - sync posedge \clk - update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45924$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:45924$1583_Y end - attribute \src "libresoc.v:185318.3-185319.37" - process $proc$libresoc.v:185318$13417 - assign { } { } - assign $0\d_cr_delay[0:0] \d_cr_delay$next - sync posedge \clk - update \d_cr_delay $0\d_cr_delay[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45926$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:45926$1585_Y end - attribute \src "libresoc.v:185320.3-185321.43" - process $proc$libresoc.v:185320$13418 - assign { } { } - assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next - sync posedge \clk - update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45928$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:45928$1587_Y end - attribute \src "libresoc.v:185322.3-185323.45" - process $proc$libresoc.v:185322$13419 - assign { } { } - assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next - sync posedge \clk - update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$libresoc.v:45930$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:45930$1589_Y end - attribute \src "libresoc.v:185889.3-185897.6" - process $proc$libresoc.v:185889$13420 - assign { } { } - assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13421 $1\dbg_dmi_addr_i$next[3:0]$13422 - attribute \src "libresoc.v:185890.5-185890.29" - switch \initial - attribute \src "libresoc.v:185890.9-185890.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13422 4'0000 - case - assign $1\dbg_dmi_addr_i$next[3:0]$13422 \jtag_dmi0__addr_i - end - sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13421 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45931$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:45931$1590_Y end - attribute \src "libresoc.v:185898.3-185906.6" - process $proc$libresoc.v:185898$13423 - assign { } { } + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$libresoc.v:45933$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:45933$1592_Y + end + connect \$7 $not$libresoc.v:45918$1577_Y + connect \$12 $reduce_or$libresoc.v:45919$1578_Y + connect \$11 $not$libresoc.v:45920$1579_Y + connect \$16 $reduce_or$libresoc.v:45921$1580_Y + connect \$15 $not$libresoc.v:45922$1581_Y + connect \$1 $not$libresoc.v:45923$1582_Y + connect \$20 $reduce_or$libresoc.v:45924$1583_Y + connect \$19 $not$libresoc.v:45925$1584_Y + connect \$24 $reduce_or$libresoc.v:45926$1585_Y + connect \$23 $not$libresoc.v:45927$1586_Y + connect \$28 $reduce_or$libresoc.v:45928$1587_Y + connect \$27 $not$libresoc.v:45929$1588_Y + connect \$31 $reduce_or$libresoc.v:45930$1589_Y + connect \$4 $reduce_or$libresoc.v:45931$1590_Y + connect \$3 $not$libresoc.v:45932$1591_Y + connect \$8 $reduce_or$libresoc.v:45933$1592_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:45949.1-46764.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:46076.3-46106.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:46107.3-46137.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:45950.7-45950.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:46138.3-46450.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:46451.3-46763.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:46076.3-46106.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:46107.3-46137.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46138.3-46450.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:46451.3-46763.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:45950.7-45950.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:45950.7-45950.20" + process $proc$libresoc.v:45950$1597 assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13424 $1\dbg_dmi_req_i$next[0:0]$13425 - attribute \src "libresoc.v:185899.5-185899.29" - switch \initial - attribute \src "libresoc.v:185899.9-185899.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13425 1'0 - case - assign $1\dbg_dmi_req_i$next[0:0]$13425 \jtag_dmi0__req_i - end + assign $0\initial[0:0] 1'0 sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13424 + update \initial $0\initial[0:0] + sync init end - attribute \src "libresoc.v:185907.3-185927.6" - process $proc$libresoc.v:185907$13426 - assign { } { } + attribute \src "libresoc.v:46076.3-46106.6" + process $proc$libresoc.v:46076$1593 assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13427 $3\dec2_cur_msr$next[63:0]$13430 - attribute \src "libresoc.v:185908.5-185908.29" + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:46077.5-46077.29" switch \initial - attribute \src "libresoc.v:185908.9-185908.17" + attribute \src "libresoc.v:46077.9-46077.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'0000000001 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13428 $2\dec2_cur_msr$next[63:0]$13429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" - switch \$117 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13429 \core_msr__data_o - case - assign $2\dec2_cur_msr$next[63:0]$13429 \dec2_cur_msr - end - case - assign $1\dec2_cur_msr$next[63:0]$13428 \dec2_cur_msr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\fast_o[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000001000 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13430 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_msr$next[63:0]$13430 $1\dec2_cur_msr$next[63:0]$13428 - end - sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13427 - end - attribute \src "libresoc.v:185928.3-185946.6" - process $proc$libresoc.v:185928$13431 - assign { } { } - assign { } { } - assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:185929.5-185929.29" - switch \initial - attribute \src "libresoc.v:185929.9-185929.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\fast_o[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'0000001001 assign { } { } - assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dec2_raw_opcode_in[31:0] 0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dec2_raw_opcode_in[31:0] \$119 - end + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 case - assign $1\dec2_raw_opcode_in[31:0] 0 + assign $1\fast_o[2:0] 3'000 end sync always - update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:185947.3-185978.6" - process $proc$libresoc.v:185947$13432 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:46107.3-46137.6" + process $proc$libresoc.v:46107$1594 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_core_pc$next[63:0]$13433 $3\core_core_pc$next[63:0]$13445 - assign $0\core_dec$next[63:0]$13434 $3\core_dec$next[63:0]$13446 - assign $0\core_eint$next[0:0]$13435 $3\core_eint$next[0:0]$13447 - assign $0\core_msr$next[63:0]$13436 $3\core_msr$next[63:0]$13448 - attribute \src "libresoc.v:185948.5-185948.29" + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46108.5-46108.29" switch \initial - attribute \src "libresoc.v:185948.9-185948.17" + attribute \src "libresoc.v:46108.9-46108.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'0000000001 assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 assign { } { } - assign $1\core_core_pc$next[63:0]$13437 $2\core_core_pc$next[63:0]$13441 - assign $1\core_dec$next[63:0]$13438 $2\core_dec$next[63:0]$13442 - assign $1\core_eint$next[0:0]$13439 $2\core_eint$next[0:0]$13443 - assign $1\core_msr$next[63:0]$13440 $2\core_msr$next[63:0]$13444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_core_pc$next[63:0]$13441 \core_core_pc - assign $2\core_dec$next[63:0]$13442 \core_dec - assign $2\core_eint$next[0:0]$13443 \core_eint - assign $2\core_msr$next[63:0]$13444 \core_msr - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_dec$next[63:0]$13442 $2\core_eint$next[0:0]$13443 $2\core_msr$next[63:0]$13444 $2\core_core_pc$next[63:0]$13441 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - end - case - assign $1\core_core_pc$next[63:0]$13437 \core_core_pc - assign $1\core_dec$next[63:0]$13438 \core_dec - assign $1\core_eint$next[0:0]$13439 \core_eint - assign $1\core_msr$next[63:0]$13440 \core_msr - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000011010 assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 assign { } { } - assign $3\core_core_pc$next[63:0]$13445 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13448 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13447 1'0 - assign $3\core_dec$next[63:0]$13446 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast_o_ok[0:0] 1'1 case - assign $3\core_core_pc$next[63:0]$13445 $1\core_core_pc$next[63:0]$13437 - assign $3\core_dec$next[63:0]$13446 $1\core_dec$next[63:0]$13438 - assign $3\core_eint$next[0:0]$13447 $1\core_eint$next[0:0]$13439 - assign $3\core_msr$next[63:0]$13448 $1\core_msr$next[63:0]$13440 + assign $1\fast_o_ok[0:0] 1'0 end sync always - update \core_core_pc$next $0\core_core_pc$next[63:0]$13433 - update \core_dec$next $0\core_dec$next[63:0]$13434 - update \core_eint$next $0\core_eint$next[0:0]$13435 - update \core_msr$next $0\core_msr$next[63:0]$13436 + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:185979.3-186002.6" - process $proc$libresoc.v:185979$13449 - assign { } { } + attribute \src "libresoc.v:46138.3-46450.6" + process $proc$libresoc.v:46138$1595 assign { } { } assign { } { } - assign $0\ilatch$next[31:0]$13450 $3\ilatch$next[31:0]$13453 - attribute \src "libresoc.v:185980.5-185980.29" + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:46139.5-46139.29" switch \initial - attribute \src "libresoc.v:185980.9-185980.17" + attribute \src "libresoc.v:46139.9-46139.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'0000000011 assign { } { } - assign $1\ilatch$next[31:0]$13451 $2\ilatch$next[31:0]$13452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\ilatch$next[31:0]$13452 \ilatch - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\ilatch$next[31:0]$13452 \$123 - end - case - assign $1\ilatch$next[31:0]$13451 \ilatch - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o[9:0] 10'0000000001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000001101 assign { } { } - assign $3\ilatch$next[31:0]$13453 0 - case - assign $3\ilatch$next[31:0]$13453 $1\ilatch$next[31:0]$13451 - end - sync always - update \ilatch$next $0\ilatch$next[31:0]$13450 - end - attribute \src "libresoc.v:186003.3-186022.6" - process $proc$libresoc.v:186003$13454 - assign { } { } - assign { } { } - assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:186004.5-186004.29" - switch \initial - attribute \src "libresoc.v:186004.9-186004.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o[9:0] 10'0000000100 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 10'0000010001 assign { } { } - assign $1\core_ivalid_i[0:0] 1'1 + assign $1\spr_o[9:0] 10'0000000101 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'0000010010 assign { } { } - assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:306" - switch \$127 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_ivalid_i[0:0] 1'1 - case - assign $2\core_ivalid_i[0:0] 1'0 - end - case - assign $1\core_ivalid_i[0:0] 1'0 - end - sync always - update \core_ivalid_i $0\core_ivalid_i[0:0] - end - attribute \src "libresoc.v:186023.3-186033.6" - process $proc$libresoc.v:186023$13455 - assign { } { } - assign { } { } - assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:186024.5-186024.29" - switch \initial - attribute \src "libresoc.v:186024.9-186024.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o[9:0] 10'0000000110 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 10'0000010011 assign { } { } - assign $1\core_issue_i[0:0] 1'1 - case - assign $1\core_issue_i[0:0] 1'0 - end - sync always - update \core_issue_i $0\core_issue_i[0:0] - end - attribute \src "libresoc.v:186034.3-186043.6" - process $proc$libresoc.v:186034$13456 - assign { } { } - assign { } { } - assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:186035.5-186035.29" - switch \initial - attribute \src "libresoc.v:186035.9-186035.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" - switch \dbg_d_gpr_req + assign $1\spr_o[9:0] 10'0000000111 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000011100 assign { } { } - assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] - case - assign $1\core_dmi__addr[4:0] 5'00000 - end - sync always - update \core_dmi__addr $0\core_dmi__addr[4:0] - end - attribute \src "libresoc.v:186044.3-186053.6" - process $proc$libresoc.v:186044$13457 - assign { } { } - assign { } { } - assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:186045.5-186045.29" - switch \initial - attribute \src "libresoc.v:186045.9-186045.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" - switch \dbg_d_gpr_req + assign $1\spr_o[9:0] 10'0000001011 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000011101 assign { } { } - assign $1\core_dmi__ren[0:0] 1'1 - case - assign $1\core_dmi__ren[0:0] 1'0 - end - sync always - update \core_dmi__ren $0\core_dmi__ren[0:0] - end - attribute \src "libresoc.v:186054.3-186062.6" - process $proc$libresoc.v:186054$13458 - assign { } { } - assign { } { } - assign $0\d_reg_delay$next[0:0]$13459 $1\d_reg_delay$next[0:0]$13460 - attribute \src "libresoc.v:186055.5-186055.29" - switch \initial - attribute \src "libresoc.v:186055.9-186055.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o[9:0] 10'0000001100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000110000 assign { } { } - assign $1\d_reg_delay$next[0:0]$13460 1'0 - case - assign $1\d_reg_delay$next[0:0]$13460 \dbg_d_gpr_req - end - sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13459 - end - attribute \src "libresoc.v:186063.3-186072.6" - process $proc$libresoc.v:186063$13461 - assign { } { } - assign { } { } - assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:186064.5-186064.29" - switch \initial - attribute \src "libresoc.v:186064.9-186064.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:334" - switch \d_reg_delay + assign $1\spr_o[9:0] 10'0000001101 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000111101 assign { } { } - assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o - case - assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] - end - attribute \src "libresoc.v:186073.3-186082.6" - process $proc$libresoc.v:186073$13462 - assign { } { } - assign { } { } - assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:186074.5-186074.29" - switch \initial - attribute \src "libresoc.v:186074.9-186074.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:334" - switch \d_reg_delay + assign $1\spr_o[9:0] 10'0000001110 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0010000000 assign { } { } - assign $1\dbg_d_gpr_ack[0:0] 1'1 - case - assign $1\dbg_d_gpr_ack[0:0] 1'0 - end - sync always - update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] - end - attribute \src "libresoc.v:186083.3-186092.6" - process $proc$libresoc.v:186083$13463 - assign { } { } - assign { } { } - assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:186084.5-186084.29" - switch \initial - attribute \src "libresoc.v:186084.9-186084.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" - switch \dbg_d_cr_req + assign $1\spr_o[9:0] 10'0000001111 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0010000001 assign { } { } - assign $1\core_full_rd2__ren[7:0] 8'11111111 - case - assign $1\core_full_rd2__ren[7:0] 8'00000000 - end - sync always - update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] - end - attribute \src "libresoc.v:186093.3-186101.6" - process $proc$libresoc.v:186093$13464 - assign { } { } - assign { } { } - assign $0\d_cr_delay$next[0:0]$13465 $1\d_cr_delay$next[0:0]$13466 - attribute \src "libresoc.v:186094.5-186094.29" - switch \initial - attribute \src "libresoc.v:186094.9-186094.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o[9:0] 10'0000010000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0010000010 assign { } { } - assign $1\d_cr_delay$next[0:0]$13466 1'0 - case - assign $1\d_cr_delay$next[0:0]$13466 \dbg_d_cr_req - end - sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13465 - end - attribute \src "libresoc.v:186102.3-186111.6" - process $proc$libresoc.v:186102$13467 - assign { } { } - assign { } { } - assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:186103.5-186103.29" - switch \initial - attribute \src "libresoc.v:186103.9-186103.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" - switch \d_cr_delay + assign $1\spr_o[9:0] 10'0000010001 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0010000011 assign { } { } - assign $1\dbg_d_cr_data[63:0] \$129 - case - assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] - end - attribute \src "libresoc.v:186112.3-186121.6" - process $proc$libresoc.v:186112$13468 - assign { } { } - assign { } { } - assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:186113.5-186113.29" - switch \initial - attribute \src "libresoc.v:186113.9-186113.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:344" - switch \d_cr_delay + assign $1\spr_o[9:0] 10'0000010010 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0010001000 assign { } { } - assign $1\dbg_d_cr_ack[0:0] 1'1 - case - assign $1\dbg_d_cr_ack[0:0] 1'0 - end - sync always - update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] - end - attribute \src "libresoc.v:186122.3-186131.6" - process $proc$libresoc.v:186122$13469 - assign { } { } - assign { } { } - assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:186123.5-186123.29" - switch \initial - attribute \src "libresoc.v:186123.9-186123.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" - switch \dbg_d_xer_req + assign $1\spr_o[9:0] 10'0000010011 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 assign { } { } - assign $1\core_full_rd__ren[2:0] 3'111 + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 case - assign $1\core_full_rd__ren[2:0] 3'000 + assign $1\spr_o[9:0] 10'0000000000 end sync always - update \core_full_rd__ren $0\core_full_rd__ren[2:0] + update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:186132.3-186140.6" - process $proc$libresoc.v:186132$13470 + attribute \src "libresoc.v:46451.3-46763.6" + process $proc$libresoc.v:46451$1596 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13471 $1\d_xer_delay$next[0:0]$13472 - attribute \src "libresoc.v:186133.5-186133.29" + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:46452.5-46452.29" switch \initial - attribute \src "libresoc.v:186133.9-186133.17" + attribute \src "libresoc.v:46452.9-46452.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100100000 assign { } { } - assign $1\d_xer_delay$next[0:0]$13472 1'0 - case - assign $1\d_xer_delay$next[0:0]$13472 \dbg_d_xer_req - end - sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13471 - end - attribute \src "libresoc.v:186141.3-186150.6" - process $proc$libresoc.v:186141$13473 - assign { } { } - assign { } { } - assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:186142.5-186142.29" - switch \initial - attribute \src "libresoc.v:186142.9-186142.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" - switch \d_xer_delay + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100100001 assign { } { } - assign $1\dbg_d_xer_data[63:0] \$131 - case - assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] - end - attribute \src "libresoc.v:186151.3-186160.6" - process $proc$libresoc.v:186151$13474 - assign { } { } - assign { } { } - assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:186152.5-186152.29" - switch \initial - attribute \src "libresoc.v:186152.9-186152.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" - switch \d_xer_delay + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100100010 assign { } { } - assign $1\dbg_d_xer_ack[0:0] 1'1 - case - assign $1\dbg_d_xer_ack[0:0] 1'0 - end - sync always - update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] - end - attribute \src "libresoc.v:186161.3-186175.6" - process $proc$libresoc.v:186161$13475 - assign { } { } - assign { } { } - assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:186162.5-186162.29" - switch \initial - attribute \src "libresoc.v:186162.9-186162.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100100011 assign { } { } - assign $1\core_issue__addr[2:0] 3'110 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 10'1100100100 assign { } { } - assign $1\core_issue__addr[2:0] 3'111 - case - assign $1\core_issue__addr[2:0] 3'000 - end - sync always - update \core_issue__addr $0\core_issue__addr[2:0] - end - attribute \src "libresoc.v:186176.3-186190.6" - process $proc$libresoc.v:186176$13476 - assign { } { } - assign { } { } - assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:186177.5-186177.29" - switch \initial - attribute \src "libresoc.v:186177.9-186177.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100100101 assign { } { } - assign $1\core_issue__ren[0:0] 1'1 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 10'1100100110 assign { } { } - assign $1\core_issue__ren[0:0] 1'1 - case - assign $1\core_issue__ren[0:0] 1'0 - end - sync always - update \core_issue__ren $0\core_issue__ren[0:0] - end - attribute \src "libresoc.v:186191.3-186218.6" - process $proc$libresoc.v:186191$13477 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$133$next[1:0]$13478 $2\fsm_state$133$next[1:0]$13480 - attribute \src "libresoc.v:186192.5-186192.29" - switch \initial - attribute \src "libresoc.v:186192.9-186192.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100101000 assign { } { } - assign $1\fsm_state$133$next[1:0]$13479 2'01 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100101001 assign { } { } - assign $1\fsm_state$133$next[1:0]$13479 2'10 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 10'1100101010 assign { } { } - assign $1\fsm_state$133$next[1:0]$13479 2'11 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1100101011 assign { } { } - assign $1\fsm_state$133$next[1:0]$13479 2'00 - case - assign $1\fsm_state$133$next[1:0]$13479 \fsm_state$133 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100110000 assign { } { } - assign $2\fsm_state$133$next[1:0]$13480 2'00 - case - assign $2\fsm_state$133$next[1:0]$13480 $1\fsm_state$133$next[1:0]$13479 - end - sync always - update \fsm_state$133$next $0\fsm_state$133$next[1:0]$13478 - end - attribute \src "libresoc.v:186219.3-186229.6" - process $proc$libresoc.v:186219$13481 - assign { } { } - assign { } { } - assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:186220.5-186220.29" - switch \initial - attribute \src "libresoc.v:186220.9-186220.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100110111 assign { } { } - assign $1\new_dec[63:0] \$134 [63:0] - case - assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \new_dec $0\new_dec[63:0] - end - attribute \src "libresoc.v:186230.3-186244.6" - process $proc$libresoc.v:186230$13482 - assign { } { } - assign { } { } - assign $0\core_issue__addr$11[2:0]$13483 $1\core_issue__addr$11[2:0]$13484 - attribute \src "libresoc.v:186231.5-186231.29" - switch \initial - attribute \src "libresoc.v:186231.9-186231.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1101010000 assign { } { } - assign $1\core_issue__addr$11[2:0]$13484 3'110 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1101010001 assign { } { } - assign $1\core_issue__addr$11[2:0]$13484 3'111 - case - assign $1\core_issue__addr$11[2:0]$13484 3'000 - end - sync always - update \core_issue__addr$11 $0\core_issue__addr$11[2:0]$13483 - end - attribute \src "libresoc.v:186245.3-186259.6" - process $proc$libresoc.v:186245$13485 - assign { } { } - assign { } { } - assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:186246.5-186246.29" - switch \initial - attribute \src "libresoc.v:186246.9-186246.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1101010111 assign { } { } - assign $1\core_issue__wen[0:0] 1'1 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1110000000 assign { } { } - assign $1\core_issue__wen[0:0] 1'1 - case - assign $1\core_issue__wen[0:0] 1'0 - end - sync always - update \core_issue__wen $0\core_issue__wen[0:0] - end - attribute \src "libresoc.v:186260.3-186274.6" - process $proc$libresoc.v:186260$13486 - assign { } { } - assign { } { } - assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:186261.5-186261.29" - switch \initial - attribute \src "libresoc.v:186261.9-186261.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1110000010 assign { } { } - assign $1\core_issue__data_i[63:0] \new_dec + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1111111111 assign { } { } - assign $1\core_issue__data_i[63:0] \new_tb + assign $1\spr_o_ok[0:0] 1'1 case - assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr_o_ok[0:0] 1'0 end sync always - update \core_issue__data_i $0\core_issue__data_i[63:0] + update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:186275.3-186290.6" - process $proc$libresoc.v:186275$13487 +end +attribute \src "libresoc.v:46768.1-47583.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$2 + attribute \src "libresoc.v:46895.3-46925.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:46926.3-46956.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:46769.7-46769.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:46957.3-47269.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:47270.3-47582.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:46895.3-46925.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:46926.3-46956.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46957.3-47269.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:47270.3-47582.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:46769.7-46769.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:46769.7-46769.20" + process $proc$libresoc.v:46769$1602 assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:46895.3-46925.6" + process $proc$libresoc.v:46895$1598 assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13488 $2\dec2_cur_dec$next[63:0]$13490 - attribute \src "libresoc.v:186276.5-186276.29" + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:46896.5-46896.29" switch \initial - attribute \src "libresoc.v:186276.9-186276.17" + attribute \src "libresoc.v:46896.9-46896.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'0000000001 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13489 \new_dec - case - assign $1\dec2_cur_dec$next[63:0]$13489 \dec2_cur_dec - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\fast_o[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000001000 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13490 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\dec2_cur_dec$next[63:0]$13490 $1\dec2_cur_dec$next[63:0]$13489 - end - sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13488 - end - attribute \src "libresoc.v:186291.3-186301.6" - process $proc$libresoc.v:186291$13491 - assign { } { } - assign { } { } - assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:186292.5-186292.29" - switch \initial - attribute \src "libresoc.v:186292.9-186292.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:380" - switch \fsm_state$133 + assign $1\fast_o[2:0] 3'001 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'0000001001 assign { } { } - assign $1\new_tb[63:0] \$137 [63:0] - case - assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \new_tb $0\new_tb[63:0] - end - attribute \src "libresoc.v:186302.3-186310.6" - process $proc$libresoc.v:186302$13492 - assign { } { } - assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13493 $1\dbg_dmi_we_i$next[0:0]$13494 - attribute \src "libresoc.v:186303.5-186303.29" - switch \initial - attribute \src "libresoc.v:186303.9-186303.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000010110 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13494 1'0 - case - assign $1\dbg_dmi_we_i$next[0:0]$13494 \jtag_dmi0__we_i - end - sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13493 - end - attribute \src "libresoc.v:186311.3-186319.6" - process $proc$libresoc.v:186311$13495 - assign { } { } - assign { } { } - assign $0\pc_ok_delay$next[0:0]$13496 $1\pc_ok_delay$next[0:0]$13497 - attribute \src "libresoc.v:186312.5-186312.29" - switch \initial - attribute \src "libresoc.v:186312.9-186312.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\fast_o[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000011010 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13497 1'0 - case - assign $1\pc_ok_delay$next[0:0]$13497 \$39 - end - sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13496 - end - attribute \src "libresoc.v:186320.3-186335.6" - process $proc$libresoc.v:186320$13498 - assign { } { } - assign { } { } - assign { } { } - assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:186321.5-186321.29" - switch \initial - attribute \src "libresoc.v:186321.9-186321.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - switch \pc_i_ok + assign $1\fast_o[2:0] 3'011 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000011011 assign { } { } - assign $1\pc[63:0] \pc_i - case - assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:213" - switch \pc_ok_delay + assign $1\fast_o[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 assign { } { } - assign $2\pc[63:0] \core_cia__data_o + assign $1\fast_o[2:0] 3'010 case - assign $2\pc[63:0] $1\pc[63:0] + assign $1\fast_o[2:0] 3'000 end sync always - update \pc $0\pc[63:0] + update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:186336.3-186348.6" - process $proc$libresoc.v:186336$13499 + attribute \src "libresoc.v:46926.3-46956.6" + process $proc$libresoc.v:46926$1599 assign { } { } assign { } { } - assign $0\core_cia__ren[3:0] $1\core_cia__ren[3:0] - attribute \src "libresoc.v:186337.5-186337.29" + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:46927.5-46927.29" switch \initial - attribute \src "libresoc.v:186337.9-186337.17" + attribute \src "libresoc.v:46927.9-46927.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" - switch \pc_i_ok - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $1\core_cia__ren[3:0] 4'0000 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i attribute \src "libresoc.v:0.0-0.0" - case + case 10'0000000001 assign { } { } - assign $1\core_cia__ren[3:0] 4'0001 - end - sync always - update \core_cia__ren $0\core_cia__ren[3:0] - end - attribute \src "libresoc.v:186349.3-186369.6" - process $proc$libresoc.v:186349$13500 - assign { } { } - assign { } { } - assign $0\core_wen[3:0] $1\core_wen[3:0] - attribute \src "libresoc.v:186350.5-186350.29" - switch \initial - attribute \src "libresoc.v:186350.9-186350.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'0000001000 assign { } { } - assign $1\core_wen[3:0] $2\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - switch \$41 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_wen[3:0] $3\core_wen[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - switch \$43 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_wen[3:0] 4'0001 - case - assign $3\core_wen[3:0] 4'0000 - end - case - assign $2\core_wen[3:0] 4'0000 - end - case - assign $1\core_wen[3:0] 4'0000 - end - sync always - update \core_wen $0\core_wen[3:0] - end - attribute \src "libresoc.v:186370.3-186390.6" - process $proc$libresoc.v:186370$13501 - assign { } { } - assign { } { } - assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:186371.5-186371.29" - switch \initial - attribute \src "libresoc.v:186371.9-186371.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'0000001001 assign { } { } - assign $1\core_data_i[63:0] $2\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - switch \$45 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_data_i[63:0] $3\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" - switch \$47 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_data_i[63:0] \nia - case - assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - case - assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync always - update \core_data_i $0\core_data_i[63:0] - end - attribute \src "libresoc.v:186391.3-186406.6" - process $proc$libresoc.v:186391$13502 - assign { } { } - assign { } { } - assign $0\core_msr__ren[3:0] $1\core_msr__ren[3:0] - attribute \src "libresoc.v:186392.5-186392.29" - switch \initial - attribute \src "libresoc.v:186392.9-186392.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'0000010110 assign { } { } - assign $1\core_msr__ren[3:0] $2\core_msr__ren[3:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$53 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\core_msr__ren[3:0] 4'0010 - case - assign $2\core_msr__ren[3:0] 4'0000 - end - case - assign $1\core_msr__ren[3:0] 4'0000 - end - sync always - update \core_msr__ren $0\core_msr__ren[3:0] - end - attribute \src "libresoc.v:186407.3-186415.6" - process $proc$libresoc.v:186407$13503 - assign { } { } - assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13504 $1\dbg_dmi_din$next[63:0]$13505 - attribute \src "libresoc.v:186408.5-186408.29" - switch \initial - attribute \src "libresoc.v:186408.9-186408.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0000011010 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13505 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\dbg_dmi_din$next[63:0]$13505 \jtag_dmi0__din - end - sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13504 - end - attribute \src "libresoc.v:186416.3-186440.6" - process $proc$libresoc.v:186416$13506 - assign { } { } - assign { } { } - assign { } { } - assign $0\pc_changed$next[0:0]$13507 $3\pc_changed$next[0:0]$13510 - attribute \src "libresoc.v:186417.5-186417.29" - switch \initial - attribute \src "libresoc.v:186417.9-186417.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'0000011011 assign { } { } - assign $1\pc_changed$next[0:0]$13508 1'0 + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'0100001100 assign { } { } - assign $1\pc_changed$next[0:0]$13508 $2\pc_changed$next[0:0]$13509 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:308" - switch \$55 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\pc_changed$next[0:0]$13509 1'1 - case - assign $2\pc_changed$next[0:0]$13509 \pc_changed - end - case - assign $1\pc_changed$next[0:0]$13508 \pc_changed - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100101111 assign { } { } - assign $3\pc_changed$next[0:0]$13510 1'0 + assign $1\fast_o_ok[0:0] 1'1 case - assign $3\pc_changed$next[0:0]$13510 $1\pc_changed$next[0:0]$13508 + assign $1\fast_o_ok[0:0] 1'0 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13507 + update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:186441.3-186563.6" - process $proc$libresoc.v:186441$13511 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_asmcode$next[7:0]$13512 $1\core_asmcode$next[7:0]$13571 - assign $0\core_core_core_cia$next[63:0]$13513 $1\core_core_core_cia$next[63:0]$13572 - assign $0\core_core_core_cr_rd$next[7:0]$13514 $1\core_core_core_cr_rd$next[7:0]$13573 - assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13516 $1\core_core_core_cr_wr$next[7:0]$13575 - assign { } { } - assign { } { } + attribute \src "libresoc.v:46957.3-47269.6" + process $proc$libresoc.v:46957$1600 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_core_core_fn_unit$next[11:0]$13525 $1\core_core_core_fn_unit$next[11:0]$13584 - assign $0\core_core_core_input_carry$next[1:0]$13526 $1\core_core_core_input_carry$next[1:0]$13585 - assign $0\core_core_core_insn$next[31:0]$13527 $1\core_core_core_insn$next[31:0]$13586 - assign $0\core_core_core_insn_type$next[6:0]$13528 $1\core_core_core_insn_type$next[6:0]$13587 - assign $0\core_core_core_is_32bit$next[0:0]$13529 $1\core_core_core_is_32bit$next[0:0]$13588 - assign $0\core_core_core_msr$next[63:0]$13530 $1\core_core_core_msr$next[63:0]$13589 - assign $0\core_core_core_oe$next[0:0]$13531 $1\core_core_core_oe$next[0:0]$13590 - assign { } { } - assign $0\core_core_core_rc$next[0:0]$13533 $1\core_core_core_rc$next[0:0]$13592 - assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$13535 $1\core_core_core_trapaddr$next[12:0]$13594 - assign $0\core_core_core_traptype$next[7:0]$13536 $1\core_core_core_traptype$next[7:0]$13595 - assign $0\core_core_cr_in1$next[2:0]$13537 $1\core_core_cr_in1$next[2:0]$13596 - assign { } { } - assign $0\core_core_cr_in2$1$next[2:0]$13539 $1\core_core_cr_in2$1$next[2:0]$13598 - assign $0\core_core_cr_in2$next[2:0]$13540 $1\core_core_cr_in2$next[2:0]$13599 - assign { } { } - assign { } { } - assign $0\core_core_cr_out$next[2:0]$13543 $1\core_core_cr_out$next[2:0]$13602 - assign { } { } - assign $0\core_core_ea$next[4:0]$13545 $1\core_core_ea$next[4:0]$13604 - assign $0\core_core_fast1$next[2:0]$13546 $1\core_core_fast1$next[2:0]$13605 - assign { } { } - assign $0\core_core_fast2$next[2:0]$13548 $1\core_core_fast2$next[2:0]$13607 - assign { } { } - assign $0\core_core_fasto1$next[2:0]$13550 $1\core_core_fasto1$next[2:0]$13609 - assign $0\core_core_fasto2$next[2:0]$13551 $1\core_core_fasto2$next[2:0]$13610 - assign $0\core_core_lk$next[0:0]$13552 $1\core_core_lk$next[0:0]$13611 - assign $0\core_core_reg1$next[4:0]$13553 $1\core_core_reg1$next[4:0]$13612 - assign { } { } - assign $0\core_core_reg2$next[4:0]$13555 $1\core_core_reg2$next[4:0]$13614 - assign { } { } - assign $0\core_core_reg3$next[4:0]$13557 $1\core_core_reg3$next[4:0]$13616 - assign { } { } - assign $0\core_core_rego$next[4:0]$13559 $1\core_core_rego$next[4:0]$13618 - assign $0\core_core_spr1$next[9:0]$13560 $1\core_core_spr1$next[9:0]$13619 - assign { } { } - assign $0\core_core_spro$next[9:0]$13562 $1\core_core_spro$next[9:0]$13621 - assign $0\core_core_xer_in$next[2:0]$13563 $1\core_core_xer_in$next[2:0]$13622 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\core_xer_out$next[0:0]$13570 $1\core_xer_out$next[0:0]$13629 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13515 $4\core_core_core_cr_rd_ok$next[0:0]$13748 - assign $0\core_core_core_exc_$signal$3$next[0:0]$13517 $4\core_core_core_exc_$signal$3$next[0:0]$13749 - assign $0\core_core_core_exc_$signal$4$next[0:0]$13518 $4\core_core_core_exc_$signal$4$next[0:0]$13750 - assign $0\core_core_core_exc_$signal$5$next[0:0]$13519 $4\core_core_core_exc_$signal$5$next[0:0]$13751 - assign $0\core_core_core_exc_$signal$6$next[0:0]$13520 $4\core_core_core_exc_$signal$6$next[0:0]$13752 - assign $0\core_core_core_exc_$signal$7$next[0:0]$13521 $4\core_core_core_exc_$signal$7$next[0:0]$13753 - assign $0\core_core_core_exc_$signal$8$next[0:0]$13522 $4\core_core_core_exc_$signal$8$next[0:0]$13754 - assign $0\core_core_core_exc_$signal$9$next[0:0]$13523 $4\core_core_core_exc_$signal$9$next[0:0]$13755 - assign $0\core_core_core_exc_$signal$next[0:0]$13524 $4\core_core_core_exc_$signal$next[0:0]$13756 - assign $0\core_core_core_oe_ok$next[0:0]$13532 $4\core_core_core_oe_ok$next[0:0]$13757 - assign $0\core_core_core_rc_ok$next[0:0]$13534 $4\core_core_core_rc_ok$next[0:0]$13758 - assign $0\core_core_cr_in1_ok$next[0:0]$13538 $4\core_core_cr_in1_ok$next[0:0]$13759 - assign $0\core_core_cr_in2_ok$2$next[0:0]$13541 $4\core_core_cr_in2_ok$2$next[0:0]$13760 - assign $0\core_core_cr_in2_ok$next[0:0]$13542 $4\core_core_cr_in2_ok$next[0:0]$13761 - assign $0\core_core_cr_wr_ok$next[0:0]$13544 $4\core_core_cr_wr_ok$next[0:0]$13762 - assign $0\core_core_fast1_ok$next[0:0]$13547 $4\core_core_fast1_ok$next[0:0]$13763 - assign $0\core_core_fast2_ok$next[0:0]$13549 $4\core_core_fast2_ok$next[0:0]$13764 - assign $0\core_core_reg1_ok$next[0:0]$13554 $4\core_core_reg1_ok$next[0:0]$13765 - assign $0\core_core_reg2_ok$next[0:0]$13556 $4\core_core_reg2_ok$next[0:0]$13766 - assign $0\core_core_reg3_ok$next[0:0]$13558 $4\core_core_reg3_ok$next[0:0]$13767 - assign $0\core_core_spr1_ok$next[0:0]$13561 $4\core_core_spr1_ok$next[0:0]$13768 - assign $0\core_cr_out_ok$next[0:0]$13564 $4\core_cr_out_ok$next[0:0]$13769 - assign $0\core_ea_ok$next[0:0]$13565 $4\core_ea_ok$next[0:0]$13770 - assign $0\core_fasto1_ok$next[0:0]$13566 $4\core_fasto1_ok$next[0:0]$13771 - assign $0\core_fasto2_ok$next[0:0]$13567 $4\core_fasto2_ok$next[0:0]$13772 - assign $0\core_rego_ok$next[0:0]$13568 $4\core_rego_ok$next[0:0]$13773 - assign $0\core_spro_ok$next[0:0]$13569 $4\core_spro_ok$next[0:0]$13774 - attribute \src "libresoc.v:186442.5-186442.29" + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:46958.5-46958.29" switch \initial - attribute \src "libresoc.v:186442.9-186442.17" + attribute \src "libresoc.v:46958.9-46958.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + case 10'0000000011 assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$13588 $1\core_core_cr_wr_ok$next[0:0]$13603 $1\core_core_core_cr_wr$next[7:0]$13575 $1\core_core_core_cr_rd_ok$next[0:0]$13574 $1\core_core_core_cr_rd$next[7:0]$13573 $1\core_core_core_trapaddr$next[12:0]$13594 $1\core_core_core_exc_$signal$9$next[0:0]$13582 $1\core_core_core_exc_$signal$8$next[0:0]$13581 $1\core_core_core_exc_$signal$7$next[0:0]$13580 $1\core_core_core_exc_$signal$6$next[0:0]$13579 $1\core_core_core_exc_$signal$5$next[0:0]$13578 $1\core_core_core_exc_$signal$4$next[0:0]$13577 $1\core_core_core_exc_$signal$3$next[0:0]$13576 $1\core_core_core_exc_$signal$next[0:0]$13583 $1\core_core_core_traptype$next[7:0]$13595 $1\core_core_core_input_carry$next[1:0]$13585 $1\core_core_core_oe_ok$next[0:0]$13591 $1\core_core_core_oe$next[0:0]$13590 $1\core_core_core_rc_ok$next[0:0]$13593 $1\core_core_core_rc$next[0:0]$13592 $1\core_core_lk$next[0:0]$13611 $1\core_core_core_fn_unit$next[11:0]$13584 $1\core_core_core_insn_type$next[6:0]$13587 $1\core_core_core_insn$next[31:0]$13586 $1\core_core_core_cia$next[63:0]$13572 $1\core_core_core_msr$next[63:0]$13589 $1\core_cr_out_ok$next[0:0]$13623 $1\core_core_cr_out$next[2:0]$13602 $1\core_core_cr_in2_ok$2$next[0:0]$13600 $1\core_core_cr_in2$1$next[2:0]$13598 $1\core_core_cr_in2_ok$next[0:0]$13601 $1\core_core_cr_in2$next[2:0]$13599 $1\core_core_cr_in1_ok$next[0:0]$13597 $1\core_core_cr_in1$next[2:0]$13596 $1\core_fasto2_ok$next[0:0]$13626 $1\core_core_fasto2$next[2:0]$13610 $1\core_fasto1_ok$next[0:0]$13625 $1\core_core_fasto1$next[2:0]$13609 $1\core_core_fast2_ok$next[0:0]$13608 $1\core_core_fast2$next[2:0]$13607 $1\core_core_fast1_ok$next[0:0]$13606 $1\core_core_fast1$next[2:0]$13605 $1\core_xer_out$next[0:0]$13629 $1\core_core_xer_in$next[2:0]$13622 $1\core_core_spr1_ok$next[0:0]$13620 $1\core_core_spr1$next[9:0]$13619 $1\core_spro_ok$next[0:0]$13628 $1\core_core_spro$next[9:0]$13621 $1\core_core_reg3_ok$next[0:0]$13617 $1\core_core_reg3$next[4:0]$13616 $1\core_core_reg2_ok$next[0:0]$13615 $1\core_core_reg2$next[4:0]$13614 $1\core_core_reg1_ok$next[0:0]$13613 $1\core_core_reg1$next[4:0]$13612 $1\core_ea_ok$next[0:0]$13624 $1\core_core_ea$next[4:0]$13604 $1\core_rego_ok$next[0:0]$13627 $1\core_core_rego$next[4:0]$13618 $1\core_asmcode$next[7:0]$13571 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr_o[9:0] 10'0000100001 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'0100001101 assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 assign { } { } - assign $1\core_asmcode$next[7:0]$13571 $2\core_asmcode$next[7:0]$13630 - assign $1\core_core_core_cia$next[63:0]$13572 $2\core_core_core_cia$next[63:0]$13631 - assign $1\core_core_core_cr_rd$next[7:0]$13573 $2\core_core_core_cr_rd$next[7:0]$13632 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13574 $2\core_core_core_cr_rd_ok$next[0:0]$13633 - assign $1\core_core_core_cr_wr$next[7:0]$13575 $2\core_core_core_cr_wr$next[7:0]$13634 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13576 $2\core_core_core_exc_$signal$3$next[0:0]$13635 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13577 $2\core_core_core_exc_$signal$4$next[0:0]$13636 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13578 $2\core_core_core_exc_$signal$5$next[0:0]$13637 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13579 $2\core_core_core_exc_$signal$6$next[0:0]$13638 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13580 $2\core_core_core_exc_$signal$7$next[0:0]$13639 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13581 $2\core_core_core_exc_$signal$8$next[0:0]$13640 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13582 $2\core_core_core_exc_$signal$9$next[0:0]$13641 - assign $1\core_core_core_exc_$signal$next[0:0]$13583 $2\core_core_core_exc_$signal$next[0:0]$13642 - assign $1\core_core_core_fn_unit$next[11:0]$13584 $2\core_core_core_fn_unit$next[11:0]$13643 - assign $1\core_core_core_input_carry$next[1:0]$13585 $2\core_core_core_input_carry$next[1:0]$13644 - assign $1\core_core_core_insn$next[31:0]$13586 $2\core_core_core_insn$next[31:0]$13645 - assign $1\core_core_core_insn_type$next[6:0]$13587 $2\core_core_core_insn_type$next[6:0]$13646 - assign $1\core_core_core_is_32bit$next[0:0]$13588 $2\core_core_core_is_32bit$next[0:0]$13647 - assign $1\core_core_core_msr$next[63:0]$13589 $2\core_core_core_msr$next[63:0]$13648 - assign $1\core_core_core_oe$next[0:0]$13590 $2\core_core_core_oe$next[0:0]$13649 - assign $1\core_core_core_oe_ok$next[0:0]$13591 $2\core_core_core_oe_ok$next[0:0]$13650 - assign $1\core_core_core_rc$next[0:0]$13592 $2\core_core_core_rc$next[0:0]$13651 - assign $1\core_core_core_rc_ok$next[0:0]$13593 $2\core_core_core_rc_ok$next[0:0]$13652 - assign $1\core_core_core_trapaddr$next[12:0]$13594 $2\core_core_core_trapaddr$next[12:0]$13653 - assign $1\core_core_core_traptype$next[7:0]$13595 $2\core_core_core_traptype$next[7:0]$13654 - assign $1\core_core_cr_in1$next[2:0]$13596 $2\core_core_cr_in1$next[2:0]$13655 - assign $1\core_core_cr_in1_ok$next[0:0]$13597 $2\core_core_cr_in1_ok$next[0:0]$13656 - assign $1\core_core_cr_in2$1$next[2:0]$13598 $2\core_core_cr_in2$1$next[2:0]$13657 - assign $1\core_core_cr_in2$next[2:0]$13599 $2\core_core_cr_in2$next[2:0]$13658 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13600 $2\core_core_cr_in2_ok$2$next[0:0]$13659 - assign $1\core_core_cr_in2_ok$next[0:0]$13601 $2\core_core_cr_in2_ok$next[0:0]$13660 - assign $1\core_core_cr_out$next[2:0]$13602 $2\core_core_cr_out$next[2:0]$13661 - assign $1\core_core_cr_wr_ok$next[0:0]$13603 $2\core_core_cr_wr_ok$next[0:0]$13662 - assign $1\core_core_ea$next[4:0]$13604 $2\core_core_ea$next[4:0]$13663 - assign $1\core_core_fast1$next[2:0]$13605 $2\core_core_fast1$next[2:0]$13664 - assign $1\core_core_fast1_ok$next[0:0]$13606 $2\core_core_fast1_ok$next[0:0]$13665 - assign $1\core_core_fast2$next[2:0]$13607 $2\core_core_fast2$next[2:0]$13666 - assign $1\core_core_fast2_ok$next[0:0]$13608 $2\core_core_fast2_ok$next[0:0]$13667 - assign $1\core_core_fasto1$next[2:0]$13609 $2\core_core_fasto1$next[2:0]$13668 - assign $1\core_core_fasto2$next[2:0]$13610 $2\core_core_fasto2$next[2:0]$13669 - assign $1\core_core_lk$next[0:0]$13611 $2\core_core_lk$next[0:0]$13670 - assign $1\core_core_reg1$next[4:0]$13612 $2\core_core_reg1$next[4:0]$13671 - assign $1\core_core_reg1_ok$next[0:0]$13613 $2\core_core_reg1_ok$next[0:0]$13672 - assign $1\core_core_reg2$next[4:0]$13614 $2\core_core_reg2$next[4:0]$13673 - assign $1\core_core_reg2_ok$next[0:0]$13615 $2\core_core_reg2_ok$next[0:0]$13674 - assign $1\core_core_reg3$next[4:0]$13616 $2\core_core_reg3$next[4:0]$13675 - assign $1\core_core_reg3_ok$next[0:0]$13617 $2\core_core_reg3_ok$next[0:0]$13676 - assign $1\core_core_rego$next[4:0]$13618 $2\core_core_rego$next[4:0]$13677 - assign $1\core_core_spr1$next[9:0]$13619 $2\core_core_spr1$next[9:0]$13678 - assign $1\core_core_spr1_ok$next[0:0]$13620 $2\core_core_spr1_ok$next[0:0]$13679 - assign $1\core_core_spro$next[9:0]$13621 $2\core_core_spro$next[9:0]$13680 - assign $1\core_core_xer_in$next[2:0]$13622 $2\core_core_xer_in$next[2:0]$13681 - assign $1\core_cr_out_ok$next[0:0]$13623 $2\core_cr_out_ok$next[0:0]$13682 - assign $1\core_ea_ok$next[0:0]$13624 $2\core_ea_ok$next[0:0]$13683 - assign $1\core_fasto1_ok$next[0:0]$13625 $2\core_fasto1_ok$next[0:0]$13684 - assign $1\core_fasto2_ok$next[0:0]$13626 $2\core_fasto2_ok$next[0:0]$13685 - assign $1\core_rego_ok$next[0:0]$13627 $2\core_rego_ok$next[0:0]$13686 - assign $1\core_spro_ok$next[0:0]$13628 $2\core_spro_ok$next[0:0]$13687 - assign $1\core_xer_out$next[0:0]$13629 $2\core_xer_out$next[0:0]$13688 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_asmcode$next[7:0]$13630 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$13631 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$13632 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$13633 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$13634 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$13635 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$13636 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$13637 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$13638 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$13639 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$13640 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$13641 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$13642 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[11:0]$13643 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$13644 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$13645 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$13646 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$13647 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$13648 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$13649 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$13650 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$13651 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$13652 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$13653 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$13654 \core_core_core_traptype - assign $2\core_core_cr_in1$next[2:0]$13655 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$13656 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[2:0]$13657 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[2:0]$13658 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$13659 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$13660 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[2:0]$13661 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$13662 \core_core_cr_wr_ok - assign $2\core_core_ea$next[4:0]$13663 \core_core_ea - assign $2\core_core_fast1$next[2:0]$13664 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$13665 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$13666 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$13667 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$13668 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$13669 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$13670 \core_core_lk - assign $2\core_core_reg1$next[4:0]$13671 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$13672 \core_core_reg1_ok - assign $2\core_core_reg2$next[4:0]$13673 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$13674 \core_core_reg2_ok - assign $2\core_core_reg3$next[4:0]$13675 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$13676 \core_core_reg3_ok - assign $2\core_core_rego$next[4:0]$13677 \core_core_rego - assign $2\core_core_spr1$next[9:0]$13678 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$13679 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$13680 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$13681 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$13682 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$13683 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$13684 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$13685 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$13686 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$13687 \core_spro_ok - assign $2\core_xer_out$next[0:0]$13688 \core_xer_out - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$13647 $2\core_core_cr_wr_ok$next[0:0]$13662 $2\core_core_core_cr_wr$next[7:0]$13634 $2\core_core_core_cr_rd_ok$next[0:0]$13633 $2\core_core_core_cr_rd$next[7:0]$13632 $2\core_core_core_trapaddr$next[12:0]$13653 $2\core_core_core_exc_$signal$9$next[0:0]$13641 $2\core_core_core_exc_$signal$8$next[0:0]$13640 $2\core_core_core_exc_$signal$7$next[0:0]$13639 $2\core_core_core_exc_$signal$6$next[0:0]$13638 $2\core_core_core_exc_$signal$5$next[0:0]$13637 $2\core_core_core_exc_$signal$4$next[0:0]$13636 $2\core_core_core_exc_$signal$3$next[0:0]$13635 $2\core_core_core_exc_$signal$next[0:0]$13642 $2\core_core_core_traptype$next[7:0]$13654 $2\core_core_core_input_carry$next[1:0]$13644 $2\core_core_core_oe_ok$next[0:0]$13650 $2\core_core_core_oe$next[0:0]$13649 $2\core_core_core_rc_ok$next[0:0]$13652 $2\core_core_core_rc$next[0:0]$13651 $2\core_core_lk$next[0:0]$13670 $2\core_core_core_fn_unit$next[11:0]$13643 $2\core_core_core_insn_type$next[6:0]$13646 $2\core_core_core_insn$next[31:0]$13645 $2\core_core_core_cia$next[63:0]$13631 $2\core_core_core_msr$next[63:0]$13648 $2\core_cr_out_ok$next[0:0]$13682 $2\core_core_cr_out$next[2:0]$13661 $2\core_core_cr_in2_ok$2$next[0:0]$13659 $2\core_core_cr_in2$1$next[2:0]$13657 $2\core_core_cr_in2_ok$next[0:0]$13660 $2\core_core_cr_in2$next[2:0]$13658 $2\core_core_cr_in1_ok$next[0:0]$13656 $2\core_core_cr_in1$next[2:0]$13655 $2\core_fasto2_ok$next[0:0]$13685 $2\core_core_fasto2$next[2:0]$13669 $2\core_fasto1_ok$next[0:0]$13684 $2\core_core_fasto1$next[2:0]$13668 $2\core_core_fast2_ok$next[0:0]$13667 $2\core_core_fast2$next[2:0]$13666 $2\core_core_fast1_ok$next[0:0]$13665 $2\core_core_fast1$next[2:0]$13664 $2\core_xer_out$next[0:0]$13688 $2\core_core_xer_in$next[2:0]$13681 $2\core_core_spr1_ok$next[0:0]$13679 $2\core_core_spr1$next[9:0]$13678 $2\core_spro_ok$next[0:0]$13687 $2\core_core_spro$next[9:0]$13680 $2\core_core_reg3_ok$next[0:0]$13676 $2\core_core_reg3$next[4:0]$13675 $2\core_core_reg2_ok$next[0:0]$13674 $2\core_core_reg2$next[4:0]$13673 $2\core_core_reg1_ok$next[0:0]$13672 $2\core_core_reg1$next[4:0]$13671 $2\core_ea_ok$next[0:0]$13683 $2\core_core_ea$next[4:0]$13663 $2\core_rego_ok$next[0:0]$13686 $2\core_core_rego$next[4:0]$13677 $2\core_asmcode$next[7:0]$13630 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$14 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$13 \dec2_cr_in2$12 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } - end + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1100100101 assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:47270.3-47582.6" + process $proc$libresoc.v:47270$1601 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:47271.5-47271.29" + switch \initial + attribute \src "libresoc.v:47271.9-47271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:68" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 assign { } { } - assign $1\core_asmcode$next[7:0]$13571 $3\core_asmcode$next[7:0]$13689 - assign $1\core_core_core_cia$next[63:0]$13572 $3\core_core_core_cia$next[63:0]$13690 - assign $1\core_core_core_cr_rd$next[7:0]$13573 $3\core_core_core_cr_rd$next[7:0]$13691 - assign $1\core_core_core_cr_rd_ok$next[0:0]$13574 $3\core_core_core_cr_rd_ok$next[0:0]$13692 - assign $1\core_core_core_cr_wr$next[7:0]$13575 $3\core_core_core_cr_wr$next[7:0]$13693 - assign $1\core_core_core_exc_$signal$3$next[0:0]$13576 $3\core_core_core_exc_$signal$3$next[0:0]$13694 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13577 $3\core_core_core_exc_$signal$4$next[0:0]$13695 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13578 $3\core_core_core_exc_$signal$5$next[0:0]$13696 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13579 $3\core_core_core_exc_$signal$6$next[0:0]$13697 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13580 $3\core_core_core_exc_$signal$7$next[0:0]$13698 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13581 $3\core_core_core_exc_$signal$8$next[0:0]$13699 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13582 $3\core_core_core_exc_$signal$9$next[0:0]$13700 - assign $1\core_core_core_exc_$signal$next[0:0]$13583 $3\core_core_core_exc_$signal$next[0:0]$13701 - assign $1\core_core_core_fn_unit$next[11:0]$13584 $3\core_core_core_fn_unit$next[11:0]$13702 - assign $1\core_core_core_input_carry$next[1:0]$13585 $3\core_core_core_input_carry$next[1:0]$13703 - assign $1\core_core_core_insn$next[31:0]$13586 $3\core_core_core_insn$next[31:0]$13704 - assign $1\core_core_core_insn_type$next[6:0]$13587 $3\core_core_core_insn_type$next[6:0]$13705 - assign $1\core_core_core_is_32bit$next[0:0]$13588 $3\core_core_core_is_32bit$next[0:0]$13706 - assign $1\core_core_core_msr$next[63:0]$13589 $3\core_core_core_msr$next[63:0]$13707 - assign $1\core_core_core_oe$next[0:0]$13590 $3\core_core_core_oe$next[0:0]$13708 - assign $1\core_core_core_oe_ok$next[0:0]$13591 $3\core_core_core_oe_ok$next[0:0]$13709 - assign $1\core_core_core_rc$next[0:0]$13592 $3\core_core_core_rc$next[0:0]$13710 - assign $1\core_core_core_rc_ok$next[0:0]$13593 $3\core_core_core_rc_ok$next[0:0]$13711 - assign $1\core_core_core_trapaddr$next[12:0]$13594 $3\core_core_core_trapaddr$next[12:0]$13712 - assign $1\core_core_core_traptype$next[7:0]$13595 $3\core_core_core_traptype$next[7:0]$13713 - assign $1\core_core_cr_in1$next[2:0]$13596 $3\core_core_cr_in1$next[2:0]$13714 - assign $1\core_core_cr_in1_ok$next[0:0]$13597 $3\core_core_cr_in1_ok$next[0:0]$13715 - assign $1\core_core_cr_in2$1$next[2:0]$13598 $3\core_core_cr_in2$1$next[2:0]$13716 - assign $1\core_core_cr_in2$next[2:0]$13599 $3\core_core_cr_in2$next[2:0]$13717 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13600 $3\core_core_cr_in2_ok$2$next[0:0]$13718 - assign $1\core_core_cr_in2_ok$next[0:0]$13601 $3\core_core_cr_in2_ok$next[0:0]$13719 - assign $1\core_core_cr_out$next[2:0]$13602 $3\core_core_cr_out$next[2:0]$13720 - assign $1\core_core_cr_wr_ok$next[0:0]$13603 $3\core_core_cr_wr_ok$next[0:0]$13721 - assign $1\core_core_ea$next[4:0]$13604 $3\core_core_ea$next[4:0]$13722 - assign $1\core_core_fast1$next[2:0]$13605 $3\core_core_fast1$next[2:0]$13723 - assign $1\core_core_fast1_ok$next[0:0]$13606 $3\core_core_fast1_ok$next[0:0]$13724 - assign $1\core_core_fast2$next[2:0]$13607 $3\core_core_fast2$next[2:0]$13725 - assign $1\core_core_fast2_ok$next[0:0]$13608 $3\core_core_fast2_ok$next[0:0]$13726 - assign $1\core_core_fasto1$next[2:0]$13609 $3\core_core_fasto1$next[2:0]$13727 - assign $1\core_core_fasto2$next[2:0]$13610 $3\core_core_fasto2$next[2:0]$13728 - assign $1\core_core_lk$next[0:0]$13611 $3\core_core_lk$next[0:0]$13729 - assign $1\core_core_reg1$next[4:0]$13612 $3\core_core_reg1$next[4:0]$13730 - assign $1\core_core_reg1_ok$next[0:0]$13613 $3\core_core_reg1_ok$next[0:0]$13731 - assign $1\core_core_reg2$next[4:0]$13614 $3\core_core_reg2$next[4:0]$13732 - assign $1\core_core_reg2_ok$next[0:0]$13615 $3\core_core_reg2_ok$next[0:0]$13733 - assign $1\core_core_reg3$next[4:0]$13616 $3\core_core_reg3$next[4:0]$13734 - assign $1\core_core_reg3_ok$next[0:0]$13617 $3\core_core_reg3_ok$next[0:0]$13735 - assign $1\core_core_rego$next[4:0]$13618 $3\core_core_rego$next[4:0]$13736 - assign $1\core_core_spr1$next[9:0]$13619 $3\core_core_spr1$next[9:0]$13737 - assign $1\core_core_spr1_ok$next[0:0]$13620 $3\core_core_spr1_ok$next[0:0]$13738 - assign $1\core_core_spro$next[9:0]$13621 $3\core_core_spro$next[9:0]$13739 - assign $1\core_core_xer_in$next[2:0]$13622 $3\core_core_xer_in$next[2:0]$13740 - assign $1\core_cr_out_ok$next[0:0]$13623 $3\core_cr_out_ok$next[0:0]$13741 - assign $1\core_ea_ok$next[0:0]$13624 $3\core_ea_ok$next[0:0]$13742 - assign $1\core_fasto1_ok$next[0:0]$13625 $3\core_fasto1_ok$next[0:0]$13743 - assign $1\core_fasto2_ok$next[0:0]$13626 $3\core_fasto2_ok$next[0:0]$13744 - assign $1\core_rego_ok$next[0:0]$13627 $3\core_rego_ok$next[0:0]$13745 - assign $1\core_spro_ok$next[0:0]$13628 $3\core_spro_ok$next[0:0]$13746 - assign $1\core_xer_out$next[0:0]$13629 $3\core_xer_out$next[0:0]$13747 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - switch \$59 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $3\core_core_core_is_32bit$next[0:0]$13706 $3\core_core_cr_wr_ok$next[0:0]$13721 $3\core_core_core_cr_wr$next[7:0]$13693 $3\core_core_core_cr_rd_ok$next[0:0]$13692 $3\core_core_core_cr_rd$next[7:0]$13691 $3\core_core_core_trapaddr$next[12:0]$13712 $3\core_core_core_exc_$signal$9$next[0:0]$13700 $3\core_core_core_exc_$signal$8$next[0:0]$13699 $3\core_core_core_exc_$signal$7$next[0:0]$13698 $3\core_core_core_exc_$signal$6$next[0:0]$13697 $3\core_core_core_exc_$signal$5$next[0:0]$13696 $3\core_core_core_exc_$signal$4$next[0:0]$13695 $3\core_core_core_exc_$signal$3$next[0:0]$13694 $3\core_core_core_exc_$signal$next[0:0]$13701 $3\core_core_core_traptype$next[7:0]$13713 $3\core_core_core_input_carry$next[1:0]$13703 $3\core_core_core_oe_ok$next[0:0]$13709 $3\core_core_core_oe$next[0:0]$13708 $3\core_core_core_rc_ok$next[0:0]$13711 $3\core_core_core_rc$next[0:0]$13710 $3\core_core_lk$next[0:0]$13729 $3\core_core_core_fn_unit$next[11:0]$13702 $3\core_core_core_insn_type$next[6:0]$13705 $3\core_core_core_insn$next[31:0]$13704 $3\core_core_core_cia$next[63:0]$13690 $3\core_core_core_msr$next[63:0]$13707 $3\core_cr_out_ok$next[0:0]$13741 $3\core_core_cr_out$next[2:0]$13720 $3\core_core_cr_in2_ok$2$next[0:0]$13718 $3\core_core_cr_in2$1$next[2:0]$13716 $3\core_core_cr_in2_ok$next[0:0]$13719 $3\core_core_cr_in2$next[2:0]$13717 $3\core_core_cr_in1_ok$next[0:0]$13715 $3\core_core_cr_in1$next[2:0]$13714 $3\core_fasto2_ok$next[0:0]$13744 $3\core_core_fasto2$next[2:0]$13728 $3\core_fasto1_ok$next[0:0]$13743 $3\core_core_fasto1$next[2:0]$13727 $3\core_core_fast2_ok$next[0:0]$13726 $3\core_core_fast2$next[2:0]$13725 $3\core_core_fast1_ok$next[0:0]$13724 $3\core_core_fast1$next[2:0]$13723 $3\core_xer_out$next[0:0]$13747 $3\core_core_xer_in$next[2:0]$13740 $3\core_core_spr1_ok$next[0:0]$13738 $3\core_core_spr1$next[9:0]$13737 $3\core_spro_ok$next[0:0]$13746 $3\core_core_spro$next[9:0]$13739 $3\core_core_reg3_ok$next[0:0]$13735 $3\core_core_reg3$next[4:0]$13734 $3\core_core_reg2_ok$next[0:0]$13733 $3\core_core_reg2$next[4:0]$13732 $3\core_core_reg1_ok$next[0:0]$13731 $3\core_core_reg1$next[4:0]$13730 $3\core_ea_ok$next[0:0]$13742 $3\core_core_ea$next[4:0]$13722 $3\core_rego_ok$next[0:0]$13745 $3\core_core_rego$next[4:0]$13736 $3\core_asmcode$next[7:0]$13689 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\core_asmcode$next[7:0]$13689 \core_asmcode - assign $3\core_core_core_cia$next[63:0]$13690 \core_core_core_cia - assign $3\core_core_core_cr_rd$next[7:0]$13691 \core_core_core_cr_rd - assign $3\core_core_core_cr_rd_ok$next[0:0]$13692 \core_core_core_cr_rd_ok - assign $3\core_core_core_cr_wr$next[7:0]$13693 \core_core_core_cr_wr - assign $3\core_core_core_exc_$signal$3$next[0:0]$13694 \core_core_core_exc_$signal$3 - assign $3\core_core_core_exc_$signal$4$next[0:0]$13695 \core_core_core_exc_$signal$4 - assign $3\core_core_core_exc_$signal$5$next[0:0]$13696 \core_core_core_exc_$signal$5 - assign $3\core_core_core_exc_$signal$6$next[0:0]$13697 \core_core_core_exc_$signal$6 - assign $3\core_core_core_exc_$signal$7$next[0:0]$13698 \core_core_core_exc_$signal$7 - assign $3\core_core_core_exc_$signal$8$next[0:0]$13699 \core_core_core_exc_$signal$8 - assign $3\core_core_core_exc_$signal$9$next[0:0]$13700 \core_core_core_exc_$signal$9 - assign $3\core_core_core_exc_$signal$next[0:0]$13701 \core_core_core_exc_$signal - assign $3\core_core_core_fn_unit$next[11:0]$13702 \core_core_core_fn_unit - assign $3\core_core_core_input_carry$next[1:0]$13703 \core_core_core_input_carry - assign $3\core_core_core_insn$next[31:0]$13704 \core_core_core_insn - assign $3\core_core_core_insn_type$next[6:0]$13705 \core_core_core_insn_type - assign $3\core_core_core_is_32bit$next[0:0]$13706 \core_core_core_is_32bit - assign $3\core_core_core_msr$next[63:0]$13707 \core_core_core_msr - assign $3\core_core_core_oe$next[0:0]$13708 \core_core_core_oe - assign $3\core_core_core_oe_ok$next[0:0]$13709 \core_core_core_oe_ok - assign $3\core_core_core_rc$next[0:0]$13710 \core_core_core_rc - assign $3\core_core_core_rc_ok$next[0:0]$13711 \core_core_core_rc_ok - assign $3\core_core_core_trapaddr$next[12:0]$13712 \core_core_core_trapaddr - assign $3\core_core_core_traptype$next[7:0]$13713 \core_core_core_traptype - assign $3\core_core_cr_in1$next[2:0]$13714 \core_core_cr_in1 - assign $3\core_core_cr_in1_ok$next[0:0]$13715 \core_core_cr_in1_ok - assign $3\core_core_cr_in2$1$next[2:0]$13716 \core_core_cr_in2$1 - assign $3\core_core_cr_in2$next[2:0]$13717 \core_core_cr_in2 - assign $3\core_core_cr_in2_ok$2$next[0:0]$13718 \core_core_cr_in2_ok$2 - assign $3\core_core_cr_in2_ok$next[0:0]$13719 \core_core_cr_in2_ok - assign $3\core_core_cr_out$next[2:0]$13720 \core_core_cr_out - assign $3\core_core_cr_wr_ok$next[0:0]$13721 \core_core_cr_wr_ok - assign $3\core_core_ea$next[4:0]$13722 \core_core_ea - assign $3\core_core_fast1$next[2:0]$13723 \core_core_fast1 - assign $3\core_core_fast1_ok$next[0:0]$13724 \core_core_fast1_ok - assign $3\core_core_fast2$next[2:0]$13725 \core_core_fast2 - assign $3\core_core_fast2_ok$next[0:0]$13726 \core_core_fast2_ok - assign $3\core_core_fasto1$next[2:0]$13727 \core_core_fasto1 - assign $3\core_core_fasto2$next[2:0]$13728 \core_core_fasto2 - assign $3\core_core_lk$next[0:0]$13729 \core_core_lk - assign $3\core_core_reg1$next[4:0]$13730 \core_core_reg1 - assign $3\core_core_reg1_ok$next[0:0]$13731 \core_core_reg1_ok - assign $3\core_core_reg2$next[4:0]$13732 \core_core_reg2 - assign $3\core_core_reg2_ok$next[0:0]$13733 \core_core_reg2_ok - assign $3\core_core_reg3$next[4:0]$13734 \core_core_reg3 - assign $3\core_core_reg3_ok$next[0:0]$13735 \core_core_reg3_ok - assign $3\core_core_rego$next[4:0]$13736 \core_core_rego - assign $3\core_core_spr1$next[9:0]$13737 \core_core_spr1 - assign $3\core_core_spr1_ok$next[0:0]$13738 \core_core_spr1_ok - assign $3\core_core_spro$next[9:0]$13739 \core_core_spro - assign $3\core_core_xer_in$next[2:0]$13740 \core_core_xer_in - assign $3\core_cr_out_ok$next[0:0]$13741 \core_cr_out_ok - assign $3\core_ea_ok$next[0:0]$13742 \core_ea_ok - assign $3\core_fasto1_ok$next[0:0]$13743 \core_fasto1_ok - assign $3\core_fasto2_ok$next[0:0]$13744 \core_fasto2_ok - assign $3\core_rego_ok$next[0:0]$13745 \core_rego_ok - assign $3\core_spro_ok$next[0:0]$13746 \core_spro_ok - assign $3\core_xer_out$next[0:0]$13747 \core_xer_out - end - case - assign $1\core_asmcode$next[7:0]$13571 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$13572 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$13573 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$13574 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$13575 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$13576 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$13577 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$13578 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$13579 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$13580 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$13581 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$13582 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$13583 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[11:0]$13584 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$13585 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$13586 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$13587 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$13588 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$13589 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$13590 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$13591 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$13592 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$13593 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$13594 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$13595 \core_core_core_traptype - assign $1\core_core_cr_in1$next[2:0]$13596 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$13597 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[2:0]$13598 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[2:0]$13599 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$13600 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$13601 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[2:0]$13602 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$13603 \core_core_cr_wr_ok - assign $1\core_core_ea$next[4:0]$13604 \core_core_ea - assign $1\core_core_fast1$next[2:0]$13605 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$13606 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$13607 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$13608 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$13609 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$13610 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$13611 \core_core_lk - assign $1\core_core_reg1$next[4:0]$13612 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$13613 \core_core_reg1_ok - assign $1\core_core_reg2$next[4:0]$13614 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$13615 \core_core_reg2_ok - assign $1\core_core_reg3$next[4:0]$13616 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$13617 \core_core_reg3_ok - assign $1\core_core_rego$next[4:0]$13618 \core_core_rego - assign $1\core_core_spr1$next[9:0]$13619 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$13620 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$13621 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$13622 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$13623 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$13624 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$13625 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$13626 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$13627 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$13628 \core_spro_ok - assign $1\core_xer_out$next[0:0]$13629 \core_xer_out - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'0100111001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 assign { } { } - assign $4\core_rego_ok$next[0:0]$13773 1'0 - assign $4\core_ea_ok$next[0:0]$13770 1'0 - assign $4\core_core_reg1_ok$next[0:0]$13765 1'0 - assign $4\core_core_reg2_ok$next[0:0]$13766 1'0 - assign $4\core_core_reg3_ok$next[0:0]$13767 1'0 - assign $4\core_spro_ok$next[0:0]$13774 1'0 - assign $4\core_core_spr1_ok$next[0:0]$13768 1'0 - assign $4\core_core_fast1_ok$next[0:0]$13763 1'0 - assign $4\core_core_fast2_ok$next[0:0]$13764 1'0 - assign $4\core_fasto1_ok$next[0:0]$13771 1'0 - assign $4\core_fasto2_ok$next[0:0]$13772 1'0 - assign $4\core_core_cr_in1_ok$next[0:0]$13759 1'0 - assign $4\core_core_cr_in2_ok$next[0:0]$13761 1'0 - assign $4\core_core_cr_in2_ok$2$next[0:0]$13760 1'0 - assign $4\core_cr_out_ok$next[0:0]$13769 1'0 - assign $4\core_core_core_rc_ok$next[0:0]$13758 1'0 - assign $4\core_core_core_oe_ok$next[0:0]$13757 1'0 - assign $4\core_core_core_exc_$signal$next[0:0]$13756 1'0 - assign $4\core_core_core_exc_$signal$3$next[0:0]$13749 1'0 - assign $4\core_core_core_exc_$signal$4$next[0:0]$13750 1'0 - assign $4\core_core_core_exc_$signal$5$next[0:0]$13751 1'0 - assign $4\core_core_core_exc_$signal$6$next[0:0]$13752 1'0 - assign $4\core_core_core_exc_$signal$7$next[0:0]$13753 1'0 - assign $4\core_core_core_exc_$signal$8$next[0:0]$13754 1'0 - assign $4\core_core_core_exc_$signal$9$next[0:0]$13755 1'0 - assign $4\core_core_core_cr_rd_ok$next[0:0]$13748 1'0 - assign $4\core_core_cr_wr_ok$next[0:0]$13762 1'0 - case - assign $4\core_core_core_cr_rd_ok$next[0:0]$13748 $1\core_core_core_cr_rd_ok$next[0:0]$13574 - assign $4\core_core_core_exc_$signal$3$next[0:0]$13749 $1\core_core_core_exc_$signal$3$next[0:0]$13576 - assign $4\core_core_core_exc_$signal$4$next[0:0]$13750 $1\core_core_core_exc_$signal$4$next[0:0]$13577 - assign $4\core_core_core_exc_$signal$5$next[0:0]$13751 $1\core_core_core_exc_$signal$5$next[0:0]$13578 - assign $4\core_core_core_exc_$signal$6$next[0:0]$13752 $1\core_core_core_exc_$signal$6$next[0:0]$13579 - assign $4\core_core_core_exc_$signal$7$next[0:0]$13753 $1\core_core_core_exc_$signal$7$next[0:0]$13580 - assign $4\core_core_core_exc_$signal$8$next[0:0]$13754 $1\core_core_core_exc_$signal$8$next[0:0]$13581 - assign $4\core_core_core_exc_$signal$9$next[0:0]$13755 $1\core_core_core_exc_$signal$9$next[0:0]$13582 - assign $4\core_core_core_exc_$signal$next[0:0]$13756 $1\core_core_core_exc_$signal$next[0:0]$13583 - assign $4\core_core_core_oe_ok$next[0:0]$13757 $1\core_core_core_oe_ok$next[0:0]$13591 - assign $4\core_core_core_rc_ok$next[0:0]$13758 $1\core_core_core_rc_ok$next[0:0]$13593 - assign $4\core_core_cr_in1_ok$next[0:0]$13759 $1\core_core_cr_in1_ok$next[0:0]$13597 - assign $4\core_core_cr_in2_ok$2$next[0:0]$13760 $1\core_core_cr_in2_ok$2$next[0:0]$13600 - assign $4\core_core_cr_in2_ok$next[0:0]$13761 $1\core_core_cr_in2_ok$next[0:0]$13601 - assign $4\core_core_cr_wr_ok$next[0:0]$13762 $1\core_core_cr_wr_ok$next[0:0]$13603 - assign $4\core_core_fast1_ok$next[0:0]$13763 $1\core_core_fast1_ok$next[0:0]$13606 - assign $4\core_core_fast2_ok$next[0:0]$13764 $1\core_core_fast2_ok$next[0:0]$13608 - assign $4\core_core_reg1_ok$next[0:0]$13765 $1\core_core_reg1_ok$next[0:0]$13613 - assign $4\core_core_reg2_ok$next[0:0]$13766 $1\core_core_reg2_ok$next[0:0]$13615 - assign $4\core_core_reg3_ok$next[0:0]$13767 $1\core_core_reg3_ok$next[0:0]$13617 - assign $4\core_core_spr1_ok$next[0:0]$13768 $1\core_core_spr1_ok$next[0:0]$13620 - assign $4\core_cr_out_ok$next[0:0]$13769 $1\core_cr_out_ok$next[0:0]$13623 - assign $4\core_ea_ok$next[0:0]$13770 $1\core_ea_ok$next[0:0]$13624 - assign $4\core_fasto1_ok$next[0:0]$13771 $1\core_fasto1_ok$next[0:0]$13625 - assign $4\core_fasto2_ok$next[0:0]$13772 $1\core_fasto2_ok$next[0:0]$13626 - assign $4\core_rego_ok$next[0:0]$13773 $1\core_rego_ok$next[0:0]$13627 - assign $4\core_spro_ok$next[0:0]$13774 $1\core_spro_ok$next[0:0]$13628 - end - sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13512 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13513 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13514 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13515 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13516 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13517 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13518 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13519 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13520 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13521 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13522 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13523 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13524 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$13525 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13526 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13527 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13528 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13529 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13530 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13531 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13532 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13533 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13534 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13535 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13536 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$13537 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13538 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$13539 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$13540 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13541 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$13542 - update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$13543 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$13544 - update \core_core_ea$next $0\core_core_ea$next[4:0]$13545 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$13546 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$13547 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$13548 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$13549 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$13550 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$13551 - update \core_core_lk$next $0\core_core_lk$next[0:0]$13552 - update \core_core_reg1$next $0\core_core_reg1$next[4:0]$13553 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$13554 - update \core_core_reg2$next $0\core_core_reg2$next[4:0]$13555 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$13556 - update \core_core_reg3$next $0\core_core_reg3$next[4:0]$13557 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$13558 - update \core_core_rego$next $0\core_core_rego$next[4:0]$13559 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$13560 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$13561 - update \core_core_spro$next $0\core_core_spro$next[9:0]$13562 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$13563 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$13564 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$13565 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$13566 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$13567 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$13568 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$13569 - update \core_xer_out$next $0\core_xer_out$next[0:0]$13570 - end - attribute \src "libresoc.v:186564.3-186572.6" - process $proc$libresoc.v:186564$13775 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13776 $1\jtag_dmi0__ack_o$next[0:0]$13777 - attribute \src "libresoc.v:186565.5-186565.29" - switch \initial - attribute \src "libresoc.v:186565.9-186565.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100010010 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13777 1'0 - case - assign $1\jtag_dmi0__ack_o$next[0:0]$13777 \dbg_dmi_ack_o - end - sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13776 - end - attribute \src "libresoc.v:186573.3-186581.6" - process $proc$libresoc.v:186573$13778 - assign { } { } - assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13779 $1\jtag_dmi0__dout$next[63:0]$13780 - attribute \src "libresoc.v:186574.5-186574.29" - switch \initial - attribute \src "libresoc.v:186574.9-186574.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100010011 assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13780 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $1\jtag_dmi0__dout$next[63:0]$13780 \dbg_dmi_dout - end - sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13779 - end - attribute \src "libresoc.v:186582.3-186590.6" - process $proc$libresoc.v:186582$13781 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$13782 $1\dec2_cur_eint$next[0:0]$13783 - attribute \src "libresoc.v:186583.5-186583.29" - switch \initial - attribute \src "libresoc.v:186583.9-186583.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100010100 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$13783 1'0 - case - assign $1\dec2_cur_eint$next[0:0]$13783 \xics_icp_core_irq_o - end - sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$13782 - end - attribute \src "libresoc.v:186591.3-186600.6" - process $proc$libresoc.v:186591$13784 - assign { } { } - assign { } { } - assign $0\delay$next[1:0]$13785 $1\delay$next[1:0]$13786 - attribute \src "libresoc.v:186592.5-186592.29" - switch \initial - attribute \src "libresoc.v:186592.9-186592.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" - switch \$21 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100010101 assign { } { } - assign $1\delay$next[1:0]$13786 \$23 [1:0] - case - assign $1\delay$next[1:0]$13786 \delay - end - sync always - update \delay$next $0\delay$next[1:0]$13785 - end - attribute \src "libresoc.v:186601.3-186637.6" - process $proc$libresoc.v:186601$13787 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13788 $4\core_raw_insn_i$next[31:0]$13792 - attribute \src "libresoc.v:186602.5-186602.29" - switch \initial - attribute \src "libresoc.v:186602.9-186602.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100010110 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13789 0 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100010111 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13789 $2\core_raw_insn_i$next[31:0]$13790 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_raw_insn_i$next[31:0]$13790 \core_raw_insn_i - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13790 \dec2_raw_opcode_in - end + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1100011000 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13789 $3\core_raw_insn_i$next[31:0]$13791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - switch \$61 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13791 0 - case - assign $3\core_raw_insn_i$next[31:0]$13791 \core_raw_insn_i - end - case - assign $1\core_raw_insn_i$next[31:0]$13789 \core_raw_insn_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100011011 assign { } { } - assign $4\core_raw_insn_i$next[31:0]$13792 0 - case - assign $4\core_raw_insn_i$next[31:0]$13792 $1\core_raw_insn_i$next[31:0]$13789 - end - sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13788 - end - attribute \src "libresoc.v:186638.3-186674.6" - process $proc$libresoc.v:186638$13793 - assign { } { } - assign { } { } - assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13794 $4\core_bigendian_i$10$next[0:0]$13798 - attribute \src "libresoc.v:186639.5-186639.29" - switch \initial - attribute \src "libresoc.v:186639.9-186639.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100011100 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13795 1'0 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100011101 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13795 $2\core_bigendian_i$10$next[0:0]$13796 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_bigendian_i$10$next[0:0]$13796 \core_bigendian_i$10 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13796 \core_bigendian_i - end + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1100011110 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13795 $3\core_bigendian_i$10$next[0:0]$13797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - switch \$63 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13797 1'0 - case - assign $3\core_bigendian_i$10$next[0:0]$13797 \core_bigendian_i$10 - end - case - assign $1\core_bigendian_i$10$next[0:0]$13795 \core_bigendian_i$10 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100100000 assign { } { } - assign $4\core_bigendian_i$10$next[0:0]$13798 1'0 - case - assign $4\core_bigendian_i$10$next[0:0]$13798 $1\core_bigendian_i$10$next[0:0]$13795 - end - sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13794 - end - attribute \src "libresoc.v:186675.3-186690.6" - process $proc$libresoc.v:186675$13799 - assign { } { } - assign { } { } - assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:186676.5-186676.29" - switch \initial - attribute \src "libresoc.v:186676.9-186676.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100100001 assign { } { } - assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$69 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_pc_i[47:0] \pc [47:0] - case - assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - case - assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 - end - sync always - update \imem_a_pc_i $0\imem_a_pc_i[47:0] - end - attribute \src "libresoc.v:186691.3-186715.6" - process $proc$libresoc.v:186691$13800 - assign { } { } - assign { } { } - assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:186692.5-186692.29" - switch \initial - attribute \src "libresoc.v:186692.9-186692.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100100010 assign { } { } - assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$75 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_a_valid_i[0:0] 1'1 - case - assign $2\imem_a_valid_i[0:0] 1'0 - end + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100100011 assign { } { } - assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_a_valid_i[0:0] 1'1 - case - assign $3\imem_a_valid_i[0:0] 1'0 - end - case - assign $1\imem_a_valid_i[0:0] 1'0 - end - sync always - update \imem_a_valid_i $0\imem_a_valid_i[0:0] - end - attribute \src "libresoc.v:186716.3-186740.6" - process $proc$libresoc.v:186716$13801 - assign { } { } - assign { } { } - assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:186717.5-186717.29" - switch \initial - attribute \src "libresoc.v:186717.9-186717.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100100100 assign { } { } - assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$81 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\imem_f_valid_i[0:0] 1'1 - case - assign $2\imem_f_valid_i[0:0] 1'0 - end + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100100101 assign { } { } - assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\imem_f_valid_i[0:0] 1'1 - case - assign $3\imem_f_valid_i[0:0] 1'0 - end - case - assign $1\imem_f_valid_i[0:0] 1'0 - end - sync always - update \imem_f_valid_i $0\imem_f_valid_i[0:0] - end - attribute \src "libresoc.v:186741.3-186761.6" - process $proc$libresoc.v:186741$13802 - assign { } { } - assign { } { } - assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13803 $3\dec2_cur_pc$next[63:0]$13806 - attribute \src "libresoc.v:186742.5-186742.29" - switch \initial - attribute \src "libresoc.v:186742.9-186742.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100100110 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13804 $2\dec2_cur_pc$next[63:0]$13805 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$87 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13805 \pc - case - assign $2\dec2_cur_pc$next[63:0]$13805 \dec2_cur_pc - end - case - assign $1\dec2_cur_pc$next[63:0]$13804 \dec2_cur_pc - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100101000 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13806 64'0000000000000000000000000000000000000000000000000000000000000000 - case - assign $3\dec2_cur_pc$next[63:0]$13806 $1\dec2_cur_pc$next[63:0]$13804 - end - sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13803 - end - attribute \src "libresoc.v:186762.3-186791.6" - process $proc$libresoc.v:186762$13807 - assign { } { } - assign { } { } - assign { } { } - assign $0\msr_read$next[0:0]$13808 $4\msr_read$next[0:0]$13812 - attribute \src "libresoc.v:186763.5-186763.29" - switch \initial - attribute \src "libresoc.v:186763.9-186763.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100101001 assign { } { } - assign $1\msr_read$next[0:0]$13809 $2\msr_read$next[0:0]$13810 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$93 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\msr_read$next[0:0]$13810 1'0 - case - assign $2\msr_read$next[0:0]$13810 \msr_read - end + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100101010 assign { } { } - assign $1\msr_read$next[0:0]$13809 $3\msr_read$next[0:0]$13811 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" - switch \$95 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $3\msr_read$next[0:0]$13811 1'1 - case - assign $3\msr_read$next[0:0]$13811 \msr_read - end - case - assign $1\msr_read$next[0:0]$13809 \msr_read - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1100101011 assign { } { } - assign $4\msr_read$next[0:0]$13812 1'1 - case - assign $4\msr_read$next[0:0]$13812 $1\msr_read$next[0:0]$13809 - end - sync always - update \msr_read$next $0\msr_read$next[0:0]$13808 - end - attribute \src "libresoc.v:186792.3-186837.6" - process $proc$libresoc.v:186792$13813 - assign { } { } - assign { } { } - assign { } { } - assign $0\fsm_state$next[1:0]$13814 $5\fsm_state$next[1:0]$13819 - attribute \src "libresoc.v:186793.5-186793.29" - switch \initial - attribute \src "libresoc.v:186793.9-186793.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1100110000 assign { } { } - assign $1\fsm_state$next[1:0]$13815 $2\fsm_state$next[1:0]$13816 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$101 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $2\fsm_state$next[1:0]$13816 2'01 - case - assign $2\fsm_state$next[1:0]$13816 \fsm_state - end + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'01 + case 10'1100110111 assign { } { } - assign $1\fsm_state$next[1:0]$13815 $3\fsm_state$next[1:0]$13817 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" - switch \imem_f_busy_o - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $3\fsm_state$next[1:0]$13817 \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $3\fsm_state$next[1:0]$13817 2'10 - end + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'10 + case 10'1101010000 assign { } { } - assign $1\fsm_state$next[1:0]$13815 2'11 + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'11 + case 10'1101010001 assign { } { } - assign $1\fsm_state$next[1:0]$13815 $4\fsm_state$next[1:0]$13818 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" - switch \$103 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $4\fsm_state$next[1:0]$13818 2'00 - case - assign $4\fsm_state$next[1:0]$13818 \fsm_state - end - case - assign $1\fsm_state$next[1:0]$13815 \fsm_state - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \rst + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 10'1101010111 assign { } { } - assign $5\fsm_state$next[1:0]$13819 2'00 - case - assign $5\fsm_state$next[1:0]$13819 $1\fsm_state$next[1:0]$13815 - end - sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13814 - end - attribute \src "libresoc.v:186838.3-186856.6" - process $proc$libresoc.v:186838$13820 - assign { } { } - assign { } { } - assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:186839.5-186839.29" - switch \initial - attribute \src "libresoc.v:186839.9-186839.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state + assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" - case 2'00 + case 10'1110000000 assign { } { } - assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$109 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\core_stopped_i[0:0] 1'1 - end + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 case - assign $1\core_stopped_i[0:0] 1'0 + assign $1\spr_o_ok[0:0] 1'0 end sync always - update \core_stopped_i $0\core_stopped_i[0:0] + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:47588.1-48717.10" +attribute \cells_not_processed 1 +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 7 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 6 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 8 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 372 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 374 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 344 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 input 338 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 347 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 346 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 342 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 340 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 339 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 348 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 input 341 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 343 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 345 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 19 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 21 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 23 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 37 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 41 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 42 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 43 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 47 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 48 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 49 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 53 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 54 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 55 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 59 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 60 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 61 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 65 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 66 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 67 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 71 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 72 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 25 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 29 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 30 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 31 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 35 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 36 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 73 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 77 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 78 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 79 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 83 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 84 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 85 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 89 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 90 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 91 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 95 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 96 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 97 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 101 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 102 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 103 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 107 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 108 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 109 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 113 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 114 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 115 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 119 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 120 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 333 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 327 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 336 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 335 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 331 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 329 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 328 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 337 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 330 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 332 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 334 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 355 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 349 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 2 input 358 \icp_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 3 input 357 \icp_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 353 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 351 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 350 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 359 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 352 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 354 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 356 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 366 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 360 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 2 input 369 \ics_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 3 input 368 \ics_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 364 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 362 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 361 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 370 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 363 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 365 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 367 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 371 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 17 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 10 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 14 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 12 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 11 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 18 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 13 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 15 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 16 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:106" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 122 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 124 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 127 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 126 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 130 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 132 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 135 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 134 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 144 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 137 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 141 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 142 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 377 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 375 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 376 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" + wire \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:480" + wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 146 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 148 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 373 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 156 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 149 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 153 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 154 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 157 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 161 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 162 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 163 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 178 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 231 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 267 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 269 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 271 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 233 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 235 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 237 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 239 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 241 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 243 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 245 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 247 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 249 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 251 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 253 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 261 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 257 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 255 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 265 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 181 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 274 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 275 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 276 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 184 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 185 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 186 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 292 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 293 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 294 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 298 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 299 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 300 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 304 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 305 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 306 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 310 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 311 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 312 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 316 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 317 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 318 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 322 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 323 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 324 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 190 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 191 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 192 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 196 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 197 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 198 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 202 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 203 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 204 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 208 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 209 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 210 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 214 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 215 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 216 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 220 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 221 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 222 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 226 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 227 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 228 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 280 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 281 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 282 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 286 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 287 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 288 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 259 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 263 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire \ti_coresync_clk + attribute \module_not_derived 1 + attribute \src "libresoc.v:48353.7-48359.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + connect \clk_sel_i \clk_sel_i + connect \pll_18_o \pll_18_o + connect \pll_lck_o \pll_lck_o end - attribute \src "libresoc.v:186857.3-186875.6" - process $proc$libresoc.v:186857$13821 - assign { } { } - assign { } { } - assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:186858.5-186858.29" - switch \initial - attribute \src "libresoc.v:186858.9-186858.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" - switch \fsm_state - attribute \src "libresoc.v:0.0-0.0" - case 2'00 - assign { } { } - assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:252" - switch \$115 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign $2\dbg_core_stopped_i[0:0] 1'0 - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $2\dbg_core_stopped_i[0:0] 1'1 - end - case - assign $1\dbg_core_stopped_i[0:0] 1'0 - end - sync always - update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + attribute \module_not_derived 1 + attribute \src "libresoc.v:48360.6-48712.4" + cell \ti \ti + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \busy_o \busy_o + connect \clk \clk + connect \core_bigendian_i \core_bigendian_i + connect \coresync_clk \ti_coresync_clk + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pc_i \pc_i + connect \pc_i_ok \pc_i_ok + connect \pc_o \pc_o + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o end - connect \$99 $not$libresoc.v:185095$13263_Y - connect \$101 $and$libresoc.v:185096$13264_Y - connect \$103 $not$libresoc.v:185097$13265_Y - connect \$105 $not$libresoc.v:185098$13266_Y - connect \$107 $not$libresoc.v:185099$13267_Y - connect \$109 $and$libresoc.v:185100$13268_Y - connect \$111 $not$libresoc.v:185101$13269_Y - connect \$113 $not$libresoc.v:185102$13270_Y - connect \$115 $and$libresoc.v:185103$13271_Y - connect \$117 $not$libresoc.v:185104$13272_Y - connect \$120 $mul$libresoc.v:185105$13273_Y - connect \$119 $shr$libresoc.v:185106$13274_Y [31:0] - connect \$124 $mul$libresoc.v:185107$13275_Y - connect \$123 $shr$libresoc.v:185108$13276_Y [31:0] - connect \$127 $ne$libresoc.v:185109$13277_Y - connect \$129 $pos$libresoc.v:185110$13279_Y - connect \$131 $pos$libresoc.v:185111$13281_Y - connect \$135 $sub$libresoc.v:185112$13282_Y - connect \$138 $add$libresoc.v:185113$13283_Y - connect \$21 $ne$libresoc.v:185114$13284_Y - connect \$24 $sub$libresoc.v:185115$13285_Y - connect \$26 $or$libresoc.v:185116$13286_Y - connect \$28 $or$libresoc.v:185117$13287_Y - connect \$30 $ne$libresoc.v:185118$13288_Y - connect \$32 $not$libresoc.v:185119$13289_Y - connect \$34 $and$libresoc.v:185120$13290_Y - connect \$37 $add$libresoc.v:185121$13291_Y - connect \$39 $not$libresoc.v:185122$13292_Y - connect \$41 $not$libresoc.v:185123$13293_Y - connect \$43 $not$libresoc.v:185124$13294_Y - connect \$45 $not$libresoc.v:185125$13295_Y - connect \$47 $not$libresoc.v:185126$13296_Y - connect \$49 $not$libresoc.v:185127$13297_Y - connect \$51 $not$libresoc.v:185128$13298_Y - connect \$53 $and$libresoc.v:185129$13299_Y - connect \$56 $and$libresoc.v:185130$13300_Y - connect \$55 $reduce_or$libresoc.v:185131$13301_Y - connect \$59 $not$libresoc.v:185132$13302_Y - connect \$61 $not$libresoc.v:185133$13303_Y - connect \$63 $not$libresoc.v:185134$13304_Y - connect \$65 $not$libresoc.v:185135$13305_Y - connect \$67 $not$libresoc.v:185136$13306_Y - connect \$69 $and$libresoc.v:185137$13307_Y - connect \$71 $not$libresoc.v:185138$13308_Y - connect \$73 $not$libresoc.v:185139$13309_Y - connect \$75 $and$libresoc.v:185140$13310_Y - connect \$77 $not$libresoc.v:185141$13311_Y - connect \$79 $not$libresoc.v:185142$13312_Y - connect \$81 $and$libresoc.v:185143$13313_Y - connect \$83 $not$libresoc.v:185144$13314_Y - connect \$85 $not$libresoc.v:185145$13315_Y - connect \$87 $and$libresoc.v:185146$13316_Y - connect \$89 $not$libresoc.v:185147$13317_Y - connect \$91 $not$libresoc.v:185148$13318_Y - connect \$93 $and$libresoc.v:185149$13319_Y - connect \$95 $not$libresoc.v:185150$13320_Y - connect \$97 $not$libresoc.v:185151$13321_Y - connect \$23 \$24 - connect \$36 \$37 - connect \$134 \$135 - connect \$137 \$138 - connect \dbg_core_dbg_msr \dec2_cur_msr - connect \dbg_core_dbg_pc \pc - connect \dbg_terminate_i \core_core_terminate_o - connect \nia \$37 [63:0] - connect \pc_o \dec2_cur_pc - connect \core_cu_st__go_i \cu_st__rel_o_rise - connect \core_cu_ad__go_i \core_cu_ad__rel_o - connect \cu_st__rel_o_rise \$34 - connect \cu_st__rel_o_dly$next \core_cu_st__rel_o - connect \dec2_bigendian \core_bigendian_i - connect \busy_o \core_corebusy_o - connect \core_coresync_rst \ti_rst - connect \ti_rst \$30 - connect \por_clk \clk - connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } + connect \ti_coresync_clk \pll_clk_pll_o + connect \pllclk_rst \rst + connect \pll_clk_24_i \clk + connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:186899.1-188084.10" +attribute \src "libresoc.v:48721.1-52499.10" attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" +attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" -module \trap0 - attribute \src "libresoc.v:187629.3-187630.25" - wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:187627.3-187628.41" - wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:187987.3-187995.6" - wire $0\alu_l_r_alu$next[0:0]$14126 - attribute \src "libresoc.v:187555.3-187556.39" - wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14052 - attribute \src "libresoc.v:187595.3-187596.61" - wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$14053 - attribute \src "libresoc.v:187589.3-187590.69" - wire width 12 $0\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14054 - attribute \src "libresoc.v:187591.3-187592.63" - wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14055 - attribute \src "libresoc.v:187587.3-187588.73" - wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14056 - attribute \src "libresoc.v:187597.3-187598.71" - wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14057 - attribute \src "libresoc.v:187603.3-187604.71" - wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14058 - attribute \src "libresoc.v:187593.3-187594.61" - wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14059 - attribute \src "libresoc.v:187601.3-187602.71" - wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14060 - attribute \src "libresoc.v:187599.3-187600.71" - wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:187978.3-187986.6" - wire $0\alui_l_r_alui$next[0:0]$14123 - attribute \src "libresoc.v:187557.3-187558.43" - wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187828.3-187849.6" - wire width 64 $0\data_r0__o$next[63:0]$14071 - attribute \src "libresoc.v:187583.3-187584.37" - wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:187828.3-187849.6" - wire $0\data_r0__o_ok$next[0:0]$14072 - attribute \src "libresoc.v:187585.3-187586.43" - wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187850.3-187871.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14079 - attribute \src "libresoc.v:187579.3-187580.45" - wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:187850.3-187871.6" - wire $0\data_r1__fast1_ok$next[0:0]$14080 - attribute \src "libresoc.v:187581.3-187582.51" - wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:187872.3-187893.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14087 - attribute \src "libresoc.v:187575.3-187576.45" - wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:187872.3-187893.6" - wire $0\data_r2__fast2_ok$next[0:0]$14088 - attribute \src "libresoc.v:187577.3-187578.51" - wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:187894.3-187915.6" - wire width 64 $0\data_r3__nia$next[63:0]$14095 - attribute \src "libresoc.v:187571.3-187572.41" - wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:187894.3-187915.6" - wire $0\data_r3__nia_ok$next[0:0]$14096 - attribute \src "libresoc.v:187573.3-187574.47" - wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:187916.3-187937.6" - wire width 64 $0\data_r4__msr$next[63:0]$14103 - attribute \src "libresoc.v:187567.3-187568.41" - wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:187916.3-187937.6" - wire $0\data_r4__msr_ok$next[0:0]$14104 - attribute \src "libresoc.v:187569.3-187570.47" - wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:187996.3-188005.6" - wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:188006.3-188015.6" - wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:188016.3-188025.6" - wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:188026.3-188035.6" - wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:188036.3-188045.6" - wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:186900.7-186900.20" +module \ti + attribute \src "libresoc.v:52231.3-52267.6" + wire $0\bigendian_i$next[0:0]$2133 + attribute \src "libresoc.v:50848.3-50849.39" + wire $0\bigendian_i[0:0] + attribute \src "libresoc.v:51929.3-51941.6" + wire width 4 $0\cia__ren[3:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $0\core_asmcode$next[7:0]$1851 + attribute \src "libresoc.v:50852.3-50853.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $0\core_core_cia$next[63:0]$1852 + attribute \src "libresoc.v:50928.3-50929.43" + wire width 64 $0\core_core_cia[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $0\core_core_cr_rd$next[7:0]$1853 + attribute \src "libresoc.v:50972.3-50973.47" + wire width 8 $0\core_core_cr_rd[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_cr_rd_ok$next[0:0]$1854 + attribute \src "libresoc.v:50974.3-50975.53" + wire $0\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $0\core_core_cr_wr$next[7:0]$1855 + attribute \src "libresoc.v:50976.3-50977.47" + wire width 8 $0\core_core_cr_wr[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_cr_wr_ok$next[0:0]$1856 + attribute \src "libresoc.v:50978.3-50979.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$50$next[0:0]$1857 + attribute \src "libresoc.v:50954.3-50955.67" + wire $0\core_core_exc_$signal$50[0:0]$1726 + attribute \src "libresoc.v:48894.7-48894.40" + wire $0\core_core_exc_$signal$50[0:0]$2172 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$51$next[0:0]$1858 + attribute \src "libresoc.v:50956.3-50957.67" + wire $0\core_core_exc_$signal$51[0:0]$1728 + attribute \src "libresoc.v:48898.7-48898.40" + wire $0\core_core_exc_$signal$51[0:0]$2174 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$52$next[0:0]$1859 + attribute \src "libresoc.v:50958.3-50959.67" + wire $0\core_core_exc_$signal$52[0:0]$1730 + attribute \src "libresoc.v:48902.7-48902.40" + wire $0\core_core_exc_$signal$52[0:0]$2176 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$53$next[0:0]$1860 + attribute \src "libresoc.v:50960.3-50961.67" + wire $0\core_core_exc_$signal$53[0:0]$1732 + attribute \src "libresoc.v:48906.7-48906.40" + wire $0\core_core_exc_$signal$53[0:0]$2178 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$54$next[0:0]$1861 + attribute \src "libresoc.v:50962.3-50963.67" + wire $0\core_core_exc_$signal$54[0:0]$1734 + attribute \src "libresoc.v:48910.7-48910.40" + wire $0\core_core_exc_$signal$54[0:0]$2180 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$55$next[0:0]$1862 + attribute \src "libresoc.v:50964.3-50965.67" + wire $0\core_core_exc_$signal$55[0:0]$1736 + attribute \src "libresoc.v:48914.7-48914.40" + wire $0\core_core_exc_$signal$55[0:0]$2182 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$56$next[0:0]$1863 + attribute \src "libresoc.v:50966.3-50967.67" + wire $0\core_core_exc_$signal$56[0:0]$1738 + attribute \src "libresoc.v:48918.7-48918.40" + wire $0\core_core_exc_$signal$56[0:0]$2184 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_exc_$signal$next[0:0]$1864 + attribute \src "libresoc.v:50952.3-50953.61" + wire $0\core_core_exc_$signal[0:0]$1724 + attribute \src "libresoc.v:48892.7-48892.37" + wire $0\core_core_exc_$signal[0:0]$2170 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 12 $0\core_core_fn_unit$next[11:0]$1865 + attribute \src "libresoc.v:50934.3-50935.51" + wire width 12 $0\core_core_fn_unit[11:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 2 $0\core_core_input_carry$next[1:0]$1866 + attribute \src "libresoc.v:50948.3-50949.59" + wire width 2 $0\core_core_input_carry[1:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 32 $0\core_core_insn$next[31:0]$1867 + attribute \src "libresoc.v:50930.3-50931.45" + wire width 32 $0\core_core_insn[31:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 7 $0\core_core_insn_type$next[6:0]$1868 + attribute \src "libresoc.v:50932.3-50933.55" + wire width 7 $0\core_core_insn_type[6:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_is_32bit$next[0:0]$1869 + attribute \src "libresoc.v:50980.3-50981.53" + wire $0\core_core_is_32bit[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_lk$next[0:0]$1870 + attribute \src "libresoc.v:50936.3-50937.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $0\core_core_msr$next[63:0]$1871 + attribute \src "libresoc.v:50926.3-50927.43" + wire width 64 $0\core_core_msr[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_oe$next[0:0]$1872 + attribute \src "libresoc.v:50942.3-50943.41" + wire $0\core_core_oe[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_oe_ok$next[0:0]$1873 + attribute \src "libresoc.v:50944.3-50945.47" + wire $0\core_core_oe_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_rc$next[0:0]$1874 + attribute \src "libresoc.v:50938.3-50939.41" + wire $0\core_core_rc[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_core_rc_ok$next[0:0]$1875 + attribute \src "libresoc.v:50940.3-50941.47" + wire $0\core_core_rc_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 13 $0\core_core_trapaddr$next[12:0]$1876 + attribute \src "libresoc.v:50970.3-50971.53" + wire width 13 $0\core_core_trapaddr[12:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $0\core_core_traptype$next[7:0]$1877 + attribute \src "libresoc.v:50950.3-50951.53" + wire width 8 $0\core_core_traptype[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_cr_in1$next[2:0]$1878 + attribute \src "libresoc.v:50908.3-50909.39" + wire width 3 $0\core_cr_in1[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_cr_in1_ok$next[0:0]$1879 + attribute \src "libresoc.v:50910.3-50911.45" + wire $0\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_cr_in2$48$next[2:0]$1880 + attribute \src "libresoc.v:50916.3-50917.47" + wire width 3 $0\core_cr_in2$48[2:0]$1704 + attribute \src "libresoc.v:49079.13-49079.36" + wire width 3 $0\core_cr_in2$48[2:0]$2202 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_cr_in2$next[2:0]$1881 + attribute \src "libresoc.v:50912.3-50913.39" + wire width 3 $0\core_cr_in2[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_cr_in2_ok$49$next[0:0]$1882 + attribute \src "libresoc.v:50918.3-50919.53" + wire $0\core_cr_in2_ok$49[0:0]$1706 + attribute \src "libresoc.v:49087.7-49087.33" + wire $0\core_cr_in2_ok$49[0:0]$2205 + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_cr_in2_ok$next[0:0]$1883 + attribute \src "libresoc.v:50914.3-50915.45" + wire $0\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_cr_out$next[2:0]$1884 + attribute \src "libresoc.v:50920.3-50921.39" + wire width 3 $0\core_cr_out[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_cr_out_ok$next[0:0]$1885 + attribute \src "libresoc.v:50922.3-50923.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $0\core_dec$next[63:0]$1772 + attribute \src "libresoc.v:50838.3-50839.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $0\core_ea$next[4:0]$1886 + attribute \src "libresoc.v:50860.3-50861.31" + wire width 5 $0\core_ea[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_ea_ok$next[0:0]$1887 + attribute \src "libresoc.v:50862.3-50863.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire $0\core_eint$next[0:0]$1773 + attribute \src "libresoc.v:51006.3-51007.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_fast1$next[2:0]$1888 + attribute \src "libresoc.v:50890.3-50891.37" + wire width 3 $0\core_fast1[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_fast1_ok$next[0:0]$1889 + attribute \src "libresoc.v:50892.3-50893.43" + wire $0\core_fast1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_fast2$next[2:0]$1890 + attribute \src "libresoc.v:50894.3-50895.37" + wire width 3 $0\core_fast2[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_fast2_ok$next[0:0]$1891 + attribute \src "libresoc.v:50896.3-50897.43" + wire $0\core_fast2_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_fasto1$next[2:0]$1892 + attribute \src "libresoc.v:50898.3-50899.39" + wire width 3 $0\core_fasto1[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_fasto1_ok$next[0:0]$1893 + attribute \src "libresoc.v:50900.3-50901.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_fasto2$next[2:0]$1894 + attribute \src "libresoc.v:50904.3-50905.39" + wire width 3 $0\core_fasto2[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_fasto2_ok$next[0:0]$1895 + attribute \src "libresoc.v:50906.3-50907.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $0\core_msr$next[63:0]$1774 + attribute \src "libresoc.v:50990.3-50991.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $0\core_pc$next[63:0]$1775 + attribute \src "libresoc.v:50968.3-50969.31" + wire width 64 $0\core_pc[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $0\core_reg1$next[4:0]$1896 + attribute \src "libresoc.v:50864.3-50865.35" + wire width 5 $0\core_reg1[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_reg1_ok$next[0:0]$1897 + attribute \src "libresoc.v:50866.3-50867.41" + wire $0\core_reg1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $0\core_reg2$next[4:0]$1898 + attribute \src "libresoc.v:50868.3-50869.35" + wire width 5 $0\core_reg2[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_reg2_ok$next[0:0]$1899 + attribute \src "libresoc.v:50870.3-50871.41" + wire $0\core_reg2_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $0\core_reg3$next[4:0]$1900 + attribute \src "libresoc.v:50872.3-50873.35" + wire width 5 $0\core_reg3[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_reg3_ok$next[0:0]$1901 + attribute \src "libresoc.v:50874.3-50875.41" + wire $0\core_reg3_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $0\core_rego$next[4:0]$1902 + attribute \src "libresoc.v:50854.3-50855.35" + wire width 5 $0\core_rego[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_rego_ok$next[0:0]$1903 + attribute \src "libresoc.v:50856.3-50857.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $0\core_spr1$next[9:0]$1904 + attribute \src "libresoc.v:50882.3-50883.35" + wire width 10 $0\core_spr1[9:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_spr1_ok$next[0:0]$1905 + attribute \src "libresoc.v:50884.3-50885.41" + wire $0\core_spr1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $0\core_spro$next[9:0]$1906 + attribute \src "libresoc.v:50876.3-50877.35" + wire width 10 $0\core_spro[9:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_spro_ok$next[0:0]$1907 + attribute \src "libresoc.v:50878.3-50879.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:52431.3-52449.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $0\core_xer_in$next[2:0]$1908 + attribute \src "libresoc.v:50886.3-50887.39" + wire width 3 $0\core_xer_in[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $0\core_xer_out$next[0:0]$1909 + attribute \src "libresoc.v:50888.3-50889.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:50986.3-50987.30" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:51686.3-51694.6" + wire $0\d_cr_delay$next[0:0]$1804 + attribute \src "libresoc.v:50902.3-50903.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:51647.3-51655.6" + wire $0\d_reg_delay$next[0:0]$1798 + attribute \src "libresoc.v:50924.3-50925.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:51725.3-51733.6" + wire $0\d_xer_delay$next[0:0]$1810 + attribute \src "libresoc.v:50880.3-50881.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:51963.3-51983.6" + wire width 64 $0\data_i[63:0] + attribute \src "libresoc.v:52450.3-52468.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:51705.3-51714.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:51695.3-51704.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:51666.3-51675.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:51656.3-51665.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:51744.3-51753.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:51734.3-51743.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:51482.3-51490.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1760 + attribute \src "libresoc.v:51004.3-51005.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:52000.3-52008.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$1843 + attribute \src "libresoc.v:50998.3-50999.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:51491.3-51499.6" + wire $0\dbg_dmi_req_i$next[0:0]$1763 + attribute \src "libresoc.v:51002.3-51003.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:51895.3-51903.6" + wire $0\dbg_dmi_we_i$next[0:0]$1832 + attribute \src "libresoc.v:51000.3-51001.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:51868.3-51883.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$1827 + attribute \src "libresoc.v:50836.3-50837.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:52175.3-52183.6" + wire $0\dec2_cur_eint$next[0:0]$2121 + attribute \src "libresoc.v:50992.3-50993.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:51500.3-51520.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$1766 + attribute \src "libresoc.v:50840.3-50841.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:52334.3-52354.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$2142 + attribute \src "libresoc.v:50846.3-50847.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:51521.3-51539.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:52184.3-52193.6" + wire width 2 $0\delay$next[1:0]$2124 + attribute \src "libresoc.v:50988.3-50989.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:51627.3-51636.6" + wire width 5 $0\dmi__addr[4:0] + attribute \src "libresoc.v:51637.3-51646.6" + wire $0\dmi__ren[0:0] + attribute \src "libresoc.v:51784.3-51811.6" + wire width 2 $0\fsm_state$131$next[1:0]$1817 + attribute \src "libresoc.v:50858.3-50859.45" + wire width 2 $0\fsm_state$131[1:0]$1674 + attribute \src "libresoc.v:49998.13-49998.35" + wire width 2 $0\fsm_state$131[1:0]$2251 + attribute \src "libresoc.v:52385.3-52430.6" + wire width 2 $0\fsm_state$next[1:0]$2153 + attribute \src "libresoc.v:50842.3-50843.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:51676.3-51685.6" + wire width 8 $0\full_rd2__ren[7:0] + attribute \src "libresoc.v:51715.3-51724.6" + wire width 3 $0\full_rd__ren[2:0] + attribute \src "libresoc.v:51572.3-51595.6" + wire width 32 $0\ilatch$next[31:0]$1789 + attribute \src "libresoc.v:50946.3-50947.29" + wire width 32 $0\ilatch[31:0] + attribute \src "libresoc.v:52268.3-52283.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52284.3-52308.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52309.3-52333.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:48722.7-48722.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187765.3-187773.6" - wire $0\opc_l_r_opc$next[0:0]$14037 - attribute \src "libresoc.v:187613.3-187614.39" - wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187756.3-187764.6" - wire $0\opc_l_s_opc$next[0:0]$14034 - attribute \src "libresoc.v:187615.3-187616.39" - wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188046.3-188054.6" - wire width 5 $0\prev_wr_go$next[4:0]$14134 - attribute \src "libresoc.v:187625.3-187626.37" - wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:187710.3-187719.6" - wire $0\req_done[0:0] - attribute \src "libresoc.v:187801.3-187809.6" - wire width 5 $0\req_l_r_req$next[4:0]$14049 - attribute \src "libresoc.v:187605.3-187606.39" - wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:187792.3-187800.6" - wire width 5 $0\req_l_s_req$next[4:0]$14046 - attribute \src "libresoc.v:187607.3-187608.39" - wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:187729.3-187737.6" - wire $0\rok_l_r_rdok$next[0:0]$14025 - attribute \src "libresoc.v:187621.3-187622.41" - wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187720.3-187728.6" - wire $0\rok_l_s_rdok$next[0:0]$14022 - attribute \src "libresoc.v:187623.3-187624.41" - wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187747.3-187755.6" - wire $0\rst_l_r_rst$next[0:0]$14031 - attribute \src "libresoc.v:187617.3-187618.39" - wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187738.3-187746.6" - wire $0\rst_l_s_rst$next[0:0]$14028 - attribute \src "libresoc.v:187619.3-187620.39" - wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187783.3-187791.6" - wire width 4 $0\src_l_r_src$next[3:0]$14043 - attribute \src "libresoc.v:187609.3-187610.39" - wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:187774.3-187782.6" - wire width 4 $0\src_l_s_src$next[3:0]$14040 - attribute \src "libresoc.v:187611.3-187612.39" - wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:187938.3-187947.6" - wire width 64 $0\src_r0$next[63:0]$14111 - attribute \src "libresoc.v:187565.3-187566.29" - wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:187948.3-187957.6" - wire width 64 $0\src_r1$next[63:0]$14114 - attribute \src "libresoc.v:187563.3-187564.29" - wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:187958.3-187967.6" - wire width 64 $0\src_r2$next[63:0]$14117 - attribute \src "libresoc.v:187561.3-187562.29" - wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:187968.3-187977.6" - wire width 64 $0\src_r3$next[63:0]$14120 - attribute \src "libresoc.v:187559.3-187560.29" - wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:187026.7-187026.24" - wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:187036.7-187036.26" - wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:187987.3-187995.6" - wire $1\alu_l_r_alu$next[0:0]$14127 - attribute \src "libresoc.v:187044.7-187044.25" - wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14061 - attribute \src "libresoc.v:187080.14-187080.59" - wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 - attribute \src "libresoc.v:187097.14-187097.50" - wire width 12 $1\alu_trap0_trap_op__fn_unit[11:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14063 - attribute \src "libresoc.v:187101.14-187101.45" - wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 - attribute \src "libresoc.v:187179.13-187179.49" - wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 - attribute \src "libresoc.v:187183.7-187183.41" - wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:187810.3-187827.6" - wire width 8 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$0\wen[3:0] + attribute \src "libresoc.v:52231.3-52267.6" + wire $1\bigendian_i$next[0:0]$2134 + attribute \src "libresoc.v:48854.7-48854.25" + wire $1\bigendian_i[0:0] + attribute \src "libresoc.v:51929.3-51941.6" + wire width 4 $1\cia__ren[3:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $1\core_asmcode$next[7:0]$1910 + attribute \src "libresoc.v:48866.13-48866.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $1\core_core_cia$next[63:0]$1911 + attribute \src "libresoc.v:48872.14-48872.50" + wire width 64 $1\core_core_cia[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $1\core_core_cr_rd$next[7:0]$1912 + attribute \src "libresoc.v:48876.13-48876.36" + wire width 8 $1\core_core_cr_rd[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_cr_rd_ok$next[0:0]$1913 + attribute \src "libresoc.v:48880.7-48880.32" + wire $1\core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $1\core_core_cr_wr$next[7:0]$1914 + attribute \src "libresoc.v:48884.13-48884.36" + wire width 8 $1\core_core_cr_wr[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_cr_wr_ok$next[0:0]$1915 + attribute \src "libresoc.v:48888.7-48888.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$50$next[0:0]$1916 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$51$next[0:0]$1917 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$52$next[0:0]$1918 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$53$next[0:0]$1919 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$54$next[0:0]$1920 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$55$next[0:0]$1921 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$56$next[0:0]$1922 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_exc_$signal$next[0:0]$1923 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 12 $1\core_core_fn_unit$next[11:0]$1924 + attribute \src "libresoc.v:48937.14-48937.41" + wire width 12 $1\core_core_fn_unit[11:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 2 $1\core_core_input_carry$next[1:0]$1925 + attribute \src "libresoc.v:48945.13-48945.41" + wire width 2 $1\core_core_input_carry[1:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 32 $1\core_core_insn$next[31:0]$1926 + attribute \src "libresoc.v:48949.14-48949.36" + wire width 32 $1\core_core_insn[31:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 7 $1\core_core_insn_type$next[6:0]$1927 + attribute \src "libresoc.v:49027.13-49027.40" + wire width 7 $1\core_core_insn_type[6:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_is_32bit$next[0:0]$1928 + attribute \src "libresoc.v:49031.7-49031.32" + wire $1\core_core_is_32bit[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_lk$next[0:0]$1929 + attribute \src "libresoc.v:49035.7-49035.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $1\core_core_msr$next[63:0]$1930 + attribute \src "libresoc.v:49039.14-49039.50" + wire width 64 $1\core_core_msr[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_oe$next[0:0]$1931 + attribute \src "libresoc.v:49043.7-49043.26" + wire $1\core_core_oe[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_oe_ok$next[0:0]$1932 + attribute \src "libresoc.v:49047.7-49047.29" + wire $1\core_core_oe_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_rc$next[0:0]$1933 + attribute \src "libresoc.v:49051.7-49051.26" + wire $1\core_core_rc[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_core_rc_ok$next[0:0]$1934 + attribute \src "libresoc.v:49055.7-49055.29" + wire $1\core_core_rc_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 13 $1\core_core_trapaddr$next[12:0]$1935 + attribute \src "libresoc.v:49059.14-49059.43" + wire width 13 $1\core_core_trapaddr[12:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $1\core_core_traptype$next[7:0]$1936 + attribute \src "libresoc.v:49063.13-49063.39" + wire width 8 $1\core_core_traptype[7:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_cr_in1$next[2:0]$1937 + attribute \src "libresoc.v:49069.13-49069.31" + wire width 3 $1\core_cr_in1[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_cr_in1_ok$next[0:0]$1938 + attribute \src "libresoc.v:49073.7-49073.28" + wire $1\core_cr_in1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_cr_in2$48$next[2:0]$1939 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_cr_in2$next[2:0]$1940 + attribute \src "libresoc.v:49077.13-49077.31" + wire width 3 $1\core_cr_in2[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_cr_in2_ok$49$next[0:0]$1941 + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_cr_in2_ok$next[0:0]$1942 + attribute \src "libresoc.v:49085.7-49085.28" + wire $1\core_cr_in2_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_cr_out$next[2:0]$1943 + attribute \src "libresoc.v:49093.13-49093.31" + wire width 3 $1\core_cr_out[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_cr_out_ok$next[0:0]$1944 + attribute \src "libresoc.v:49097.7-49097.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $1\core_dec$next[63:0]$1776 + attribute \src "libresoc.v:49101.14-49101.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $1\core_ea$next[4:0]$1945 + attribute \src "libresoc.v:49105.13-49105.28" + wire width 5 $1\core_ea[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_ea_ok$next[0:0]$1946 + attribute \src "libresoc.v:49109.7-49109.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire $1\core_eint$next[0:0]$1777 + attribute \src "libresoc.v:49113.7-49113.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_fast1$next[2:0]$1947 + attribute \src "libresoc.v:49117.13-49117.30" + wire width 3 $1\core_fast1[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_fast1_ok$next[0:0]$1948 + attribute \src "libresoc.v:49121.7-49121.27" + wire $1\core_fast1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_fast2$next[2:0]$1949 + attribute \src "libresoc.v:49125.13-49125.30" + wire width 3 $1\core_fast2[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_fast2_ok$next[0:0]$1950 + attribute \src "libresoc.v:49129.7-49129.27" + wire $1\core_fast2_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_fasto1$next[2:0]$1951 + attribute \src "libresoc.v:49133.13-49133.31" + wire width 3 $1\core_fasto1[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_fasto1_ok$next[0:0]$1952 + attribute \src "libresoc.v:49137.7-49137.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_fasto2$next[2:0]$1953 + attribute \src "libresoc.v:49141.13-49141.31" + wire width 3 $1\core_fasto2[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_fasto2_ok$next[0:0]$1954 + attribute \src "libresoc.v:49145.7-49145.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $1\core_msr$next[63:0]$1778 + attribute \src "libresoc.v:49149.14-49149.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $1\core_pc$next[63:0]$1779 + attribute \src "libresoc.v:49153.14-49153.44" + wire width 64 $1\core_pc[63:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $1\core_reg1$next[4:0]$1955 + attribute \src "libresoc.v:49157.13-49157.30" + wire width 5 $1\core_reg1[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_reg1_ok$next[0:0]$1956 + attribute \src "libresoc.v:49161.7-49161.26" + wire $1\core_reg1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $1\core_reg2$next[4:0]$1957 + attribute \src "libresoc.v:49165.13-49165.30" + wire width 5 $1\core_reg2[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_reg2_ok$next[0:0]$1958 + attribute \src "libresoc.v:49169.7-49169.26" + wire $1\core_reg2_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $1\core_reg3$next[4:0]$1959 + attribute \src "libresoc.v:49173.13-49173.30" + wire width 5 $1\core_reg3[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_reg3_ok$next[0:0]$1960 + attribute \src "libresoc.v:49177.7-49177.26" + wire $1\core_reg3_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $1\core_rego$next[4:0]$1961 + attribute \src "libresoc.v:49181.13-49181.30" + wire width 5 $1\core_rego[4:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_rego_ok$next[0:0]$1962 + attribute \src "libresoc.v:49185.7-49185.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $1\core_spr1$next[9:0]$1963 + attribute \src "libresoc.v:49300.13-49300.32" + wire width 10 $1\core_spr1[9:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_spr1_ok$next[0:0]$1964 + attribute \src "libresoc.v:49304.7-49304.26" + wire $1\core_spr1_ok[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $1\core_spro$next[9:0]$1965 + attribute \src "libresoc.v:49419.13-49419.32" + wire width 10 $1\core_spro[9:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_spro_ok$next[0:0]$1966 + attribute \src "libresoc.v:49423.7-49423.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:52431.3-52449.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $1\core_xer_in$next[2:0]$1967 + attribute \src "libresoc.v:49431.13-49431.31" + wire width 3 $1\core_xer_in[2:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire $1\core_xer_out$next[0:0]$1968 + attribute \src "libresoc.v:49435.7-49435.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:49451.7-49451.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:51686.3-51694.6" + wire $1\d_cr_delay$next[0:0]$1805 + attribute \src "libresoc.v:49457.7-49457.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:51647.3-51655.6" + wire $1\d_reg_delay$next[0:0]$1799 + attribute \src "libresoc.v:49461.7-49461.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:51725.3-51733.6" + wire $1\d_xer_delay$next[0:0]$1811 + attribute \src "libresoc.v:49465.7-49465.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:51963.3-51983.6" + wire width 64 $1\data_i[63:0] + attribute \src "libresoc.v:52450.3-52468.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:51705.3-51714.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:51695.3-51704.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:51666.3-51675.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:51656.3-51665.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:51744.3-51753.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:51734.3-51743.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:51482.3-51490.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1761 + attribute \src "libresoc.v:49503.13-49503.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:52000.3-52008.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$1844 + attribute \src "libresoc.v:49507.14-49507.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:51491.3-51499.6" + wire $1\dbg_dmi_req_i$next[0:0]$1764 + attribute \src "libresoc.v:49513.7-49513.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:51895.3-51903.6" + wire $1\dbg_dmi_we_i$next[0:0]$1833 + attribute \src "libresoc.v:49517.7-49517.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:51868.3-51883.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$1828 + attribute \src "libresoc.v:49553.14-49553.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:52175.3-52183.6" + wire $1\dec2_cur_eint$next[0:0]$2122 + attribute \src "libresoc.v:49557.7-49557.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:51500.3-51520.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$1767 + attribute \src "libresoc.v:49561.14-49561.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:52334.3-52354.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$2143 + attribute \src "libresoc.v:49565.14-49565.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:51521.3-51539.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:52184.3-52193.6" + wire width 2 $1\delay$next[1:0]$2125 + attribute \src "libresoc.v:49974.13-49974.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:51627.3-51636.6" + wire width 5 $1\dmi__addr[4:0] + attribute \src "libresoc.v:51637.3-51646.6" + wire $1\dmi__ren[0:0] + attribute \src "libresoc.v:51784.3-51811.6" + wire width 2 $1\fsm_state$131$next[1:0]$1818 + attribute \src "libresoc.v:52385.3-52430.6" + wire width 2 $1\fsm_state$next[1:0]$2154 + attribute \src "libresoc.v:49996.13-49996.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:51676.3-51685.6" + wire width 8 $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:51715.3-51724.6" + wire width 3 $1\full_rd__ren[2:0] + attribute \src "libresoc.v:51572.3-51595.6" + wire width 32 $1\ilatch$next[31:0]$1790 + attribute \src "libresoc.v:50248.14-50248.28" + wire width 32 $1\ilatch[31:0] + attribute \src "libresoc.v:52268.3-52283.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52284.3-52308.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52309.3-52333.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:51823.3-51837.6" + wire width 3 $1\issue__addr$135[2:0]$1823 + attribute \src "libresoc.v:51754.3-51768.6" + wire width 3 $1\issue__addr[2:0] + attribute \src "libresoc.v:51853.3-51867.6" + wire width 64 $1\issue__data_i[63:0] + attribute \src "libresoc.v:51769.3-51783.6" + wire $1\issue__ren[0:0] + attribute \src "libresoc.v:51838.3-51852.6" + wire $1\issue__wen[0:0] + attribute \src "libresoc.v:51616.3-51626.6" + wire $1\issue_i[0:0] + attribute \src "libresoc.v:51596.3-51615.6" + wire $1\ivalid_i[0:0] + attribute \src "libresoc.v:52157.3-52165.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$2116 + attribute \src "libresoc.v:50282.7-50282.30" + wire $1\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:52166.3-52174.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$2119 + attribute \src "libresoc.v:50290.14-50290.52" + wire width 64 $1\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:51984.3-51999.6" + wire width 4 $1\msr__ren[3:0] + attribute \src "libresoc.v:52355.3-52384.6" + wire $1\msr_read$next[0:0]$2148 + attribute \src "libresoc.v:50350.7-50350.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:51812.3-51822.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:51884.3-51894.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:51913.3-51928.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:52009.3-52033.6" + wire $1\pc_changed$next[0:0]$1847 + attribute \src "libresoc.v:50378.7-50378.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:51904.3-51912.6" + wire $1\pc_ok_delay$next[0:0]$1836 + attribute \src "libresoc.v:50388.7-50388.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:52194.3-52230.6" + wire width 32 $1\raw_insn_i$next[31:0]$2128 + attribute \src "libresoc.v:50402.14-50402.32" + wire width 32 $1\raw_insn_i[31:0] + attribute \src "libresoc.v:51942.3-51962.6" + wire width 4 $1\wen[3:0] + attribute \src "libresoc.v:52231.3-52267.6" + wire $2\bigendian_i$next[0:0]$2135 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $2\core_asmcode$next[7:0]$1969 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $2\core_core_cia$next[63:0]$1970 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $2\core_core_cr_rd$next[7:0]$1971 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_cr_rd_ok$next[0:0]$1972 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $2\core_core_cr_wr$next[7:0]$1973 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_cr_wr_ok$next[0:0]$1974 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$50$next[0:0]$1975 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$51$next[0:0]$1976 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$52$next[0:0]$1977 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$53$next[0:0]$1978 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$54$next[0:0]$1979 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$55$next[0:0]$1980 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$56$next[0:0]$1981 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_exc_$signal$next[0:0]$1982 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 12 $2\core_core_fn_unit$next[11:0]$1983 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 2 $2\core_core_input_carry$next[1:0]$1984 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 32 $2\core_core_insn$next[31:0]$1985 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 7 $2\core_core_insn_type$next[6:0]$1986 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_is_32bit$next[0:0]$1987 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_lk$next[0:0]$1988 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $2\core_core_msr$next[63:0]$1989 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_oe$next[0:0]$1990 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_oe_ok$next[0:0]$1991 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_rc$next[0:0]$1992 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_core_rc_ok$next[0:0]$1993 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 13 $2\core_core_trapaddr$next[12:0]$1994 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $2\core_core_traptype$next[7:0]$1995 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_cr_in1$next[2:0]$1996 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_cr_in1_ok$next[0:0]$1997 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_cr_in2$48$next[2:0]$1998 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_cr_in2$next[2:0]$1999 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_cr_in2_ok$49$next[0:0]$2000 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_cr_in2_ok$next[0:0]$2001 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_cr_out$next[2:0]$2002 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_cr_out_ok$next[0:0]$2003 + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $2\core_dec$next[63:0]$1780 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $2\core_ea$next[4:0]$2004 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_ea_ok$next[0:0]$2005 + attribute \src "libresoc.v:51540.3-51571.6" + wire $2\core_eint$next[0:0]$1781 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_fast1$next[2:0]$2006 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_fast1_ok$next[0:0]$2007 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_fast2$next[2:0]$2008 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_fast2_ok$next[0:0]$2009 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_fasto1$next[2:0]$2010 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_fasto1_ok$next[0:0]$2011 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_fasto2$next[2:0]$2012 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_fasto2_ok$next[0:0]$2013 + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $2\core_msr$next[63:0]$1782 + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $2\core_pc$next[63:0]$1783 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $2\core_reg1$next[4:0]$2014 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_reg1_ok$next[0:0]$2015 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $2\core_reg2$next[4:0]$2016 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_reg2_ok$next[0:0]$2017 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $2\core_reg3$next[4:0]$2018 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_reg3_ok$next[0:0]$2019 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $2\core_rego$next[4:0]$2020 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_rego_ok$next[0:0]$2021 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $2\core_spr1$next[9:0]$2022 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_spr1_ok$next[0:0]$2023 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $2\core_spro$next[9:0]$2024 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_spro_ok$next[0:0]$2025 + attribute \src "libresoc.v:52431.3-52449.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $2\core_xer_in$next[2:0]$2026 + attribute \src "libresoc.v:52034.3-52156.6" + wire $2\core_xer_out$next[0:0]$2027 + attribute \src "libresoc.v:51963.3-51983.6" + wire width 64 $2\data_i[63:0] + attribute \src "libresoc.v:52450.3-52468.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:51868.3-51883.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$1829 + attribute \src "libresoc.v:51500.3-51520.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$1768 + attribute \src "libresoc.v:52334.3-52354.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$2144 + attribute \src "libresoc.v:51521.3-51539.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:51784.3-51811.6" + wire width 2 $2\fsm_state$131$next[1:0]$1819 + attribute \src "libresoc.v:52385.3-52430.6" + wire width 2 $2\fsm_state$next[1:0]$2155 + attribute \src "libresoc.v:51572.3-51595.6" + wire width 32 $2\ilatch$next[31:0]$1791 + attribute \src "libresoc.v:52268.3-52283.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52284.3-52308.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52309.3-52333.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:51596.3-51615.6" + wire $2\ivalid_i[0:0] + attribute \src "libresoc.v:51984.3-51999.6" + wire width 4 $2\msr__ren[3:0] + attribute \src "libresoc.v:52355.3-52384.6" + wire $2\msr_read$next[0:0]$2149 + attribute \src "libresoc.v:51913.3-51928.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:52009.3-52033.6" + wire $2\pc_changed$next[0:0]$1848 + attribute \src "libresoc.v:52194.3-52230.6" + wire width 32 $2\raw_insn_i$next[31:0]$2129 + attribute \src "libresoc.v:51942.3-51962.6" + wire width 4 $2\wen[3:0] + attribute \src "libresoc.v:52231.3-52267.6" + wire $3\bigendian_i$next[0:0]$2136 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $3\core_asmcode$next[7:0]$2028 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $3\core_core_cia$next[63:0]$2029 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $3\core_core_cr_rd$next[7:0]$2030 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_cr_rd_ok$next[0:0]$2031 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $3\core_core_cr_wr$next[7:0]$2032 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_cr_wr_ok$next[0:0]$2033 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$50$next[0:0]$2034 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$51$next[0:0]$2035 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$52$next[0:0]$2036 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$53$next[0:0]$2037 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$54$next[0:0]$2038 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$55$next[0:0]$2039 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$56$next[0:0]$2040 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_exc_$signal$next[0:0]$2041 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 12 $3\core_core_fn_unit$next[11:0]$2042 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 2 $3\core_core_input_carry$next[1:0]$2043 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 32 $3\core_core_insn$next[31:0]$2044 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 7 $3\core_core_insn_type$next[6:0]$2045 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_is_32bit$next[0:0]$2046 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_lk$next[0:0]$2047 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 64 $3\core_core_msr$next[63:0]$2048 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_oe$next[0:0]$2049 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_oe_ok$next[0:0]$2050 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_rc$next[0:0]$2051 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_core_rc_ok$next[0:0]$2052 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 13 $3\core_core_trapaddr$next[12:0]$2053 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 8 $3\core_core_traptype$next[7:0]$2054 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_cr_in1$next[2:0]$2055 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_cr_in1_ok$next[0:0]$2056 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_cr_in2$48$next[2:0]$2057 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_cr_in2$next[2:0]$2058 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_cr_in2_ok$49$next[0:0]$2059 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_cr_in2_ok$next[0:0]$2060 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_cr_out$next[2:0]$2061 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_cr_out_ok$next[0:0]$2062 + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $3\core_dec$next[63:0]$1784 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $3\core_ea$next[4:0]$2063 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_ea_ok$next[0:0]$2064 + attribute \src "libresoc.v:51540.3-51571.6" + wire $3\core_eint$next[0:0]$1785 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_fast1$next[2:0]$2065 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_fast1_ok$next[0:0]$2066 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_fast2$next[2:0]$2067 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_fast2_ok$next[0:0]$2068 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_fasto1$next[2:0]$2069 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_fasto1_ok$next[0:0]$2070 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_fasto2$next[2:0]$2071 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_fasto2_ok$next[0:0]$2072 + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $3\core_msr$next[63:0]$1786 + attribute \src "libresoc.v:51540.3-51571.6" + wire width 64 $3\core_pc$next[63:0]$1787 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $3\core_reg1$next[4:0]$2073 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_reg1_ok$next[0:0]$2074 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $3\core_reg2$next[4:0]$2075 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_reg2_ok$next[0:0]$2076 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $3\core_reg3$next[4:0]$2077 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_reg3_ok$next[0:0]$2078 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 5 $3\core_rego$next[4:0]$2079 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_rego_ok$next[0:0]$2080 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $3\core_spr1$next[9:0]$2081 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_spr1_ok$next[0:0]$2082 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 10 $3\core_spro$next[9:0]$2083 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_spro_ok$next[0:0]$2084 + attribute \src "libresoc.v:52034.3-52156.6" + wire width 3 $3\core_xer_in$next[2:0]$2085 + attribute \src "libresoc.v:52034.3-52156.6" + wire $3\core_xer_out$next[0:0]$2086 + attribute \src "libresoc.v:51963.3-51983.6" + wire width 64 $3\data_i[63:0] + attribute \src "libresoc.v:51500.3-51520.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$1769 + attribute \src "libresoc.v:52334.3-52354.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$2145 + attribute \src "libresoc.v:52385.3-52430.6" + wire width 2 $3\fsm_state$next[1:0]$2156 + attribute \src "libresoc.v:51572.3-51595.6" + wire width 32 $3\ilatch$next[31:0]$1792 + attribute \src "libresoc.v:52284.3-52308.6" + wire $3\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52309.3-52333.6" + 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$ne$libresoc.v:50801$1627_Y + attribute \src "libresoc.v:50780.19-50780.102" + wire $not$libresoc.v:50780$1604_Y + attribute \src "libresoc.v:50781.19-50781.107" + wire $not$libresoc.v:50781$1605_Y + attribute \src "libresoc.v:50782.19-50782.109" + wire $not$libresoc.v:50782$1606_Y + attribute \src "libresoc.v:50785.19-50785.107" + wire $not$libresoc.v:50785$1609_Y + attribute \src "libresoc.v:50786.19-50786.109" + wire $not$libresoc.v:50786$1610_Y + attribute \src "libresoc.v:50788.19-50788.100" + wire $not$libresoc.v:50788$1612_Y + attribute \src "libresoc.v:50802.18-50802.103" + wire $not$libresoc.v:50802$1628_Y + attribute \src "libresoc.v:50805.18-50805.98" + wire $not$libresoc.v:50805$1631_Y + attribute \src "libresoc.v:50806.18-50806.101" + wire $not$libresoc.v:50806$1632_Y + attribute \src "libresoc.v:50807.18-50807.101" + wire $not$libresoc.v:50807$1633_Y + attribute \src "libresoc.v:50808.18-50808.101" + wire $not$libresoc.v:50808$1634_Y + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire \$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire \$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire \$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire \$123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + wire width 32 \$117 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire width 3 \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:288" + wire width 32 \$121 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + wire width 7 \$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393" + wire width 65 \$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393" + wire width 65 \$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" + wire width 65 \$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" + wire width 65 \$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" wire \$15 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + wire width 4 \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" wire \$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" wire \$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 \$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 5 \$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 4 \$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 5 \$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 5 \$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 \$81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 \$83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 \$85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 \$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire \all_rd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \all_rd_dly$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire \all_rd_pulse - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire \alu_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire \alu_done_dly$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire \alu_pulse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 5 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 333 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 169 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 324 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 334 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + wire \bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:94" + wire \bigendian_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:105" + wire output 3 \busy_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 351 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \core_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \core_asmcode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:104" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + wire width 64 \core_core_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + wire width 64 \core_core_cia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \core_core_cr_rd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_trap0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast1$1 + wire width 8 \core_core_cr_rd$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_trap0_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast2$2 + wire \core_core_cr_rd_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_trap0_msr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire \alu_trap0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire \alu_trap0_n_valid_o + wire \core_core_cr_rd_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_trap0_nia + wire width 8 \core_core_cr_wr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 \alu_trap0_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire \alu_trap0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire \alu_trap0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__cia$next + wire width 8 \core_core_cr_wr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \core_core_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \core_core_cr_wr_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$55$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$56$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \core_core_exc_$signal$next attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -392518,14 +139626,22 @@ module \trap0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_trap0_trap_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 \alu_trap0_trap_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_trap0_trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_trap0_trap_op__insn$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 12 \core_core_fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 12 \core_core_fn_unit$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 \core_core_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 \core_core_input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 \core_core_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 \core_core_insn$next attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -392600,138 +139716,584 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_trap0_trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire \alu_trap0_trap_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \alu_trap0_trap_op__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \alu_trap0_trap_op__ldst_exc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_trap0_trap_op__msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \alu_trap0_trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 \alu_trap0_trap_op__traptype$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire output 12 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire input 11 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 \core_core_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 \core_core_insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \core_core_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \core_core_is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \core_core_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \core_core_lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \core_core_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \core_core_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire 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input 13 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire \cu_shadown_i + wire \cu_ad__rel_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 22 \cu_wr__go_i + wire \cu_st__go_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 21 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 5 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r0__o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r1__fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__fast2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r2__fast2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r3__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r3__nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r3__nia_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r4__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r4__msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r4__msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire \data_r4__msr_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 23 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 26 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 27 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 29 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 31 \dest5_o + wire \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \cu_st__rel_o_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \cu_st__rel_o_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \cu_st__rel_o_rise + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + wire \d_cr_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" + wire \d_cr_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + wire \d_reg_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:333" + wire \d_reg_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" + wire \d_xer_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" + wire \d_xer_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dbg_core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dbg_core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" + wire \dbg_core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:97" + wire \dbg_core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" + wire \dbg_core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" + wire width 7 \dbg_d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" + wire \dbg_d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" + wire width 64 \dbg_d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:76" + wire \dbg_d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire \dbg_dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 \dbg_dmi_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 \dbg_dmi_din$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 \dbg_dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire \dbg_dmi_req_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire \dbg_dmi_we_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:102" + wire \dbg_terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \dec2_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:446" + wire \dec2_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" + wire width 64 \dec2_cia attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 24 \fast1_ok + wire width 3 \dec2_cr_in1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 25 \fast2_ok - attribute \src "libresoc.v:186900.7-186900.15" - wire \initial + wire \dec2_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec2_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec2_cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec2_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \dec2_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \dec2_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 \dec2_cur_dec$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire \dec2_cur_eint$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 \dec2_cur_msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 \dec2_cur_pc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \dec2_exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec2_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 30 \msr_ok + wire width 3 \dec2_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \dec2_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_fasto1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 28 \nia_ok + wire width 3 \dec2_fasto2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire output 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \opc_l_q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 6 \oper_i_alu_trap0__cia + wire \dec2_fasto2_ok attribute \enum_base_type "Function" attribute \enum_value_000000000000 "NONE" attribute \enum_value_000000000010 "ALU" @@ -392745,10 +140307,16 @@ module \trap0 attribute \enum_value_001000000000 "DIV" attribute \enum_value_010000000000 "SPR" attribute \enum_value_100000000000 "MMU" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 12 input 3 \oper_i_alu_trap0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 4 \oper_i_alu_trap0__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 12 \dec2_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 \dec2_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 \dec2_insn attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" attribute \enum_value_0000001 "OP_NOP" @@ -392823,4951 +140391,6346 @@ module \trap0 attribute \enum_value_1001001 "OP_SC" attribute \enum_value_1001010 "OP_MTMSR" attribute \enum_value_1001011 "OP_TLBIE" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \oper_i_alu_trap0__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire input 7 \oper_i_alu_trap0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 10 \oper_i_alu_trap0__ldst_exc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \oper_i_alu_trap0__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 9 \oper_i_alu_trap0__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 8 input 8 \oper_i_alu_trap0__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire \req_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rok_l_r_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire \rst_l_r_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 17 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 18 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 19 \src4_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187495$13922 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 \dec2_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire \dec2_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire \dec2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \dec2_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:445" + wire width 32 \dec2_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 \dec2_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute 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\enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + wire width 2 \fsm_state$131 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + wire width 2 \fsm_state$131$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \full_rd2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \full_rd2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 6 \full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \full_rd__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 14 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 8 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 13 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 10 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 12 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 11 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 335 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 341 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 336 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 337 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 338 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 342 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 339 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 340 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 348 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 343 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 345 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 347 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 349 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 346 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 350 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:197" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \imem_wb_icache_en + attribute \src "libresoc.v:48722.7-48722.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 344 \int_level_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 \issue__addr$135 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:98" + wire \issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" + wire \ivalid_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \jtag_dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 331 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 325 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 327 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 332 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 330 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 326 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 328 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 329 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \msr__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:391" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:408" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:204" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 7 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 6 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:102" + wire width 64 output 5 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:205" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \raw_insn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:93" + wire width 32 \raw_insn_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 167 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 168 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 322 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 323 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:172" + wire \ti_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" + cell $add $add$libresoc.v:50797$1623 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$95 - connect \B \$97 - connect \Y $and$libresoc.v:187495$13922_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:50797$1623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" + cell $add $add$libresoc.v:50804$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:50804$1630_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187496$13923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50779$1603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187496$13923_Y + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:50779$1603_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187497$13924 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50783$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187497$13924_Y + connect \A \$103 + connect \B \$105 + connect \Y $and$libresoc.v:50783$1607_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187498$13925 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50787$1611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187498$13925_Y + connect \A \$109 + connect \B \$111 + connect \Y $and$libresoc.v:50787$1611_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187499$13926 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$libresoc.v:50803$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187499$13926_Y + connect \A \cu_st__rel_o + connect \B \$21 + connect \Y $and$libresoc.v:50803$1629_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187500$13927 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50812$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187500$13927_Y + connect \A \$38 + connect \B \$40 + connect \Y $and$libresoc.v:50812$1638_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187501$13928 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + cell $and $and$libresoc.v:50813$1639 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:187501$13928_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \state_nia_wen + connect \B 1'1 + connect \Y $and$libresoc.v:50813$1639_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187502$13929 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50820$1646 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \$111 - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187502$13929_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \$65 + connect \Y $and$libresoc.v:50820$1646_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187503$13930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50823$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187503$13930_Y + connect \A \$69 + connect \B \$71 + connect \Y $and$libresoc.v:50823$1649_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187504$13931 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50826$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187504$13931_Y + connect \A \$75 + connect \B \$77 + connect \Y $and$libresoc.v:50826$1652_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:187505$13932 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50829$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \$5 - connect \Y $and$libresoc.v:187505$13932_Y + connect \A \$81 + connect \B \$83 + connect \Y $and$libresoc.v:50829$1655_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187506$13933 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $and $and$libresoc.v:50832$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187506$13933_Y + connect \A \$87 + connect \B \$89 + connect \Y $and$libresoc.v:50832$1658_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:50794$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_rd2__data_o + connect \Y $extend$libresoc.v:50794$1618_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$libresoc.v:50795$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \full_rd__data_o + connect \Y $extend$libresoc.v:50795$1620_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187507$13934 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:50789$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187507$13934_Y + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:50789$1613_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187508$13935 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$libresoc.v:50791$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$libresoc.v:50791$1615_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + cell $ne $ne$libresoc.v:50784$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187508$13935_Y + connect \A \delay + connect \B 1'0 + connect \Y $ne$libresoc.v:50784$1608_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:187510$13937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + cell $ne $ne$libresoc.v:50793$1617 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 7 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B \$13 - connect \Y $and$libresoc.v:187510$13937_Y + connect \A \core_core_insn_type + connect \B 7'0000001 + connect \Y $ne$libresoc.v:50793$1617_Y end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $and$libresoc.v:187512$13939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $ne $ne$libresoc.v:50801$1627 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \alu_done + connect \A \delay connect \B \$17 - connect \Y $and$libresoc.v:187512$13939_Y + connect \Y $ne$libresoc.v:50801$1627_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:187513$13940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50780$1604 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187513$13940_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50780$1604_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187515$13942 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50781$1605 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__rel_o - connect \B \$25 - connect \Y $and$libresoc.v:187515$13942_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50781$1605_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187518$13945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50782$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \$23 - connect \Y $and$libresoc.v:187518$13945_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50782$1606_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:187522$13949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50785$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:187522$13949_Y + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50785$1609_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:187524$13951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50786$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B \$39 - connect \Y $and$libresoc.v:187524$13951_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50786$1610_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187525$13952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + cell $not $not$libresoc.v:50788$1612 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187525$13952_Y + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:50788$1612_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187527$13954 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$libresoc.v:50802$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$41 - connect \B \$45 - connect \Y $and$libresoc.v:187527$13954_Y + connect \A \cu_st__rel_o_dly + connect \Y $not$libresoc.v:50802$1628_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187529$13956 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206" + cell $not $not$libresoc.v:50805$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $not$libresoc.v:50805$1631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50806$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50806$1632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + cell $not $not$libresoc.v:50807$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:50807$1633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50808$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50808$1634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + cell $not $not$libresoc.v:50809$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$libresoc.v:50809$1635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50810$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50810$1636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50811$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50811$1637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50815$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50815$1641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50816$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50816$1642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + cell $not $not$libresoc.v:50817$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \corebusy_o + connect \Y $not$libresoc.v:50817$1643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50818$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50818$1644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50819$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50819$1645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50821$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50821$1647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50822$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50822$1648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50824$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50824$1650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50825$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50825$1651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50827$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50827$1653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50828$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50828$1654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50830$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50830$1656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50831$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50831$1657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + cell $not $not$libresoc.v:50833$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$libresoc.v:50833$1659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50834$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$libresoc.v:50834$1660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + cell $not $not$libresoc.v:50835$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$49 - connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:187529$13956_Y + connect \A \core_coresync_rst + connect \Y $not$libresoc.v:50835$1661_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187530$13957 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $or $or$libresoc.v:50799$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$51 - connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:187530$13957_Y + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $or$libresoc.v:50799$1625_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187531$13958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180" + cell $or $or$libresoc.v:50800$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$53 - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187531$13958_Y + connect \A \$15 + connect \B \rst + connect \Y $or$libresoc.v:50800$1626_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:50794$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:50794$1618_Y + connect \Y $pos$libresoc.v:50794$1619_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$libresoc.v:50795$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:50795$1620_Y + connect \Y $pos$libresoc.v:50795$1621_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:50814$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \Y $reduce_or$libresoc.v:50814$1640_Y + end + attribute \src "libresoc.v:50790.19-50790.42" + cell $shr $shr$libresoc.v:50790$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$118 + connect \Y $shr$libresoc.v:50790$1614_Y + end + attribute \src "libresoc.v:50792.19-50792.42" + cell $shr $shr$libresoc.v:50792$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$122 + connect \Y $shr$libresoc.v:50792$1616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393" + cell $sub $sub$libresoc.v:50796$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:50796$1622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + cell $sub $sub$libresoc.v:50798$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:50798$1624_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51008.8-51011.4" + cell \core \core + connect \coresync_clk \coresync_clk + connect \coresync_rst \core_coresync_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51012.7-51037.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51038.8-51104.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$1 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$2 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \exc_$signal \dec2_exc_$signal + connect \exc_$signal$3 \dec2_exc_$signal$3 + connect \exc_$signal$4 \dec2_exc_$signal$4 + connect \exc_$signal$5 \dec2_exc_$signal$5 + connect \exc_$signal$6 \dec2_exc_$signal$6 + connect \exc_$signal$7 \dec2_exc_$signal$7 + connect \exc_$signal$8 \dec2_exc_$signal$8 + connect \exc_$signal$9 \dec2_exc_$signal$9 + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51105.8-51121.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51122.8-51452.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \clk \clk + connect \dmi0__ack_o \jtag_dmi0__ack_o + connect \dmi0__addr_i \jtag_dmi0__addr_i + connect \dmi0__din \jtag_dmi0__din + connect \dmi0__dout \jtag_dmi0__dout + connect \dmi0__req_i \jtag_dmi0__req_i + connect \dmi0__we_i \jtag_dmi0__we_i + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + 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\sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51453.12-51467.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:51468.12-51481.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst + end + attribute \src "libresoc.v:48722.7-48722.20" + process $proc$libresoc.v:48722$2161 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:48854.7-48854.25" + process $proc$libresoc.v:48854$2162 + assign { } { } + assign $1\bigendian_i[0:0] 1'0 + sync always + sync init + update \bigendian_i $1\bigendian_i[0:0] + end + attribute \src "libresoc.v:48866.13-48866.33" + process $proc$libresoc.v:48866$2163 + assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "libresoc.v:48872.14-48872.50" + process $proc$libresoc.v:48872$2164 + assign { } { } + assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_cia $1\core_core_cia[63:0] + end + attribute \src "libresoc.v:48876.13-48876.36" + process $proc$libresoc.v:48876$2165 + assign { } { } + assign $1\core_core_cr_rd[7:0] 8'00000000 + sync always + sync init + update \core_core_cr_rd $1\core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:48880.7-48880.32" + process $proc$libresoc.v:48880$2166 + assign { } { } + assign $1\core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:48884.13-48884.36" + process $proc$libresoc.v:48884$2167 + assign { } { } + assign $1\core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_cr_wr $1\core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:48888.7-48888.32" + process $proc$libresoc.v:48888$2168 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:48892.7-48892.37" + process $proc$libresoc.v:48892$2169 + assign { } { } + assign $0\core_core_exc_$signal[0:0]$2170 1'0 + sync always + sync init + update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$2170 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:187536$13963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187536$13963_Y + attribute \src "libresoc.v:48894.7-48894.40" + process $proc$libresoc.v:48894$2171 + assign { } { } + assign $0\core_core_exc_$signal$50[0:0]$2172 1'0 + sync always + sync init + update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$2172 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:187537$13964 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187537$13964_Y + attribute \src "libresoc.v:48898.7-48898.40" + process $proc$libresoc.v:48898$2173 + assign { } { } + assign $0\core_core_exc_$signal$51[0:0]$2174 1'0 + sync always + sync init + update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$2174 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187540$13967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187540$13967_Y + attribute \src "libresoc.v:48902.7-48902.40" + process $proc$libresoc.v:48902$2175 + assign { } { } + assign $0\core_core_exc_$signal$52[0:0]$2176 1'0 + sync always + sync init + update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$2176 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187541$13968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187541$13968_Y + attribute \src "libresoc.v:48906.7-48906.40" + process $proc$libresoc.v:48906$2177 + assign { } { } + assign $0\core_core_exc_$signal$53[0:0]$2178 1'0 + sync always + sync init + update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$2178 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187542$13969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast2_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187542$13969_Y + attribute \src "libresoc.v:48910.7-48910.40" + process $proc$libresoc.v:48910$2179 + assign { } { } + assign $0\core_core_exc_$signal$54[0:0]$2180 1'0 + sync always + sync init + update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$2180 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187543$13970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \nia_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187543$13970_Y + attribute \src "libresoc.v:48914.7-48914.40" + process $proc$libresoc.v:48914$2181 + assign { } { } + assign $0\core_core_exc_$signal$55[0:0]$2182 1'0 + sync always + sync init + update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$2182 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187544$13971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_ok - connect \B \cu_busy_o - connect \Y $and$libresoc.v:187544$13971_Y + attribute \src "libresoc.v:48918.7-48918.40" + process $proc$libresoc.v:48918$2183 + assign { } { } + assign $0\core_core_exc_$signal$56[0:0]$2184 1'0 + sync always + sync init + update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$2184 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:187550$13977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:187550$13977_Y + attribute \src "libresoc.v:48937.14-48937.41" + process $proc$libresoc.v:48937$2185 + assign { } { } + assign $1\core_core_fn_unit[11:0] 12'000000000000 + sync always + sync init + update \core_core_fn_unit $1\core_core_fn_unit[11:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:187551$13978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:187551$13978_Y + attribute \src "libresoc.v:48945.13-48945.41" + process $proc$libresoc.v:48945$2186 + assign { } { } + assign $1\core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_input_carry $1\core_core_input_carry[1:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187552$13979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187552$13979_Y + attribute \src "libresoc.v:48949.14-48949.36" + process $proc$libresoc.v:48949$2187 + assign { } { } + assign $1\core_core_insn[31:0] 0 + sync always + sync init + update \core_core_insn $1\core_core_insn[31:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187553$13980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$93 - connect \B 4'1111 - connect \Y $and$libresoc.v:187553$13980_Y + attribute \src "libresoc.v:49027.13-49027.40" + process $proc$libresoc.v:49027$2188 + assign { } { } + assign $1\core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_insn_type $1\core_core_insn_type[6:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:187526$13953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$43 - connect \B 1'0 - connect \Y $eq$libresoc.v:187526$13953_Y + attribute \src "libresoc.v:49031.7-49031.32" + process $proc$libresoc.v:49031$2189 + assign { } { } + assign $1\core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_is_32bit $1\core_core_is_32bit[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:187528$13955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $eq$libresoc.v:187528$13955_Y + attribute \src "libresoc.v:49035.7-49035.26" + process $proc$libresoc.v:49035$2190 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:187509$13936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $not$libresoc.v:187509$13936_Y + attribute \src "libresoc.v:49039.14-49039.50" + process $proc$libresoc.v:49039$2191 + assign { } { } + assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_msr $1\core_core_msr[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $not$libresoc.v:187511$13938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $not$libresoc.v:187511$13938_Y + attribute \src "libresoc.v:49043.7-49043.26" + process $proc$libresoc.v:49043$2192 + assign { } { } + assign $1\core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_oe $1\core_core_oe[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187514$13941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:187514$13941_Y + attribute \src "libresoc.v:49047.7-49047.29" + process $proc$libresoc.v:49047$2193 + assign { } { } + assign $1\core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_oe_ok $1\core_core_oe_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187517$13944 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:187517$13944_Y + attribute \src "libresoc.v:49051.7-49051.26" + process $proc$libresoc.v:49051$2194 + assign { } { } + assign $1\core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_rc $1\core_core_rc[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:187523$13950 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:187523$13950_Y + attribute \src "libresoc.v:49055.7-49055.29" + process $proc$libresoc.v:49055$2195 + assign { } { } + assign $1\core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_rc_ok $1\core_core_rc_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:187538$13965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:187538$13965_Y + attribute \src "libresoc.v:49059.14-49059.43" + process $proc$libresoc.v:49059$2196 + assign { } { } + assign $1\core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_trapaddr $1\core_core_trapaddr[12:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:187554$13981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:187554$13981_Y + attribute \src "libresoc.v:49063.13-49063.39" + process $proc$libresoc.v:49063$2197 + assign { } { } + assign $1\core_core_traptype[7:0] 8'00000000 + sync always + sync init + update \core_core_traptype $1\core_core_traptype[7:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:187521$13948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$33 - connect \B \$35 - connect \Y $or$libresoc.v:187521$13948_Y + attribute \src "libresoc.v:49069.13-49069.31" + process $proc$libresoc.v:49069$2198 + assign { } { } + assign $1\core_cr_in1[2:0] 3'000 + sync always + sync init + update \core_cr_in1 $1\core_cr_in1[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:187532$13959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187532$13959_Y + attribute \src "libresoc.v:49073.7-49073.28" + process $proc$libresoc.v:49073$2199 + assign { } { } + assign $1\core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_cr_in1_ok $1\core_cr_in1_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:187533$13960 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187533$13960_Y + attribute \src "libresoc.v:49077.13-49077.31" + process $proc$libresoc.v:49077$2200 + assign { } { } + assign $1\core_cr_in2[2:0] 3'000 + sync always + sync init + update \core_cr_in2 $1\core_cr_in2[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:187534$13961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187534$13961_Y + attribute \src "libresoc.v:49079.13-49079.36" + process $proc$libresoc.v:49079$2201 + assign { } { } + assign $0\core_cr_in2$48[2:0]$2202 3'000 + sync always + sync init + update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$2202 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:187535$13962 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187535$13962_Y + attribute \src "libresoc.v:49085.7-49085.28" + process $proc$libresoc.v:49085$2203 + assign { } { } + assign $1\core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_cr_in2_ok $1\core_cr_in2_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:187539$13966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $or$libresoc.v:187539$13966_Y + attribute \src "libresoc.v:49087.7-49087.33" + process $proc$libresoc.v:49087$2204 + assign { } { } + assign $0\core_cr_in2_ok$49[0:0]$2205 1'0 + sync always + sync init + update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$2205 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:187549$13976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \$6 - connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:187549$13976_Y + attribute \src "libresoc.v:49093.13-49093.31" + process $proc$libresoc.v:49093$2206 + assign { } { } + assign $1\core_cr_out[2:0] 3'000 + sync always + sync init + update \core_cr_out $1\core_cr_out[2:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:187494$13921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $reduce_and$libresoc.v:187494$13921_Y + attribute \src "libresoc.v:49097.7-49097.28" + process $proc$libresoc.v:49097$2207 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:187516$13943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \$27 - connect \Y $reduce_or$libresoc.v:187516$13943_Y + attribute \src "libresoc.v:49101.14-49101.45" + process $proc$libresoc.v:49101$2208 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187519$13946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:187519$13946_Y + attribute \src "libresoc.v:49105.13-49105.28" + process $proc$libresoc.v:49105$2209 + assign { } { } + assign $1\core_ea[4:0] 5'00000 + sync always + sync init + update \core_ea $1\core_ea[4:0] end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187520$13947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:187520$13947_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187545$13972 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:187545$13972_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187546$13973 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:187546$13973_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187547$13974 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:187547$13974_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $ternary$libresoc.v:187548$13975 - parameter \WIDTH 64 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:187548$13975_Y + attribute \src "libresoc.v:49109.7-49109.24" + process $proc$libresoc.v:49109$2210 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187631.14-187637.4" - cell \alu_l$45 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu + attribute \src "libresoc.v:49113.7-49113.23" + process $proc$libresoc.v:49113$2211 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187638.13-187668.4" - cell \alu_trap0 \alu_trap0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \fast1 \alu_trap0_fast1 - connect \fast1$1 \alu_trap0_fast1$1 - connect \fast1_ok \fast1_ok - connect \fast2 \alu_trap0_fast2 - connect \fast2$2 \alu_trap0_fast2$2 - connect \fast2_ok \fast2_ok - connect \msr \alu_trap0_msr - connect \msr_ok \msr_ok - connect \n_ready_i \alu_trap0_n_ready_i - connect \n_valid_o \alu_trap0_n_valid_o - connect \nia \alu_trap0_nia - connect \nia_ok \nia_ok - connect \o \alu_trap0_o - connect \o_ok \o_ok - connect \p_ready_o \alu_trap0_p_ready_o - connect \p_valid_i \alu_trap0_p_valid_i - connect \ra \alu_trap0_ra - connect \rb \alu_trap0_rb - connect \trap_op__cia \alu_trap0_trap_op__cia - connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit - connect \trap_op__insn \alu_trap0_trap_op__insn - connect \trap_op__insn_type \alu_trap0_trap_op__insn_type - connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit - connect \trap_op__ldst_exc \alu_trap0_trap_op__ldst_exc - connect \trap_op__msr \alu_trap0_trap_op__msr - connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr - connect \trap_op__traptype \alu_trap0_trap_op__traptype + attribute \src "libresoc.v:49117.13-49117.30" + process $proc$libresoc.v:49117$2212 + assign { } { } + assign $1\core_fast1[2:0] 3'000 + sync always + sync init + update \core_fast1 $1\core_fast1[2:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187669.15-187675.4" - cell \alui_l$44 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui + attribute \src "libresoc.v:49121.7-49121.27" + process $proc$libresoc.v:49121$2213 + assign { } { } + assign $1\core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_fast1_ok $1\core_fast1_ok[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187676.14-187682.4" - cell \opc_l$40 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_opc \opc_l_q_opc - connect \r_opc \opc_l_r_opc - connect \s_opc \opc_l_s_opc + attribute \src "libresoc.v:49125.13-49125.30" + process $proc$libresoc.v:49125$2214 + assign { } { } + assign $1\core_fast2[2:0] 3'000 + sync always + sync init + update \core_fast2 $1\core_fast2[2:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187683.14-187689.4" - cell \req_l$41 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \r_req \req_l_r_req - connect \s_req \req_l_s_req + attribute \src "libresoc.v:49129.7-49129.27" + process $proc$libresoc.v:49129$2215 + assign { } { } + assign $1\core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_fast2_ok $1\core_fast2_ok[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187690.14-187696.4" - cell \rok_l$43 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \r_rdok \rok_l_r_rdok - connect \s_rdok \rok_l_s_rdok + attribute \src "libresoc.v:49133.13-49133.31" + process $proc$libresoc.v:49133$2216 + assign { } { } + assign $1\core_fasto1[2:0] 3'000 + sync always + sync init + update \core_fasto1 $1\core_fasto1[2:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187697.14-187702.4" - cell \rst_l$42 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_rst \rst_l_r_rst - connect \s_rst \rst_l_s_rst + attribute \src "libresoc.v:49137.7-49137.28" + process $proc$libresoc.v:49137$2217 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:187703.14-187709.4" - cell \src_l$39 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_src \src_l_q_src - connect \r_src \src_l_r_src - connect \s_src \src_l_s_src + attribute \src "libresoc.v:49141.13-49141.31" + process $proc$libresoc.v:49141$2218 + assign { } { } + assign $1\core_fasto2[2:0] 3'000 + sync always + sync init + update \core_fasto2 $1\core_fasto2[2:0] end - attribute \src "libresoc.v:186900.7-186900.20" - process $proc$libresoc.v:186900$14136 + attribute \src "libresoc.v:49145.7-49145.28" + process $proc$libresoc.v:49145$2219 assign { } { } - assign $0\initial[0:0] 1'0 + assign $1\core_fasto2_ok[0:0] 1'0 sync always - update \initial $0\initial[0:0] sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:187026.7-187026.24" - process $proc$libresoc.v:187026$14137 + attribute \src "libresoc.v:49149.14-49149.45" + process $proc$libresoc.v:49149$2220 assign { } { } - assign $1\all_rd_dly[0:0] 1'0 + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \all_rd_dly $1\all_rd_dly[0:0] + update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:187036.7-187036.26" - process $proc$libresoc.v:187036$14138 + attribute \src "libresoc.v:49153.14-49153.44" + process $proc$libresoc.v:49153$2221 assign { } { } - assign $1\alu_done_dly[0:0] 1'0 + assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_done_dly $1\alu_done_dly[0:0] + update \core_pc $1\core_pc[63:0] end - attribute \src "libresoc.v:187044.7-187044.25" - process $proc$libresoc.v:187044$14139 + attribute \src "libresoc.v:49157.13-49157.30" + process $proc$libresoc.v:49157$2222 assign { } { } - assign $1\alu_l_r_alu[0:0] 1'1 + assign $1\core_reg1[4:0] 5'00000 sync always sync init - update \alu_l_r_alu $1\alu_l_r_alu[0:0] + update \core_reg1 $1\core_reg1[4:0] end - attribute \src "libresoc.v:187080.14-187080.59" - process $proc$libresoc.v:187080$14140 + attribute \src "libresoc.v:49161.7-49161.26" + process $proc$libresoc.v:49161$2223 assign { } { } - assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_reg1_ok[0:0] 1'0 sync always sync init - update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] + update \core_reg1_ok $1\core_reg1_ok[0:0] end - attribute \src "libresoc.v:187097.14-187097.50" - process $proc$libresoc.v:187097$14141 + attribute \src "libresoc.v:49165.13-49165.30" + process $proc$libresoc.v:49165$2224 assign { } { } - assign $1\alu_trap0_trap_op__fn_unit[11:0] 12'000000000000 + assign $1\core_reg2[4:0] 5'00000 sync always sync init - update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[11:0] + update \core_reg2 $1\core_reg2[4:0] end - attribute \src "libresoc.v:187101.14-187101.45" - process $proc$libresoc.v:187101$14142 + attribute \src "libresoc.v:49169.7-49169.26" + process $proc$libresoc.v:49169$2225 assign { } { } - assign $1\alu_trap0_trap_op__insn[31:0] 0 + assign $1\core_reg2_ok[0:0] 1'0 sync always sync init - update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] + update \core_reg2_ok $1\core_reg2_ok[0:0] end - attribute \src "libresoc.v:187179.13-187179.49" - process $proc$libresoc.v:187179$14143 + attribute \src "libresoc.v:49173.13-49173.30" + process $proc$libresoc.v:49173$2226 assign { } { } - assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 + assign $1\core_reg3[4:0] 5'00000 sync always sync init - update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] + update \core_reg3 $1\core_reg3[4:0] end - attribute \src "libresoc.v:187183.7-187183.41" - process $proc$libresoc.v:187183$14144 + attribute \src "libresoc.v:49177.7-49177.26" + process $proc$libresoc.v:49177$2227 assign { } { } - assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 + assign $1\core_reg3_ok[0:0] 1'0 sync always sync init - update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] + update \core_reg3_ok $1\core_reg3_ok[0:0] end - attribute \src "libresoc.v:187187.13-187187.48" - process $proc$libresoc.v:187187$14145 + attribute \src "libresoc.v:49181.13-49181.30" + process $proc$libresoc.v:49181$2228 assign { } { } - assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 + assign $1\core_rego[4:0] 5'00000 sync always sync init - update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] + update \core_rego $1\core_rego[4:0] end - attribute \src "libresoc.v:187191.14-187191.59" - process $proc$libresoc.v:187191$14146 + attribute \src "libresoc.v:49185.7-49185.26" + process $proc$libresoc.v:49185$2229 assign { } { } - assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_rego_ok[0:0] 1'0 sync always sync init - update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] + update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:187195.14-187195.52" - process $proc$libresoc.v:187195$14147 + attribute \src "libresoc.v:49300.13-49300.32" + process $proc$libresoc.v:49300$2230 assign { } { } - assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 + assign $1\core_spr1[9:0] 10'0000000000 sync always sync init - update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] + update \core_spr1 $1\core_spr1[9:0] end - attribute \src "libresoc.v:187199.13-187199.48" - process $proc$libresoc.v:187199$14148 + attribute \src "libresoc.v:49304.7-49304.26" + process $proc$libresoc.v:49304$2231 assign { } { } - assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 + assign $1\core_spr1_ok[0:0] 1'0 sync always sync init - update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] + update \core_spr1_ok $1\core_spr1_ok[0:0] end - attribute \src "libresoc.v:187205.7-187205.27" - process $proc$libresoc.v:187205$14149 + attribute \src "libresoc.v:49419.13-49419.32" + process $proc$libresoc.v:49419$2232 assign { } { } - assign $1\alui_l_r_alui[0:0] 1'1 + assign $1\core_spro[9:0] 10'0000000000 sync always sync init - update \alui_l_r_alui $1\alui_l_r_alui[0:0] + update \core_spro $1\core_spro[9:0] end - attribute \src "libresoc.v:187237.14-187237.47" - process $proc$libresoc.v:187237$14150 + attribute \src "libresoc.v:49423.7-49423.26" + process $proc$libresoc.v:49423$2233 assign { } { } - assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_spro_ok[0:0] 1'0 sync always sync init - update \data_r0__o $1\data_r0__o[63:0] + update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:187241.7-187241.27" - process $proc$libresoc.v:187241$14151 + attribute \src "libresoc.v:49431.13-49431.31" + process $proc$libresoc.v:49431$2234 assign { } { } - assign $1\data_r0__o_ok[0:0] 1'0 + assign $1\core_xer_in[2:0] 3'000 sync always sync init - update \data_r0__o_ok $1\data_r0__o_ok[0:0] + update \core_xer_in $1\core_xer_in[2:0] end - attribute \src "libresoc.v:187245.14-187245.51" - process $proc$libresoc.v:187245$14152 + attribute \src "libresoc.v:49435.7-49435.26" + process $proc$libresoc.v:49435$2235 assign { } { } - assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_xer_out[0:0] 1'0 sync always sync init - update \data_r1__fast1 $1\data_r1__fast1[63:0] + update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:187249.7-187249.31" - process $proc$libresoc.v:187249$14153 + attribute \src "libresoc.v:49451.7-49451.30" + process $proc$libresoc.v:49451$2236 assign { } { } - assign $1\data_r1__fast1_ok[0:0] 1'0 + assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init - update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:187253.14-187253.51" - process $proc$libresoc.v:187253$14154 + attribute \src "libresoc.v:49457.7-49457.24" + process $proc$libresoc.v:49457$2237 assign { } { } - assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\d_cr_delay[0:0] 1'0 sync always sync init - update \data_r2__fast2 $1\data_r2__fast2[63:0] + update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:187257.7-187257.31" - process $proc$libresoc.v:187257$14155 + attribute \src "libresoc.v:49461.7-49461.25" + process $proc$libresoc.v:49461$2238 assign { } { } - assign $1\data_r2__fast2_ok[0:0] 1'0 + assign $1\d_reg_delay[0:0] 1'0 sync always sync init - update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] + update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:187261.14-187261.49" - process $proc$libresoc.v:187261$14156 + attribute \src "libresoc.v:49465.7-49465.25" + process $proc$libresoc.v:49465$2239 assign { } { } - assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\d_xer_delay[0:0] 1'0 sync always sync init - update \data_r3__nia $1\data_r3__nia[63:0] + update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:187265.7-187265.29" - process $proc$libresoc.v:187265$14157 + attribute \src "libresoc.v:49503.13-49503.34" + process $proc$libresoc.v:49503$2240 assign { } { } - assign $1\data_r3__nia_ok[0:0] 1'0 + assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init - update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:187269.14-187269.49" - process $proc$libresoc.v:187269$14158 + attribute \src "libresoc.v:49507.14-49507.48" + process $proc$libresoc.v:49507$2241 assign { } { } - assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \data_r4__msr $1\data_r4__msr[63:0] + update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:187273.7-187273.29" - process $proc$libresoc.v:187273$14159 + attribute \src "libresoc.v:49513.7-49513.27" + process $proc$libresoc.v:49513$2242 assign { } { } - assign $1\data_r4__msr_ok[0:0] 1'0 + assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init - update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:187304.7-187304.25" - process $proc$libresoc.v:187304$14160 + attribute \src "libresoc.v:49517.7-49517.26" + process $proc$libresoc.v:49517$2243 assign { } { } - assign $1\opc_l_r_opc[0:0] 1'1 + assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init - update \opc_l_r_opc $1\opc_l_r_opc[0:0] + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:187308.7-187308.25" - process $proc$libresoc.v:187308$14161 + attribute \src "libresoc.v:49553.14-49553.49" + process $proc$libresoc.v:49553$2244 assign { } { } - assign $1\opc_l_s_opc[0:0] 1'0 + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \opc_l_s_opc $1\opc_l_s_opc[0:0] + update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:187417.13-187417.31" - process $proc$libresoc.v:187417$14162 + attribute \src "libresoc.v:49557.7-49557.27" + process $proc$libresoc.v:49557$2245 assign { } { } - assign $1\prev_wr_go[4:0] 5'00000 + assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init - update \prev_wr_go $1\prev_wr_go[4:0] + update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:187425.13-187425.32" - process $proc$libresoc.v:187425$14163 + attribute \src "libresoc.v:49561.14-49561.49" + process $proc$libresoc.v:49561$2246 assign { } { } - assign $1\req_l_r_req[4:0] 5'11111 + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \req_l_r_req $1\req_l_r_req[4:0] + update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:187429.13-187429.32" - process $proc$libresoc.v:187429$14164 + attribute \src "libresoc.v:49565.14-49565.48" + process $proc$libresoc.v:49565$2247 assign { } { } - assign $1\req_l_s_req[4:0] 5'00000 + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \req_l_s_req $1\req_l_s_req[4:0] + update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:187441.7-187441.26" - process $proc$libresoc.v:187441$14165 + attribute \src "libresoc.v:49974.13-49974.25" + process $proc$libresoc.v:49974$2248 assign { } { } - assign $1\rok_l_r_rdok[0:0] 1'1 + assign $1\delay[1:0] 2'11 sync always sync init - update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + update \delay $1\delay[1:0] end - attribute \src "libresoc.v:187445.7-187445.26" - process $proc$libresoc.v:187445$14166 + attribute \src "libresoc.v:49996.13-49996.29" + process $proc$libresoc.v:49996$2249 assign { } { } - assign $1\rok_l_s_rdok[0:0] 1'0 + assign $1\fsm_state[1:0] 2'00 sync always sync init - update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:187449.7-187449.25" - process $proc$libresoc.v:187449$14167 + attribute \src "libresoc.v:49998.13-49998.35" + process $proc$libresoc.v:49998$2250 assign { } { } - assign $1\rst_l_r_rst[0:0] 1'1 + assign $0\fsm_state$131[1:0]$2251 2'00 sync always sync init - update \rst_l_r_rst $1\rst_l_r_rst[0:0] + update \fsm_state$131 $0\fsm_state$131[1:0]$2251 end - attribute \src "libresoc.v:187453.7-187453.25" - process $proc$libresoc.v:187453$14168 + attribute \src "libresoc.v:50248.14-50248.28" + process $proc$libresoc.v:50248$2252 assign { } { } - assign $1\rst_l_s_rst[0:0] 1'0 + assign $1\ilatch[31:0] 0 sync always sync init - update \rst_l_s_rst $1\rst_l_s_rst[0:0] + update \ilatch $1\ilatch[31:0] end - attribute \src "libresoc.v:187469.13-187469.31" - process $proc$libresoc.v:187469$14169 + attribute \src "libresoc.v:50282.7-50282.30" + process $proc$libresoc.v:50282$2253 assign { } { } - assign $1\src_l_r_src[3:0] 4'1111 + assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init - update \src_l_r_src $1\src_l_r_src[3:0] + update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:187473.13-187473.31" - process $proc$libresoc.v:187473$14170 + attribute \src "libresoc.v:50290.14-50290.52" + process $proc$libresoc.v:50290$2254 assign { } { } - assign $1\src_l_s_src[3:0] 4'0000 + assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \src_l_s_src $1\src_l_s_src[3:0] + update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:187477.14-187477.43" - process $proc$libresoc.v:187477$14171 + attribute \src "libresoc.v:50350.7-50350.22" + process $proc$libresoc.v:50350$2255 assign { } { } - assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_read[0:0] 1'1 sync always sync init - update \src_r0 $1\src_r0[63:0] + update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:187481.14-187481.43" - process $proc$libresoc.v:187481$14172 + attribute \src "libresoc.v:50378.7-50378.24" + process $proc$libresoc.v:50378$2256 assign { } { } - assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\pc_changed[0:0] 1'0 sync always sync init - update \src_r1 $1\src_r1[63:0] + update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:187485.14-187485.43" - process $proc$libresoc.v:187485$14173 + attribute \src "libresoc.v:50388.7-50388.25" + process $proc$libresoc.v:50388$2257 assign { } { } - assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\pc_ok_delay[0:0] 1'0 sync always sync init - update \src_r2 $1\src_r2[63:0] + update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:187489.14-187489.43" - process $proc$libresoc.v:187489$14174 + attribute \src "libresoc.v:50402.14-50402.32" + process $proc$libresoc.v:50402$2258 assign { } { } - assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\raw_insn_i[31:0] 0 sync always sync init - update \src_r3 $1\src_r3[63:0] + update \raw_insn_i $1\raw_insn_i[31:0] end - attribute \src "libresoc.v:187555.3-187556.39" - process $proc$libresoc.v:187555$13982 + attribute \src "libresoc.v:50836.3-50837.41" + process $proc$libresoc.v:50836$1662 assign { } { } - assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next - sync posedge \coresync_clk - update \alu_l_r_alu $0\alu_l_r_alu[0:0] + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:187557.3-187558.43" - process $proc$libresoc.v:187557$13983 + attribute \src "libresoc.v:50838.3-50839.33" + process $proc$libresoc.v:50838$1663 assign { } { } - assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next - sync posedge \coresync_clk - update \alui_l_r_alui $0\alui_l_r_alui[0:0] + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:187559.3-187560.29" - process $proc$libresoc.v:187559$13984 + attribute \src "libresoc.v:50840.3-50841.41" + process $proc$libresoc.v:50840$1664 assign { } { } - assign $0\src_r3[63:0] \src_r3$next - sync posedge \coresync_clk - update \src_r3 $0\src_r3[63:0] + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:187561.3-187562.29" - process $proc$libresoc.v:187561$13985 + attribute \src "libresoc.v:50842.3-50843.35" + process $proc$libresoc.v:50842$1665 assign { } { } - assign $0\src_r2[63:0] \src_r2$next - sync posedge \coresync_clk - update \src_r2 $0\src_r2[63:0] + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:187563.3-187564.29" - process $proc$libresoc.v:187563$13986 + attribute \src "libresoc.v:50844.3-50845.33" + process $proc$libresoc.v:50844$1666 assign { } { } - assign $0\src_r1[63:0] \src_r1$next - sync posedge \coresync_clk - update \src_r1 $0\src_r1[63:0] + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:187565.3-187566.29" - process $proc$libresoc.v:187565$13987 + attribute \src "libresoc.v:50846.3-50847.39" + process $proc$libresoc.v:50846$1667 assign { } { } - assign $0\src_r0[63:0] \src_r0$next - sync posedge \coresync_clk - update \src_r0 $0\src_r0[63:0] + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:187567.3-187568.41" - process $proc$libresoc.v:187567$13988 + attribute \src "libresoc.v:50848.3-50849.39" + process $proc$libresoc.v:50848$1668 assign { } { } - assign $0\data_r4__msr[63:0] \data_r4__msr$next - sync posedge \coresync_clk - update \data_r4__msr $0\data_r4__msr[63:0] + assign $0\bigendian_i[0:0] \bigendian_i$next + sync posedge \clk + update \bigendian_i $0\bigendian_i[0:0] end - attribute \src "libresoc.v:187569.3-187570.47" - process $proc$libresoc.v:187569$13989 + attribute \src "libresoc.v:50850.3-50851.37" + process $proc$libresoc.v:50850$1669 assign { } { } - assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next - sync posedge \coresync_clk - update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] + assign $0\raw_insn_i[31:0] \raw_insn_i$next + sync posedge \clk + update \raw_insn_i $0\raw_insn_i[31:0] end - attribute \src "libresoc.v:187571.3-187572.41" - process $proc$libresoc.v:187571$13990 + attribute \src "libresoc.v:50852.3-50853.41" + process $proc$libresoc.v:50852$1670 assign { } { } - assign $0\data_r3__nia[63:0] \data_r3__nia$next - sync posedge \coresync_clk - update \data_r3__nia $0\data_r3__nia[63:0] + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:187573.3-187574.47" - process $proc$libresoc.v:187573$13991 + attribute \src "libresoc.v:50854.3-50855.35" + process $proc$libresoc.v:50854$1671 assign { } { } - assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next - sync posedge \coresync_clk - update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] + assign $0\core_rego[4:0] \core_rego$next + sync posedge \clk + update \core_rego $0\core_rego[4:0] end - attribute \src "libresoc.v:187575.3-187576.45" - process $proc$libresoc.v:187575$13992 + attribute \src "libresoc.v:50856.3-50857.41" + process $proc$libresoc.v:50856$1672 assign { } { } - assign $0\data_r2__fast2[63:0] \data_r2__fast2$next - sync posedge \coresync_clk - update \data_r2__fast2 $0\data_r2__fast2[63:0] + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:187577.3-187578.51" - process $proc$libresoc.v:187577$13993 + attribute \src "libresoc.v:50858.3-50859.45" + process $proc$libresoc.v:50858$1673 assign { } { } - assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next - sync posedge \coresync_clk - update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] + assign $0\fsm_state$131[1:0]$1674 \fsm_state$131$next + sync posedge \clk + update \fsm_state$131 $0\fsm_state$131[1:0]$1674 end - attribute \src "libresoc.v:187579.3-187580.45" - process $proc$libresoc.v:187579$13994 + attribute \src "libresoc.v:50860.3-50861.31" + process $proc$libresoc.v:50860$1675 assign { } { } - assign $0\data_r1__fast1[63:0] \data_r1__fast1$next - sync posedge \coresync_clk - update \data_r1__fast1 $0\data_r1__fast1[63:0] + assign $0\core_ea[4:0] \core_ea$next + sync posedge \clk + update \core_ea $0\core_ea[4:0] end - attribute \src "libresoc.v:187581.3-187582.51" - process $proc$libresoc.v:187581$13995 + attribute \src "libresoc.v:50862.3-50863.37" + process $proc$libresoc.v:50862$1676 assign { } { } - assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next - sync posedge \coresync_clk - update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:187583.3-187584.37" - process $proc$libresoc.v:187583$13996 + attribute \src "libresoc.v:50864.3-50865.35" + process $proc$libresoc.v:50864$1677 assign { } { } - assign $0\data_r0__o[63:0] \data_r0__o$next - sync posedge \coresync_clk - update \data_r0__o $0\data_r0__o[63:0] + assign $0\core_reg1[4:0] \core_reg1$next + sync posedge \clk + update \core_reg1 $0\core_reg1[4:0] end - attribute \src "libresoc.v:187585.3-187586.43" - process $proc$libresoc.v:187585$13997 + attribute \src "libresoc.v:50866.3-50867.41" + process $proc$libresoc.v:50866$1678 assign { } { } - assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next - sync posedge \coresync_clk - update \data_r0__o_ok $0\data_r0__o_ok[0:0] + assign $0\core_reg1_ok[0:0] \core_reg1_ok$next + sync posedge \clk + update \core_reg1_ok $0\core_reg1_ok[0:0] end - attribute \src "libresoc.v:187587.3-187588.73" - process $proc$libresoc.v:187587$13998 + attribute \src "libresoc.v:50868.3-50869.35" + process $proc$libresoc.v:50868$1679 assign { } { } - assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] + assign $0\core_reg2[4:0] \core_reg2$next + sync posedge \clk + update \core_reg2 $0\core_reg2[4:0] end - attribute \src "libresoc.v:187589.3-187590.69" - process $proc$libresoc.v:187589$13999 + attribute \src "libresoc.v:50870.3-50871.41" + process $proc$libresoc.v:50870$1680 assign { } { } - assign $0\alu_trap0_trap_op__fn_unit[11:0] \alu_trap0_trap_op__fn_unit$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[11:0] + assign $0\core_reg2_ok[0:0] \core_reg2_ok$next + sync posedge \clk + update \core_reg2_ok $0\core_reg2_ok[0:0] end - attribute \src "libresoc.v:187591.3-187592.63" - process $proc$libresoc.v:187591$14000 + attribute \src "libresoc.v:50872.3-50873.35" + process $proc$libresoc.v:50872$1681 assign { } { } - assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] + assign $0\core_reg3[4:0] \core_reg3$next + sync posedge \clk + update \core_reg3 $0\core_reg3[4:0] end - attribute \src "libresoc.v:187593.3-187594.61" - process $proc$libresoc.v:187593$14001 + attribute \src "libresoc.v:50874.3-50875.41" + process $proc$libresoc.v:50874$1682 assign { } { } - assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] + assign $0\core_reg3_ok[0:0] \core_reg3_ok$next + sync posedge \clk + update \core_reg3_ok $0\core_reg3_ok[0:0] end - attribute \src "libresoc.v:187595.3-187596.61" - process $proc$libresoc.v:187595$14002 + attribute \src "libresoc.v:50876.3-50877.35" + process $proc$libresoc.v:50876$1683 assign { } { } - assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] + assign $0\core_spro[9:0] \core_spro$next + sync posedge \clk + update \core_spro $0\core_spro[9:0] end - attribute \src "libresoc.v:187597.3-187598.71" - process $proc$libresoc.v:187597$14003 + attribute \src "libresoc.v:50878.3-50879.41" + process $proc$libresoc.v:50878$1684 assign { } { } - assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:187599.3-187600.71" - process $proc$libresoc.v:187599$14004 + attribute \src "libresoc.v:50880.3-50881.39" + process $proc$libresoc.v:50880$1685 assign { } { } - assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:187601.3-187602.71" - process $proc$libresoc.v:187601$14005 + attribute \src "libresoc.v:50882.3-50883.35" + process $proc$libresoc.v:50882$1686 assign { } { } - assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] + assign $0\core_spr1[9:0] \core_spr1$next + sync posedge \clk + update \core_spr1 $0\core_spr1[9:0] end - attribute \src "libresoc.v:187603.3-187604.71" - process $proc$libresoc.v:187603$14006 + attribute \src "libresoc.v:50884.3-50885.41" + process $proc$libresoc.v:50884$1687 assign { } { } - assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next - sync posedge \coresync_clk - update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] + assign $0\core_spr1_ok[0:0] \core_spr1_ok$next + sync posedge \clk + update \core_spr1_ok $0\core_spr1_ok[0:0] end - attribute \src "libresoc.v:187605.3-187606.39" - process $proc$libresoc.v:187605$14007 + attribute \src "libresoc.v:50886.3-50887.39" + process $proc$libresoc.v:50886$1688 assign { } { } - assign $0\req_l_r_req[4:0] \req_l_r_req$next - sync posedge \coresync_clk - update \req_l_r_req $0\req_l_r_req[4:0] + assign $0\core_xer_in[2:0] \core_xer_in$next + sync posedge \clk + update \core_xer_in $0\core_xer_in[2:0] end - attribute \src "libresoc.v:187607.3-187608.39" - process $proc$libresoc.v:187607$14008 + attribute \src "libresoc.v:50888.3-50889.41" + process $proc$libresoc.v:50888$1689 assign { } { } - assign $0\req_l_s_req[4:0] \req_l_s_req$next - sync posedge \coresync_clk - update \req_l_s_req $0\req_l_s_req[4:0] + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:187609.3-187610.39" - process $proc$libresoc.v:187609$14009 + attribute \src "libresoc.v:50890.3-50891.37" + process $proc$libresoc.v:50890$1690 assign { } { } - assign $0\src_l_r_src[3:0] \src_l_r_src$next - sync posedge \coresync_clk - update \src_l_r_src $0\src_l_r_src[3:0] + assign $0\core_fast1[2:0] \core_fast1$next + sync posedge \clk + update \core_fast1 $0\core_fast1[2:0] end - attribute \src "libresoc.v:187611.3-187612.39" - process $proc$libresoc.v:187611$14010 + attribute \src "libresoc.v:50892.3-50893.43" + process $proc$libresoc.v:50892$1691 assign { } { } - assign $0\src_l_s_src[3:0] \src_l_s_src$next - sync posedge \coresync_clk - update \src_l_s_src $0\src_l_s_src[3:0] + assign $0\core_fast1_ok[0:0] \core_fast1_ok$next + sync posedge \clk + update \core_fast1_ok $0\core_fast1_ok[0:0] end - attribute \src "libresoc.v:187613.3-187614.39" - process $proc$libresoc.v:187613$14011 + attribute \src "libresoc.v:50894.3-50895.37" + process $proc$libresoc.v:50894$1692 assign { } { } - assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next - sync posedge \coresync_clk - update \opc_l_r_opc $0\opc_l_r_opc[0:0] + assign $0\core_fast2[2:0] \core_fast2$next + sync posedge \clk + update \core_fast2 $0\core_fast2[2:0] end - attribute \src "libresoc.v:187615.3-187616.39" - process $proc$libresoc.v:187615$14012 + attribute \src "libresoc.v:50896.3-50897.43" + process $proc$libresoc.v:50896$1693 assign { } { } - assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next - sync posedge \coresync_clk - update \opc_l_s_opc $0\opc_l_s_opc[0:0] + assign $0\core_fast2_ok[0:0] \core_fast2_ok$next + sync posedge \clk + update \core_fast2_ok $0\core_fast2_ok[0:0] end - attribute \src "libresoc.v:187617.3-187618.39" - process $proc$libresoc.v:187617$14013 + attribute \src "libresoc.v:50898.3-50899.39" + process $proc$libresoc.v:50898$1694 assign { } { } - assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next - sync posedge \coresync_clk - update \rst_l_r_rst $0\rst_l_r_rst[0:0] + assign $0\core_fasto1[2:0] \core_fasto1$next + sync posedge \clk + update \core_fasto1 $0\core_fasto1[2:0] end - attribute \src "libresoc.v:187619.3-187620.39" - process $proc$libresoc.v:187619$14014 + attribute \src "libresoc.v:50900.3-50901.45" + process $proc$libresoc.v:50900$1695 assign { } { } - assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next - sync posedge \coresync_clk - update \rst_l_s_rst $0\rst_l_s_rst[0:0] + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:187621.3-187622.41" - process $proc$libresoc.v:187621$14015 + attribute \src "libresoc.v:50902.3-50903.37" + process $proc$libresoc.v:50902$1696 assign { } { } - assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next - sync posedge \coresync_clk - update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:187623.3-187624.41" - process $proc$libresoc.v:187623$14016 + attribute \src "libresoc.v:50904.3-50905.39" + process $proc$libresoc.v:50904$1697 assign { } { } - assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next - sync posedge \coresync_clk - update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + assign $0\core_fasto2[2:0] \core_fasto2$next + sync posedge \clk + update \core_fasto2 $0\core_fasto2[2:0] end - attribute \src "libresoc.v:187625.3-187626.37" - process $proc$libresoc.v:187625$14017 + attribute \src "libresoc.v:50906.3-50907.45" + process $proc$libresoc.v:50906$1698 assign { } { } - assign $0\prev_wr_go[4:0] \prev_wr_go$next - sync posedge \coresync_clk - update \prev_wr_go $0\prev_wr_go[4:0] + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:187627.3-187628.41" - process $proc$libresoc.v:187627$14018 + attribute \src "libresoc.v:50908.3-50909.39" + process $proc$libresoc.v:50908$1699 assign { } { } - assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o - sync posedge \coresync_clk - update \alu_done_dly $0\alu_done_dly[0:0] + assign $0\core_cr_in1[2:0] \core_cr_in1$next + sync posedge \clk + update \core_cr_in1 $0\core_cr_in1[2:0] end - attribute \src "libresoc.v:187629.3-187630.25" - process $proc$libresoc.v:187629$14019 + attribute \src "libresoc.v:50910.3-50911.45" + process $proc$libresoc.v:50910$1700 assign { } { } - assign $0\all_rd_dly[0:0] \$11 - sync posedge \coresync_clk - update \all_rd_dly $0\all_rd_dly[0:0] + assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next + sync posedge \clk + update \core_cr_in1_ok $0\core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:50912.3-50913.39" + process $proc$libresoc.v:50912$1701 + assign { } { } + assign $0\core_cr_in2[2:0] \core_cr_in2$next + sync posedge \clk + update \core_cr_in2 $0\core_cr_in2[2:0] + end + attribute \src "libresoc.v:50914.3-50915.45" + process $proc$libresoc.v:50914$1702 + assign { } { } + assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next + sync posedge \clk + update \core_cr_in2_ok $0\core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:50916.3-50917.47" + process $proc$libresoc.v:50916$1703 + assign { } { } + assign $0\core_cr_in2$48[2:0]$1704 \core_cr_in2$48$next + sync posedge \clk + update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$1704 + end + attribute \src "libresoc.v:50918.3-50919.53" + process $proc$libresoc.v:50918$1705 + assign { } { } + assign $0\core_cr_in2_ok$49[0:0]$1706 \core_cr_in2_ok$49$next + sync posedge \clk + update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$1706 + end + attribute \src "libresoc.v:50920.3-50921.39" + process $proc$libresoc.v:50920$1707 + assign { } { } + assign $0\core_cr_out[2:0] \core_cr_out$next + sync posedge \clk + update \core_cr_out $0\core_cr_out[2:0] + end + attribute \src "libresoc.v:50922.3-50923.45" + process $proc$libresoc.v:50922$1708 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:50924.3-50925.39" + process $proc$libresoc.v:50924$1709 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:50926.3-50927.43" + process $proc$libresoc.v:50926$1710 + assign { } { } + assign $0\core_core_msr[63:0] \core_core_msr$next + sync posedge \clk + update \core_core_msr $0\core_core_msr[63:0] + end + attribute \src "libresoc.v:50928.3-50929.43" + process $proc$libresoc.v:50928$1711 + assign { } { } + assign $0\core_core_cia[63:0] \core_core_cia$next + sync posedge \clk + update \core_core_cia $0\core_core_cia[63:0] + end + attribute \src "libresoc.v:50930.3-50931.45" + process $proc$libresoc.v:50930$1712 + assign { } { } + assign $0\core_core_insn[31:0] \core_core_insn$next + sync posedge \clk + update \core_core_insn $0\core_core_insn[31:0] + end + attribute \src "libresoc.v:50932.3-50933.55" + process $proc$libresoc.v:50932$1713 + assign { } { } + assign $0\core_core_insn_type[6:0] \core_core_insn_type$next + sync posedge \clk + update \core_core_insn_type $0\core_core_insn_type[6:0] + end + attribute \src "libresoc.v:50934.3-50935.51" + process $proc$libresoc.v:50934$1714 + assign { } { } + assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next + sync posedge \clk + update \core_core_fn_unit $0\core_core_fn_unit[11:0] + end + attribute \src "libresoc.v:50936.3-50937.41" + process $proc$libresoc.v:50936$1715 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:50938.3-50939.41" + process $proc$libresoc.v:50938$1716 + assign { } { } + assign $0\core_core_rc[0:0] \core_core_rc$next + sync posedge \clk + update \core_core_rc $0\core_core_rc[0:0] + end + attribute \src "libresoc.v:50940.3-50941.47" + process $proc$libresoc.v:50940$1717 + assign { } { } + assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next + sync posedge \clk + update \core_core_rc_ok $0\core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:50942.3-50943.41" + process $proc$libresoc.v:50942$1718 + assign { } { } + assign $0\core_core_oe[0:0] \core_core_oe$next + sync posedge \clk + update \core_core_oe $0\core_core_oe[0:0] + end + attribute \src "libresoc.v:50944.3-50945.47" + process $proc$libresoc.v:50944$1719 + assign { } { } + assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next + sync posedge \clk + update \core_core_oe_ok $0\core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:50946.3-50947.29" + process $proc$libresoc.v:50946$1720 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:50948.3-50949.59" + process $proc$libresoc.v:50948$1721 + assign { } { } + assign $0\core_core_input_carry[1:0] \core_core_input_carry$next + sync posedge \clk + update \core_core_input_carry $0\core_core_input_carry[1:0] + end + attribute \src "libresoc.v:50950.3-50951.53" + process $proc$libresoc.v:50950$1722 + assign { } { } + assign $0\core_core_traptype[7:0] \core_core_traptype$next + sync posedge \clk + update \core_core_traptype $0\core_core_traptype[7:0] + end + attribute \src "libresoc.v:50952.3-50953.61" + process $proc$libresoc.v:50952$1723 + assign { } { } + assign $0\core_core_exc_$signal[0:0]$1724 \core_core_exc_$signal$next + sync posedge \clk + update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$1724 + end + attribute \src "libresoc.v:50954.3-50955.67" + process $proc$libresoc.v:50954$1725 + assign { } { } + assign $0\core_core_exc_$signal$50[0:0]$1726 \core_core_exc_$signal$50$next + sync posedge \clk + update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$1726 + end + attribute \src "libresoc.v:50956.3-50957.67" + process $proc$libresoc.v:50956$1727 + assign { } { } + assign $0\core_core_exc_$signal$51[0:0]$1728 \core_core_exc_$signal$51$next + sync posedge \clk + update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$1728 + end + attribute \src "libresoc.v:50958.3-50959.67" + process $proc$libresoc.v:50958$1729 + assign { } { } + assign $0\core_core_exc_$signal$52[0:0]$1730 \core_core_exc_$signal$52$next + sync posedge \clk + update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$1730 + end + attribute \src "libresoc.v:50960.3-50961.67" + process $proc$libresoc.v:50960$1731 + assign { } { } + assign $0\core_core_exc_$signal$53[0:0]$1732 \core_core_exc_$signal$53$next + sync posedge \clk + update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$1732 + end + attribute \src "libresoc.v:50962.3-50963.67" + process $proc$libresoc.v:50962$1733 + assign { } { } + assign $0\core_core_exc_$signal$54[0:0]$1734 \core_core_exc_$signal$54$next + sync posedge \clk + update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$1734 + end + attribute \src "libresoc.v:50964.3-50965.67" + process $proc$libresoc.v:50964$1735 + assign { } { } + assign $0\core_core_exc_$signal$55[0:0]$1736 \core_core_exc_$signal$55$next + sync posedge \clk + update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$1736 + end + attribute \src "libresoc.v:50966.3-50967.67" + process $proc$libresoc.v:50966$1737 + assign { } { } + assign $0\core_core_exc_$signal$56[0:0]$1738 \core_core_exc_$signal$56$next + sync posedge \clk + update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$1738 + end + attribute \src "libresoc.v:50968.3-50969.31" + process $proc$libresoc.v:50968$1739 + assign { } { } + assign $0\core_pc[63:0] \core_pc$next + sync posedge \clk + update \core_pc $0\core_pc[63:0] + end + attribute \src "libresoc.v:50970.3-50971.53" + process $proc$libresoc.v:50970$1740 + assign { } { } + assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next + sync posedge \clk + update \core_core_trapaddr $0\core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:50972.3-50973.47" + process $proc$libresoc.v:50972$1741 + assign { } { } + assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next + sync posedge \clk + update \core_core_cr_rd $0\core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:50974.3-50975.53" + process $proc$libresoc.v:50974$1742 + assign { } { } + assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:50976.3-50977.47" + process $proc$libresoc.v:50976$1743 + assign { } { } + assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next + sync posedge \clk + update \core_core_cr_wr $0\core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:50978.3-50979.53" + process $proc$libresoc.v:50978$1744 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:50980.3-50981.53" + process $proc$libresoc.v:50980$1745 + assign { } { } + assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next + sync posedge \clk + update \core_core_is_32bit $0\core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:50982.3-50983.37" + process $proc$libresoc.v:50982$1746 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:50984.3-50985.39" + process $proc$libresoc.v:50984$1747 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:50986.3-50987.30" + process $proc$libresoc.v:50986$1748 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] 1'0 + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:50988.3-50989.27" + process $proc$libresoc.v:50988$1749 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:50990.3-50991.33" + process $proc$libresoc.v:50990$1750 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:50992.3-50993.43" + process $proc$libresoc.v:50992$1751 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:50994.3-50995.47" + process $proc$libresoc.v:50994$1752 + assign { } { } + assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next + sync posedge \clk + update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:50996.3-50997.49" + process $proc$libresoc.v:50996$1753 + assign { } { } + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + sync posedge \clk + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:50998.3-50999.39" + process $proc$libresoc.v:50998$1754 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:51000.3-51001.41" + process $proc$libresoc.v:51000$1755 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:51002.3-51003.43" + process $proc$libresoc.v:51002$1756 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:51004.3-51005.45" + process $proc$libresoc.v:51004$1757 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:51006.3-51007.35" + process $proc$libresoc.v:51006$1758 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:187710.3-187719.6" - process $proc$libresoc.v:187710$14020 + attribute \src "libresoc.v:51482.3-51490.6" + process $proc$libresoc.v:51482$1759 assign { } { } assign { } { } - assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:187711.5-187711.29" + assign $0\dbg_dmi_addr_i$next[3:0]$1760 $1\dbg_dmi_addr_i$next[3:0]$1761 + attribute \src "libresoc.v:51483.5-51483.29" switch \initial - attribute \src "libresoc.v:187711.9-187711.17" + attribute \src "libresoc.v:51483.9-51483.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch \$55 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_done[0:0] 1'1 + assign $1\dbg_dmi_addr_i$next[3:0]$1761 4'0000 case - assign $1\req_done[0:0] \$47 + assign $1\dbg_dmi_addr_i$next[3:0]$1761 \jtag_dmi0__addr_i end sync always - update \req_done $0\req_done[0:0] + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1760 end - attribute \src "libresoc.v:187720.3-187728.6" - process $proc$libresoc.v:187720$14021 + attribute \src "libresoc.v:51491.3-51499.6" + process $proc$libresoc.v:51491$1762 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14022 $1\rok_l_s_rdok$next[0:0]$14023 - attribute \src "libresoc.v:187721.5-187721.29" + assign $0\dbg_dmi_req_i$next[0:0]$1763 $1\dbg_dmi_req_i$next[0:0]$1764 + attribute \src "libresoc.v:51492.5-51492.29" switch \initial - attribute \src "libresoc.v:187721.9-187721.17" + attribute \src "libresoc.v:51492.9-51492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14023 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$1764 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14023 \cu_issue_i + assign $1\dbg_dmi_req_i$next[0:0]$1764 \jtag_dmi0__req_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14022 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1763 end - attribute \src "libresoc.v:187729.3-187737.6" - process $proc$libresoc.v:187729$14024 + attribute \src "libresoc.v:51500.3-51520.6" + process $proc$libresoc.v:51500$1765 + assign { } { } assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14025 $1\rok_l_r_rdok$next[0:0]$14026 - attribute \src "libresoc.v:187730.5-187730.29" + assign $0\dec2_cur_msr$next[63:0]$1766 $3\dec2_cur_msr$next[63:0]$1769 + attribute \src "libresoc.v:51501.5-51501.29" switch \initial - attribute \src "libresoc.v:187730.9-187730.17" + attribute \src "libresoc.v:51501.9-51501.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$1767 $2\dec2_cur_msr$next[63:0]$1768 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$1768 \msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$1768 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$1767 \dec2_cur_msr + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14026 1'1 + assign $3\dec2_cur_msr$next[63:0]$1769 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\rok_l_r_rdok$next[0:0]$14026 \$65 + assign $3\dec2_cur_msr$next[63:0]$1769 $1\dec2_cur_msr$next[63:0]$1767 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14025 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1766 end - attribute \src "libresoc.v:187738.3-187746.6" - process $proc$libresoc.v:187738$14027 + attribute \src "libresoc.v:51521.3-51539.6" + process $proc$libresoc.v:51521$1770 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14028 $1\rst_l_s_rst$next[0:0]$14029 - attribute \src "libresoc.v:187739.5-187739.29" + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:51522.5-51522.29" switch \initial - attribute \src "libresoc.v:187739.9-187739.17" + attribute \src "libresoc.v:51522.9-51522.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14029 1'0 + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$117 + end case - assign $1\rst_l_s_rst$next[0:0]$14029 \all_rd + assign $1\dec2_raw_opcode_in[31:0] 0 end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14028 + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:187747.3-187755.6" - process $proc$libresoc.v:187747$14030 + attribute \src "libresoc.v:51540.3-51571.6" + process $proc$libresoc.v:51540$1771 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14031 $1\rst_l_r_rst$next[0:0]$14032 - attribute \src "libresoc.v:187748.5-187748.29" + assign { } { } + assign $0\core_dec$next[63:0]$1772 $3\core_dec$next[63:0]$1784 + assign $0\core_eint$next[0:0]$1773 $3\core_eint$next[0:0]$1785 + assign $0\core_msr$next[63:0]$1774 $3\core_msr$next[63:0]$1786 + assign $0\core_pc$next[63:0]$1775 $3\core_pc$next[63:0]$1787 + attribute \src "libresoc.v:51541.5-51541.29" switch \initial - attribute \src "libresoc.v:187748.9-187748.17" + attribute \src "libresoc.v:51541.9-51541.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_dec$next[63:0]$1776 $2\core_dec$next[63:0]$1780 + assign $1\core_eint$next[0:0]$1777 $2\core_eint$next[0:0]$1781 + assign $1\core_msr$next[63:0]$1778 $2\core_msr$next[63:0]$1782 + assign $1\core_pc$next[63:0]$1779 $2\core_pc$next[63:0]$1783 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_dec$next[63:0]$1780 \core_dec + assign $2\core_eint$next[0:0]$1781 \core_eint + assign $2\core_msr$next[63:0]$1782 \core_msr + assign $2\core_pc$next[63:0]$1783 \core_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$1780 $2\core_eint$next[0:0]$1781 $2\core_msr$next[63:0]$1782 $2\core_pc$next[63:0]$1783 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_dec$next[63:0]$1776 \core_dec + assign $1\core_eint$next[0:0]$1777 \core_eint + assign $1\core_msr$next[63:0]$1778 \core_msr + assign $1\core_pc$next[63:0]$1779 \core_pc + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14032 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $3\core_pc$next[63:0]$1787 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$1786 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$1785 1'0 + assign $3\core_dec$next[63:0]$1784 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\rst_l_r_rst$next[0:0]$14032 \rst_r + assign $3\core_dec$next[63:0]$1784 $1\core_dec$next[63:0]$1776 + assign $3\core_eint$next[0:0]$1785 $1\core_eint$next[0:0]$1777 + assign $3\core_msr$next[63:0]$1786 $1\core_msr$next[63:0]$1778 + assign $3\core_pc$next[63:0]$1787 $1\core_pc$next[63:0]$1779 end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14031 + update \core_dec$next $0\core_dec$next[63:0]$1772 + update \core_eint$next $0\core_eint$next[0:0]$1773 + update \core_msr$next $0\core_msr$next[63:0]$1774 + update \core_pc$next $0\core_pc$next[63:0]$1775 end - attribute \src "libresoc.v:187756.3-187764.6" - process $proc$libresoc.v:187756$14033 + attribute \src "libresoc.v:51572.3-51595.6" + process $proc$libresoc.v:51572$1788 + assign { } { } assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14034 $1\opc_l_s_opc$next[0:0]$14035 - attribute \src "libresoc.v:187757.5-187757.29" + assign $0\ilatch$next[31:0]$1789 $3\ilatch$next[31:0]$1792 + attribute \src "libresoc.v:51573.5-51573.29" switch \initial - attribute \src "libresoc.v:187757.9-187757.17" + attribute \src "libresoc.v:51573.9-51573.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$1790 $2\ilatch$next[31:0]$1791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$1791 \ilatch + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$1791 \$121 + end + case + assign $1\ilatch$next[31:0]$1790 \ilatch + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14035 1'0 + assign $3\ilatch$next[31:0]$1792 0 case - assign $1\opc_l_s_opc$next[0:0]$14035 \cu_issue_i + assign $3\ilatch$next[31:0]$1792 $1\ilatch$next[31:0]$1790 end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14034 + update \ilatch$next $0\ilatch$next[31:0]$1789 end - attribute \src "libresoc.v:187765.3-187773.6" - process $proc$libresoc.v:187765$14036 + attribute \src "libresoc.v:51596.3-51615.6" + process $proc$libresoc.v:51596$1793 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14037 $1\opc_l_r_opc$next[0:0]$14038 - attribute \src "libresoc.v:187766.5-187766.29" + assign $0\ivalid_i[0:0] $1\ivalid_i[0:0] + attribute \src "libresoc.v:51597.5-51597.29" switch \initial - attribute \src "libresoc.v:187766.9-187766.17" + attribute \src "libresoc.v:51597.9-51597.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 + assign { } { } + assign $1\ivalid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14038 1'1 + assign $1\ivalid_i[0:0] $2\ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ivalid_i[0:0] 1'1 + case + assign $2\ivalid_i[0:0] 1'0 + end case - assign $1\opc_l_r_opc$next[0:0]$14038 \req_done + assign $1\ivalid_i[0:0] 1'0 end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14037 + update \ivalid_i $0\ivalid_i[0:0] end - attribute \src "libresoc.v:187774.3-187782.6" - process $proc$libresoc.v:187774$14039 + attribute \src "libresoc.v:51616.3-51626.6" + process $proc$libresoc.v:51616$1794 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14040 $1\src_l_s_src$next[3:0]$14041 - attribute \src "libresoc.v:187775.5-187775.29" + assign $0\issue_i[0:0] $1\issue_i[0:0] + attribute \src "libresoc.v:51617.5-51617.29" switch \initial - attribute \src "libresoc.v:187775.9-187775.17" + attribute \src "libresoc.v:51617.9-51617.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'10 assign { } { } - assign $1\src_l_s_src$next[3:0]$14041 4'0000 + assign $1\issue_i[0:0] 1'1 case - assign $1\src_l_s_src$next[3:0]$14041 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\issue_i[0:0] 1'0 end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14040 + update \issue_i $0\issue_i[0:0] end - attribute \src "libresoc.v:187783.3-187791.6" - process $proc$libresoc.v:187783$14042 + attribute \src "libresoc.v:51627.3-51636.6" + process $proc$libresoc.v:51627$1795 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14043 $1\src_l_r_src$next[3:0]$14044 - attribute \src "libresoc.v:187784.5-187784.29" + assign $0\dmi__addr[4:0] $1\dmi__addr[4:0] + attribute \src "libresoc.v:51628.5-51628.29" switch \initial - attribute \src "libresoc.v:187784.9-187784.17" + attribute \src "libresoc.v:51628.9-51628.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14044 4'1111 + assign $1\dmi__addr[4:0] \dbg_d_gpr_addr [4:0] case - assign $1\src_l_r_src$next[3:0]$14044 \reset_r + assign $1\dmi__addr[4:0] 5'00000 end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14043 + update \dmi__addr $0\dmi__addr[4:0] end - attribute \src "libresoc.v:187792.3-187800.6" - process $proc$libresoc.v:187792$14045 + attribute \src "libresoc.v:51637.3-51646.6" + process $proc$libresoc.v:51637$1796 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14046 $1\req_l_s_req$next[4:0]$14047 - attribute \src "libresoc.v:187793.5-187793.29" + assign $0\dmi__ren[0:0] $1\dmi__ren[0:0] + attribute \src "libresoc.v:51638.5-51638.29" switch \initial - attribute \src "libresoc.v:187793.9-187793.17" + attribute \src "libresoc.v:51638.9-51638.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" + switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14047 5'00000 + assign $1\dmi__ren[0:0] 1'1 case - assign $1\req_l_s_req$next[4:0]$14047 \$67 + assign $1\dmi__ren[0:0] 1'0 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14046 + update \dmi__ren $0\dmi__ren[0:0] end - attribute \src "libresoc.v:187801.3-187809.6" - process $proc$libresoc.v:187801$14048 + attribute \src "libresoc.v:51647.3-51655.6" + process $proc$libresoc.v:51647$1797 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14049 $1\req_l_r_req$next[4:0]$14050 - attribute \src "libresoc.v:187802.5-187802.29" + assign $0\d_reg_delay$next[0:0]$1798 $1\d_reg_delay$next[0:0]$1799 + attribute \src "libresoc.v:51648.5-51648.29" switch \initial - attribute \src "libresoc.v:187802.9-187802.17" + attribute \src "libresoc.v:51648.9-51648.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14050 5'11111 + assign $1\d_reg_delay$next[0:0]$1799 1'0 case - assign $1\req_l_r_req$next[4:0]$14050 \$69 + assign $1\d_reg_delay$next[0:0]$1799 \dbg_d_gpr_req end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14049 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1798 end - attribute \src "libresoc.v:187810.3-187827.6" - process $proc$libresoc.v:187810$14051 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:51656.3-51665.6" + process $proc$libresoc.v:51656$1800 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14052 $1\alu_trap0_trap_op__cia$next[63:0]$14061 - assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$14053 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14054 $1\alu_trap0_trap_op__insn$next[31:0]$14063 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14055 $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14056 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14057 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14066 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14058 $1\alu_trap0_trap_op__msr$next[63:0]$14067 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14059 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14068 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14060 $1\alu_trap0_trap_op__traptype$next[7:0]$14069 - attribute \src "libresoc.v:187811.5-187811.29" + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:51657.5-51657.29" switch \initial - attribute \src "libresoc.v:187811.9-187811.17" + attribute \src "libresoc.v:51657.9-51657.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14066 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14068 $1\alu_trap0_trap_op__traptype$next[7:0]$14069 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 $1\alu_trap0_trap_op__cia$next[63:0]$14061 $1\alu_trap0_trap_op__msr$next[63:0]$14067 $1\alu_trap0_trap_op__insn$next[31:0]$14063 $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign $1\dbg_d_gpr_data[63:0] \dmi__data_o case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14061 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$14062 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14063 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14064 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14065 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14066 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14067 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14068 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14069 \alu_trap0_trap_op__traptype + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14052 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$14053 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14054 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14055 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14056 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14057 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14058 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14059 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14060 + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:187828.3-187849.6" - process $proc$libresoc.v:187828$14070 - assign { } { } + attribute \src "libresoc.v:51666.3-51675.6" + process $proc$libresoc.v:51666$1801 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r0__o$next[63:0]$14071 $2\data_r0__o$next[63:0]$14075 - assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14072 $3\data_r0__o_ok$next[0:0]$14077 - attribute \src "libresoc.v:187829.5-187829.29" + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:51667.5-51667.29" switch \initial - attribute \src "libresoc.v:187829.9-187829.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14074 $1\data_r0__o$next[63:0]$14073 } { \o_ok \alu_trap0_o } - case - assign $1\data_r0__o$next[63:0]$14073 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14074 \data_r0__o_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:51667.9-51667.17" case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14076 $2\data_r0__o$next[63:0]$14075 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14075 $1\data_r0__o$next[63:0]$14073 - assign $2\data_r0__o_ok$next[0:0]$14076 $1\data_r0__o_ok$next[0:0]$14074 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:335" + switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14077 1'0 + assign $1\dbg_d_gpr_ack[0:0] 1'1 case - assign $3\data_r0__o_ok$next[0:0]$14077 $2\data_r0__o_ok$next[0:0]$14076 + assign $1\dbg_d_gpr_ack[0:0] 1'0 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14071 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14072 + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:187850.3-187871.6" - process $proc$libresoc.v:187850$14078 - assign { } { } + attribute \src "libresoc.v:51676.3-51685.6" + process $proc$libresoc.v:51676$1802 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\data_r1__fast1$next[63:0]$14079 $2\data_r1__fast1$next[63:0]$14083 - assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14080 $3\data_r1__fast1_ok$next[0:0]$14085 - attribute \src "libresoc.v:187851.5-187851.29" + assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0] + attribute \src "libresoc.v:51677.5-51677.29" switch \initial - attribute \src "libresoc.v:187851.9-187851.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:51677.9-51677.17" case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14082 $1\data_r1__fast1$next[63:0]$14081 } { \fast1_ok \alu_trap0_fast1 } - case - assign $1\data_r1__fast1$next[63:0]$14081 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14082 \data_r1__fast1_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14084 $2\data_r1__fast1$next[63:0]$14083 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14083 $1\data_r1__fast1$next[63:0]$14081 - assign $2\data_r1__fast1_ok$next[0:0]$14084 $1\data_r1__fast1_ok$next[0:0]$14082 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14085 1'0 + assign $1\full_rd2__ren[7:0] 8'11111111 case - assign $3\data_r1__fast1_ok$next[0:0]$14085 $2\data_r1__fast1_ok$next[0:0]$14084 + assign $1\full_rd2__ren[7:0] 8'00000000 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14079 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14080 + update \full_rd2__ren $0\full_rd2__ren[7:0] end - attribute \src "libresoc.v:187872.3-187893.6" - process $proc$libresoc.v:187872$14086 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:51686.3-51694.6" + process $proc$libresoc.v:51686$1803 assign { } { } - assign $0\data_r2__fast2$next[63:0]$14087 $2\data_r2__fast2$next[63:0]$14091 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14088 $3\data_r2__fast2_ok$next[0:0]$14093 - attribute \src "libresoc.v:187873.5-187873.29" + assign $0\d_cr_delay$next[0:0]$1804 $1\d_cr_delay$next[0:0]$1805 + attribute \src "libresoc.v:51687.5-51687.29" switch \initial - attribute \src "libresoc.v:187873.9-187873.17" + attribute \src "libresoc.v:51687.9-51687.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14090 $1\data_r2__fast2$next[63:0]$14089 } { \fast2_ok \alu_trap0_fast2 } - case - assign $1\data_r2__fast2$next[63:0]$14089 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14090 \data_r2__fast2_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14092 $2\data_r2__fast2$next[63:0]$14091 } 65'00000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\data_r2__fast2$next[63:0]$14091 $1\data_r2__fast2$next[63:0]$14089 - assign $2\data_r2__fast2_ok$next[0:0]$14092 $1\data_r2__fast2_ok$next[0:0]$14090 - end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14093 1'0 + assign $1\d_cr_delay$next[0:0]$1805 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14093 $2\data_r2__fast2_ok$next[0:0]$14092 + assign $1\d_cr_delay$next[0:0]$1805 \dbg_d_cr_req end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14087 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14088 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1804 end - attribute \src "libresoc.v:187894.3-187915.6" - process $proc$libresoc.v:187894$14094 - assign { } { } - assign { } { } + attribute \src "libresoc.v:51695.3-51704.6" + process $proc$libresoc.v:51695$1806 assign { } { } assign { } { } - assign { } { } - assign { } { } - assign $0\data_r3__nia$next[63:0]$14095 $2\data_r3__nia$next[63:0]$14099 - assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14096 $3\data_r3__nia_ok$next[0:0]$14101 - attribute \src "libresoc.v:187895.5-187895.29" + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:51696.5-51696.29" switch \initial - attribute \src "libresoc.v:187895.9-187895.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:51696.9-51696.17" case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14098 $1\data_r3__nia$next[63:0]$14097 } { \nia_ok \alu_trap0_nia } - case - assign $1\data_r3__nia$next[63:0]$14097 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14098 \data_r3__nia_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14100 $2\data_r3__nia$next[63:0]$14099 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14099 $1\data_r3__nia$next[63:0]$14097 - assign $2\data_r3__nia_ok$next[0:0]$14100 $1\data_r3__nia_ok$next[0:0]$14098 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" + switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14101 1'0 + assign $1\dbg_d_cr_data[63:0] \$127 case - assign $3\data_r3__nia_ok$next[0:0]$14101 $2\data_r3__nia_ok$next[0:0]$14100 + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14095 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14096 + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:187916.3-187937.6" - process $proc$libresoc.v:187916$14102 - assign { } { } - assign { } { } - assign { } { } + attribute \src "libresoc.v:51705.3-51714.6" + process $proc$libresoc.v:51705$1807 assign { } { } assign { } { } - assign { } { } - assign $0\data_r4__msr$next[63:0]$14103 $2\data_r4__msr$next[63:0]$14107 - assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14104 $3\data_r4__msr_ok$next[0:0]$14109 - attribute \src "libresoc.v:187917.5-187917.29" + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:51706.5-51706.29" switch \initial - attribute \src "libresoc.v:187917.9-187917.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch \alu_pulse - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14106 $1\data_r4__msr$next[63:0]$14105 } { \msr_ok \alu_trap0_msr } - case - assign $1\data_r4__msr$next[63:0]$14105 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14106 \data_r4__msr_ok - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch \cu_issue_i - attribute \src "libresoc.v:0.0-0.0" + attribute \src "libresoc.v:51706.9-51706.17" case 1'1 - assign { } { } - assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14108 $2\data_r4__msr$next[63:0]$14107 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14107 $1\data_r4__msr$next[63:0]$14105 - assign $2\data_r4__msr_ok$next[0:0]$14108 $1\data_r4__msr_ok$next[0:0]$14106 end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:345" + switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14109 1'0 + assign $1\dbg_d_cr_ack[0:0] 1'1 case - assign $3\data_r4__msr_ok$next[0:0]$14109 $2\data_r4__msr_ok$next[0:0]$14108 + assign $1\dbg_d_cr_ack[0:0] 1'0 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14103 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14104 + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:187938.3-187947.6" - process $proc$libresoc.v:187938$14110 + attribute \src "libresoc.v:51715.3-51724.6" + process $proc$libresoc.v:51715$1808 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14111 $1\src_r0$next[63:0]$14112 - attribute \src "libresoc.v:187939.5-187939.29" + assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0] + attribute \src "libresoc.v:51716.5-51716.29" switch \initial - attribute \src "libresoc.v:187939.9-187939.17" + attribute \src "libresoc.v:51716.9-51716.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:351" + switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14112 \src1_i + assign $1\full_rd__ren[2:0] 3'111 case - assign $1\src_r0$next[63:0]$14112 \src_r0 + assign $1\full_rd__ren[2:0] 3'000 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14111 + update \full_rd__ren $0\full_rd__ren[2:0] end - attribute \src "libresoc.v:187948.3-187957.6" - process $proc$libresoc.v:187948$14113 + attribute \src "libresoc.v:51725.3-51733.6" + process $proc$libresoc.v:51725$1809 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14114 $1\src_r1$next[63:0]$14115 - attribute \src "libresoc.v:187949.5-187949.29" + assign $0\d_xer_delay$next[0:0]$1810 $1\d_xer_delay$next[0:0]$1811 + attribute \src "libresoc.v:51726.5-51726.29" switch \initial - attribute \src "libresoc.v:187949.9-187949.17" + attribute \src "libresoc.v:51726.9-51726.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [1] + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14115 \src2_i + assign $1\d_xer_delay$next[0:0]$1811 1'0 case - assign $1\src_r1$next[63:0]$14115 \src_r1 + assign $1\d_xer_delay$next[0:0]$1811 \dbg_d_xer_req end sync always - update \src_r1$next $0\src_r1$next[63:0]$14114 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1810 end - attribute \src "libresoc.v:187958.3-187967.6" - process $proc$libresoc.v:187958$14116 + attribute \src "libresoc.v:51734.3-51743.6" + process $proc$libresoc.v:51734$1812 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14117 $1\src_r2$next[63:0]$14118 - attribute \src "libresoc.v:187959.5-187959.29" + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:51735.5-51735.29" switch \initial - attribute \src "libresoc.v:187959.9-187959.17" + attribute \src "libresoc.v:51735.9-51735.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14118 \src3_i + assign $1\dbg_d_xer_data[63:0] \$129 case - assign $1\src_r2$next[63:0]$14118 \src_r2 + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14117 + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:187968.3-187977.6" - process $proc$libresoc.v:187968$14119 + attribute \src "libresoc.v:51744.3-51753.6" + process $proc$libresoc.v:51744$1813 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14120 $1\src_r3$next[63:0]$14121 - attribute \src "libresoc.v:187969.5-187969.29" + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:51745.5-51745.29" switch \initial - attribute \src "libresoc.v:187969.9-187969.17" + attribute \src "libresoc.v:51745.9-51745.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch \src_l_q_src [3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" + switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14121 \src4_i + assign $1\dbg_d_xer_ack[0:0] 1'1 case - assign $1\src_r3$next[63:0]$14121 \src_r3 + assign $1\dbg_d_xer_ack[0:0] 1'0 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14120 + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:187978.3-187986.6" - process $proc$libresoc.v:187978$14122 + attribute \src "libresoc.v:51754.3-51768.6" + process $proc$libresoc.v:51754$1814 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14123 $1\alui_l_r_alui$next[0:0]$14124 - attribute \src "libresoc.v:187979.5-187979.29" + assign $0\issue__addr[2:0] $1\issue__addr[2:0] + attribute \src "libresoc.v:51755.5-51755.29" switch \initial - attribute \src "libresoc.v:187979.9-187979.17" + attribute \src "libresoc.v:51755.9-51755.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 + assign { } { } + assign $1\issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14124 1'1 + assign $1\issue__addr[2:0] 3'111 case - assign $1\alui_l_r_alui$next[0:0]$14124 \$89 + assign $1\issue__addr[2:0] 3'000 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14123 + update \issue__addr $0\issue__addr[2:0] end - attribute \src "libresoc.v:187987.3-187995.6" - process $proc$libresoc.v:187987$14125 + attribute \src "libresoc.v:51769.3-51783.6" + process $proc$libresoc.v:51769$1815 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14126 $1\alu_l_r_alu$next[0:0]$14127 - attribute \src "libresoc.v:187988.5-187988.29" + assign $0\issue__ren[0:0] $1\issue__ren[0:0] + attribute \src "libresoc.v:51770.5-51770.29" switch \initial - attribute \src "libresoc.v:187988.9-187988.17" + attribute \src "libresoc.v:51770.9-51770.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'00 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14127 1'1 + assign $1\issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\issue__ren[0:0] 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14127 \$91 + assign $1\issue__ren[0:0] 1'0 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14126 + update \issue__ren $0\issue__ren[0:0] end - attribute \src "libresoc.v:187996.3-188005.6" - process $proc$libresoc.v:187996$14128 + attribute \src "libresoc.v:51784.3-51811.6" + process $proc$libresoc.v:51784$1816 + assign { } { } assign { } { } assign { } { } - assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:187997.5-187997.29" + assign $0\fsm_state$131$next[1:0]$1817 $2\fsm_state$131$next[1:0]$1819 + attribute \src "libresoc.v:51785.5-51785.29" switch \initial - attribute \src "libresoc.v:187997.9-187997.17" + attribute \src "libresoc.v:51785.9-51785.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1818 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1818 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1818 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$131$next[1:0]$1818 2'00 + case + assign $1\fsm_state$131$next[1:0]$1818 \fsm_state$131 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dest1_o[63:0] \data_r0__o + assign $2\fsm_state$131$next[1:0]$1819 2'00 case - assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fsm_state$131$next[1:0]$1819 $1\fsm_state$131$next[1:0]$1818 end sync always - update \dest1_o $0\dest1_o[63:0] + update \fsm_state$131$next $0\fsm_state$131$next[1:0]$1817 end - attribute \src "libresoc.v:188006.3-188015.6" - process $proc$libresoc.v:188006$14129 + attribute \src "libresoc.v:51812.3-51822.6" + process $proc$libresoc.v:51812$1820 assign { } { } assign { } { } - assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:188007.5-188007.29" + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:51813.5-51813.29" switch \initial - attribute \src "libresoc.v:188007.9-188007.17" + attribute \src "libresoc.v:51813.9-51813.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 assign { } { } - assign $1\dest2_o[63:0] \data_r1__fast1 + assign $1\new_dec[63:0] \$132 [63:0] case - assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dest2_o $0\dest2_o[63:0] + update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:188016.3-188025.6" - process $proc$libresoc.v:188016$14130 + attribute \src "libresoc.v:51823.3-51837.6" + process $proc$libresoc.v:51823$1821 assign { } { } assign { } { } - assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:188017.5-188017.29" + assign $0\issue__addr$135[2:0]$1822 $1\issue__addr$135[2:0]$1823 + attribute \src "libresoc.v:51824.5-51824.29" switch \initial - attribute \src "libresoc.v:188017.9-188017.17" + attribute \src "libresoc.v:51824.9-51824.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 assign { } { } - assign $1\dest3_o[63:0] \data_r2__fast2 + assign $1\issue__addr$135[2:0]$1823 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\issue__addr$135[2:0]$1823 3'111 case - assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\issue__addr$135[2:0]$1823 3'000 end sync always - update \dest3_o $0\dest3_o[63:0] + update \issue__addr$135 $0\issue__addr$135[2:0]$1822 end - attribute \src "libresoc.v:188026.3-188035.6" - process $proc$libresoc.v:188026$14131 + attribute \src "libresoc.v:51838.3-51852.6" + process $proc$libresoc.v:51838$1824 assign { } { } assign { } { } - assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:188027.5-188027.29" + assign $0\issue__wen[0:0] $1\issue__wen[0:0] + attribute \src "libresoc.v:51839.5-51839.29" switch \initial - attribute \src "libresoc.v:188027.9-188027.17" + attribute \src "libresoc.v:51839.9-51839.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 + assign { } { } + assign $1\issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 assign { } { } - assign $1\dest4_o[63:0] \data_r3__nia + assign $1\issue__wen[0:0] 1'1 case - assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\issue__wen[0:0] 1'0 end sync always - update \dest4_o $0\dest4_o[63:0] + update \issue__wen $0\issue__wen[0:0] end - attribute \src "libresoc.v:188036.3-188045.6" - process $proc$libresoc.v:188036$14132 + attribute \src "libresoc.v:51853.3-51867.6" + process $proc$libresoc.v:51853$1825 assign { } { } assign { } { } - assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:188037.5-188037.29" + assign $0\issue__data_i[63:0] $1\issue__data_i[63:0] + attribute \src "libresoc.v:51854.5-51854.29" switch \initial - attribute \src "libresoc.v:188037.9-188037.17" + attribute \src "libresoc.v:51854.9-51854.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch \$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'01 + assign { } { } + assign $1\issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 assign { } { } - assign $1\dest5_o[63:0] \data_r4__msr + assign $1\issue__data_i[63:0] \new_tb case - assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \dest5_o $0\dest5_o[63:0] + update \issue__data_i $0\issue__data_i[63:0] end - attribute \src "libresoc.v:188046.3-188054.6" - process $proc$libresoc.v:188046$14133 + attribute \src "libresoc.v:51868.3-51883.6" + process $proc$libresoc.v:51868$1826 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14134 $1\prev_wr_go$next[4:0]$14135 - attribute \src "libresoc.v:188047.5-188047.29" + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$1827 $2\dec2_cur_dec$next[63:0]$1829 + attribute \src "libresoc.v:51869.5-51869.29" switch \initial - attribute \src "libresoc.v:188047.9-188047.17" + attribute \src "libresoc.v:51869.9-51869.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$1828 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$1828 \dec2_cur_dec + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14135 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14135 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14134 - end - connect \$5 $reduce_and$libresoc.v:187494$13921_Y - connect \$99 $and$libresoc.v:187495$13922_Y - connect \$101 $and$libresoc.v:187496$13923_Y - connect \$103 $and$libresoc.v:187497$13924_Y - connect \$105 $and$libresoc.v:187498$13925_Y - connect \$107 $and$libresoc.v:187499$13926_Y - connect \$109 $and$libresoc.v:187500$13927_Y - connect \$111 $and$libresoc.v:187501$13928_Y - connect \$113 $and$libresoc.v:187502$13929_Y - connect \$115 $and$libresoc.v:187503$13930_Y - connect \$117 $and$libresoc.v:187504$13931_Y - connect \$11 $and$libresoc.v:187505$13932_Y - connect \$119 $and$libresoc.v:187506$13933_Y - connect \$121 $and$libresoc.v:187507$13934_Y - connect \$123 $and$libresoc.v:187508$13935_Y - connect \$13 $not$libresoc.v:187509$13936_Y - connect \$15 $and$libresoc.v:187510$13937_Y - connect \$17 $not$libresoc.v:187511$13938_Y - connect \$19 $and$libresoc.v:187512$13939_Y - connect \$21 $and$libresoc.v:187513$13940_Y - connect \$25 $not$libresoc.v:187514$13941_Y - connect \$27 $and$libresoc.v:187515$13942_Y - connect \$24 $reduce_or$libresoc.v:187516$13943_Y - connect \$23 $not$libresoc.v:187517$13944_Y - connect \$31 $and$libresoc.v:187518$13945_Y - connect \$33 $reduce_or$libresoc.v:187519$13946_Y - connect \$35 $reduce_or$libresoc.v:187520$13947_Y - connect \$37 $or$libresoc.v:187521$13948_Y - connect \$3 $and$libresoc.v:187522$13949_Y - connect \$39 $not$libresoc.v:187523$13950_Y - connect \$41 $and$libresoc.v:187524$13951_Y - connect \$43 $and$libresoc.v:187525$13952_Y - connect \$45 $eq$libresoc.v:187526$13953_Y - connect \$47 $and$libresoc.v:187527$13954_Y - connect \$49 $eq$libresoc.v:187528$13955_Y - connect \$51 $and$libresoc.v:187529$13956_Y - connect \$53 $and$libresoc.v:187530$13957_Y - connect \$55 $and$libresoc.v:187531$13958_Y - connect \$57 $or$libresoc.v:187532$13959_Y - connect \$59 $or$libresoc.v:187533$13960_Y - connect \$61 $or$libresoc.v:187534$13961_Y - connect \$63 $or$libresoc.v:187535$13962_Y - connect \$65 $and$libresoc.v:187536$13963_Y - connect \$67 $and$libresoc.v:187537$13964_Y - connect \$6 $not$libresoc.v:187538$13965_Y - connect \$69 $or$libresoc.v:187539$13966_Y - connect \$71 $and$libresoc.v:187540$13967_Y - connect \$73 $and$libresoc.v:187541$13968_Y - connect \$75 $and$libresoc.v:187542$13969_Y - connect \$77 $and$libresoc.v:187543$13970_Y - connect \$79 $and$libresoc.v:187544$13971_Y - connect \$81 $ternary$libresoc.v:187545$13972_Y - connect \$83 $ternary$libresoc.v:187546$13973_Y - connect \$85 $ternary$libresoc.v:187547$13974_Y - connect \$87 $ternary$libresoc.v:187548$13975_Y - connect \$8 $or$libresoc.v:187549$13976_Y - connect \$89 $and$libresoc.v:187550$13977_Y - connect \$91 $and$libresoc.v:187551$13978_Y - connect \$93 $and$libresoc.v:187552$13979_Y - connect \$95 $and$libresoc.v:187553$13980_Y - connect \$97 $not$libresoc.v:187554$13981_Y - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 - connect \cu_wr__rel_o \$113 - connect \cu_rd__rel_o \$99 - connect \cu_busy_o \opc_l_q_opc - connect \alu_l_s_alu \all_rd_pulse - connect \alu_trap0_n_ready_i \alu_l_q_alu - connect \alui_l_s_alui \all_rd_pulse - connect \alu_trap0_p_valid_i \alui_l_q_alui - connect \alu_trap0_fast2$2 \$87 - connect \alu_trap0_fast1$1 \$85 - connect \alu_trap0_rb \$83 - connect \alu_trap0_ra \$81 - connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } - connect \reset_r \$63 - connect \reset_w \$61 - connect \rst_r \$59 - connect \reset \$57 - connect \wr_any \$37 - connect \cu_done_o \$31 - connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - connect \alu_pulse \alu_done_rise - connect \alu_done_rise \$19 - connect \alu_done_dly$next \alu_done - connect \alu_done \alu_trap0_n_valid_o - connect \all_rd_pulse \all_rd_rise - connect \all_rd_rise \$15 - connect \all_rd_dly$next \all_rd - connect \all_rd \$11 -end -attribute \src "libresoc.v:188088.1-188146.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" -attribute \generator "nMigen" -module \upd_l - attribute \src "libresoc.v:188089.7-188089.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:188134.3-188142.6" - wire $0\q_int$next[0:0]$14185 - attribute \src "libresoc.v:188132.3-188133.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:188134.3-188142.6" - wire $1\q_int$next[0:0]$14186 - attribute \src "libresoc.v:188111.7-188111.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:188124.17-188124.96" - wire $and$libresoc.v:188124$14175_Y - attribute \src "libresoc.v:188129.17-188129.96" - wire $and$libresoc.v:188129$14180_Y - attribute \src "libresoc.v:188126.18-188126.93" - wire $not$libresoc.v:188126$14177_Y - attribute \src "libresoc.v:188128.17-188128.92" - wire $not$libresoc.v:188128$14179_Y - attribute \src "libresoc.v:188131.17-188131.92" - wire $not$libresoc.v:188131$14182_Y - attribute \src "libresoc.v:188125.18-188125.98" - wire $or$libresoc.v:188125$14176_Y - attribute \src "libresoc.v:188127.18-188127.99" - wire $or$libresoc.v:188127$14178_Y - attribute \src "libresoc.v:188130.17-188130.97" - wire $or$libresoc.v:188130$14181_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:188089.7-188089.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:188124$14175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:188124$14175_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:188129$14180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:188129$14180_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:188126$14177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \Y $not$libresoc.v:188126$14177_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:188128$14179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $not$libresoc.v:188128$14179_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:188131$14182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $not$libresoc.v:188131$14182_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:188125$14176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_upd - connect \Y $or$libresoc.v:188125$14176_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:188127$14178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \B \q_int - connect \Y $or$libresoc.v:188127$14178_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:188130$14181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_upd - connect \Y $or$libresoc.v:188130$14181_Y - end - attribute \src "libresoc.v:188089.7-188089.20" - process $proc$libresoc.v:188089$14187 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:188111.7-188111.19" - process $proc$libresoc.v:188111$14188 - assign { } { } - assign $1\q_int[0:0] 1'0 + assign $2\dec2_cur_dec$next[63:0]$1829 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$1829 $1\dec2_cur_dec$next[63:0]$1828 + end sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:188132.3-188133.27" - process $proc$libresoc.v:188132$14183 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1827 end - attribute \src "libresoc.v:188134.3-188142.6" - process $proc$libresoc.v:188134$14184 + attribute \src "libresoc.v:51884.3-51894.6" + process $proc$libresoc.v:51884$1830 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14185 $1\q_int$next[0:0]$14186 - attribute \src "libresoc.v:188135.5-188135.29" + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:51885.5-51885.29" switch \initial - attribute \src "libresoc.v:188135.9-188135.17" + attribute \src "libresoc.v:51885.9-51885.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:381" + switch \fsm_state$131 attribute \src "libresoc.v:0.0-0.0" - case 1'1 + case 2'11 assign { } { } - assign $1\q_int$next[0:0]$14186 1'0 + assign $1\new_tb[63:0] \$136 [63:0] case - assign $1\q_int$next[0:0]$14186 \$5 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \q_int$next $0\q_int$next[0:0]$14185 - end - connect \$9 $and$libresoc.v:188124$14175_Y - connect \$11 $or$libresoc.v:188125$14176_Y - connect \$13 $not$libresoc.v:188126$14177_Y - connect \$15 $or$libresoc.v:188127$14178_Y - connect \$1 $not$libresoc.v:188128$14179_Y - connect \$3 $and$libresoc.v:188129$14180_Y - connect \$5 $or$libresoc.v:188130$14181_Y - connect \$7 $not$libresoc.v:188131$14182_Y - connect \qlq_upd \$15 - connect \qn_upd \$13 - connect \q_upd \$11 -end -attribute \src "libresoc.v:188150.1-188208.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" -attribute \generator "nMigen" -module \valid_l - attribute \src "libresoc.v:188151.7-188151.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:188196.3-188204.6" - wire $0\q_int$next[0:0]$14199 - attribute \src "libresoc.v:188194.3-188195.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:188196.3-188204.6" - wire $1\q_int$next[0:0]$14200 - attribute \src "libresoc.v:188173.7-188173.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:188186.17-188186.96" - wire $and$libresoc.v:188186$14189_Y - attribute \src "libresoc.v:188191.17-188191.96" - wire $and$libresoc.v:188191$14194_Y - attribute \src "libresoc.v:188188.18-188188.95" - wire $not$libresoc.v:188188$14191_Y - attribute \src "libresoc.v:188190.17-188190.94" - wire $not$libresoc.v:188190$14193_Y - attribute \src "libresoc.v:188193.17-188193.94" - wire $not$libresoc.v:188193$14196_Y - attribute \src "libresoc.v:188187.18-188187.100" - wire $or$libresoc.v:188187$14190_Y - attribute \src "libresoc.v:188189.18-188189.101" - wire $or$libresoc.v:188189$14192_Y - attribute \src "libresoc.v:188192.17-188192.99" - wire $or$libresoc.v:188192$14195_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:188151.7-188151.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 3 \q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 4 \r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:188186$14189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:188186$14189_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:188191$14194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:188191$14194_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:188188$14191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \Y $not$libresoc.v:188188$14191_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:188190$14193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $not$libresoc.v:188190$14193_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:188193$14196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $not$libresoc.v:188193$14196_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:188187$14190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_valid - connect \Y $or$libresoc.v:188187$14190_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:188189$14192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \B \q_int - connect \Y $or$libresoc.v:188189$14192_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:188192$14195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_valid - connect \Y $or$libresoc.v:188192$14195_Y - end - attribute \src "libresoc.v:188151.7-188151.20" - process $proc$libresoc.v:188151$14201 - assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:188173.7-188173.19" - process $proc$libresoc.v:188173$14202 - assign { } { } - assign $1\q_int[0:0] 1'0 - sync always - sync init - update \q_int $1\q_int[0:0] - end - attribute \src "libresoc.v:188194.3-188195.27" - process $proc$libresoc.v:188194$14197 - assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] + update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:188196.3-188204.6" - process $proc$libresoc.v:188196$14198 + attribute \src "libresoc.v:51895.3-51903.6" + process $proc$libresoc.v:51895$1831 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14199 $1\q_int$next[0:0]$14200 - attribute \src "libresoc.v:188197.5-188197.29" + assign $0\dbg_dmi_we_i$next[0:0]$1832 $1\dbg_dmi_we_i$next[0:0]$1833 + attribute \src "libresoc.v:51896.5-51896.29" switch \initial - attribute \src "libresoc.v:188197.9-188197.17" + attribute \src "libresoc.v:51896.9-51896.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14200 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$1833 1'0 case - assign $1\q_int$next[0:0]$14200 \$5 + assign $1\dbg_dmi_we_i$next[0:0]$1833 \jtag_dmi0__we_i end sync always - update \q_int$next $0\q_int$next[0:0]$14199 - end - connect \$9 $and$libresoc.v:188186$14189_Y - connect \$11 $or$libresoc.v:188187$14190_Y - connect \$13 $not$libresoc.v:188188$14191_Y - connect \$15 $or$libresoc.v:188189$14192_Y - connect \$1 $not$libresoc.v:188190$14193_Y - connect \$3 $and$libresoc.v:188191$14194_Y - connect \$5 $or$libresoc.v:188192$14195_Y - connect \$7 $not$libresoc.v:188193$14196_Y - connect \qlq_valid \$15 - connect \qn_valid \$13 - connect \q_valid \$11 -end -attribute \src "libresoc.v:188212.1-188270.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" -attribute \generator "nMigen" -module \wri_l - attribute \src "libresoc.v:188213.7-188213.20" - wire $0\initial[0:0] - attribute \src "libresoc.v:188258.3-188266.6" - wire $0\q_int$next[0:0]$14213 - attribute \src "libresoc.v:188256.3-188257.27" - wire $0\q_int[0:0] - attribute \src "libresoc.v:188258.3-188266.6" - wire $1\q_int$next[0:0]$14214 - attribute \src "libresoc.v:188235.7-188235.19" - wire $1\q_int[0:0] - attribute \src "libresoc.v:188248.17-188248.96" - wire $and$libresoc.v:188248$14203_Y - attribute \src "libresoc.v:188253.17-188253.96" - wire $and$libresoc.v:188253$14208_Y - attribute \src "libresoc.v:188250.18-188250.93" - wire $not$libresoc.v:188250$14205_Y - attribute \src "libresoc.v:188252.17-188252.92" - wire $not$libresoc.v:188252$14207_Y - attribute \src "libresoc.v:188255.17-188255.92" - wire $not$libresoc.v:188255$14210_Y - attribute \src "libresoc.v:188249.18-188249.98" - wire $or$libresoc.v:188249$14204_Y - attribute \src "libresoc.v:188251.18-188251.99" - wire $or$libresoc.v:188251$14206_Y - attribute \src "libresoc.v:188254.17-188254.97" - wire $or$libresoc.v:188254$14209_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire \$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire \$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" - wire input 1 \coresync_rst - attribute \src "libresoc.v:188213.7-188213.15" - wire \initial - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire output 4 \q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire \qlq_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire \qn_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire input 3 \r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire input 2 \s_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $and$libresoc.v:188248$14203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$7 - connect \Y $and$libresoc.v:188248$14203_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $and$libresoc.v:188253$14208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B \$1 - connect \Y $and$libresoc.v:188253$14208_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $not$libresoc.v:188250$14205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \Y $not$libresoc.v:188250$14205_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $not$libresoc.v:188252$14207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $not$libresoc.v:188252$14207_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $not$libresoc.v:188255$14210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $not$libresoc.v:188255$14210_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $or$libresoc.v:188249$14204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$9 - connect \B \s_wri - connect \Y $or$libresoc.v:188249$14204_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $or$libresoc.v:188251$14206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \B \q_int - connect \Y $or$libresoc.v:188251$14206_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $or$libresoc.v:188254$14209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$3 - connect \B \s_wri - connect \Y $or$libresoc.v:188254$14209_Y + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1832 end - attribute \src "libresoc.v:188213.7-188213.20" - process $proc$libresoc.v:188213$14215 + attribute \src "libresoc.v:51904.3-51912.6" + process $proc$libresoc.v:51904$1834 assign { } { } - assign $0\initial[0:0] 1'0 - sync always - update \initial $0\initial[0:0] - sync init - end - attribute \src "libresoc.v:188235.7-188235.19" - process $proc$libresoc.v:188235$14216 assign { } { } - assign $1\q_int[0:0] 1'0 + assign $0\pc_ok_delay$next[0:0]$1835 $1\pc_ok_delay$next[0:0]$1836 + attribute \src "libresoc.v:51905.5-51905.29" + switch \initial + attribute \src "libresoc.v:51905.9-51905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$1836 1'0 + case + assign $1\pc_ok_delay$next[0:0]$1836 \$28 + end sync always - sync init - update \q_int $1\q_int[0:0] + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1835 end - attribute \src "libresoc.v:188256.3-188257.27" - process $proc$libresoc.v:188256$14211 + attribute \src "libresoc.v:51913.3-51928.6" + process $proc$libresoc.v:51913$1837 assign { } { } - assign $0\q_int[0:0] \q_int$next - sync posedge \coresync_clk - update \q_int $0\q_int[0:0] - end - attribute \src "libresoc.v:188258.3-188266.6" - process $proc$libresoc.v:188258$14212 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14213 $1\q_int$next[0:0]$14214 - attribute \src "libresoc.v:188259.5-188259.29" + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:51914.5-51914.29" switch \initial - attribute \src "libresoc.v:188259.9-188259.17" + attribute \src "libresoc.v:51914.9-51914.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \pc_ok_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14214 1'0 + assign $2\pc[63:0] \cia__data_o case - assign $1\q_int$next[0:0]$14214 \$5 + assign $2\pc[63:0] $1\pc[63:0] end sync always - update \q_int$next $0\q_int$next[0:0]$14213 - end - connect \$9 $and$libresoc.v:188248$14203_Y - connect \$11 $or$libresoc.v:188249$14204_Y - connect \$13 $not$libresoc.v:188250$14205_Y - connect \$15 $or$libresoc.v:188251$14206_Y - connect \$1 $not$libresoc.v:188252$14207_Y - connect \$3 $and$libresoc.v:188253$14208_Y - connect \$5 $or$libresoc.v:188254$14209_Y - connect \$7 $not$libresoc.v:188255$14210_Y - connect \qlq_wri \$15 - connect \qn_wri \$13 - connect \q_wri \$11 -end -attribute \src "libresoc.v:188274.1-188340.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" -attribute \generator "nMigen" -module \wrpick_CR_cr_a - attribute \src "libresoc.v:188319.17-188319.91" - wire $not$libresoc.v:188319$14217_Y - attribute \src "libresoc.v:188321.18-188321.93" - wire $not$libresoc.v:188321$14219_Y - attribute \src "libresoc.v:188323.18-188323.93" - wire $not$libresoc.v:188323$14221_Y - attribute \src "libresoc.v:188324.17-188324.89" - wire width 6 $not$libresoc.v:188324$14222_Y - attribute \src "libresoc.v:188326.18-188326.93" - wire $not$libresoc.v:188326$14224_Y - attribute \src "libresoc.v:188329.17-188329.91" - wire $not$libresoc.v:188329$14227_Y - attribute \src "libresoc.v:188320.18-188320.106" - wire $reduce_or$libresoc.v:188320$14218_Y - attribute \src "libresoc.v:188322.18-188322.106" - wire $reduce_or$libresoc.v:188322$14220_Y - attribute \src "libresoc.v:188325.18-188325.106" - wire $reduce_or$libresoc.v:188325$14223_Y - attribute \src "libresoc.v:188327.18-188327.90" - wire $reduce_or$libresoc.v:188327$14225_Y - attribute \src "libresoc.v:188328.17-188328.103" - wire $reduce_or$libresoc.v:188328$14226_Y - attribute \src "libresoc.v:188330.17-188330.105" - wire $reduce_or$libresoc.v:188330$14228_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 6 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188319$14217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:188319$14217_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188321$14219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:188321$14219_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188323$14221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:188323$14221_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188324$14222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \i - connect \Y $not$libresoc.v:188324$14222_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188326$14224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:188326$14224_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188329$14227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:188329$14227_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188320$14218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188320$14218_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188322$14220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:188322$14220_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188325$14223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:188325$14223_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188327$14225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188327$14225_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188328$14226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188328$14226_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188330$14228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188330$14228_Y - end - connect \$7 $not$libresoc.v:188319$14217_Y - connect \$12 $reduce_or$libresoc.v:188320$14218_Y - connect \$11 $not$libresoc.v:188321$14219_Y - connect \$16 $reduce_or$libresoc.v:188322$14220_Y - connect \$15 $not$libresoc.v:188323$14221_Y - connect \$1 $not$libresoc.v:188324$14222_Y - connect \$20 $reduce_or$libresoc.v:188325$14223_Y - connect \$19 $not$libresoc.v:188326$14224_Y - connect \$23 $reduce_or$libresoc.v:188327$14225_Y - connect \$4 $reduce_or$libresoc.v:188328$14226_Y - connect \$3 $not$libresoc.v:188329$14227_Y - connect \$8 $reduce_or$libresoc.v:188330$14228_Y - connect \en_o \$23 - connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:188344.1-188365.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" -attribute \generator "nMigen" -module \wrpick_CR_full_cr - attribute \src "libresoc.v:188359.17-188359.89" - wire $not$libresoc.v:188359$14229_Y - attribute \src "libresoc.v:188360.17-188360.89" - wire $reduce_or$libresoc.v:188360$14230_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188359$14229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:188359$14229_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188360$14230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188360$14230_Y - end - connect \$1 $not$libresoc.v:188359$14229_Y - connect \$3 $reduce_or$libresoc.v:188360$14230_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:188369.1-188426.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" -attribute \generator "nMigen" -module \wrpick_FAST_fast1 - attribute \src "libresoc.v:188408.17-188408.91" - wire $not$libresoc.v:188408$14231_Y - attribute \src "libresoc.v:188410.18-188410.93" - wire $not$libresoc.v:188410$14233_Y - attribute \src "libresoc.v:188412.18-188412.93" - wire $not$libresoc.v:188412$14235_Y - attribute \src "libresoc.v:188413.17-188413.89" - wire width 5 $not$libresoc.v:188413$14236_Y - attribute \src "libresoc.v:188416.17-188416.91" - wire $not$libresoc.v:188416$14239_Y - attribute \src "libresoc.v:188409.18-188409.106" - wire $reduce_or$libresoc.v:188409$14232_Y - attribute \src "libresoc.v:188411.18-188411.106" - wire $reduce_or$libresoc.v:188411$14234_Y - attribute \src "libresoc.v:188414.18-188414.90" - wire $reduce_or$libresoc.v:188414$14237_Y - attribute \src "libresoc.v:188415.17-188415.103" - wire $reduce_or$libresoc.v:188415$14238_Y - attribute \src "libresoc.v:188417.17-188417.105" - wire $reduce_or$libresoc.v:188417$14240_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 5 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 5 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 5 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 5 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188408$14231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:188408$14231_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188410$14233 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:188410$14233_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188412$14235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:188412$14235_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188413$14236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \i - connect \Y $not$libresoc.v:188413$14236_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188416$14239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:188416$14239_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188409$14232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188409$14232_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188411$14234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:188411$14234_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188414$14237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188414$14237_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188415$14238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188415$14238_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - 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"test_issuer.ti.core.wrpick_INT_o" -attribute \generator "nMigen" -module \wrpick_INT_o - attribute \src "libresoc.v:188499.17-188499.91" - wire $not$libresoc.v:188499$14241_Y - attribute \src "libresoc.v:188501.18-188501.93" - wire $not$libresoc.v:188501$14243_Y - attribute \src "libresoc.v:188503.18-188503.93" - wire $not$libresoc.v:188503$14245_Y - attribute \src "libresoc.v:188504.17-188504.89" - wire width 10 $not$libresoc.v:188504$14246_Y - attribute \src "libresoc.v:188506.18-188506.93" - wire $not$libresoc.v:188506$14248_Y - attribute \src "libresoc.v:188508.18-188508.93" - wire $not$libresoc.v:188508$14250_Y - attribute \src "libresoc.v:188510.18-188510.93" - wire $not$libresoc.v:188510$14252_Y - attribute \src "libresoc.v:188512.18-188512.93" - wire $not$libresoc.v:188512$14254_Y - attribute \src "libresoc.v:188514.18-188514.93" - wire $not$libresoc.v:188514$14256_Y - attribute \src "libresoc.v:188517.17-188517.91" - wire $not$libresoc.v:188517$14259_Y - attribute \src "libresoc.v:188500.18-188500.106" - wire $reduce_or$libresoc.v:188500$14242_Y - attribute \src "libresoc.v:188502.18-188502.106" - wire $reduce_or$libresoc.v:188502$14244_Y - attribute \src "libresoc.v:188505.18-188505.106" - wire $reduce_or$libresoc.v:188505$14247_Y - attribute \src "libresoc.v:188507.18-188507.106" - wire $reduce_or$libresoc.v:188507$14249_Y - attribute \src "libresoc.v:188509.18-188509.106" - wire $reduce_or$libresoc.v:188509$14251_Y - attribute \src "libresoc.v:188511.18-188511.106" - wire $reduce_or$libresoc.v:188511$14253_Y - attribute \src "libresoc.v:188513.18-188513.106" - wire $reduce_or$libresoc.v:188513$14255_Y - attribute \src "libresoc.v:188515.18-188515.90" - wire $reduce_or$libresoc.v:188515$14257_Y - attribute \src "libresoc.v:188516.17-188516.103" - wire $reduce_or$libresoc.v:188516$14258_Y - attribute \src "libresoc.v:188518.17-188518.105" - wire $reduce_or$libresoc.v:188518$14260_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 10 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 10 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 10 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 10 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188499$14241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:188499$14241_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188501$14243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:188501$14243_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188503$14245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$16 - connect \Y $not$libresoc.v:188503$14245_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188504$14246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 10 - connect \A \i - connect \Y $not$libresoc.v:188504$14246_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188506$14248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$20 - connect \Y $not$libresoc.v:188506$14248_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188508$14250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$24 - connect \Y $not$libresoc.v:188508$14250_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188510$14252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$28 - connect \Y $not$libresoc.v:188510$14252_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188512$14254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$32 - connect \Y $not$libresoc.v:188512$14254_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188514$14256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$36 - connect \Y $not$libresoc.v:188514$14256_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188517$14259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:188517$14259_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188500$14242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188500$14242_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188502$14244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:188502$14244_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188505$14247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:188505$14247_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188507$14249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:188507$14249_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188509$14251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:188509$14251_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188511$14253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:188511$14253_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188513$14255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:188513$14255_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188515$14257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188515$14257_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188516$14258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188516$14258_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188518$14260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188518$14260_Y - end - connect \$7 $not$libresoc.v:188499$14241_Y - connect \$12 $reduce_or$libresoc.v:188500$14242_Y - connect \$11 $not$libresoc.v:188501$14243_Y - connect \$16 $reduce_or$libresoc.v:188502$14244_Y - connect \$15 $not$libresoc.v:188503$14245_Y - connect \$1 $not$libresoc.v:188504$14246_Y - connect \$20 $reduce_or$libresoc.v:188505$14247_Y - connect \$19 $not$libresoc.v:188506$14248_Y - connect \$24 $reduce_or$libresoc.v:188507$14249_Y - connect \$23 $not$libresoc.v:188508$14250_Y - connect \$28 $reduce_or$libresoc.v:188509$14251_Y - connect \$27 $not$libresoc.v:188510$14252_Y - connect \$32 $reduce_or$libresoc.v:188511$14253_Y - connect \$31 $not$libresoc.v:188512$14254_Y - connect \$36 $reduce_or$libresoc.v:188513$14255_Y - connect \$35 $not$libresoc.v:188514$14256_Y - connect \$39 $reduce_or$libresoc.v:188515$14257_Y - connect \$4 $reduce_or$libresoc.v:188516$14258_Y - connect \$3 $not$libresoc.v:188517$14259_Y - connect \$8 $reduce_or$libresoc.v:188518$14260_Y - connect \en_o \$39 - connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - connect \t9 \$35 - connect \t8 \$31 - connect \t7 \$27 - connect \t6 \$23 - connect \t5 \$19 - connect \t4 \$15 - connect \t3 \$11 - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:188536.1-188557.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" -attribute \generator "nMigen" -module \wrpick_SPR_spr1 - attribute \src "libresoc.v:188551.17-188551.89" - wire $not$libresoc.v:188551$14261_Y - attribute \src "libresoc.v:188552.17-188552.89" - wire $reduce_or$libresoc.v:188552$14262_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188551$14261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:188551$14261_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188552$14262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188552$14262_Y - end - connect \$1 $not$libresoc.v:188551$14261_Y - connect \$3 $reduce_or$libresoc.v:188552$14262_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:188561.1-188582.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" -attribute \generator "nMigen" -module \wrpick_STATE_msr - attribute \src "libresoc.v:188576.17-188576.89" - wire $not$libresoc.v:188576$14263_Y - attribute \src "libresoc.v:188577.17-188577.89" - wire $reduce_or$libresoc.v:188577$14264_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188576$14263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \Y $not$libresoc.v:188576$14263_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188577$14264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188577$14264_Y - end - connect \$1 $not$libresoc.v:188576$14263_Y - connect \$3 $reduce_or$libresoc.v:188577$14264_Y - connect \en_o \$3 - connect \o \t0 - connect \t0 \i - connect \ni \$1 -end -attribute \src "libresoc.v:188586.1-188616.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" -attribute \generator "nMigen" -module \wrpick_STATE_nia - attribute \src "libresoc.v:188607.17-188607.89" - wire width 2 $not$libresoc.v:188607$14265_Y - attribute \src "libresoc.v:188609.17-188609.91" - wire $not$libresoc.v:188609$14267_Y - attribute \src "libresoc.v:188608.17-188608.103" - wire $reduce_or$libresoc.v:188608$14266_Y - attribute \src "libresoc.v:188610.17-188610.89" - wire $reduce_or$libresoc.v:188610$14268_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188607$14265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \i - connect \Y $not$libresoc.v:188607$14265_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188609$14267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:188609$14267_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188608$14266 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188608$14266_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188610$14268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188610$14268_Y - end - connect \$1 $not$libresoc.v:188607$14265_Y - connect \$4 $reduce_or$libresoc.v:188608$14266_Y - connect \$3 $not$libresoc.v:188609$14267_Y - connect \$7 $reduce_or$libresoc.v:188610$14268_Y - connect \en_o \$7 - connect \o { \t1 \t0 } - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:188620.1-188659.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" -attribute \generator "nMigen" -module \wrpick_XER_xer_ca - attribute \src "libresoc.v:188647.17-188647.91" - wire $not$libresoc.v:188647$14269_Y - attribute \src "libresoc.v:188649.17-188649.89" - wire width 3 $not$libresoc.v:188649$14271_Y - attribute \src "libresoc.v:188651.17-188651.91" - wire $not$libresoc.v:188651$14273_Y - attribute \src "libresoc.v:188648.18-188648.90" - wire $reduce_or$libresoc.v:188648$14270_Y - attribute \src "libresoc.v:188650.17-188650.103" - wire $reduce_or$libresoc.v:188650$14272_Y - attribute \src "libresoc.v:188652.17-188652.105" - wire $reduce_or$libresoc.v:188652$14274_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 3 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188647$14269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:188647$14269_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188649$14271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \i - connect \Y $not$libresoc.v:188649$14271_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188651$14273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:188651$14273_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188648$14270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188648$14270_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188650$14272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188650$14272_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188652$14274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188652$14274_Y - end - connect \$7 $not$libresoc.v:188647$14269_Y - connect \$11 $reduce_or$libresoc.v:188648$14270_Y - connect \$1 $not$libresoc.v:188649$14271_Y - connect \$4 $reduce_or$libresoc.v:188650$14272_Y - connect \$3 $not$libresoc.v:188651$14273_Y - connect \$8 $reduce_or$libresoc.v:188652$14274_Y - connect \en_o \$11 - connect \o { \t2 \t1 \t0 } - connect \t2 \$7 - connect \t1 \$3 - connect \t0 \i [0] - connect \ni \$1 -end -attribute \src "libresoc.v:188663.1-188711.10" -attribute \cells_not_processed 1 -attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" -attribute \generator "nMigen" -module \wrpick_XER_xer_ov - attribute \src "libresoc.v:188696.17-188696.91" - wire $not$libresoc.v:188696$14275_Y - attribute \src "libresoc.v:188698.18-188698.93" - wire $not$libresoc.v:188698$14277_Y - attribute \src "libresoc.v:188700.17-188700.89" - wire width 4 $not$libresoc.v:188700$14279_Y - attribute \src "libresoc.v:188702.17-188702.91" - wire $not$libresoc.v:188702$14281_Y - attribute \src "libresoc.v:188697.18-188697.106" - wire $reduce_or$libresoc.v:188697$14276_Y - attribute \src "libresoc.v:188699.18-188699.90" - wire $reduce_or$libresoc.v:188699$14278_Y - attribute \src "libresoc.v:188701.17-188701.103" - wire $reduce_or$libresoc.v:188701$14280_Y - attribute \src "libresoc.v:188703.17-188703.105" - wire $reduce_or$libresoc.v:188703$14282_Y - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 4 \$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire \$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire \$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 input 3 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188696$14275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$8 - connect \Y $not$libresoc.v:188696$14275_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188698$14277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$12 - connect \Y $not$libresoc.v:188698$14277_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $not$libresoc.v:188700$14279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \i - connect \Y $not$libresoc.v:188700$14279_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $not$libresoc.v:188702$14281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$4 - connect \Y $not$libresoc.v:188702$14281_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188697$14276 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:188697$14276_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_or $reduce_or$libresoc.v:188699$14278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $reduce_or$libresoc.v:188699$14278_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188701$14280 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:188701$14280_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_or $reduce_or$libresoc.v:188703$14282 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:188703$14282_Y - end - connect \$7 $not$libresoc.v:188696$14275_Y - connect \$12 $reduce_or$libresoc.v:188697$14276_Y - connect \$11 $not$libresoc.v:188698$14277_Y - connect \$15 $reduce_or$libresoc.v:188699$14278_Y - connect \$1 $not$libresoc.v:188700$14279_Y - connect \$4 $reduce_or$libresoc.v:188701$14280_Y - connect \$3 $not$libresoc.v:188702$14281_Y - connect \$8 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire \reg_2_w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$11$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 4 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 5 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 6 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 7 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 8 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 9 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 11 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 13 \wen$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 15 \wen$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:188934$14291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src10__data_o - connect \B \$7 - connect \Y $or$libresoc.v:188934$14291_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:188936$14293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src21__data_o - connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:188936$14293_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:188937$14294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src20__data_o - connect \B \$14 - connect \Y $or$libresoc.v:188937$14294_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:188939$14296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src31__data_o - connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:188939$14296_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $or$libresoc.v:188940$14297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src30__data_o - connect \B \$21 - connect \Y $or$libresoc.v:188940$14297_Y - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $or$libresoc.v:188942$14299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src11__data_o - connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:188942$14299_Y - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188935$14292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:188935$14292_Y + update \pc $0\pc[63:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188938$14295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:188938$14295_Y + attribute \src "libresoc.v:51929.3-51941.6" + process $proc$libresoc.v:51929$1838 + assign { } { } + assign { } { } + assign $0\cia__ren[3:0] $1\cia__ren[3:0] + attribute \src "libresoc.v:51930.5-51930.29" + switch \initial + attribute \src "libresoc.v:51930.9-51930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:207" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\cia__ren[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cia__ren[3:0] 4'0001 + end + sync always + update \cia__ren $0\cia__ren[3:0] end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:188941$14298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:188941$14298_Y + attribute \src "libresoc.v:51942.3-51962.6" + process $proc$libresoc.v:51942$1839 + assign { } { } + assign { } { } + assign $0\wen[3:0] $1\wen[3:0] + attribute \src "libresoc.v:51943.5-51943.29" + switch \initial + attribute \src "libresoc.v:51943.9-51943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\wen[3:0] $2\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$30 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wen[3:0] $3\wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \$32 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wen[3:0] 4'0001 + case + assign $3\wen[3:0] 4'0000 + end + case + assign $2\wen[3:0] 4'0000 + end + case + assign $1\wen[3:0] 4'0000 + end + sync always + update \wen $0\wen[3:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:188949.15-188968.4" - cell \reg_0$132 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest10__data_i \reg_0_dest10__data_i - connect \dest10__wen \reg_0_dest10__wen - connect \dest20__data_i \reg_0_dest20__data_i - connect \dest20__wen \reg_0_dest20__wen - connect \dest30__data_i \reg_0_dest30__data_i - connect \dest30__wen \reg_0_dest30__wen - connect \r0__data_o \reg_0_r0__data_o - connect \r0__ren \reg_0_r0__ren - connect \src10__data_o \reg_0_src10__data_o - connect \src10__ren \reg_0_src10__ren - connect \src20__data_o \reg_0_src20__data_o - connect \src20__ren \reg_0_src20__ren - connect \src30__data_o \reg_0_src30__data_o - connect \src30__ren \reg_0_src30__ren - connect \w0__data_i \reg_0_w0__data_i - connect \w0__wen \reg_0_w0__wen + attribute \src "libresoc.v:51963.3-51983.6" + process $proc$libresoc.v:51963$1840 + assign { } { } + assign { } { } + assign $0\data_i[63:0] $1\data_i[63:0] + attribute \src "libresoc.v:51964.5-51964.29" + switch \initial + attribute \src "libresoc.v:51964.9-51964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\data_i[63:0] $2\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\data_i[63:0] $3\data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315" + switch \$36 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_i[63:0] \nia + case + assign $3\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \data_i $0\data_i[63:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:188969.15-188988.4" - cell \reg_1$133 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest11__data_i \reg_1_dest11__data_i - connect \dest11__wen \reg_1_dest11__wen - connect \dest21__data_i \reg_1_dest21__data_i - connect \dest21__wen \reg_1_dest21__wen - connect \dest31__data_i \reg_1_dest31__data_i - connect \dest31__wen \reg_1_dest31__wen - connect \r1__data_o \reg_1_r1__data_o - connect \r1__ren \reg_1_r1__ren - connect \src11__data_o \reg_1_src11__data_o - connect \src11__ren \reg_1_src11__ren - connect \src21__data_o \reg_1_src21__data_o - connect \src21__ren \reg_1_src21__ren - connect \src31__data_o \reg_1_src31__data_o - connect \src31__ren \reg_1_src31__ren - connect \w1__data_i \reg_1_w1__data_i - connect \w1__wen \reg_1_w1__wen + attribute \src "libresoc.v:51984.3-51999.6" + process $proc$libresoc.v:51984$1841 + assign { } { } + assign { } { } + assign $0\msr__ren[3:0] $1\msr__ren[3:0] + attribute \src "libresoc.v:51985.5-51985.29" + switch \initial + attribute \src "libresoc.v:51985.9-51985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr__ren[3:0] $2\msr__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr__ren[3:0] 4'0010 + case + assign $2\msr__ren[3:0] 4'0000 + end + case + assign $1\msr__ren[3:0] 4'0000 + end + sync always + update \msr__ren $0\msr__ren[3:0] end - attribute \module_not_derived 1 - attribute \src "libresoc.v:188989.15-189008.4" - cell \reg_2$134 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \dest12__data_i \reg_2_dest12__data_i - connect \dest12__wen \reg_2_dest12__wen - connect \dest22__data_i \reg_2_dest22__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \dest32__data_i \reg_2_dest32__data_i - connect \dest32__wen \reg_2_dest32__wen - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src12__ren \reg_2_src12__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src22__ren \reg_2_src22__ren - connect \src32__data_o \reg_2_src32__data_o - connect \src32__ren \reg_2_src32__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen - end - attribute \src "libresoc.v:188768.7-188768.20" - process $proc$libresoc.v:188768$14317 + attribute \src "libresoc.v:52000.3-52008.6" + process $proc$libresoc.v:52000$1842 assign { } { } - assign $0\initial[0:0] 1'0 + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$1843 $1\dbg_dmi_din$next[63:0]$1844 + attribute \src "libresoc.v:52001.5-52001.29" + switch \initial + attribute \src "libresoc.v:52001.9-52001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$1844 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$1844 \jtag_dmi0__din + end sync always - update \initial $0\initial[0:0] - sync init + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1843 end - attribute \src "libresoc.v:188902.13-188902.29" - process $proc$libresoc.v:188902$14318 + attribute \src "libresoc.v:52009.3-52033.6" + process $proc$libresoc.v:52009$1845 + assign { } { } + assign { } { } assign { } { } - assign $1\ren_delay[2:0] 3'000 + assign $0\pc_changed$next[0:0]$1846 $3\pc_changed$next[0:0]$1849 + attribute \src "libresoc.v:52010.5-52010.29" + switch \initial + attribute \src "libresoc.v:52010.9-52010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\pc_changed$next[0:0]$1847 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$1847 $2\pc_changed$next[0:0]$1848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$1848 1'1 + case + assign $2\pc_changed$next[0:0]$1848 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$1847 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$1849 1'0 + case + assign $3\pc_changed$next[0:0]$1849 $1\pc_changed$next[0:0]$1847 + end sync always - sync init - update \ren_delay $1\ren_delay[2:0] + update \pc_changed$next $0\pc_changed$next[0:0]$1846 end - attribute \src "libresoc.v:188904.13-188904.34" - process $proc$libresoc.v:188904$14319 + attribute \src "libresoc.v:52034.3-52156.6" + process $proc$libresoc.v:52034$1850 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$1851 $1\core_asmcode$next[7:0]$1910 + assign $0\core_core_cia$next[63:0]$1852 $1\core_core_cia$next[63:0]$1911 + assign $0\core_core_cr_rd$next[7:0]$1853 $1\core_core_cr_rd$next[7:0]$1912 + assign { } { } + assign $0\core_core_cr_wr$next[7:0]$1855 $1\core_core_cr_wr$next[7:0]$1914 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_fn_unit$next[11:0]$1865 $1\core_core_fn_unit$next[11:0]$1924 + assign $0\core_core_input_carry$next[1:0]$1866 $1\core_core_input_carry$next[1:0]$1925 + assign $0\core_core_insn$next[31:0]$1867 $1\core_core_insn$next[31:0]$1926 + assign $0\core_core_insn_type$next[6:0]$1868 $1\core_core_insn_type$next[6:0]$1927 + assign $0\core_core_is_32bit$next[0:0]$1869 $1\core_core_is_32bit$next[0:0]$1928 + assign $0\core_core_lk$next[0:0]$1870 $1\core_core_lk$next[0:0]$1929 + assign $0\core_core_msr$next[63:0]$1871 $1\core_core_msr$next[63:0]$1930 + assign $0\core_core_oe$next[0:0]$1872 $1\core_core_oe$next[0:0]$1931 + assign { } { } + assign $0\core_core_rc$next[0:0]$1874 $1\core_core_rc$next[0:0]$1933 + assign { } { } + assign $0\core_core_trapaddr$next[12:0]$1876 $1\core_core_trapaddr$next[12:0]$1935 + assign $0\core_core_traptype$next[7:0]$1877 $1\core_core_traptype$next[7:0]$1936 + assign $0\core_cr_in1$next[2:0]$1878 $1\core_cr_in1$next[2:0]$1937 assign { } { } - assign $0\ren_delay$11[2:0]$14320 3'000 + assign $0\core_cr_in2$48$next[2:0]$1880 $1\core_cr_in2$48$next[2:0]$1939 + assign $0\core_cr_in2$next[2:0]$1881 $1\core_cr_in2$next[2:0]$1940 + assign { } { } + assign { } { } + assign $0\core_cr_out$next[2:0]$1884 $1\core_cr_out$next[2:0]$1943 + assign { } { } + assign $0\core_ea$next[4:0]$1886 $1\core_ea$next[4:0]$1945 + assign { } { } + assign $0\core_fast1$next[2:0]$1888 $1\core_fast1$next[2:0]$1947 + assign { } { } + assign $0\core_fast2$next[2:0]$1890 $1\core_fast2$next[2:0]$1949 + assign { } { } + assign $0\core_fasto1$next[2:0]$1892 $1\core_fasto1$next[2:0]$1951 + assign { } { } + assign $0\core_fasto2$next[2:0]$1894 $1\core_fasto2$next[2:0]$1953 + assign { } { } + assign $0\core_reg1$next[4:0]$1896 $1\core_reg1$next[4:0]$1955 + assign { } { } + assign $0\core_reg2$next[4:0]$1898 $1\core_reg2$next[4:0]$1957 + assign { } { } + assign $0\core_reg3$next[4:0]$1900 $1\core_reg3$next[4:0]$1959 + assign { } { } + assign $0\core_rego$next[4:0]$1902 $1\core_rego$next[4:0]$1961 + assign { } { } + assign $0\core_spr1$next[9:0]$1904 $1\core_spr1$next[9:0]$1963 + assign { } { } + assign $0\core_spro$next[9:0]$1906 $1\core_spro$next[9:0]$1965 + assign { } { } + assign $0\core_xer_in$next[2:0]$1908 $1\core_xer_in$next[2:0]$1967 + assign $0\core_xer_out$next[0:0]$1909 $1\core_xer_out$next[0:0]$1968 + assign $0\core_core_cr_rd_ok$next[0:0]$1854 $4\core_core_cr_rd_ok$next[0:0]$2087 + assign $0\core_core_cr_wr_ok$next[0:0]$1856 $4\core_core_cr_wr_ok$next[0:0]$2088 + assign $0\core_core_exc_$signal$50$next[0:0]$1857 $4\core_core_exc_$signal$50$next[0:0]$2089 + assign $0\core_core_exc_$signal$51$next[0:0]$1858 $4\core_core_exc_$signal$51$next[0:0]$2090 + assign $0\core_core_exc_$signal$52$next[0:0]$1859 $4\core_core_exc_$signal$52$next[0:0]$2091 + assign $0\core_core_exc_$signal$53$next[0:0]$1860 $4\core_core_exc_$signal$53$next[0:0]$2092 + assign $0\core_core_exc_$signal$54$next[0:0]$1861 $4\core_core_exc_$signal$54$next[0:0]$2093 + assign $0\core_core_exc_$signal$55$next[0:0]$1862 $4\core_core_exc_$signal$55$next[0:0]$2094 + assign $0\core_core_exc_$signal$56$next[0:0]$1863 $4\core_core_exc_$signal$56$next[0:0]$2095 + assign $0\core_core_exc_$signal$next[0:0]$1864 $4\core_core_exc_$signal$next[0:0]$2096 + assign $0\core_core_oe_ok$next[0:0]$1873 $4\core_core_oe_ok$next[0:0]$2097 + assign $0\core_core_rc_ok$next[0:0]$1875 $4\core_core_rc_ok$next[0:0]$2098 + assign $0\core_cr_in1_ok$next[0:0]$1879 $4\core_cr_in1_ok$next[0:0]$2099 + assign $0\core_cr_in2_ok$49$next[0:0]$1882 $4\core_cr_in2_ok$49$next[0:0]$2100 + assign $0\core_cr_in2_ok$next[0:0]$1883 $4\core_cr_in2_ok$next[0:0]$2101 + assign $0\core_cr_out_ok$next[0:0]$1885 $4\core_cr_out_ok$next[0:0]$2102 + assign $0\core_ea_ok$next[0:0]$1887 $4\core_ea_ok$next[0:0]$2103 + assign $0\core_fast1_ok$next[0:0]$1889 $4\core_fast1_ok$next[0:0]$2104 + assign $0\core_fast2_ok$next[0:0]$1891 $4\core_fast2_ok$next[0:0]$2105 + assign $0\core_fasto1_ok$next[0:0]$1893 $4\core_fasto1_ok$next[0:0]$2106 + assign $0\core_fasto2_ok$next[0:0]$1895 $4\core_fasto2_ok$next[0:0]$2107 + assign $0\core_reg1_ok$next[0:0]$1897 $4\core_reg1_ok$next[0:0]$2108 + assign $0\core_reg2_ok$next[0:0]$1899 $4\core_reg2_ok$next[0:0]$2109 + assign $0\core_reg3_ok$next[0:0]$1901 $4\core_reg3_ok$next[0:0]$2110 + assign $0\core_rego_ok$next[0:0]$1903 $4\core_rego_ok$next[0:0]$2111 + assign $0\core_spr1_ok$next[0:0]$1905 $4\core_spr1_ok$next[0:0]$2112 + assign $0\core_spro_ok$next[0:0]$1907 $4\core_spro_ok$next[0:0]$2113 + attribute \src "libresoc.v:52035.5-52035.29" + switch \initial + attribute \src "libresoc.v:52035.9-52035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_is_32bit$next[0:0]$1928 $1\core_core_cr_wr_ok$next[0:0]$1915 $1\core_core_cr_wr$next[7:0]$1914 $1\core_core_cr_rd_ok$next[0:0]$1913 $1\core_core_cr_rd$next[7:0]$1912 $1\core_core_trapaddr$next[12:0]$1935 $1\core_core_exc_$signal$56$next[0:0]$1922 $1\core_core_exc_$signal$55$next[0:0]$1921 $1\core_core_exc_$signal$54$next[0:0]$1920 $1\core_core_exc_$signal$53$next[0:0]$1919 $1\core_core_exc_$signal$52$next[0:0]$1918 $1\core_core_exc_$signal$51$next[0:0]$1917 $1\core_core_exc_$signal$50$next[0:0]$1916 $1\core_core_exc_$signal$next[0:0]$1923 $1\core_core_traptype$next[7:0]$1936 $1\core_core_input_carry$next[1:0]$1925 $1\core_core_oe_ok$next[0:0]$1932 $1\core_core_oe$next[0:0]$1931 $1\core_core_rc_ok$next[0:0]$1934 $1\core_core_rc$next[0:0]$1933 $1\core_core_lk$next[0:0]$1929 $1\core_core_fn_unit$next[11:0]$1924 $1\core_core_insn_type$next[6:0]$1927 $1\core_core_insn$next[31:0]$1926 $1\core_core_cia$next[63:0]$1911 $1\core_core_msr$next[63:0]$1930 $1\core_cr_out_ok$next[0:0]$1944 $1\core_cr_out$next[2:0]$1943 $1\core_cr_in2_ok$49$next[0:0]$1941 $1\core_cr_in2$48$next[2:0]$1939 $1\core_cr_in2_ok$next[0:0]$1942 $1\core_cr_in2$next[2:0]$1940 $1\core_cr_in1_ok$next[0:0]$1938 $1\core_cr_in1$next[2:0]$1937 $1\core_fasto2_ok$next[0:0]$1954 $1\core_fasto2$next[2:0]$1953 $1\core_fasto1_ok$next[0:0]$1952 $1\core_fasto1$next[2:0]$1951 $1\core_fast2_ok$next[0:0]$1950 $1\core_fast2$next[2:0]$1949 $1\core_fast1_ok$next[0:0]$1948 $1\core_fast1$next[2:0]$1947 $1\core_xer_out$next[0:0]$1968 $1\core_xer_in$next[2:0]$1967 $1\core_spr1_ok$next[0:0]$1964 $1\core_spr1$next[9:0]$1963 $1\core_spro_ok$next[0:0]$1966 $1\core_spro$next[9:0]$1965 $1\core_reg3_ok$next[0:0]$1960 $1\core_reg3$next[4:0]$1959 $1\core_reg2_ok$next[0:0]$1958 $1\core_reg2$next[4:0]$1957 $1\core_reg1_ok$next[0:0]$1956 $1\core_reg1$next[4:0]$1955 $1\core_ea_ok$next[0:0]$1946 $1\core_ea$next[4:0]$1945 $1\core_rego_ok$next[0:0]$1962 $1\core_rego$next[4:0]$1961 $1\core_asmcode$next[7:0]$1910 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1910 $2\core_asmcode$next[7:0]$1969 + assign $1\core_core_cia$next[63:0]$1911 $2\core_core_cia$next[63:0]$1970 + assign $1\core_core_cr_rd$next[7:0]$1912 $2\core_core_cr_rd$next[7:0]$1971 + assign $1\core_core_cr_rd_ok$next[0:0]$1913 $2\core_core_cr_rd_ok$next[0:0]$1972 + assign $1\core_core_cr_wr$next[7:0]$1914 $2\core_core_cr_wr$next[7:0]$1973 + assign $1\core_core_cr_wr_ok$next[0:0]$1915 $2\core_core_cr_wr_ok$next[0:0]$1974 + assign $1\core_core_exc_$signal$50$next[0:0]$1916 $2\core_core_exc_$signal$50$next[0:0]$1975 + assign $1\core_core_exc_$signal$51$next[0:0]$1917 $2\core_core_exc_$signal$51$next[0:0]$1976 + assign $1\core_core_exc_$signal$52$next[0:0]$1918 $2\core_core_exc_$signal$52$next[0:0]$1977 + assign $1\core_core_exc_$signal$53$next[0:0]$1919 $2\core_core_exc_$signal$53$next[0:0]$1978 + assign $1\core_core_exc_$signal$54$next[0:0]$1920 $2\core_core_exc_$signal$54$next[0:0]$1979 + assign $1\core_core_exc_$signal$55$next[0:0]$1921 $2\core_core_exc_$signal$55$next[0:0]$1980 + assign $1\core_core_exc_$signal$56$next[0:0]$1922 $2\core_core_exc_$signal$56$next[0:0]$1981 + assign $1\core_core_exc_$signal$next[0:0]$1923 $2\core_core_exc_$signal$next[0:0]$1982 + assign $1\core_core_fn_unit$next[11:0]$1924 $2\core_core_fn_unit$next[11:0]$1983 + assign $1\core_core_input_carry$next[1:0]$1925 $2\core_core_input_carry$next[1:0]$1984 + assign $1\core_core_insn$next[31:0]$1926 $2\core_core_insn$next[31:0]$1985 + assign $1\core_core_insn_type$next[6:0]$1927 $2\core_core_insn_type$next[6:0]$1986 + assign $1\core_core_is_32bit$next[0:0]$1928 $2\core_core_is_32bit$next[0:0]$1987 + assign $1\core_core_lk$next[0:0]$1929 $2\core_core_lk$next[0:0]$1988 + assign $1\core_core_msr$next[63:0]$1930 $2\core_core_msr$next[63:0]$1989 + assign $1\core_core_oe$next[0:0]$1931 $2\core_core_oe$next[0:0]$1990 + assign $1\core_core_oe_ok$next[0:0]$1932 $2\core_core_oe_ok$next[0:0]$1991 + assign $1\core_core_rc$next[0:0]$1933 $2\core_core_rc$next[0:0]$1992 + assign $1\core_core_rc_ok$next[0:0]$1934 $2\core_core_rc_ok$next[0:0]$1993 + assign $1\core_core_trapaddr$next[12:0]$1935 $2\core_core_trapaddr$next[12:0]$1994 + assign $1\core_core_traptype$next[7:0]$1936 $2\core_core_traptype$next[7:0]$1995 + assign $1\core_cr_in1$next[2:0]$1937 $2\core_cr_in1$next[2:0]$1996 + assign $1\core_cr_in1_ok$next[0:0]$1938 $2\core_cr_in1_ok$next[0:0]$1997 + assign $1\core_cr_in2$48$next[2:0]$1939 $2\core_cr_in2$48$next[2:0]$1998 + assign $1\core_cr_in2$next[2:0]$1940 $2\core_cr_in2$next[2:0]$1999 + assign $1\core_cr_in2_ok$49$next[0:0]$1941 $2\core_cr_in2_ok$49$next[0:0]$2000 + assign $1\core_cr_in2_ok$next[0:0]$1942 $2\core_cr_in2_ok$next[0:0]$2001 + assign $1\core_cr_out$next[2:0]$1943 $2\core_cr_out$next[2:0]$2002 + assign $1\core_cr_out_ok$next[0:0]$1944 $2\core_cr_out_ok$next[0:0]$2003 + assign $1\core_ea$next[4:0]$1945 $2\core_ea$next[4:0]$2004 + assign $1\core_ea_ok$next[0:0]$1946 $2\core_ea_ok$next[0:0]$2005 + assign $1\core_fast1$next[2:0]$1947 $2\core_fast1$next[2:0]$2006 + assign $1\core_fast1_ok$next[0:0]$1948 $2\core_fast1_ok$next[0:0]$2007 + assign $1\core_fast2$next[2:0]$1949 $2\core_fast2$next[2:0]$2008 + assign $1\core_fast2_ok$next[0:0]$1950 $2\core_fast2_ok$next[0:0]$2009 + assign $1\core_fasto1$next[2:0]$1951 $2\core_fasto1$next[2:0]$2010 + assign $1\core_fasto1_ok$next[0:0]$1952 $2\core_fasto1_ok$next[0:0]$2011 + assign $1\core_fasto2$next[2:0]$1953 $2\core_fasto2$next[2:0]$2012 + assign $1\core_fasto2_ok$next[0:0]$1954 $2\core_fasto2_ok$next[0:0]$2013 + assign $1\core_reg1$next[4:0]$1955 $2\core_reg1$next[4:0]$2014 + assign $1\core_reg1_ok$next[0:0]$1956 $2\core_reg1_ok$next[0:0]$2015 + assign $1\core_reg2$next[4:0]$1957 $2\core_reg2$next[4:0]$2016 + assign $1\core_reg2_ok$next[0:0]$1958 $2\core_reg2_ok$next[0:0]$2017 + assign $1\core_reg3$next[4:0]$1959 $2\core_reg3$next[4:0]$2018 + assign $1\core_reg3_ok$next[0:0]$1960 $2\core_reg3_ok$next[0:0]$2019 + assign $1\core_rego$next[4:0]$1961 $2\core_rego$next[4:0]$2020 + assign $1\core_rego_ok$next[0:0]$1962 $2\core_rego_ok$next[0:0]$2021 + assign $1\core_spr1$next[9:0]$1963 $2\core_spr1$next[9:0]$2022 + assign $1\core_spr1_ok$next[0:0]$1964 $2\core_spr1_ok$next[0:0]$2023 + assign $1\core_spro$next[9:0]$1965 $2\core_spro$next[9:0]$2024 + assign $1\core_spro_ok$next[0:0]$1966 $2\core_spro_ok$next[0:0]$2025 + assign $1\core_xer_in$next[2:0]$1967 $2\core_xer_in$next[2:0]$2026 + assign $1\core_xer_out$next[0:0]$1968 $2\core_xer_out$next[0:0]$2027 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_asmcode$next[7:0]$1969 \core_asmcode + assign $2\core_core_cia$next[63:0]$1970 \core_core_cia + assign $2\core_core_cr_rd$next[7:0]$1971 \core_core_cr_rd + assign $2\core_core_cr_rd_ok$next[0:0]$1972 \core_core_cr_rd_ok + assign $2\core_core_cr_wr$next[7:0]$1973 \core_core_cr_wr + assign $2\core_core_cr_wr_ok$next[0:0]$1974 \core_core_cr_wr_ok + assign $2\core_core_exc_$signal$50$next[0:0]$1975 \core_core_exc_$signal$50 + assign $2\core_core_exc_$signal$51$next[0:0]$1976 \core_core_exc_$signal$51 + assign $2\core_core_exc_$signal$52$next[0:0]$1977 \core_core_exc_$signal$52 + assign $2\core_core_exc_$signal$53$next[0:0]$1978 \core_core_exc_$signal$53 + assign $2\core_core_exc_$signal$54$next[0:0]$1979 \core_core_exc_$signal$54 + assign $2\core_core_exc_$signal$55$next[0:0]$1980 \core_core_exc_$signal$55 + assign $2\core_core_exc_$signal$56$next[0:0]$1981 \core_core_exc_$signal$56 + assign $2\core_core_exc_$signal$next[0:0]$1982 \core_core_exc_$signal + assign $2\core_core_fn_unit$next[11:0]$1983 \core_core_fn_unit + assign $2\core_core_input_carry$next[1:0]$1984 \core_core_input_carry + assign $2\core_core_insn$next[31:0]$1985 \core_core_insn + assign $2\core_core_insn_type$next[6:0]$1986 \core_core_insn_type + assign $2\core_core_is_32bit$next[0:0]$1987 \core_core_is_32bit + assign $2\core_core_lk$next[0:0]$1988 \core_core_lk + assign $2\core_core_msr$next[63:0]$1989 \core_core_msr + assign $2\core_core_oe$next[0:0]$1990 \core_core_oe + assign $2\core_core_oe_ok$next[0:0]$1991 \core_core_oe_ok + assign $2\core_core_rc$next[0:0]$1992 \core_core_rc + assign $2\core_core_rc_ok$next[0:0]$1993 \core_core_rc_ok + assign $2\core_core_trapaddr$next[12:0]$1994 \core_core_trapaddr + assign $2\core_core_traptype$next[7:0]$1995 \core_core_traptype + assign $2\core_cr_in1$next[2:0]$1996 \core_cr_in1 + assign $2\core_cr_in1_ok$next[0:0]$1997 \core_cr_in1_ok + assign $2\core_cr_in2$48$next[2:0]$1998 \core_cr_in2$48 + assign $2\core_cr_in2$next[2:0]$1999 \core_cr_in2 + assign $2\core_cr_in2_ok$49$next[0:0]$2000 \core_cr_in2_ok$49 + assign $2\core_cr_in2_ok$next[0:0]$2001 \core_cr_in2_ok + assign $2\core_cr_out$next[2:0]$2002 \core_cr_out + assign $2\core_cr_out_ok$next[0:0]$2003 \core_cr_out_ok + assign $2\core_ea$next[4:0]$2004 \core_ea + assign $2\core_ea_ok$next[0:0]$2005 \core_ea_ok + assign $2\core_fast1$next[2:0]$2006 \core_fast1 + assign $2\core_fast1_ok$next[0:0]$2007 \core_fast1_ok + assign $2\core_fast2$next[2:0]$2008 \core_fast2 + assign $2\core_fast2_ok$next[0:0]$2009 \core_fast2_ok + assign $2\core_fasto1$next[2:0]$2010 \core_fasto1 + assign $2\core_fasto1_ok$next[0:0]$2011 \core_fasto1_ok + assign $2\core_fasto2$next[2:0]$2012 \core_fasto2 + assign $2\core_fasto2_ok$next[0:0]$2013 \core_fasto2_ok + assign $2\core_reg1$next[4:0]$2014 \core_reg1 + assign $2\core_reg1_ok$next[0:0]$2015 \core_reg1_ok + assign $2\core_reg2$next[4:0]$2016 \core_reg2 + assign $2\core_reg2_ok$next[0:0]$2017 \core_reg2_ok + assign $2\core_reg3$next[4:0]$2018 \core_reg3 + assign $2\core_reg3_ok$next[0:0]$2019 \core_reg3_ok + assign $2\core_rego$next[4:0]$2020 \core_rego + assign $2\core_rego_ok$next[0:0]$2021 \core_rego_ok + assign $2\core_spr1$next[9:0]$2022 \core_spr1 + assign $2\core_spr1_ok$next[0:0]$2023 \core_spr1_ok + assign $2\core_spro$next[9:0]$2024 \core_spro + assign $2\core_spro_ok$next[0:0]$2025 \core_spro_ok + assign $2\core_xer_in$next[2:0]$2026 \core_xer_in + assign $2\core_xer_out$next[0:0]$2027 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_is_32bit$next[0:0]$1987 $2\core_core_cr_wr_ok$next[0:0]$1974 $2\core_core_cr_wr$next[7:0]$1973 $2\core_core_cr_rd_ok$next[0:0]$1972 $2\core_core_cr_rd$next[7:0]$1971 $2\core_core_trapaddr$next[12:0]$1994 $2\core_core_exc_$signal$56$next[0:0]$1981 $2\core_core_exc_$signal$55$next[0:0]$1980 $2\core_core_exc_$signal$54$next[0:0]$1979 $2\core_core_exc_$signal$53$next[0:0]$1978 $2\core_core_exc_$signal$52$next[0:0]$1977 $2\core_core_exc_$signal$51$next[0:0]$1976 $2\core_core_exc_$signal$50$next[0:0]$1975 $2\core_core_exc_$signal$next[0:0]$1982 $2\core_core_traptype$next[7:0]$1995 $2\core_core_input_carry$next[1:0]$1984 $2\core_core_oe_ok$next[0:0]$1991 $2\core_core_oe$next[0:0]$1990 $2\core_core_rc_ok$next[0:0]$1993 $2\core_core_rc$next[0:0]$1992 $2\core_core_lk$next[0:0]$1988 $2\core_core_fn_unit$next[11:0]$1983 $2\core_core_insn_type$next[6:0]$1986 $2\core_core_insn$next[31:0]$1985 $2\core_core_cia$next[63:0]$1970 $2\core_core_msr$next[63:0]$1989 $2\core_cr_out_ok$next[0:0]$2003 $2\core_cr_out$next[2:0]$2002 $2\core_cr_in2_ok$49$next[0:0]$2000 $2\core_cr_in2$48$next[2:0]$1998 $2\core_cr_in2_ok$next[0:0]$2001 $2\core_cr_in2$next[2:0]$1999 $2\core_cr_in1_ok$next[0:0]$1997 $2\core_cr_in1$next[2:0]$1996 $2\core_fasto2_ok$next[0:0]$2013 $2\core_fasto2$next[2:0]$2012 $2\core_fasto1_ok$next[0:0]$2011 $2\core_fasto1$next[2:0]$2010 $2\core_fast2_ok$next[0:0]$2009 $2\core_fast2$next[2:0]$2008 $2\core_fast1_ok$next[0:0]$2007 $2\core_fast1$next[2:0]$2006 $2\core_xer_out$next[0:0]$2027 $2\core_xer_in$next[2:0]$2026 $2\core_spr1_ok$next[0:0]$2023 $2\core_spr1$next[9:0]$2022 $2\core_spro_ok$next[0:0]$2025 $2\core_spro$next[9:0]$2024 $2\core_reg3_ok$next[0:0]$2019 $2\core_reg3$next[4:0]$2018 $2\core_reg2_ok$next[0:0]$2017 $2\core_reg2$next[4:0]$2016 $2\core_reg1_ok$next[0:0]$2015 $2\core_reg1$next[4:0]$2014 $2\core_ea_ok$next[0:0]$2005 $2\core_ea$next[4:0]$2004 $2\core_rego_ok$next[0:0]$2021 $2\core_rego$next[4:0]$2020 $2\core_asmcode$next[7:0]$1969 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$9 \dec2_exc_$signal$8 \dec2_exc_$signal$7 \dec2_exc_$signal$6 \dec2_exc_$signal$5 \dec2_exc_$signal$4 \dec2_exc_$signal$3 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$1910 $3\core_asmcode$next[7:0]$2028 + assign $1\core_core_cia$next[63:0]$1911 $3\core_core_cia$next[63:0]$2029 + assign $1\core_core_cr_rd$next[7:0]$1912 $3\core_core_cr_rd$next[7:0]$2030 + assign $1\core_core_cr_rd_ok$next[0:0]$1913 $3\core_core_cr_rd_ok$next[0:0]$2031 + assign $1\core_core_cr_wr$next[7:0]$1914 $3\core_core_cr_wr$next[7:0]$2032 + assign $1\core_core_cr_wr_ok$next[0:0]$1915 $3\core_core_cr_wr_ok$next[0:0]$2033 + assign $1\core_core_exc_$signal$50$next[0:0]$1916 $3\core_core_exc_$signal$50$next[0:0]$2034 + assign $1\core_core_exc_$signal$51$next[0:0]$1917 $3\core_core_exc_$signal$51$next[0:0]$2035 + assign $1\core_core_exc_$signal$52$next[0:0]$1918 $3\core_core_exc_$signal$52$next[0:0]$2036 + assign $1\core_core_exc_$signal$53$next[0:0]$1919 $3\core_core_exc_$signal$53$next[0:0]$2037 + assign $1\core_core_exc_$signal$54$next[0:0]$1920 $3\core_core_exc_$signal$54$next[0:0]$2038 + assign $1\core_core_exc_$signal$55$next[0:0]$1921 $3\core_core_exc_$signal$55$next[0:0]$2039 + assign $1\core_core_exc_$signal$56$next[0:0]$1922 $3\core_core_exc_$signal$56$next[0:0]$2040 + assign $1\core_core_exc_$signal$next[0:0]$1923 $3\core_core_exc_$signal$next[0:0]$2041 + assign $1\core_core_fn_unit$next[11:0]$1924 $3\core_core_fn_unit$next[11:0]$2042 + assign $1\core_core_input_carry$next[1:0]$1925 $3\core_core_input_carry$next[1:0]$2043 + assign $1\core_core_insn$next[31:0]$1926 $3\core_core_insn$next[31:0]$2044 + assign $1\core_core_insn_type$next[6:0]$1927 $3\core_core_insn_type$next[6:0]$2045 + assign $1\core_core_is_32bit$next[0:0]$1928 $3\core_core_is_32bit$next[0:0]$2046 + assign $1\core_core_lk$next[0:0]$1929 $3\core_core_lk$next[0:0]$2047 + assign $1\core_core_msr$next[63:0]$1930 $3\core_core_msr$next[63:0]$2048 + assign $1\core_core_oe$next[0:0]$1931 $3\core_core_oe$next[0:0]$2049 + assign $1\core_core_oe_ok$next[0:0]$1932 $3\core_core_oe_ok$next[0:0]$2050 + assign $1\core_core_rc$next[0:0]$1933 $3\core_core_rc$next[0:0]$2051 + assign $1\core_core_rc_ok$next[0:0]$1934 $3\core_core_rc_ok$next[0:0]$2052 + assign $1\core_core_trapaddr$next[12:0]$1935 $3\core_core_trapaddr$next[12:0]$2053 + assign $1\core_core_traptype$next[7:0]$1936 $3\core_core_traptype$next[7:0]$2054 + assign $1\core_cr_in1$next[2:0]$1937 $3\core_cr_in1$next[2:0]$2055 + assign $1\core_cr_in1_ok$next[0:0]$1938 $3\core_cr_in1_ok$next[0:0]$2056 + assign $1\core_cr_in2$48$next[2:0]$1939 $3\core_cr_in2$48$next[2:0]$2057 + assign $1\core_cr_in2$next[2:0]$1940 $3\core_cr_in2$next[2:0]$2058 + assign $1\core_cr_in2_ok$49$next[0:0]$1941 $3\core_cr_in2_ok$49$next[0:0]$2059 + assign $1\core_cr_in2_ok$next[0:0]$1942 $3\core_cr_in2_ok$next[0:0]$2060 + assign $1\core_cr_out$next[2:0]$1943 $3\core_cr_out$next[2:0]$2061 + assign $1\core_cr_out_ok$next[0:0]$1944 $3\core_cr_out_ok$next[0:0]$2062 + assign $1\core_ea$next[4:0]$1945 $3\core_ea$next[4:0]$2063 + assign $1\core_ea_ok$next[0:0]$1946 $3\core_ea_ok$next[0:0]$2064 + assign $1\core_fast1$next[2:0]$1947 $3\core_fast1$next[2:0]$2065 + assign $1\core_fast1_ok$next[0:0]$1948 $3\core_fast1_ok$next[0:0]$2066 + assign $1\core_fast2$next[2:0]$1949 $3\core_fast2$next[2:0]$2067 + assign $1\core_fast2_ok$next[0:0]$1950 $3\core_fast2_ok$next[0:0]$2068 + assign $1\core_fasto1$next[2:0]$1951 $3\core_fasto1$next[2:0]$2069 + assign $1\core_fasto1_ok$next[0:0]$1952 $3\core_fasto1_ok$next[0:0]$2070 + assign $1\core_fasto2$next[2:0]$1953 $3\core_fasto2$next[2:0]$2071 + assign $1\core_fasto2_ok$next[0:0]$1954 $3\core_fasto2_ok$next[0:0]$2072 + assign $1\core_reg1$next[4:0]$1955 $3\core_reg1$next[4:0]$2073 + assign $1\core_reg1_ok$next[0:0]$1956 $3\core_reg1_ok$next[0:0]$2074 + assign $1\core_reg2$next[4:0]$1957 $3\core_reg2$next[4:0]$2075 + assign $1\core_reg2_ok$next[0:0]$1958 $3\core_reg2_ok$next[0:0]$2076 + assign $1\core_reg3$next[4:0]$1959 $3\core_reg3$next[4:0]$2077 + assign $1\core_reg3_ok$next[0:0]$1960 $3\core_reg3_ok$next[0:0]$2078 + assign $1\core_rego$next[4:0]$1961 $3\core_rego$next[4:0]$2079 + assign $1\core_rego_ok$next[0:0]$1962 $3\core_rego_ok$next[0:0]$2080 + assign $1\core_spr1$next[9:0]$1963 $3\core_spr1$next[9:0]$2081 + assign $1\core_spr1_ok$next[0:0]$1964 $3\core_spr1_ok$next[0:0]$2082 + assign $1\core_spro$next[9:0]$1965 $3\core_spro$next[9:0]$2083 + assign $1\core_spro_ok$next[0:0]$1966 $3\core_spro_ok$next[0:0]$2084 + assign $1\core_xer_in$next[2:0]$1967 $3\core_xer_in$next[2:0]$2085 + assign $1\core_xer_out$next[0:0]$1968 $3\core_xer_out$next[0:0]$2086 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_is_32bit$next[0:0]$2046 $3\core_core_cr_wr_ok$next[0:0]$2033 $3\core_core_cr_wr$next[7:0]$2032 $3\core_core_cr_rd_ok$next[0:0]$2031 $3\core_core_cr_rd$next[7:0]$2030 $3\core_core_trapaddr$next[12:0]$2053 $3\core_core_exc_$signal$56$next[0:0]$2040 $3\core_core_exc_$signal$55$next[0:0]$2039 $3\core_core_exc_$signal$54$next[0:0]$2038 $3\core_core_exc_$signal$53$next[0:0]$2037 $3\core_core_exc_$signal$52$next[0:0]$2036 $3\core_core_exc_$signal$51$next[0:0]$2035 $3\core_core_exc_$signal$50$next[0:0]$2034 $3\core_core_exc_$signal$next[0:0]$2041 $3\core_core_traptype$next[7:0]$2054 $3\core_core_input_carry$next[1:0]$2043 $3\core_core_oe_ok$next[0:0]$2050 $3\core_core_oe$next[0:0]$2049 $3\core_core_rc_ok$next[0:0]$2052 $3\core_core_rc$next[0:0]$2051 $3\core_core_lk$next[0:0]$2047 $3\core_core_fn_unit$next[11:0]$2042 $3\core_core_insn_type$next[6:0]$2045 $3\core_core_insn$next[31:0]$2044 $3\core_core_cia$next[63:0]$2029 $3\core_core_msr$next[63:0]$2048 $3\core_cr_out_ok$next[0:0]$2062 $3\core_cr_out$next[2:0]$2061 $3\core_cr_in2_ok$49$next[0:0]$2059 $3\core_cr_in2$48$next[2:0]$2057 $3\core_cr_in2_ok$next[0:0]$2060 $3\core_cr_in2$next[2:0]$2058 $3\core_cr_in1_ok$next[0:0]$2056 $3\core_cr_in1$next[2:0]$2055 $3\core_fasto2_ok$next[0:0]$2072 $3\core_fasto2$next[2:0]$2071 $3\core_fasto1_ok$next[0:0]$2070 $3\core_fasto1$next[2:0]$2069 $3\core_fast2_ok$next[0:0]$2068 $3\core_fast2$next[2:0]$2067 $3\core_fast1_ok$next[0:0]$2066 $3\core_fast1$next[2:0]$2065 $3\core_xer_out$next[0:0]$2086 $3\core_xer_in$next[2:0]$2085 $3\core_spr1_ok$next[0:0]$2082 $3\core_spr1$next[9:0]$2081 $3\core_spro_ok$next[0:0]$2084 $3\core_spro$next[9:0]$2083 $3\core_reg3_ok$next[0:0]$2078 $3\core_reg3$next[4:0]$2077 $3\core_reg2_ok$next[0:0]$2076 $3\core_reg2$next[4:0]$2075 $3\core_reg1_ok$next[0:0]$2074 $3\core_reg1$next[4:0]$2073 $3\core_ea_ok$next[0:0]$2064 $3\core_ea$next[4:0]$2063 $3\core_rego_ok$next[0:0]$2080 $3\core_rego$next[4:0]$2079 $3\core_asmcode$next[7:0]$2028 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$2028 \core_asmcode + assign $3\core_core_cia$next[63:0]$2029 \core_core_cia + assign $3\core_core_cr_rd$next[7:0]$2030 \core_core_cr_rd + assign $3\core_core_cr_rd_ok$next[0:0]$2031 \core_core_cr_rd_ok + assign $3\core_core_cr_wr$next[7:0]$2032 \core_core_cr_wr + assign $3\core_core_cr_wr_ok$next[0:0]$2033 \core_core_cr_wr_ok + assign $3\core_core_exc_$signal$50$next[0:0]$2034 \core_core_exc_$signal$50 + assign $3\core_core_exc_$signal$51$next[0:0]$2035 \core_core_exc_$signal$51 + assign $3\core_core_exc_$signal$52$next[0:0]$2036 \core_core_exc_$signal$52 + assign $3\core_core_exc_$signal$53$next[0:0]$2037 \core_core_exc_$signal$53 + assign $3\core_core_exc_$signal$54$next[0:0]$2038 \core_core_exc_$signal$54 + assign $3\core_core_exc_$signal$55$next[0:0]$2039 \core_core_exc_$signal$55 + assign $3\core_core_exc_$signal$56$next[0:0]$2040 \core_core_exc_$signal$56 + assign $3\core_core_exc_$signal$next[0:0]$2041 \core_core_exc_$signal + assign $3\core_core_fn_unit$next[11:0]$2042 \core_core_fn_unit + assign $3\core_core_input_carry$next[1:0]$2043 \core_core_input_carry + assign $3\core_core_insn$next[31:0]$2044 \core_core_insn + assign $3\core_core_insn_type$next[6:0]$2045 \core_core_insn_type + assign $3\core_core_is_32bit$next[0:0]$2046 \core_core_is_32bit + assign $3\core_core_lk$next[0:0]$2047 \core_core_lk + assign $3\core_core_msr$next[63:0]$2048 \core_core_msr + assign $3\core_core_oe$next[0:0]$2049 \core_core_oe + assign $3\core_core_oe_ok$next[0:0]$2050 \core_core_oe_ok + assign $3\core_core_rc$next[0:0]$2051 \core_core_rc + assign $3\core_core_rc_ok$next[0:0]$2052 \core_core_rc_ok + assign $3\core_core_trapaddr$next[12:0]$2053 \core_core_trapaddr + assign $3\core_core_traptype$next[7:0]$2054 \core_core_traptype + assign $3\core_cr_in1$next[2:0]$2055 \core_cr_in1 + assign $3\core_cr_in1_ok$next[0:0]$2056 \core_cr_in1_ok + assign $3\core_cr_in2$48$next[2:0]$2057 \core_cr_in2$48 + assign $3\core_cr_in2$next[2:0]$2058 \core_cr_in2 + assign $3\core_cr_in2_ok$49$next[0:0]$2059 \core_cr_in2_ok$49 + assign $3\core_cr_in2_ok$next[0:0]$2060 \core_cr_in2_ok + assign $3\core_cr_out$next[2:0]$2061 \core_cr_out + assign $3\core_cr_out_ok$next[0:0]$2062 \core_cr_out_ok + assign $3\core_ea$next[4:0]$2063 \core_ea + assign $3\core_ea_ok$next[0:0]$2064 \core_ea_ok + assign $3\core_fast1$next[2:0]$2065 \core_fast1 + assign $3\core_fast1_ok$next[0:0]$2066 \core_fast1_ok + assign $3\core_fast2$next[2:0]$2067 \core_fast2 + assign $3\core_fast2_ok$next[0:0]$2068 \core_fast2_ok + assign $3\core_fasto1$next[2:0]$2069 \core_fasto1 + assign $3\core_fasto1_ok$next[0:0]$2070 \core_fasto1_ok + assign $3\core_fasto2$next[2:0]$2071 \core_fasto2 + assign $3\core_fasto2_ok$next[0:0]$2072 \core_fasto2_ok + assign $3\core_reg1$next[4:0]$2073 \core_reg1 + assign $3\core_reg1_ok$next[0:0]$2074 \core_reg1_ok + assign $3\core_reg2$next[4:0]$2075 \core_reg2 + assign $3\core_reg2_ok$next[0:0]$2076 \core_reg2_ok + assign $3\core_reg3$next[4:0]$2077 \core_reg3 + assign $3\core_reg3_ok$next[0:0]$2078 \core_reg3_ok + assign $3\core_rego$next[4:0]$2079 \core_rego + assign $3\core_rego_ok$next[0:0]$2080 \core_rego_ok + assign $3\core_spr1$next[9:0]$2081 \core_spr1 + assign $3\core_spr1_ok$next[0:0]$2082 \core_spr1_ok + assign $3\core_spro$next[9:0]$2083 \core_spro + assign $3\core_spro_ok$next[0:0]$2084 \core_spro_ok + assign $3\core_xer_in$next[2:0]$2085 \core_xer_in + assign $3\core_xer_out$next[0:0]$2086 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$1910 \core_asmcode + assign $1\core_core_cia$next[63:0]$1911 \core_core_cia + assign $1\core_core_cr_rd$next[7:0]$1912 \core_core_cr_rd + assign $1\core_core_cr_rd_ok$next[0:0]$1913 \core_core_cr_rd_ok + assign $1\core_core_cr_wr$next[7:0]$1914 \core_core_cr_wr + assign $1\core_core_cr_wr_ok$next[0:0]$1915 \core_core_cr_wr_ok + assign $1\core_core_exc_$signal$50$next[0:0]$1916 \core_core_exc_$signal$50 + assign $1\core_core_exc_$signal$51$next[0:0]$1917 \core_core_exc_$signal$51 + assign $1\core_core_exc_$signal$52$next[0:0]$1918 \core_core_exc_$signal$52 + assign $1\core_core_exc_$signal$53$next[0:0]$1919 \core_core_exc_$signal$53 + assign $1\core_core_exc_$signal$54$next[0:0]$1920 \core_core_exc_$signal$54 + assign $1\core_core_exc_$signal$55$next[0:0]$1921 \core_core_exc_$signal$55 + assign $1\core_core_exc_$signal$56$next[0:0]$1922 \core_core_exc_$signal$56 + assign $1\core_core_exc_$signal$next[0:0]$1923 \core_core_exc_$signal + assign $1\core_core_fn_unit$next[11:0]$1924 \core_core_fn_unit + assign $1\core_core_input_carry$next[1:0]$1925 \core_core_input_carry + assign $1\core_core_insn$next[31:0]$1926 \core_core_insn + assign $1\core_core_insn_type$next[6:0]$1927 \core_core_insn_type + assign $1\core_core_is_32bit$next[0:0]$1928 \core_core_is_32bit + assign $1\core_core_lk$next[0:0]$1929 \core_core_lk + assign $1\core_core_msr$next[63:0]$1930 \core_core_msr + assign $1\core_core_oe$next[0:0]$1931 \core_core_oe + assign $1\core_core_oe_ok$next[0:0]$1932 \core_core_oe_ok + assign $1\core_core_rc$next[0:0]$1933 \core_core_rc + assign $1\core_core_rc_ok$next[0:0]$1934 \core_core_rc_ok + assign $1\core_core_trapaddr$next[12:0]$1935 \core_core_trapaddr + assign $1\core_core_traptype$next[7:0]$1936 \core_core_traptype + assign $1\core_cr_in1$next[2:0]$1937 \core_cr_in1 + assign $1\core_cr_in1_ok$next[0:0]$1938 \core_cr_in1_ok + assign $1\core_cr_in2$48$next[2:0]$1939 \core_cr_in2$48 + assign $1\core_cr_in2$next[2:0]$1940 \core_cr_in2 + assign $1\core_cr_in2_ok$49$next[0:0]$1941 \core_cr_in2_ok$49 + assign $1\core_cr_in2_ok$next[0:0]$1942 \core_cr_in2_ok + assign $1\core_cr_out$next[2:0]$1943 \core_cr_out + assign $1\core_cr_out_ok$next[0:0]$1944 \core_cr_out_ok + assign $1\core_ea$next[4:0]$1945 \core_ea + assign $1\core_ea_ok$next[0:0]$1946 \core_ea_ok + assign $1\core_fast1$next[2:0]$1947 \core_fast1 + assign $1\core_fast1_ok$next[0:0]$1948 \core_fast1_ok + assign $1\core_fast2$next[2:0]$1949 \core_fast2 + assign $1\core_fast2_ok$next[0:0]$1950 \core_fast2_ok + assign $1\core_fasto1$next[2:0]$1951 \core_fasto1 + assign $1\core_fasto1_ok$next[0:0]$1952 \core_fasto1_ok + assign $1\core_fasto2$next[2:0]$1953 \core_fasto2 + assign $1\core_fasto2_ok$next[0:0]$1954 \core_fasto2_ok + assign $1\core_reg1$next[4:0]$1955 \core_reg1 + assign $1\core_reg1_ok$next[0:0]$1956 \core_reg1_ok + assign $1\core_reg2$next[4:0]$1957 \core_reg2 + assign $1\core_reg2_ok$next[0:0]$1958 \core_reg2_ok + assign $1\core_reg3$next[4:0]$1959 \core_reg3 + assign $1\core_reg3_ok$next[0:0]$1960 \core_reg3_ok + assign $1\core_rego$next[4:0]$1961 \core_rego + assign $1\core_rego_ok$next[0:0]$1962 \core_rego_ok + assign $1\core_spr1$next[9:0]$1963 \core_spr1 + assign $1\core_spr1_ok$next[0:0]$1964 \core_spr1_ok + assign $1\core_spro$next[9:0]$1965 \core_spro + assign $1\core_spro_ok$next[0:0]$1966 \core_spro_ok + assign $1\core_xer_in$next[2:0]$1967 \core_xer_in + assign $1\core_xer_out$next[0:0]$1968 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$2111 1'0 + assign $4\core_ea_ok$next[0:0]$2103 1'0 + assign $4\core_reg1_ok$next[0:0]$2108 1'0 + assign $4\core_reg2_ok$next[0:0]$2109 1'0 + assign $4\core_reg3_ok$next[0:0]$2110 1'0 + assign $4\core_spro_ok$next[0:0]$2113 1'0 + assign $4\core_spr1_ok$next[0:0]$2112 1'0 + assign $4\core_fast1_ok$next[0:0]$2104 1'0 + assign $4\core_fast2_ok$next[0:0]$2105 1'0 + assign $4\core_fasto1_ok$next[0:0]$2106 1'0 + assign $4\core_fasto2_ok$next[0:0]$2107 1'0 + assign $4\core_cr_in1_ok$next[0:0]$2099 1'0 + assign $4\core_cr_in2_ok$next[0:0]$2101 1'0 + assign $4\core_cr_in2_ok$49$next[0:0]$2100 1'0 + assign $4\core_cr_out_ok$next[0:0]$2102 1'0 + assign $4\core_core_rc_ok$next[0:0]$2098 1'0 + assign $4\core_core_oe_ok$next[0:0]$2097 1'0 + assign $4\core_core_exc_$signal$next[0:0]$2096 1'0 + assign $4\core_core_exc_$signal$50$next[0:0]$2089 1'0 + assign $4\core_core_exc_$signal$51$next[0:0]$2090 1'0 + assign $4\core_core_exc_$signal$52$next[0:0]$2091 1'0 + assign $4\core_core_exc_$signal$53$next[0:0]$2092 1'0 + assign $4\core_core_exc_$signal$54$next[0:0]$2093 1'0 + assign $4\core_core_exc_$signal$55$next[0:0]$2094 1'0 + assign $4\core_core_exc_$signal$56$next[0:0]$2095 1'0 + assign $4\core_core_cr_rd_ok$next[0:0]$2087 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$2088 1'0 + case + assign $4\core_core_cr_rd_ok$next[0:0]$2087 $1\core_core_cr_rd_ok$next[0:0]$1913 + assign $4\core_core_cr_wr_ok$next[0:0]$2088 $1\core_core_cr_wr_ok$next[0:0]$1915 + assign $4\core_core_exc_$signal$50$next[0:0]$2089 $1\core_core_exc_$signal$50$next[0:0]$1916 + assign $4\core_core_exc_$signal$51$next[0:0]$2090 $1\core_core_exc_$signal$51$next[0:0]$1917 + assign $4\core_core_exc_$signal$52$next[0:0]$2091 $1\core_core_exc_$signal$52$next[0:0]$1918 + assign $4\core_core_exc_$signal$53$next[0:0]$2092 $1\core_core_exc_$signal$53$next[0:0]$1919 + assign $4\core_core_exc_$signal$54$next[0:0]$2093 $1\core_core_exc_$signal$54$next[0:0]$1920 + assign $4\core_core_exc_$signal$55$next[0:0]$2094 $1\core_core_exc_$signal$55$next[0:0]$1921 + assign $4\core_core_exc_$signal$56$next[0:0]$2095 $1\core_core_exc_$signal$56$next[0:0]$1922 + assign $4\core_core_exc_$signal$next[0:0]$2096 $1\core_core_exc_$signal$next[0:0]$1923 + assign $4\core_core_oe_ok$next[0:0]$2097 $1\core_core_oe_ok$next[0:0]$1932 + assign $4\core_core_rc_ok$next[0:0]$2098 $1\core_core_rc_ok$next[0:0]$1934 + assign $4\core_cr_in1_ok$next[0:0]$2099 $1\core_cr_in1_ok$next[0:0]$1938 + assign $4\core_cr_in2_ok$49$next[0:0]$2100 $1\core_cr_in2_ok$49$next[0:0]$1941 + assign $4\core_cr_in2_ok$next[0:0]$2101 $1\core_cr_in2_ok$next[0:0]$1942 + assign $4\core_cr_out_ok$next[0:0]$2102 $1\core_cr_out_ok$next[0:0]$1944 + assign $4\core_ea_ok$next[0:0]$2103 $1\core_ea_ok$next[0:0]$1946 + assign $4\core_fast1_ok$next[0:0]$2104 $1\core_fast1_ok$next[0:0]$1948 + assign $4\core_fast2_ok$next[0:0]$2105 $1\core_fast2_ok$next[0:0]$1950 + assign $4\core_fasto1_ok$next[0:0]$2106 $1\core_fasto1_ok$next[0:0]$1952 + assign $4\core_fasto2_ok$next[0:0]$2107 $1\core_fasto2_ok$next[0:0]$1954 + assign $4\core_reg1_ok$next[0:0]$2108 $1\core_reg1_ok$next[0:0]$1956 + assign $4\core_reg2_ok$next[0:0]$2109 $1\core_reg2_ok$next[0:0]$1958 + assign $4\core_reg3_ok$next[0:0]$2110 $1\core_reg3_ok$next[0:0]$1960 + assign $4\core_rego_ok$next[0:0]$2111 $1\core_rego_ok$next[0:0]$1962 + assign $4\core_spr1_ok$next[0:0]$2112 $1\core_spr1_ok$next[0:0]$1964 + assign $4\core_spro_ok$next[0:0]$2113 $1\core_spro_ok$next[0:0]$1966 + end sync always - sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14320 + update \core_asmcode$next $0\core_asmcode$next[7:0]$1851 + update \core_core_cia$next $0\core_core_cia$next[63:0]$1852 + update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1853 + update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1854 + update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1855 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1856 + update \core_core_exc_$signal$50$next $0\core_core_exc_$signal$50$next[0:0]$1857 + update \core_core_exc_$signal$51$next $0\core_core_exc_$signal$51$next[0:0]$1858 + update \core_core_exc_$signal$52$next $0\core_core_exc_$signal$52$next[0:0]$1859 + update \core_core_exc_$signal$53$next $0\core_core_exc_$signal$53$next[0:0]$1860 + update \core_core_exc_$signal$54$next $0\core_core_exc_$signal$54$next[0:0]$1861 + update \core_core_exc_$signal$55$next $0\core_core_exc_$signal$55$next[0:0]$1862 + update \core_core_exc_$signal$56$next $0\core_core_exc_$signal$56$next[0:0]$1863 + update \core_core_exc_$signal$next $0\core_core_exc_$signal$next[0:0]$1864 + update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1865 + update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1866 + update \core_core_insn$next $0\core_core_insn$next[31:0]$1867 + update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1868 + update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1869 + update \core_core_lk$next $0\core_core_lk$next[0:0]$1870 + update \core_core_msr$next $0\core_core_msr$next[63:0]$1871 + update \core_core_oe$next $0\core_core_oe$next[0:0]$1872 + update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1873 + update \core_core_rc$next $0\core_core_rc$next[0:0]$1874 + update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1875 + update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1876 + update \core_core_traptype$next $0\core_core_traptype$next[7:0]$1877 + update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1878 + update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1879 + update \core_cr_in2$48$next $0\core_cr_in2$48$next[2:0]$1880 + update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1881 + update \core_cr_in2_ok$49$next $0\core_cr_in2_ok$49$next[0:0]$1882 + update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1883 + update \core_cr_out$next $0\core_cr_out$next[2:0]$1884 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1885 + update \core_ea$next $0\core_ea$next[4:0]$1886 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1887 + update \core_fast1$next $0\core_fast1$next[2:0]$1888 + update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1889 + update \core_fast2$next $0\core_fast2$next[2:0]$1890 + update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1891 + update \core_fasto1$next $0\core_fasto1$next[2:0]$1892 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1893 + update \core_fasto2$next $0\core_fasto2$next[2:0]$1894 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1895 + update \core_reg1$next $0\core_reg1$next[4:0]$1896 + update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1897 + update \core_reg2$next $0\core_reg2$next[4:0]$1898 + update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1899 + update \core_reg3$next $0\core_reg3$next[4:0]$1900 + update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1901 + update \core_rego$next $0\core_rego$next[4:0]$1902 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1903 + update \core_spr1$next $0\core_spr1$next[9:0]$1904 + update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1905 + update \core_spro$next $0\core_spro$next[9:0]$1906 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1907 + update \core_xer_in$next $0\core_xer_in$next[2:0]$1908 + update \core_xer_out$next $0\core_xer_out$next[0:0]$1909 + end + attribute \src "libresoc.v:52157.3-52165.6" + process $proc$libresoc.v:52157$2114 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__ack_o$next[0:0]$2115 $1\jtag_dmi0__ack_o$next[0:0]$2116 + attribute \src "libresoc.v:52158.5-52158.29" + switch \initial + attribute \src "libresoc.v:52158.9-52158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__ack_o$next[0:0]$2116 1'0 + case + assign $1\jtag_dmi0__ack_o$next[0:0]$2116 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$2115 end - attribute \src "libresoc.v:188908.13-188908.34" - process $proc$libresoc.v:188908$14321 + attribute \src "libresoc.v:52166.3-52174.6" + process $proc$libresoc.v:52166$2117 assign { } { } - assign $0\ren_delay$18[2:0]$14322 3'000 + assign { } { } + assign $0\jtag_dmi0__dout$next[63:0]$2118 $1\jtag_dmi0__dout$next[63:0]$2119 + attribute \src "libresoc.v:52167.5-52167.29" + switch \initial + attribute \src "libresoc.v:52167.9-52167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__dout$next[63:0]$2119 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0__dout$next[63:0]$2119 \dbg_dmi_dout + end sync always - sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14322 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$2118 end - attribute \src "libresoc.v:188943.3-188944.43" - process $proc$libresoc.v:188943$14300 + attribute \src "libresoc.v:52175.3-52183.6" + process $proc$libresoc.v:52175$2120 assign { } { } - assign $0\ren_delay$18[2:0]$14301 \ren_delay$18$next - sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14301 + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$2121 $1\dec2_cur_eint$next[0:0]$2122 + attribute \src "libresoc.v:52176.5-52176.29" + switch \initial + attribute \src "libresoc.v:52176.9-52176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$2122 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$2122 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$2121 end - attribute \src "libresoc.v:188945.3-188946.43" - process $proc$libresoc.v:188945$14302 + attribute \src "libresoc.v:52184.3-52193.6" + process $proc$libresoc.v:52184$2123 assign { } { } - assign $0\ren_delay$11[2:0]$14303 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14303 + assign { } { } + assign $0\delay$next[1:0]$2124 $1\delay$next[1:0]$2125 + attribute \src "libresoc.v:52185.5-52185.29" + switch \initial + attribute \src "libresoc.v:52185.9-52185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + switch \$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$2125 \$12 [1:0] + case + assign $1\delay$next[1:0]$2125 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$2124 end - attribute \src "libresoc.v:188947.3-188948.35" - process $proc$libresoc.v:188947$14304 + attribute \src "libresoc.v:52194.3-52230.6" + process $proc$libresoc.v:52194$2126 assign { } { } - assign $0\ren_delay[2:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[2:0] + assign { } { } + assign { } { } + assign $0\raw_insn_i$next[31:0]$2127 $4\raw_insn_i$next[31:0]$2131 + attribute \src "libresoc.v:52195.5-52195.29" + switch \initial + attribute \src "libresoc.v:52195.9-52195.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\raw_insn_i$next[31:0]$2128 0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\raw_insn_i$next[31:0]$2128 $2\raw_insn_i$next[31:0]$2129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\raw_insn_i$next[31:0]$2129 \raw_insn_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\raw_insn_i$next[31:0]$2129 \dec2_raw_opcode_in + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\raw_insn_i$next[31:0]$2128 $3\raw_insn_i$next[31:0]$2130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\raw_insn_i$next[31:0]$2130 0 + case + assign $3\raw_insn_i$next[31:0]$2130 \raw_insn_i + end + case + assign $1\raw_insn_i$next[31:0]$2128 \raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\raw_insn_i$next[31:0]$2131 0 + case + assign $4\raw_insn_i$next[31:0]$2131 $1\raw_insn_i$next[31:0]$2128 + end + sync always + update \raw_insn_i$next $0\raw_insn_i$next[31:0]$2127 end - attribute \src "libresoc.v:189009.3-189017.6" - process $proc$libresoc.v:189009$14305 + attribute \src "libresoc.v:52231.3-52267.6" + process $proc$libresoc.v:52231$2132 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14306 $1\ren_delay$18$next[2:0]$14307 - attribute \src "libresoc.v:189010.5-189010.29" + assign { } { } + assign $0\bigendian_i$next[0:0]$2133 $4\bigendian_i$next[0:0]$2137 + attribute \src "libresoc.v:52232.5-52232.29" switch \initial - attribute \src "libresoc.v:189010.9-189010.17" + attribute \src "libresoc.v:52232.9-52232.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\bigendian_i$next[0:0]$2134 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\bigendian_i$next[0:0]$2134 $2\bigendian_i$next[0:0]$2135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\bigendian_i$next[0:0]$2135 \bigendian_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\bigendian_i$next[0:0]$2135 \core_bigendian_i + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\bigendian_i$next[0:0]$2134 $3\bigendian_i$next[0:0]$2136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\bigendian_i$next[0:0]$2136 1'0 + case + assign $3\bigendian_i$next[0:0]$2136 \bigendian_i + end + case + assign $1\bigendian_i$next[0:0]$2134 \bigendian_i + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14307 3'000 + assign $4\bigendian_i$next[0:0]$2137 1'0 case - assign $1\ren_delay$18$next[2:0]$14307 \src3__ren + assign $4\bigendian_i$next[0:0]$2137 $1\bigendian_i$next[0:0]$2134 end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14306 + update \bigendian_i$next $0\bigendian_i$next[0:0]$2133 end - attribute \src "libresoc.v:189018.3-189027.6" - process $proc$libresoc.v:189018$14308 + attribute \src "libresoc.v:52268.3-52283.6" + process $proc$libresoc.v:52268$2138 assign { } { } assign { } { } - assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:189019.5-189019.29" + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:52269.5-52269.29" switch \initial - attribute \src "libresoc.v:189019.9-189019.17" + attribute \src "libresoc.v:52269.9-52269.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "libresoc.v:52284.3-52308.6" + process $proc$libresoc.v:52284$2139 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:52285.5-52285.29" + switch \initial + attribute \src "libresoc.v:52285.9-52285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "libresoc.v:52309.3-52333.6" + process $proc$libresoc.v:52309$2140 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:52310.5-52310.29" + switch \initial + attribute \src "libresoc.v:52310.9-52310.17" case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 assign { } { } - assign $1\src3__data_o[1:0] \$23 + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end case - assign $1\src3__data_o[1:0] 2'00 + assign $1\imem_f_valid_i[0:0] 1'0 end sync always - update \src3__data_o $0\src3__data_o[1:0] + update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:189028.3-189036.6" - process $proc$libresoc.v:189028$14309 + attribute \src "libresoc.v:52334.3-52354.6" + process $proc$libresoc.v:52334$2141 + assign { } { } assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14310 $1\ren_delay$next[2:0]$14311 - attribute \src "libresoc.v:189029.5-189029.29" + assign $0\dec2_cur_pc$next[63:0]$2142 $3\dec2_cur_pc$next[63:0]$2145 + attribute \src "libresoc.v:52335.5-52335.29" switch \initial - attribute \src "libresoc.v:189029.9-189029.17" + attribute \src "libresoc.v:52335.9-52335.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$2143 $2\dec2_cur_pc$next[63:0]$2144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$2144 \pc + case + assign $2\dec2_cur_pc$next[63:0]$2144 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$2143 \dec2_cur_pc + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14311 3'000 + assign $3\dec2_cur_pc$next[63:0]$2145 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\ren_delay$next[2:0]$14311 \src1__ren + assign $3\dec2_cur_pc$next[63:0]$2145 $1\dec2_cur_pc$next[63:0]$2143 end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14310 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$2142 end - attribute \src "libresoc.v:189037.3-189046.6" - process $proc$libresoc.v:189037$14312 + attribute \src "libresoc.v:52355.3-52384.6" + process $proc$libresoc.v:52355$2146 assign { } { } assign { } { } - assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:189038.5-189038.29" + assign { } { } + assign $0\msr_read$next[0:0]$2147 $4\msr_read$next[0:0]$2151 + attribute \src "libresoc.v:52356.5-52356.29" switch \initial - attribute \src "libresoc.v:189038.9-189038.17" + attribute \src "libresoc.v:52356.9-52356.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$2148 $2\msr_read$next[0:0]$2149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$2149 1'0 + case + assign $2\msr_read$next[0:0]$2149 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$2148 $3\msr_read$next[0:0]$2150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$2150 1'1 + case + assign $3\msr_read$next[0:0]$2150 \msr_read + end + case + assign $1\msr_read$next[0:0]$2148 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src1__data_o[1:0] \$9 + assign $4\msr_read$next[0:0]$2151 1'1 case - assign $1\src1__data_o[1:0] 2'00 + assign $4\msr_read$next[0:0]$2151 $1\msr_read$next[0:0]$2148 end sync always - update \src1__data_o $0\src1__data_o[1:0] + update \msr_read$next $0\msr_read$next[0:0]$2147 end - attribute \src "libresoc.v:189047.3-189055.6" - process $proc$libresoc.v:189047$14313 + attribute \src "libresoc.v:52385.3-52430.6" + process $proc$libresoc.v:52385$2152 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14314 $1\ren_delay$11$next[2:0]$14315 - attribute \src "libresoc.v:189048.5-189048.29" + assign { } { } + assign $0\fsm_state$next[1:0]$2153 $5\fsm_state$next[1:0]$2158 + attribute \src "libresoc.v:52386.5-52386.29" switch \initial - attribute \src "libresoc.v:189048.9-189048.17" + attribute \src "libresoc.v:52386.9-52386.17" case 1'1 case end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$2154 $2\fsm_state$next[1:0]$2155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$2155 2'01 + case + assign $2\fsm_state$next[1:0]$2155 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$2154 $3\fsm_state$next[1:0]$2156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\fsm_state$next[1:0]$2156 \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\fsm_state$next[1:0]$2156 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$2154 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$2154 $4\fsm_state$next[1:0]$2157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$2157 2'00 + case + assign $4\fsm_state$next[1:0]$2157 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$2154 \fsm_state + end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" - switch \coresync_rst + switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14315 3'000 + assign $5\fsm_state$next[1:0]$2158 2'00 + case + assign $5\fsm_state$next[1:0]$2158 $1\fsm_state$next[1:0]$2154 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$2153 + end + attribute \src "libresoc.v:52431.3-52449.6" + process $proc$libresoc.v:52431$2159 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:52432.5-52432.29" + switch \initial + attribute \src "libresoc.v:52432.9-52432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end case - assign $1\ren_delay$11$next[2:0]$14315 \src2__ren + assign $1\core_stopped_i[0:0] 1'0 end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14314 + update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:189056.3-189065.6" - process $proc$libresoc.v:189056$14316 + attribute \src "libresoc.v:52450.3-52468.6" + process $proc$libresoc.v:52450$2160 assign { } { } assign { } { } - assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:189057.5-189057.29" + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:52451.5-52451.29" switch \initial - attribute \src "libresoc.v:189057.9-189057.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch \$12 - attribute \src "libresoc.v:0.0-0.0" - case 1'1 - assign { } { } - assign $1\src2__data_o[1:0] \$16 - case - assign $1\src2__data_o[1:0] 2'00 - end - sync always - update \src2__data_o $0\src2__data_o[1:0] - end - connect \$9 $or$libresoc.v:188934$14291_Y - connect \$12 $reduce_or$libresoc.v:188935$14292_Y - connect \$14 $or$libresoc.v:188936$14293_Y - connect \$16 $or$libresoc.v:188937$14294_Y - connect \$19 $reduce_or$libresoc.v:188938$14295_Y - connect \$21 $or$libresoc.v:188939$14296_Y - connect \$23 $or$libresoc.v:188940$14297_Y - connect \$5 $reduce_or$libresoc.v:188941$14298_Y - connect \$7 $or$libresoc.v:188942$14299_Y - connect \full_wr__data_i 6'000000 - connect \full_wr__wen 3'000 - connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 - connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 - connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } - connect \reg_2_dest32__data_i \data_i$1 - connect \reg_1_dest31__data_i \data_i$1 - connect \reg_0_dest30__data_i \data_i$1 - connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 - connect \reg_2_dest22__data_i \data_i - connect \reg_1_dest21__data_i \data_i - connect \reg_0_dest20__data_i \data_i - connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen - connect \reg_2_dest12__data_i \data_i$3 - connect \reg_1_dest11__data_i \data_i$3 - connect \reg_0_dest10__data_i \data_i$3 - connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 - connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren - connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren - connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren + attribute \src "libresoc.v:52451.9-52451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:245" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + connect \$99 $and$libresoc.v:50779$1603_Y + connect \$101 $not$libresoc.v:50780$1604_Y + connect \$103 $not$libresoc.v:50781$1605_Y + connect \$105 $not$libresoc.v:50782$1606_Y + connect \$107 $and$libresoc.v:50783$1607_Y + connect \$10 $ne$libresoc.v:50784$1608_Y + connect \$109 $not$libresoc.v:50785$1609_Y + connect \$111 $not$libresoc.v:50786$1610_Y + connect \$113 $and$libresoc.v:50787$1611_Y + connect \$115 $not$libresoc.v:50788$1612_Y + connect \$118 $mul$libresoc.v:50789$1613_Y + connect \$117 $shr$libresoc.v:50790$1614_Y [31:0] + connect \$122 $mul$libresoc.v:50791$1615_Y + connect \$121 $shr$libresoc.v:50792$1616_Y [31:0] + connect \$125 $ne$libresoc.v:50793$1617_Y + connect \$127 $pos$libresoc.v:50794$1619_Y + connect \$129 $pos$libresoc.v:50795$1621_Y + connect \$133 $sub$libresoc.v:50796$1622_Y + connect \$137 $add$libresoc.v:50797$1623_Y + connect \$13 $sub$libresoc.v:50798$1624_Y + connect \$15 $or$libresoc.v:50799$1625_Y + connect \$17 $or$libresoc.v:50800$1626_Y + connect \$19 $ne$libresoc.v:50801$1627_Y + connect \$21 $not$libresoc.v:50802$1628_Y + connect \$23 $and$libresoc.v:50803$1629_Y + connect \$26 $add$libresoc.v:50804$1630_Y + connect \$28 $not$libresoc.v:50805$1631_Y + connect \$30 $not$libresoc.v:50806$1632_Y + connect \$32 $not$libresoc.v:50807$1633_Y + connect \$34 $not$libresoc.v:50808$1634_Y + connect \$36 $not$libresoc.v:50809$1635_Y + connect \$38 $not$libresoc.v:50810$1636_Y + connect \$40 $not$libresoc.v:50811$1637_Y + connect \$42 $and$libresoc.v:50812$1638_Y + connect \$45 $and$libresoc.v:50813$1639_Y + connect \$44 $reduce_or$libresoc.v:50814$1640_Y + connect \$57 $not$libresoc.v:50815$1641_Y + connect \$59 $not$libresoc.v:50816$1642_Y + connect \$61 $not$libresoc.v:50817$1643_Y + connect \$63 $not$libresoc.v:50818$1644_Y + connect \$65 $not$libresoc.v:50819$1645_Y + connect \$67 $and$libresoc.v:50820$1646_Y + connect \$69 $not$libresoc.v:50821$1647_Y + connect \$71 $not$libresoc.v:50822$1648_Y + connect \$73 $and$libresoc.v:50823$1649_Y + connect \$75 $not$libresoc.v:50824$1650_Y + connect \$77 $not$libresoc.v:50825$1651_Y + connect \$79 $and$libresoc.v:50826$1652_Y + connect \$81 $not$libresoc.v:50827$1653_Y + connect \$83 $not$libresoc.v:50828$1654_Y + connect \$85 $and$libresoc.v:50829$1655_Y + connect \$87 $not$libresoc.v:50830$1656_Y + connect \$89 $not$libresoc.v:50831$1657_Y + connect \$91 $and$libresoc.v:50832$1658_Y + connect \$93 $not$libresoc.v:50833$1659_Y + connect \$95 $not$libresoc.v:50834$1660_Y + connect \$97 $not$libresoc.v:50835$1661_Y + connect \$12 \$13 + connect \$25 \$26 + connect \$132 \$133 + connect \$136 \$137 + connect \corebusy_o 1'0 + connect \cu_st__rel_o 1'0 + connect \cu_ad__rel_o 1'0 + connect \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \core_terminate_o 1'0 + connect \state_nia_wen 4'0000 + connect \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \full_rd2__data_o 0 + connect \full_rd__data_o 6'000000 + connect \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i 1'0 + connect \nia \$26 [63:0] + connect \pc_o \dec2_cur_pc + connect \cu_st__go_i \cu_st__rel_o_rise + connect \cu_ad__go_i 1'0 + connect \cu_st__rel_o_rise \$23 + connect \cu_st__rel_o_dly$next 1'0 + connect \dec2_bigendian \core_bigendian_i + connect \busy_o 1'0 + connect \core_coresync_rst \ti_rst + connect \ti_rst \$19 + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } end -attribute \src "libresoc.v:189091.1-189405.10" +attribute \src "libresoc.v:52503.1-52817.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:189269.3-189297.6" + attribute \src "libresoc.v:52681.3-52709.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:189320.3-189328.6" - wire $0\core_irq_o$next[0:0]$14358 - attribute \src "libresoc.v:189211.3-189212.37" + attribute \src "libresoc.v:52732.3-52740.6" + wire $0\core_irq_o$next[0:0]$2294 + attribute \src "libresoc.v:52623.3-52624.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $0\cppr$10[7:0]$14362 - attribute \src "libresoc.v:189225.3-189240.6" - wire width 8 $0\cppr$next[7:0]$14341 - attribute \src "libresoc.v:189215.3-189216.25" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $0\cppr$10[7:0]$2298 + attribute \src "libresoc.v:52637.3-52652.6" + wire width 8 $0\cppr$next[7:0]$2277 + attribute \src "libresoc.v:52627.3-52628.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:189329.3-189338.6" + attribute \src "libresoc.v:52741.3-52750.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:189092.7-189092.20" + attribute \src "libresoc.v:52504.7-52504.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire $0\irq$12[0:0]$14363 - attribute \src "libresoc.v:189225.3-189240.6" - wire $0\irq$next[0:0]$14342 - attribute \src "libresoc.v:189219.3-189220.23" + attribute \src "libresoc.v:52751.3-52813.6" + wire $0\irq$12[0:0]$2299 + attribute \src "libresoc.v:52637.3-52652.6" + wire $0\irq$next[0:0]$2278 + attribute \src "libresoc.v:52631.3-52632.23" wire $0\irq[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $0\mfrr$11[7:0]$14364 - attribute \src "libresoc.v:189225.3-189240.6" - wire width 8 $0\mfrr$next[7:0]$14343 - attribute \src "libresoc.v:189217.3-189218.25" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $0\mfrr$11[7:0]$2300 + attribute \src "libresoc.v:52637.3-52652.6" + wire width 8 $0\mfrr$next[7:0]$2279 + attribute \src "libresoc.v:52629.3-52630.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:189308.3-189319.6" + attribute \src "libresoc.v:52720.3-52731.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:189298.3-189307.6" + attribute \src "libresoc.v:52710.3-52719.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire $0\wb_ack$14[0:0]$14365 - attribute \src "libresoc.v:189225.3-189240.6" - wire $0\wb_ack$next[0:0]$14344 - attribute \src "libresoc.v:189223.3-189224.29" + attribute \src "libresoc.v:52751.3-52813.6" + wire $0\wb_ack$14[0:0]$2301 + attribute \src "libresoc.v:52637.3-52652.6" + wire $0\wb_ack$next[0:0]$2280 + attribute \src "libresoc.v:52635.3-52636.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 32 $0\wb_rd_data$13[31:0]$14366 - attribute \src "libresoc.v:189225.3-189240.6" - wire width 32 $0\wb_rd_data$next[31:0]$14345 - attribute \src "libresoc.v:189221.3-189222.37" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 32 $0\wb_rd_data$13[31:0]$2302 + attribute \src "libresoc.v:52637.3-52652.6" + wire width 32 $0\wb_rd_data$next[31:0]$2281 + attribute \src "libresoc.v:52633.3-52634.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:189241.3-189268.6" + attribute \src "libresoc.v:52653.3-52680.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 24 $0\xisr$9[23:0]$14367 - attribute \src "libresoc.v:189225.3-189240.6" - wire width 24 $0\xisr$next[23:0]$14346 - attribute \src "libresoc.v:189213.3-189214.25" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 24 $0\xisr$9[23:0]$2303 + attribute \src "libresoc.v:52637.3-52652.6" + wire width 24 $0\xisr$next[23:0]$2282 + attribute \src "libresoc.v:52625.3-52626.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:189269.3-189297.6" + attribute \src "libresoc.v:52681.3-52709.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:189320.3-189328.6" - wire $1\core_irq_o$next[0:0]$14359 - attribute \src "libresoc.v:189121.7-189121.24" + attribute \src "libresoc.v:52732.3-52740.6" + wire $1\core_irq_o$next[0:0]$2295 + attribute \src "libresoc.v:52533.7-52533.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $1\cppr$10[7:0]$14368 - attribute \src "libresoc.v:189225.3-189240.6" - wire width 8 $1\cppr$next[7:0]$14347 - attribute \src "libresoc.v:189125.13-189125.25" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $1\cppr$10[7:0]$2304 + attribute \src "libresoc.v:52637.3-52652.6" + wire width 8 $1\cppr$next[7:0]$2283 + attribute \src "libresoc.v:52537.13-52537.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:189329.3-189338.6" + attribute \src "libresoc.v:52741.3-52750.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire $1\irq$12[0:0]$14378 - attribute \src "libresoc.v:189225.3-189240.6" - wire $1\irq$next[0:0]$14348 - attribute \src "libresoc.v:189154.7-189154.17" + attribute \src "libresoc.v:52751.3-52813.6" + wire $1\irq$12[0:0]$2314 + attribute \src "libresoc.v:52637.3-52652.6" + wire $1\irq$next[0:0]$2284 + attribute \src "libresoc.v:52566.7-52566.17" wire $1\irq[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $1\mfrr$11[7:0]$14369 - attribute \src "libresoc.v:189225.3-189240.6" - wire width 8 $1\mfrr$next[7:0]$14349 - attribute \src "libresoc.v:189162.13-189162.25" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $1\mfrr$11[7:0]$2305 + attribute \src "libresoc.v:52637.3-52652.6" + wire width 8 $1\mfrr$next[7:0]$2285 + attribute \src "libresoc.v:52574.13-52574.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:189308.3-189319.6" + attribute \src "libresoc.v:52720.3-52731.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:189298.3-189307.6" + attribute \src "libresoc.v:52710.3-52719.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire $1\wb_ack$14[0:0]$14370 - attribute \src "libresoc.v:189225.3-189240.6" - wire $1\wb_ack$next[0:0]$14350 - attribute \src "libresoc.v:189176.7-189176.20" + attribute \src "libresoc.v:52751.3-52813.6" + wire $1\wb_ack$14[0:0]$2306 + attribute \src "libresoc.v:52637.3-52652.6" + wire $1\wb_ack$next[0:0]$2286 + attribute \src "libresoc.v:52588.7-52588.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:189225.3-189240.6" - wire width 32 $1\wb_rd_data$next[31:0]$14351 - attribute \src "libresoc.v:189184.14-189184.32" + attribute \src "libresoc.v:52637.3-52652.6" + wire width 32 $1\wb_rd_data$next[31:0]$2287 + attribute \src "libresoc.v:52596.14-52596.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:189241.3-189268.6" + attribute \src "libresoc.v:52653.3-52680.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 24 $1\xisr$9[23:0]$14375 - attribute \src "libresoc.v:189225.3-189240.6" - wire width 24 $1\xisr$next[23:0]$14352 - attribute \src "libresoc.v:189194.14-189194.31" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 24 $1\xisr$9[23:0]$2311 + attribute \src "libresoc.v:52637.3-52652.6" + wire width 24 $1\xisr$next[23:0]$2288 + attribute \src "libresoc.v:52606.14-52606.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:189269.3-189297.6" + attribute \src "libresoc.v:52681.3-52709.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $2\cppr$10[7:0]$14371 - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $2\mfrr$11[7:0]$14372 - attribute \src "libresoc.v:189241.3-189268.6" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $2\cppr$10[7:0]$2307 + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $2\mfrr$11[7:0]$2308 + attribute \src "libresoc.v:52653.3-52680.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 24 $2\xisr$9[23:0]$14376 - attribute \src "libresoc.v:189269.3-189297.6" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 24 $2\xisr$9[23:0]$2312 + attribute \src "libresoc.v:52681.3-52709.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $3\cppr$10[7:0]$14373 - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $3\mfrr$11[7:0]$14374 - attribute \src "libresoc.v:189241.3-189268.6" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $3\cppr$10[7:0]$2309 + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $3\mfrr$11[7:0]$2310 + attribute \src "libresoc.v:52653.3-52680.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189339.3-189401.6" - wire width 8 $4\cppr$10[7:0]$14377 - attribute \src "libresoc.v:189241.3-189268.6" + attribute \src "libresoc.v:52751.3-52813.6" + wire width 8 $4\cppr$10[7:0]$2313 + attribute \src "libresoc.v:52653.3-52680.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189201.18-189201.116" - wire $and$libresoc.v:189201$14323_Y - attribute \src "libresoc.v:189205.18-189205.116" - wire $and$libresoc.v:189205$14327_Y - attribute \src "libresoc.v:189207.18-189207.116" - wire $and$libresoc.v:189207$14329_Y - attribute \src "libresoc.v:189210.17-189210.109" - wire $and$libresoc.v:189210$14332_Y - attribute \src "libresoc.v:189206.18-189206.110" - wire $eq$libresoc.v:189206$14328_Y - attribute \src "libresoc.v:189203.18-189203.114" - wire $lt$libresoc.v:189203$14325_Y - attribute \src "libresoc.v:189204.18-189204.109" - wire $lt$libresoc.v:189204$14326_Y - attribute \src "libresoc.v:189209.18-189209.114" - wire $lt$libresoc.v:189209$14331_Y - attribute \src "libresoc.v:189202.18-189202.109" - wire $ne$libresoc.v:189202$14324_Y - attribute \src "libresoc.v:189208.18-189208.109" - wire $ne$libresoc.v:189208$14330_Y + attribute \src "libresoc.v:52613.18-52613.116" + wire $and$libresoc.v:52613$2259_Y + attribute \src "libresoc.v:52617.18-52617.116" + wire $and$libresoc.v:52617$2263_Y + attribute \src "libresoc.v:52619.18-52619.116" + wire $and$libresoc.v:52619$2265_Y + attribute \src "libresoc.v:52622.17-52622.109" + wire $and$libresoc.v:52622$2268_Y + attribute \src "libresoc.v:52618.18-52618.110" + wire $eq$libresoc.v:52618$2264_Y + attribute \src "libresoc.v:52615.18-52615.114" + wire $lt$libresoc.v:52615$2261_Y + attribute \src "libresoc.v:52616.18-52616.109" + wire $lt$libresoc.v:52616$2262_Y + attribute \src "libresoc.v:52621.18-52621.114" + wire $lt$libresoc.v:52621$2267_Y + attribute \src "libresoc.v:52614.18-52614.109" + wire $ne$libresoc.v:52614$2260_Y + attribute \src "libresoc.v:52620.18-52620.109" + wire $ne$libresoc.v:52620$2266_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -397792,7 +146755,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 4 \core_irq_o @@ -397826,7 +146789,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:189092.7-189092.15" + attribute \src "libresoc.v:52504.7-52504.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -397848,7 +146811,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -397877,7 +146840,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:189201$14323 + cell $and $and$libresoc.v:52613$2259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -397885,10 +146848,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:189201$14323_Y + connect \Y $and$libresoc.v:52613$2259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:189205$14327 + cell $and $and$libresoc.v:52617$2263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -397896,10 +146859,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:189205$14327_Y + connect \Y $and$libresoc.v:52617$2263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:189207$14329 + cell $and $and$libresoc.v:52619$2265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -397907,10 +146870,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:189207$14329_Y + connect \Y $and$libresoc.v:52619$2265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:189210$14332 + cell $and $and$libresoc.v:52622$2268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -397918,10 +146881,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:189210$14332_Y + connect \Y $and$libresoc.v:52622$2268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:189206$14328 + cell $eq $eq$libresoc.v:52618$2264 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397929,10 +146892,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:189206$14328_Y + connect \Y $eq$libresoc.v:52618$2264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:189203$14325 + cell $lt $lt$libresoc.v:52615$2261 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -397940,10 +146903,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:189203$14325_Y + connect \Y $lt$libresoc.v:52615$2261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:189204$14326 + cell $lt $lt$libresoc.v:52616$2262 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -397951,10 +146914,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:189204$14326_Y + connect \Y $lt$libresoc.v:52616$2262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:189209$14331 + cell $lt $lt$libresoc.v:52621$2267 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -397962,10 +146925,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:189209$14331_Y + connect \Y $lt$libresoc.v:52621$2267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:189202$14324 + cell $ne $ne$libresoc.v:52614$2260 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -397973,10 +146936,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:189202$14324_Y + connect \Y $ne$libresoc.v:52614$2260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:189208$14330 + cell $ne $ne$libresoc.v:52620$2266 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -397984,123 +146947,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:189208$14330_Y + connect \Y $ne$libresoc.v:52620$2266_Y end - attribute \src "libresoc.v:189092.7-189092.20" - process $proc$libresoc.v:189092$14379 + attribute \src "libresoc.v:52504.7-52504.20" + process $proc$libresoc.v:52504$2315 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189121.7-189121.24" - process $proc$libresoc.v:189121$14380 + attribute \src "libresoc.v:52533.7-52533.24" + process $proc$libresoc.v:52533$2316 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:189125.13-189125.25" - process $proc$libresoc.v:189125$14381 + attribute \src "libresoc.v:52537.13-52537.25" + process $proc$libresoc.v:52537$2317 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:189154.7-189154.17" - process $proc$libresoc.v:189154$14382 + attribute \src "libresoc.v:52566.7-52566.17" + process $proc$libresoc.v:52566$2318 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:189162.13-189162.25" - process $proc$libresoc.v:189162$14383 + attribute \src "libresoc.v:52574.13-52574.25" + process $proc$libresoc.v:52574$2319 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:189176.7-189176.20" - process $proc$libresoc.v:189176$14384 + attribute \src "libresoc.v:52588.7-52588.20" + process $proc$libresoc.v:52588$2320 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:189184.14-189184.32" - process $proc$libresoc.v:189184$14385 + attribute \src "libresoc.v:52596.14-52596.32" + process $proc$libresoc.v:52596$2321 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:189194.14-189194.31" - process $proc$libresoc.v:189194$14386 + attribute \src "libresoc.v:52606.14-52606.31" + process $proc$libresoc.v:52606$2322 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:189211.3-189212.37" - process $proc$libresoc.v:189211$14333 + attribute \src "libresoc.v:52623.3-52624.37" + process $proc$libresoc.v:52623$2269 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:189213.3-189214.25" - process $proc$libresoc.v:189213$14334 + attribute \src "libresoc.v:52625.3-52626.25" + process $proc$libresoc.v:52625$2270 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:189215.3-189216.25" - process $proc$libresoc.v:189215$14335 + attribute \src "libresoc.v:52627.3-52628.25" + process $proc$libresoc.v:52627$2271 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:189217.3-189218.25" - process $proc$libresoc.v:189217$14336 + attribute \src "libresoc.v:52629.3-52630.25" + process $proc$libresoc.v:52629$2272 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:189219.3-189220.23" - process $proc$libresoc.v:189219$14337 + attribute \src "libresoc.v:52631.3-52632.23" + process $proc$libresoc.v:52631$2273 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:189221.3-189222.37" - process $proc$libresoc.v:189221$14338 + attribute \src "libresoc.v:52633.3-52634.37" + process $proc$libresoc.v:52633$2274 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:189223.3-189224.29" - process $proc$libresoc.v:189223$14339 + attribute \src "libresoc.v:52635.3-52636.29" + process $proc$libresoc.v:52635$2275 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:189225.3-189240.6" - process $proc$libresoc.v:189225$14340 + attribute \src "libresoc.v:52637.3-52652.6" + process $proc$libresoc.v:52637$2276 assign { } { } assign { } { } assign { } { } @@ -398108,15 +147071,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14341 $1\cppr$next[7:0]$14347 - assign $0\irq$next[0:0]$14342 $1\irq$next[0:0]$14348 - assign $0\mfrr$next[7:0]$14343 $1\mfrr$next[7:0]$14349 - assign $0\wb_ack$next[0:0]$14344 $1\wb_ack$next[0:0]$14350 - assign $0\wb_rd_data$next[31:0]$14345 $1\wb_rd_data$next[31:0]$14351 - assign $0\xisr$next[23:0]$14346 $1\xisr$next[23:0]$14352 - attribute \src "libresoc.v:189226.5-189226.29" + assign $0\cppr$next[7:0]$2277 $1\cppr$next[7:0]$2283 + assign $0\irq$next[0:0]$2278 $1\irq$next[0:0]$2284 + assign $0\mfrr$next[7:0]$2279 $1\mfrr$next[7:0]$2285 + assign $0\wb_ack$next[0:0]$2280 $1\wb_ack$next[0:0]$2286 + assign $0\wb_rd_data$next[31:0]$2281 $1\wb_rd_data$next[31:0]$2287 + assign $0\xisr$next[23:0]$2282 $1\xisr$next[23:0]$2288 + attribute \src "libresoc.v:52638.5-52638.29" switch \initial - attribute \src "libresoc.v:189226.9-189226.17" + attribute \src "libresoc.v:52638.9-52638.17" case 1'1 case end @@ -398130,36 +147093,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14352 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14347 8'00000000 - assign $1\mfrr$next[7:0]$14349 8'11111111 - assign $1\irq$next[0:0]$14348 1'0 - assign $1\wb_rd_data$next[31:0]$14351 0 - assign $1\wb_ack$next[0:0]$14350 1'0 + assign $1\xisr$next[23:0]$2288 24'000000000000000000000000 + assign $1\cppr$next[7:0]$2283 8'00000000 + assign $1\mfrr$next[7:0]$2285 8'11111111 + assign $1\irq$next[0:0]$2284 1'0 + assign $1\wb_rd_data$next[31:0]$2287 0 + assign $1\wb_ack$next[0:0]$2286 1'0 case - assign $1\cppr$next[7:0]$14347 \cppr$2 - assign $1\irq$next[0:0]$14348 \irq$4 - assign $1\mfrr$next[7:0]$14349 \mfrr$3 - assign $1\wb_ack$next[0:0]$14350 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14351 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14352 \xisr$1 + assign $1\cppr$next[7:0]$2283 \cppr$2 + assign $1\irq$next[0:0]$2284 \irq$4 + assign $1\mfrr$next[7:0]$2285 \mfrr$3 + assign $1\wb_ack$next[0:0]$2286 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$2287 \wb_rd_data$5 + assign $1\xisr$next[23:0]$2288 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14341 - update \irq$next $0\irq$next[0:0]$14342 - update \mfrr$next $0\mfrr$next[7:0]$14343 - update \wb_ack$next $0\wb_ack$next[0:0]$14344 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14345 - update \xisr$next $0\xisr$next[23:0]$14346 + update \cppr$next $0\cppr$next[7:0]$2277 + update \irq$next $0\irq$next[0:0]$2278 + update \mfrr$next $0\mfrr$next[7:0]$2279 + update \wb_ack$next $0\wb_ack$next[0:0]$2280 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2281 + update \xisr$next $0\xisr$next[23:0]$2282 end - attribute \src "libresoc.v:189241.3-189268.6" - process $proc$libresoc.v:189241$14353 + attribute \src "libresoc.v:52653.3-52680.6" + process $proc$libresoc.v:52653$2289 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:189242.5-189242.29" + attribute \src "libresoc.v:52654.5-52654.29" switch \initial - attribute \src "libresoc.v:189242.9-189242.17" + attribute \src "libresoc.v:52654.9-52654.17" case 1'1 case end @@ -398203,14 +147166,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:189269.3-189297.6" - process $proc$libresoc.v:189269$14354 + attribute \src "libresoc.v:52681.3-52709.6" + process $proc$libresoc.v:52681$2290 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:189270.5-189270.29" + attribute \src "libresoc.v:52682.5-52682.29" switch \initial - attribute \src "libresoc.v:189270.9-189270.17" + attribute \src "libresoc.v:52682.9-52682.17" case 1'1 case end @@ -398253,14 +147216,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:189298.3-189307.6" - process $proc$libresoc.v:189298$14355 + attribute \src "libresoc.v:52710.3-52719.6" + process $proc$libresoc.v:52710$2291 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:189299.5-189299.29" + attribute \src "libresoc.v:52711.5-52711.29" switch \initial - attribute \src "libresoc.v:189299.9-189299.17" + attribute \src "libresoc.v:52711.9-52711.17" case 1'1 case end @@ -398276,13 +147239,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:189308.3-189319.6" - process $proc$libresoc.v:189308$14356 + attribute \src "libresoc.v:52720.3-52731.6" + process $proc$libresoc.v:52720$2292 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:189309.5-189309.29" + attribute \src "libresoc.v:52721.5-52721.29" switch \initial - attribute \src "libresoc.v:189309.9-189309.17" + attribute \src "libresoc.v:52721.9-52721.17" case 1'1 case end @@ -398300,14 +147263,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:189320.3-189328.6" - process $proc$libresoc.v:189320$14357 + attribute \src "libresoc.v:52732.3-52740.6" + process $proc$libresoc.v:52732$2293 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14358 $1\core_irq_o$next[0:0]$14359 - attribute \src "libresoc.v:189321.5-189321.29" + assign $0\core_irq_o$next[0:0]$2294 $1\core_irq_o$next[0:0]$2295 + attribute \src "libresoc.v:52733.5-52733.29" switch \initial - attribute \src "libresoc.v:189321.9-189321.17" + attribute \src "libresoc.v:52733.9-52733.17" case 1'1 case end @@ -398316,21 +147279,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14359 1'0 + assign $1\core_irq_o$next[0:0]$2295 1'0 case - assign $1\core_irq_o$next[0:0]$14359 \irq + assign $1\core_irq_o$next[0:0]$2295 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14358 + update \core_irq_o$next $0\core_irq_o$next[0:0]$2294 end - attribute \src "libresoc.v:189329.3-189338.6" - process $proc$libresoc.v:189329$14360 + attribute \src "libresoc.v:52741.3-52750.6" + process $proc$libresoc.v:52741$2296 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:189330.5-189330.29" + attribute \src "libresoc.v:52742.5-52742.29" switch \initial - attribute \src "libresoc.v:189330.9-189330.17" + attribute \src "libresoc.v:52742.9-52742.17" case 1'1 case end @@ -398346,8 +147309,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:189339.3-189401.6" - process $proc$libresoc.v:189339$14361 + attribute \src "libresoc.v:52751.3-52813.6" + process $proc$libresoc.v:52751$2297 assign { } { } assign { } { } assign { } { } @@ -398357,18 +147320,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14364 $1\mfrr$11[7:0]$14369 - assign $0\wb_ack$14[0:0]$14365 $1\wb_ack$14[0:0]$14370 + assign $0\mfrr$11[7:0]$2300 $1\mfrr$11[7:0]$2305 + assign $0\wb_ack$14[0:0]$2301 $1\wb_ack$14[0:0]$2306 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14367 $2\xisr$9[23:0]$14376 - assign $0\cppr$10[7:0]$14362 $4\cppr$10[7:0]$14377 - assign $0\wb_rd_data$13[31:0]$14366 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14363 $1\irq$12[0:0]$14378 - attribute \src "libresoc.v:189340.5-189340.29" + assign $0\xisr$9[23:0]$2303 $2\xisr$9[23:0]$2312 + assign $0\cppr$10[7:0]$2298 $4\cppr$10[7:0]$2313 + assign $0\wb_rd_data$13[31:0]$2302 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$2299 $1\irq$12[0:0]$2314 + attribute \src "libresoc.v:52752.5-52752.29" switch \initial - attribute \src "libresoc.v:189340.9-189340.17" + attribute \src "libresoc.v:52752.9-52752.17" case 1'1 case end @@ -398379,712 +147342,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14370 1'1 - assign $1\cppr$10[7:0]$14368 $2\cppr$10[7:0]$14371 - assign $1\mfrr$11[7:0]$14369 $2\mfrr$11[7:0]$14372 + assign $1\wb_ack$14[0:0]$2306 1'1 + assign $1\cppr$10[7:0]$2304 $2\cppr$10[7:0]$2307 + assign $1\mfrr$11[7:0]$2305 $2\mfrr$11[7:0]$2308 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14371 $3\cppr$10[7:0]$14373 - assign $2\mfrr$11[7:0]$14372 $3\mfrr$11[7:0]$14374 + assign $2\cppr$10[7:0]$2307 $3\cppr$10[7:0]$2309 + assign $2\mfrr$11[7:0]$2308 $3\mfrr$11[7:0]$2310 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14374 \mfrr - assign $3\cppr$10[7:0]$14373 \be_in [31:24] + assign $3\mfrr$11[7:0]$2310 \mfrr + assign $3\cppr$10[7:0]$2309 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14374 \mfrr - assign $3\cppr$10[7:0]$14373 \be_in [31:24] + assign $3\mfrr$11[7:0]$2310 \mfrr + assign $3\cppr$10[7:0]$2309 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14373 \cppr + assign $3\cppr$10[7:0]$2309 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14374 \be_in [31:24] + assign $3\mfrr$11[7:0]$2310 \be_in [31:24] case - assign $3\cppr$10[7:0]$14373 \cppr - assign $3\mfrr$11[7:0]$14374 \mfrr + assign $3\cppr$10[7:0]$2309 \cppr + assign $3\mfrr$11[7:0]$2310 \mfrr end case - assign $2\cppr$10[7:0]$14371 \cppr - assign $2\mfrr$11[7:0]$14372 \mfrr + assign $2\cppr$10[7:0]$2307 \cppr + assign $2\mfrr$11[7:0]$2308 \mfrr end case - assign $1\cppr$10[7:0]$14368 \cppr - assign $1\mfrr$11[7:0]$14369 \mfrr - assign $1\wb_ack$14[0:0]$14370 1'0 + assign $1\cppr$10[7:0]$2304 \cppr + assign $1\mfrr$11[7:0]$2305 \mfrr + assign $1\wb_ack$14[0:0]$2306 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14375 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$2311 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14375 24'000000000000000000000000 + assign $1\xisr$9[23:0]$2311 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14376 24'000000000000000000000010 + assign $2\xisr$9[23:0]$2312 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14376 $1\xisr$9[23:0]$14375 + assign $2\xisr$9[23:0]$2312 $1\xisr$9[23:0]$2311 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14377 \min_pri + assign $4\cppr$10[7:0]$2313 \min_pri case - assign $4\cppr$10[7:0]$14377 $1\cppr$10[7:0]$14368 + assign $4\cppr$10[7:0]$2313 $1\cppr$10[7:0]$2304 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14378 1'1 + assign $1\irq$12[0:0]$2314 1'1 case - assign $1\irq$12[0:0]$14378 1'0 + assign $1\irq$12[0:0]$2314 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14362 - update \irq$12 $0\irq$12[0:0]$14363 - update \mfrr$11 $0\mfrr$11[7:0]$14364 - update \wb_ack$14 $0\wb_ack$14[0:0]$14365 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14366 - update \xisr$9 $0\xisr$9[23:0]$14367 + update \cppr$10 $0\cppr$10[7:0]$2298 + update \irq$12 $0\irq$12[0:0]$2299 + update \mfrr$11 $0\mfrr$11[7:0]$2300 + update \wb_ack$14 $0\wb_ack$14[0:0]$2301 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2302 + update \xisr$9 $0\xisr$9[23:0]$2303 end - connect \$15 $and$libresoc.v:189201$14323_Y - connect \$17 $ne$libresoc.v:189202$14324_Y - connect \$19 $lt$libresoc.v:189203$14325_Y - connect \$21 $lt$libresoc.v:189204$14326_Y - connect \$23 $and$libresoc.v:189205$14327_Y - connect \$25 $eq$libresoc.v:189206$14328_Y - connect \$27 $and$libresoc.v:189207$14329_Y - connect \$29 $ne$libresoc.v:189208$14330_Y - connect \$31 $lt$libresoc.v:189209$14331_Y - connect \$7 $and$libresoc.v:189210$14332_Y + connect \$15 $and$libresoc.v:52613$2259_Y + connect \$17 $ne$libresoc.v:52614$2260_Y + connect \$19 $lt$libresoc.v:52615$2261_Y + connect \$21 $lt$libresoc.v:52616$2262_Y + connect \$23 $and$libresoc.v:52617$2263_Y + connect \$25 $eq$libresoc.v:52618$2264_Y + connect \$27 $and$libresoc.v:52619$2265_Y + connect \$29 $ne$libresoc.v:52620$2266_Y + connect \$31 $lt$libresoc.v:52621$2267_Y + connect \$7 $and$libresoc.v:52622$2268_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:189409.1-190458.10" +attribute \src "libresoc.v:52821.1-53870.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:190339.3-190388.6" + attribute \src "libresoc.v:53751.3-53800.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:190050.3-190059.6" + attribute \src "libresoc.v:53462.3-53471.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:190259.3-190268.6" + attribute \src "libresoc.v:53671.3-53680.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:190279.3-190288.6" + attribute \src "libresoc.v:53691.3-53700.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:190299.3-190308.6" + attribute \src "libresoc.v:53711.3-53720.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:190319.3-190328.6" + attribute \src "libresoc.v:53731.3-53740.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:190389.3-190398.6" + attribute \src "libresoc.v:53801.3-53810.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:190409.3-190418.6" + attribute \src "libresoc.v:53821.3-53830.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:190070.3-190079.6" + attribute \src "libresoc.v:53482.3-53491.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:190090.3-190099.6" + attribute \src "libresoc.v:53502.3-53511.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:190110.3-190119.6" + attribute \src "libresoc.v:53522.3-53531.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:190139.3-190148.6" + attribute \src "libresoc.v:53551.3-53560.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:190159.3-190168.6" + attribute \src "libresoc.v:53571.3-53580.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:190179.3-190188.6" + attribute \src "libresoc.v:53591.3-53600.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:190199.3-190208.6" + attribute \src "libresoc.v:53611.3-53620.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:190219.3-190228.6" + attribute \src "libresoc.v:53631.3-53640.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:190239.3-190248.6" + attribute \src "libresoc.v:53651.3-53660.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:190040.3-190049.6" + attribute \src "libresoc.v:53452.3-53461.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:190249.3-190258.6" + attribute \src "libresoc.v:53661.3-53670.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:190269.3-190278.6" + attribute \src "libresoc.v:53681.3-53690.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:190289.3-190298.6" + attribute \src "libresoc.v:53701.3-53710.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:190309.3-190318.6" + attribute \src "libresoc.v:53721.3-53730.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:190329.3-190338.6" + attribute \src "libresoc.v:53741.3-53750.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:190399.3-190408.6" + attribute \src "libresoc.v:53811.3-53820.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:190060.3-190069.6" + attribute \src "libresoc.v:53472.3-53481.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:190080.3-190089.6" + attribute \src "libresoc.v:53492.3-53501.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:190100.3-190109.6" + attribute \src "libresoc.v:53512.3-53521.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:190120.3-190129.6" + attribute \src "libresoc.v:53532.3-53541.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:190149.3-190158.6" + attribute \src "libresoc.v:53561.3-53570.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:190169.3-190178.6" + attribute \src "libresoc.v:53581.3-53590.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:190189.3-190198.6" + attribute \src "libresoc.v:53601.3-53610.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:190209.3-190218.6" + attribute \src "libresoc.v:53621.3-53630.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:190229.3-190238.6" + attribute \src "libresoc.v:53641.3-53650.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:190419.3-190428.6" + attribute \src "libresoc.v:53831.3-53840.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:189940.3-189941.25" + attribute \src "libresoc.v:53342.3-53343.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:189938.3-189939.28" + attribute \src "libresoc.v:53340.3-53341.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:190438.3-190446.6" - wire $0\ics_wb__ack$next[0:0]$14633 - attribute \src "libresoc.v:189932.3-189933.39" + attribute \src "libresoc.v:53850.3-53858.6" + wire $0\ics_wb__ack$next[0:0]$2569 + attribute \src "libresoc.v:53334.3-53335.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:190429.3-190437.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$14630 - attribute \src "libresoc.v:189934.3-189935.43" + attribute \src "libresoc.v:53841.3-53849.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$2566 + attribute \src "libresoc.v:53336.3-53337.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:189410.7-189410.20" + attribute \src "libresoc.v:52822.7-52822.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190130.3-190138.6" - wire width 16 $0\int_level_l$next[15:0]$14602 - attribute \src "libresoc.v:189936.3-189937.39" + attribute \src "libresoc.v:53542.3-53550.6" + wire width 16 $0\int_level_l$next[15:0]$2538 + attribute \src "libresoc.v:53338.3-53339.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive0_pri$next[7:0]$14512 - attribute \src "libresoc.v:189942.3-189943.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive0_pri$next[7:0]$2448 + attribute \src "libresoc.v:53344.3-53345.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive10_pri$next[7:0]$14513 - attribute \src "libresoc.v:189920.3-189921.37" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive10_pri$next[7:0]$2449 + attribute \src "libresoc.v:53364.3-53365.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive11_pri$next[7:0]$14514 - attribute \src "libresoc.v:189922.3-189923.37" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive11_pri$next[7:0]$2450 + attribute \src "libresoc.v:53324.3-53325.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive12_pri$next[7:0]$14515 - attribute \src "libresoc.v:189924.3-189925.37" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive12_pri$next[7:0]$2451 + attribute \src "libresoc.v:53326.3-53327.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive13_pri$next[7:0]$14516 - attribute \src "libresoc.v:189926.3-189927.37" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive13_pri$next[7:0]$2452 + attribute \src "libresoc.v:53328.3-53329.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive14_pri$next[7:0]$14517 - attribute \src "libresoc.v:189928.3-189929.37" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive14_pri$next[7:0]$2453 + attribute \src "libresoc.v:53330.3-53331.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive15_pri$next[7:0]$14518 - attribute \src "libresoc.v:189930.3-189931.37" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive15_pri$next[7:0]$2454 + attribute \src "libresoc.v:53332.3-53333.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive1_pri$next[7:0]$14519 - attribute \src "libresoc.v:189944.3-189945.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive1_pri$next[7:0]$2455 + attribute \src "libresoc.v:53346.3-53347.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive2_pri$next[7:0]$14520 - attribute \src "libresoc.v:189946.3-189947.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive2_pri$next[7:0]$2456 + attribute \src "libresoc.v:53348.3-53349.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive3_pri$next[7:0]$14521 - attribute \src "libresoc.v:189948.3-189949.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive3_pri$next[7:0]$2457 + attribute \src "libresoc.v:53350.3-53351.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive4_pri$next[7:0]$14522 - attribute \src "libresoc.v:189950.3-189951.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive4_pri$next[7:0]$2458 + attribute \src "libresoc.v:53352.3-53353.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive5_pri$next[7:0]$14523 - attribute \src "libresoc.v:189952.3-189953.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive5_pri$next[7:0]$2459 + attribute \src "libresoc.v:53354.3-53355.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive6_pri$next[7:0]$14524 - attribute \src "libresoc.v:189912.3-189913.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive6_pri$next[7:0]$2460 + attribute \src "libresoc.v:53356.3-53357.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive7_pri$next[7:0]$14525 - attribute \src "libresoc.v:189914.3-189915.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive7_pri$next[7:0]$2461 + attribute \src "libresoc.v:53358.3-53359.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive8_pri$next[7:0]$14526 - attribute \src "libresoc.v:189916.3-189917.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive8_pri$next[7:0]$2462 + attribute \src "libresoc.v:53360.3-53361.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $0\xive9_pri$next[7:0]$14527 - attribute \src "libresoc.v:189918.3-189919.35" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $0\xive9_pri$next[7:0]$2463 + attribute \src "libresoc.v:53362.3-53363.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:190339.3-190388.6" + attribute \src "libresoc.v:53751.3-53800.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:190050.3-190059.6" + attribute \src "libresoc.v:53462.3-53471.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:190259.3-190268.6" + attribute \src "libresoc.v:53671.3-53680.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:190279.3-190288.6" + attribute \src "libresoc.v:53691.3-53700.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:190299.3-190308.6" + attribute \src "libresoc.v:53711.3-53720.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:190319.3-190328.6" + attribute \src "libresoc.v:53731.3-53740.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:190389.3-190398.6" + attribute \src "libresoc.v:53801.3-53810.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:190409.3-190418.6" + attribute \src "libresoc.v:53821.3-53830.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:190070.3-190079.6" + attribute \src "libresoc.v:53482.3-53491.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:190090.3-190099.6" + attribute \src "libresoc.v:53502.3-53511.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:190110.3-190119.6" + attribute \src "libresoc.v:53522.3-53531.6" wire width 4 $1\cur_idx3[3:0] - attribute \src "libresoc.v:190139.3-190148.6" + attribute \src "libresoc.v:53551.3-53560.6" wire width 4 $1\cur_idx4[3:0] - attribute \src "libresoc.v:190159.3-190168.6" + attribute \src "libresoc.v:53571.3-53580.6" wire width 4 $1\cur_idx5[3:0] - attribute \src "libresoc.v:190179.3-190188.6" + attribute \src "libresoc.v:53591.3-53600.6" wire width 4 $1\cur_idx6[3:0] - attribute \src "libresoc.v:190199.3-190208.6" + attribute \src "libresoc.v:53611.3-53620.6" wire width 4 $1\cur_idx7[3:0] - attribute \src "libresoc.v:190219.3-190228.6" + attribute \src "libresoc.v:53631.3-53640.6" wire width 4 $1\cur_idx8[3:0] - attribute \src "libresoc.v:190239.3-190248.6" + attribute \src "libresoc.v:53651.3-53660.6" wire width 4 $1\cur_idx9[3:0] - attribute \src "libresoc.v:190040.3-190049.6" + attribute \src "libresoc.v:53452.3-53461.6" wire width 8 $1\cur_pri0[7:0] - attribute \src "libresoc.v:190249.3-190258.6" + attribute \src "libresoc.v:53661.3-53670.6" wire width 8 $1\cur_pri10[7:0] - attribute \src "libresoc.v:190269.3-190278.6" + attribute \src "libresoc.v:53681.3-53690.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:190289.3-190298.6" + attribute \src "libresoc.v:53701.3-53710.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:190309.3-190318.6" + attribute \src "libresoc.v:53721.3-53730.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:190329.3-190338.6" + attribute \src "libresoc.v:53741.3-53750.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:190399.3-190408.6" + attribute \src "libresoc.v:53811.3-53820.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:190060.3-190069.6" + attribute \src "libresoc.v:53472.3-53481.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:190080.3-190089.6" + attribute \src "libresoc.v:53492.3-53501.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:190100.3-190109.6" + attribute \src "libresoc.v:53512.3-53521.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:190120.3-190129.6" + attribute \src "libresoc.v:53532.3-53541.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:190149.3-190158.6" + attribute \src "libresoc.v:53561.3-53570.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:190169.3-190178.6" + attribute \src "libresoc.v:53581.3-53590.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:190189.3-190198.6" + attribute \src "libresoc.v:53601.3-53610.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:190209.3-190218.6" + attribute \src "libresoc.v:53621.3-53630.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:190229.3-190238.6" + attribute \src "libresoc.v:53641.3-53650.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:190419.3-190428.6" + attribute \src "libresoc.v:53831.3-53840.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:189691.13-189691.30" + attribute \src "libresoc.v:53103.13-53103.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:189696.13-189696.29" + attribute \src "libresoc.v:53108.13-53108.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:190438.3-190446.6" - wire $1\ics_wb__ack$next[0:0]$14634 - attribute \src "libresoc.v:189705.7-189705.25" + attribute \src "libresoc.v:53850.3-53858.6" + wire $1\ics_wb__ack$next[0:0]$2570 + attribute \src "libresoc.v:53117.7-53117.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:190429.3-190437.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$14631 - attribute \src "libresoc.v:189714.14-189714.35" + attribute \src "libresoc.v:53841.3-53849.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$2567 + attribute \src "libresoc.v:53126.14-53126.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:190130.3-190138.6" - wire width 16 $1\int_level_l$next[15:0]$14603 - attribute \src "libresoc.v:189726.14-189726.36" + attribute \src "libresoc.v:53542.3-53550.6" + wire width 16 $1\int_level_l$next[15:0]$2539 + attribute \src "libresoc.v:53138.14-53138.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive0_pri$next[7:0]$14528 - attribute \src "libresoc.v:189746.13-189746.30" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive0_pri$next[7:0]$2464 + attribute \src "libresoc.v:53158.13-53158.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive10_pri$next[7:0]$14529 - attribute \src "libresoc.v:189750.13-189750.31" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive10_pri$next[7:0]$2465 + attribute \src "libresoc.v:53162.13-53162.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive11_pri$next[7:0]$14530 - attribute \src "libresoc.v:189754.13-189754.31" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive11_pri$next[7:0]$2466 + attribute \src "libresoc.v:53166.13-53166.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive12_pri$next[7:0]$14531 - attribute \src "libresoc.v:189758.13-189758.31" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive12_pri$next[7:0]$2467 + attribute \src "libresoc.v:53170.13-53170.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive13_pri$next[7:0]$14532 - attribute \src "libresoc.v:189762.13-189762.31" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive13_pri$next[7:0]$2468 + attribute \src "libresoc.v:53174.13-53174.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive14_pri$next[7:0]$14533 - attribute \src "libresoc.v:189766.13-189766.31" + attribute \src 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$1\xive2_pri$next[7:0]$2472 + attribute \src "libresoc.v:53190.13-53190.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive3_pri$next[7:0]$14537 - attribute \src "libresoc.v:189782.13-189782.30" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive3_pri$next[7:0]$2473 + attribute \src "libresoc.v:53194.13-53194.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive4_pri$next[7:0]$14538 - attribute \src "libresoc.v:189786.13-189786.30" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive4_pri$next[7:0]$2474 + attribute \src "libresoc.v:53198.13-53198.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:189954.3-190039.6" - wire width 8 $1\xive5_pri$next[7:0]$14539 - attribute \src "libresoc.v:189790.13-189790.30" + attribute \src "libresoc.v:53366.3-53451.6" + wire width 8 $1\xive5_pri$next[7:0]$2475 + attribute \src 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+148258,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -399393,7 +148356,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:189410.7-189410.15" + attribute \src "libresoc.v:52822.7-52822.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -399413,7 +148376,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:167" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:168" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -399482,7 +148445,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189811$14389 + cell $and $and$libresoc.v:53223$2325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399490,10 +148453,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:189811$14389_Y + connect \Y $and$libresoc.v:53223$2325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189813$14391 + cell $and $and$libresoc.v:53225$2327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399501,10 +148464,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:189813$14391_Y + connect \Y $and$libresoc.v:53225$2327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189815$14393 + cell $and $and$libresoc.v:53227$2329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399512,10 +148475,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:189815$14393_Y + connect \Y $and$libresoc.v:53227$2329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189817$14395 + cell $and $and$libresoc.v:53229$2331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399523,10 +148486,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:189817$14395_Y + connect \Y $and$libresoc.v:53229$2331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189819$14397 + cell $and $and$libresoc.v:53231$2333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399534,10 +148497,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:189819$14397_Y + connect \Y $and$libresoc.v:53231$2333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189821$14399 + cell $and $and$libresoc.v:53233$2335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399545,10 +148508,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:189821$14399_Y + connect \Y $and$libresoc.v:53233$2335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189823$14401 + cell $and $and$libresoc.v:53235$2337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399556,10 +148519,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:189823$14401_Y + connect \Y $and$libresoc.v:53235$2337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189826$14404 + cell $and $and$libresoc.v:53238$2340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399567,10 +148530,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:189826$14404_Y + connect \Y $and$libresoc.v:53238$2340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189828$14406 + cell $and $and$libresoc.v:53240$2342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399578,10 +148541,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:189828$14406_Y + connect \Y $and$libresoc.v:53240$2342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189830$14408 + cell $and $and$libresoc.v:53242$2344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399589,10 +148552,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:189830$14408_Y + connect \Y $and$libresoc.v:53242$2344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189833$14411 + cell $and $and$libresoc.v:53245$2347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399600,10 +148563,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:189833$14411_Y + connect \Y $and$libresoc.v:53245$2347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189835$14413 + cell $and $and$libresoc.v:53247$2349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399611,10 +148574,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:189835$14413_Y + connect \Y $and$libresoc.v:53247$2349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189837$14415 + cell $and $and$libresoc.v:53249$2351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399622,10 +148585,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:189837$14415_Y + connect \Y $and$libresoc.v:53249$2351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189839$14417 + cell $and $and$libresoc.v:53251$2353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399633,10 +148596,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:189839$14417_Y + connect \Y $and$libresoc.v:53251$2353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189841$14419 + cell $and $and$libresoc.v:53253$2355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399644,10 +148607,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:189841$14419_Y + connect \Y $and$libresoc.v:53253$2355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189843$14421 + cell $and $and$libresoc.v:53255$2357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399655,10 +148618,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:189843$14421_Y + connect \Y $and$libresoc.v:53255$2357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189845$14423 + cell $and $and$libresoc.v:53257$2359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399666,10 +148629,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:189845$14423_Y + connect \Y $and$libresoc.v:53257$2359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189848$14426 + cell $and $and$libresoc.v:53260$2362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399677,10 +148640,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:189848$14426_Y + connect \Y $and$libresoc.v:53260$2362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189850$14428 + cell $and $and$libresoc.v:53262$2364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399688,10 +148651,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:189850$14428_Y + connect \Y $and$libresoc.v:53262$2364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189852$14430 + cell $and $and$libresoc.v:53264$2366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399699,10 +148662,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:189852$14430_Y + connect \Y $and$libresoc.v:53264$2366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189855$14433 + cell $and $and$libresoc.v:53267$2369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399710,10 +148673,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:189855$14433_Y + connect \Y $and$libresoc.v:53267$2369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189857$14435 + cell $and $and$libresoc.v:53269$2371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399721,10 +148684,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:189857$14435_Y + connect \Y $and$libresoc.v:53269$2371_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189859$14437 + cell $and $and$libresoc.v:53271$2373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399732,10 +148695,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:189859$14437_Y + connect \Y $and$libresoc.v:53271$2373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189861$14439 + cell $and $and$libresoc.v:53273$2375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399743,10 +148706,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:189861$14439_Y + connect \Y $and$libresoc.v:53273$2375_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189863$14441 + cell $and $and$libresoc.v:53275$2377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399754,10 +148717,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:189863$14441_Y + connect \Y $and$libresoc.v:53275$2377_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189866$14444 + cell $and $and$libresoc.v:53278$2380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399765,10 +148728,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:189866$14444_Y + connect \Y $and$libresoc.v:53278$2380_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:189890$14468 + cell $and $and$libresoc.v:53302$2404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399776,10 +148739,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:189890$14468_Y + connect \Y $and$libresoc.v:53302$2404_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:189898$14476 + cell $and $and$libresoc.v:53310$2412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399787,10 +148750,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:189898$14476_Y + connect \Y $and$libresoc.v:53310$2412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189900$14478 + cell $and $and$libresoc.v:53312$2414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399798,10 +148761,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:189900$14478_Y + connect \Y $and$libresoc.v:53312$2414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189902$14480 + cell $and $and$libresoc.v:53314$2416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399809,10 +148772,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:189902$14480_Y + connect \Y $and$libresoc.v:53314$2416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189904$14482 + cell $and $and$libresoc.v:53316$2418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399820,10 +148783,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:189904$14482_Y + connect \Y $and$libresoc.v:53316$2418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189907$14485 + cell $and $and$libresoc.v:53319$2421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399831,10 +148794,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:189907$14485_Y + connect \Y $and$libresoc.v:53319$2421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189909$14487 + cell $and $and$libresoc.v:53321$2423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399842,10 +148805,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:189909$14487_Y + connect \Y $and$libresoc.v:53321$2423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:189911$14489 + cell $and $and$libresoc.v:53323$2425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399853,10 +148816,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:189911$14489_Y + connect \Y $and$libresoc.v:53323$2425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189825$14403 + cell $eq $eq$libresoc.v:53237$2339 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399864,10 +148827,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189825$14403_Y + connect \Y $eq$libresoc.v:53237$2339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189847$14425 + cell $eq $eq$libresoc.v:53259$2361 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399875,10 +148838,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189847$14425_Y + connect \Y $eq$libresoc.v:53259$2361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:189864$14442 + cell $eq $eq$libresoc.v:53276$2378 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -399886,10 +148849,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:189864$14442_Y + connect \Y $eq$libresoc.v:53276$2378_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189867$14445 + cell $eq $eq$libresoc.v:53279$2381 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399897,10 +148860,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:189867$14445_Y + connect \Y $eq$libresoc.v:53279$2381_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189869$14447 + cell $eq $eq$libresoc.v:53281$2383 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399908,10 +148871,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189869$14447_Y + connect \Y $eq$libresoc.v:53281$2383_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189871$14449 + cell $eq $eq$libresoc.v:53283$2385 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399919,10 +148882,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189871$14449_Y + connect \Y $eq$libresoc.v:53283$2385_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189873$14451 + cell $eq $eq$libresoc.v:53285$2387 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399930,10 +148893,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189873$14451_Y + connect \Y $eq$libresoc.v:53285$2387_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189875$14453 + cell $eq $eq$libresoc.v:53287$2389 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399941,10 +148904,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189875$14453_Y + connect \Y $eq$libresoc.v:53287$2389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189877$14455 + cell $eq $eq$libresoc.v:53289$2391 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399952,10 +148915,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189877$14455_Y + connect \Y $eq$libresoc.v:53289$2391_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:189879$14457 + cell $eq $eq$libresoc.v:53291$2393 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -399963,10 +148926,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:189879$14457_Y + connect \Y $eq$libresoc.v:53291$2393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189880$14458 + cell $eq $eq$libresoc.v:53292$2394 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399974,10 +148937,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189880$14458_Y + connect \Y $eq$libresoc.v:53292$2394_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189882$14460 + cell $eq $eq$libresoc.v:53294$2396 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399985,10 +148948,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189882$14460_Y + connect \Y $eq$libresoc.v:53294$2396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189884$14462 + cell $eq $eq$libresoc.v:53296$2398 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -399996,10 +148959,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189884$14462_Y + connect \Y $eq$libresoc.v:53296$2398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189886$14464 + cell $eq $eq$libresoc.v:53298$2400 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400007,10 +148970,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189886$14464_Y + connect \Y $eq$libresoc.v:53298$2400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189888$14466 + cell $eq $eq$libresoc.v:53300$2402 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400018,10 +148981,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189888$14466_Y + connect \Y $eq$libresoc.v:53300$2402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189891$14469 + cell $eq $eq$libresoc.v:53303$2405 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400029,10 +148992,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189891$14469_Y + connect \Y $eq$libresoc.v:53303$2405_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189893$14471 + cell $eq $eq$libresoc.v:53305$2407 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400040,10 +149003,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189893$14471_Y + connect \Y $eq$libresoc.v:53305$2407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189895$14473 + cell $eq $eq$libresoc.v:53307$2409 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400051,10 +149014,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189895$14473_Y + connect \Y $eq$libresoc.v:53307$2409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:189906$14484 + cell $eq $eq$libresoc.v:53318$2420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400062,10 +149025,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:189906$14484_Y + connect \Y $eq$libresoc.v:53318$2420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189810$14388 + cell $lt $lt$libresoc.v:53222$2324 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400073,10 +149036,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:189810$14388_Y + connect \Y $lt$libresoc.v:53222$2324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189812$14390 + cell $lt $lt$libresoc.v:53224$2326 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400084,10 +149047,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:189812$14390_Y + connect \Y $lt$libresoc.v:53224$2326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189814$14392 + cell $lt $lt$libresoc.v:53226$2328 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400095,10 +149058,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:189814$14392_Y + connect \Y $lt$libresoc.v:53226$2328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189816$14394 + cell $lt $lt$libresoc.v:53228$2330 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400106,10 +149069,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:189816$14394_Y + connect \Y $lt$libresoc.v:53228$2330_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189818$14396 + cell $lt $lt$libresoc.v:53230$2332 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400117,10 +149080,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:189818$14396_Y + connect \Y $lt$libresoc.v:53230$2332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189820$14398 + cell $lt $lt$libresoc.v:53232$2334 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400128,10 +149091,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:189820$14398_Y + connect \Y $lt$libresoc.v:53232$2334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189822$14400 + cell $lt $lt$libresoc.v:53234$2336 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400139,10 +149102,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:189822$14400_Y + connect \Y $lt$libresoc.v:53234$2336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189824$14402 + cell $lt $lt$libresoc.v:53236$2338 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400150,10 +149113,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:189824$14402_Y + connect \Y $lt$libresoc.v:53236$2338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189827$14405 + cell $lt $lt$libresoc.v:53239$2341 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400161,10 +149124,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:189827$14405_Y + connect \Y $lt$libresoc.v:53239$2341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189829$14407 + cell $lt $lt$libresoc.v:53241$2343 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400172,10 +149135,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:189829$14407_Y + connect \Y $lt$libresoc.v:53241$2343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189832$14410 + cell $lt $lt$libresoc.v:53244$2346 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400183,10 +149146,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:189832$14410_Y + connect \Y $lt$libresoc.v:53244$2346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189834$14412 + cell $lt $lt$libresoc.v:53246$2348 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400194,10 +149157,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:189834$14412_Y + connect \Y $lt$libresoc.v:53246$2348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189836$14414 + cell $lt $lt$libresoc.v:53248$2350 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400205,10 +149168,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:189836$14414_Y + connect \Y $lt$libresoc.v:53248$2350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189838$14416 + cell $lt $lt$libresoc.v:53250$2352 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400216,10 +149179,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:189838$14416_Y + connect \Y $lt$libresoc.v:53250$2352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189840$14418 + cell $lt $lt$libresoc.v:53252$2354 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400227,10 +149190,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:189840$14418_Y + connect \Y $lt$libresoc.v:53252$2354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189842$14420 + cell $lt $lt$libresoc.v:53254$2356 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400238,10 +149201,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:189842$14420_Y + connect \Y $lt$libresoc.v:53254$2356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189844$14422 + cell $lt $lt$libresoc.v:53256$2358 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400249,10 +149212,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:189844$14422_Y + connect \Y $lt$libresoc.v:53256$2358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189846$14424 + cell $lt $lt$libresoc.v:53258$2360 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400260,10 +149223,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:189846$14424_Y + connect \Y $lt$libresoc.v:53258$2360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189849$14427 + cell $lt $lt$libresoc.v:53261$2363 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400271,10 +149234,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:189849$14427_Y + connect \Y $lt$libresoc.v:53261$2363_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189851$14429 + cell $lt $lt$libresoc.v:53263$2365 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400282,10 +149245,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:189851$14429_Y + connect \Y $lt$libresoc.v:53263$2365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189854$14432 + cell $lt $lt$libresoc.v:53266$2368 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400293,10 +149256,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:189854$14432_Y + connect \Y $lt$libresoc.v:53266$2368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189856$14434 + cell $lt $lt$libresoc.v:53268$2370 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400304,10 +149267,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:189856$14434_Y + connect \Y $lt$libresoc.v:53268$2370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189858$14436 + cell $lt $lt$libresoc.v:53270$2372 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400315,10 +149278,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:189858$14436_Y + connect \Y $lt$libresoc.v:53270$2372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189860$14438 + cell $lt $lt$libresoc.v:53272$2374 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400326,10 +149289,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:189860$14438_Y + connect \Y $lt$libresoc.v:53272$2374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189862$14440 + cell $lt $lt$libresoc.v:53274$2376 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400337,10 +149300,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:189862$14440_Y + connect \Y $lt$libresoc.v:53274$2376_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189865$14443 + cell $lt $lt$libresoc.v:53277$2379 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400348,10 +149311,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:189865$14443_Y + connect \Y $lt$libresoc.v:53277$2379_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189899$14477 + cell $lt $lt$libresoc.v:53311$2413 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400359,10 +149322,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:189899$14477_Y + connect \Y $lt$libresoc.v:53311$2413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189901$14479 + cell $lt $lt$libresoc.v:53313$2415 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400370,10 +149333,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:189901$14479_Y + connect \Y $lt$libresoc.v:53313$2415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189903$14481 + cell $lt $lt$libresoc.v:53315$2417 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400381,10 +149344,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:189903$14481_Y + connect \Y $lt$libresoc.v:53315$2417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189905$14483 + cell $lt $lt$libresoc.v:53317$2419 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400392,10 +149355,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:189905$14483_Y + connect \Y $lt$libresoc.v:53317$2419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189908$14486 + cell $lt $lt$libresoc.v:53320$2422 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400403,10 +149366,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:189908$14486_Y + connect \Y $lt$libresoc.v:53320$2422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:189910$14488 + cell $lt $lt$libresoc.v:53322$2424 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -400414,10 +149377,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:189910$14488_Y + connect \Y $lt$libresoc.v:53322$2424_Y end - attribute \src "libresoc.v:189897.18-189897.40" - cell $shr $shr$libresoc.v:189897$14475 + attribute \src "libresoc.v:53309.18-53309.40" + cell $shr $shr$libresoc.v:53309$2411 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -400425,469 +149388,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:189897$14475_Y + connect \Y $shr$libresoc.v:53309$2411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189809$14387 + cell $mux $ternary$libresoc.v:53221$2323 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:189809$14387_Y + connect \Y $ternary$libresoc.v:53221$2323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189831$14409 + cell $mux $ternary$libresoc.v:53243$2345 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:189831$14409_Y + connect \Y $ternary$libresoc.v:53243$2345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189853$14431 + cell $mux $ternary$libresoc.v:53265$2367 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:189853$14431_Y + connect \Y $ternary$libresoc.v:53265$2367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189868$14446 + cell $mux $ternary$libresoc.v:53280$2382 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:189868$14446_Y + connect \Y $ternary$libresoc.v:53280$2382_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189870$14448 + cell $mux $ternary$libresoc.v:53282$2384 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:189870$14448_Y + connect \Y $ternary$libresoc.v:53282$2384_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189872$14450 + cell $mux $ternary$libresoc.v:53284$2386 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:189872$14450_Y + connect \Y $ternary$libresoc.v:53284$2386_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189874$14452 + cell $mux $ternary$libresoc.v:53286$2388 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:189874$14452_Y + connect \Y $ternary$libresoc.v:53286$2388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189876$14454 + cell $mux $ternary$libresoc.v:53288$2390 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:189876$14454_Y + connect \Y $ternary$libresoc.v:53288$2390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189878$14456 + cell $mux $ternary$libresoc.v:53290$2392 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:189878$14456_Y + connect \Y $ternary$libresoc.v:53290$2392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189881$14459 + cell $mux $ternary$libresoc.v:53293$2395 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:189881$14459_Y + connect \Y $ternary$libresoc.v:53293$2395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189883$14461 + cell $mux $ternary$libresoc.v:53295$2397 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:189883$14461_Y + connect \Y $ternary$libresoc.v:53295$2397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189885$14463 + cell $mux $ternary$libresoc.v:53297$2399 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:189885$14463_Y + connect \Y $ternary$libresoc.v:53297$2399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189887$14465 + cell $mux $ternary$libresoc.v:53299$2401 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:189887$14465_Y + connect \Y $ternary$libresoc.v:53299$2401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189889$14467 + cell $mux $ternary$libresoc.v:53301$2403 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:189889$14467_Y + connect \Y $ternary$libresoc.v:53301$2403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189892$14470 + cell $mux $ternary$libresoc.v:53304$2406 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:189892$14470_Y + connect \Y $ternary$libresoc.v:53304$2406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189894$14472 + cell $mux $ternary$libresoc.v:53306$2408 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:189894$14472_Y + connect \Y $ternary$libresoc.v:53306$2408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:189896$14474 + cell $mux $ternary$libresoc.v:53308$2410 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:189896$14474_Y + connect \Y $ternary$libresoc.v:53308$2410_Y end - attribute \src "libresoc.v:189410.7-189410.20" - process $proc$libresoc.v:189410$14635 + attribute \src "libresoc.v:52822.7-52822.20" + process $proc$libresoc.v:52822$2571 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189691.13-189691.30" - process $proc$libresoc.v:189691$14636 + attribute \src "libresoc.v:53103.13-53103.30" + process $proc$libresoc.v:53103$2572 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:189696.13-189696.29" - process $proc$libresoc.v:189696$14637 + attribute \src "libresoc.v:53108.13-53108.29" + process $proc$libresoc.v:53108$2573 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:189705.7-189705.25" - process $proc$libresoc.v:189705$14638 + attribute \src "libresoc.v:53117.7-53117.25" + process $proc$libresoc.v:53117$2574 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:189714.14-189714.35" - process $proc$libresoc.v:189714$14639 + attribute \src "libresoc.v:53126.14-53126.35" + process $proc$libresoc.v:53126$2575 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:189726.14-189726.36" - process $proc$libresoc.v:189726$14640 + attribute \src "libresoc.v:53138.14-53138.36" + process $proc$libresoc.v:53138$2576 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:189746.13-189746.30" - process $proc$libresoc.v:189746$14641 + attribute \src "libresoc.v:53158.13-53158.30" + process $proc$libresoc.v:53158$2577 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:189750.13-189750.31" - process $proc$libresoc.v:189750$14642 + attribute \src "libresoc.v:53162.13-53162.31" + process $proc$libresoc.v:53162$2578 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:189754.13-189754.31" - process $proc$libresoc.v:189754$14643 + attribute \src "libresoc.v:53166.13-53166.31" + process $proc$libresoc.v:53166$2579 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:189758.13-189758.31" - process $proc$libresoc.v:189758$14644 + attribute \src "libresoc.v:53170.13-53170.31" + process $proc$libresoc.v:53170$2580 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:189762.13-189762.31" - process $proc$libresoc.v:189762$14645 + attribute \src "libresoc.v:53174.13-53174.31" + process $proc$libresoc.v:53174$2581 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:189766.13-189766.31" - process $proc$libresoc.v:189766$14646 + attribute \src "libresoc.v:53178.13-53178.31" + process $proc$libresoc.v:53178$2582 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:189770.13-189770.31" - process $proc$libresoc.v:189770$14647 + attribute \src "libresoc.v:53182.13-53182.31" + process $proc$libresoc.v:53182$2583 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:189774.13-189774.30" - process $proc$libresoc.v:189774$14648 + attribute \src "libresoc.v:53186.13-53186.30" + process $proc$libresoc.v:53186$2584 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:189778.13-189778.30" - process $proc$libresoc.v:189778$14649 + attribute \src "libresoc.v:53190.13-53190.30" + process $proc$libresoc.v:53190$2585 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:189782.13-189782.30" - process $proc$libresoc.v:189782$14650 + attribute \src "libresoc.v:53194.13-53194.30" + process $proc$libresoc.v:53194$2586 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:189786.13-189786.30" - process $proc$libresoc.v:189786$14651 + attribute \src "libresoc.v:53198.13-53198.30" + process $proc$libresoc.v:53198$2587 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:189790.13-189790.30" - process $proc$libresoc.v:189790$14652 + attribute \src "libresoc.v:53202.13-53202.30" + process $proc$libresoc.v:53202$2588 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:189794.13-189794.30" - process $proc$libresoc.v:189794$14653 + attribute \src "libresoc.v:53206.13-53206.30" + process $proc$libresoc.v:53206$2589 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:189798.13-189798.30" - process $proc$libresoc.v:189798$14654 + attribute \src "libresoc.v:53210.13-53210.30" + process $proc$libresoc.v:53210$2590 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:189802.13-189802.30" - process $proc$libresoc.v:189802$14655 + attribute \src "libresoc.v:53214.13-53214.30" + process $proc$libresoc.v:53214$2591 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:189806.13-189806.30" - process $proc$libresoc.v:189806$14656 + attribute \src "libresoc.v:53218.13-53218.30" + process $proc$libresoc.v:53218$2592 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:189912.3-189913.35" - process $proc$libresoc.v:189912$14490 - assign { } { } - assign $0\xive6_pri[7:0] \xive6_pri$next - sync posedge \clk - update \xive6_pri $0\xive6_pri[7:0] - end - attribute \src "libresoc.v:189914.3-189915.35" - process $proc$libresoc.v:189914$14491 - assign { } { } - assign $0\xive7_pri[7:0] \xive7_pri$next - sync posedge \clk - update \xive7_pri $0\xive7_pri[7:0] - end - attribute \src "libresoc.v:189916.3-189917.35" - process $proc$libresoc.v:189916$14492 - assign { } { } - assign $0\xive8_pri[7:0] \xive8_pri$next - sync posedge \clk - update \xive8_pri $0\xive8_pri[7:0] - end - attribute \src "libresoc.v:189918.3-189919.35" - process $proc$libresoc.v:189918$14493 - assign { } { } - assign $0\xive9_pri[7:0] \xive9_pri$next - sync posedge \clk - update \xive9_pri $0\xive9_pri[7:0] - end - attribute \src "libresoc.v:189920.3-189921.37" - process $proc$libresoc.v:189920$14494 - assign { } { } - assign $0\xive10_pri[7:0] \xive10_pri$next - sync posedge \clk - update \xive10_pri $0\xive10_pri[7:0] - end - attribute \src "libresoc.v:189922.3-189923.37" - process $proc$libresoc.v:189922$14495 + attribute \src "libresoc.v:53324.3-53325.37" + process $proc$libresoc.v:53324$2426 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:189924.3-189925.37" - process $proc$libresoc.v:189924$14496 + attribute \src "libresoc.v:53326.3-53327.37" + process $proc$libresoc.v:53326$2427 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:189926.3-189927.37" - process $proc$libresoc.v:189926$14497 + attribute \src "libresoc.v:53328.3-53329.37" + process $proc$libresoc.v:53328$2428 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:189928.3-189929.37" - process $proc$libresoc.v:189928$14498 + attribute \src "libresoc.v:53330.3-53331.37" + process $proc$libresoc.v:53330$2429 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:189930.3-189931.37" - process $proc$libresoc.v:189930$14499 + attribute \src "libresoc.v:53332.3-53333.37" + process $proc$libresoc.v:53332$2430 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:189932.3-189933.39" - process $proc$libresoc.v:189932$14500 + attribute \src "libresoc.v:53334.3-53335.39" + process $proc$libresoc.v:53334$2431 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:189934.3-189935.43" - process $proc$libresoc.v:189934$14501 + attribute \src "libresoc.v:53336.3-53337.43" + process $proc$libresoc.v:53336$2432 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:189936.3-189937.39" - process $proc$libresoc.v:189936$14502 + attribute \src "libresoc.v:53338.3-53339.39" + process $proc$libresoc.v:53338$2433 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:189938.3-189939.28" - process $proc$libresoc.v:189938$14503 + attribute \src "libresoc.v:53340.3-53341.28" + process $proc$libresoc.v:53340$2434 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:189940.3-189941.25" - process $proc$libresoc.v:189940$14504 + attribute \src "libresoc.v:53342.3-53343.25" + process $proc$libresoc.v:53342$2435 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:189942.3-189943.35" - process $proc$libresoc.v:189942$14505 + attribute \src "libresoc.v:53344.3-53345.35" + process $proc$libresoc.v:53344$2436 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:189944.3-189945.35" - process $proc$libresoc.v:189944$14506 + attribute \src "libresoc.v:53346.3-53347.35" + process $proc$libresoc.v:53346$2437 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:189946.3-189947.35" - process $proc$libresoc.v:189946$14507 + attribute \src "libresoc.v:53348.3-53349.35" + process $proc$libresoc.v:53348$2438 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:189948.3-189949.35" - process $proc$libresoc.v:189948$14508 + attribute \src "libresoc.v:53350.3-53351.35" + process $proc$libresoc.v:53350$2439 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:189950.3-189951.35" - process $proc$libresoc.v:189950$14509 + attribute \src "libresoc.v:53352.3-53353.35" + process $proc$libresoc.v:53352$2440 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:189952.3-189953.35" - process $proc$libresoc.v:189952$14510 + attribute \src "libresoc.v:53354.3-53355.35" + process $proc$libresoc.v:53354$2441 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:189954.3-190039.6" - process $proc$libresoc.v:189954$14511 + attribute \src "libresoc.v:53356.3-53357.35" + process $proc$libresoc.v:53356$2442 + assign { } { } + assign $0\xive6_pri[7:0] \xive6_pri$next + sync posedge \clk + update \xive6_pri $0\xive6_pri[7:0] + end + attribute \src "libresoc.v:53358.3-53359.35" + process $proc$libresoc.v:53358$2443 + assign { } { } + assign $0\xive7_pri[7:0] \xive7_pri$next + sync posedge \clk + update \xive7_pri $0\xive7_pri[7:0] + end + attribute \src "libresoc.v:53360.3-53361.35" + process $proc$libresoc.v:53360$2444 + assign { } { } + assign $0\xive8_pri[7:0] \xive8_pri$next + sync posedge \clk + update \xive8_pri $0\xive8_pri[7:0] + end + attribute \src "libresoc.v:53362.3-53363.35" + process $proc$libresoc.v:53362$2445 + assign { } { } + assign $0\xive9_pri[7:0] \xive9_pri$next + sync posedge \clk + update \xive9_pri $0\xive9_pri[7:0] + end + attribute \src "libresoc.v:53364.3-53365.37" + process $proc$libresoc.v:53364$2446 + assign { } { } + assign $0\xive10_pri[7:0] \xive10_pri$next + sync posedge \clk + update \xive10_pri $0\xive10_pri[7:0] + end + attribute \src "libresoc.v:53366.3-53451.6" + process $proc$libresoc.v:53366$2447 assign { } { } assign { } { } assign { } { } @@ -400936,25 +149899,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14512 $4\xive0_pri$next[7:0]$14576 - assign $0\xive10_pri$next[7:0]$14513 $4\xive10_pri$next[7:0]$14577 - assign $0\xive11_pri$next[7:0]$14514 $4\xive11_pri$next[7:0]$14578 - assign $0\xive12_pri$next[7:0]$14515 $4\xive12_pri$next[7:0]$14579 - assign $0\xive13_pri$next[7:0]$14516 $4\xive13_pri$next[7:0]$14580 - assign $0\xive14_pri$next[7:0]$14517 $4\xive14_pri$next[7:0]$14581 - assign $0\xive15_pri$next[7:0]$14518 $4\xive15_pri$next[7:0]$14582 - assign $0\xive1_pri$next[7:0]$14519 $4\xive1_pri$next[7:0]$14583 - assign $0\xive2_pri$next[7:0]$14520 $4\xive2_pri$next[7:0]$14584 - assign $0\xive3_pri$next[7:0]$14521 $4\xive3_pri$next[7:0]$14585 - assign $0\xive4_pri$next[7:0]$14522 $4\xive4_pri$next[7:0]$14586 - assign $0\xive5_pri$next[7:0]$14523 $4\xive5_pri$next[7:0]$14587 - assign $0\xive6_pri$next[7:0]$14524 $4\xive6_pri$next[7:0]$14588 - assign $0\xive7_pri$next[7:0]$14525 $4\xive7_pri$next[7:0]$14589 - assign $0\xive8_pri$next[7:0]$14526 $4\xive8_pri$next[7:0]$14590 - assign $0\xive9_pri$next[7:0]$14527 $4\xive9_pri$next[7:0]$14591 - attribute \src "libresoc.v:189955.5-189955.29" + assign $0\xive0_pri$next[7:0]$2448 $4\xive0_pri$next[7:0]$2512 + assign $0\xive10_pri$next[7:0]$2449 $4\xive10_pri$next[7:0]$2513 + assign $0\xive11_pri$next[7:0]$2450 $4\xive11_pri$next[7:0]$2514 + assign $0\xive12_pri$next[7:0]$2451 $4\xive12_pri$next[7:0]$2515 + assign $0\xive13_pri$next[7:0]$2452 $4\xive13_pri$next[7:0]$2516 + assign $0\xive14_pri$next[7:0]$2453 $4\xive14_pri$next[7:0]$2517 + assign $0\xive15_pri$next[7:0]$2454 $4\xive15_pri$next[7:0]$2518 + assign $0\xive1_pri$next[7:0]$2455 $4\xive1_pri$next[7:0]$2519 + assign $0\xive2_pri$next[7:0]$2456 $4\xive2_pri$next[7:0]$2520 + assign $0\xive3_pri$next[7:0]$2457 $4\xive3_pri$next[7:0]$2521 + assign $0\xive4_pri$next[7:0]$2458 $4\xive4_pri$next[7:0]$2522 + assign $0\xive5_pri$next[7:0]$2459 $4\xive5_pri$next[7:0]$2523 + assign $0\xive6_pri$next[7:0]$2460 $4\xive6_pri$next[7:0]$2524 + assign $0\xive7_pri$next[7:0]$2461 $4\xive7_pri$next[7:0]$2525 + assign $0\xive8_pri$next[7:0]$2462 $4\xive8_pri$next[7:0]$2526 + assign $0\xive9_pri$next[7:0]$2463 $4\xive9_pri$next[7:0]$2527 + attribute \src "libresoc.v:53367.5-53367.29" switch \initial - attribute \src "libresoc.v:189955.9-189955.17" + attribute \src "libresoc.v:53367.9-53367.17" case 1'1 case end @@ -400978,22 +149941,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14528 $2\xive0_pri$next[7:0]$14544 - assign $1\xive10_pri$next[7:0]$14529 $2\xive10_pri$next[7:0]$14545 - assign $1\xive11_pri$next[7:0]$14530 $2\xive11_pri$next[7:0]$14546 - assign $1\xive12_pri$next[7:0]$14531 $2\xive12_pri$next[7:0]$14547 - assign $1\xive13_pri$next[7:0]$14532 $2\xive13_pri$next[7:0]$14548 - assign $1\xive14_pri$next[7:0]$14533 $2\xive14_pri$next[7:0]$14549 - assign $1\xive15_pri$next[7:0]$14534 $2\xive15_pri$next[7:0]$14550 - assign $1\xive1_pri$next[7:0]$14535 $2\xive1_pri$next[7:0]$14551 - assign $1\xive2_pri$next[7:0]$14536 $2\xive2_pri$next[7:0]$14552 - assign $1\xive3_pri$next[7:0]$14537 $2\xive3_pri$next[7:0]$14553 - assign $1\xive4_pri$next[7:0]$14538 $2\xive4_pri$next[7:0]$14554 - assign $1\xive5_pri$next[7:0]$14539 $2\xive5_pri$next[7:0]$14555 - assign $1\xive6_pri$next[7:0]$14540 $2\xive6_pri$next[7:0]$14556 - assign $1\xive7_pri$next[7:0]$14541 $2\xive7_pri$next[7:0]$14557 - assign $1\xive8_pri$next[7:0]$14542 $2\xive8_pri$next[7:0]$14558 - assign $1\xive9_pri$next[7:0]$14543 $2\xive9_pri$next[7:0]$14559 + assign $1\xive0_pri$next[7:0]$2464 $2\xive0_pri$next[7:0]$2480 + assign $1\xive10_pri$next[7:0]$2465 $2\xive10_pri$next[7:0]$2481 + assign $1\xive11_pri$next[7:0]$2466 $2\xive11_pri$next[7:0]$2482 + assign $1\xive12_pri$next[7:0]$2467 $2\xive12_pri$next[7:0]$2483 + assign $1\xive13_pri$next[7:0]$2468 $2\xive13_pri$next[7:0]$2484 + assign $1\xive14_pri$next[7:0]$2469 $2\xive14_pri$next[7:0]$2485 + assign $1\xive15_pri$next[7:0]$2470 $2\xive15_pri$next[7:0]$2486 + assign $1\xive1_pri$next[7:0]$2471 $2\xive1_pri$next[7:0]$2487 + assign $1\xive2_pri$next[7:0]$2472 $2\xive2_pri$next[7:0]$2488 + assign $1\xive3_pri$next[7:0]$2473 $2\xive3_pri$next[7:0]$2489 + assign $1\xive4_pri$next[7:0]$2474 $2\xive4_pri$next[7:0]$2490 + assign $1\xive5_pri$next[7:0]$2475 $2\xive5_pri$next[7:0]$2491 + assign $1\xive6_pri$next[7:0]$2476 $2\xive6_pri$next[7:0]$2492 + assign $1\xive7_pri$next[7:0]$2477 $2\xive7_pri$next[7:0]$2493 + assign $1\xive8_pri$next[7:0]$2478 $2\xive8_pri$next[7:0]$2494 + assign $1\xive9_pri$next[7:0]$2479 $2\xive9_pri$next[7:0]$2495 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -401014,381 +149977,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14544 $3\xive0_pri$next[7:0]$14560 - assign $2\xive10_pri$next[7:0]$14545 $3\xive10_pri$next[7:0]$14561 - assign $2\xive11_pri$next[7:0]$14546 $3\xive11_pri$next[7:0]$14562 - assign $2\xive12_pri$next[7:0]$14547 $3\xive12_pri$next[7:0]$14563 - assign $2\xive13_pri$next[7:0]$14548 $3\xive13_pri$next[7:0]$14564 - assign $2\xive14_pri$next[7:0]$14549 $3\xive14_pri$next[7:0]$14565 - assign $2\xive15_pri$next[7:0]$14550 $3\xive15_pri$next[7:0]$14566 - assign $2\xive1_pri$next[7:0]$14551 $3\xive1_pri$next[7:0]$14567 - assign $2\xive2_pri$next[7:0]$14552 $3\xive2_pri$next[7:0]$14568 - assign $2\xive3_pri$next[7:0]$14553 $3\xive3_pri$next[7:0]$14569 - assign $2\xive4_pri$next[7:0]$14554 $3\xive4_pri$next[7:0]$14570 - assign $2\xive5_pri$next[7:0]$14555 $3\xive5_pri$next[7:0]$14571 - assign $2\xive6_pri$next[7:0]$14556 $3\xive6_pri$next[7:0]$14572 - assign $2\xive7_pri$next[7:0]$14557 $3\xive7_pri$next[7:0]$14573 - assign $2\xive8_pri$next[7:0]$14558 $3\xive8_pri$next[7:0]$14574 - assign $2\xive9_pri$next[7:0]$14559 $3\xive9_pri$next[7:0]$14575 + assign $2\xive0_pri$next[7:0]$2480 $3\xive0_pri$next[7:0]$2496 + assign $2\xive10_pri$next[7:0]$2481 $3\xive10_pri$next[7:0]$2497 + assign $2\xive11_pri$next[7:0]$2482 $3\xive11_pri$next[7:0]$2498 + assign $2\xive12_pri$next[7:0]$2483 $3\xive12_pri$next[7:0]$2499 + assign $2\xive13_pri$next[7:0]$2484 $3\xive13_pri$next[7:0]$2500 + assign $2\xive14_pri$next[7:0]$2485 $3\xive14_pri$next[7:0]$2501 + assign $2\xive15_pri$next[7:0]$2486 $3\xive15_pri$next[7:0]$2502 + assign $2\xive1_pri$next[7:0]$2487 $3\xive1_pri$next[7:0]$2503 + assign $2\xive2_pri$next[7:0]$2488 $3\xive2_pri$next[7:0]$2504 + assign $2\xive3_pri$next[7:0]$2489 $3\xive3_pri$next[7:0]$2505 + assign $2\xive4_pri$next[7:0]$2490 $3\xive4_pri$next[7:0]$2506 + assign $2\xive5_pri$next[7:0]$2491 $3\xive5_pri$next[7:0]$2507 + assign $2\xive6_pri$next[7:0]$2492 $3\xive6_pri$next[7:0]$2508 + assign $2\xive7_pri$next[7:0]$2493 $3\xive7_pri$next[7:0]$2509 + assign $2\xive8_pri$next[7:0]$2494 $3\xive8_pri$next[7:0]$2510 + assign $2\xive9_pri$next[7:0]$2495 $3\xive9_pri$next[7:0]$2511 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive0_pri$next[7:0]$14560 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive0_pri$next[7:0]$2496 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive1_pri$next[7:0]$14567 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive1_pri$next[7:0]$2503 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive2_pri$next[7:0]$14568 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive2_pri$next[7:0]$2504 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive3_pri$next[7:0]$14569 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive3_pri$next[7:0]$2505 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive4_pri$next[7:0]$14570 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive4_pri$next[7:0]$2506 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive5_pri$next[7:0]$14571 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive5_pri$next[7:0]$2507 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive6_pri$next[7:0]$14572 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive6_pri$next[7:0]$2508 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive7_pri$next[7:0]$14573 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive7_pri$next[7:0]$2509 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive8_pri$next[7:0]$14574 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive8_pri$next[7:0]$2510 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14575 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$2511 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive10_pri$next[7:0]$14561 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive10_pri$next[7:0]$2497 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive11_pri$next[7:0]$14562 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive11_pri$next[7:0]$2498 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive12_pri$next[7:0]$14563 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive12_pri$next[7:0]$2499 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive13_pri$next[7:0]$14564 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive13_pri$next[7:0]$2500 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive14_pri$next[7:0]$14565 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive14_pri$next[7:0]$2501 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri - assign $3\xive15_pri$next[7:0]$14566 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri + assign $3\xive15_pri$next[7:0]$2502 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14560 \xive0_pri - assign $3\xive10_pri$next[7:0]$14561 \xive10_pri - assign $3\xive11_pri$next[7:0]$14562 \xive11_pri - assign $3\xive12_pri$next[7:0]$14563 \xive12_pri - assign $3\xive13_pri$next[7:0]$14564 \xive13_pri - assign $3\xive14_pri$next[7:0]$14565 \xive14_pri - assign $3\xive15_pri$next[7:0]$14566 \xive15_pri - assign $3\xive1_pri$next[7:0]$14567 \xive1_pri - assign $3\xive2_pri$next[7:0]$14568 \xive2_pri - assign $3\xive3_pri$next[7:0]$14569 \xive3_pri - assign $3\xive4_pri$next[7:0]$14570 \xive4_pri - assign $3\xive5_pri$next[7:0]$14571 \xive5_pri - assign $3\xive6_pri$next[7:0]$14572 \xive6_pri - assign $3\xive7_pri$next[7:0]$14573 \xive7_pri - assign $3\xive8_pri$next[7:0]$14574 \xive8_pri - assign $3\xive9_pri$next[7:0]$14575 \xive9_pri + assign $3\xive0_pri$next[7:0]$2496 \xive0_pri + assign $3\xive10_pri$next[7:0]$2497 \xive10_pri + assign $3\xive11_pri$next[7:0]$2498 \xive11_pri + assign $3\xive12_pri$next[7:0]$2499 \xive12_pri + assign $3\xive13_pri$next[7:0]$2500 \xive13_pri + assign $3\xive14_pri$next[7:0]$2501 \xive14_pri + assign $3\xive15_pri$next[7:0]$2502 \xive15_pri + assign $3\xive1_pri$next[7:0]$2503 \xive1_pri + assign $3\xive2_pri$next[7:0]$2504 \xive2_pri + assign $3\xive3_pri$next[7:0]$2505 \xive3_pri + assign $3\xive4_pri$next[7:0]$2506 \xive4_pri + assign $3\xive5_pri$next[7:0]$2507 \xive5_pri + assign $3\xive6_pri$next[7:0]$2508 \xive6_pri + assign $3\xive7_pri$next[7:0]$2509 \xive7_pri + assign $3\xive8_pri$next[7:0]$2510 \xive8_pri + assign $3\xive9_pri$next[7:0]$2511 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14544 \xive0_pri - assign $2\xive10_pri$next[7:0]$14545 \xive10_pri - assign $2\xive11_pri$next[7:0]$14546 \xive11_pri - assign $2\xive12_pri$next[7:0]$14547 \xive12_pri - assign $2\xive13_pri$next[7:0]$14548 \xive13_pri - assign $2\xive14_pri$next[7:0]$14549 \xive14_pri - assign $2\xive15_pri$next[7:0]$14550 \xive15_pri - assign $2\xive1_pri$next[7:0]$14551 \xive1_pri - assign $2\xive2_pri$next[7:0]$14552 \xive2_pri - assign $2\xive3_pri$next[7:0]$14553 \xive3_pri - assign $2\xive4_pri$next[7:0]$14554 \xive4_pri - assign $2\xive5_pri$next[7:0]$14555 \xive5_pri - assign $2\xive6_pri$next[7:0]$14556 \xive6_pri - assign $2\xive7_pri$next[7:0]$14557 \xive7_pri - assign $2\xive8_pri$next[7:0]$14558 \xive8_pri - assign $2\xive9_pri$next[7:0]$14559 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14528 \xive0_pri - assign $1\xive10_pri$next[7:0]$14529 \xive10_pri - assign $1\xive11_pri$next[7:0]$14530 \xive11_pri - assign $1\xive12_pri$next[7:0]$14531 \xive12_pri - assign $1\xive13_pri$next[7:0]$14532 \xive13_pri - assign $1\xive14_pri$next[7:0]$14533 \xive14_pri - assign $1\xive15_pri$next[7:0]$14534 \xive15_pri - assign $1\xive1_pri$next[7:0]$14535 \xive1_pri - assign $1\xive2_pri$next[7:0]$14536 \xive2_pri - assign $1\xive3_pri$next[7:0]$14537 \xive3_pri - assign $1\xive4_pri$next[7:0]$14538 \xive4_pri - assign $1\xive5_pri$next[7:0]$14539 \xive5_pri - assign $1\xive6_pri$next[7:0]$14540 \xive6_pri - assign $1\xive7_pri$next[7:0]$14541 \xive7_pri - assign $1\xive8_pri$next[7:0]$14542 \xive8_pri - assign $1\xive9_pri$next[7:0]$14543 \xive9_pri + assign $2\xive0_pri$next[7:0]$2480 \xive0_pri + assign $2\xive10_pri$next[7:0]$2481 \xive10_pri + assign $2\xive11_pri$next[7:0]$2482 \xive11_pri + assign $2\xive12_pri$next[7:0]$2483 \xive12_pri + assign $2\xive13_pri$next[7:0]$2484 \xive13_pri + assign $2\xive14_pri$next[7:0]$2485 \xive14_pri + assign $2\xive15_pri$next[7:0]$2486 \xive15_pri + assign $2\xive1_pri$next[7:0]$2487 \xive1_pri + assign $2\xive2_pri$next[7:0]$2488 \xive2_pri + assign $2\xive3_pri$next[7:0]$2489 \xive3_pri + assign $2\xive4_pri$next[7:0]$2490 \xive4_pri + assign $2\xive5_pri$next[7:0]$2491 \xive5_pri + assign $2\xive6_pri$next[7:0]$2492 \xive6_pri + assign $2\xive7_pri$next[7:0]$2493 \xive7_pri + assign $2\xive8_pri$next[7:0]$2494 \xive8_pri + assign $2\xive9_pri$next[7:0]$2495 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$2464 \xive0_pri + assign $1\xive10_pri$next[7:0]$2465 \xive10_pri + assign $1\xive11_pri$next[7:0]$2466 \xive11_pri + assign $1\xive12_pri$next[7:0]$2467 \xive12_pri + assign $1\xive13_pri$next[7:0]$2468 \xive13_pri + assign $1\xive14_pri$next[7:0]$2469 \xive14_pri + assign $1\xive15_pri$next[7:0]$2470 \xive15_pri + assign $1\xive1_pri$next[7:0]$2471 \xive1_pri + assign $1\xive2_pri$next[7:0]$2472 \xive2_pri + assign $1\xive3_pri$next[7:0]$2473 \xive3_pri + assign $1\xive4_pri$next[7:0]$2474 \xive4_pri + assign $1\xive5_pri$next[7:0]$2475 \xive5_pri + assign $1\xive6_pri$next[7:0]$2476 \xive6_pri + assign $1\xive7_pri$next[7:0]$2477 \xive7_pri + assign $1\xive8_pri$next[7:0]$2478 \xive8_pri + assign $1\xive9_pri$next[7:0]$2479 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -401410,66 +150373,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14576 8'11111111 - assign $4\xive1_pri$next[7:0]$14583 8'11111111 - assign $4\xive2_pri$next[7:0]$14584 8'11111111 - assign $4\xive3_pri$next[7:0]$14585 8'11111111 - assign $4\xive4_pri$next[7:0]$14586 8'11111111 - assign $4\xive5_pri$next[7:0]$14587 8'11111111 - assign $4\xive6_pri$next[7:0]$14588 8'11111111 - assign $4\xive7_pri$next[7:0]$14589 8'11111111 - assign $4\xive8_pri$next[7:0]$14590 8'11111111 - assign $4\xive9_pri$next[7:0]$14591 8'11111111 - assign $4\xive10_pri$next[7:0]$14577 8'11111111 - assign $4\xive11_pri$next[7:0]$14578 8'11111111 - assign $4\xive12_pri$next[7:0]$14579 8'11111111 - assign $4\xive13_pri$next[7:0]$14580 8'11111111 - assign $4\xive14_pri$next[7:0]$14581 8'11111111 - assign $4\xive15_pri$next[7:0]$14582 8'11111111 + assign $4\xive0_pri$next[7:0]$2512 8'11111111 + assign $4\xive1_pri$next[7:0]$2519 8'11111111 + assign $4\xive2_pri$next[7:0]$2520 8'11111111 + assign $4\xive3_pri$next[7:0]$2521 8'11111111 + assign $4\xive4_pri$next[7:0]$2522 8'11111111 + assign $4\xive5_pri$next[7:0]$2523 8'11111111 + assign $4\xive6_pri$next[7:0]$2524 8'11111111 + assign $4\xive7_pri$next[7:0]$2525 8'11111111 + assign $4\xive8_pri$next[7:0]$2526 8'11111111 + assign $4\xive9_pri$next[7:0]$2527 8'11111111 + assign $4\xive10_pri$next[7:0]$2513 8'11111111 + assign $4\xive11_pri$next[7:0]$2514 8'11111111 + assign $4\xive12_pri$next[7:0]$2515 8'11111111 + assign $4\xive13_pri$next[7:0]$2516 8'11111111 + assign $4\xive14_pri$next[7:0]$2517 8'11111111 + assign $4\xive15_pri$next[7:0]$2518 8'11111111 case - assign $4\xive0_pri$next[7:0]$14576 $1\xive0_pri$next[7:0]$14528 - assign $4\xive10_pri$next[7:0]$14577 $1\xive10_pri$next[7:0]$14529 - assign $4\xive11_pri$next[7:0]$14578 $1\xive11_pri$next[7:0]$14530 - assign $4\xive12_pri$next[7:0]$14579 $1\xive12_pri$next[7:0]$14531 - assign $4\xive13_pri$next[7:0]$14580 $1\xive13_pri$next[7:0]$14532 - assign $4\xive14_pri$next[7:0]$14581 $1\xive14_pri$next[7:0]$14533 - assign $4\xive15_pri$next[7:0]$14582 $1\xive15_pri$next[7:0]$14534 - assign $4\xive1_pri$next[7:0]$14583 $1\xive1_pri$next[7:0]$14535 - assign $4\xive2_pri$next[7:0]$14584 $1\xive2_pri$next[7:0]$14536 - assign $4\xive3_pri$next[7:0]$14585 $1\xive3_pri$next[7:0]$14537 - assign $4\xive4_pri$next[7:0]$14586 $1\xive4_pri$next[7:0]$14538 - assign $4\xive5_pri$next[7:0]$14587 $1\xive5_pri$next[7:0]$14539 - assign $4\xive6_pri$next[7:0]$14588 $1\xive6_pri$next[7:0]$14540 - assign $4\xive7_pri$next[7:0]$14589 $1\xive7_pri$next[7:0]$14541 - assign $4\xive8_pri$next[7:0]$14590 $1\xive8_pri$next[7:0]$14542 - assign $4\xive9_pri$next[7:0]$14591 $1\xive9_pri$next[7:0]$14543 + assign $4\xive0_pri$next[7:0]$2512 $1\xive0_pri$next[7:0]$2464 + assign $4\xive10_pri$next[7:0]$2513 $1\xive10_pri$next[7:0]$2465 + assign $4\xive11_pri$next[7:0]$2514 $1\xive11_pri$next[7:0]$2466 + assign $4\xive12_pri$next[7:0]$2515 $1\xive12_pri$next[7:0]$2467 + assign $4\xive13_pri$next[7:0]$2516 $1\xive13_pri$next[7:0]$2468 + assign $4\xive14_pri$next[7:0]$2517 $1\xive14_pri$next[7:0]$2469 + assign $4\xive15_pri$next[7:0]$2518 $1\xive15_pri$next[7:0]$2470 + assign $4\xive1_pri$next[7:0]$2519 $1\xive1_pri$next[7:0]$2471 + assign $4\xive2_pri$next[7:0]$2520 $1\xive2_pri$next[7:0]$2472 + assign $4\xive3_pri$next[7:0]$2521 $1\xive3_pri$next[7:0]$2473 + assign $4\xive4_pri$next[7:0]$2522 $1\xive4_pri$next[7:0]$2474 + assign $4\xive5_pri$next[7:0]$2523 $1\xive5_pri$next[7:0]$2475 + assign $4\xive6_pri$next[7:0]$2524 $1\xive6_pri$next[7:0]$2476 + assign $4\xive7_pri$next[7:0]$2525 $1\xive7_pri$next[7:0]$2477 + assign $4\xive8_pri$next[7:0]$2526 $1\xive8_pri$next[7:0]$2478 + assign $4\xive9_pri$next[7:0]$2527 $1\xive9_pri$next[7:0]$2479 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14512 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14513 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14514 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14515 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14516 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14517 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14518 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14519 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14520 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14521 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14522 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14523 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14524 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14525 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14526 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14527 + update \xive0_pri$next $0\xive0_pri$next[7:0]$2448 + update \xive10_pri$next $0\xive10_pri$next[7:0]$2449 + update \xive11_pri$next $0\xive11_pri$next[7:0]$2450 + update \xive12_pri$next $0\xive12_pri$next[7:0]$2451 + update \xive13_pri$next $0\xive13_pri$next[7:0]$2452 + update \xive14_pri$next $0\xive14_pri$next[7:0]$2453 + update \xive15_pri$next $0\xive15_pri$next[7:0]$2454 + update \xive1_pri$next $0\xive1_pri$next[7:0]$2455 + update \xive2_pri$next $0\xive2_pri$next[7:0]$2456 + update \xive3_pri$next $0\xive3_pri$next[7:0]$2457 + update \xive4_pri$next $0\xive4_pri$next[7:0]$2458 + update \xive5_pri$next $0\xive5_pri$next[7:0]$2459 + update \xive6_pri$next $0\xive6_pri$next[7:0]$2460 + update \xive7_pri$next $0\xive7_pri$next[7:0]$2461 + update \xive8_pri$next $0\xive8_pri$next[7:0]$2462 + update \xive9_pri$next $0\xive9_pri$next[7:0]$2463 end - attribute \src "libresoc.v:190040.3-190049.6" - process $proc$libresoc.v:190040$14592 + attribute \src "libresoc.v:53452.3-53461.6" + process $proc$libresoc.v:53452$2528 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:190041.5-190041.29" + attribute \src "libresoc.v:53453.5-53453.29" switch \initial - attribute \src "libresoc.v:190041.9-190041.17" + attribute \src "libresoc.v:53453.9-53453.17" case 1'1 case end @@ -401485,14 +150448,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:190050.3-190059.6" - process $proc$libresoc.v:190050$14593 + attribute \src "libresoc.v:53462.3-53471.6" + process $proc$libresoc.v:53462$2529 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:190051.5-190051.29" + attribute \src "libresoc.v:53463.5-53463.29" switch \initial - attribute \src "libresoc.v:190051.9-190051.17" + attribute \src "libresoc.v:53463.9-53463.17" case 1'1 case end @@ -401508,14 +150471,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:190060.3-190069.6" - process $proc$libresoc.v:190060$14594 + attribute \src "libresoc.v:53472.3-53481.6" + process $proc$libresoc.v:53472$2530 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:190061.5-190061.29" + attribute \src "libresoc.v:53473.5-53473.29" switch \initial - attribute \src "libresoc.v:190061.9-190061.17" + attribute \src "libresoc.v:53473.9-53473.17" case 1'1 case end @@ -401531,14 +150494,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:190070.3-190079.6" - process $proc$libresoc.v:190070$14595 + attribute \src "libresoc.v:53482.3-53491.6" + process $proc$libresoc.v:53482$2531 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:190071.5-190071.29" + attribute \src "libresoc.v:53483.5-53483.29" switch \initial - attribute \src "libresoc.v:190071.9-190071.17" + attribute \src "libresoc.v:53483.9-53483.17" case 1'1 case end @@ -401554,14 +150517,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:190080.3-190089.6" - process $proc$libresoc.v:190080$14596 + attribute \src "libresoc.v:53492.3-53501.6" + process $proc$libresoc.v:53492$2532 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:190081.5-190081.29" + attribute \src "libresoc.v:53493.5-53493.29" switch \initial - attribute \src "libresoc.v:190081.9-190081.17" + attribute \src "libresoc.v:53493.9-53493.17" case 1'1 case end @@ -401577,14 +150540,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:190090.3-190099.6" - process $proc$libresoc.v:190090$14597 + attribute \src "libresoc.v:53502.3-53511.6" + process $proc$libresoc.v:53502$2533 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:190091.5-190091.29" + attribute \src "libresoc.v:53503.5-53503.29" switch \initial - attribute \src "libresoc.v:190091.9-190091.17" + attribute \src "libresoc.v:53503.9-53503.17" case 1'1 case end @@ -401600,14 +150563,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:190100.3-190109.6" - process $proc$libresoc.v:190100$14598 + attribute \src "libresoc.v:53512.3-53521.6" + process $proc$libresoc.v:53512$2534 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:190101.5-190101.29" + attribute \src "libresoc.v:53513.5-53513.29" switch \initial - attribute \src "libresoc.v:190101.9-190101.17" + attribute \src "libresoc.v:53513.9-53513.17" case 1'1 case end @@ -401623,14 +150586,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:190110.3-190119.6" - process $proc$libresoc.v:190110$14599 + attribute \src "libresoc.v:53522.3-53531.6" + process $proc$libresoc.v:53522$2535 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:190111.5-190111.29" + attribute \src "libresoc.v:53523.5-53523.29" switch \initial - attribute \src "libresoc.v:190111.9-190111.17" + attribute \src "libresoc.v:53523.9-53523.17" case 1'1 case end @@ -401646,14 +150609,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:190120.3-190129.6" - process $proc$libresoc.v:190120$14600 + attribute \src "libresoc.v:53532.3-53541.6" + process $proc$libresoc.v:53532$2536 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:190121.5-190121.29" + attribute \src "libresoc.v:53533.5-53533.29" switch \initial - attribute \src "libresoc.v:190121.9-190121.17" + attribute \src "libresoc.v:53533.9-53533.17" case 1'1 case end @@ -401669,14 +150632,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:190130.3-190138.6" - process $proc$libresoc.v:190130$14601 + attribute \src "libresoc.v:53542.3-53550.6" + process $proc$libresoc.v:53542$2537 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14602 $1\int_level_l$next[15:0]$14603 - attribute \src "libresoc.v:190131.5-190131.29" + assign $0\int_level_l$next[15:0]$2538 $1\int_level_l$next[15:0]$2539 + attribute \src "libresoc.v:53543.5-53543.29" switch \initial - attribute \src "libresoc.v:190131.9-190131.17" + attribute \src "libresoc.v:53543.9-53543.17" case 1'1 case end @@ -401685,21 +150648,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14603 16'0000000000000000 + assign $1\int_level_l$next[15:0]$2539 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14603 \int_level_i + assign $1\int_level_l$next[15:0]$2539 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14602 + update \int_level_l$next $0\int_level_l$next[15:0]$2538 end - attribute \src "libresoc.v:190139.3-190148.6" - process $proc$libresoc.v:190139$14604 + attribute \src "libresoc.v:53551.3-53560.6" + process $proc$libresoc.v:53551$2540 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:190140.5-190140.29" + attribute \src "libresoc.v:53552.5-53552.29" switch \initial - attribute \src "libresoc.v:190140.9-190140.17" + attribute \src "libresoc.v:53552.9-53552.17" case 1'1 case end @@ -401715,14 +150678,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:190149.3-190158.6" - process $proc$libresoc.v:190149$14605 + attribute \src "libresoc.v:53561.3-53570.6" + process $proc$libresoc.v:53561$2541 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:190150.5-190150.29" + attribute \src "libresoc.v:53562.5-53562.29" switch \initial - attribute \src "libresoc.v:190150.9-190150.17" + attribute \src "libresoc.v:53562.9-53562.17" case 1'1 case end @@ -401738,14 +150701,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:190159.3-190168.6" - process $proc$libresoc.v:190159$14606 + attribute \src "libresoc.v:53571.3-53580.6" + process $proc$libresoc.v:53571$2542 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:190160.5-190160.29" + attribute \src "libresoc.v:53572.5-53572.29" switch \initial - attribute \src "libresoc.v:190160.9-190160.17" + attribute \src "libresoc.v:53572.9-53572.17" case 1'1 case end @@ -401761,14 +150724,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:190169.3-190178.6" - process $proc$libresoc.v:190169$14607 + attribute \src "libresoc.v:53581.3-53590.6" + process $proc$libresoc.v:53581$2543 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:190170.5-190170.29" + attribute \src "libresoc.v:53582.5-53582.29" switch \initial - attribute \src "libresoc.v:190170.9-190170.17" + attribute \src "libresoc.v:53582.9-53582.17" case 1'1 case end @@ -401784,14 +150747,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:190179.3-190188.6" - process $proc$libresoc.v:190179$14608 + attribute \src "libresoc.v:53591.3-53600.6" + process $proc$libresoc.v:53591$2544 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:190180.5-190180.29" + attribute \src "libresoc.v:53592.5-53592.29" switch \initial - attribute \src "libresoc.v:190180.9-190180.17" + attribute \src "libresoc.v:53592.9-53592.17" case 1'1 case end @@ -401807,14 +150770,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:190189.3-190198.6" - process $proc$libresoc.v:190189$14609 + attribute \src "libresoc.v:53601.3-53610.6" + process $proc$libresoc.v:53601$2545 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:190190.5-190190.29" + attribute \src "libresoc.v:53602.5-53602.29" switch \initial - attribute \src "libresoc.v:190190.9-190190.17" + attribute \src "libresoc.v:53602.9-53602.17" case 1'1 case end @@ -401830,14 +150793,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:190199.3-190208.6" - process $proc$libresoc.v:190199$14610 + attribute \src "libresoc.v:53611.3-53620.6" + process $proc$libresoc.v:53611$2546 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:190200.5-190200.29" + attribute \src "libresoc.v:53612.5-53612.29" switch \initial - attribute \src "libresoc.v:190200.9-190200.17" + attribute \src "libresoc.v:53612.9-53612.17" case 1'1 case end @@ -401853,14 +150816,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:190209.3-190218.6" - process $proc$libresoc.v:190209$14611 + attribute \src "libresoc.v:53621.3-53630.6" + process $proc$libresoc.v:53621$2547 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:190210.5-190210.29" + attribute \src "libresoc.v:53622.5-53622.29" switch \initial - attribute \src "libresoc.v:190210.9-190210.17" + attribute \src "libresoc.v:53622.9-53622.17" case 1'1 case end @@ -401876,14 +150839,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:190219.3-190228.6" - process $proc$libresoc.v:190219$14612 + attribute \src "libresoc.v:53631.3-53640.6" + process $proc$libresoc.v:53631$2548 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:190220.5-190220.29" + attribute \src "libresoc.v:53632.5-53632.29" switch \initial - attribute \src "libresoc.v:190220.9-190220.17" + attribute \src "libresoc.v:53632.9-53632.17" case 1'1 case end @@ -401899,14 +150862,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:190229.3-190238.6" - process $proc$libresoc.v:190229$14613 + attribute \src "libresoc.v:53641.3-53650.6" + process $proc$libresoc.v:53641$2549 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:190230.5-190230.29" + attribute \src "libresoc.v:53642.5-53642.29" switch \initial - attribute \src "libresoc.v:190230.9-190230.17" + attribute \src "libresoc.v:53642.9-53642.17" case 1'1 case end @@ -401922,14 +150885,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:190239.3-190248.6" - process $proc$libresoc.v:190239$14614 + attribute \src "libresoc.v:53651.3-53660.6" + process $proc$libresoc.v:53651$2550 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:190240.5-190240.29" + attribute \src "libresoc.v:53652.5-53652.29" switch \initial - attribute \src "libresoc.v:190240.9-190240.17" + attribute \src "libresoc.v:53652.9-53652.17" case 1'1 case end @@ -401945,14 +150908,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:190249.3-190258.6" - process $proc$libresoc.v:190249$14615 + attribute \src "libresoc.v:53661.3-53670.6" + process $proc$libresoc.v:53661$2551 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:190250.5-190250.29" + attribute \src "libresoc.v:53662.5-53662.29" switch \initial - attribute \src "libresoc.v:190250.9-190250.17" + attribute \src "libresoc.v:53662.9-53662.17" case 1'1 case end @@ -401968,14 +150931,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:190259.3-190268.6" - process $proc$libresoc.v:190259$14616 + attribute \src "libresoc.v:53671.3-53680.6" + process $proc$libresoc.v:53671$2552 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:190260.5-190260.29" + attribute \src "libresoc.v:53672.5-53672.29" switch \initial - attribute \src "libresoc.v:190260.9-190260.17" + attribute \src "libresoc.v:53672.9-53672.17" case 1'1 case end @@ -401991,14 +150954,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:190269.3-190278.6" - process $proc$libresoc.v:190269$14617 + attribute \src "libresoc.v:53681.3-53690.6" + process $proc$libresoc.v:53681$2553 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:190270.5-190270.29" + attribute \src "libresoc.v:53682.5-53682.29" switch \initial - attribute \src "libresoc.v:190270.9-190270.17" + attribute \src "libresoc.v:53682.9-53682.17" case 1'1 case end @@ -402014,14 +150977,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:190279.3-190288.6" - process $proc$libresoc.v:190279$14618 + attribute \src "libresoc.v:53691.3-53700.6" + process $proc$libresoc.v:53691$2554 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:190280.5-190280.29" + attribute \src "libresoc.v:53692.5-53692.29" switch \initial - attribute \src "libresoc.v:190280.9-190280.17" + attribute \src "libresoc.v:53692.9-53692.17" case 1'1 case end @@ -402037,14 +151000,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:190289.3-190298.6" - process $proc$libresoc.v:190289$14619 + attribute \src "libresoc.v:53701.3-53710.6" + process $proc$libresoc.v:53701$2555 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:190290.5-190290.29" + attribute \src "libresoc.v:53702.5-53702.29" switch \initial - attribute \src "libresoc.v:190290.9-190290.17" + attribute \src "libresoc.v:53702.9-53702.17" case 1'1 case end @@ -402060,14 +151023,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:190299.3-190308.6" - process $proc$libresoc.v:190299$14620 + attribute \src "libresoc.v:53711.3-53720.6" + process $proc$libresoc.v:53711$2556 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:190300.5-190300.29" + attribute \src "libresoc.v:53712.5-53712.29" switch \initial - attribute \src "libresoc.v:190300.9-190300.17" + attribute \src "libresoc.v:53712.9-53712.17" case 1'1 case end @@ -402083,14 +151046,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:190309.3-190318.6" - process $proc$libresoc.v:190309$14621 + attribute \src "libresoc.v:53721.3-53730.6" + process $proc$libresoc.v:53721$2557 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:190310.5-190310.29" + attribute \src "libresoc.v:53722.5-53722.29" switch \initial - attribute \src "libresoc.v:190310.9-190310.17" + attribute \src "libresoc.v:53722.9-53722.17" case 1'1 case end @@ -402106,14 +151069,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:190319.3-190328.6" - process $proc$libresoc.v:190319$14622 + attribute \src "libresoc.v:53731.3-53740.6" + process $proc$libresoc.v:53731$2558 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:190320.5-190320.29" + attribute \src "libresoc.v:53732.5-53732.29" switch \initial - attribute \src "libresoc.v:190320.9-190320.17" + attribute \src "libresoc.v:53732.9-53732.17" case 1'1 case end @@ -402129,14 +151092,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:190329.3-190338.6" - process $proc$libresoc.v:190329$14623 + attribute \src "libresoc.v:53741.3-53750.6" + process $proc$libresoc.v:53741$2559 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:190330.5-190330.29" + attribute \src "libresoc.v:53742.5-53742.29" switch \initial - attribute \src "libresoc.v:190330.9-190330.17" + attribute \src "libresoc.v:53742.9-53742.17" case 1'1 case end @@ -402152,14 +151115,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:190339.3-190388.6" - process $proc$libresoc.v:190339$14624 + attribute \src "libresoc.v:53751.3-53800.6" + process $proc$libresoc.v:53751$2560 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:190340.5-190340.29" + attribute \src "libresoc.v:53752.5-53752.29" switch \initial - attribute \src "libresoc.v:190340.9-190340.17" + attribute \src "libresoc.v:53752.9-53752.17" case 1'1 case end @@ -402252,14 +151215,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:190389.3-190398.6" - process $proc$libresoc.v:190389$14625 + attribute \src "libresoc.v:53801.3-53810.6" + process $proc$libresoc.v:53801$2561 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:190390.5-190390.29" + attribute \src "libresoc.v:53802.5-53802.29" switch \initial - attribute \src "libresoc.v:190390.9-190390.17" + attribute \src "libresoc.v:53802.9-53802.17" case 1'1 case end @@ -402275,14 +151238,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:190399.3-190408.6" - process $proc$libresoc.v:190399$14626 + attribute \src "libresoc.v:53811.3-53820.6" + process $proc$libresoc.v:53811$2562 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:190400.5-190400.29" + attribute \src "libresoc.v:53812.5-53812.29" switch \initial - attribute \src "libresoc.v:190400.9-190400.17" + attribute \src "libresoc.v:53812.9-53812.17" case 1'1 case end @@ -402298,14 +151261,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:190409.3-190418.6" - process $proc$libresoc.v:190409$14627 + attribute \src "libresoc.v:53821.3-53830.6" + process $proc$libresoc.v:53821$2563 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:190410.5-190410.29" + attribute \src "libresoc.v:53822.5-53822.29" switch \initial - attribute \src "libresoc.v:190410.9-190410.17" + attribute \src "libresoc.v:53822.9-53822.17" case 1'1 case end @@ -402321,14 +151284,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:190419.3-190428.6" - process $proc$libresoc.v:190419$14628 + attribute \src "libresoc.v:53831.3-53840.6" + process $proc$libresoc.v:53831$2564 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:190420.5-190420.29" + attribute \src "libresoc.v:53832.5-53832.29" switch \initial - attribute \src "libresoc.v:190420.9-190420.17" + attribute \src "libresoc.v:53832.9-53832.17" case 1'1 case end @@ -402344,14 +151307,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:190429.3-190437.6" - process $proc$libresoc.v:190429$14629 + attribute \src "libresoc.v:53841.3-53849.6" + process $proc$libresoc.v:53841$2565 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$14630 $1\ics_wb__dat_r$next[31:0]$14631 - attribute \src "libresoc.v:190430.5-190430.29" + assign $0\ics_wb__dat_r$next[31:0]$2566 $1\ics_wb__dat_r$next[31:0]$2567 + attribute \src "libresoc.v:53842.5-53842.29" switch \initial - attribute \src "libresoc.v:190430.9-190430.17" + attribute \src "libresoc.v:53842.9-53842.17" case 1'1 case end @@ -402360,21 +151323,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$14631 0 + assign $1\ics_wb__dat_r$next[31:0]$2567 0 case - assign $1\ics_wb__dat_r$next[31:0]$14631 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$2567 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$14630 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2566 end - attribute \src "libresoc.v:190438.3-190446.6" - process $proc$libresoc.v:190438$14632 + attribute \src "libresoc.v:53850.3-53858.6" + process $proc$libresoc.v:53850$2568 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$14633 $1\ics_wb__ack$next[0:0]$14634 - attribute \src "libresoc.v:190439.5-190439.29" + assign $0\ics_wb__ack$next[0:0]$2569 $1\ics_wb__ack$next[0:0]$2570 + attribute \src "libresoc.v:53851.5-53851.29" switch \initial - attribute \src "libresoc.v:190439.9-190439.17" + attribute \src "libresoc.v:53851.9-53851.17" case 1'1 case end @@ -402383,116 +151346,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$14634 1'0 - case - assign $1\ics_wb__ack$next[0:0]$14634 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$14633 - end - connect \$7 $ternary$libresoc.v:189809$14387_Y - connect \$99 $lt$libresoc.v:189810$14388_Y - connect \$101 $and$libresoc.v:189811$14389_Y - connect \$103 $lt$libresoc.v:189812$14390_Y - connect \$105 $and$libresoc.v:189813$14391_Y - connect \$107 $lt$libresoc.v:189814$14392_Y - connect \$109 $and$libresoc.v:189815$14393_Y - connect \$111 $lt$libresoc.v:189816$14394_Y - connect \$113 $and$libresoc.v:189817$14395_Y - connect \$115 $lt$libresoc.v:189818$14396_Y - connect \$117 $and$libresoc.v:189819$14397_Y - connect \$119 $lt$libresoc.v:189820$14398_Y - connect \$121 $and$libresoc.v:189821$14399_Y - connect \$123 $lt$libresoc.v:189822$14400_Y - connect \$125 $and$libresoc.v:189823$14401_Y - connect \$127 $lt$libresoc.v:189824$14402_Y - connect \$12 $eq$libresoc.v:189825$14403_Y - connect \$129 $and$libresoc.v:189826$14404_Y - connect \$131 $lt$libresoc.v:189827$14405_Y - connect \$133 $and$libresoc.v:189828$14406_Y - connect \$135 $lt$libresoc.v:189829$14407_Y - connect \$137 $and$libresoc.v:189830$14408_Y - connect \$11 $ternary$libresoc.v:189831$14409_Y - connect \$139 $lt$libresoc.v:189832$14410_Y - connect \$141 $and$libresoc.v:189833$14411_Y - connect \$143 $lt$libresoc.v:189834$14412_Y - connect \$145 $and$libresoc.v:189835$14413_Y - connect \$147 $lt$libresoc.v:189836$14414_Y - connect \$149 $and$libresoc.v:189837$14415_Y - connect \$151 $lt$libresoc.v:189838$14416_Y - connect \$153 $and$libresoc.v:189839$14417_Y - connect \$155 $lt$libresoc.v:189840$14418_Y - connect \$157 $and$libresoc.v:189841$14419_Y - connect \$159 $lt$libresoc.v:189842$14420_Y - connect \$161 $and$libresoc.v:189843$14421_Y - connect \$163 $lt$libresoc.v:189844$14422_Y - connect \$165 $and$libresoc.v:189845$14423_Y - connect \$167 $lt$libresoc.v:189846$14424_Y - connect \$16 $eq$libresoc.v:189847$14425_Y - connect \$169 $and$libresoc.v:189848$14426_Y - connect \$171 $lt$libresoc.v:189849$14427_Y - connect \$173 $and$libresoc.v:189850$14428_Y - connect \$175 $lt$libresoc.v:189851$14429_Y - connect \$177 $and$libresoc.v:189852$14430_Y - connect \$15 $ternary$libresoc.v:189853$14431_Y - connect \$179 $lt$libresoc.v:189854$14432_Y - connect \$181 $and$libresoc.v:189855$14433_Y - connect \$183 $lt$libresoc.v:189856$14434_Y - connect \$185 $and$libresoc.v:189857$14435_Y - connect \$187 $lt$libresoc.v:189858$14436_Y - connect \$189 $and$libresoc.v:189859$14437_Y - connect \$191 $lt$libresoc.v:189860$14438_Y - connect \$193 $and$libresoc.v:189861$14439_Y - connect \$195 $lt$libresoc.v:189862$14440_Y - connect \$197 $and$libresoc.v:189863$14441_Y - connect \$1 $eq$libresoc.v:189864$14442_Y - connect \$199 $lt$libresoc.v:189865$14443_Y - connect \$201 $and$libresoc.v:189866$14444_Y - connect \$204 $eq$libresoc.v:189867$14445_Y - connect \$203 $ternary$libresoc.v:189868$14446_Y - connect \$20 $eq$libresoc.v:189869$14447_Y - connect \$19 $ternary$libresoc.v:189870$14448_Y - connect \$24 $eq$libresoc.v:189871$14449_Y - connect \$23 $ternary$libresoc.v:189872$14450_Y - connect \$28 $eq$libresoc.v:189873$14451_Y - connect \$27 $ternary$libresoc.v:189874$14452_Y - connect \$32 $eq$libresoc.v:189875$14453_Y - connect \$31 $ternary$libresoc.v:189876$14454_Y - connect \$36 $eq$libresoc.v:189877$14455_Y - connect \$35 $ternary$libresoc.v:189878$14456_Y - connect \$3 $eq$libresoc.v:189879$14457_Y - connect \$40 $eq$libresoc.v:189880$14458_Y - connect \$39 $ternary$libresoc.v:189881$14459_Y - connect \$44 $eq$libresoc.v:189882$14460_Y - connect \$43 $ternary$libresoc.v:189883$14461_Y - connect \$48 $eq$libresoc.v:189884$14462_Y - connect \$47 $ternary$libresoc.v:189885$14463_Y - connect \$52 $eq$libresoc.v:189886$14464_Y - connect \$51 $ternary$libresoc.v:189887$14465_Y - connect \$56 $eq$libresoc.v:189888$14466_Y - connect \$55 $ternary$libresoc.v:189889$14467_Y - connect \$5 $and$libresoc.v:189890$14468_Y - connect \$60 $eq$libresoc.v:189891$14469_Y - connect \$59 $ternary$libresoc.v:189892$14470_Y - connect \$64 $eq$libresoc.v:189893$14471_Y - connect \$63 $ternary$libresoc.v:189894$14472_Y - connect \$68 $eq$libresoc.v:189895$14473_Y - connect \$67 $ternary$libresoc.v:189896$14474_Y - connect \$71 $shr$libresoc.v:189897$14475_Y [0] - connect \$73 $and$libresoc.v:189898$14476_Y - connect \$75 $lt$libresoc.v:189899$14477_Y - connect \$77 $and$libresoc.v:189900$14478_Y - connect \$79 $lt$libresoc.v:189901$14479_Y - connect \$81 $and$libresoc.v:189902$14480_Y - connect \$83 $lt$libresoc.v:189903$14481_Y - connect \$85 $and$libresoc.v:189904$14482_Y - connect \$87 $lt$libresoc.v:189905$14483_Y - connect \$8 $eq$libresoc.v:189906$14484_Y - connect \$89 $and$libresoc.v:189907$14485_Y - connect \$91 $lt$libresoc.v:189908$14486_Y - connect \$93 $and$libresoc.v:189909$14487_Y - connect \$95 $lt$libresoc.v:189910$14488_Y - connect \$97 $and$libresoc.v:189911$14489_Y + assign $1\ics_wb__ack$next[0:0]$2570 1'0 + case + assign $1\ics_wb__ack$next[0:0]$2570 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2569 + end + connect \$7 $ternary$libresoc.v:53221$2323_Y + connect \$99 $lt$libresoc.v:53222$2324_Y + connect \$101 $and$libresoc.v:53223$2325_Y + connect \$103 $lt$libresoc.v:53224$2326_Y + connect \$105 $and$libresoc.v:53225$2327_Y + connect \$107 $lt$libresoc.v:53226$2328_Y + connect \$109 $and$libresoc.v:53227$2329_Y + connect \$111 $lt$libresoc.v:53228$2330_Y + connect \$113 $and$libresoc.v:53229$2331_Y + connect \$115 $lt$libresoc.v:53230$2332_Y + connect \$117 $and$libresoc.v:53231$2333_Y + connect \$119 $lt$libresoc.v:53232$2334_Y + connect \$121 $and$libresoc.v:53233$2335_Y + connect \$123 $lt$libresoc.v:53234$2336_Y + connect \$125 $and$libresoc.v:53235$2337_Y + connect \$127 $lt$libresoc.v:53236$2338_Y + connect \$12 $eq$libresoc.v:53237$2339_Y + connect \$129 $and$libresoc.v:53238$2340_Y + connect \$131 $lt$libresoc.v:53239$2341_Y + connect \$133 $and$libresoc.v:53240$2342_Y + connect \$135 $lt$libresoc.v:53241$2343_Y + connect \$137 $and$libresoc.v:53242$2344_Y + connect \$11 $ternary$libresoc.v:53243$2345_Y + connect \$139 $lt$libresoc.v:53244$2346_Y + connect \$141 $and$libresoc.v:53245$2347_Y + connect \$143 $lt$libresoc.v:53246$2348_Y + connect \$145 $and$libresoc.v:53247$2349_Y + connect \$147 $lt$libresoc.v:53248$2350_Y + connect \$149 $and$libresoc.v:53249$2351_Y + connect \$151 $lt$libresoc.v:53250$2352_Y + connect \$153 $and$libresoc.v:53251$2353_Y + connect \$155 $lt$libresoc.v:53252$2354_Y + connect \$157 $and$libresoc.v:53253$2355_Y + connect \$159 $lt$libresoc.v:53254$2356_Y + connect \$161 $and$libresoc.v:53255$2357_Y + connect \$163 $lt$libresoc.v:53256$2358_Y + connect \$165 $and$libresoc.v:53257$2359_Y + connect \$167 $lt$libresoc.v:53258$2360_Y + connect \$16 $eq$libresoc.v:53259$2361_Y + connect \$169 $and$libresoc.v:53260$2362_Y + connect \$171 $lt$libresoc.v:53261$2363_Y + connect \$173 $and$libresoc.v:53262$2364_Y + connect \$175 $lt$libresoc.v:53263$2365_Y + connect \$177 $and$libresoc.v:53264$2366_Y + connect \$15 $ternary$libresoc.v:53265$2367_Y + connect \$179 $lt$libresoc.v:53266$2368_Y + connect \$181 $and$libresoc.v:53267$2369_Y + connect \$183 $lt$libresoc.v:53268$2370_Y + connect \$185 $and$libresoc.v:53269$2371_Y + connect \$187 $lt$libresoc.v:53270$2372_Y + connect \$189 $and$libresoc.v:53271$2373_Y + connect \$191 $lt$libresoc.v:53272$2374_Y + connect \$193 $and$libresoc.v:53273$2375_Y + connect \$195 $lt$libresoc.v:53274$2376_Y + connect \$197 $and$libresoc.v:53275$2377_Y + connect \$1 $eq$libresoc.v:53276$2378_Y + connect \$199 $lt$libresoc.v:53277$2379_Y + connect \$201 $and$libresoc.v:53278$2380_Y + connect \$204 $eq$libresoc.v:53279$2381_Y + connect \$203 $ternary$libresoc.v:53280$2382_Y + connect \$20 $eq$libresoc.v:53281$2383_Y + connect \$19 $ternary$libresoc.v:53282$2384_Y + connect \$24 $eq$libresoc.v:53283$2385_Y + connect \$23 $ternary$libresoc.v:53284$2386_Y + connect \$28 $eq$libresoc.v:53285$2387_Y + connect \$27 $ternary$libresoc.v:53286$2388_Y + connect \$32 $eq$libresoc.v:53287$2389_Y + connect \$31 $ternary$libresoc.v:53288$2390_Y + connect \$36 $eq$libresoc.v:53289$2391_Y + connect \$35 $ternary$libresoc.v:53290$2392_Y + connect \$3 $eq$libresoc.v:53291$2393_Y + connect \$40 $eq$libresoc.v:53292$2394_Y + connect \$39 $ternary$libresoc.v:53293$2395_Y + connect \$44 $eq$libresoc.v:53294$2396_Y + connect \$43 $ternary$libresoc.v:53295$2397_Y + connect \$48 $eq$libresoc.v:53296$2398_Y + connect \$47 $ternary$libresoc.v:53297$2399_Y + connect \$52 $eq$libresoc.v:53298$2400_Y + connect \$51 $ternary$libresoc.v:53299$2401_Y + connect \$56 $eq$libresoc.v:53300$2402_Y + connect \$55 $ternary$libresoc.v:53301$2403_Y + connect \$5 $and$libresoc.v:53302$2404_Y + connect \$60 $eq$libresoc.v:53303$2405_Y + connect \$59 $ternary$libresoc.v:53304$2406_Y + connect \$64 $eq$libresoc.v:53305$2407_Y + connect \$63 $ternary$libresoc.v:53306$2408_Y + connect \$68 $eq$libresoc.v:53307$2409_Y + connect \$67 $ternary$libresoc.v:53308$2410_Y + connect \$71 $shr$libresoc.v:53309$2411_Y [0] + connect \$73 $and$libresoc.v:53310$2412_Y + connect \$75 $lt$libresoc.v:53311$2413_Y + connect \$77 $and$libresoc.v:53312$2414_Y + connect \$79 $lt$libresoc.v:53313$2415_Y + connect \$81 $and$libresoc.v:53314$2416_Y + connect \$83 $lt$libresoc.v:53315$2417_Y + connect \$85 $and$libresoc.v:53316$2418_Y + connect \$87 $lt$libresoc.v:53317$2419_Y + connect \$8 $eq$libresoc.v:53318$2420_Y + connect \$89 $and$libresoc.v:53319$2421_Y + connect \$91 $lt$libresoc.v:53320$2422_Y + connect \$93 $and$libresoc.v:53321$2423_Y + connect \$95 $lt$libresoc.v:53322$2424_Y + connect \$97 $and$libresoc.v:53323$2425_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 -- 2.30.2